* [dpdk-dev] [PATCH 01/14] net/bnxt: tf core index table updates
2021-09-01 14:24 [dpdk-dev] [PATCH 00/14] enhancements to host based flow table management Venkat Duvvuru
@ 2021-09-01 14:24 ` Venkat Duvvuru
2021-09-01 14:24 ` [dpdk-dev] [PATCH 02/14] net/bnxt: enable dpool allocator Venkat Duvvuru
` (13 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-01 14:24 UTC (permalink / raw)
To: dev; +Cc: Farah Smith
From: Farah Smith <farah.smith@broadcom.com>
Remove unused shadow table functionality.
Signed-off-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Peter Spreadborough <peter.spreadborough@broadcom.com>
---
drivers/net/bnxt/tf_core/tf_core.c | 65 --------------
drivers/net/bnxt/tf_core/tf_core.h | 103 +----------------------
drivers/net/bnxt/tf_core/tf_device.h | 22 -----
drivers/net/bnxt/tf_core/tf_device_p4.c | 2 -
drivers/net/bnxt/tf_core/tf_device_p58.c | 2 -
drivers/net/bnxt/tf_core/tf_em_common.c | 4 +
drivers/net/bnxt/tf_core/tf_tbl.c | 21 -----
drivers/net/bnxt/tf_core/tf_tbl.h | 72 ----------------
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 3 +-
9 files changed, 7 insertions(+), 287 deletions(-)
diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c
index 97e6165e92..5458f76e2d 100644
--- a/drivers/net/bnxt/tf_core/tf_core.c
+++ b/drivers/net/bnxt/tf_core/tf_core.c
@@ -1105,71 +1105,6 @@ tf_alloc_tbl_entry(struct tf *tfp,
return 0;
}
-int
-tf_search_tbl_entry(struct tf *tfp,
- struct tf_search_tbl_entry_parms *parms)
-{
- int rc;
- struct tf_session *tfs;
- struct tf_dev_info *dev;
- struct tf_tbl_alloc_search_parms sparms;
-
- TF_CHECK_PARMS2(tfp, parms);
-
- /* Retrieve the session information */
- rc = tf_session_get_session(tfp, &tfs);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed to lookup session, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(-rc));
- return rc;
- }
-
- /* Retrieve the device information */
- rc = tf_session_get_device(tfs, &dev);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed to lookup device, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(-rc));
- return rc;
- }
-
- if (dev->ops->tf_dev_alloc_search_tbl == NULL) {
- rc = -EOPNOTSUPP;
- TFP_DRV_LOG(ERR,
- "%s: Operation not supported, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(-rc));
- return rc;
- }
-
- memset(&sparms, 0, sizeof(struct tf_tbl_alloc_search_parms));
- sparms.dir = parms->dir;
- sparms.type = parms->type;
- sparms.result = parms->result;
- sparms.result_sz_in_bytes = parms->result_sz_in_bytes;
- sparms.alloc = parms->alloc;
- sparms.tbl_scope_id = parms->tbl_scope_id;
- rc = dev->ops->tf_dev_alloc_search_tbl(tfp, &sparms);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: TBL allocation failed, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(-rc));
- return rc;
- }
-
- /* Return the outputs from the search */
- parms->hit = sparms.hit;
- parms->search_status = sparms.search_status;
- parms->ref_cnt = sparms.ref_cnt;
- parms->idx = sparms.idx;
-
- return 0;
-}
-
int
tf_free_tbl_entry(struct tf *tfp,
struct tf_free_tbl_entry_parms *parms)
diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h
index 84b234f0e3..7e0cdf7e0d 100644
--- a/drivers/net/bnxt/tf_core/tf_core.h
+++ b/drivers/net/bnxt/tf_core/tf_core.h
@@ -1622,79 +1622,6 @@ int tf_clear_tcam_shared_entries(struct tf *tfp,
* @ref tf_get_shared_tbl_increment
*/
-/**
- * tf_alloc_tbl_entry parameter definition
- */
-struct tf_search_tbl_entry_parms {
- /**
- * [in] Receive or transmit direction
- */
- enum tf_dir dir;
- /**
- * [in] Type of the allocation
- */
- enum tf_tbl_type type;
- /**
- * [in] Table scope identifier (ignored unless TF_TBL_TYPE_EXT)
- */
- uint32_t tbl_scope_id;
- /**
- * [in] Result data to search for
- */
- uint8_t *result;
- /**
- * [in] Result data size in bytes
- */
- uint16_t result_sz_in_bytes;
- /**
- * [in] Allocate on miss.
- */
- uint8_t alloc;
- /**
- * [out] Set if matching entry found
- */
- uint8_t hit;
- /**
- * [out] Search result status (hit, miss, reject)
- */
- enum tf_search_status search_status;
- /**
- * [out] Current ref count after allocation
- */
- uint16_t ref_cnt;
- /**
- * [out] Idx of allocated entry or found entry
- */
- uint32_t idx;
-};
-
-/**
- * search Table Entry (experimental)
- *
- * This function searches the shadow copy of an index table for a matching
- * entry. The result data must match for hit to be set. Only TruFlow core
- * data is accessed. If shadow_copy is not enabled, an error is returned.
- *
- * Implementation:
- *
- * A hash is performed on the result data and mapped to a shadow copy entry
- * where the result is populated. If the result matches the entry, hit is set,
- * ref_cnt is incremented (if alloc), and the search status indicates what
- * action the caller can take regarding setting the entry.
- *
- * search status should be used as follows:
- * - On MISS, the caller should set the result into the returned index.
- *
- * - On REJECT, the caller should reject the flow since there are no resources.
- *
- * - On Hit, the matching index is returned to the caller. Additionally, the
- * ref_cnt is updated.
- *
- * Also returns success or failure code.
- */
-int tf_search_tbl_entry(struct tf *tfp,
- struct tf_search_tbl_entry_parms *parms);
-
/**
* tf_alloc_tbl_entry parameter definition
*/
@@ -1711,30 +1638,9 @@ struct tf_alloc_tbl_entry_parms {
* [in] Table scope identifier (ignored unless TF_TBL_TYPE_EXT)
*/
uint32_t tbl_scope_id;
+
/**
- * [in] Enable search for matching entry. If the table type is
- * internal the shadow copy will be searched before
- * alloc. Session must be configured with shadow copy enabled.
- */
- uint8_t search_enable;
- /**
- * [in] Result data to search for (if search_enable)
- */
- uint8_t *result;
- /**
- * [in] Result data size in bytes (if search_enable)
- */
- uint16_t result_sz_in_bytes;
- /**
- * [out] If search_enable, set if matching entry found
- */
- uint8_t hit;
- /**
- * [out] Current ref count after allocation (if search_enable)
- */
- uint16_t ref_cnt;
- /**
- * [out] Idx of allocated entry or found entry (if search_enable)
+ * [out] Idx of allocated entry
*/
uint32_t idx;
};
@@ -1790,11 +1696,6 @@ struct tf_free_tbl_entry_parms {
* [in] Index to free
*/
uint32_t idx;
- /**
- * [out] Reference count after free, only valid if session has been
- * created with shadow_copy.
- */
- uint16_t ref_cnt;
};
/**
diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h
index da3f541685..b43cfc6925 100644
--- a/drivers/net/bnxt/tf_core/tf_device.h
+++ b/drivers/net/bnxt/tf_core/tf_device.h
@@ -347,28 +347,6 @@ struct tf_dev_ops {
int (*tf_dev_free_ext_tbl)(struct tf *tfp,
struct tf_tbl_free_parms *parms);
- /**
- * Searches for the specified table type element in a shadow DB.
- *
- * This API searches for the specified table type element in a
- * device specific shadow DB. If the element is found the
- * reference count for the element is updated. If the element
- * is not found a new element is allocated from the table type
- * DB and then inserted into the shadow DB.
- *
- * [in] tfp
- * Pointer to TF handle
- *
- * [in] parms
- * Pointer to table allocation and search parameters
- *
- * Returns
- * - (0) if successful.
- * - (-EINVAL) on failure.
- */
- int (*tf_dev_alloc_search_tbl)(struct tf *tfp,
- struct tf_tbl_alloc_search_parms *parms);
-
/**
* Sets the specified table type element.
*
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c
index 971fab7bda..2e7ccec123 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.c
@@ -236,7 +236,6 @@ const struct tf_dev_ops tf_dev_ops_p4_init = {
.tf_dev_alloc_tbl = NULL,
.tf_dev_free_ext_tbl = NULL,
.tf_dev_free_tbl = NULL,
- .tf_dev_alloc_search_tbl = NULL,
.tf_dev_set_tbl = NULL,
.tf_dev_set_ext_tbl = NULL,
.tf_dev_get_tbl = NULL,
@@ -282,7 +281,6 @@ const struct tf_dev_ops tf_dev_ops_p4 = {
.tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc,
.tf_dev_free_tbl = tf_tbl_free,
.tf_dev_free_ext_tbl = tf_tbl_ext_free,
- .tf_dev_alloc_search_tbl = tf_tbl_alloc_search,
.tf_dev_set_tbl = tf_tbl_set,
.tf_dev_set_ext_tbl = tf_tbl_ext_common_set,
.tf_dev_get_tbl = tf_tbl_get,
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c
index 6bbc5e21e9..ce4d8c661f 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.c
@@ -280,7 +280,6 @@ const struct tf_dev_ops tf_dev_ops_p58_init = {
.tf_dev_alloc_tbl = NULL,
.tf_dev_free_ext_tbl = NULL,
.tf_dev_free_tbl = NULL,
- .tf_dev_alloc_search_tbl = NULL,
.tf_dev_set_tbl = NULL,
.tf_dev_set_ext_tbl = NULL,
.tf_dev_get_tbl = NULL,
@@ -326,7 +325,6 @@ const struct tf_dev_ops tf_dev_ops_p58 = {
.tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc,
.tf_dev_free_tbl = tf_tbl_free,
.tf_dev_free_ext_tbl = tf_tbl_ext_free,
- .tf_dev_alloc_search_tbl = tf_tbl_alloc_search,
.tf_dev_set_tbl = tf_tbl_set,
.tf_dev_set_ext_tbl = tf_tbl_ext_common_set,
.tf_dev_get_tbl = tf_tbl_get,
diff --git a/drivers/net/bnxt/tf_core/tf_em_common.c b/drivers/net/bnxt/tf_core/tf_em_common.c
index 812ccb0d29..3bdfc14e05 100644
--- a/drivers/net/bnxt/tf_core/tf_em_common.c
+++ b/drivers/net/bnxt/tf_core/tf_em_common.c
@@ -23,6 +23,10 @@
#include "bnxt.h"
+
+/** Invalid table scope id */
+#define TF_TBL_SCOPE_INVALID 0xffffffff
+
/* Number of pointers per page_size */
#define MAX_PAGE_PTRS(page_size) ((page_size) / sizeof(void *))
diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c
index ced59130b2..e77399c6bd 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl.c
+++ b/drivers/net/bnxt/tf_core/tf_tbl.c
@@ -26,11 +26,6 @@
struct tf;
-/**
- * Table Shadow DBs
- */
-static void *shadow_tbl_db[TF_DIR_MAX];
-
/**
* Shadow init flag, set on bind and cleared on unbind
*/
@@ -327,22 +322,6 @@ tf_tbl_free(struct tf *tfp __rte_unused,
return 0;
}
-int
-tf_tbl_alloc_search(struct tf *tfp,
- struct tf_tbl_alloc_search_parms *parms)
-{
- int rc = 0;
- TF_CHECK_PARMS2(tfp, parms);
-
- if (!shadow_init || !shadow_tbl_db[parms->dir]) {
- TFP_DRV_LOG(ERR, "%s: Shadow TBL not initialized.\n",
- tf_dir_2_str(parms->dir));
- return -EINVAL;
- }
-
- return rc;
-}
-
int
tf_tbl_set(struct tf *tfp,
struct tf_tbl_set_parms *parms)
diff --git a/drivers/net/bnxt/tf_core/tf_tbl.h b/drivers/net/bnxt/tf_core/tf_tbl.h
index aba46fd161..7e1107ffe7 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl.h
+++ b/drivers/net/bnxt/tf_core/tf_tbl.h
@@ -15,8 +15,6 @@ struct tf;
* The Table module provides processing of Internal TF table types.
*/
-/** Invalid table scope id */
-#define TF_TBL_SCOPE_INVALID 0xffffffff
/**
* Table configuration parameters
@@ -86,57 +84,6 @@ struct tf_tbl_free_parms {
* [in] Index to free
*/
uint32_t idx;
- /**
- * [out] Reference count after free, only valid if session has been
- * created with shadow_copy.
- */
- uint16_t ref_cnt;
-};
-
-/**
- * Table allocate search parameters
- */
-struct tf_tbl_alloc_search_parms {
- /**
- * [in] Receive or transmit direction
- */
- enum tf_dir dir;
- /**
- * [in] Type of the allocation
- */
- enum tf_tbl_type type;
- /**
- * [in] Table scope identifier (ignored unless TF_TBL_TYPE_EXT)
- */
- uint32_t tbl_scope_id;
- /**
- * [in] Result data to search for
- */
- uint8_t *result;
- /**
- * [in] Result data size in bytes
- */
- uint16_t result_sz_in_bytes;
- /**
- * [in] Whether or not to allocate on MISS, 1 is allocate.
- */
- uint8_t alloc;
- /**
- * [out] If search_enable, set if matching entry found
- */
- uint8_t hit;
- /**
- * [out] The status of the search (REJECT, MISS, HIT)
- */
- enum tf_search_status search_status;
- /**
- * [out] Current ref count after allocation
- */
- uint16_t ref_cnt;
- /**
- * [out] Idx of allocated entry or found entry
- */
- uint32_t idx;
};
/**
@@ -326,25 +273,6 @@ int tf_tbl_alloc(struct tf *tfp,
int tf_tbl_free(struct tf *tfp,
struct tf_tbl_free_parms *parms);
-/**
- * Supported if Shadow DB is configured. Searches the Shadow DB for
- * any matching element. If found the refcount in the shadow DB is
- * updated accordingly. If not found a new element is allocated and
- * installed into the shadow DB.
- *
- * [in] tfp
- * Pointer to TF handle, used for HCAPI communication
- *
- * [in] parms
- * Pointer to parameters
- *
- * Returns
- * - (0) if successful.
- * - (-EINVAL) on failure.
- */
-int tf_tbl_alloc_search(struct tf *tfp,
- struct tf_tbl_alloc_search_parms *parms);
-
/**
* Configures the requested element by sending a firmware request which
* then installs it into the device internal structures.
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 871dbad0fe..f3a60cc880 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -189,13 +189,12 @@ ulp_mapper_resource_index_tbl_alloc(struct bnxt_ulp_context *ulp_ctx,
aparms.type = glb_res->resource_type;
aparms.dir = glb_res->direction;
- aparms.search_enable = 0;
aparms.tbl_scope_id = tbl_scope_id;
/* Allocate the index tbl using tf api */
rc = tf_alloc_tbl_entry(tfp, &aparms);
if (rc) {
- BNXT_TF_DBG(ERR, "Failed to alloc identifier [%s][%d]\n",
+ BNXT_TF_DBG(ERR, "Failed to alloc index table [%s][%d]\n",
tf_dir_2_str(aparms.dir), aparms.type);
return rc;
}
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH 02/14] net/bnxt: enable dpool allocator
2021-09-01 14:24 [dpdk-dev] [PATCH 00/14] enhancements to host based flow table management Venkat Duvvuru
2021-09-01 14:24 ` [dpdk-dev] [PATCH 01/14] net/bnxt: tf core index table updates Venkat Duvvuru
@ 2021-09-01 14:24 ` Venkat Duvvuru
2021-09-01 14:24 ` [dpdk-dev] [PATCH 03/14] net/bnxt: add flow meter drop counter support Venkat Duvvuru
` (12 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-01 14:24 UTC (permalink / raw)
To: dev; +Cc: Peter Spreadborough
From: Peter Spreadborough <peter.spreadborough@broadcom.com>
Enable dynamic entry allocator for EM SRAM entries.
Deprecate static entry allocator code.
Signed-off-by: Peter Spreadborough <peter.spreadborough@broadcom.com>
Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
---
drivers/net/bnxt/tf_core/tf_device_p58.c | 4 -
drivers/net/bnxt/tf_core/tf_em.h | 10 -
.../net/bnxt/tf_core/tf_em_hash_internal.c | 34 ----
drivers/net/bnxt/tf_core/tf_em_internal.c | 180 +-----------------
4 files changed, 1 insertion(+), 227 deletions(-)
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c
index ce4d8c661f..808dcb1f77 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.c
@@ -348,11 +348,7 @@ const struct tf_dev_ops tf_dev_ops_p58 = {
.tf_dev_get_tcam_resc_info = tf_tcam_get_resc_info,
.tf_dev_insert_int_em_entry = tf_em_hash_insert_int_entry,
.tf_dev_delete_int_em_entry = tf_em_hash_delete_int_entry,
-#if (TF_EM_ALLOC == 1)
.tf_dev_move_int_em_entry = tf_em_move_int_entry,
-#else
- .tf_dev_move_int_em_entry = NULL,
-#endif
.tf_dev_insert_ext_em_entry = NULL,
.tf_dev_delete_ext_em_entry = NULL,
.tf_dev_get_em_resc_info = tf_em_get_resc_info,
diff --git a/drivers/net/bnxt/tf_core/tf_em.h b/drivers/net/bnxt/tf_core/tf_em.h
index 568071ad8c..074c128651 100644
--- a/drivers/net/bnxt/tf_core/tf_em.h
+++ b/drivers/net/bnxt/tf_core/tf_em.h
@@ -13,16 +13,6 @@
#include "hcapi_cfa_defs.h"
-/**
- * TF_EM_ALLOC
- *
- * 0: Use stack allocator with fixed sized entries
- * (default).
- * 1: Use dpool allocator with variable size
- * entries.
- */
-#define TF_EM_ALLOC 0
-
#define TF_EM_MIN_ENTRIES (1 << 15) /* 32K */
#define TF_EM_MAX_ENTRIES (1 << 27) /* 128M */
diff --git a/drivers/net/bnxt/tf_core/tf_em_hash_internal.c b/drivers/net/bnxt/tf_core/tf_em_hash_internal.c
index 098e8af07e..60273a798c 100644
--- a/drivers/net/bnxt/tf_core/tf_em_hash_internal.c
+++ b/drivers/net/bnxt/tf_core/tf_em_hash_internal.c
@@ -22,9 +22,7 @@
/**
* EM Pool
*/
-#if (TF_EM_ALLOC == 1)
#include "dpool.h"
-#endif
/**
* Insert EM internal entry API
@@ -41,11 +39,7 @@ tf_em_hash_insert_int_entry(struct tf *tfp,
uint16_t rptr_index = 0;
uint8_t rptr_entry = 0;
uint8_t num_of_entries = 0;
-#if (TF_EM_ALLOC == 1)
struct dpool *pool;
-#else
- struct stack *pool;
-#endif
uint32_t index;
uint32_t key0_hash;
uint32_t key1_hash;
@@ -62,7 +56,6 @@ tf_em_hash_insert_int_entry(struct tf *tfp,
rc = tf_session_get_device(tfs, &dev);
if (rc)
return rc;
-#if (TF_EM_ALLOC == 1)
pool = (struct dpool *)tfs->em_pool[parms->dir];
index = dpool_alloc(pool,
parms->em_record_sz_in_bits / 128,
@@ -74,16 +67,6 @@ tf_em_hash_insert_int_entry(struct tf *tfp,
tf_dir_2_str(parms->dir));
return -1;
}
-#else
- pool = (struct stack *)tfs->em_pool[parms->dir];
- rc = stack_pop(pool, &index);
- if (rc) {
- PMD_DRV_LOG(ERR,
- "%s, EM entry index allocation failed\n",
- tf_dir_2_str(parms->dir));
- return rc;
- }
-#endif
if (dev->ops->tf_dev_cfa_key_hash == NULL)
return -EINVAL;
@@ -103,11 +86,7 @@ tf_em_hash_insert_int_entry(struct tf *tfp,
&num_of_entries);
if (rc) {
/* Free the allocated index before returning */
-#if (TF_EM_ALLOC == 1)
dpool_free(pool, index);
-#else
- stack_push(pool, index);
-#endif
return -1;
}
@@ -128,9 +107,7 @@ tf_em_hash_insert_int_entry(struct tf *tfp,
rptr_index,
rptr_entry,
0);
-#if (TF_EM_ALLOC == 1)
dpool_set_entry_data(pool, index, parms->flow_handle);
-#endif
return 0;
}
@@ -146,11 +123,7 @@ tf_em_hash_delete_int_entry(struct tf *tfp,
{
int rc = 0;
struct tf_session *tfs;
-#if (TF_EM_ALLOC == 1)
struct dpool *pool;
-#else
- struct stack *pool;
-#endif
/* Retrieve the session information */
rc = tf_session_get_session(tfp, &tfs);
if (rc) {
@@ -165,19 +138,13 @@ tf_em_hash_delete_int_entry(struct tf *tfp,
/* Return resource to pool */
if (rc == 0) {
-#if (TF_EM_ALLOC == 1)
pool = (struct dpool *)tfs->em_pool[parms->dir];
dpool_free(pool, parms->index);
-#else
- pool = (struct stack *)tfs->em_pool[parms->dir];
- stack_push(pool, parms->index);
-#endif
}
return rc;
}
-#if (TF_EM_ALLOC == 1)
/** Move EM internal entry API
*
* returns:
@@ -212,4 +179,3 @@ tf_em_move_int_entry(struct tf *tfp,
return rc;
}
-#endif
diff --git a/drivers/net/bnxt/tf_core/tf_em_internal.c b/drivers/net/bnxt/tf_core/tf_em_internal.c
index 0720bb905d..2d57595f17 100644
--- a/drivers/net/bnxt/tf_core/tf_em_internal.c
+++ b/drivers/net/bnxt/tf_core/tf_em_internal.c
@@ -22,145 +22,7 @@
/**
* EM Pool
*/
-#if (TF_EM_ALLOC == 1)
#include "dpool.h"
-#else
-
-/**
- * Create EM Tbl pool of memory indexes.
- *
- * [in] dir
- * direction
- * [in] num_entries
- * number of entries to write
- * [in] start
- * starting offset
- *
- * Return:
- * 0 - Success, entry allocated - no search support
- * -ENOMEM -EINVAL -EOPNOTSUPP
- * - Failure, entry not allocated, out of resources
- */
-static int
-tf_create_em_pool(struct tf_session *tfs,
- enum tf_dir dir,
- uint32_t num_entries,
- uint32_t start)
-{
- struct tfp_calloc_parms parms;
- uint32_t i, j;
- int rc = 0;
- struct stack *pool;
-
- /*
- * Allocate stack pool
- */
- parms.nitems = 1;
- parms.size = sizeof(struct stack);
- parms.alignment = 0;
-
- rc = tfp_calloc(&parms);
-
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s, EM stack allocation failure %s\n",
- tf_dir_2_str(dir),
- strerror(-rc));
- return rc;
- }
-
- pool = (struct stack *)parms.mem_va;
- tfs->em_pool[dir] = (void *)pool;
-
- /* Assumes that num_entries has been checked before we get here */
- parms.nitems = num_entries / TF_SESSION_EM_ENTRY_SIZE;
- parms.size = sizeof(uint32_t);
- parms.alignment = 0;
-
- rc = tfp_calloc(&parms);
-
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s, EM pool allocation failure %s\n",
- tf_dir_2_str(dir),
- strerror(-rc));
- return rc;
- }
-
- /* Create empty stack
- */
- rc = stack_init(num_entries / TF_SESSION_EM_ENTRY_SIZE,
- (uint32_t *)parms.mem_va,
- pool);
-
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s, EM pool stack init failure %s\n",
- tf_dir_2_str(dir),
- strerror(-rc));
- goto cleanup;
- }
-
- /* Fill pool with indexes
- */
- j = start + num_entries - TF_SESSION_EM_ENTRY_SIZE;
-
- for (i = 0; i < (num_entries / TF_SESSION_EM_ENTRY_SIZE); i++) {
- rc = stack_push(pool, j);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s, EM pool stack push failure %s\n",
- tf_dir_2_str(dir),
- strerror(-rc));
- goto cleanup;
- }
-
- j -= TF_SESSION_EM_ENTRY_SIZE;
- }
-
- if (!stack_is_full(pool)) {
- rc = -EINVAL;
- TFP_DRV_LOG(ERR,
- "%s, EM pool stack failure %s\n",
- tf_dir_2_str(dir),
- strerror(-rc));
- goto cleanup;
- }
-
- return 0;
-cleanup:
- tfp_free((void *)parms.mem_va);
- tfp_free((void *)tfs->em_pool[dir]);
- tfs->em_pool[dir] = NULL;
- return rc;
-}
-
-/**
- * Create EM Tbl pool of memory indexes.
- *
- * [in] dir
- * direction
- *
- * Return:
- */
-static void
-tf_free_em_pool(struct tf_session *tfs,
- enum tf_dir dir)
-{
- struct stack *pool = (struct stack *)tfs->em_pool[dir];
- uint32_t *ptr;
-
- if (pool != NULL) {
- ptr = stack_items(pool);
-
- if (ptr != NULL)
- tfp_free(ptr);
-
- tfp_free(pool);
- tfs->em_pool[dir] = NULL;
- }
-}
-#endif /* TF_EM_ALLOC != 1 */
/**
* Insert EM internal entry API
@@ -178,11 +40,7 @@ tf_em_insert_int_entry(struct tf *tfp,
uint8_t rptr_entry = 0;
uint8_t num_of_entries = 0;
struct tf_session *tfs;
-#if (TF_EM_ALLOC == 1)
struct dpool *pool;
-#else
- struct stack *pool;
-#endif
uint32_t index;
/* Retrieve the session information */
@@ -195,7 +53,6 @@ tf_em_insert_int_entry(struct tf *tfp,
return rc;
}
-#if (TF_EM_ALLOC == 1)
pool = (struct dpool *)tfs->em_pool[parms->dir];
index = dpool_alloc(pool, TF_SESSION_EM_ENTRY_SIZE, 0);
if (index == DP_INVALID_INDEX) {
@@ -204,16 +61,6 @@ tf_em_insert_int_entry(struct tf *tfp,
tf_dir_2_str(parms->dir));
return -1;
}
-#else
- pool = (struct stack *)tfs->em_pool[parms->dir];
- rc = stack_pop(pool, &index);
- if (rc) {
- PMD_DRV_LOG(ERR,
- "%s, EM entry index allocation failed\n",
- tf_dir_2_str(parms->dir));
- return rc;
- }
-#endif
rptr_index = index;
@@ -224,11 +71,7 @@ tf_em_insert_int_entry(struct tf *tfp,
&num_of_entries);
if (rc) {
/* Free the allocated index before returning */
-#if (TF_EM_ALLOC == 1)
dpool_free(pool, index);
-#else
- stack_push(pool, index);
-#endif
return -1;
}
TF_SET_GFID(gfid,
@@ -264,11 +107,7 @@ tf_em_delete_int_entry(struct tf *tfp,
{
int rc = 0;
struct tf_session *tfs;
-#if (TF_EM_ALLOC == 1)
struct dpool *pool;
-#else
- struct stack *pool;
-#endif
/* Retrieve the session information */
rc = tf_session_get_session(tfp, &tfs);
if (rc) {
@@ -283,19 +122,13 @@ tf_em_delete_int_entry(struct tf *tfp,
/* Return resource to pool */
if (rc == 0) {
-#if (TF_EM_ALLOC == 1)
pool = (struct dpool *)tfs->em_pool[parms->dir];
dpool_free(pool, parms->index);
-#else
- pool = (struct stack *)tfs->em_pool[parms->dir];
- stack_push(pool, parms->index);
-#endif
}
return rc;
}
-#if (TF_EM_ALLOC == 1)
static int
tf_em_move_callback(void *user_data,
uint64_t entry_data,
@@ -342,7 +175,6 @@ tf_em_move_callback(void *user_data,
return rc;
}
-#endif
int
tf_em_int_bind(struct tf *tfp,
@@ -434,7 +266,7 @@ tf_em_int_bind(struct tf *tfp,
tf_dir_2_str(i));
return rc;
}
-#if (TF_EM_ALLOC == 1)
+
/*
* Allocate stack pool
*/
@@ -460,12 +292,6 @@ tf_em_int_bind(struct tf *tfp,
7,
(void *)tfp,
tf_em_move_callback);
-#else
- rc = tf_create_em_pool(tfs,
- i,
- iparms.info->entry.stride,
- iparms.info->entry.start);
-#endif
/* Logging handled in tf_create_em_pool */
if (rc)
return rc;
@@ -501,11 +327,7 @@ tf_em_int_unbind(struct tf *tfp)
if (!tf_session_is_shared_session(tfs)) {
for (i = 0; i < TF_DIR_MAX; i++)
-#if (TF_EM_ALLOC == 1)
dpool_free_all(tfs->em_pool[i]);
-#else
- tf_free_em_pool(tfs, i);
-#endif
}
rc = tf_session_get_db(tfp, TF_MODULE_TYPE_EM, &em_db_ptr);
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH 03/14] net/bnxt: add flow meter drop counter support
2021-09-01 14:24 [dpdk-dev] [PATCH 00/14] enhancements to host based flow table management Venkat Duvvuru
2021-09-01 14:24 ` [dpdk-dev] [PATCH 01/14] net/bnxt: tf core index table updates Venkat Duvvuru
2021-09-01 14:24 ` [dpdk-dev] [PATCH 02/14] net/bnxt: enable dpool allocator Venkat Duvvuru
@ 2021-09-01 14:24 ` Venkat Duvvuru
2021-09-01 14:24 ` [dpdk-dev] [PATCH 04/14] net/bnxt: add Thor SRAM mgr model Venkat Duvvuru
` (11 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-01 14:24 UTC (permalink / raw)
To: dev; +Cc: Jay Ding
From: Jay Ding <jay.ding@broadcom.com>
- Add flow meter drop counter support for Thor.
Signed-off-by: Jay Ding <jay.ding@broadcom.com>
Reviewed-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/tf_core/cfa_resource_types.h | 5 +-
drivers/net/bnxt/tf_core/tf_core.h | 8 +-
drivers/net/bnxt/tf_core/tf_device_p58.c | 1 +
drivers/net/bnxt/tf_core/tf_device_p58.h | 14 ++++
drivers/net/bnxt/tf_core/tf_tbl.c | 74 +++++++++++--------
drivers/net/bnxt/tf_core/tf_util.c | 2 +
6 files changed, 68 insertions(+), 36 deletions(-)
diff --git a/drivers/net/bnxt/tf_core/cfa_resource_types.h b/drivers/net/bnxt/tf_core/cfa_resource_types.h
index cbab0d0078..36a55d4e17 100644
--- a/drivers/net/bnxt/tf_core/cfa_resource_types.h
+++ b/drivers/net/bnxt/tf_core/cfa_resource_types.h
@@ -104,10 +104,11 @@
#define CFA_RESOURCE_TYPE_P58_WC_FKB 0x12UL
/* VEB TCAM */
#define CFA_RESOURCE_TYPE_P58_VEB_TCAM 0x13UL
+/* Metadata */
+#define CFA_RESOURCE_TYPE_P58_METADATA 0x14UL
/* Meter drop counter */
#define CFA_RESOURCE_TYPE_P58_METER_DROP_CNT 0x15UL
-#define CFA_RESOURCE_TYPE_P58_LAST CFA_RESOURCE_TYPE_P58_METER_DROP_CNT
-
+#define CFA_RESOURCE_TYPE_P58_LAST CFA_RESOURCE_TYPE_P58_METER_DROP_CNT
/* Multicast Group */
#define CFA_RESOURCE_TYPE_P45_MCG 0x0UL
diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h
index 7e0cdf7e0d..af8d13bd7e 100644
--- a/drivers/net/bnxt/tf_core/tf_core.h
+++ b/drivers/net/bnxt/tf_core/tf_core.h
@@ -283,9 +283,9 @@ enum tf_tbl_type {
TF_TBL_TYPE_ACT_MODIFY_32B,
/** TH 64B Modify Record */
TF_TBL_TYPE_ACT_MODIFY_64B,
- /** (Future) Meter Profiles */
+ /** Meter Profiles */
TF_TBL_TYPE_METER_PROF,
- /** (Future) Meter Instance */
+ /** Meter Instance */
TF_TBL_TYPE_METER_INST,
/** Wh+/SR/Th Mirror Config */
TF_TBL_TYPE_MIRROR_CONFIG,
@@ -301,6 +301,8 @@ enum tf_tbl_type {
TF_TBL_TYPE_EM_FKB,
/** TH WC Flexible Key builder */
TF_TBL_TYPE_WC_FKB,
+ /** Meter Drop Counter */
+ TF_TBL_TYPE_METER_DROP_CNT,
/* External */
@@ -2194,6 +2196,8 @@ enum tf_global_config_type {
TF_TUNNEL_ENCAP, /**< Tunnel Encap Config(TECT) */
TF_ACTION_BLOCK, /**< Action Block Config(ABCR) */
TF_COUNTER_CFG, /**< Counter Configuration (CNTRS_CTRL) */
+ TF_METER_CFG, /**< Meter Config(ACTP4_FMTCR) */
+ TF_METER_INTERVAL_CFG, /**< Meter Interval Config(FMTCR_INTERVAL) */
TF_GLOBAL_CFG_TYPE_MAX
};
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c
index 808dcb1f77..a492c62bff 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.c
@@ -43,6 +43,7 @@ const char *tf_resource_str_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = {
[CFA_RESOURCE_TYPE_P58_EM_FKB] = "em_fkb ",
[CFA_RESOURCE_TYPE_P58_WC_FKB] = "wc_fkb ",
[CFA_RESOURCE_TYPE_P58_VEB_TCAM] = "veb ",
+ [CFA_RESOURCE_TYPE_P58_METADATA] = "metadata",
};
/**
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h
index 66b0f4e983..8c2e07aa34 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.h
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.h
@@ -75,10 +75,18 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER,
0, 0, 0
},
+ [TF_TBL_TYPE_METER_DROP_CNT] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT,
+ 0, 0, 0
+ },
[TF_TBL_TYPE_MIRROR_CONFIG] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR,
0, 0, 0
},
+ [TF_TBL_TYPE_METADATA] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA,
+ 0, 0, 0
+ },
/* Policy - ARs in bank 1 */
[TF_TBL_TYPE_FULL_ACT_RECORD] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
@@ -194,5 +202,11 @@ struct tf_global_cfg_cfg tf_global_cfg_p58[TF_GLOBAL_CFG_TYPE_MAX] = {
[TF_COUNTER_CFG] = {
TF_GLOBAL_CFG_CFG_HCAPI, TF_COUNTER_CFG
},
+ [TF_METER_CFG] = {
+ TF_GLOBAL_CFG_CFG_HCAPI, TF_METER_CFG
+ },
+ [TF_METER_INTERVAL_CFG] = {
+ TF_GLOBAL_CFG_CFG_HCAPI, TF_METER_INTERVAL_CFG
+ },
};
#endif /* _TF_DEVICE_P58_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c
index e77399c6bd..7011edcd78 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl.c
+++ b/drivers/net/bnxt/tf_core/tf_tbl.c
@@ -374,23 +374,28 @@ tf_tbl_set(struct tf *tfp,
}
}
- /* Verify that the entry has been previously allocated */
- aparms.rm_db = tbl_db->tbl_db[parms->dir];
- aparms.subtype = parms->type;
- TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift);
-
- aparms.allocated = &allocated;
- rc = tf_rm_is_allocated(&aparms);
- if (rc)
- return rc;
+ /* Do not check meter drop counter because it is not allocated
+ * resources
+ */
+ if (parms->type != TF_TBL_TYPE_METER_DROP_CNT) {
+ /* Verify that the entry has been previously allocated */
+ aparms.rm_db = tbl_db->tbl_db[parms->dir];
+ aparms.subtype = parms->type;
+ TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift);
+
+ aparms.allocated = &allocated;
+ rc = tf_rm_is_allocated(&aparms);
+ if (rc)
+ return rc;
- if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
- TFP_DRV_LOG(ERR,
- "%s, Invalid or not allocated index, type:%d, idx:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type,
- parms->idx);
- return -EINVAL;
+ if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
+ TFP_DRV_LOG(ERR,
+ "%s, Invalid or not allocated index, type:%d, idx:%d\n",
+ tf_dir_2_str(parms->dir),
+ parms->type,
+ parms->idx);
+ return -EINVAL;
+ }
}
/* Set the entry */
@@ -477,23 +482,28 @@ tf_tbl_get(struct tf *tfp,
}
}
- /* Verify that the entry has been previously allocated */
- aparms.rm_db = tbl_db->tbl_db[parms->dir];
- aparms.subtype = parms->type;
- TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift);
-
- aparms.allocated = &allocated;
- rc = tf_rm_is_allocated(&aparms);
- if (rc)
- return rc;
+ /* Do not check meter drop counter because it is not allocated
+ * resources.
+ */
+ if (parms->type != TF_TBL_TYPE_METER_DROP_CNT) {
+ /* Verify that the entry has been previously allocated */
+ aparms.rm_db = tbl_db->tbl_db[parms->dir];
+ aparms.subtype = parms->type;
+ TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift);
+
+ aparms.allocated = &allocated;
+ rc = tf_rm_is_allocated(&aparms);
+ if (rc)
+ return rc;
- if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
- TFP_DRV_LOG(ERR,
- "%s, Invalid or not allocated index, type:%d, idx:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type,
- parms->idx);
- return -EINVAL;
+ if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
+ TFP_DRV_LOG(ERR,
+ "%s, Invalid or not allocated index, type:%d, idx:%d\n",
+ tf_dir_2_str(parms->dir),
+ parms->type,
+ parms->idx);
+ return -EINVAL;
+ }
}
/* Set the entry */
diff --git a/drivers/net/bnxt/tf_core/tf_util.c b/drivers/net/bnxt/tf_core/tf_util.c
index e712816209..d100399d0a 100644
--- a/drivers/net/bnxt/tf_core/tf_util.c
+++ b/drivers/net/bnxt/tf_core/tf_util.c
@@ -112,6 +112,8 @@ tf_tbl_type_2_str(enum tf_tbl_type tbl_type)
return "WC Flexible Key Builder";
case TF_TBL_TYPE_EXT:
return "External";
+ case TF_TBL_TYPE_METER_DROP_CNT:
+ return "Meter drop counter";
default:
return "Invalid tbl type";
}
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH 04/14] net/bnxt: add Thor SRAM mgr model
2021-09-01 14:24 [dpdk-dev] [PATCH 00/14] enhancements to host based flow table management Venkat Duvvuru
` (2 preceding siblings ...)
2021-09-01 14:24 ` [dpdk-dev] [PATCH 03/14] net/bnxt: add flow meter drop counter support Venkat Duvvuru
@ 2021-09-01 14:24 ` Venkat Duvvuru
2021-09-01 14:24 ` [dpdk-dev] [PATCH 05/14] net/bnxt: add flow templates support for Thor Venkat Duvvuru
` (10 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-01 14:24 UTC (permalink / raw)
To: dev; +Cc: Farah Smith
From: Farah Smith <farah.smith@broadcom.com>
Add dynamic SRAM manager allocation support.
Signed-off-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com>
Reviewed-by: Peter Spreadborough <peter.spreadborough@broadcom.com>
---
drivers/net/bnxt/tf_core/ll.c | 3 +
drivers/net/bnxt/tf_core/ll.h | 50 +-
drivers/net/bnxt/tf_core/meson.build | 2 +
drivers/net/bnxt/tf_core/tf_core.c | 104 ++-
drivers/net/bnxt/tf_core/tf_core.h | 48 +-
drivers/net/bnxt/tf_core/tf_device.c | 40 +-
drivers/net/bnxt/tf_core/tf_device.h | 133 ++-
drivers/net/bnxt/tf_core/tf_device_p4.c | 75 +-
drivers/net/bnxt/tf_core/tf_device_p4.h | 50 +-
drivers/net/bnxt/tf_core/tf_device_p58.c | 105 ++-
drivers/net/bnxt/tf_core/tf_device_p58.h | 60 +-
drivers/net/bnxt/tf_core/tf_msg.c | 2 +-
drivers/net/bnxt/tf_core/tf_rm.c | 46 +-
drivers/net/bnxt/tf_core/tf_rm.h | 62 +-
drivers/net/bnxt/tf_core/tf_session.c | 56 ++
drivers/net/bnxt/tf_core/tf_session.h | 58 +-
drivers/net/bnxt/tf_core/tf_sram_mgr.c | 971 ++++++++++++++++++++++
drivers/net/bnxt/tf_core/tf_sram_mgr.h | 317 +++++++
drivers/net/bnxt/tf_core/tf_tbl.c | 186 +----
drivers/net/bnxt/tf_core/tf_tbl.h | 15 +-
drivers/net/bnxt/tf_core/tf_tbl_sram.c | 713 ++++++++++++++++
drivers/net/bnxt/tf_core/tf_tbl_sram.h | 154 ++++
drivers/net/bnxt/tf_core/tf_tcam.c | 10 +-
drivers/net/bnxt/tf_core/tf_tcam.h | 7 +
drivers/net/bnxt/tf_core/tf_tcam_shared.c | 28 +-
drivers/net/bnxt/tf_core/tf_util.c | 10 +
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 23 +
meson_options.txt | 2 +
28 files changed, 2978 insertions(+), 352 deletions(-)
create mode 100644 drivers/net/bnxt/tf_core/tf_sram_mgr.c
create mode 100644 drivers/net/bnxt/tf_core/tf_sram_mgr.h
create mode 100644 drivers/net/bnxt/tf_core/tf_tbl_sram.c
create mode 100644 drivers/net/bnxt/tf_core/tf_tbl_sram.h
diff --git a/drivers/net/bnxt/tf_core/ll.c b/drivers/net/bnxt/tf_core/ll.c
index cd168a7970..f2bdff6b9e 100644
--- a/drivers/net/bnxt/tf_core/ll.c
+++ b/drivers/net/bnxt/tf_core/ll.c
@@ -13,6 +13,7 @@ void ll_init(struct ll *ll)
{
ll->head = NULL;
ll->tail = NULL;
+ ll->cnt = 0;
}
/* insert entry in linked list */
@@ -30,6 +31,7 @@ void ll_insert(struct ll *ll,
entry->next->prev = entry;
ll->head = entry->next->prev;
}
+ ll->cnt++;
}
/* delete entry from linked list */
@@ -49,4 +51,5 @@ void ll_delete(struct ll *ll,
entry->prev->next = entry->next;
entry->next->prev = entry->prev;
}
+ ll->cnt--;
}
diff --git a/drivers/net/bnxt/tf_core/ll.h b/drivers/net/bnxt/tf_core/ll.h
index 239478b4f8..9cf8f64ec2 100644
--- a/drivers/net/bnxt/tf_core/ll.h
+++ b/drivers/net/bnxt/tf_core/ll.h
@@ -8,6 +8,8 @@
#ifndef _LL_H_
#define _LL_H_
+#include <stdint.h>
+
/* linked list entry */
struct ll_entry {
struct ll_entry *prev;
@@ -18,6 +20,7 @@ struct ll_entry {
struct ll {
struct ll_entry *head;
struct ll_entry *tail;
+ uint32_t cnt;
};
/**
@@ -28,7 +31,7 @@ struct ll {
void ll_init(struct ll *ll);
/**
- * Linked list insert
+ * Linked list insert head
*
* [in] ll, linked list where element is inserted
* [in] entry, entry to be added
@@ -43,4 +46,49 @@ void ll_insert(struct ll *ll, struct ll_entry *entry);
*/
void ll_delete(struct ll *ll, struct ll_entry *entry);
+/**
+ * Linked list return next entry without deleting it
+ *
+ * Useful in performing search
+ *
+ * [in] Entry in the list
+ */
+static inline struct ll_entry *ll_next(struct ll_entry *entry)
+{
+ return entry->next;
+}
+
+/**
+ * Linked list return the head of the list without removing it
+ *
+ * Useful in performing search
+ *
+ * [in] ll, linked list
+ */
+static inline struct ll_entry *ll_head(struct ll *ll)
+{
+ return ll->head;
+}
+
+/**
+ * Linked list return the tail of the list without removing it
+ *
+ * Useful in performing search
+ *
+ * [in] ll, linked list
+ */
+static inline struct ll_entry *ll_tail(struct ll *ll)
+{
+ return ll->tail;
+}
+
+/**
+ * Linked list return the number of entries in the list
+ *
+ * [in] ll, linked list
+ */
+static inline uint32_t ll_cnt(struct ll *ll)
+{
+ return ll->cnt;
+}
#endif /* _LL_H_ */
diff --git a/drivers/net/bnxt/tf_core/meson.build b/drivers/net/bnxt/tf_core/meson.build
index f28e77ec2e..b7333a431b 100644
--- a/drivers/net/bnxt/tf_core/meson.build
+++ b/drivers/net/bnxt/tf_core/meson.build
@@ -16,6 +16,8 @@ sources += files(
'stack.c',
'tf_rm.c',
'tf_tbl.c',
+ 'tf_tbl_sram.c',
+ 'tf_sram_mgr.c',
'tf_em_common.c',
'tf_em_host.c',
'tf_em_internal.c',
diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c
index 5458f76e2d..936102c804 100644
--- a/drivers/net/bnxt/tf_core/tf_core.c
+++ b/drivers/net/bnxt/tf_core/tf_core.c
@@ -1079,17 +1079,16 @@ tf_alloc_tbl_entry(struct tf *tfp,
strerror(-rc));
return rc;
}
-
- } else {
- if (dev->ops->tf_dev_alloc_tbl == NULL) {
- rc = -EOPNOTSUPP;
+ } else if (dev->ops->tf_dev_is_sram_managed(tfp, parms->type)) {
+ rc = dev->ops->tf_dev_alloc_sram_tbl(tfp, &aparms);
+ if (rc) {
TFP_DRV_LOG(ERR,
- "%s: Operation not supported, rc:%s\n",
+ "%s: SRAM table allocation failed, rc:%s\n",
tf_dir_2_str(parms->dir),
strerror(-rc));
- return -EOPNOTSUPP;
+ return rc;
}
-
+ } else {
rc = dev->ops->tf_dev_alloc_tbl(tfp, &aparms);
if (rc) {
TFP_DRV_LOG(ERR,
@@ -1162,15 +1161,16 @@ tf_free_tbl_entry(struct tf *tfp,
strerror(-rc));
return rc;
}
- } else {
- if (dev->ops->tf_dev_free_tbl == NULL) {
- rc = -EOPNOTSUPP;
+ } else if (dev->ops->tf_dev_is_sram_managed(tfp, parms->type)) {
+ rc = dev->ops->tf_dev_free_sram_tbl(tfp, &fparms);
+ if (rc) {
TFP_DRV_LOG(ERR,
- "%s: Operation not supported, rc:%s\n",
+ "%s: SRAM table free failed, rc:%s\n",
tf_dir_2_str(parms->dir),
strerror(-rc));
- return -EOPNOTSUPP;
+ return rc;
}
+ } else {
rc = dev->ops->tf_dev_free_tbl(tfp, &fparms);
if (rc) {
@@ -1181,7 +1181,6 @@ tf_free_tbl_entry(struct tf *tfp,
return rc;
}
}
-
return 0;
}
@@ -1244,6 +1243,15 @@ tf_set_tbl_entry(struct tf *tfp,
strerror(-rc));
return rc;
}
+ } else if (dev->ops->tf_dev_is_sram_managed(tfp, parms->type)) {
+ rc = dev->ops->tf_dev_set_sram_tbl(tfp, &sparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: SRAM table set failed, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ strerror(-rc));
+ return rc;
+ }
} else {
if (dev->ops->tf_dev_set_tbl == NULL) {
rc = -EOPNOTSUPP;
@@ -1300,28 +1308,39 @@ tf_get_tbl_entry(struct tf *tfp,
strerror(-rc));
return rc;
}
-
- if (dev->ops->tf_dev_get_tbl == NULL) {
- rc = -EOPNOTSUPP;
- TFP_DRV_LOG(ERR,
- "%s: Operation not supported, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(-rc));
- return -EOPNOTSUPP;
- }
-
gparms.dir = parms->dir;
gparms.type = parms->type;
gparms.data = parms->data;
gparms.data_sz_in_bytes = parms->data_sz_in_bytes;
gparms.idx = parms->idx;
- rc = dev->ops->tf_dev_get_tbl(tfp, &gparms);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Table get failed, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(-rc));
- return rc;
+
+ if (dev->ops->tf_dev_is_sram_managed(tfp, parms->type)) {
+ rc = dev->ops->tf_dev_get_sram_tbl(tfp, &gparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: SRAM table get failed, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ strerror(-rc));
+ return rc;
+ }
+ } else {
+ if (dev->ops->tf_dev_get_tbl == NULL) {
+ rc = -EOPNOTSUPP;
+ TFP_DRV_LOG(ERR,
+ "%s: Operation not supported, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ strerror(-rc));
+ return -EOPNOTSUPP;
+ }
+
+ rc = dev->ops->tf_dev_get_tbl(tfp, &gparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Table get failed, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ strerror(-rc));
+ return rc;
+ }
}
return rc;
@@ -1361,6 +1380,13 @@ tf_bulk_get_tbl_entry(struct tf *tfp,
return rc;
}
+ bparms.dir = parms->dir;
+ bparms.type = parms->type;
+ bparms.starting_idx = parms->starting_idx;
+ bparms.num_entries = parms->num_entries;
+ bparms.entry_sz_in_bytes = parms->entry_sz_in_bytes;
+ bparms.physical_mem_addr = parms->physical_mem_addr;
+
if (parms->type == TF_TBL_TYPE_EXT) {
/* Not supported, yet */
rc = -EOPNOTSUPP;
@@ -1370,10 +1396,17 @@ tf_bulk_get_tbl_entry(struct tf *tfp,
strerror(-rc));
return rc;
+ } else if (dev->ops->tf_dev_is_sram_managed(tfp, parms->type)) {
+ rc = dev->ops->tf_dev_get_bulk_sram_tbl(tfp, &bparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: SRAM table bulk get failed, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ strerror(-rc));
+ }
+ return rc;
}
- /* Internal table type processing */
-
if (dev->ops->tf_dev_get_bulk_tbl == NULL) {
rc = -EOPNOTSUPP;
TFP_DRV_LOG(ERR,
@@ -1383,12 +1416,6 @@ tf_bulk_get_tbl_entry(struct tf *tfp,
return -EOPNOTSUPP;
}
- bparms.dir = parms->dir;
- bparms.type = parms->type;
- bparms.starting_idx = parms->starting_idx;
- bparms.num_entries = parms->num_entries;
- bparms.entry_sz_in_bytes = parms->entry_sz_in_bytes;
- bparms.physical_mem_addr = parms->physical_mem_addr;
rc = dev->ops->tf_dev_get_bulk_tbl(tfp, &bparms);
if (rc) {
TFP_DRV_LOG(ERR,
@@ -1397,7 +1424,6 @@ tf_bulk_get_tbl_entry(struct tf *tfp,
strerror(-rc));
return rc;
}
-
return rc;
}
diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h
index af8d13bd7e..fb02c2b161 100644
--- a/drivers/net/bnxt/tf_core/tf_core.h
+++ b/drivers/net/bnxt/tf_core/tf_core.h
@@ -65,6 +65,16 @@ enum tf_ext_mem_chan_type {
TF_EXT_MEM_CHAN_TYPE_MAX
};
+/**
+ * WC TCAM number of slice per row that devices supported
+ */
+enum tf_wc_num_slice {
+ TF_WC_TCAM_1_SLICE_PER_ROW = 1,
+ TF_WC_TCAM_2_SLICE_PER_ROW = 2,
+ TF_WC_TCAM_4_SLICE_PER_ROW = 4,
+ TF_WC_TCAM_8_SLICE_PER_ROW = 8,
+};
+
/**
* EEM record AR helper
*
@@ -670,6 +680,13 @@ struct tf_open_session_parms {
*/
void *bp;
+ /**
+ * [in]
+ *
+ * The number of slices per row for WC TCAM entry.
+ */
+ enum tf_wc_num_slice wc_num_slices;
+
/**
* [out] shared_session_creator
*
@@ -734,8 +751,6 @@ int tf_open_session(struct tf *tfp,
/**
* General internal resource info
*
- * TODO: remove tf_rm_new_entry structure and use this structure
- * internally.
*/
struct tf_resource_info {
uint16_t start;
@@ -1656,12 +1671,7 @@ struct tf_alloc_tbl_entry_parms {
* entry of the indicated type for this TruFlow session.
*
* Allocates an index table record. This function will attempt to
- * allocate an entry or search an index table for a matching entry if
- * search is enabled (only the shadow copy of the table is accessed).
- *
- * If search is not enabled, the first available free entry is
- * returned. If search is enabled and a matching entry to entry_data
- * is found hit is set to TRUE and success is returned.
+ * allocate an index table entry.
*
* External types:
*
@@ -1670,8 +1680,8 @@ struct tf_alloc_tbl_entry_parms {
* Allocates an external index table action record.
*
* NOTE:
- * Implementation of the internals of this function will be a stack with push
- * and pop.
+ * Implementation of the internals of the external function will be a stack with
+ * push and pop.
*
* Returns success or failure code.
*/
@@ -1707,20 +1717,15 @@ struct tf_free_tbl_entry_parms {
*
* Internal types:
*
- * If session has shadow_copy enabled the shadow DB is searched and if
- * found the element ref_cnt is decremented. If ref_cnt goes to
- * zero then the element is returned to the session pool.
- *
- * If the session does not have a shadow DB the element is free'ed and
- * given back to the session pool.
+ * The element is freed and given back to the session pool.
*
* External types:
*
- * Free's an external index table action record.
+ * Frees an external index table action record.
*
* NOTE:
- * Implementation of the internals of this function will be a stack with push
- * and pop.
+ * Implementation of the internals of the external table will be a stack with
+ * push and pop.
*
* Returns success or failure code.
*/
@@ -1764,9 +1769,8 @@ struct tf_set_tbl_entry_parms {
/**
* set index table entry
*
- * Used to insert an application programmed index table entry into a
- * previous allocated table location. A shadow copy of the table
- * is maintained (if enabled) (only for internal objects)
+ * Used to set an application programmed index table entry into a
+ * previous allocated table location.
*
* Returns success or failure code.
*/
diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c
index 498e668b16..25a7166bbb 100644
--- a/drivers/net/bnxt/tf_core/tf_device.c
+++ b/drivers/net/bnxt/tf_core/tf_device.c
@@ -11,10 +11,14 @@
#include "tf_rm.h"
#ifdef TF_TCAM_SHARED
#include "tf_tcam_shared.h"
+#include "tf_tbl_sram.h"
#endif /* TF_TCAM_SHARED */
struct tf;
+/* Number of slices per row for WC TCAM */
+uint16_t g_wc_num_slices_per_row = TF_WC_TCAM_1_SLICE_PER_ROW;
+
/* Forward declarations */
static int tf_dev_unbind_p4(struct tf *tfp);
static int tf_dev_unbind_p58(struct tf *tfp);
@@ -83,7 +87,8 @@ static int
tf_dev_bind_p4(struct tf *tfp,
bool shadow_copy,
struct tf_session_resources *resources,
- struct tf_dev_info *dev_handle)
+ struct tf_dev_info *dev_handle,
+ enum tf_wc_num_slice wc_num_slices)
{
int rc;
int frc;
@@ -131,7 +136,6 @@ tf_dev_bind_p4(struct tf *tfp,
if (rsv_cnt) {
tbl_cfg.num_elements = TF_TBL_TYPE_MAX;
tbl_cfg.cfg = tf_tbl_p4;
- tbl_cfg.shadow_copy = shadow_copy;
tbl_cfg.resources = resources;
rc = tf_tbl_bind(tfp, &tbl_cfg);
if (rc) {
@@ -151,6 +155,7 @@ tf_dev_bind_p4(struct tf *tfp,
tcam_cfg.cfg = tf_tcam_p4;
tcam_cfg.shadow_copy = shadow_copy;
tcam_cfg.resources = resources;
+ tcam_cfg.wc_num_slices = wc_num_slices;
#ifdef TF_TCAM_SHARED
rc = tf_tcam_shared_bind(tfp, &tcam_cfg);
#else /* !TF_TCAM_SHARED */
@@ -369,7 +374,8 @@ static int
tf_dev_bind_p58(struct tf *tfp,
bool shadow_copy,
struct tf_session_resources *resources,
- struct tf_dev_info *dev_handle)
+ struct tf_dev_info *dev_handle,
+ enum tf_wc_num_slice wc_num_slices)
{
int rc;
int frc;
@@ -414,7 +420,6 @@ tf_dev_bind_p58(struct tf *tfp,
if (rsv_cnt) {
tbl_cfg.num_elements = TF_TBL_TYPE_MAX;
tbl_cfg.cfg = tf_tbl_p58;
- tbl_cfg.shadow_copy = shadow_copy;
tbl_cfg.resources = resources;
rc = tf_tbl_bind(tfp, &tbl_cfg);
if (rc) {
@@ -423,6 +428,13 @@ tf_dev_bind_p58(struct tf *tfp,
goto fail;
}
no_rsv_flag = false;
+
+ rc = tf_tbl_sram_bind(tfp);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "SRAM table initialization failure\n");
+ goto fail;
+ }
}
rsv_cnt = tf_dev_reservation_check(TF_TCAM_TBL_TYPE_MAX,
@@ -433,6 +445,7 @@ tf_dev_bind_p58(struct tf *tfp,
tcam_cfg.cfg = tf_tcam_p58;
tcam_cfg.shadow_copy = shadow_copy;
tcam_cfg.resources = resources;
+ tcam_cfg.wc_num_slices = wc_num_slices;
#ifdef TF_TCAM_SHARED
rc = tf_tcam_shared_bind(tfp, &tcam_cfg);
#else /* !TF_TCAM_SHARED */
@@ -565,6 +578,18 @@ tf_dev_unbind_p58(struct tf *tfp)
fail = true;
}
+ /* Unbind the SRAM table prior to table as the table manager
+ * owns and frees the table DB while the SRAM table manager owns
+ * and manages it's internal data structures. SRAM table manager
+ * relies on the table rm_db to exist.
+ */
+ rc = tf_tbl_sram_unbind(tfp);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Device unbind failed, SRAM table\n");
+ fail = true;
+ }
+
rc = tf_tbl_unbind(tfp);
if (rc) {
TFP_DRV_LOG(INFO,
@@ -606,6 +631,7 @@ tf_dev_bind(struct tf *tfp __rte_unused,
enum tf_device_type type,
bool shadow_copy,
struct tf_session_resources *resources,
+ uint16_t wc_num_slices,
struct tf_dev_info *dev_handle)
{
switch (type) {
@@ -615,13 +641,15 @@ tf_dev_bind(struct tf *tfp __rte_unused,
return tf_dev_bind_p4(tfp,
shadow_copy,
resources,
- dev_handle);
+ dev_handle,
+ wc_num_slices);
case TF_DEVICE_TYPE_THOR:
dev_handle->type = type;
return tf_dev_bind_p58(tfp,
shadow_copy,
resources,
- dev_handle);
+ dev_handle,
+ wc_num_slices);
default:
TFP_DRV_LOG(ERR,
"No such device\n");
diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h
index b43cfc6925..9b0c037db0 100644
--- a/drivers/net/bnxt/tf_core/tf_device.h
+++ b/drivers/net/bnxt/tf_core/tf_device.h
@@ -57,6 +57,9 @@ struct tf_dev_info {
* [in] resources
* Pointer to resource allocation information
*
+ * [in] wc_num_slices
+ * Number of slices per row for WC
+ *
* [out] dev_handle
* Device handle
*
@@ -69,6 +72,7 @@ int tf_dev_bind(struct tf *tfp,
enum tf_device_type type,
bool shadow_copy,
struct tf_session_resources *resources,
+ uint16_t wc_num_slices,
struct tf_dev_info *dev_handle);
/**
@@ -139,6 +143,23 @@ struct tf_dev_ops {
uint16_t resource_id,
const char **resource_str);
+ /**
+ * Set the WC TCAM slice information that the device
+ * supports.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] num_slices_per_row
+ * Number of slices per row the device supports
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+ int (*tf_dev_set_tcam_slice_info)(struct tf *tfp,
+ enum tf_wc_num_slice num_slices_per_row);
+
/**
* Retrieves the WC TCAM slice information that the device
* supports.
@@ -241,6 +262,22 @@ struct tf_dev_ops {
int (*tf_dev_get_ident_resc_info)(struct tf *tfp,
struct tf_identifier_resource_info *parms);
+ /**
+ * Indicates whether the index table type is SRAM managed
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] type
+ * Truflow index table type, e.g. TF_TYPE_FULL_ACT_RECORD
+ *
+ * Returns
+ * - (0) if the table is not managed by the SRAM manager
+ * - (1) if the table is managed by the SRAM manager
+ */
+ bool (*tf_dev_is_sram_managed)(struct tf *tfp,
+ enum tf_tbl_type tbl_type);
+
/**
* Get SRAM table information.
*
@@ -289,6 +326,25 @@ struct tf_dev_ops {
int (*tf_dev_alloc_tbl)(struct tf *tfp,
struct tf_tbl_alloc_parms *parms);
+ /**
+ * Allocation of an SRAM index table type element.
+ *
+ * This API allocates the specified table type element from a
+ * device specific table type DB. The allocated element is
+ * returned.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] parms
+ * Pointer to table allocation parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+ int (*tf_dev_alloc_sram_tbl)(struct tf *tfp,
+ struct tf_tbl_alloc_parms *parms);
/**
* Allocation of a external table type element.
*
@@ -327,7 +383,24 @@ struct tf_dev_ops {
*/
int (*tf_dev_free_tbl)(struct tf *tfp,
struct tf_tbl_free_parms *parms);
-
+ /**
+ * Free of an SRAM table type element.
+ *
+ * This API free's a previous allocated table type element from a
+ * device specific table type DB.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] parms
+ * Pointer to table free parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+ int (*tf_dev_free_sram_tbl)(struct tf *tfp,
+ struct tf_tbl_free_parms *parms);
/**
* Free of a external table type element.
*
@@ -385,6 +458,25 @@ struct tf_dev_ops {
int (*tf_dev_set_ext_tbl)(struct tf *tfp,
struct tf_tbl_set_parms *parms);
+ /**
+ * Sets the specified SRAM table type element.
+ *
+ * This API sets the specified element data by invoking the
+ * firmware.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] parms
+ * Pointer to table set parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+ int (*tf_dev_set_sram_tbl)(struct tf *tfp,
+ struct tf_tbl_set_parms *parms);
+
/**
* Retrieves the specified table type element.
*
@@ -404,6 +496,25 @@ struct tf_dev_ops {
int (*tf_dev_get_tbl)(struct tf *tfp,
struct tf_tbl_get_parms *parms);
+ /**
+ * Retrieves the specified SRAM table type element.
+ *
+ * This API retrieves the specified element data by invoking the
+ * firmware.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] parms
+ * Pointer to table get parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+ int (*tf_dev_get_sram_tbl)(struct tf *tfp,
+ struct tf_tbl_get_parms *parms);
+
/**
* Retrieves the specified table type element using 'bulk'
* mechanism.
@@ -424,6 +535,26 @@ struct tf_dev_ops {
int (*tf_dev_get_bulk_tbl)(struct tf *tfp,
struct tf_tbl_get_bulk_parms *parms);
+ /**
+ * Retrieves the specified SRAM table type element using 'bulk'
+ * mechanism.
+ *
+ * This API retrieves the specified element data by invoking the
+ * firmware.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] parms
+ * Pointer to table get bulk parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+ int (*tf_dev_get_bulk_sram_tbl)(struct tf *tfp,
+ struct tf_tbl_get_bulk_parms *parms);
+
/**
* Gets the increment value to add to the shared session resource
* start offset by for each count in the "stride"
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c
index 2e7ccec123..826cd0cdbc 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.c
@@ -118,14 +118,48 @@ tf_dev_p4_get_resource_str(struct tf *tfp __rte_unused,
}
/**
- * Device specific function that retrieves the WC TCAM slices the
+ * Device specific function that set the WC TCAM slices the
* device supports.
*
* [in] tfp
* Pointer to TF handle
*
- * [out] slice_size
- * Pointer to the WC TCAM slice size
+ * [in] num_slices_per_row
+ * The WC TCAM row slice configuration
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+static int
+tf_dev_p4_set_tcam_slice_info(struct tf *tfp __rte_unused,
+ enum tf_wc_num_slice num_slices_per_row)
+{
+ switch (num_slices_per_row) {
+ case TF_WC_TCAM_1_SLICE_PER_ROW:
+ case TF_WC_TCAM_2_SLICE_PER_ROW:
+ case TF_WC_TCAM_4_SLICE_PER_ROW:
+ g_wc_num_slices_per_row = num_slices_per_row;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/**
+ * Device specific function that retrieves the TCAM slices the
+ * device supports.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] type
+ * TF TCAM type
+ *
+ * [in] key_sz
+ * The key size
*
* [out] num_slices_per_row
* Pointer to the WC TCAM row slice configuration
@@ -141,11 +175,10 @@ tf_dev_p4_get_tcam_slice_info(struct tf *tfp __rte_unused,
uint16_t *num_slices_per_row)
{
/* Single slice support */
-#define CFA_P4_WC_TCAM_SLICES_PER_ROW 1
#define CFA_P4_WC_TCAM_SLICE_SIZE 12
if (type == TF_TCAM_TBL_TYPE_WC_TCAM) {
- *num_slices_per_row = CFA_P4_WC_TCAM_SLICES_PER_ROW;
+ *num_slices_per_row = g_wc_num_slices_per_row;
if (key_sz > *num_slices_per_row * CFA_P4_WC_TCAM_SLICE_SIZE)
return -ENOTSUP;
} else { /* for other type of tcam */
@@ -220,26 +253,51 @@ static int tf_dev_p4_word_align(uint16_t size)
return ((((size) + 31) >> 5) * 4);
}
+/**
+ * Indicates whether the index table type is SRAM managed
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] type
+ * Truflow index table type, e.g. TF_TYPE_FULL_ACT_RECORD
+ *
+ * Returns
+ * - (0) if the table is not managed by the SRAM manager
+ * - (1) if the table is managed by the SRAM manager
+ */
+static bool tf_dev_p4_is_sram_managed(struct tf *tfp __rte_unused,
+ enum tf_tbl_type type __rte_unused)
+{
+ return false;
+}
/**
* Truflow P4 device specific functions
*/
const struct tf_dev_ops tf_dev_ops_p4_init = {
.tf_dev_get_max_types = tf_dev_p4_get_max_types,
.tf_dev_get_resource_str = tf_dev_p4_get_resource_str,
+ .tf_dev_set_tcam_slice_info = tf_dev_p4_set_tcam_slice_info,
.tf_dev_get_tcam_slice_info = tf_dev_p4_get_tcam_slice_info,
.tf_dev_alloc_ident = NULL,
.tf_dev_free_ident = NULL,
.tf_dev_search_ident = NULL,
.tf_dev_get_ident_resc_info = NULL,
.tf_dev_get_tbl_info = NULL,
+ .tf_dev_is_sram_managed = tf_dev_p4_is_sram_managed,
.tf_dev_alloc_ext_tbl = NULL,
.tf_dev_alloc_tbl = NULL,
+ .tf_dev_alloc_sram_tbl = NULL,
.tf_dev_free_ext_tbl = NULL,
.tf_dev_free_tbl = NULL,
+ .tf_dev_free_sram_tbl = NULL,
.tf_dev_set_tbl = NULL,
.tf_dev_set_ext_tbl = NULL,
+ .tf_dev_set_sram_tbl = NULL,
.tf_dev_get_tbl = NULL,
+ .tf_dev_get_sram_tbl = NULL,
.tf_dev_get_bulk_tbl = NULL,
+ .tf_dev_get_bulk_sram_tbl = NULL,
.tf_dev_get_shared_tbl_increment = tf_dev_p4_get_shared_tbl_increment,
.tf_dev_get_tbl_resc_info = NULL,
.tf_dev_alloc_tcam = NULL,
@@ -271,20 +329,27 @@ const struct tf_dev_ops tf_dev_ops_p4_init = {
const struct tf_dev_ops tf_dev_ops_p4 = {
.tf_dev_get_max_types = tf_dev_p4_get_max_types,
.tf_dev_get_resource_str = tf_dev_p4_get_resource_str,
+ .tf_dev_set_tcam_slice_info = tf_dev_p4_set_tcam_slice_info,
.tf_dev_get_tcam_slice_info = tf_dev_p4_get_tcam_slice_info,
.tf_dev_alloc_ident = tf_ident_alloc,
.tf_dev_free_ident = tf_ident_free,
.tf_dev_search_ident = tf_ident_search,
.tf_dev_get_ident_resc_info = tf_ident_get_resc_info,
.tf_dev_get_tbl_info = NULL,
+ .tf_dev_is_sram_managed = tf_dev_p4_is_sram_managed,
.tf_dev_alloc_tbl = tf_tbl_alloc,
.tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc,
+ .tf_dev_alloc_sram_tbl = tf_tbl_alloc,
.tf_dev_free_tbl = tf_tbl_free,
.tf_dev_free_ext_tbl = tf_tbl_ext_free,
+ .tf_dev_free_sram_tbl = tf_tbl_free,
.tf_dev_set_tbl = tf_tbl_set,
.tf_dev_set_ext_tbl = tf_tbl_ext_common_set,
+ .tf_dev_set_sram_tbl = NULL,
.tf_dev_get_tbl = tf_tbl_get,
+ .tf_dev_get_sram_tbl = NULL,
.tf_dev_get_bulk_tbl = tf_tbl_bulk_get,
+ .tf_dev_get_bulk_sram_tbl = NULL,
.tf_dev_get_shared_tbl_increment = tf_dev_p4_get_shared_tbl_increment,
.tf_dev_get_tbl_resc_info = tf_tbl_get_resc_info,
#ifdef TF_TCAM_SHARED
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h
index a73ba3cd70..c1357913f1 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.h
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.h
@@ -15,101 +15,101 @@
struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = {
[TF_IDENT_TYPE_L2_CTXT_HIGH] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_L2_CTXT_LOW] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_PROF_FUNC] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_FUNC,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_WC_PROF] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_EM_PROF] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_EM_PROF_ID,
- 0, 0, 0
+ 0, 0
},
};
struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = {
[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_PROF_TCAM] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_TCAM,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_WC_TCAM] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_SP_TCAM] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_TCAM,
- 0, 0, 0
+ 0, 0
},
};
struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = {
[TF_TBL_TYPE_FULL_ACT_RECORD] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_MCAST_GROUPS] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_ENCAP_8B] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_ENCAP_16B] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_ENCAP_64B] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_SP_SMAC] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_STATS_64] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_MODIFY_IPV4] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_METER_PROF] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_METER_INST] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_MIRROR_CONFIG] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR,
- 0, 0, 0
+ 0, 0
},
};
@@ -117,14 +117,14 @@ struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = {
struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = {
[TF_EM_TBL_TYPE_TBL_SCOPE] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_TBL_SCOPE,
- 0, 0, 0
+ 0, 0
},
};
struct tf_rm_element_cfg tf_em_int_p4[TF_EM_TBL_TYPE_MAX] = {
[TF_EM_TBL_TYPE_EM_RECORD] = {
TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_EM_REC,
- 0, 0, 0
+ 0, 0
},
};
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c
index a492c62bff..47d7836a58 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.c
@@ -17,6 +17,7 @@
#include "tf_if_tbl.h"
#include "tfp.h"
#include "tf_msg_common.h"
+#include "tf_tbl_sram.h"
#define TF_DEV_P58_PARIF_MAX 16
#define TF_DEV_P58_PF_MASK 0xfUL
@@ -105,14 +106,48 @@ tf_dev_p58_get_resource_str(struct tf *tfp __rte_unused,
}
/**
- * Device specific function that retrieves the WC TCAM slices the
+ * Device specific function that set the WC TCAM slices the
* device supports.
*
* [in] tfp
* Pointer to TF handle
*
- * [out] slice_size
- * Pointer to the WC TCAM slice size
+ * [in] num_slices_per_row
+ * The WC TCAM row slice configuration
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+static int
+tf_dev_p58_set_tcam_slice_info(struct tf *tfp __rte_unused,
+ enum tf_wc_num_slice num_slices_per_row)
+{
+ switch (num_slices_per_row) {
+ case TF_WC_TCAM_1_SLICE_PER_ROW:
+ case TF_WC_TCAM_2_SLICE_PER_ROW:
+ case TF_WC_TCAM_4_SLICE_PER_ROW:
+ g_wc_num_slices_per_row = num_slices_per_row;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/**
+ * Device specific function that retrieves the TCAM slices the
+ * device supports.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] type
+ * TF TCAM type
+ *
+ * [in] key_sz
+ * The key size
*
* [out] num_slices_per_row
* Pointer to the WC TCAM row slice configuration
@@ -123,16 +158,13 @@ tf_dev_p58_get_resource_str(struct tf *tfp __rte_unused,
*/
static int
tf_dev_p58_get_tcam_slice_info(struct tf *tfp __rte_unused,
- enum tf_tcam_tbl_type type,
- uint16_t key_sz,
- uint16_t *num_slices_per_row)
+ enum tf_tcam_tbl_type type,
+ uint16_t key_sz,
+ uint16_t *num_slices_per_row)
{
-#define CFA_P58_WC_TCAM_SLICES_PER_ROW 1
#define CFA_P58_WC_TCAM_SLICE_SIZE 24
-
if (type == TF_TCAM_TBL_TYPE_WC_TCAM) {
- /* only support single slice key size now */
- *num_slices_per_row = CFA_P58_WC_TCAM_SLICES_PER_ROW;
+ *num_slices_per_row = g_wc_num_slices_per_row;
if (key_sz > *num_slices_per_row * CFA_P58_WC_TCAM_SLICE_SIZE)
return -ENOTSUP;
} else { /* for other type of tcam */
@@ -194,6 +226,44 @@ static int tf_dev_p58_get_shared_tbl_increment(struct tf *tfp __rte_unused,
return 0;
}
+/**
+ * Indicates whether the index table type is SRAM managed
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] type
+ * Truflow index table type, e.g. TF_TYPE_FULL_ACT_RECORD
+ *
+ * Returns
+ * - (0) if the table is not managed by the SRAM manager
+ * - (1) if the table is managed by the SRAM manager
+ */
+static bool tf_dev_p58_is_sram_managed(struct tf *tfp __rte_unused,
+ enum tf_tbl_type type)
+{
+ switch (type) {
+ case TF_TBL_TYPE_FULL_ACT_RECORD:
+ case TF_TBL_TYPE_COMPACT_ACT_RECORD:
+ case TF_TBL_TYPE_ACT_ENCAP_8B:
+ case TF_TBL_TYPE_ACT_ENCAP_16B:
+ case TF_TBL_TYPE_ACT_ENCAP_32B:
+ case TF_TBL_TYPE_ACT_ENCAP_64B:
+ case TF_TBL_TYPE_ACT_SP_SMAC:
+ case TF_TBL_TYPE_ACT_SP_SMAC_IPV4:
+ case TF_TBL_TYPE_ACT_SP_SMAC_IPV6:
+ case TF_TBL_TYPE_ACT_STATS_64:
+ case TF_TBL_TYPE_ACT_MODIFY_IPV4:
+ case TF_TBL_TYPE_ACT_MODIFY_8B:
+ case TF_TBL_TYPE_ACT_MODIFY_16B:
+ case TF_TBL_TYPE_ACT_MODIFY_32B:
+ case TF_TBL_TYPE_ACT_MODIFY_64B:
+ return true;
+ default:
+ return false;
+ }
+}
+
#define TF_DEV_P58_BANK_SZ_64B 2048
/**
* Get SRAM table information.
@@ -265,26 +335,34 @@ static int tf_dev_p58_get_sram_tbl_info(struct tf *tfp __rte_unused,
}
return 0;
}
+
/**
* Truflow P58 device specific functions
*/
const struct tf_dev_ops tf_dev_ops_p58_init = {
.tf_dev_get_max_types = tf_dev_p58_get_max_types,
.tf_dev_get_resource_str = tf_dev_p58_get_resource_str,
+ .tf_dev_set_tcam_slice_info = tf_dev_p58_set_tcam_slice_info,
.tf_dev_get_tcam_slice_info = tf_dev_p58_get_tcam_slice_info,
.tf_dev_alloc_ident = NULL,
.tf_dev_free_ident = NULL,
.tf_dev_search_ident = NULL,
.tf_dev_get_ident_resc_info = NULL,
.tf_dev_get_tbl_info = NULL,
+ .tf_dev_is_sram_managed = tf_dev_p58_is_sram_managed,
.tf_dev_alloc_ext_tbl = NULL,
.tf_dev_alloc_tbl = NULL,
+ .tf_dev_alloc_sram_tbl = NULL,
.tf_dev_free_ext_tbl = NULL,
.tf_dev_free_tbl = NULL,
+ .tf_dev_free_sram_tbl = NULL,
.tf_dev_set_tbl = NULL,
.tf_dev_set_ext_tbl = NULL,
+ .tf_dev_set_sram_tbl = NULL,
.tf_dev_get_tbl = NULL,
+ .tf_dev_get_sram_tbl = NULL,
.tf_dev_get_bulk_tbl = NULL,
+ .tf_dev_get_bulk_sram_tbl = NULL,
.tf_dev_get_shared_tbl_increment = tf_dev_p58_get_shared_tbl_increment,
.tf_dev_get_tbl_resc_info = NULL,
.tf_dev_alloc_tcam = NULL,
@@ -316,20 +394,27 @@ const struct tf_dev_ops tf_dev_ops_p58_init = {
const struct tf_dev_ops tf_dev_ops_p58 = {
.tf_dev_get_max_types = tf_dev_p58_get_max_types,
.tf_dev_get_resource_str = tf_dev_p58_get_resource_str,
+ .tf_dev_set_tcam_slice_info = tf_dev_p58_set_tcam_slice_info,
.tf_dev_get_tcam_slice_info = tf_dev_p58_get_tcam_slice_info,
.tf_dev_alloc_ident = tf_ident_alloc,
.tf_dev_free_ident = tf_ident_free,
.tf_dev_search_ident = tf_ident_search,
.tf_dev_get_ident_resc_info = tf_ident_get_resc_info,
+ .tf_dev_is_sram_managed = tf_dev_p58_is_sram_managed,
.tf_dev_get_tbl_info = tf_dev_p58_get_sram_tbl_info,
.tf_dev_alloc_tbl = tf_tbl_alloc,
+ .tf_dev_alloc_sram_tbl = tf_tbl_sram_alloc,
.tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc,
.tf_dev_free_tbl = tf_tbl_free,
.tf_dev_free_ext_tbl = tf_tbl_ext_free,
+ .tf_dev_free_sram_tbl = tf_tbl_sram_free,
.tf_dev_set_tbl = tf_tbl_set,
.tf_dev_set_ext_tbl = tf_tbl_ext_common_set,
+ .tf_dev_set_sram_tbl = tf_tbl_sram_set,
.tf_dev_get_tbl = tf_tbl_get,
+ .tf_dev_get_sram_tbl = tf_tbl_sram_get,
.tf_dev_get_bulk_tbl = tf_tbl_bulk_get,
+ .tf_dev_get_bulk_sram_tbl = tf_tbl_sram_bulk_get,
.tf_dev_get_shared_tbl_increment = tf_dev_p58_get_shared_tbl_increment,
.tf_dev_get_tbl_resc_info = tf_tbl_get_resc_info,
#ifdef TF_TCAM_SHARED
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h
index 8c2e07aa34..3e8759f2df 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.h
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.h
@@ -15,107 +15,107 @@
struct tf_rm_element_cfg tf_ident_p58[TF_IDENT_TYPE_MAX] = {
[TF_IDENT_TYPE_L2_CTXT_HIGH] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_L2_CTXT_LOW] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_PROF_FUNC] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_PROF_FUNC,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_WC_PROF] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_EM_PROF] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_PROF_ID,
- 0, 0, 0
+ 0, 0
},
};
struct tf_rm_element_cfg tf_tcam_p58[TF_TCAM_TBL_TYPE_MAX] = {
[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_PROF_TCAM] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_PROF_TCAM,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_WC_TCAM] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_TCAM,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_VEB_TCAM] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_VEB_TCAM,
- 0, 0, 0
+ 0, 0
},
};
struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = {
[TF_TBL_TYPE_EM_FKB] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_WC_FKB] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_METER_PROF] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_METER_INST] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_METER_DROP_CNT] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_MIRROR_CONFIG] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_METADATA] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA,
- 0, 0, 0
+ 0, 0
},
/* Policy - ARs in bank 1 */
[TF_TBL_TYPE_FULL_ACT_RECORD] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
- .slices = 1,
+ .slices = 4,
},
[TF_TBL_TYPE_COMPACT_ACT_RECORD] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
- .slices = 1,
+ .slices = 8,
},
/* Policy - Encaps in bank 2 */
[TF_TBL_TYPE_ACT_ENCAP_8B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 1,
+ .slices = 8,
},
[TF_TBL_TYPE_ACT_ENCAP_16B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 1,
+ .slices = 4,
},
[TF_TBL_TYPE_ACT_ENCAP_32B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 1,
+ .slices = 2,
},
[TF_TBL_TYPE_ACT_ENCAP_64B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
@@ -128,19 +128,19 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 1,
+ .slices = 8,
},
[TF_TBL_TYPE_ACT_MODIFY_16B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 1,
+ .slices = 4,
},
[TF_TBL_TYPE_ACT_MODIFY_32B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 1,
+ .slices = 2,
},
[TF_TBL_TYPE_ACT_MODIFY_64B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
@@ -152,32 +152,32 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = {
[TF_TBL_TYPE_ACT_SP_SMAC] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
- .slices = 1,
+ .slices = 8,
},
[TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
- .slices = 1,
+ .slices = 4,
},
[TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
- .slices = 1,
+ .slices = 2,
},
/* Policy - Stats in bank 3 */
[TF_TBL_TYPE_ACT_STATS_64] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3,
- .slices = 1,
+ .slices = 8,
},
};
struct tf_rm_element_cfg tf_em_int_p58[TF_EM_TBL_TYPE_MAX] = {
[TF_EM_TBL_TYPE_EM_RECORD] = {
TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P58_EM_REC,
- 0, 0, 0
+ 0, 0
},
};
diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c
index e07d9168be..0fbb2fe837 100644
--- a/drivers/net/bnxt/tf_core/tf_msg.c
+++ b/drivers/net/bnxt/tf_core/tf_msg.c
@@ -2231,7 +2231,7 @@ tf_msg_get_if_tbl_entry(struct tf *tfp,
if (rc != 0)
return rc;
- tfp_memcpy(params->data, resp.data, req.size);
+ tfp_memcpy(¶ms->data[0], resp.data, req.size);
return 0;
}
diff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c
index 0a46e2a343..03c958a7d6 100644
--- a/drivers/net/bnxt/tf_core/tf_rm.c
+++ b/drivers/net/bnxt/tf_core/tf_rm.c
@@ -34,6 +34,12 @@ struct tf_rm_element {
*/
uint16_t hcapi_type;
+ /**
+ * Resource slices. How many slices will fit in the
+ * resource pool chunk size.
+ */
+ uint8_t slices;
+
/**
* HCAPI RM allocated range information for the element.
*/
@@ -356,12 +362,15 @@ tf_rm_check_residuals(struct tf_rm_new_db *rm_db,
* - - Failure if negative
*/
static int
-tf_rm_update_parent_reservations(struct tf_rm_element_cfg *cfg,
+tf_rm_update_parent_reservations(struct tf *tfp,
+ struct tf_dev_info *dev,
+ struct tf_rm_element_cfg *cfg,
uint16_t *alloc_cnt,
uint16_t num_elements,
uint16_t *req_cnt)
{
int parent, child;
+ const char *type_str;
/* Search through all the elements */
for (parent = 0; parent < num_elements; parent++) {
@@ -377,15 +386,25 @@ tf_rm_update_parent_reservations(struct tf_rm_element_cfg *cfg,
if (alloc_cnt[parent] % cfg[parent].slices)
combined_cnt++;
+ if (alloc_cnt[parent]) {
+ dev->ops->tf_dev_get_resource_str(tfp,
+ cfg[parent].hcapi_type,
+ &type_str);
+ }
+
/* Search again through all the elements */
for (child = 0; child < num_elements; child++) {
/* If this is one of my children */
if (cfg[child].cfg_type ==
TF_RM_ELEM_CFG_HCAPI_BA_CHILD &&
- cfg[child].parent_subtype == parent) {
+ cfg[child].parent_subtype == parent &&
+ alloc_cnt[child]) {
uint16_t cnt = 0;
RTE_ASSERT(cfg[child].slices);
+ dev->ops->tf_dev_get_resource_str(tfp,
+ cfg[child].hcapi_type,
+ &type_str);
/* Increment the parents combined count
* with each child's count adjusted for
* number of slices per RM allocated item.
@@ -479,7 +498,7 @@ tf_rm_create_db(struct tf *tfp,
/* Update the req_cnt based upon the element configuration
*/
- tf_rm_update_parent_reservations(parms->cfg,
+ tf_rm_update_parent_reservations(tfp, dev, parms->cfg,
parms->alloc_cnt,
parms->num_elements,
req_cnt);
@@ -594,6 +613,7 @@ tf_rm_create_db(struct tf *tfp,
db[i].cfg_type = cfg->cfg_type;
db[i].hcapi_type = cfg->hcapi_type;
+ db[i].slices = cfg->slices;
/* Save the parent subtype for later use to find the pool
*/
@@ -1271,6 +1291,26 @@ tf_rm_get_hcapi_type(struct tf_rm_get_hcapi_parms *parms)
return 0;
}
+int
+tf_rm_get_slices(struct tf_rm_get_slices_parms *parms)
+{
+ struct tf_rm_new_db *rm_db;
+ enum tf_rm_elem_cfg_type cfg_type;
+
+ TF_CHECK_PARMS2(parms, parms->rm_db);
+ rm_db = (struct tf_rm_new_db *)parms->rm_db;
+ TF_CHECK_PARMS1(rm_db->db);
+
+ cfg_type = rm_db->db[parms->subtype].cfg_type;
+
+ /* Bail out if not controlled by HCAPI */
+ if (cfg_type == TF_RM_ELEM_CFG_NULL)
+ return -ENOTSUP;
+
+ *parms->slices = rm_db->db[parms->subtype].slices;
+
+ return 0;
+}
int
tf_rm_get_inuse_count(struct tf_rm_get_inuse_count_parms *parms)
diff --git a/drivers/net/bnxt/tf_core/tf_rm.h b/drivers/net/bnxt/tf_core/tf_rm.h
index 8b984112e8..da7d0c7211 100644
--- a/drivers/net/bnxt/tf_core/tf_rm.h
+++ b/drivers/net/bnxt/tf_core/tf_rm.h
@@ -43,16 +43,6 @@ struct tf;
* support module, not called directly.
*/
-/**
- * Resource reservation single entry result. Used when accessing HCAPI
- * RM on the firmware.
- */
-struct tf_rm_new_entry {
- /** Starting index of the allocated resource */
- uint16_t start;
- /** Number of allocated elements */
- uint16_t stride;
-};
/**
* RM Element configuration enumeration. Used by the Device to
@@ -114,10 +104,6 @@ struct tf_rm_element_cfg {
*/
enum tf_rm_elem_cfg_type cfg_type;
- /* If a HCAPI to TF type conversion is required then TF type
- * can be added here.
- */
-
/**
* HCAPI RM Type for the element. Used for TF to HCAPI type
* conversion.
@@ -125,28 +111,19 @@ struct tf_rm_element_cfg {
uint16_t hcapi_type;
/**
- * if cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_CHILD
+ * if cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_CHILD/PARENT
*
* Parent Truflow module subtype associated with this resource type.
*/
uint16_t parent_subtype;
/**
- * if cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_CHILD
+ * if cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_CHILD/PARENT
*
* Resource slices. How many slices will fit in the
* resource pool chunk size.
*/
uint8_t slices;
-
- /**
- * Pool element divider count
- * If 0 or 1, there is 1:1 correspondence between the RM
- * BA pool resource element and the HCAPI RM firmware
- * resource. If > 1, the RM BA pool element has a 1:n
- * correspondence to the HCAPI RM firmware resource.
- */
- uint8_t divider;
};
/**
@@ -160,7 +137,7 @@ struct tf_rm_alloc_info {
* In case of dynamic allocation support this would have
* to be changed to linked list of tf_rm_entry instead.
*/
- struct tf_rm_new_entry entry;
+ struct tf_resource_info entry;
};
/**
@@ -331,6 +308,25 @@ struct tf_rm_get_hcapi_parms {
*/
uint16_t *hcapi_type;
};
+/**
+ * Get Slices parameters for a single element
+ */
+struct tf_rm_get_slices_parms {
+ /**
+ * [in] RM DB Handle
+ */
+ void *rm_db;
+ /**
+ * [in] TF subtype indicates which DB entry to perform the
+ * action on. (e.g. TF_TBL_TYPE_FULL_ACTION subtype of module
+ * TF_MODULE_TYPE_TABLE)
+ */
+ uint16_t subtype;
+ /**
+ * [in/out] Pointer to number of slices for the given type
+ */
+ uint16_t *slices;
+};
/**
* Get InUse count parameters for single element
@@ -394,6 +390,8 @@ struct tf_rm_check_indexes_in_range_parms {
* @ref tf_rm_get_hcapi_type
*
* @ref tf_rm_get_inuse_count
+ *
+ * @ref tf_rm_get_slice_size
*/
/**
@@ -571,5 +569,17 @@ int tf_rm_get_inuse_count(struct tf_rm_get_inuse_count_parms *parms);
int
tf_rm_check_indexes_in_range(struct tf_rm_check_indexes_in_range_parms *parms);
+/**
+ * Get the number of slices per resource bit allocator for the resource type
+ *
+ * [in] parms
+ * Pointer to get inuse parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int
+tf_rm_get_slices(struct tf_rm_get_slices_parms *parms);
#endif /* TF_RM_NEW_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_session.c b/drivers/net/bnxt/tf_core/tf_session.c
index 90b65c59e6..3e6664e9f2 100644
--- a/drivers/net/bnxt/tf_core/tf_session.c
+++ b/drivers/net/bnxt/tf_core/tf_session.c
@@ -202,6 +202,7 @@ tf_session_create(struct tf *tfp,
parms->open_cfg->device_type,
session->shadow_copy,
&parms->open_cfg->resources,
+ parms->open_cfg->wc_num_slices,
&session->dev);
/* Logging handled by dev_bind */
@@ -705,6 +706,22 @@ tf_session_get_session(struct tf *tfp,
return rc;
}
+int tf_session_get(struct tf *tfp,
+ struct tf_session **tfs,
+ struct tf_dev_info **tfd)
+{
+ int rc;
+ rc = tf_session_get_session_internal(tfp, tfs);
+
+ /* Logging done by tf_session_get_session_internal */
+ if (rc)
+ return rc;
+
+ rc = tf_session_get_device(*tfs, tfd);
+
+ return rc;
+}
+
struct tf_session_client *
tf_session_get_session_client(struct tf_session *tfs,
union tf_session_client_id session_client_id)
@@ -1012,4 +1029,43 @@ tf_session_set_tcam_shared_db(struct tf *tfp,
tfs->tcam_shared_db_handle = tcam_shared_db_handle;
return rc;
}
+
+int
+tf_session_get_sram_db(struct tf *tfp,
+ void **sram_handle)
+{
+ struct tf_session *tfs = NULL;
+ int rc = 0;
+
+ *sram_handle = NULL;
+
+ if (tfp == NULL)
+ return (-EINVAL);
+
+ rc = tf_session_get_session_internal(tfp, &tfs);
+ if (rc)
+ return rc;
+
+ *sram_handle = tfs->sram_handle;
+ return rc;
+}
+
+int
+tf_session_set_sram_db(struct tf *tfp,
+ void *sram_handle)
+{
+ struct tf_session *tfs = NULL;
+ int rc = 0;
+
+ if (tfp == NULL)
+ return (-EINVAL);
+
+ rc = tf_session_get_session_internal(tfp, &tfs);
+ if (rc)
+ return rc;
+
+ tfs->sram_handle = sram_handle;
+ return rc;
+}
+
#endif /* TF_TCAM_SHARED */
diff --git a/drivers/net/bnxt/tf_core/tf_session.h b/drivers/net/bnxt/tf_core/tf_session.h
index d68421cd13..c1d7f70060 100644
--- a/drivers/net/bnxt/tf_core/tf_session.h
+++ b/drivers/net/bnxt/tf_core/tf_session.h
@@ -166,6 +166,10 @@ struct tf_session {
*/
void *tcam_shared_db_handle;
#endif /* TF_TCAM_SHARED */
+ /**
+ * SRAM db reference for the session
+ */
+ void *sram_handle;
};
/**
@@ -278,6 +282,10 @@ struct tf_session_close_session_parms {
*
* @ref tf_session_set_tcam_shared_db
* #endif
+ *
+ * @ref tf_session_get_sram_db
+ *
+ * @ref tf_session_set_sram_db
*/
/**
@@ -435,11 +443,11 @@ tf_session_find_session_client_by_fid(struct tf_session *tfs,
/**
* Looks up the device information from the TF Session.
*
- * [in] tfp
- * Pointer to TF handle
+ * [in] tfs
+ * Pointer to session handle
*
* [out] tfd
- * Pointer pointer to the device
+ * Pointer to the device
*
* Returns
* - (0) if successful.
@@ -448,6 +456,26 @@ tf_session_find_session_client_by_fid(struct tf_session *tfs,
int tf_session_get_device(struct tf_session *tfs,
struct tf_dev_info **tfd);
+/**
+ * Returns the session and the device from the tfp.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [out] tfs
+ * Pointer to the session
+ *
+ * [out] tfd
+ * Pointer to the device
+
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_session_get(struct tf *tfp,
+ struct tf_session **tfs,
+ struct tf_dev_info **tfd);
+
/**
* Looks up the FW Session id the requested TF handle.
*
@@ -614,4 +642,28 @@ int
tf_session_get_tcam_shared_db(struct tf *tfp,
void **tcam_shared_db_handle);
+/**
+ * Set the pointer to the SRAM database
+ *
+ * [in] session, pointer to the session
+ *
+ * Returns:
+ * - the pointer to the parent bnxt struct
+ */
+int
+tf_session_set_sram_db(struct tf *tfp,
+ void *sram_handle);
+
+/**
+ * Get the pointer to the SRAM database
+ *
+ * [in] session, pointer to the session
+ *
+ * Returns:
+ * - the pointer to the parent bnxt struct
+ */
+int
+tf_session_get_sram_db(struct tf *tfp,
+ void **sram_handle);
+
#endif /* _TF_SESSION_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_sram_mgr.c b/drivers/net/bnxt/tf_core/tf_sram_mgr.c
new file mode 100644
index 0000000000..f633a78b25
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/tf_sram_mgr.c
@@ -0,0 +1,971 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019-2021 Broadcom
+ * All rights reserved.
+ */
+#include <stdlib.h>
+#include <stdio.h>
+#include "tf_sram_mgr.h"
+#include "tf_core.h"
+#include "tf_rm.h"
+#include "tf_common.h"
+#include "assert.h"
+#include "tf_util.h"
+#include "tfp.h"
+#if (STATS_CLEAR_ON_READ_SUPPORT == 0)
+#include "tf_msg.h"
+#endif
+/***************************
+ * Internal Data Structures
+ ***************************/
+
+/**
+ * TF SRAM block info
+ *
+ * Contains all the information about a particular 64B SRAM
+ * block and the slices within it.
+ */
+struct tf_sram_block {
+ /* Previous block
+ */
+ struct tf_sram_block *prev;
+ /* Next block
+ */
+ struct tf_sram_block *next;
+
+ /** Bitmap indicating which slices are in use
+ * If a bit is set, it indicates the slice
+ * in the row is in use.
+ */
+ uint8_t in_use_mask;
+
+ /** Block id - this is a 64B offset
+ */
+ uint16_t block_id;
+};
+
+/**
+ * TF SRAM block list
+ *
+ * List of 64B SRAM blocks used for fixed size slices (8, 16, 32, 64B)
+ */
+struct tf_sram_slice_list {
+ /** Pointer to head of linked list of blocks.
+ */
+ struct tf_sram_block *head;
+
+ /** Pointer to tail of linked list of blocks.
+ */
+ struct tf_sram_block *tail;
+
+ /** Total count of blocks
+ */
+ uint32_t cnt;
+
+ /** First non-full block in the list
+ */
+ struct tf_sram_block *first_not_full_block;
+
+ /** Entry slice size for this list
+ */
+ enum tf_sram_slice_size size;
+};
+
+
+/**
+ * TF SRAM bank info consists of lists of different slice sizes per bank
+ */
+struct tf_sram_bank_info {
+ struct tf_sram_slice_list slice[TF_SRAM_SLICE_SIZE_MAX];
+};
+
+/**
+ * SRAM banks consist of SRAM bank information
+ */
+struct tf_sram_bank {
+ struct tf_sram_bank_info bank[TF_SRAM_BANK_ID_MAX];
+};
+
+/**
+ * SRAM banks consist of SRAM bank information
+ */
+struct tf_sram {
+ struct tf_sram_bank dir[TF_DIR_MAX];
+};
+
+/**********************
+ * Internal functions
+ **********************/
+
+/**
+ * Get slice size in string format
+ */
+const char
+*tf_sram_slice_2_str(enum tf_sram_slice_size slice_size)
+{
+ switch (slice_size) {
+ case TF_SRAM_SLICE_SIZE_8B:
+ return "8B slice";
+ case TF_SRAM_SLICE_SIZE_16B:
+ return "16B slice";
+ case TF_SRAM_SLICE_SIZE_32B:
+ return "32B slice";
+ case TF_SRAM_SLICE_SIZE_64B:
+ return "64B slice";
+ default:
+ return "Invalid slice size";
+ }
+}
+
+/**
+ * Get bank in string format
+ */
+const char
+*tf_sram_bank_2_str(enum tf_sram_bank_id bank_id)
+{
+ switch (bank_id) {
+ case TF_SRAM_BANK_ID_0:
+ return "bank_0";
+ case TF_SRAM_BANK_ID_1:
+ return "bank_1";
+ case TF_SRAM_BANK_ID_2:
+ return "bank_2";
+ case TF_SRAM_BANK_ID_3:
+ return "bank_3";
+ default:
+ return "Invalid bank_id";
+ }
+}
+
+/**
+ * TF SRAM get slice list
+ */
+static int
+tf_sram_get_slice_list(struct tf_sram *sram,
+ struct tf_sram_slice_list **slice_list,
+ enum tf_sram_slice_size slice_size,
+ enum tf_dir dir,
+ enum tf_sram_bank_id bank_id)
+{
+ int rc = 0;
+
+ TF_CHECK_PARMS2(sram, slice_list);
+
+ *slice_list = &sram->dir[dir].bank[bank_id].slice[slice_size];
+
+ return rc;
+}
+
+uint16_t tf_sram_bank_2_base_offset[TF_SRAM_BANK_ID_MAX] = {
+ 0,
+ 2048,
+ 4096,
+ 6144
+};
+
+/**
+ * Translate a block id and bank_id to an 8B offset
+ */
+static void
+tf_sram_block_id_2_offset(enum tf_sram_bank_id bank_id, uint16_t block_id,
+ uint16_t *offset)
+{
+ *offset = (block_id + tf_sram_bank_2_base_offset[bank_id]) << 3;
+}
+
+/**
+ * Translates an 8B offset and bank_id to a block_id
+ */
+static void
+tf_sram_offset_2_block_id(enum tf_sram_bank_id bank_id, uint16_t offset,
+ uint16_t *block_id, uint16_t *slice_offset)
+{
+ *slice_offset = offset & 0x7;
+ *block_id = ((offset & ~0x7) >> 3) -
+ tf_sram_bank_2_base_offset[bank_id];
+}
+
+/**
+ * Find a matching block_id within the slice list
+ */
+static struct tf_sram_block
+*tf_sram_find_block(uint16_t block_id, struct tf_sram_slice_list *slice_list)
+{
+ uint32_t cnt;
+ struct tf_sram_block *block;
+
+ cnt = slice_list->cnt;
+ block = slice_list->head;
+
+ while (cnt > 0 && block) {
+ if (block->block_id == block_id)
+ return block;
+ block = block->next;
+ cnt--;
+ }
+ return NULL;
+}
+
+/**
+ * Given the current block get the next block within the slice list
+ *
+ * List is not changed.
+ */
+static struct tf_sram_block
+*tf_sram_get_next_block(struct tf_sram_block *block)
+{
+ struct tf_sram_block *nblock;
+
+ if (block != NULL)
+ nblock = block->next;
+ else
+ nblock = NULL;
+ return nblock;
+}
+
+/**
+ * Free an allocated slice from a block and if the block is empty,
+ * return an indication so that the block can be freed.
+ */
+static int
+tf_sram_free_slice(enum tf_sram_slice_size slice_size,
+ uint16_t slice_offset, struct tf_sram_block *block,
+ bool *block_is_empty)
+{
+ int rc = 0;
+ uint8_t shift;
+ uint8_t slice_mask = 0;
+
+ TF_CHECK_PARMS2(block, block_is_empty);
+
+ switch (slice_size) {
+ case TF_SRAM_SLICE_SIZE_8B:
+ shift = slice_offset >> 0;
+ assert(shift < 8);
+ slice_mask = 1 << shift;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_16B:
+ shift = slice_offset >> 1;
+ assert(shift < 4);
+ slice_mask = 1 << shift;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_32B:
+ shift = slice_offset >> 2;
+ assert(shift < 2);
+ slice_mask = 1 << shift;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_64B:
+ default:
+ shift = slice_offset >> 0;
+ assert(shift < 1);
+ slice_mask = 1 << shift;
+ break;
+ }
+
+ if ((block->in_use_mask & slice_mask) == 0) {
+ rc = -EINVAL;
+ TFP_DRV_LOG(ERR, "block_id(0x%x) slice(%d) was not allocated\n",
+ block->block_id, slice_offset);
+ return rc;
+ }
+
+ block->in_use_mask &= ~slice_mask;
+
+ if (block->in_use_mask == 0)
+ *block_is_empty = true;
+ else
+ *block_is_empty = false;
+
+ return rc;
+}
+
+/**
+ * TF SRAM get next slice
+ *
+ * Gets the next slice_offset available in the block
+ * and updates the in_use_mask.
+ */
+static int
+tf_sram_get_next_slice_in_block(struct tf_sram_block *block,
+ enum tf_sram_slice_size slice_size,
+ uint16_t *slice_offset,
+ bool *block_is_full)
+{
+ int rc, free_id = -1;
+ uint8_t shift, max_slices, mask, i, full_mask;
+
+ TF_CHECK_PARMS3(block, slice_offset, block_is_full);
+
+ switch (slice_size) {
+ case TF_SRAM_SLICE_SIZE_8B:
+ shift = 0;
+ max_slices = 8;
+ full_mask = 0xff;
+ break;
+ case TF_SRAM_SLICE_SIZE_16B:
+ shift = 1;
+ max_slices = 4;
+ full_mask = 0xf;
+ break;
+ case TF_SRAM_SLICE_SIZE_32B:
+ shift = 2;
+ max_slices = 2;
+ full_mask = 0x3;
+ break;
+ case TF_SRAM_SLICE_SIZE_64B:
+ default:
+ shift = 0;
+ max_slices = 1;
+ full_mask = 1;
+ break;
+ }
+
+ mask = block->in_use_mask;
+
+ for (i = 0; i < max_slices; i++) {
+ if ((mask & 1) == 0) {
+ free_id = i;
+ block->in_use_mask |= 1 << free_id;
+ break;
+ }
+ mask = mask >> 1;
+ }
+
+ if (block->in_use_mask == full_mask)
+ *block_is_full = true;
+ else
+ *block_is_full = false;
+
+
+ if (free_id >= 0) {
+ *slice_offset = free_id << shift;
+ rc = 0;
+ } else {
+ *slice_offset = 0;
+ rc = -ENOMEM;
+ }
+
+ return rc;
+}
+
+/**
+ * TF SRAM get indication as to whether the slice offset is
+ * allocated in the block.
+ *
+ */
+static int
+tf_sram_is_slice_allocated_in_block(struct tf_sram_block *block,
+ enum tf_sram_slice_size slice_size,
+ uint16_t slice_offset,
+ bool *is_allocated)
+{
+ int rc = 0;
+ uint8_t shift;
+ uint8_t slice_mask = 0;
+
+ TF_CHECK_PARMS2(block, is_allocated);
+
+ *is_allocated = false;
+
+ switch (slice_size) {
+ case TF_SRAM_SLICE_SIZE_8B:
+ shift = slice_offset >> 0;
+ assert(shift < 8);
+ slice_mask = 1 << shift;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_16B:
+ shift = slice_offset >> 1;
+ assert(shift < 4);
+ slice_mask = 1 << shift;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_32B:
+ shift = slice_offset >> 2;
+ assert(shift < 2);
+ slice_mask = 1 << shift;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_64B:
+ default:
+ shift = slice_offset >> 0;
+ assert(shift < 1);
+ slice_mask = 1 << shift;
+ break;
+ }
+
+ if ((block->in_use_mask & slice_mask) == 0) {
+ TFP_DRV_LOG(ERR, "block_id(0x%x) slice(%d) was not allocated\n",
+ block->block_id, slice_offset);
+ *is_allocated = false;
+ } else {
+ *is_allocated = true;
+ }
+
+ return rc;
+}
+
+/**
+ * Initialize slice list
+ */
+static void
+tf_sram_init_slice_list(struct tf_sram_slice_list *slice_list,
+ enum tf_sram_slice_size slice_size)
+{
+ slice_list->head = NULL;
+ slice_list->tail = NULL;
+ slice_list->cnt = 0;
+ slice_list->size = slice_size;
+}
+
+/**
+ * Get the block count
+ */
+static uint32_t
+tf_sram_get_block_cnt(struct tf_sram_slice_list *slice_list)
+{
+ return slice_list->cnt;
+}
+
+
+/**
+ * Free a block data structure - does not free to the RM
+ */
+static void
+tf_sram_free_block(struct tf_sram_slice_list *slice_list,
+ struct tf_sram_block *block)
+{
+ if (slice_list->head == block && slice_list->tail == block) {
+ slice_list->head = NULL;
+ slice_list->tail = NULL;
+ } else if (slice_list->head == block) {
+ slice_list->head = block->next;
+ slice_list->head->prev = NULL;
+ } else if (slice_list->tail == block) {
+ slice_list->tail = block->prev;
+ slice_list->tail->next = NULL;
+ } else {
+ block->prev->next = block->next;
+ block->next->prev = block->prev;
+ }
+ tfp_free(block);
+ slice_list->cnt--;
+}
+/**
+ * Free the entire slice_list
+ */
+static void
+tf_sram_free_slice_list(struct tf_sram_slice_list *slice_list)
+{
+ uint32_t i, block_cnt;
+ struct tf_sram_block *nblock, *block;
+
+ block_cnt = tf_sram_get_block_cnt(slice_list);
+ block = slice_list->head;
+
+ for (i = 0; i < block_cnt; i++) {
+ nblock = block->next;
+ tf_sram_free_block(slice_list, block);
+ block = nblock;
+ }
+}
+
+/**
+ * Allocate a single SRAM block from memory and add it to the slice list
+ */
+static struct tf_sram_block
+*tf_sram_alloc_block(struct tf_sram_slice_list *slice_list,
+ uint16_t block_id)
+{
+ struct tf_sram_block *block;
+ struct tfp_calloc_parms cparms;
+ int rc;
+
+ cparms.nitems = 1;
+ cparms.size = sizeof(struct tf_sram_block);
+ cparms.alignment = 0;
+ rc = tfp_calloc(&cparms);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "Failed to allocate block, rc:%s\n",
+ strerror(-rc));
+ return NULL;
+ }
+ block = (struct tf_sram_block *)cparms.mem_va;
+ block->block_id = block_id;
+
+ if (slice_list->head == NULL) {
+ slice_list->head = block;
+ slice_list->tail = block;
+ block->next = NULL;
+ block->prev = NULL;
+ } else {
+ block->next = slice_list->head;
+ block->prev = NULL;
+ block->next->prev = block;
+ slice_list->head = block->next->prev;
+ }
+ slice_list->cnt++;
+ return block;
+}
+
+/**
+ * Find the first not full block in the slice list
+ */
+static void
+tf_sram_find_first_not_full_block(struct tf_sram_slice_list *slice_list,
+ enum tf_sram_slice_size slice_size,
+ struct tf_sram_block **first_not_full_block)
+{
+ struct tf_sram_block *block = slice_list->head;
+ uint8_t slice_mask, mask;
+
+ switch (slice_size) {
+ case TF_SRAM_SLICE_SIZE_8B:
+ slice_mask = 0xff;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_16B:
+ slice_mask = 0xf;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_32B:
+ slice_mask = 0x3;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_64B:
+ default:
+ slice_mask = 0x1;
+ break;
+ }
+
+ *first_not_full_block = NULL;
+
+ while (block) {
+ mask = block->in_use_mask & slice_mask;
+ if (mask != slice_mask) {
+ *first_not_full_block = block;
+ break;
+ }
+ block = block->next;
+ }
+}
+static void
+tf_sram_dump_block(struct tf_sram_block *block)
+{
+ TFP_DRV_LOG(INFO, "block_id(0x%x) in_use_mask(0x%02x)\n",
+ block->block_id,
+ block->in_use_mask);
+}
+
+/**********************
+ * External functions
+ **********************/
+int
+tf_sram_mgr_bind(void **sram_handle)
+{
+ int rc = 0;
+ enum tf_sram_bank_id bank_id;
+ enum tf_sram_slice_size slice_size;
+ struct tf_sram *sram;
+ struct tf_sram_slice_list *slice_list;
+ enum tf_dir dir;
+ struct tfp_calloc_parms cparms;
+
+ TF_CHECK_PARMS1(sram_handle);
+
+ cparms.nitems = 1;
+ cparms.size = sizeof(struct tf_sram);
+ cparms.alignment = 0;
+ rc = tfp_calloc(&cparms);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "Failed to allocate SRAM mgmt data, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ sram = (struct tf_sram *)cparms.mem_va;
+
+ /* For each direction
+ */
+ for (dir = 0; dir < TF_DIR_MAX; dir++) {
+ /* For each bank
+ */
+ for (bank_id = TF_SRAM_BANK_ID_0;
+ bank_id < TF_SRAM_BANK_ID_MAX;
+ bank_id++) {
+ /* Create each sized slice empty list
+ */
+ for (slice_size = TF_SRAM_SLICE_SIZE_8B;
+ slice_size < TF_SRAM_SLICE_SIZE_MAX;
+ slice_size++) {
+ rc = tf_sram_get_slice_list(sram, &slice_list,
+ slice_size, dir,
+ bank_id);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "No SRAM slice list, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ tf_sram_init_slice_list(slice_list, slice_size);
+ }
+ }
+ }
+
+ *sram_handle = sram;
+
+ return rc;
+}
+
+int
+tf_sram_mgr_unbind(void *sram_handle)
+{
+ int rc = 0;
+ struct tf_sram *sram;
+ enum tf_sram_bank_id bank_id;
+ enum tf_sram_slice_size slice_size;
+ enum tf_dir dir;
+ struct tf_sram_slice_list *slice_list;
+
+ TF_CHECK_PARMS1(sram_handle);
+
+ sram = (struct tf_sram *)sram_handle;
+
+ for (dir = 0; dir < TF_DIR_MAX; dir++) {
+ /* For each bank
+ */
+ for (bank_id = TF_SRAM_BANK_ID_0;
+ bank_id < TF_SRAM_BANK_ID_MAX;
+ bank_id++) {
+ /* For each slice size
+ */
+ for (slice_size = TF_SRAM_SLICE_SIZE_8B;
+ slice_size < TF_SRAM_SLICE_SIZE_MAX;
+ slice_size++) {
+ rc = tf_sram_get_slice_list(sram, &slice_list,
+ slice_size, dir,
+ bank_id);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "No SRAM slice list, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ if (tf_sram_get_block_cnt(slice_list))
+ tf_sram_free_slice_list(slice_list);
+ }
+ }
+ }
+
+ tfp_free(sram);
+ sram_handle = NULL;
+
+ /* Freeing of the RM resources is handled by the table manager */
+ return rc;
+}
+
+int tf_sram_mgr_alloc(void *sram_handle,
+ struct tf_sram_mgr_alloc_parms *parms)
+{
+ int rc = 0;
+ struct tf_sram *sram;
+ struct tf_sram_slice_list *slice_list;
+ uint16_t block_id, slice_offset = 0;
+ uint32_t index;
+ struct tf_sram_block *block;
+ struct tf_rm_allocate_parms aparms = { 0 };
+ bool block_is_full;
+ uint16_t block_offset;
+
+ TF_CHECK_PARMS3(sram_handle, parms, parms->sram_offset);
+
+ sram = (struct tf_sram *)sram_handle;
+
+ /* Check the current slice list
+ */
+ rc = tf_sram_get_slice_list(sram, &slice_list, parms->slice_size,
+ parms->dir, parms->bank_id);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "No SRAM slice list, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ /* If the list is empty or all entries are full allocate a new block
+ */
+ if (!slice_list->first_not_full_block) {
+ /* Allocate and insert a new block
+ */
+ aparms.index = &index;
+ aparms.subtype = parms->tbl_type;
+ aparms.rm_db = parms->rm_db;
+ rc = tf_rm_allocate(&aparms);
+ if (rc)
+ return rc;
+
+ block_id = index;
+ block = tf_sram_alloc_block(slice_list, block_id);
+ } else {
+ /* Block exists
+ */
+ block =
+ (struct tf_sram_block *)(slice_list->first_not_full_block);
+ }
+ rc = tf_sram_get_next_slice_in_block(block,
+ parms->slice_size,
+ &slice_offset,
+ &block_is_full);
+
+ /* Find the new first non-full block in the list
+ */
+ tf_sram_find_first_not_full_block(slice_list,
+ parms->slice_size,
+ &slice_list->first_not_full_block);
+
+ tf_sram_block_id_2_offset(parms->bank_id, block->block_id,
+ &block_offset);
+
+ *parms->sram_offset = block_offset + slice_offset;
+ return rc;
+}
+
+int
+tf_sram_mgr_free(void *sram_handle,
+ struct tf_sram_mgr_free_parms *parms)
+{
+ int rc = 0;
+ struct tf_sram *sram;
+ struct tf_sram_slice_list *slice_list;
+ uint16_t block_id, slice_offset;
+ struct tf_sram_block *block;
+ bool block_is_empty;
+ struct tf_rm_free_parms fparms = { 0 };
+
+ TF_CHECK_PARMS2(sram_handle, parms);
+
+ sram = (struct tf_sram *)sram_handle;
+
+ /* Check the current slice list
+ */
+ rc = tf_sram_get_slice_list(sram, &slice_list, parms->slice_size,
+ parms->dir, parms->bank_id);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "No SRAM slice list, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ /* Determine the block id and slice offset from the SRAM offset
+ */
+ tf_sram_offset_2_block_id(parms->bank_id, parms->sram_offset, &block_id,
+ &slice_offset);
+
+ /* Search the list of blocks for the matching block id
+ */
+ block = tf_sram_find_block(block_id, slice_list);
+ if (block == NULL) {
+ TFP_DRV_LOG(ERR, "block not found 0x%x\n", block_id);
+ return rc;
+ }
+
+ /* If found, search for the matching SRAM slice in use.
+ */
+ rc = tf_sram_free_slice(parms->slice_size, slice_offset,
+ block, &block_is_empty);
+ if (rc) {
+ TFP_DRV_LOG(ERR, "Error freeing slice (%s)\n", strerror(-rc));
+ return rc;
+ }
+#if (STATS_CLEAR_ON_READ_SUPPORT == 0)
+ /* If this is a counter, clear it. In the future we need to switch to
+ * using the special access registers on Thor to automatically clear on
+ * read.
+ */
+ /* If this is counter table, clear the entry on free */
+ if (parms->tbl_type == TF_TBL_TYPE_ACT_STATS_64) {
+ uint8_t data[8] = { 0 };
+ uint16_t hcapi_type = 0;
+ struct tf_rm_get_hcapi_parms hparms = { 0 };
+
+ /* Get the hcapi type */
+ hparms.rm_db = parms->rm_db;
+ hparms.subtype = parms->tbl_type;
+ hparms.hcapi_type = &hcapi_type;
+ rc = tf_rm_get_hcapi_type(&hparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Failed type lookup, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->tbl_type),
+ strerror(-rc));
+ return rc;
+ }
+ /* Clear the counter
+ */
+ rc = tf_msg_set_tbl_entry(parms->tfp,
+ parms->dir,
+ hcapi_type,
+ sizeof(data),
+ data,
+ parms->sram_offset);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Set failed, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->tbl_type),
+ strerror(-rc));
+ return rc;
+ }
+ }
+#endif
+ /* If the block is empty, free the block to the RM
+ */
+ if (block_is_empty) {
+ fparms.rm_db = parms->rm_db;
+ fparms.subtype = parms->tbl_type;
+ fparms.index = block_id;
+ rc = tf_rm_free(&fparms);
+
+ if (rc) {
+ TFP_DRV_LOG(ERR, "Free block_id(%d) failed error(%s)\n",
+ block_id, strerror(-rc));
+ }
+ /* Free local entry regardless
+ */
+ tf_sram_free_block(slice_list, block);
+
+ /* Find the next non-full block in the list
+ */
+ tf_sram_find_first_not_full_block(slice_list,
+ parms->slice_size,
+ &slice_list->first_not_full_block);
+ }
+
+ return rc;
+}
+
+int
+tf_sram_mgr_dump(void *sram_handle,
+ struct tf_sram_mgr_dump_parms *parms)
+{
+ int rc = 0;
+ struct tf_sram *sram;
+ struct tf_sram_slice_list *slice_list;
+ uint32_t block_cnt, i;
+ struct tf_sram_block *block;
+
+ TF_CHECK_PARMS2(sram_handle, parms);
+
+ sram = (struct tf_sram *)sram_handle;
+
+ rc = tf_sram_get_slice_list(sram, &slice_list, parms->slice_size,
+ parms->dir, parms->bank_id);
+ if (rc)
+ return rc;
+
+ if (slice_list->cnt || slice_list->first_not_full_block) {
+ TFP_DRV_LOG(INFO, "\n********** %s: %s: %s ***********\n",
+ tf_sram_bank_2_str(parms->bank_id),
+ tf_dir_2_str(parms->dir),
+ tf_sram_slice_2_str(parms->slice_size));
+
+ block_cnt = tf_sram_get_block_cnt(slice_list);
+ TFP_DRV_LOG(INFO, "block_cnt(%d)\n", block_cnt);
+ if (slice_list->first_not_full_block)
+ TFP_DRV_LOG(INFO, "first_not_full_block(0x%x)\n",
+ slice_list->first_not_full_block->block_id);
+ block = slice_list->head;
+ for (i = 0; i < block_cnt; i++) {
+ tf_sram_dump_block(block);
+ block = tf_sram_get_next_block(block);
+ }
+ TFP_DRV_LOG(INFO, "*********************************\n");
+ }
+ return rc;
+}
+/**
+ * Validate an SRAM Slice is allocated
+ *
+ * Validate whether the SRAM slice is allocated
+ *
+ * [in] sram_handle
+ * Pointer to SRAM handle
+ *
+ * [in] parms
+ * Pointer to the SRAM alloc parameters
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ *
+ */
+int tf_sram_mgr_is_allocated(void *sram_handle,
+ struct tf_sram_mgr_is_allocated_parms *parms)
+{
+ int rc = 0;
+ struct tf_sram *sram;
+ struct tf_sram_slice_list *slice_list;
+ uint16_t block_id, slice_offset;
+ struct tf_sram_block *block;
+
+ TF_CHECK_PARMS3(sram_handle, parms, parms->is_allocated);
+
+ sram = (struct tf_sram *)sram_handle;
+
+ /* Check the current slice list
+ */
+ rc = tf_sram_get_slice_list(sram, &slice_list, parms->slice_size,
+ parms->dir, parms->bank_id);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "No SRAM slice list, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ /* If the list is empty, then it cannot be allocated
+ */
+ if (!slice_list->cnt) {
+ TFP_DRV_LOG(ERR, "List is empty for %s:%s:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_sram_slice_2_str(parms->slice_size),
+ tf_sram_bank_2_str(parms->bank_id));
+
+ parms->is_allocated = false;
+ goto done;
+ }
+
+ /* Determine the block id and slice offset from the SRAM offset
+ */
+ tf_sram_offset_2_block_id(parms->bank_id, parms->sram_offset, &block_id,
+ &slice_offset);
+
+ /* Search the list of blocks for the matching block id
+ */
+ block = tf_sram_find_block(block_id, slice_list);
+ if (block == NULL) {
+ TFP_DRV_LOG(ERR, "block not found in list 0x%x\n",
+ parms->sram_offset);
+ parms->is_allocated = false;
+ goto done;
+ }
+
+ rc = tf_sram_is_slice_allocated_in_block(block,
+ parms->slice_size,
+ slice_offset,
+ parms->is_allocated);
+done:
+ return rc;
+}
diff --git a/drivers/net/bnxt/tf_core/tf_sram_mgr.h b/drivers/net/bnxt/tf_core/tf_sram_mgr.h
new file mode 100644
index 0000000000..4abe3fb468
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/tf_sram_mgr.h
@@ -0,0 +1,317 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019-2021 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef _TF_SRAM_MGR_H_
+#define _TF_SRAM_MGR_H_
+
+#include <string.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <ctype.h>
+#include <limits.h>
+#include <errno.h>
+#include "tf_core.h"
+#include "tf_rm.h"
+
+/* When special access registers are used to access the SRAM, stats can be
+ * automatically cleared on read by the hardware. This requires additional
+ * support to be added in the firmware to use these registers for statistics.
+ * The support entails using the special access registers to read the stats.
+ * These are stored in bank 3 currently but may move depending upon the
+ * policy defined in tf_device_p58.h
+ */
+#define STATS_CLEAR_ON_READ_SUPPORT 0
+
+#define TF_SRAM_MGR_BLOCK_SZ_BYTES 64
+#define TF_SRAM_MGR_MIN_SLICE_BYTES 8
+/**
+ * Bank identifier
+ */
+enum tf_sram_bank_id {
+ TF_SRAM_BANK_ID_0, /**< SRAM Bank 0 id */
+ TF_SRAM_BANK_ID_1, /**< SRAM Bank 1 id */
+ TF_SRAM_BANK_ID_2, /**< SRAM Bank 2 id */
+ TF_SRAM_BANK_ID_3, /**< SRAM Bank 3 id */
+ TF_SRAM_BANK_ID_MAX /**< SRAM Bank index limit */
+};
+
+/**
+ * TF slice size.
+ *
+ * A slice is part of a 64B row
+ *
+ * Each slice is a multiple of 8B
+ */
+enum tf_sram_slice_size {
+ TF_SRAM_SLICE_SIZE_8B, /**< 8 byte SRAM slice */
+ TF_SRAM_SLICE_SIZE_16B, /**< 16 byte SRAM slice */
+ TF_SRAM_SLICE_SIZE_32B, /**< 32 byte SRAM slice */
+ TF_SRAM_SLICE_SIZE_64B, /**< 64 byte SRAM slice */
+ TF_SRAM_SLICE_SIZE_MAX /**< slice limit */
+};
+
+
+/** Initialize the SRAM slice manager
+ *
+ * The SRAM slice manager manages slices within 64B rows. Slices are of size
+ * tf_sram_slice_size. This function provides a handle to the SRAM manager
+ * data.
+ *
+ * SRAM manager data may dynamically allocate data upon initialization if
+ * running on the host.
+ *
+ * [in/out] sram_handle
+ * Pointer to SRAM handle
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ *
+ * Returns the handle for the SRAM slice manager
+ */
+int tf_sram_mgr_bind(void **sram_handle);
+
+/** Uninitialize the SRAM slice manager
+ *
+ * Frees any dynamically allocated data structures for SRAM slice management.
+ *
+ * [in] sram_handle
+ * Pointer to SRAM handle
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ */
+int tf_sram_mgr_unbind(void *sram_handle);
+
+/**
+ * tf_sram_mgr_alloc_parms parameter definition
+ */
+struct tf_sram_mgr_alloc_parms {
+ /**
+ * [in] dir
+ */
+ enum tf_dir dir;
+ /**
+ * [in] bank
+ *
+ * the SRAM bank to allocate from
+ */
+ enum tf_sram_bank_id bank_id;
+ /**
+ * [in] slice_size
+ *
+ * the slice size to allocate
+ */
+ enum tf_sram_slice_size slice_size;
+ /**
+ * [in/out] sram_slice
+ *
+ * A pointer to be filled with an 8B sram slice offset
+ */
+ uint16_t *sram_offset;
+ /**
+ * [in] RM DB Handle required for RM allocation
+ */
+ void *rm_db;
+ /**
+ * [in] tf table type
+ */
+ enum tf_tbl_type tbl_type;
+};
+
+/**
+ * Allocate an SRAM Slice
+ *
+ * Allocate an SRAM slice from the indicated bank. If successful an 8B SRAM
+ * offset will be returned. Slices are variable sized. This may result in
+ * a row being allocated from the RM SRAM bank pool if required.
+ *
+ * [in] sram_handle
+ * Pointer to SRAM handle
+ *
+ * [in] parms
+ * Pointer to the SRAM alloc parameters
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ *
+ */
+int tf_sram_mgr_alloc(void *sram_handle,
+ struct tf_sram_mgr_alloc_parms *parms);
+/**
+ * tf_sram_mgr_free_parms parameter definition
+ */
+struct tf_sram_mgr_free_parms {
+ /**
+ * [in] dir
+ */
+ enum tf_dir dir;
+ /**
+ * [in] bank
+ *
+ * the SRAM bank to free to
+ */
+ enum tf_sram_bank_id bank_id;
+ /**
+ * [in] slice_size
+ *
+ * the slice size to be returned
+ */
+ enum tf_sram_slice_size slice_size;
+ /**
+ * [in] sram_offset
+ *
+ * the SRAM slice offset (8B) to be returned
+ */
+ uint16_t sram_offset;
+ /**
+ * [in] RM DB Handle required for RM free
+ */
+ void *rm_db;
+ /**
+ * [in] tf table type
+ */
+ enum tf_tbl_type tbl_type;
+#if (STATS_CLEAR_ON_READ_SUPPORT == 0)
+ /**
+ * [in] tfp
+ *
+ * A pointer to the tf handle
+ */
+ void *tfp;
+#endif
+};
+
+/**
+ * Free an SRAM Slice
+ *
+ * Free an SRAM slice to the indicated bank. This may result in a 64B row
+ * being returned to the RM SRAM bank pool.
+ *
+ * [in] sram_handle
+ * Pointer to SRAM handle
+ *
+ * [in] parms
+ * Pointer to the SRAM free parameters
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ *
+ */
+int tf_sram_mgr_free(void *sram_handle,
+ struct tf_sram_mgr_free_parms *parms);
+
+/**
+ * tf_sram_mgr_dump_parms parameter definition
+ */
+struct tf_sram_mgr_dump_parms {
+ /**
+ * [in] dir
+ */
+ enum tf_dir dir;
+ /**
+ * [in] bank
+ *
+ * the SRAM bank to dump
+ */
+ enum tf_sram_bank_id bank_id;
+ /**
+ * [in] slice_size
+ *
+ * the slice size list to be dumped
+ */
+ enum tf_sram_slice_size slice_size;
+};
+
+/**
+ * Dump a slice list
+ *
+ * Dump the slice list given the SRAM bank and the slice size
+ *
+ * [in] sram_handle
+ * Pointer to SRAM handle
+ *
+ * [in] parms
+ * Pointer to the SRAM free parameters
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ *
+ */
+int tf_sram_mgr_dump(void *sram_handle,
+ struct tf_sram_mgr_dump_parms *parms);
+
+/**
+ * tf_sram_mgr_is_allocated_parms parameter definition
+ */
+struct tf_sram_mgr_is_allocated_parms {
+ /**
+ * [in] dir
+ */
+ enum tf_dir dir;
+ /**
+ * [in] bank
+ *
+ * the SRAM bank to allocate from
+ */
+ enum tf_sram_bank_id bank_id;
+ /**
+ * [in] slice_size
+ *
+ * the slice size which was allocated
+ */
+ enum tf_sram_slice_size slice_size;
+ /**
+ * [in] sram_offset
+ *
+ * The sram slice offset to validate
+ */
+ uint16_t sram_offset;
+ /**
+ * [in/out] is_allocated
+ *
+ * Pointer passed in to be filled with indication of allocation
+ */
+ bool *is_allocated;
+};
+
+/**
+ * Validate an SRAM Slice is allocated
+ *
+ * Validate whether the SRAM slice is allocated
+ *
+ * [in] sram_handle
+ * Pointer to SRAM handle
+ *
+ * [in] parms
+ * Pointer to the SRAM alloc parameters
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ *
+ */
+int tf_sram_mgr_is_allocated(void *sram_handle,
+ struct tf_sram_mgr_is_allocated_parms *parms);
+
+/**
+ * Given the slice size, return a char string
+ */
+const char
+*tf_sram_slice_2_str(enum tf_sram_slice_size slice_size);
+
+/**
+ * Given the bank_id, return a char string
+ */
+const char
+*tf_sram_bank_2_str(enum tf_sram_bank_id bank_id);
+
+#endif /* _TF_SRAM_MGR_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c
index 7011edcd78..0a8720e7b6 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl.c
+++ b/drivers/net/bnxt/tf_core/tf_tbl.c
@@ -16,20 +16,11 @@
#include "tf_session.h"
#include "tf_device.h"
-#define TF_TBL_RM_TO_PTR(new_idx, idx, base, shift) { \
- *(new_idx) = (((idx) + (base)) << (shift)); \
-}
-
-#define TF_TBL_PTR_TO_RM(new_idx, idx, base, shift) { \
- *(new_idx) = (((idx) >> (shift)) - (base)); \
-}
-
struct tf;
-/**
- * Shadow init flag, set on bind and cleared on unbind
- */
-static uint8_t shadow_init;
+#define TF_TBL_RM_TO_PTR(new_idx, idx, base, shift) { \
+ *(new_idx) = (((idx) + (base)) << (shift)); \
+}
int
tf_tbl_bind(struct tf *tfp,
@@ -121,8 +112,6 @@ tf_tbl_unbind(struct tf *tfp)
tbl_db->tbl_db[i] = NULL;
}
- shadow_init = 0;
-
return 0;
}
@@ -135,7 +124,6 @@ tf_tbl_alloc(struct tf *tfp __rte_unused,
struct tf_rm_allocate_parms aparms = { 0 };
struct tf_session *tfs;
struct tf_dev_info *dev;
- uint16_t base = 0, shift = 0;
struct tbl_rm_db *tbl_db;
void *tbl_db_ptr = NULL;
@@ -154,28 +142,12 @@ tf_tbl_alloc(struct tf *tfp __rte_unused,
rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr);
if (rc) {
TFP_DRV_LOG(ERR,
- "Failed to get em_ext_db from session, rc:%s\n",
+ "Failed to get tbl_db from session, rc:%s\n",
strerror(-rc));
return rc;
}
tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
- /* Only get table info if required for the device */
- if (dev->ops->tf_dev_get_tbl_info) {
- rc = dev->ops->tf_dev_get_tbl_info(tfp,
- tbl_db->tbl_db[parms->dir],
- parms->type,
- &base,
- &shift);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed to get table info:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type);
- return rc;
- }
- }
-
/* Allocate requested element */
aparms.rm_db = tbl_db->tbl_db[parms->dir];
aparms.subtype = parms->type;
@@ -183,13 +155,12 @@ tf_tbl_alloc(struct tf *tfp __rte_unused,
rc = tf_rm_allocate(&aparms);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s: Failed allocate, type:%d\n",
+ "%s: Failed allocate, type:%s\n",
tf_dir_2_str(parms->dir),
- parms->type);
+ tf_tbl_type_2_str(parms->type));
return rc;
}
- TF_TBL_RM_TO_PTR(&idx, idx, base, shift);
*parms->idx = idx;
return 0;
@@ -205,7 +176,6 @@ tf_tbl_free(struct tf *tfp __rte_unused,
int allocated = 0;
struct tf_session *tfs;
struct tf_dev_info *dev;
- uint16_t base = 0, shift = 0;
struct tbl_rm_db *tbl_db;
void *tbl_db_ptr = NULL;
@@ -230,28 +200,10 @@ tf_tbl_free(struct tf *tfp __rte_unused,
}
tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
- /* Only get table info if required for the device */
- if (dev->ops->tf_dev_get_tbl_info) {
- rc = dev->ops->tf_dev_get_tbl_info(tfp,
- tbl_db->tbl_db[parms->dir],
- parms->type,
- &base,
- &shift);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed to get table info:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type);
- return rc;
- }
- }
-
/* Check if element is in use */
aparms.rm_db = tbl_db->tbl_db[parms->dir];
aparms.subtype = parms->type;
-
- TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift);
-
+ aparms.index = parms->idx;
aparms.allocated = &allocated;
rc = tf_rm_is_allocated(&aparms);
if (rc)
@@ -259,9 +211,9 @@ tf_tbl_free(struct tf *tfp __rte_unused,
if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
TFP_DRV_LOG(ERR,
- "%s: Entry already free, type:%d, index:%d\n",
+ "%s: Entry already free, type:%s, index:%d\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
parms->idx);
return -EINVAL;
}
@@ -279,9 +231,9 @@ tf_tbl_free(struct tf *tfp __rte_unused,
rc = tf_rm_get_hcapi_type(&hparms);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Failed type lookup, type:%d, rc:%s\n",
+ "%s, Failed type lookup, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
return rc;
}
@@ -295,9 +247,9 @@ tf_tbl_free(struct tf *tfp __rte_unused,
parms->idx);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Set failed, type:%d, rc:%s\n",
+ "%s, Set failed, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
return rc;
}
@@ -306,15 +258,13 @@ tf_tbl_free(struct tf *tfp __rte_unused,
/* Free requested element */
fparms.rm_db = tbl_db->tbl_db[parms->dir];
fparms.subtype = parms->type;
-
- TF_TBL_PTR_TO_RM(&fparms.index, parms->idx, base, shift);
-
+ fparms.index = parms->idx;
rc = tf_rm_free(&fparms);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s: Free failed, type:%d, index:%d\n",
+ "%s: Free failed, type:%s, index:%d\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
parms->idx);
return rc;
}
@@ -333,7 +283,6 @@ tf_tbl_set(struct tf *tfp,
struct tf_rm_get_hcapi_parms hparms = { 0 };
struct tf_session *tfs;
struct tf_dev_info *dev;
- uint16_t base = 0, shift = 0;
struct tbl_rm_db *tbl_db;
void *tbl_db_ptr = NULL;
@@ -358,21 +307,6 @@ tf_tbl_set(struct tf *tfp,
}
tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
- /* Only get table info if required for the device */
- if (dev->ops->tf_dev_get_tbl_info) {
- rc = dev->ops->tf_dev_get_tbl_info(tfp,
- tbl_db->tbl_db[parms->dir],
- parms->type,
- &base,
- &shift);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed to get table info:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type);
- return rc;
- }
- }
/* Do not check meter drop counter because it is not allocated
* resources
@@ -381,19 +315,18 @@ tf_tbl_set(struct tf *tfp,
/* Verify that the entry has been previously allocated */
aparms.rm_db = tbl_db->tbl_db[parms->dir];
aparms.subtype = parms->type;
- TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift);
-
aparms.allocated = &allocated;
+ aparms.index = parms->idx;
rc = tf_rm_is_allocated(&aparms);
if (rc)
return rc;
if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
TFP_DRV_LOG(ERR,
- "%s, Invalid or not allocated index, type:%d, idx:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type,
- parms->idx);
+ "%s, Invalid or not allocated, type:%s, idx:%d\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->idx);
return -EINVAL;
}
}
@@ -405,9 +338,9 @@ tf_tbl_set(struct tf *tfp,
rc = tf_rm_get_hcapi_type(&hparms);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Failed type lookup, type:%d, rc:%s\n",
+ "%s, Failed type lookup, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
return rc;
}
@@ -420,9 +353,9 @@ tf_tbl_set(struct tf *tfp,
parms->idx);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Set failed, type:%d, rc:%s\n",
+ "%s, Set failed, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
return rc;
}
@@ -441,7 +374,6 @@ tf_tbl_get(struct tf *tfp,
struct tf_rm_get_hcapi_parms hparms = { 0 };
struct tf_session *tfs;
struct tf_dev_info *dev;
- uint16_t base = 0, shift = 0;
struct tbl_rm_db *tbl_db;
void *tbl_db_ptr = NULL;
@@ -466,22 +398,6 @@ tf_tbl_get(struct tf *tfp,
}
tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
- /* Only get table info if required for the device */
- if (dev->ops->tf_dev_get_tbl_info) {
- rc = dev->ops->tf_dev_get_tbl_info(tfp,
- tbl_db->tbl_db[parms->dir],
- parms->type,
- &base,
- &shift);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed to get table info:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type);
- return rc;
- }
- }
-
/* Do not check meter drop counter because it is not allocated
* resources.
*/
@@ -489,8 +405,7 @@ tf_tbl_get(struct tf *tfp,
/* Verify that the entry has been previously allocated */
aparms.rm_db = tbl_db->tbl_db[parms->dir];
aparms.subtype = parms->type;
- TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift);
-
+ aparms.index = parms->idx;
aparms.allocated = &allocated;
rc = tf_rm_is_allocated(&aparms);
if (rc)
@@ -498,9 +413,9 @@ tf_tbl_get(struct tf *tfp,
if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
TFP_DRV_LOG(ERR,
- "%s, Invalid or not allocated index, type:%d, idx:%d\n",
+ "%s, Invalid or not allocated index, type:%s, idx:%d\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
parms->idx);
return -EINVAL;
}
@@ -513,9 +428,9 @@ tf_tbl_get(struct tf *tfp,
rc = tf_rm_get_hcapi_type(&hparms);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Failed type lookup, type:%d, rc:%s\n",
+ "%s, Failed type lookup, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
return rc;
}
@@ -529,9 +444,9 @@ tf_tbl_get(struct tf *tfp,
parms->idx);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Get failed, type:%d, rc:%s\n",
+ "%s, Get failed, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
return rc;
}
@@ -549,7 +464,6 @@ tf_tbl_bulk_get(struct tf *tfp,
struct tf_rm_check_indexes_in_range_parms cparms = { 0 };
struct tf_session *tfs;
struct tf_dev_info *dev;
- uint16_t base = 0, shift = 0;
struct tbl_rm_db *tbl_db;
void *tbl_db_ptr = NULL;
@@ -574,40 +488,21 @@ tf_tbl_bulk_get(struct tf *tfp,
}
tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
- /* Only get table info if required for the device */
- if (dev->ops->tf_dev_get_tbl_info) {
- rc = dev->ops->tf_dev_get_tbl_info(tfp,
- tbl_db->tbl_db[parms->dir],
- parms->type,
- &base,
- &shift);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed to get table info:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type);
- return rc;
- }
- }
-
/* Verify that the entries are in the range of reserved resources. */
cparms.rm_db = tbl_db->tbl_db[parms->dir];
cparms.subtype = parms->type;
-
- TF_TBL_PTR_TO_RM(&cparms.starting_index, parms->starting_idx,
- base, shift);
-
cparms.num_entries = parms->num_entries;
+ cparms.starting_index = parms->starting_idx;
rc = tf_rm_check_indexes_in_range(&cparms);
if (rc) {
TFP_DRV_LOG(ERR,
"%s, Invalid or %d index starting from %d"
- " not in range, type:%d",
+ " not in range, type:%s",
tf_dir_2_str(parms->dir),
parms->starting_idx,
parms->num_entries,
- parms->type);
+ tf_tbl_type_2_str(parms->type));
return rc;
}
@@ -617,9 +512,9 @@ tf_tbl_bulk_get(struct tf *tfp,
rc = tf_rm_get_hcapi_type(&hparms);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Failed type lookup, type:%d, rc:%s\n",
+ "%s, Failed type lookup, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
return rc;
}
@@ -634,9 +529,9 @@ tf_tbl_bulk_get(struct tf *tfp,
parms->physical_mem_addr);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Bulk get failed, type:%d, rc:%s\n",
+ "%s, Bulk get failed, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
}
@@ -653,9 +548,9 @@ tf_tbl_get_resc_info(struct tf *tfp,
struct tf_rm_get_alloc_info_parms ainfo;
void *tbl_db_ptr = NULL;
struct tbl_rm_db *tbl_db;
- uint16_t base = 0, shift = 0;
struct tf_dev_info *dev;
struct tf_session *tfs;
+ uint16_t base = 0, shift = 0;
TF_CHECK_PARMS2(tfp, tbl);
@@ -677,7 +572,6 @@ tf_tbl_get_resc_info(struct tf *tfp,
tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
- /* check if reserved resource for WC is multiple of num_slices */
for (d = 0; d < TF_DIR_MAX; d++) {
ainfo.rm_db = tbl_db->tbl_db[d];
dinfo = tbl[d].info;
diff --git a/drivers/net/bnxt/tf_core/tf_tbl.h b/drivers/net/bnxt/tf_core/tf_tbl.h
index 7e1107ffe7..2483718e5d 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl.h
+++ b/drivers/net/bnxt/tf_core/tf_tbl.h
@@ -28,14 +28,6 @@ struct tf_tbl_cfg_parms {
* Table Type element configuration array
*/
struct tf_rm_element_cfg *cfg;
- /**
- * Shadow table type configuration array
- */
- struct tf_shadow_tbl_cfg *shadow_cfg;
- /**
- * Boolean controlling the request shadow copy.
- */
- bool shadow_copy;
/**
* Session resource allocations
*/
@@ -197,8 +189,6 @@ struct tbl_rm_db {
*
* @ref tf_tbl_free
*
- * @ref tf_tbl_alloc_search
- *
* @ref tf_tbl_set
*
* @ref tf_tbl_get
@@ -255,10 +245,7 @@ int tf_tbl_alloc(struct tf *tfp,
struct tf_tbl_alloc_parms *parms);
/**
- * Free's the requested table type and returns it to the DB. If shadow
- * DB is enabled its searched first and if found the element refcount
- * is decremented. If refcount goes to 0 then its returned to the
- * table type DB.
+ * Frees the requested table type and returns it to the DB.
*
* [in] tfp
* Pointer to TF handle, used for HCAPI communication
diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.c b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
new file mode 100644
index 0000000000..ea10afecb6
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
@@ -0,0 +1,713 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019-2021 Broadcom
+ * All rights reserved.
+ */
+
+/* Truflow Table APIs and supporting code */
+
+#include <rte_common.h>
+
+#include "tf_tbl.h"
+#include "tf_tbl_sram.h"
+#include "tf_sram_mgr.h"
+#include "tf_common.h"
+#include "tf_rm.h"
+#include "tf_util.h"
+#include "tf_msg.h"
+#include "tfp.h"
+#include "tf_session.h"
+#include "tf_device.h"
+#include "cfa_resource_types.h"
+
+#define DBG_SRAM 0
+
+/**
+ * tf_sram_tbl_get_info_parms parameter definition
+ */
+struct tf_tbl_sram_get_info_parms {
+ /**
+ * [in] table RM database
+ */
+ void *rm_db;
+ /**
+ * [in] Receive or transmit direction
+ */
+ enum tf_dir dir;
+ /**
+ * [in] table_type
+ *
+ * the TF index table type
+ */
+ enum tf_tbl_type tbl_type;
+ /**
+ * [out] bank
+ *
+ * The SRAM bank associated with the type
+ */
+ enum tf_sram_bank_id bank_id;
+ /**
+ * [out] slice_size
+ *
+ * the slice size for the indicated table type
+ */
+ enum tf_sram_slice_size slice_size;
+};
+
+/**
+ * Translate HCAPI type to SRAM Manager bank
+ */
+const uint16_t tf_tbl_sram_hcapi_2_bank[CFA_RESOURCE_TYPE_P58_LAST] = {
+ [CFA_RESOURCE_TYPE_P58_SRAM_BANK_0] = TF_SRAM_BANK_ID_0,
+ [CFA_RESOURCE_TYPE_P58_SRAM_BANK_1] = TF_SRAM_BANK_ID_1,
+ [CFA_RESOURCE_TYPE_P58_SRAM_BANK_2] = TF_SRAM_BANK_ID_2,
+ [CFA_RESOURCE_TYPE_P58_SRAM_BANK_3] = TF_SRAM_BANK_ID_3
+};
+
+#define TF_TBL_SRAM_SLICES_MAX \
+ (TF_SRAM_MGR_BLOCK_SZ_BYTES / TF_SRAM_MGR_MIN_SLICE_BYTES)
+/**
+ * Translate HCAPI type to SRAM Manager bank
+ */
+const uint8_t tf_tbl_sram_slices_2_size[TF_TBL_SRAM_SLICES_MAX + 1] = {
+ [0] = TF_SRAM_SLICE_SIZE_64B, /* if 0 slices assume 1 64B block */
+ [1] = TF_SRAM_SLICE_SIZE_64B, /* 1 slice per 64B block */
+ [2] = TF_SRAM_SLICE_SIZE_32B, /* 2 slices per 64B block */
+ [4] = TF_SRAM_SLICE_SIZE_16B, /* 4 slices per 64B block */
+ [8] = TF_SRAM_SLICE_SIZE_8B /* 8 slices per 64B block */
+};
+
+/**
+ * Get SRAM Table Information for a given index table type
+ *
+ *
+ * [in] sram_handle
+ * Pointer to SRAM handle
+ *
+ * [in] parms
+ * Pointer to the SRAM get info parameters
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ *
+ */
+static int tf_tbl_sram_get_info(struct tf_tbl_sram_get_info_parms *parms)
+{
+ int rc = 0;
+ uint16_t hcapi_type;
+ uint16_t slices;
+ struct tf_rm_get_hcapi_parms hparms;
+ struct tf_rm_get_slices_parms sparms;
+
+ hparms.rm_db = parms->rm_db;
+ hparms.subtype = parms->tbl_type;
+ hparms.hcapi_type = &hcapi_type;
+
+ rc = tf_rm_get_hcapi_type(&hparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get hcapi_type %s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->tbl_type),
+ strerror(-rc));
+ return rc;
+ }
+ parms->bank_id = tf_tbl_sram_hcapi_2_bank[hcapi_type];
+
+ sparms.rm_db = parms->rm_db;
+ sparms.subtype = parms->tbl_type;
+ sparms.slices = &slices;
+
+ rc = tf_rm_get_slices(&sparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get slice cnt %s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->tbl_type),
+ strerror(-rc));
+ return rc;
+ }
+ if (slices)
+ parms->slice_size = tf_tbl_sram_slices_2_size[slices];
+
+ TFP_DRV_LOG(INFO,
+ "(%s) bank(%s) slice_size(%s)\n",
+ tf_tbl_type_2_str(parms->tbl_type),
+ tf_sram_bank_2_str(parms->bank_id),
+ tf_sram_slice_2_str(parms->slice_size));
+ return rc;
+}
+
+int
+tf_tbl_sram_bind(struct tf *tfp __rte_unused)
+{
+ int rc = 0;
+ void *sram_handle = NULL;
+
+ TF_CHECK_PARMS1(tfp);
+
+ rc = tf_sram_mgr_bind(&sram_handle);
+
+ tf_session_set_sram_db(tfp, sram_handle);
+
+ TFP_DRV_LOG(INFO,
+ "SRAM Table - initialized\n");
+
+ return rc;
+}
+
+int
+tf_tbl_sram_unbind(struct tf *tfp __rte_unused)
+{
+ int rc = 0;
+ void *sram_handle = NULL;
+
+ TF_CHECK_PARMS1(tfp);
+
+ rc = tf_session_get_sram_db(tfp, &sram_handle);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get sram_handle from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ if (sram_handle)
+ rc = tf_sram_mgr_unbind(sram_handle);
+
+ TFP_DRV_LOG(INFO,
+ "SRAM Table - deinitialized\n");
+ return rc;
+}
+
+int
+tf_tbl_sram_alloc(struct tf *tfp,
+ struct tf_tbl_alloc_parms *parms)
+{
+ int rc;
+ uint16_t idx;
+ struct tf_session *tfs;
+ struct tf_dev_info *dev;
+ struct tf_tbl_sram_get_info_parms iparms = { 0 };
+ struct tf_sram_mgr_alloc_parms aparms = { 0 };
+ struct tbl_rm_db *tbl_db;
+ void *tbl_db_ptr = NULL;
+ void *sram_handle = NULL;
+
+ TF_CHECK_PARMS2(tfp, parms);
+
+ /* Retrieve the session information */
+ rc = tf_session_get(tfp, &tfs, &dev);
+ if (rc)
+ return rc;
+
+ rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get tbl_db from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
+
+ rc = tf_session_get_sram_db(tfp, &sram_handle);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get sram_handle from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ iparms.rm_db = tbl_db->tbl_db[parms->dir];
+ iparms.dir = parms->dir;
+ iparms.tbl_type = parms->type;
+
+ rc = tf_tbl_sram_get_info(&iparms);
+
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get SRAM info %s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type));
+ return rc;
+ }
+
+ aparms.dir = parms->dir;
+ aparms.bank_id = iparms.bank_id;
+ aparms.slice_size = iparms.slice_size;
+ aparms.sram_offset = &idx;
+ aparms.tbl_type = parms->type;
+ aparms.rm_db = tbl_db->tbl_db[parms->dir];
+
+ rc = tf_sram_mgr_alloc(sram_handle, &aparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to allocate SRAM table:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type));
+ return rc;
+ }
+ *parms->idx = idx;
+
+#if (DBG_SRAM == 1)
+ {
+ struct tf_sram_mgr_dump_parms dparms;
+
+ dparms.dir = parms->dir;
+ dparms.bank_id = iparms.bank_id;
+ dparms.slice_size = iparms.slice_size;
+
+ rc = tf_sram_mgr_dump(sram_handle, &dparms);
+ }
+#endif
+
+ return rc;
+}
+
+int
+tf_tbl_sram_free(struct tf *tfp __rte_unused,
+ struct tf_tbl_free_parms *parms)
+{
+ int rc;
+ struct tf_session *tfs;
+ struct tf_dev_info *dev;
+ struct tbl_rm_db *tbl_db;
+ void *tbl_db_ptr = NULL;
+ struct tf_tbl_sram_get_info_parms iparms = { 0 };
+ struct tf_sram_mgr_free_parms fparms = { 0 };
+ struct tf_sram_mgr_is_allocated_parms aparms = { 0 };
+ bool allocated = false;
+ void *sram_handle = NULL;
+
+ TF_CHECK_PARMS2(tfp, parms);
+
+ /* Retrieve the session information */
+ rc = tf_session_get(tfp, &tfs, &dev);
+ if (rc)
+ return rc;
+
+ rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get em_ext_db from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
+
+ rc = tf_session_get_sram_db(tfp, &sram_handle);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get sram_handle from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ iparms.rm_db = tbl_db->tbl_db[parms->dir];
+ iparms.dir = parms->dir;
+ iparms.tbl_type = parms->type;
+
+ rc = tf_tbl_sram_get_info(&iparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get table info:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type));
+ return rc;
+ }
+
+#if (DBG_SRAM == 1)
+ {
+ struct tf_sram_mgr_dump_parms dparms;
+
+ printf("%s: %s: %s\n", tf_dir_2_str(parms->dir),
+ tf_sram_slice_2_str(iparms.slice_size),
+ tf_sram_bank_2_str(iparms.bank_id));
+
+ dparms.dir = parms->dir;
+ dparms.bank_id = iparms.bank_id;
+ dparms.slice_size = iparms.slice_size;
+
+ rc = tf_sram_mgr_dump(sram_handle, &dparms);
+ }
+#endif
+
+ aparms.sram_offset = parms->idx;
+ aparms.slice_size = iparms.slice_size;
+ aparms.bank_id = iparms.bank_id;
+ aparms.dir = parms->dir;
+ aparms.is_allocated = &allocated;
+
+ rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
+ if (rc || !allocated) {
+ TFP_DRV_LOG(ERR,
+ "%s: Free of invalid entry:%s idx(%d):(%s)\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->idx,
+ strerror(-rc));
+ rc = -ENOMEM;
+ return rc;
+ }
+
+ fparms.rm_db = tbl_db->tbl_db[parms->dir];
+ fparms.tbl_type = parms->type;
+ fparms.sram_offset = parms->idx;
+ fparms.slice_size = iparms.slice_size;
+ fparms.bank_id = iparms.bank_id;
+ fparms.dir = parms->dir;
+#if (STATS_CLEAR_ON_READ_SUPPORT == 0)
+ fparms.tfp = tfp;
+#endif
+ rc = tf_sram_mgr_free(sram_handle, &fparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to free entry:%s idx(%d)\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->idx);
+ return rc;
+ }
+
+
+#if (DBG_SRAM == 1)
+ {
+ struct tf_sram_mgr_dump_parms dparms;
+
+ printf("%s: %s: %s\n", tf_dir_2_str(parms->dir),
+ tf_sram_slice_2_str(iparms.slice_size),
+ tf_sram_bank_2_str(iparms.bank_id));
+
+ dparms.dir = parms->dir;
+ dparms.bank_id = iparms.bank_id;
+ dparms.slice_size = iparms.slice_size;
+
+ rc = tf_sram_mgr_dump(sram_handle, &dparms);
+ }
+#endif
+ return rc;
+}
+
+int
+tf_tbl_sram_set(struct tf *tfp,
+ struct tf_tbl_set_parms *parms)
+{
+ int rc;
+ bool allocated = 0;
+ uint16_t hcapi_type;
+ struct tf_rm_get_hcapi_parms hparms = { 0 };
+ struct tf_session *tfs;
+ struct tf_dev_info *dev;
+ struct tbl_rm_db *tbl_db;
+ void *tbl_db_ptr = NULL;
+ struct tf_tbl_sram_get_info_parms iparms = { 0 };
+ struct tf_sram_mgr_is_allocated_parms aparms = { 0 };
+ void *sram_handle = NULL;
+
+
+ TF_CHECK_PARMS3(tfp, parms, parms->data);
+
+ /* Retrieve the session information */
+ rc = tf_session_get(tfp, &tfs, &dev);
+ if (rc)
+ return rc;
+
+ rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get em_ext_db from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
+
+ rc = tf_session_get_sram_db(tfp, &sram_handle);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get sram_handle from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ iparms.rm_db = tbl_db->tbl_db[parms->dir];
+ iparms.dir = parms->dir;
+ iparms.tbl_type = parms->type;
+
+ rc = tf_tbl_sram_get_info(&iparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get table info:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type));
+ return rc;
+ }
+
+ aparms.sram_offset = parms->idx;
+ aparms.slice_size = iparms.slice_size;
+ aparms.bank_id = iparms.bank_id;
+ aparms.dir = parms->dir;
+ aparms.is_allocated = &allocated;
+ rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
+ if (rc || !allocated) {
+ TFP_DRV_LOG(ERR,
+ "%s: Entry not allocated:%s idx(%d):(%s)\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->idx,
+ strerror(-rc));
+ rc = -ENOMEM;
+ return rc;
+ }
+
+ /* Set the entry */
+ hparms.rm_db = tbl_db->tbl_db[parms->dir];
+ hparms.subtype = parms->type;
+ hparms.hcapi_type = &hcapi_type;
+ rc = tf_rm_get_hcapi_type(&hparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Failed type lookup, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ strerror(-rc));
+ return rc;
+ }
+
+ rc = tf_msg_set_tbl_entry(tfp,
+ parms->dir,
+ hcapi_type,
+ parms->data_sz_in_bytes,
+ parms->data,
+ parms->idx);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Set failed, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ strerror(-rc));
+ return rc;
+ }
+ return rc;
+}
+
+int
+tf_tbl_sram_get(struct tf *tfp,
+ struct tf_tbl_get_parms *parms)
+{
+ int rc;
+ uint16_t hcapi_type;
+ bool allocated = 0;
+ struct tf_rm_get_hcapi_parms hparms = { 0 };
+ struct tf_session *tfs;
+ struct tf_dev_info *dev;
+ struct tbl_rm_db *tbl_db;
+ void *tbl_db_ptr = NULL;
+ struct tf_tbl_sram_get_info_parms iparms = { 0 };
+ struct tf_sram_mgr_is_allocated_parms aparms = { 0 };
+ void *sram_handle = NULL;
+
+ TF_CHECK_PARMS3(tfp, parms, parms->data);
+
+ /* Retrieve the session information */
+ rc = tf_session_get(tfp, &tfs, &dev);
+ if (rc)
+ return rc;
+
+ rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get em_ext_db from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
+
+ rc = tf_session_get_sram_db(tfp, &sram_handle);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get sram_handle from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ iparms.rm_db = tbl_db->tbl_db[parms->dir];
+ iparms.dir = parms->dir;
+ iparms.tbl_type = parms->type;
+
+ rc = tf_tbl_sram_get_info(&iparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get table info:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type));
+ return rc;
+ }
+
+ aparms.sram_offset = parms->idx;
+ aparms.slice_size = iparms.slice_size;
+ aparms.bank_id = iparms.bank_id;
+ aparms.dir = parms->dir;
+ aparms.is_allocated = &allocated;
+
+ rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
+ if (rc || !allocated) {
+ TFP_DRV_LOG(ERR,
+ "%s: Entry not allocated:%s idx(%d):(%s)\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->idx,
+ strerror(-rc));
+ rc = -ENOMEM;
+ return rc;
+ }
+
+ /* Get the entry */
+ hparms.rm_db = tbl_db->tbl_db[parms->dir];
+ hparms.subtype = parms->type;
+ hparms.hcapi_type = &hcapi_type;
+ rc = tf_rm_get_hcapi_type(&hparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Failed type lookup, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ strerror(-rc));
+ return rc;
+ }
+
+ /* Get the entry */
+ rc = tf_msg_get_tbl_entry(tfp,
+ parms->dir,
+ hcapi_type,
+ parms->data_sz_in_bytes,
+ parms->data,
+ parms->idx);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Get failed, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ strerror(-rc));
+ return rc;
+ }
+ return rc;
+}
+
+int
+tf_tbl_sram_bulk_get(struct tf *tfp,
+ struct tf_tbl_get_bulk_parms *parms)
+{
+ int rc;
+ uint16_t hcapi_type;
+ struct tf_rm_get_hcapi_parms hparms = { 0 };
+ struct tf_tbl_sram_get_info_parms iparms = { 0 };
+ struct tf_session *tfs;
+ struct tf_dev_info *dev;
+ struct tbl_rm_db *tbl_db;
+ void *tbl_db_ptr = NULL;
+ uint16_t idx;
+ struct tf_sram_mgr_is_allocated_parms aparms = { 0 };
+ bool allocated = false;
+ void *sram_handle = NULL;
+
+ TF_CHECK_PARMS2(tfp, parms);
+
+ /* Retrieve the session information */
+ rc = tf_session_get(tfp, &tfs, &dev);
+ if (rc)
+ return rc;
+
+ rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get em_ext_db from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
+
+ rc = tf_session_get_sram_db(tfp, &sram_handle);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get sram_handle from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ iparms.rm_db = tbl_db->tbl_db[parms->dir];
+ iparms.dir = parms->dir;
+ iparms.tbl_type = parms->type;
+
+ rc = tf_tbl_sram_get_info(&iparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get table info:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type));
+ return rc;
+ }
+
+ /* Validate the start offset and the end offset is allocated
+ * This API is only used for statistics. 8 Byte entry allocation
+ * is used to verify
+ */
+ aparms.sram_offset = parms->starting_idx;
+ aparms.slice_size = iparms.slice_size;
+ aparms.bank_id = iparms.bank_id;
+ aparms.dir = parms->dir;
+ aparms.is_allocated = &allocated;
+ rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
+ if (rc || !allocated) {
+ TFP_DRV_LOG(ERR,
+ "%s: Entry not allocated:%s starting_idx(%d):(%s)\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->starting_idx,
+ strerror(-rc));
+ rc = -ENOMEM;
+ return rc;
+ }
+ idx = parms->starting_idx + parms->num_entries - 1;
+ aparms.sram_offset = idx;
+ rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
+ if (rc || !allocated) {
+ TFP_DRV_LOG(ERR,
+ "%s: Entry not allocated:%s last_idx(%d):(%s)\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ idx,
+ strerror(-rc));
+ rc = -ENOMEM;
+ return rc;
+ }
+
+ hparms.rm_db = tbl_db->tbl_db[parms->dir];
+ hparms.subtype = parms->type;
+ hparms.hcapi_type = &hcapi_type;
+ rc = tf_rm_get_hcapi_type(&hparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Failed type lookup, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ strerror(-rc));
+ return rc;
+ }
+
+ /* Get the entries */
+ rc = tf_msg_bulk_get_tbl_entry(tfp,
+ parms->dir,
+ hcapi_type,
+ parms->starting_idx,
+ parms->num_entries,
+ parms->entry_sz_in_bytes,
+ parms->physical_mem_addr);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Bulk get failed, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ strerror(-rc));
+ }
+ return rc;
+}
diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.h b/drivers/net/bnxt/tf_core/tf_tbl_sram.h
new file mode 100644
index 0000000000..32001e34a9
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.h
@@ -0,0 +1,154 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019-2021 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef TF_TBL_SRAM_H_
+#define TF_TBL_SRAM_H_
+
+#include "tf_core.h"
+#include "stack.h"
+
+
+/**
+ * The SRAM Table module provides processing of managed SRAM types.
+ */
+
+
+/**
+ * @page tblsram SRAM Table
+ *
+ * @ref tf_tbl_sram_bind
+ *
+ * @ref tf_tbl_sram_unbind
+ *
+ * @ref tf_tbl_sram_alloc
+ *
+ * @ref tf_tbl_sram_free
+ *
+ * @ref tf_tbl_sram_set
+ *
+ * @ref tf_tbl_sram_get
+ *
+ * @ref tf_tbl_sram_bulk_get
+ */
+
+/**
+ * Initializes the Table module with the requested DBs. Must be
+ * invoked as the first thing before any of the access functions.
+ *
+ * [in] tfp
+ * Pointer to TF handle, used for HCAPI communication
+ *
+ * [in] parms
+ * Pointer to Table configuration parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_tbl_sram_bind(struct tf *tfp);
+
+/**
+ * Cleans up the private DBs and releases all the data.
+ *
+ * [in] tfp
+ * Pointer to TF handle, used for HCAPI communication
+ *
+ * [in] parms
+ * Pointer to parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_tbl_sram_unbind(struct tf *tfp);
+
+/**
+ * Allocates the requested table type from the internal RM DB.
+ *
+ * [in] tfp
+ * Pointer to TF handle, used for HCAPI communication
+ *
+ * [in] parms
+ * Pointer to Table allocation parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_tbl_sram_alloc(struct tf *tfp,
+ struct tf_tbl_alloc_parms *parms);
+
+/**
+ * Free's the requested table type and returns it to the DB. If shadow
+ * DB is enabled its searched first and if found the element refcount
+ * is decremented. If refcount goes to 0 then its returned to the
+ * table type DB.
+ *
+ * [in] tfp
+ * Pointer to TF handle, used for HCAPI communication
+ *
+ * [in] parms
+ * Pointer to Table free parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_tbl_sram_free(struct tf *tfp,
+ struct tf_tbl_free_parms *parms);
+
+
+/**
+ * Configures the requested element by sending a firmware request which
+ * then installs it into the device internal structures.
+ *
+ * [in] tfp
+ * Pointer to TF handle, used for HCAPI communication
+ *
+ * [in] parms
+ * Pointer to Table set parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_tbl_sram_set(struct tf *tfp,
+ struct tf_tbl_set_parms *parms);
+
+/**
+ * Retrieves the requested element by sending a firmware request to get
+ * the element.
+ *
+ * [in] tfp
+ * Pointer to TF handle, used for HCAPI communication
+ *
+ * [in] parms
+ * Pointer to Table get parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_tbl_sram_get(struct tf *tfp,
+ struct tf_tbl_get_parms *parms);
+
+/**
+ * Retrieves bulk block of elements by sending a firmware request to
+ * get the elements.
+ *
+ * [in] tfp
+ * Pointer to TF handle, used for HCAPI communication
+ *
+ * [in] parms
+ * Pointer to Table get bulk parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_tbl_sram_bulk_get(struct tf *tfp,
+ struct tf_tbl_get_bulk_parms *parms);
+
+#endif /* TF_TBL_SRAM_H */
diff --git a/drivers/net/bnxt/tf_core/tf_tcam.c b/drivers/net/bnxt/tf_core/tf_tcam.c
index 45206c5992..806af3070a 100644
--- a/drivers/net/bnxt/tf_core/tf_tcam.c
+++ b/drivers/net/bnxt/tf_core/tf_tcam.c
@@ -43,7 +43,7 @@ tf_tcam_bind(struct tf *tfp,
struct tf_shadow_tcam_free_db_parms fshadow;
struct tf_shadow_tcam_cfg_parms shadow_cfg;
struct tf_shadow_tcam_create_db_parms shadow_cdb;
- uint16_t num_slices = 1;
+ uint16_t num_slices = parms->wc_num_slices;
struct tf_session *tfs;
struct tf_dev_info *dev;
struct tcam_rm_db *tcam_db;
@@ -61,7 +61,7 @@ tf_tcam_bind(struct tf *tfp,
if (rc)
return rc;
- if (dev->ops->tf_dev_get_tcam_slice_info == NULL) {
+ if (dev->ops->tf_dev_set_tcam_slice_info == NULL) {
rc = -EOPNOTSUPP;
TFP_DRV_LOG(ERR,
"Operation not supported, rc:%s\n",
@@ -69,10 +69,8 @@ tf_tcam_bind(struct tf *tfp,
return rc;
}
- rc = dev->ops->tf_dev_get_tcam_slice_info(tfp,
- TF_TCAM_TBL_TYPE_WC_TCAM,
- 0,
- &num_slices);
+ rc = dev->ops->tf_dev_set_tcam_slice_info(tfp,
+ num_slices);
if (rc)
return rc;
diff --git a/drivers/net/bnxt/tf_core/tf_tcam.h b/drivers/net/bnxt/tf_core/tf_tcam.h
index bed17af6ae..b1e7a92b0b 100644
--- a/drivers/net/bnxt/tf_core/tf_tcam.h
+++ b/drivers/net/bnxt/tf_core/tf_tcam.h
@@ -12,6 +12,9 @@
* The TCAM module provides processing of Internal TCAM types.
*/
+/* Number of slices per row for WC TCAM */
+extern uint16_t g_wc_num_slices_per_row;
+
/**
* TCAM configuration parameters
*/
@@ -36,6 +39,10 @@ struct tf_tcam_cfg_parms {
* Session resource allocations
*/
struct tf_session_resources *resources;
+ /**
+ * WC number of slices per row.
+ */
+ enum tf_wc_num_slice wc_num_slices;
};
/**
diff --git a/drivers/net/bnxt/tf_core/tf_tcam_shared.c b/drivers/net/bnxt/tf_core/tf_tcam_shared.c
index 83b6fbd5fb..c120c6f577 100644
--- a/drivers/net/bnxt/tf_core/tf_tcam_shared.c
+++ b/drivers/net/bnxt/tf_core/tf_tcam_shared.c
@@ -279,18 +279,6 @@ tf_tcam_shared_bind(struct tf *tfp,
if (rc)
return rc;
- rc = tf_tcam_shared_get_slices(tfp,
- dev,
- &num_slices);
- if (rc)
- return rc;
-
- if (num_slices > 1) {
- TFP_DRV_LOG(ERR,
- "Only single slice supported\n");
- return -EOPNOTSUPP;
- }
-
tf_tcam_shared_create_db(&tcam_shared_wc);
@@ -330,6 +318,18 @@ tf_tcam_shared_bind(struct tf *tfp,
tf_session_set_tcam_shared_db(tfp, (void *)tcam_shared_wc);
}
+
+ rc = tf_tcam_shared_get_slices(tfp,
+ dev,
+ &num_slices);
+ if (rc)
+ return rc;
+
+ if (num_slices > 1) {
+ TFP_DRV_LOG(ERR,
+ "Only single slice supported\n");
+ return -EOPNOTSUPP;
+ }
}
done:
return rc;
@@ -972,9 +972,9 @@ tf_tcam_shared_move_entry(struct tf *tfp,
sparms.idx = dphy_idx;
sparms.key = gparms.key;
sparms.mask = gparms.mask;
- sparms.key_size = gparms.key_size;
+ sparms.key_size = key_sz_bytes;
sparms.result = gparms.result;
- sparms.result_size = gparms.result_size;
+ sparms.result_size = remap_sz_bytes;
rc = tf_msg_tcam_entry_set(tfp, dev, &sparms);
if (rc) {
diff --git a/drivers/net/bnxt/tf_core/tf_util.c b/drivers/net/bnxt/tf_core/tf_util.c
index d100399d0a..c1b9be0755 100644
--- a/drivers/net/bnxt/tf_core/tf_util.c
+++ b/drivers/net/bnxt/tf_core/tf_util.c
@@ -76,6 +76,8 @@ tf_tbl_type_2_str(enum tf_tbl_type tbl_type)
switch (tbl_type) {
case TF_TBL_TYPE_FULL_ACT_RECORD:
return "Full Action record";
+ case TF_TBL_TYPE_COMPACT_ACT_RECORD:
+ return "Compact Action record";
case TF_TBL_TYPE_MCAST_GROUPS:
return "Multicast Groups";
case TF_TBL_TYPE_ACT_ENCAP_8B:
@@ -96,6 +98,14 @@ tf_tbl_type_2_str(enum tf_tbl_type tbl_type)
return "Stats 64B";
case TF_TBL_TYPE_ACT_MODIFY_IPV4:
return "Modify IPv4";
+ case TF_TBL_TYPE_ACT_MODIFY_8B:
+ return "Modify 8B";
+ case TF_TBL_TYPE_ACT_MODIFY_16B:
+ return "Modify 16B";
+ case TF_TBL_TYPE_ACT_MODIFY_32B:
+ return "Modify 32B";
+ case TF_TBL_TYPE_ACT_MODIFY_64B:
+ return "Modify 64B";
case TF_TBL_TYPE_METER_PROF:
return "Meter Profile";
case TF_TBL_TYPE_METER_INST:
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index dbf85e4eda..183bae66c5 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -384,6 +384,7 @@ ulp_ctx_shared_session_open(struct bnxt *bp,
size_t copy_nbytes;
uint32_t ulp_dev_id = BNXT_ULP_DEVICE_ID_LAST;
int32_t rc = 0;
+ uint8_t app_id;
/* only perform this if shared session is enabled. */
if (!bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx))
@@ -422,6 +423,12 @@ ulp_ctx_shared_session_open(struct bnxt *bp,
if (rc)
return rc;
+ rc = bnxt_ulp_cntxt_app_id_get(bp->ulp_ctx, &app_id);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Unable to get the app id from ulp.\n");
+ return -EINVAL;
+ }
+
rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &ulp_dev_id);
if (rc) {
BNXT_TF_DBG(ERR, "Unable to get device id from ulp.\n");
@@ -445,6 +452,10 @@ ulp_ctx_shared_session_open(struct bnxt *bp,
parms.shadow_copy = true;
parms.bp = bp;
+ if (app_id == 0 || app_id == 3)
+ parms.wc_num_slices = TF_WC_TCAM_2_SLICE_PER_ROW;
+ else
+ parms.wc_num_slices = TF_WC_TCAM_1_SLICE_PER_ROW;
/*
* Open the session here, but the collect the resources during the
@@ -516,6 +527,7 @@ ulp_ctx_session_open(struct bnxt *bp,
struct tf_open_session_parms params;
struct tf_session_resources *resources;
uint32_t ulp_dev_id = BNXT_ULP_DEVICE_ID_LAST;
+ uint8_t app_id;
memset(¶ms, 0, sizeof(params));
@@ -529,6 +541,12 @@ ulp_ctx_session_open(struct bnxt *bp,
params.shadow_copy = true;
+ rc = bnxt_ulp_cntxt_app_id_get(bp->ulp_ctx, &app_id);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Unable to get the app id from ulp.\n");
+ return -EINVAL;
+ }
+
rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &ulp_dev_id);
if (rc) {
BNXT_TF_DBG(ERR, "Unable to get device id from ulp.\n");
@@ -556,6 +574,11 @@ ulp_ctx_session_open(struct bnxt *bp,
return rc;
params.bp = bp;
+ if (app_id == 0 || app_id == 3)
+ params.wc_num_slices = TF_WC_TCAM_2_SLICE_PER_ROW;
+ else
+ params.wc_num_slices = TF_WC_TCAM_1_SLICE_PER_ROW;
+
rc = tf_open_session(&bp->tfp, ¶ms);
if (rc) {
BNXT_TF_DBG(ERR, "Failed to open TF session - %s, rc = %d\n",
diff --git a/meson_options.txt b/meson_options.txt
index 0e92734c49..f686e6d92a 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -46,3 +46,5 @@ option('tests', type: 'boolean', value: true, description:
'build unit tests')
option('use_hpet', type: 'boolean', value: false, description:
'use HPET timer in EAL')
+option('bnxt_tf_wc_slices', type: 'integer', min: 1, max: 4, value: 2,
+ description: 'Number of slices per WC TCAM entry')
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH 05/14] net/bnxt: add flow templates support for Thor
2021-09-01 14:24 [dpdk-dev] [PATCH 00/14] enhancements to host based flow table management Venkat Duvvuru
` (3 preceding siblings ...)
2021-09-01 14:24 ` [dpdk-dev] [PATCH 04/14] net/bnxt: add Thor SRAM mgr model Venkat Duvvuru
@ 2021-09-01 14:24 ` Venkat Duvvuru
2021-09-01 14:24 ` [dpdk-dev] [PATCH 06/14] net/bnxt: add support for tunnel offloads Venkat Duvvuru
` (9 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-01 14:24 UTC (permalink / raw)
To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Template adds non-VFR based support for testpmd with:
matches to include
- DMAC, SIP, DIP, Proto, Sport, Dport
- SIP, DIP, Proto, Sport, Dport
actions:
- count, drop
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
---
drivers/net/bnxt/tf_ulp/bnxt_tf_common.h | 6 +
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 36 +++---
drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 12 ++
.../bnxt/tf_ulp/generic_templates/meson.build | 17 ++-
.../ulp_template_db_thor_class.c | 1 -
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 122 +++++++++++++++++-
drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 26 +++-
drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c | 5 +
drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 111 +++++++++++++++-
drivers/net/bnxt/tf_ulp/ulp_matcher.c | 13 ++
drivers/net/bnxt/tf_ulp/ulp_port_db.c | 15 ++-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 9 +-
drivers/net/bnxt/tf_ulp/ulp_tun.c | 20 +++
drivers/net/bnxt/tf_ulp/ulp_utils.c | 8 +-
16 files changed, 356 insertions(+), 49 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
index f59da41e54..e0ebed3fed 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
@@ -13,6 +13,12 @@
#define BNXT_TF_DBG(lvl, fmt, args...) PMD_DRV_LOG(lvl, fmt, ## args)
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#define BNXT_TF_INF(fmt, args...) PMD_DRV_LOG(INFO, fmt, ## args)
+#else
+#define BNXT_TF_INF(fmt, args...)
+#endif
+
#define BNXT_ULP_EM_FLOWS 8192
#define BNXT_ULP_1M_FLOWS 1000000
#define BNXT_EEM_RX_GLOBAL_ID_MASK (BNXT_ULP_1M_FLOWS - 1)
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 183bae66c5..475c7a6cdf 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -698,6 +698,11 @@ ulp_eem_tbl_scope_init(struct bnxt *bp)
rc);
return rc;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+ BNXT_TF_DBG(DEBUG, "TableScope=0x%0x %d\n",
+ params.tbl_scope_id,
+ params.tbl_scope_id);
+#endif
rc = bnxt_ulp_cntxt_tbl_scope_id_set(bp->ulp_ctx, params.tbl_scope_id);
if (rc) {
BNXT_TF_DBG(ERR, "Unable to set table scope id\n");
@@ -825,6 +830,8 @@ ulp_ctx_init(struct bnxt *bp,
goto error_deinit;
}
+ /* TODO: For now we are overriding to APP:1 on this branch*/
+ bp->app_id = 1;
rc = bnxt_ulp_cntxt_app_id_set(bp->ulp_ctx, bp->app_id);
if (rc) {
BNXT_TF_DBG(ERR, "Unable to set app_id for ULP init.\n");
@@ -838,11 +845,6 @@ ulp_ctx_init(struct bnxt *bp,
goto error_deinit;
}
- if (devid == BNXT_ULP_DEVICE_ID_THOR) {
- ulp_data->ulp_flags &= ~BNXT_ULP_VF_REP_ENABLED;
- BNXT_TF_DBG(ERR, "Enabled non-VFR mode\n");
- }
-
/*
* Shared session must be created before first regular session but after
* the ulp_ctx is valid.
@@ -902,7 +904,7 @@ ulp_dparms_init(struct bnxt *bp, struct bnxt_ulp_context *ulp_ctx)
dparms->ext_flow_db_num_entries = bp->max_num_kflows * 1024;
/* GFID = 2 * num_flows */
dparms->mark_db_gfid_entries = dparms->ext_flow_db_num_entries * 2;
- BNXT_TF_DBG(DEBUG, "Set the number of flows = %"PRIu64"\n",
+ BNXT_TF_DBG(DEBUG, "Set the number of flows = %" PRIu64 "\n",
dparms->ext_flow_db_num_entries);
return 0;
@@ -1393,17 +1395,13 @@ bnxt_ulp_port_init(struct bnxt *bp)
uint32_t ulp_flags;
int32_t rc = 0;
+ if (!bp || !BNXT_TRUFLOW_EN(bp))
+ return rc;
+
if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
BNXT_TF_DBG(ERR,
"Skip ulp init for port: %d, not a TVF or PF\n",
- bp->eth_dev->data->port_id);
- return rc;
- }
-
- if (!BNXT_TRUFLOW_EN(bp)) {
- BNXT_TF_DBG(DEBUG,
- "Skip ulp init for port: %d, truflow is not enabled\n",
- bp->eth_dev->data->port_id);
+ bp->eth_dev->data->port_id);
return rc;
}
@@ -1524,6 +1522,9 @@ bnxt_ulp_port_deinit(struct bnxt *bp)
struct rte_pci_device *pci_dev;
struct rte_pci_addr *pci_addr;
+ if (!BNXT_TRUFLOW_EN(bp))
+ return;
+
if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
BNXT_TF_DBG(ERR,
"Skip ULP deinit port:%d, not a TVF or PF\n",
@@ -1531,13 +1532,6 @@ bnxt_ulp_port_deinit(struct bnxt *bp)
return;
}
- if (!BNXT_TRUFLOW_EN(bp)) {
- BNXT_TF_DBG(DEBUG,
- "Skip ULP deinit for port:%d, truflow is not enabled\n",
- bp->eth_dev->data->port_id);
- return;
- }
-
if (!bp->ulp_ctx) {
BNXT_TF_DBG(DEBUG, "ulp ctx already de-allocated\n");
return;
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
index 19e9dba356..238b1d9657 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
@@ -13,6 +13,9 @@
#include "ulp_port_db.h"
#include "ulp_ha_mgr.h"
#include <rte_malloc.h>
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#include "ulp_template_debug_proto.h"
+#endif
static int32_t
bnxt_ulp_flow_validate_args(const struct rte_flow_attr *attr,
@@ -222,6 +225,15 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
else if (ret == BNXT_TF_RC_FID)
goto return_fid;
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER
+ /* Dump the rte flow pattern */
+ ulp_parser_hdr_info_dump(¶ms);
+ /* Dump the rte flow action */
+ ulp_parser_act_info_dump(¶ms);
+#endif
+#endif
+
ret = ulp_matcher_pattern_match(¶ms, ¶ms.class_id);
if (ret != BNXT_TF_RC_SUCCESS)
goto free_fid;
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/meson.build b/drivers/net/bnxt/tf_ulp/generic_templates/meson.build
index b1e7b8cc32..16b27a2e24 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/meson.build
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/meson.build
@@ -2,12 +2,15 @@
# Copyright(c) 2018 Intel Corporation
# Copyright(c) 2020 Broadcom
+#Include the folder for headers
includes += include_directories('.')
+
+#Add the source files
sources += files(
- 'ulp_template_db_class.c',
- 'ulp_template_db_act.c',
- 'ulp_template_db_tbl.c',
- 'ulp_template_db_wh_plus_act.c',
- 'ulp_template_db_wh_plus_class.c',
- 'ulp_template_db_thor_act.c',
- 'ulp_template_db_thor_class.c')
+ 'ulp_template_db_class.c',
+ 'ulp_template_db_act.c',
+ 'ulp_template_db_tbl.c',
+ 'ulp_template_db_wh_plus_act.c',
+ 'ulp_template_db_wh_plus_class.c',
+ 'ulp_template_db_thor_act.c',
+ 'ulp_template_db_thor_class.c')
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
index 83f6152700..e342f340d9 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
@@ -6104,4 +6104,3 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.ident_bit_pos = 29
}
};
-
diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
index 13f71ed83b..22c51976ac 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
@@ -35,7 +35,7 @@ ulp_fc_mgr_shadow_mem_alloc(struct hw_fc_mem_info *parms, int size)
rte_mem_lock_page(parms->mem_va);
parms->mem_pa = (void *)(uintptr_t)rte_mem_virt2phy(parms->mem_va);
- if (parms->mem_pa == (void *)(uintptr_t)RTE_BAD_IOVA) {
+ if (parms->mem_pa == (void *)RTE_BAD_IOVA) {
BNXT_TF_DBG(ERR, "Allocate failed mem_pa\n");
return -ENOMEM;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
index ab6013f0e3..747a360aa0 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
@@ -116,7 +116,7 @@ ulp_flow_db_resource_func_get(struct ulp_fdb_resource_info *res_info)
func = (((res_info->nxt_resource_idx & ULP_FLOW_DB_RES_FUNC_MASK) >>
ULP_FLOW_DB_RES_FUNC_BITS) << ULP_FLOW_DB_RES_FUNC_UPPER);
- /* The resource func is split into upper and lower */
+ /* The reource func is split into upper and lower */
if (func & ULP_FLOW_DB_RES_FUNC_NEED_LOWER)
return (func | res_info->resource_func_lower);
return func;
@@ -654,6 +654,9 @@ ulp_flow_db_fid_alloc(struct bnxt_ulp_context *ulp_ctxt,
if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR)
ulp_flow_db_func_id_set(flow_db, *fid, func_id);
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+ BNXT_TF_DBG(ERR, "flow_id = %u:%u allocated\n", flow_type, *fid);
+#endif
/* return success */
return 0;
}
@@ -714,7 +717,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt,
if (params->critical_resource && fid_resource->resource_em_handle) {
BNXT_TF_DBG(DEBUG, "Ignore multiple critical resources\n");
- /* Ignore the multiple critical resources */
+ /* Ignore the multiple criticial resources */
params->critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO;
}
@@ -766,7 +769,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt,
* flow_type [in] Specify it is regular or default flow
* fid [in] The index to the flow entry
* params [in/out] The contents to be copied into params.
- * Only the critical_resource needs to be set by the caller.
+ * Onlythe critical_resource needs to be set by the caller.
*
* Returns 0 on success and negative on failure.
*/
@@ -937,6 +940,9 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt,
ulp_clear_tun_inner_entry(tun_tbl, fid);
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+ BNXT_TF_DBG(ERR, "flow_id = %u:%u freed\n", flow_type, fid);
+#endif
/* all good, return success */
return 0;
}
@@ -1921,3 +1927,113 @@ void ulp_flow_db_shared_session_set(struct ulp_flow_db_res_params *res,
if (res && (shared & BNXT_ULP_SHARED_SESSION_YES))
res->fdb_flags |= ULP_FDB_FLAG_SHARED_SESSION;
}
+
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+/*
+ * Dump the entry details
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ *
+ * returns none
+ */
+static void ulp_flow_db_res_dump(struct ulp_fdb_resource_info *r,
+ uint32_t *nxt_res)
+{
+ uint8_t res_func = ulp_flow_db_resource_func_get(r);
+
+ BNXT_TF_DBG(DEBUG, "Resource func = %x, nxt_resource_idx = %x\n",
+ res_func, (ULP_FLOW_DB_RES_NXT_MASK & r->nxt_resource_idx));
+ if (res_func == BNXT_ULP_RESOURCE_FUNC_EM_TABLE)
+ BNXT_TF_DBG(DEBUG, "EM Handle = 0x%016" PRIX64 "\n",
+ r->resource_em_handle);
+ else
+ BNXT_TF_DBG(DEBUG, "Handle = 0x%08x\n", r->resource_hndl);
+
+ *nxt_res = 0;
+ ULP_FLOW_DB_RES_NXT_SET(*nxt_res,
+ r->nxt_resource_idx);
+}
+
+/*
+ * Dump the flow entry details
+ *
+ * flow_db [in] Ptr to flow db
+ * fid [in] flow id
+ *
+ * returns none
+ */
+void
+ulp_flow_db_debug_fid_dump(struct bnxt_ulp_flow_db *flow_db, uint32_t fid)
+{
+ struct ulp_fdb_resource_info *r;
+ struct bnxt_ulp_flow_tbl *flow_tbl;
+ uint32_t nxt_res = 0;
+ uint32_t def_flag = 0, reg_flag = 0;
+
+ flow_tbl = &flow_db->flow_tbl;
+ if (ulp_flow_db_active_flows_bit_is_set(flow_db,
+ BNXT_ULP_FDB_TYPE_REGULAR, fid))
+ reg_flag = 1;
+ if (ulp_flow_db_active_flows_bit_is_set(flow_db,
+ BNXT_ULP_FDB_TYPE_DEFAULT, fid))
+ def_flag = 1;
+
+ if (reg_flag && def_flag)
+ BNXT_TF_DBG(DEBUG, "RID = %u\n", fid);
+ else if (reg_flag)
+ BNXT_TF_DBG(DEBUG, "Regular fid = %u and func id = %u\n",
+ fid, flow_db->func_id_tbl[fid]);
+ else if (def_flag)
+ BNXT_TF_DBG(DEBUG, "Default fid = %u\n", fid);
+ else
+ return;
+ /* iterate the resource */
+ nxt_res = fid;
+ do {
+ r = &flow_tbl->flow_resources[nxt_res];
+ ulp_flow_db_res_dump(r, &nxt_res);
+ } while (nxt_res);
+}
+
+/*
+ * Dump the flow database entry details
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ * flow_id [in] if zero then all fids are dumped.
+ *
+ * returns none
+ */
+int32_t ulp_flow_db_debug_dump(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t flow_id)
+{
+ struct bnxt_ulp_flow_db *flow_db;
+ struct bnxt_ulp_flow_tbl *flow_tbl;
+ uint32_t fid;
+
+ if (!ulp_ctxt || !ulp_ctxt->cfg_data) {
+ BNXT_TF_DBG(ERR, "Invalid Arguments\n");
+ return -EINVAL;
+ }
+ flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
+ if (!flow_db) {
+ BNXT_TF_DBG(ERR, "Invalid Arguments\n");
+ return -EINVAL;
+ }
+
+ flow_tbl = &flow_db->flow_tbl;
+ if (flow_id) {
+ ulp_flow_db_debug_fid_dump(flow_db, flow_id);
+ return 0;
+ }
+
+ BNXT_TF_DBG(DEBUG, "Dump flows = %u:%u\n",
+ flow_tbl->num_flows,
+ flow_tbl->num_resources);
+ BNXT_TF_DBG(DEBUG, "Head_index = %u, Tail_index = %u\n",
+ flow_tbl->head_index, flow_tbl->tail_index);
+ for (fid = 1; fid < flow_tbl->num_flows; fid++)
+ ulp_flow_db_debug_fid_dump(flow_db, fid);
+ BNXT_TF_DBG(DEBUG, "Done.\n");
+ return 0;
+}
+#endif
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
index 67afca8872..0ddfa6f66d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
@@ -18,7 +18,7 @@
/*
* Structure for the flow database resource information
- * The below structure is based on the below partitions
+ * The below structure is based on the below paritions
* nxt_resource_idx = dir[31],resource_func_upper[30:28],nxt_resource_idx[27:0]
* If resource_func is EM_TBL then use resource_em_handle.
* Else the other part of the union is used and
@@ -417,4 +417,28 @@ ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt);
void ulp_flow_db_shared_session_set(struct ulp_flow_db_res_params *res,
enum bnxt_ulp_shared_session shared);
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+/*
+ * Dump the flow entry details
+ *
+ * flow_db [in] Ptr to flow db
+ * fid [in] flow id
+ *
+ * returns none
+ */
+void
+ulp_flow_db_debug_fid_dump(struct bnxt_ulp_flow_db *flow_db, uint32_t fid);
+
+/*
+ * Dump the flow database entry details
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ * flow_id [in] if zero then all fids are dumped.
+ *
+ * returns none
+ */
+int32_t ulp_flow_db_debug_dump(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t flow_id);
+#endif
+
#endif /* _ULP_FLOW_DB_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
index 3c1af0b007..c6b2b1675d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
@@ -10,6 +10,11 @@
#include "ulp_mapper.h"
#include "ulp_flow_db.h"
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#include "ulp_template_debug_proto.h"
+#include "ulp_tf_debug.h"
+#endif
+
/* Retrieve the generic table initialization parameters for the tbl_idx */
static struct bnxt_ulp_generic_tbl_params*
ulp_mapper_gen_tbl_params_get(uint32_t tbl_idx)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
index 5f5b5d639e..bc5627ec5b 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
@@ -185,7 +185,7 @@ ulp_ha_mgr_timer_cb(void *arg __rte_unused)
rc = ulp_ha_mgr_state_get(ulp_ctx, &curr_state);
if (rc) {
/*
- * This shouldn't happen, if it does, reset the timer
+ * This shouldn't happen, if it does, resetart the timer
* and try again next time.
*/
BNXT_TF_DBG(ERR, "Failed(%d) to get state.\n",
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index f3a60cc880..7fc3767b33 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -22,6 +22,11 @@
#include "ulp_ha_mgr.h"
#include "bnxt_tf_pmd_shim.h"
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#include "ulp_template_debug_proto.h"
+#include "ulp_tf_debug.h"
+#endif
+
static uint8_t mapper_fld_zeros[16] = { 0 };
static uint8_t mapper_fld_ones[16] = {
@@ -156,6 +161,13 @@ ulp_mapper_resource_ident_allocate(struct bnxt_ulp_context *ulp_ctx,
tf_free_identifier(tfp, &fparms);
return rc;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ BNXT_TF_DBG(DEBUG, "Allocated Glb Res Ident [%s][%d][%d] = 0x%04x\n",
+ tf_dir_2_str(iparms.dir),
+ glb_res->glb_regfile_index, iparms.ident_type, iparms.id);
+#endif
+#endif
return rc;
}
@@ -216,6 +228,13 @@ ulp_mapper_resource_index_tbl_alloc(struct bnxt_ulp_context *ulp_ctx,
tf_free_tbl_entry(tfp, &free_parms);
return rc;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ BNXT_TF_DBG(DEBUG, "Allocated Glb Res Index [%s][%d][%d] = 0x%04x\n",
+ tf_dir_2_str(aparms.dir),
+ glb_res->glb_regfile_index, aparms.type, aparms.idx);
+#endif
+#endif
return rc;
}
@@ -784,6 +803,9 @@ ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms,
tf_ident_2_str(iparms.ident_type));
return rc;
}
+ BNXT_TF_INF("Alloc ident %s:%s.success.\n",
+ tf_dir_2_str(iparms.dir),
+ tf_ident_2_str(iparms.ident_type));
id = (uint64_t)tfp_cpu_to_be_64(iparms.id);
if (ulp_regfile_write(parms->regfile, idx, id)) {
@@ -813,6 +835,11 @@ ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms,
} else {
*val = iparms.id;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_ident_field_dump("Ident", ident, tbl, iparms.id);
+#endif
+#endif
return 0;
error:
@@ -877,6 +904,10 @@ ulp_mapper_ident_extract(struct bnxt_ulp_mapper_parms *parms,
sparms.search_id);
return rc;
}
+ BNXT_TF_INF("Search ident %s:%s:%x.success.\n",
+ tf_dir_2_str(sparms.dir),
+ tf_tbl_type_2_str(sparms.ident_type),
+ sparms.search_id);
/* Write it to the regfile */
id = (uint64_t)tfp_cpu_to_be_64(sparms.search_id);
@@ -904,6 +935,11 @@ ulp_mapper_ident_extract(struct bnxt_ulp_mapper_parms *parms,
goto error;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_ident_field_dump("Ident", ident, tbl, sparms.search_id);
+#endif
+#endif
return 0;
error:
@@ -996,7 +1032,7 @@ ulp_mapper_field_src_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
idx = tfp_be_to_cpu_16(idx);
- if (idx >= BNXT_ULP_CF_IDX_LAST || bytelen > sizeof(uint64_t)) {
+ if (idx >= BNXT_ULP_CF_IDX_LAST || bytelen > sizeof(uint32_t)) {
BNXT_TF_DBG(ERR, "comp field [%d] read oob %d\n", idx,
bytelen);
return -EINVAL;
@@ -1448,7 +1484,16 @@ ulp_mapper_field_opc_process(struct bnxt_ulp_mapper_parms *parms,
break;
}
- return rc;
+ if (!rc) {
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ if (fld->field_src1 != BNXT_ULP_FIELD_SRC_ZERO)
+ ulp_mapper_field_dump(name, fld, blob, write_idx, val,
+ val_len);
+#endif
+#endif
+ return rc;
+ }
error:
BNXT_TF_DBG(ERR, "Error in %s:%s process %u:%u\n", name,
fld->description, (val) ? write_idx : 0, val_len);
@@ -1500,8 +1545,15 @@ ulp_mapper_tbl_result_build(struct bnxt_ulp_mapper_parms *parms,
}
/* if encap bit swap is enabled perform the bit swap */
- if (parms->device_params->encap_byte_swap && encap_flds)
+ if (parms->device_params->encap_byte_swap && encap_flds) {
ulp_blob_perform_encap_swap(data);
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ BNXT_TF_DBG(INFO, "Dump after encap swap\n");
+ ulp_mapper_blob_dump(data);
+#endif
+#endif
+ }
return rc;
}
@@ -1725,6 +1777,9 @@ ulp_mapper_tcam_tbl_entry_write(struct bnxt_ulp_mapper_parms *parms,
tf_dir_2_str(sparms.dir), sparms.idx);
return -EIO;
}
+ BNXT_TF_INF("tcam[%s][%s][%x] write success.\n",
+ tf_tcam_tbl_2_str(sparms.tcam_tbl_type),
+ tf_dir_2_str(sparms.dir), sparms.idx);
/* Mark action */
rc = ulp_mapper_mark_act_ptr_process(parms, tbl);
@@ -1733,6 +1788,11 @@ ulp_mapper_tcam_tbl_entry_write(struct bnxt_ulp_mapper_parms *parms,
return rc;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_tcam_entry_dump("TCAM", idx, tbl, key, mask, data);
+#endif
+#endif
return rc;
}
@@ -1838,6 +1898,12 @@ static void ulp_mapper_wc_tcam_tbl_post_process(struct ulp_blob *blob)
{
ulp_blob_perform_64B_word_swap(blob);
ulp_blob_perform_64B_byte_swap(blob);
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ BNXT_TF_DBG(INFO, "Dump after wc tcam post process\n");
+ ulp_mapper_blob_dump(blob);
+#endif
+#endif
}
static int32_t
@@ -2134,6 +2200,11 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
BNXT_TF_DBG(ERR, "Failed to build the result blob\n");
return rc;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_result_dump("EM Result", tbl, &data);
+#endif
+#endif
if (dparms->dynamic_pad_en) {
uint32_t abits = dparms->em_blk_align_bits;
@@ -2148,6 +2219,11 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
ulp_blob_pad_align(&data, abits);
ulp_blob_perform_byte_reverse(&data, ULP_BITS_2_BYTE(abits));
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_result_dump("EM Merged Result", tbl, &data);
+#endif
+#endif
}
/* do the transpose for the internal EM keys */
@@ -2160,6 +2236,11 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
}
tmplen = ulp_blob_data_len_get(&key);
ulp_blob_perform_byte_reverse(&key, ULP_BITS_2_BYTE(tmplen));
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_result_dump("EM Key Transpose", tbl, &key);
+#endif
+#endif
}
rc = bnxt_ulp_cntxt_tbl_scope_id_get(parms->ulp_ctx,
@@ -2190,6 +2271,12 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return rc;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_em_dump("EM", &key, &data, &iparms);
+ /* tf_dump_tables(tfp, iparms.tbl_scope_id); */
+#endif
+#endif
/* Mark action process */
if (mtype == BNXT_ULP_FLOW_MEM_TYPE_EXT &&
tbl->resource_type == TF_MEM_EXTERNAL)
@@ -2479,6 +2566,9 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
sparms.idx, rc);
goto error;
}
+ BNXT_TF_INF("Index table[%s][%s][%x] write successful.\n",
+ tf_tbl_type_2_str(sparms.type),
+ tf_dir_2_str(sparms.dir), sparms.idx);
/* Calculate action record size */
if (tbl->resource_type == TF_TBL_TYPE_EXT) {
@@ -2635,6 +2725,10 @@ ulp_mapper_if_tbl_process(struct bnxt_ulp_mapper_parms *parms,
iftbl_params.idx, rc);
return rc;
}
+ BNXT_TF_INF("Set table[%s][%s][%x] success.\n",
+ tf_if_tbl_2_str(iftbl_params.type),
+ tf_dir_2_str(iftbl_params.dir),
+ iftbl_params.idx);
/*
* TBD: Need to look at the need to store idx in flow db for restore
@@ -2697,6 +2791,12 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms,
/* The_key is a byte array convert it to a search index */
cache_key = ulp_blob_data_get(&key, &tmplen);
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ BNXT_TF_DBG(DEBUG, "The gen_tbl[%u] key\n", tbl_idx);
+ ulp_mapper_blob_dump(&key);
+#endif
+#endif
/* get the generic table */
gen_tbl_list = &parms->mapper_data->gen_tbl_list[tbl_idx];
@@ -3495,6 +3595,11 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid)
for (tbl_idx = 0; tbl_idx < num_tbls && cond_goto;) {
tbl = &tbls[tbl_idx];
cond_goto = tbl->execute_info.cond_true_goto;
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_table_dump(tbl, tbl_idx);
+#endif
+#endif
/* Process the conditional func code opcodes */
if (ulp_mapper_func_info_process(parms, tbl)) {
BNXT_TF_DBG(ERR, "Failed to process cond update\n");
diff --git a/drivers/net/bnxt/tf_ulp/ulp_matcher.c b/drivers/net/bnxt/tf_ulp/ulp_matcher.c
index 67fa61fc7c..e06d8f6287 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_matcher.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_matcher.c
@@ -6,6 +6,10 @@
#include "ulp_matcher.h"
#include "ulp_utils.h"
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#include "ulp_template_debug_proto.h"
+#endif
+
/* Utility function to calculate the class matcher hash */
static uint32_t
ulp_matcher_class_hash_calculate(uint64_t hi_sig, uint64_t lo_sig)
@@ -95,6 +99,11 @@ ulp_matcher_pattern_match(struct ulp_rte_parser_params *params,
error:
BNXT_TF_DBG(DEBUG, "Did not find any matching template\n");
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+ BNXT_TF_DBG(DEBUG, "class_hid:0x%x, Hdr:%" PRIX64 " Fld:%" PRIX64 "\n",
+ class_hid, params->hdr_bitmap.bits,
+ params->fld_bitmap.bits);
+#endif
*class_id = 0;
return BNXT_TF_RC_ERROR;
}
@@ -142,6 +151,10 @@ ulp_matcher_action_match(struct ulp_rte_parser_params *params,
error:
BNXT_TF_DBG(DEBUG, "Did not find any matching action template\n");
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+ BNXT_TF_DBG(DEBUG, "act_hid:0x%x, Hdr:%" PRIX64 "\n",
+ act_hid, params->act_bitmap.bits);
+#endif
*act_id = 0;
return BNXT_TF_RC_ERROR;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.c b/drivers/net/bnxt/tf_ulp/ulp_port_db.c
index 4045473097..7d9865b3e3 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_port_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.c
@@ -7,9 +7,13 @@
#include "bnxt.h"
#include "bnxt_vnic.h"
#include "bnxt_tf_common.h"
+#include "bnxt_tf_pmd_shim.h"
#include "ulp_port_db.h"
#include "tfp.h"
-#include "bnxt_tf_pmd_shim.h"
+
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#include "ulp_tf_debug.h"
+#endif
static uint32_t
ulp_port_db_allocate_ifindex(struct bnxt_ulp_port_db *port_db)
@@ -151,12 +155,12 @@ int32_t ulp_port_db_dev_port_intf_update(struct bnxt_ulp_context *ulp_ctxt,
intf->type = bnxt_pmd_get_interface_type(port_id);
intf->drv_func_id = bnxt_pmd_get_fw_func_id(port_id,
- BNXT_ULP_INTF_TYPE_INVALID);
+ BNXT_ULP_INTF_TYPE_INVALID);
func = &port_db->ulp_func_id_tbl[intf->drv_func_id];
if (!func->func_valid) {
func->func_svif = bnxt_pmd_get_svif(port_id, true,
- BNXT_ULP_INTF_TYPE_INVALID);
+ BNXT_ULP_INTF_TYPE_INVALID);
func->func_spif = bnxt_pmd_get_phy_port_id(port_id);
func->func_parif =
bnxt_pmd_get_parif(port_id, BNXT_ULP_INTF_TYPE_INVALID);
@@ -202,6 +206,11 @@ int32_t ulp_port_db_dev_port_intf_update(struct bnxt_ulp_context *ulp_ctxt,
port_data->port_vport = bnxt_pmd_get_vport(port_id);
port_data->port_valid = true;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PORT
+ ulp_port_db_dump(port_db, intf, port_id);
+#endif
+#endif
return 0;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index 5fd52b8f36..79b9957781 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -8,6 +8,7 @@
#include "ulp_template_struct.h"
#include "bnxt_ulp.h"
#include "bnxt_tf_common.h"
+#include "bnxt_tf_pmd_shim.h"
#include "ulp_rte_parser.h"
#include "ulp_matcher.h"
#include "ulp_utils.h"
@@ -855,7 +856,7 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
BNXT_ULP_HDR_BIT_II_VLAN);
inner_flag = 1;
} else {
- BNXT_TF_DBG(ERR, "Error Parsing:Vlan hdr found without eth\n");
+ BNXT_TF_DBG(ERR, "Error Parsing:Vlan hdr found withtout eth\n");
return BNXT_TF_RC_ERROR;
}
/* Update the field protocol hdr bitmap */
@@ -1135,8 +1136,8 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
ulp_rte_prsr_fld_mask(params, &idx, size, &ver_spec, &ver_mask,
ULP_PRSR_ACT_DEFAULT);
/*
- * The TC and flow label field are ignored since OVS is setting
- * it for match and it is not supported.
+ * The TC and flow label field are ignored since OVS is
+ * setting it for match and it is not supported.
* This is a work around and
* shall be addressed in the future.
*/
@@ -2138,7 +2139,7 @@ ulp_rte_vf_act_handler(const struct rte_flow_action *action_item,
return BNXT_TF_RC_PARSE_ERR;
}
- bp = bnxt_get_bp(params->port_id);
+ bp = bnxt_pmd_get_bp(params->port_id);
if (bp == NULL) {
BNXT_TF_DBG(ERR, "Invalid bp\n");
return BNXT_TF_RC_ERROR;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.c b/drivers/net/bnxt/tf_ulp/ulp_tun.c
index cb8530d791..a1dd5b902c 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_tun.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_tun.c
@@ -3,6 +3,8 @@
* All rights reserved.
*/
+#include <sys/queue.h>
+
#include <rte_malloc.h>
#include "ulp_tun.h"
@@ -29,6 +31,15 @@ ulp_install_outer_tun_flow(struct ulp_rte_parser_params *params,
ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F1);
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER
+ /* Dump the rte flow pattern */
+ ulp_parser_hdr_info_dump(params);
+ /* Dump the rte flow action */
+ ulp_parser_act_info_dump(params);
+#endif
+#endif
+
ret = ulp_matcher_pattern_match(params, ¶ms->class_id);
if (ret != BNXT_TF_RC_SUCCESS)
goto err;
@@ -146,6 +157,15 @@ ulp_post_process_cache_inner_tun_flow(struct ulp_rte_parser_params *params,
struct ulp_per_port_flow_info *flow_info;
int ret;
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER
+ /* Dump the rte flow pattern */
+ ulp_parser_hdr_info_dump(params);
+ /* Dump the rte flow action */
+ ulp_parser_act_info_dump(params);
+#endif
+#endif
+
ret = ulp_matcher_pattern_match(params, ¶ms->class_id);
if (ret != BNXT_TF_RC_SUCCESS)
return BNXT_TF_RC_ERROR;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c
index bafb539c8d..1649e157f2 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c
@@ -62,7 +62,7 @@ ulp_regfile_read(struct ulp_regfile *regfile,
* data [in] The value is written into this variable. It is going to be in the
* same byte order as it was written.
*
- * size [in] The size in bytes of the value being written into this
+ * size [in] The size in bytes of the value beingritten into this
* variable.
*
* returns 0 on success
@@ -295,7 +295,7 @@ ulp_blob_push(struct ulp_blob *blob,
datalen,
data);
if (!rc) {
- BNXT_TF_DBG(ERR, "Failed to write blob\n");
+ BNXT_TF_DBG(ERR, "Failed ro write blob\n");
return 0;
}
blob->write_idx += datalen;
@@ -355,7 +355,7 @@ ulp_blob_insert(struct ulp_blob *blob, uint32_t offset,
datalen,
data);
if (!rc) {
- BNXT_TF_DBG(ERR, "Failed to write blob\n");
+ BNXT_TF_DBG(ERR, "Failed ro write blob\n");
return 0;
}
/* copy the previously stored data */
@@ -409,7 +409,7 @@ ulp_blob_push_64(struct ulp_blob *blob,
*
* data [in] 32-bit value to be added to the blob.
*
- * datalen [in] The number of bits to be added to the blob.
+ * datalen [in] The number of bits to be added ot the blob.
*
* The offset of the data is updated after each push of data.
* NULL returned on error, pointer pushed value otherwise.
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH 06/14] net/bnxt: add support for tunnel offloads
2021-09-01 14:24 [dpdk-dev] [PATCH 00/14] enhancements to host based flow table management Venkat Duvvuru
` (4 preceding siblings ...)
2021-09-01 14:24 ` [dpdk-dev] [PATCH 05/14] net/bnxt: add flow templates support for Thor Venkat Duvvuru
@ 2021-09-01 14:24 ` Venkat Duvvuru
2021-09-01 14:24 ` [dpdk-dev] [PATCH 07/14] net/bnxt: add support for dynamic encap action Venkat Duvvuru
` (8 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-01 14:24 UTC (permalink / raw)
To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Added support for tunnel offloads, this includes the support for
VXLAN decap action where two flows indicate tunnel offload rule. The
first flow indicate the tunnel properties and second flow indicates the
inner packet structure. The templates are updated to support this
feature.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com>
---
drivers/net/bnxt/tf_ulp/bnxt_tf_common.h | 4 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 12 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 20 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 212 +-
.../generic_templates/ulp_template_db_act.c | 2 +-
.../generic_templates/ulp_template_db_class.c | 8541 +++++++++++-----
.../generic_templates/ulp_template_db_enum.h | 210 +-
.../generic_templates/ulp_template_db_field.h | 654 +-
.../generic_templates/ulp_template_db_tbl.c | 645 +-
.../ulp_template_db_thor_class.c | 110 +-
.../ulp_template_db_wh_plus_act.c | 2 +-
.../ulp_template_db_wh_plus_class.c | 8577 +++++++++++------
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 46 +-
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h | 8 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 562 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 44 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 52 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.h | 6 +-
drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c | 31 +
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 134 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 10 +-
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 10 +-
drivers/net/bnxt/tf_ulp/ulp_tun.c | 541 +-
drivers/net/bnxt/tf_ulp/ulp_tun.h | 89 +-
24 files changed, 13810 insertions(+), 6712 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
index e0ebed3fed..6c4bcd2d90 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
@@ -37,9 +37,7 @@
enum bnxt_tf_rc {
BNXT_TF_RC_PARSE_ERR = -2,
BNXT_TF_RC_ERROR = -1,
- BNXT_TF_RC_SUCCESS = 0,
- BNXT_TF_RC_NORMAL = 1,
- BNXT_TF_RC_FID = 2,
+ BNXT_TF_RC_SUCCESS = 0
};
/* eth IPv4 Type */
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 475c7a6cdf..dfafd9ff5b 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -860,8 +860,6 @@ ulp_ctx_init(struct bnxt *bp,
if (rc)
goto error_deinit;
- ulp_tun_tbl_init(ulp_data->tun_tbl);
-
bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, &bp->tfp);
return rc;
@@ -2064,3 +2062,13 @@ bnxt_ulp_cntxt_entry_release(void)
{
rte_spinlock_unlock(&bnxt_ulp_ctxt_lock);
}
+
+/* Function to get the app tunnel details from the ulp context. */
+struct bnxt_flow_app_tun_ent *
+bnxt_ulp_cntxt_ptr2_app_tun_list_get(struct bnxt_ulp_context *ulp)
+{
+ if (!ulp || !ulp->cfg_data)
+ return NULL;
+
+ return ulp->cfg_data->app_tun;
+}
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
index 082ca501b6..006df9cbc5 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
@@ -47,6 +47,18 @@ enum bnxt_ulp_flow_mem_type {
BNXT_ULP_FLOW_MEM_TYPE_LAST = 3
};
+enum bnxt_rte_flow_item_type {
+ BNXT_RTE_FLOW_ITEM_TYPE_END = (uint32_t)INT_MIN,
+ BNXT_RTE_FLOW_ITEM_TYPE_VXLAN_DECAP,
+ BNXT_RTE_FLOW_ITEM_TYPE_LAST
+};
+
+enum bnxt_rte_flow_action_type {
+ BNXT_RTE_FLOW_ACTION_TYPE_END = (uint32_t)INT_MIN,
+ BNXT_RTE_FLOW_ACTION_TYPE_VXLAN_DECAP,
+ BNXT_RTE_FLOW_ACTION_TYPE_LAST
+};
+
struct bnxt_ulp_df_rule_info {
uint32_t def_port_flow_id;
uint8_t valid;
@@ -79,6 +91,7 @@ struct bnxt_ulp_data {
bool accum_stats;
uint8_t app_id;
uint8_t num_shared_clients;
+ struct bnxt_flow_app_tun_ent app_tun[BNXT_ULP_MAX_TUN_CACHE_ENTRIES];
};
struct bnxt_ulp_context {
@@ -258,9 +271,6 @@ bnxt_ulp_cntxt_acquire_fdb_lock(struct bnxt_ulp_context *ulp_ctx);
void
bnxt_ulp_cntxt_release_fdb_lock(struct bnxt_ulp_context *ulp_ctx);
-int32_t
-ulp_post_process_tun_flow(struct ulp_rte_parser_params *params);
-
struct bnxt_ulp_glb_resource_info *
bnxt_ulp_app_glb_resource_info_list_get(uint32_t *num_entries);
@@ -301,4 +311,8 @@ bnxt_ulp_cntxt_entry_release(void);
uint8_t
bnxt_ulp_cntxt_num_shared_clients_get(struct bnxt_ulp_context *ulp_ctx);
+
+struct bnxt_flow_app_tun_ent *
+bnxt_ulp_cntxt_ptr2_app_tun_list_get(struct bnxt_ulp_context *ulp);
+
#endif /* _BNXT_ULP_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
index 238b1d9657..3daf5942e8 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
@@ -12,6 +12,7 @@
#include "ulp_fc_mgr.h"
#include "ulp_port_db.h"
#include "ulp_ha_mgr.h"
+#include "ulp_tun.h"
#include <rte_malloc.h>
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
#include "ulp_template_debug_proto.h"
@@ -101,12 +102,13 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms,
mapper_cparms->act_prop = ¶ms->act_prop;
mapper_cparms->flow_id = params->fid;
mapper_cparms->parent_flow = params->parent_flow;
- mapper_cparms->parent_fid = params->parent_fid;
+ mapper_cparms->child_flow = params->child_flow;
mapper_cparms->fld_bitmap = ¶ms->fld_bitmap;
mapper_cparms->flow_pattern_id = params->flow_pattern_id;
mapper_cparms->act_pattern_id = params->act_pattern_id;
mapper_cparms->app_id = params->app_id;
mapper_cparms->port_id = params->port_id;
+ mapper_cparms->tun_idx = params->tun_idx;
/* update the signature fields into the computed field list */
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_HDR_SIG_ID,
@@ -218,12 +220,14 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
params.func_id = func_id;
params.priority = attr->priority;
params.port_id = dev->data->port_id;
+
/* Perform the rte flow post process */
- ret = bnxt_ulp_rte_parser_post_process(¶ms);
+ bnxt_ulp_rte_parser_post_process(¶ms);
+
+ /* do the tunnel offload process if any */
+ ret = ulp_tunnel_offload_process(¶ms);
if (ret == BNXT_TF_RC_ERROR)
goto free_fid;
- else if (ret == BNXT_TF_RC_FID)
- goto return_fid;
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER
@@ -249,7 +253,6 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
if (ret)
goto free_fid;
-return_fid:
bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
flow_id = (struct rte_flow *)((uintptr_t)fid);
@@ -314,11 +317,12 @@ bnxt_ulp_flow_validate(struct rte_eth_dev *dev,
goto parse_error;
/* Perform the rte flow post process */
- ret = bnxt_ulp_rte_parser_post_process(¶ms);
+ bnxt_ulp_rte_parser_post_process(¶ms);
+
+ /* do the tunnel offload process if any */
+ ret = ulp_tunnel_offload_process(¶ms);
if (ret == BNXT_TF_RC_ERROR)
goto parse_error;
- else if (ret == BNXT_TF_RC_FID)
- return 0;
ret = ulp_matcher_pattern_match(¶ms, &class_id);
@@ -475,11 +479,201 @@ bnxt_ulp_flow_query(struct rte_eth_dev *eth_dev,
return rc;
}
+/* Tunnel offload Apis */
+#define BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS 1
+
+static int
+bnxt_ulp_tunnel_decap_set(struct rte_eth_dev *eth_dev,
+ struct rte_flow_tunnel *tunnel,
+ struct rte_flow_action **pmd_actions,
+ uint32_t *num_of_actions,
+ struct rte_flow_error *error)
+{
+ struct bnxt_ulp_context *ulp_ctx;
+ struct bnxt_flow_app_tun_ent *tun_entry;
+ int32_t rc = 0;
+
+ ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev);
+ if (ulp_ctx == NULL) {
+ BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
+ "ULP context uninitialized");
+ return -EINVAL;
+ }
+
+ if (tunnel == NULL) {
+ BNXT_TF_DBG(ERR, "No tunnel specified\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "no tunnel specified");
+ return -EINVAL;
+ }
+
+ if (tunnel->type != RTE_FLOW_ITEM_TYPE_VXLAN) {
+ BNXT_TF_DBG(ERR, "Tunnel type unsupported\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "tunnel type unsupported");
+ return -EINVAL;
+ }
+
+ rc = ulp_app_tun_search_entry(ulp_ctx, tunnel, &tun_entry);
+ if (rc < 0) {
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "tunnel decap set failed");
+ return -EINVAL;
+ }
+
+ rc = ulp_app_tun_entry_set_decap_action(tun_entry);
+ if (rc < 0) {
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "tunnel decap set failed");
+ return -EINVAL;
+ }
+
+ *pmd_actions = &tun_entry->action;
+ *num_of_actions = BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS;
+ return 0;
+}
+
+static int
+bnxt_ulp_tunnel_match(struct rte_eth_dev *eth_dev,
+ struct rte_flow_tunnel *tunnel,
+ struct rte_flow_item **pmd_items,
+ uint32_t *num_of_items,
+ struct rte_flow_error *error)
+{
+ struct bnxt_ulp_context *ulp_ctx;
+ struct bnxt_flow_app_tun_ent *tun_entry;
+ int32_t rc = 0;
+
+ ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev);
+ if (ulp_ctx == NULL) {
+ BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
+ "ULP context uninitialized");
+ return -EINVAL;
+ }
+
+ if (tunnel == NULL) {
+ BNXT_TF_DBG(ERR, "No tunnel specified\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
+ "no tunnel specified");
+ return -EINVAL;
+ }
+
+ if (tunnel->type != RTE_FLOW_ITEM_TYPE_VXLAN) {
+ BNXT_TF_DBG(ERR, "Tunnel type unsupported\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
+ "tunnel type unsupported");
+ return -EINVAL;
+ }
+
+ rc = ulp_app_tun_search_entry(ulp_ctx, tunnel, &tun_entry);
+ if (rc < 0) {
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "tunnel match set failed");
+ return -EINVAL;
+ }
+
+ rc = ulp_app_tun_entry_set_decap_item(tun_entry);
+ if (rc < 0) {
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "tunnel match set failed");
+ return -EINVAL;
+ }
+
+ *pmd_items = &tun_entry->item;
+ *num_of_items = BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS;
+ return 0;
+}
+
+static int
+bnxt_ulp_tunnel_decap_release(struct rte_eth_dev *eth_dev,
+ struct rte_flow_action *pmd_actions,
+ uint32_t num_actions,
+ struct rte_flow_error *error)
+{
+ struct bnxt_ulp_context *ulp_ctx;
+ struct bnxt_flow_app_tun_ent *tun_entry;
+ const struct rte_flow_action *action_item = pmd_actions;
+
+ ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev);
+ if (ulp_ctx == NULL) {
+ BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
+ "ULP context uninitialized");
+ return -EINVAL;
+ }
+ if (num_actions != BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS) {
+ BNXT_TF_DBG(ERR, "num actions is invalid\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "num actions is invalid");
+ return -EINVAL;
+ }
+ while (action_item && action_item->type != RTE_FLOW_ACTION_TYPE_END) {
+ if (action_item->type == (typeof(tun_entry->action.type))
+ BNXT_RTE_FLOW_ACTION_TYPE_VXLAN_DECAP) {
+ tun_entry = ulp_app_tun_match_entry(ulp_ctx,
+ action_item->conf);
+ ulp_app_tun_entry_delete(tun_entry);
+ }
+ action_item++;
+ }
+ return 0;
+}
+
+static int
+bnxt_ulp_tunnel_item_release(struct rte_eth_dev *eth_dev,
+ struct rte_flow_item *pmd_items,
+ uint32_t num_items,
+ struct rte_flow_error *error)
+{
+ struct bnxt_ulp_context *ulp_ctx;
+ struct bnxt_flow_app_tun_ent *tun_entry;
+
+ ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev);
+ if (ulp_ctx == NULL) {
+ BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
+ "ULP context uninitialized");
+ return -EINVAL;
+ }
+ if (num_items != BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS) {
+ BNXT_TF_DBG(ERR, "num items is invalid\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "num items is invalid");
+ return -EINVAL;
+ }
+
+ tun_entry = ulp_app_tun_match_entry(ulp_ctx, pmd_items->spec);
+ ulp_app_tun_entry_delete(tun_entry);
+ return 0;
+}
+
const struct rte_flow_ops bnxt_ulp_rte_flow_ops = {
.validate = bnxt_ulp_flow_validate,
.create = bnxt_ulp_flow_create,
.destroy = bnxt_ulp_flow_destroy,
.flush = bnxt_ulp_flow_flush,
.query = bnxt_ulp_flow_query,
- .isolate = NULL
+ .isolate = NULL,
+ /* Tunnel offload callbacks */
+ .tunnel_decap_set = bnxt_ulp_tunnel_decap_set,
+ .tunnel_match = bnxt_ulp_tunnel_match,
+ .tunnel_action_decap_release = bnxt_ulp_tunnel_decap_release,
+ .tunnel_item_release = bnxt_ulp_tunnel_item_release,
+ .get_restore_info = NULL
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c
index e18f314856..0da6070d7d 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Wed Mar 17 11:31:19 2021 */
+/* date: Mon May 17 15:30:41 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
index 9c419f6a15..f74687acfa 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Wed Mar 17 11:31:19 2021 */
+/* date: Thu May 20 11:56:39 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -360,348 +360,510 @@ uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {
[BNXT_ULP_CLASS_HID_15db] = 342,
[BNXT_ULP_CLASS_HID_1151] = 343,
[BNXT_ULP_CLASS_HID_315d] = 344,
- [BNXT_ULP_CLASS_HID_34c6] = 345,
- [BNXT_ULP_CLASS_HID_0c22] = 346,
- [BNXT_ULP_CLASS_HID_1cbe] = 347,
- [BNXT_ULP_CLASS_HID_179a] = 348,
- [BNXT_ULP_CLASS_HID_59be] = 349,
- [BNXT_ULP_CLASS_HID_515a] = 350,
- [BNXT_ULP_CLASS_HID_1c72] = 351,
- [BNXT_ULP_CLASS_HID_171e] = 352,
- [BNXT_ULP_CLASS_HID_19c8] = 353,
- [BNXT_ULP_CLASS_HID_112c] = 354,
- [BNXT_ULP_CLASS_HID_4d68] = 355,
- [BNXT_ULP_CLASS_HID_444c] = 356,
- [BNXT_ULP_CLASS_HID_0e8c] = 357,
- [BNXT_ULP_CLASS_HID_09e0] = 358,
- [BNXT_ULP_CLASS_HID_1af0] = 359,
- [BNXT_ULP_CLASS_HID_15d4] = 360,
- [BNXT_ULP_CLASS_HID_1dd0] = 361,
- [BNXT_ULP_CLASS_HID_14f4] = 362,
- [BNXT_ULP_CLASS_HID_70b0] = 363,
- [BNXT_ULP_CLASS_HID_4854] = 364,
- [BNXT_ULP_CLASS_HID_3dd4] = 365,
- [BNXT_ULP_CLASS_HID_34f8] = 366,
- [BNXT_ULP_CLASS_HID_09e8] = 367,
- [BNXT_ULP_CLASS_HID_008c] = 368,
- [BNXT_ULP_CLASS_HID_34e6] = 369,
- [BNXT_ULP_CLASS_HID_0c02] = 370,
- [BNXT_ULP_CLASS_HID_1c9e] = 371,
- [BNXT_ULP_CLASS_HID_17ba] = 372,
- [BNXT_ULP_CLASS_HID_429e] = 373,
- [BNXT_ULP_CLASS_HID_5dba] = 374,
- [BNXT_ULP_CLASS_HID_2a16] = 375,
- [BNXT_ULP_CLASS_HID_2532] = 376,
- [BNXT_ULP_CLASS_HID_2da2] = 377,
- [BNXT_ULP_CLASS_HID_24fe] = 378,
- [BNXT_ULP_CLASS_HID_355a] = 379,
- [BNXT_ULP_CLASS_HID_0c76] = 380,
- [BNXT_ULP_CLASS_HID_13e6] = 381,
- [BNXT_ULP_CLASS_HID_7276] = 382,
- [BNXT_ULP_CLASS_HID_42d2] = 383,
- [BNXT_ULP_CLASS_HID_5dee] = 384,
- [BNXT_ULP_CLASS_HID_59de] = 385,
- [BNXT_ULP_CLASS_HID_513a] = 386,
- [BNXT_ULP_CLASS_HID_1c12] = 387,
- [BNXT_ULP_CLASS_HID_177e] = 388,
- [BNXT_ULP_CLASS_HID_0e92] = 389,
- [BNXT_ULP_CLASS_HID_09fe] = 390,
- [BNXT_ULP_CLASS_HID_5c1a] = 391,
- [BNXT_ULP_CLASS_HID_5746] = 392,
- [BNXT_ULP_CLASS_HID_79da] = 393,
- [BNXT_ULP_CLASS_HID_7106] = 394,
- [BNXT_ULP_CLASS_HID_3c1e] = 395,
- [BNXT_ULP_CLASS_HID_377a] = 396,
- [BNXT_ULP_CLASS_HID_2e9e] = 397,
- [BNXT_ULP_CLASS_HID_29fa] = 398,
- [BNXT_ULP_CLASS_HID_14d2] = 399,
- [BNXT_ULP_CLASS_HID_7742] = 400,
- [BNXT_ULP_CLASS_HID_3706] = 401,
- [BNXT_ULP_CLASS_HID_0fe2] = 402,
- [BNXT_ULP_CLASS_HID_1f7e] = 403,
- [BNXT_ULP_CLASS_HID_145a] = 404,
- [BNXT_ULP_CLASS_HID_417e] = 405,
- [BNXT_ULP_CLASS_HID_5e5a] = 406,
- [BNXT_ULP_CLASS_HID_29f6] = 407,
- [BNXT_ULP_CLASS_HID_26d2] = 408,
- [BNXT_ULP_CLASS_HID_2e42] = 409,
- [BNXT_ULP_CLASS_HID_271e] = 410,
- [BNXT_ULP_CLASS_HID_36ba] = 411,
- [BNXT_ULP_CLASS_HID_0f96] = 412,
- [BNXT_ULP_CLASS_HID_1006] = 413,
- [BNXT_ULP_CLASS_HID_7196] = 414,
- [BNXT_ULP_CLASS_HID_4132] = 415,
- [BNXT_ULP_CLASS_HID_5e0e] = 416,
- [BNXT_ULP_CLASS_HID_59fe] = 417,
- [BNXT_ULP_CLASS_HID_511a] = 418,
- [BNXT_ULP_CLASS_HID_1c32] = 419,
- [BNXT_ULP_CLASS_HID_175e] = 420,
- [BNXT_ULP_CLASS_HID_0eb2] = 421,
- [BNXT_ULP_CLASS_HID_09de] = 422,
- [BNXT_ULP_CLASS_HID_5c3a] = 423,
- [BNXT_ULP_CLASS_HID_5766] = 424,
- [BNXT_ULP_CLASS_HID_79fa] = 425,
- [BNXT_ULP_CLASS_HID_7126] = 426,
- [BNXT_ULP_CLASS_HID_3c3e] = 427,
- [BNXT_ULP_CLASS_HID_375a] = 428,
- [BNXT_ULP_CLASS_HID_2ebe] = 429,
- [BNXT_ULP_CLASS_HID_29da] = 430,
- [BNXT_ULP_CLASS_HID_14f2] = 431,
- [BNXT_ULP_CLASS_HID_7762] = 432,
- [BNXT_ULP_CLASS_HID_19e8] = 433,
- [BNXT_ULP_CLASS_HID_110c] = 434,
- [BNXT_ULP_CLASS_HID_4d48] = 435,
- [BNXT_ULP_CLASS_HID_446c] = 436,
- [BNXT_ULP_CLASS_HID_0eac] = 437,
- [BNXT_ULP_CLASS_HID_09c0] = 438,
- [BNXT_ULP_CLASS_HID_1ad0] = 439,
- [BNXT_ULP_CLASS_HID_15f4] = 440,
- [BNXT_ULP_CLASS_HID_39ec] = 441,
- [BNXT_ULP_CLASS_HID_3100] = 442,
- [BNXT_ULP_CLASS_HID_0210] = 443,
- [BNXT_ULP_CLASS_HID_1d34] = 444,
- [BNXT_ULP_CLASS_HID_2ea0] = 445,
- [BNXT_ULP_CLASS_HID_29c4] = 446,
- [BNXT_ULP_CLASS_HID_3ad4] = 447,
- [BNXT_ULP_CLASS_HID_35e8] = 448,
- [BNXT_ULP_CLASS_HID_5d80] = 449,
- [BNXT_ULP_CLASS_HID_54a4] = 450,
- [BNXT_ULP_CLASS_HID_29b4] = 451,
- [BNXT_ULP_CLASS_HID_20c8] = 452,
- [BNXT_ULP_CLASS_HID_7244] = 453,
- [BNXT_ULP_CLASS_HID_4d98] = 454,
- [BNXT_ULP_CLASS_HID_5e68] = 455,
- [BNXT_ULP_CLASS_HID_598c] = 456,
- [BNXT_ULP_CLASS_HID_1248] = 457,
- [BNXT_ULP_CLASS_HID_74d8] = 458,
- [BNXT_ULP_CLASS_HID_49a8] = 459,
- [BNXT_ULP_CLASS_HID_40cc] = 460,
- [BNXT_ULP_CLASS_HID_0b0c] = 461,
- [BNXT_ULP_CLASS_HID_0220] = 462,
- [BNXT_ULP_CLASS_HID_1730] = 463,
- [BNXT_ULP_CLASS_HID_7980] = 464,
- [BNXT_ULP_CLASS_HID_1db0] = 465,
- [BNXT_ULP_CLASS_HID_1494] = 466,
- [BNXT_ULP_CLASS_HID_70d0] = 467,
- [BNXT_ULP_CLASS_HID_4834] = 468,
- [BNXT_ULP_CLASS_HID_3db4] = 469,
- [BNXT_ULP_CLASS_HID_3498] = 470,
- [BNXT_ULP_CLASS_HID_0988] = 471,
- [BNXT_ULP_CLASS_HID_00ec] = 472,
- [BNXT_ULP_CLASS_HID_3f44] = 473,
- [BNXT_ULP_CLASS_HID_36a8] = 474,
- [BNXT_ULP_CLASS_HID_0b58] = 475,
- [BNXT_ULP_CLASS_HID_02bc] = 476,
- [BNXT_ULP_CLASS_HID_5f48] = 477,
- [BNXT_ULP_CLASS_HID_56ac] = 478,
- [BNXT_ULP_CLASS_HID_2b5c] = 479,
- [BNXT_ULP_CLASS_HID_2280] = 480,
- [BNXT_ULP_CLASS_HID_4000] = 481,
- [BNXT_ULP_CLASS_HID_5b64] = 482,
- [BNXT_ULP_CLASS_HID_2c14] = 483,
- [BNXT_ULP_CLASS_HID_2778] = 484,
- [BNXT_ULP_CLASS_HID_18f8] = 485,
- [BNXT_ULP_CLASS_HID_13dc] = 486,
- [BNXT_ULP_CLASS_HID_4c18] = 487,
- [BNXT_ULP_CLASS_HID_477c] = 488,
- [BNXT_ULP_CLASS_HID_1a88] = 489,
- [BNXT_ULP_CLASS_HID_15ec] = 490,
- [BNXT_ULP_CLASS_HID_4e28] = 491,
- [BNXT_ULP_CLASS_HID_490c] = 492,
- [BNXT_ULP_CLASS_HID_3a8c] = 493,
- [BNXT_ULP_CLASS_HID_35f0] = 494,
- [BNXT_ULP_CLASS_HID_06e0] = 495,
- [BNXT_ULP_CLASS_HID_01c4] = 496,
- [BNXT_ULP_CLASS_HID_1a08] = 497,
- [BNXT_ULP_CLASS_HID_12ec] = 498,
- [BNXT_ULP_CLASS_HID_4ea8] = 499,
- [BNXT_ULP_CLASS_HID_478c] = 500,
- [BNXT_ULP_CLASS_HID_0d4c] = 501,
- [BNXT_ULP_CLASS_HID_0a20] = 502,
- [BNXT_ULP_CLASS_HID_1930] = 503,
- [BNXT_ULP_CLASS_HID_1614] = 504,
- [BNXT_ULP_CLASS_HID_3a0c] = 505,
- [BNXT_ULP_CLASS_HID_32e0] = 506,
- [BNXT_ULP_CLASS_HID_01f0] = 507,
- [BNXT_ULP_CLASS_HID_1ed4] = 508,
- [BNXT_ULP_CLASS_HID_2d40] = 509,
- [BNXT_ULP_CLASS_HID_2a24] = 510,
- [BNXT_ULP_CLASS_HID_3934] = 511,
- [BNXT_ULP_CLASS_HID_3608] = 512,
- [BNXT_ULP_CLASS_HID_5e60] = 513,
- [BNXT_ULP_CLASS_HID_5744] = 514,
- [BNXT_ULP_CLASS_HID_2a54] = 515,
- [BNXT_ULP_CLASS_HID_2328] = 516,
- [BNXT_ULP_CLASS_HID_71a4] = 517,
- [BNXT_ULP_CLASS_HID_4e78] = 518,
- [BNXT_ULP_CLASS_HID_5d88] = 519,
- [BNXT_ULP_CLASS_HID_5a6c] = 520,
- [BNXT_ULP_CLASS_HID_11a8] = 521,
- [BNXT_ULP_CLASS_HID_7738] = 522,
- [BNXT_ULP_CLASS_HID_4a48] = 523,
- [BNXT_ULP_CLASS_HID_432c] = 524,
- [BNXT_ULP_CLASS_HID_08ec] = 525,
- [BNXT_ULP_CLASS_HID_01c0] = 526,
- [BNXT_ULP_CLASS_HID_14d0] = 527,
- [BNXT_ULP_CLASS_HID_7a60] = 528,
- [BNXT_ULP_CLASS_HID_1d90] = 529,
- [BNXT_ULP_CLASS_HID_14b4] = 530,
- [BNXT_ULP_CLASS_HID_70f0] = 531,
- [BNXT_ULP_CLASS_HID_4814] = 532,
- [BNXT_ULP_CLASS_HID_3d94] = 533,
- [BNXT_ULP_CLASS_HID_34b8] = 534,
- [BNXT_ULP_CLASS_HID_09a8] = 535,
- [BNXT_ULP_CLASS_HID_00cc] = 536,
- [BNXT_ULP_CLASS_HID_3f64] = 537,
- [BNXT_ULP_CLASS_HID_3688] = 538,
- [BNXT_ULP_CLASS_HID_0b78] = 539,
- [BNXT_ULP_CLASS_HID_029c] = 540,
- [BNXT_ULP_CLASS_HID_5f68] = 541,
- [BNXT_ULP_CLASS_HID_568c] = 542,
- [BNXT_ULP_CLASS_HID_2b7c] = 543,
- [BNXT_ULP_CLASS_HID_22a0] = 544,
- [BNXT_ULP_CLASS_HID_4020] = 545,
- [BNXT_ULP_CLASS_HID_5b44] = 546,
- [BNXT_ULP_CLASS_HID_2c34] = 547,
- [BNXT_ULP_CLASS_HID_2758] = 548,
- [BNXT_ULP_CLASS_HID_18d8] = 549,
- [BNXT_ULP_CLASS_HID_13fc] = 550,
- [BNXT_ULP_CLASS_HID_4c38] = 551,
- [BNXT_ULP_CLASS_HID_475c] = 552,
- [BNXT_ULP_CLASS_HID_1aa8] = 553,
- [BNXT_ULP_CLASS_HID_15cc] = 554,
- [BNXT_ULP_CLASS_HID_4e08] = 555,
- [BNXT_ULP_CLASS_HID_492c] = 556,
- [BNXT_ULP_CLASS_HID_3aac] = 557,
- [BNXT_ULP_CLASS_HID_35d0] = 558,
- [BNXT_ULP_CLASS_HID_06c0] = 559,
- [BNXT_ULP_CLASS_HID_01e4] = 560,
- [BNXT_ULP_CLASS_HID_4d32] = 561,
- [BNXT_ULP_CLASS_HID_54aa] = 562,
- [BNXT_ULP_CLASS_HID_0686] = 563,
- [BNXT_ULP_CLASS_HID_540e] = 564,
- [BNXT_ULP_CLASS_HID_2e3c] = 565,
- [BNXT_ULP_CLASS_HID_3a20] = 566,
- [BNXT_ULP_CLASS_HID_46f0] = 567,
- [BNXT_ULP_CLASS_HID_52e4] = 568,
- [BNXT_ULP_CLASS_HID_55e4] = 569,
- [BNXT_ULP_CLASS_HID_21f8] = 570,
- [BNXT_ULP_CLASS_HID_75e8] = 571,
- [BNXT_ULP_CLASS_HID_41fc] = 572,
- [BNXT_ULP_CLASS_HID_4d12] = 573,
- [BNXT_ULP_CLASS_HID_548a] = 574,
- [BNXT_ULP_CLASS_HID_3356] = 575,
- [BNXT_ULP_CLASS_HID_1ace] = 576,
- [BNXT_ULP_CLASS_HID_1a9a] = 577,
- [BNXT_ULP_CLASS_HID_4d46] = 578,
- [BNXT_ULP_CLASS_HID_2812] = 579,
- [BNXT_ULP_CLASS_HID_338a] = 580,
- [BNXT_ULP_CLASS_HID_06e6] = 581,
- [BNXT_ULP_CLASS_HID_546e] = 582,
- [BNXT_ULP_CLASS_HID_46ee] = 583,
- [BNXT_ULP_CLASS_HID_0d22] = 584,
- [BNXT_ULP_CLASS_HID_26e2] = 585,
- [BNXT_ULP_CLASS_HID_746a] = 586,
- [BNXT_ULP_CLASS_HID_1fa6] = 587,
- [BNXT_ULP_CLASS_HID_2d2e] = 588,
- [BNXT_ULP_CLASS_HID_4ef2] = 589,
- [BNXT_ULP_CLASS_HID_576a] = 590,
- [BNXT_ULP_CLASS_HID_30b6] = 591,
- [BNXT_ULP_CLASS_HID_192e] = 592,
- [BNXT_ULP_CLASS_HID_197a] = 593,
- [BNXT_ULP_CLASS_HID_4ea6] = 594,
- [BNXT_ULP_CLASS_HID_2bf2] = 595,
- [BNXT_ULP_CLASS_HID_306a] = 596,
- [BNXT_ULP_CLASS_HID_06c6] = 597,
- [BNXT_ULP_CLASS_HID_544e] = 598,
- [BNXT_ULP_CLASS_HID_46ce] = 599,
- [BNXT_ULP_CLASS_HID_0d02] = 600,
- [BNXT_ULP_CLASS_HID_26c2] = 601,
- [BNXT_ULP_CLASS_HID_744a] = 602,
- [BNXT_ULP_CLASS_HID_1f86] = 603,
- [BNXT_ULP_CLASS_HID_2d0e] = 604,
- [BNXT_ULP_CLASS_HID_2e1c] = 605,
- [BNXT_ULP_CLASS_HID_3a00] = 606,
- [BNXT_ULP_CLASS_HID_46d0] = 607,
- [BNXT_ULP_CLASS_HID_52c4] = 608,
- [BNXT_ULP_CLASS_HID_4e10] = 609,
- [BNXT_ULP_CLASS_HID_5a04] = 610,
- [BNXT_ULP_CLASS_HID_1f98] = 611,
- [BNXT_ULP_CLASS_HID_72f8] = 612,
- [BNXT_ULP_CLASS_HID_0a78] = 613,
- [BNXT_ULP_CLASS_HID_166c] = 614,
- [BNXT_ULP_CLASS_HID_233c] = 615,
- [BNXT_ULP_CLASS_HID_0f20] = 616,
- [BNXT_ULP_CLASS_HID_2a7c] = 617,
- [BNXT_ULP_CLASS_HID_3660] = 618,
- [BNXT_ULP_CLASS_HID_4330] = 619,
- [BNXT_ULP_CLASS_HID_2f24] = 620,
- [BNXT_ULP_CLASS_HID_5584] = 621,
- [BNXT_ULP_CLASS_HID_2198] = 622,
- [BNXT_ULP_CLASS_HID_7588] = 623,
- [BNXT_ULP_CLASS_HID_419c] = 624,
- [BNXT_ULP_CLASS_HID_7758] = 625,
- [BNXT_ULP_CLASS_HID_43ac] = 626,
- [BNXT_ULP_CLASS_HID_0c10] = 627,
- [BNXT_ULP_CLASS_HID_1864] = 628,
- [BNXT_ULP_CLASS_HID_30c8] = 629,
- [BNXT_ULP_CLASS_HID_1cdc] = 630,
- [BNXT_ULP_CLASS_HID_50cc] = 631,
- [BNXT_ULP_CLASS_HID_3d20] = 632,
- [BNXT_ULP_CLASS_HID_529c] = 633,
- [BNXT_ULP_CLASS_HID_3ef0] = 634,
- [BNXT_ULP_CLASS_HID_72e0] = 635,
- [BNXT_ULP_CLASS_HID_5ef4] = 636,
- [BNXT_ULP_CLASS_HID_2dfc] = 637,
- [BNXT_ULP_CLASS_HID_39e0] = 638,
- [BNXT_ULP_CLASS_HID_4530] = 639,
- [BNXT_ULP_CLASS_HID_5124] = 640,
- [BNXT_ULP_CLASS_HID_4df0] = 641,
- [BNXT_ULP_CLASS_HID_59e4] = 642,
- [BNXT_ULP_CLASS_HID_1c78] = 643,
- [BNXT_ULP_CLASS_HID_7118] = 644,
- [BNXT_ULP_CLASS_HID_0998] = 645,
- [BNXT_ULP_CLASS_HID_158c] = 646,
- [BNXT_ULP_CLASS_HID_20dc] = 647,
- [BNXT_ULP_CLASS_HID_0cc0] = 648,
- [BNXT_ULP_CLASS_HID_299c] = 649,
- [BNXT_ULP_CLASS_HID_3580] = 650,
- [BNXT_ULP_CLASS_HID_40d0] = 651,
- [BNXT_ULP_CLASS_HID_2cc4] = 652,
- [BNXT_ULP_CLASS_HID_55a4] = 653,
- [BNXT_ULP_CLASS_HID_21b8] = 654,
- [BNXT_ULP_CLASS_HID_75a8] = 655,
- [BNXT_ULP_CLASS_HID_41bc] = 656,
- [BNXT_ULP_CLASS_HID_7778] = 657,
- [BNXT_ULP_CLASS_HID_438c] = 658,
- [BNXT_ULP_CLASS_HID_0c30] = 659,
- [BNXT_ULP_CLASS_HID_1844] = 660,
- [BNXT_ULP_CLASS_HID_30e8] = 661,
- [BNXT_ULP_CLASS_HID_1cfc] = 662,
- [BNXT_ULP_CLASS_HID_50ec] = 663,
- [BNXT_ULP_CLASS_HID_3d00] = 664,
- [BNXT_ULP_CLASS_HID_52bc] = 665,
- [BNXT_ULP_CLASS_HID_3ed0] = 666,
- [BNXT_ULP_CLASS_HID_72c0] = 667,
- [BNXT_ULP_CLASS_HID_5ed4] = 668,
- [BNXT_ULP_CLASS_HID_3866] = 669,
- [BNXT_ULP_CLASS_HID_381e] = 670,
- [BNXT_ULP_CLASS_HID_3860] = 671,
- [BNXT_ULP_CLASS_HID_0454] = 672,
- [BNXT_ULP_CLASS_HID_3818] = 673,
- [BNXT_ULP_CLASS_HID_042c] = 674,
- [BNXT_ULP_CLASS_HID_3846] = 675,
- [BNXT_ULP_CLASS_HID_387e] = 676,
- [BNXT_ULP_CLASS_HID_3ba6] = 677,
- [BNXT_ULP_CLASS_HID_385e] = 678,
- [BNXT_ULP_CLASS_HID_3840] = 679,
- [BNXT_ULP_CLASS_HID_0474] = 680,
- [BNXT_ULP_CLASS_HID_3878] = 681,
- [BNXT_ULP_CLASS_HID_044c] = 682,
- [BNXT_ULP_CLASS_HID_3ba0] = 683,
- [BNXT_ULP_CLASS_HID_0794] = 684,
- [BNXT_ULP_CLASS_HID_3858] = 685,
- [BNXT_ULP_CLASS_HID_046c] = 686
+ [BNXT_ULP_CLASS_HID_3612] = 345,
+ [BNXT_ULP_CLASS_HID_66da] = 346,
+ [BNXT_ULP_CLASS_HID_6165] = 347,
+ [BNXT_ULP_CLASS_HID_2aa1] = 348,
+ [BNXT_ULP_CLASS_HID_09cd] = 349,
+ [BNXT_ULP_CLASS_HID_3845] = 350,
+ [BNXT_ULP_CLASS_HID_11e9] = 351,
+ [BNXT_ULP_CLASS_HID_4361] = 352,
+ [BNXT_ULP_CLASS_HID_218d] = 353,
+ [BNXT_ULP_CLASS_HID_5105] = 354,
+ [BNXT_ULP_CLASS_HID_0c89] = 355,
+ [BNXT_ULP_CLASS_HID_3e81] = 356,
+ [BNXT_ULP_CLASS_HID_1dad] = 357,
+ [BNXT_ULP_CLASS_HID_4ca5] = 358,
+ [BNXT_ULP_CLASS_HID_25c9] = 359,
+ [BNXT_ULP_CLASS_HID_57c1] = 360,
+ [BNXT_ULP_CLASS_HID_33ed] = 361,
+ [BNXT_ULP_CLASS_HID_65e5] = 362,
+ [BNXT_ULP_CLASS_HID_6dd9] = 363,
+ [BNXT_ULP_CLASS_HID_261d] = 364,
+ [BNXT_ULP_CLASS_HID_0571] = 365,
+ [BNXT_ULP_CLASS_HID_34f9] = 366,
+ [BNXT_ULP_CLASS_HID_1d55] = 367,
+ [BNXT_ULP_CLASS_HID_4fdd] = 368,
+ [BNXT_ULP_CLASS_HID_2d31] = 369,
+ [BNXT_ULP_CLASS_HID_5db9] = 370,
+ [BNXT_ULP_CLASS_HID_0035] = 371,
+ [BNXT_ULP_CLASS_HID_323d] = 372,
+ [BNXT_ULP_CLASS_HID_1111] = 373,
+ [BNXT_ULP_CLASS_HID_4019] = 374,
+ [BNXT_ULP_CLASS_HID_2975] = 375,
+ [BNXT_ULP_CLASS_HID_5b7d] = 376,
+ [BNXT_ULP_CLASS_HID_3f51] = 377,
+ [BNXT_ULP_CLASS_HID_6959] = 378,
+ [BNXT_ULP_CLASS_HID_0e85] = 379,
+ [BNXT_ULP_CLASS_HID_380d] = 380,
+ [BNXT_ULP_CLASS_HID_1f21] = 381,
+ [BNXT_ULP_CLASS_HID_4ea9] = 382,
+ [BNXT_ULP_CLASS_HID_1705] = 383,
+ [BNXT_ULP_CLASS_HID_418d] = 384,
+ [BNXT_ULP_CLASS_HID_2721] = 385,
+ [BNXT_ULP_CLASS_HID_57a9] = 386,
+ [BNXT_ULP_CLASS_HID_1a25] = 387,
+ [BNXT_ULP_CLASS_HID_342d] = 388,
+ [BNXT_ULP_CLASS_HID_2b01] = 389,
+ [BNXT_ULP_CLASS_HID_5a09] = 390,
+ [BNXT_ULP_CLASS_HID_2325] = 391,
+ [BNXT_ULP_CLASS_HID_5d2d] = 392,
+ [BNXT_ULP_CLASS_HID_3101] = 393,
+ [BNXT_ULP_CLASS_HID_6309] = 394,
+ [BNXT_ULP_CLASS_HID_0bad] = 395,
+ [BNXT_ULP_CLASS_HID_2535] = 396,
+ [BNXT_ULP_CLASS_HID_1869] = 397,
+ [BNXT_ULP_CLASS_HID_4bf1] = 398,
+ [BNXT_ULP_CLASS_HID_136d] = 399,
+ [BNXT_ULP_CLASS_HID_43f5] = 400,
+ [BNXT_ULP_CLASS_HID_2129] = 401,
+ [BNXT_ULP_CLASS_HID_53b1] = 402,
+ [BNXT_ULP_CLASS_HID_072d] = 403,
+ [BNXT_ULP_CLASS_HID_3135] = 404,
+ [BNXT_ULP_CLASS_HID_1429] = 405,
+ [BNXT_ULP_CLASS_HID_4731] = 406,
+ [BNXT_ULP_CLASS_HID_2f6d] = 407,
+ [BNXT_ULP_CLASS_HID_5f75] = 408,
+ [BNXT_ULP_CLASS_HID_3d69] = 409,
+ [BNXT_ULP_CLASS_HID_6f71] = 410,
+ [BNXT_ULP_CLASS_HID_0dbd] = 411,
+ [BNXT_ULP_CLASS_HID_3f25] = 412,
+ [BNXT_ULP_CLASS_HID_1239] = 413,
+ [BNXT_ULP_CLASS_HID_4da1] = 414,
+ [BNXT_ULP_CLASS_HID_153d] = 415,
+ [BNXT_ULP_CLASS_HID_45a5] = 416,
+ [BNXT_ULP_CLASS_HID_3bb9] = 417,
+ [BNXT_ULP_CLASS_HID_55a1] = 418,
+ [BNXT_ULP_CLASS_HID_193d] = 419,
+ [BNXT_ULP_CLASS_HID_4b25] = 420,
+ [BNXT_ULP_CLASS_HID_2e39] = 421,
+ [BNXT_ULP_CLASS_HID_5921] = 422,
+ [BNXT_ULP_CLASS_HID_213d] = 423,
+ [BNXT_ULP_CLASS_HID_5125] = 424,
+ [BNXT_ULP_CLASS_HID_3739] = 425,
+ [BNXT_ULP_CLASS_HID_093d] = 426,
+ [BNXT_ULP_CLASS_HID_684d] = 427,
+ [BNXT_ULP_CLASS_HID_2389] = 428,
+ [BNXT_ULP_CLASS_HID_00e5] = 429,
+ [BNXT_ULP_CLASS_HID_316d] = 430,
+ [BNXT_ULP_CLASS_HID_18c1] = 431,
+ [BNXT_ULP_CLASS_HID_4a49] = 432,
+ [BNXT_ULP_CLASS_HID_28a5] = 433,
+ [BNXT_ULP_CLASS_HID_582d] = 434,
+ [BNXT_ULP_CLASS_HID_05a1] = 435,
+ [BNXT_ULP_CLASS_HID_37a9] = 436,
+ [BNXT_ULP_CLASS_HID_1485] = 437,
+ [BNXT_ULP_CLASS_HID_458d] = 438,
+ [BNXT_ULP_CLASS_HID_2ce1] = 439,
+ [BNXT_ULP_CLASS_HID_5ee9] = 440,
+ [BNXT_ULP_CLASS_HID_3ac5] = 441,
+ [BNXT_ULP_CLASS_HID_6ccd] = 442,
+ [BNXT_ULP_CLASS_HID_0b11] = 443,
+ [BNXT_ULP_CLASS_HID_3d99] = 444,
+ [BNXT_ULP_CLASS_HID_1ab5] = 445,
+ [BNXT_ULP_CLASS_HID_4b3d] = 446,
+ [BNXT_ULP_CLASS_HID_1291] = 447,
+ [BNXT_ULP_CLASS_HID_4419] = 448,
+ [BNXT_ULP_CLASS_HID_22b5] = 449,
+ [BNXT_ULP_CLASS_HID_523d] = 450,
+ [BNXT_ULP_CLASS_HID_1fb1] = 451,
+ [BNXT_ULP_CLASS_HID_31b9] = 452,
+ [BNXT_ULP_CLASS_HID_2e95] = 453,
+ [BNXT_ULP_CLASS_HID_5f9d] = 454,
+ [BNXT_ULP_CLASS_HID_26b1] = 455,
+ [BNXT_ULP_CLASS_HID_58b9] = 456,
+ [BNXT_ULP_CLASS_HID_3495] = 457,
+ [BNXT_ULP_CLASS_HID_669d] = 458,
+ [BNXT_ULP_CLASS_HID_0e39] = 459,
+ [BNXT_ULP_CLASS_HID_20a1] = 460,
+ [BNXT_ULP_CLASS_HID_1dfd] = 461,
+ [BNXT_ULP_CLASS_HID_4e65] = 462,
+ [BNXT_ULP_CLASS_HID_16f9] = 463,
+ [BNXT_ULP_CLASS_HID_4661] = 464,
+ [BNXT_ULP_CLASS_HID_24bd] = 465,
+ [BNXT_ULP_CLASS_HID_5625] = 466,
+ [BNXT_ULP_CLASS_HID_02b9] = 467,
+ [BNXT_ULP_CLASS_HID_34a1] = 468,
+ [BNXT_ULP_CLASS_HID_11bd] = 469,
+ [BNXT_ULP_CLASS_HID_42a5] = 470,
+ [BNXT_ULP_CLASS_HID_2af9] = 471,
+ [BNXT_ULP_CLASS_HID_5ae1] = 472,
+ [BNXT_ULP_CLASS_HID_38fd] = 473,
+ [BNXT_ULP_CLASS_HID_6ae5] = 474,
+ [BNXT_ULP_CLASS_HID_0829] = 475,
+ [BNXT_ULP_CLASS_HID_3ab1] = 476,
+ [BNXT_ULP_CLASS_HID_17ad] = 477,
+ [BNXT_ULP_CLASS_HID_4835] = 478,
+ [BNXT_ULP_CLASS_HID_10a9] = 479,
+ [BNXT_ULP_CLASS_HID_4031] = 480,
+ [BNXT_ULP_CLASS_HID_3e2d] = 481,
+ [BNXT_ULP_CLASS_HID_5035] = 482,
+ [BNXT_ULP_CLASS_HID_1ca9] = 483,
+ [BNXT_ULP_CLASS_HID_4eb1] = 484,
+ [BNXT_ULP_CLASS_HID_2bad] = 485,
+ [BNXT_ULP_CLASS_HID_5cb5] = 486,
+ [BNXT_ULP_CLASS_HID_24a9] = 487,
+ [BNXT_ULP_CLASS_HID_54b1] = 488,
+ [BNXT_ULP_CLASS_HID_32ad] = 489,
+ [BNXT_ULP_CLASS_HID_0ca9] = 490,
+ [BNXT_ULP_CLASS_HID_7f35] = 491,
+ [BNXT_ULP_CLASS_HID_34f1] = 492,
+ [BNXT_ULP_CLASS_HID_179d] = 493,
+ [BNXT_ULP_CLASS_HID_2615] = 494,
+ [BNXT_ULP_CLASS_HID_0fb9] = 495,
+ [BNXT_ULP_CLASS_HID_5d31] = 496,
+ [BNXT_ULP_CLASS_HID_3fdd] = 497,
+ [BNXT_ULP_CLASS_HID_4f55] = 498,
+ [BNXT_ULP_CLASS_HID_12d9] = 499,
+ [BNXT_ULP_CLASS_HID_20d1] = 500,
+ [BNXT_ULP_CLASS_HID_03fd] = 501,
+ [BNXT_ULP_CLASS_HID_52f5] = 502,
+ [BNXT_ULP_CLASS_HID_3b99] = 503,
+ [BNXT_ULP_CLASS_HID_4991] = 504,
+ [BNXT_ULP_CLASS_HID_2dbd] = 505,
+ [BNXT_ULP_CLASS_HID_7bb5] = 506,
+ [BNXT_ULP_CLASS_HID_34c6] = 507,
+ [BNXT_ULP_CLASS_HID_0c22] = 508,
+ [BNXT_ULP_CLASS_HID_1cbe] = 509,
+ [BNXT_ULP_CLASS_HID_179a] = 510,
+ [BNXT_ULP_CLASS_HID_59be] = 511,
+ [BNXT_ULP_CLASS_HID_515a] = 512,
+ [BNXT_ULP_CLASS_HID_1c72] = 513,
+ [BNXT_ULP_CLASS_HID_171e] = 514,
+ [BNXT_ULP_CLASS_HID_19c8] = 515,
+ [BNXT_ULP_CLASS_HID_112c] = 516,
+ [BNXT_ULP_CLASS_HID_4d68] = 517,
+ [BNXT_ULP_CLASS_HID_444c] = 518,
+ [BNXT_ULP_CLASS_HID_0e8c] = 519,
+ [BNXT_ULP_CLASS_HID_09e0] = 520,
+ [BNXT_ULP_CLASS_HID_1af0] = 521,
+ [BNXT_ULP_CLASS_HID_15d4] = 522,
+ [BNXT_ULP_CLASS_HID_1dd0] = 523,
+ [BNXT_ULP_CLASS_HID_14f4] = 524,
+ [BNXT_ULP_CLASS_HID_70b0] = 525,
+ [BNXT_ULP_CLASS_HID_4854] = 526,
+ [BNXT_ULP_CLASS_HID_3dd4] = 527,
+ [BNXT_ULP_CLASS_HID_34f8] = 528,
+ [BNXT_ULP_CLASS_HID_09e8] = 529,
+ [BNXT_ULP_CLASS_HID_008c] = 530,
+ [BNXT_ULP_CLASS_HID_34e6] = 531,
+ [BNXT_ULP_CLASS_HID_0c02] = 532,
+ [BNXT_ULP_CLASS_HID_1c9e] = 533,
+ [BNXT_ULP_CLASS_HID_17ba] = 534,
+ [BNXT_ULP_CLASS_HID_429e] = 535,
+ [BNXT_ULP_CLASS_HID_5dba] = 536,
+ [BNXT_ULP_CLASS_HID_2a16] = 537,
+ [BNXT_ULP_CLASS_HID_2532] = 538,
+ [BNXT_ULP_CLASS_HID_2da2] = 539,
+ [BNXT_ULP_CLASS_HID_24fe] = 540,
+ [BNXT_ULP_CLASS_HID_355a] = 541,
+ [BNXT_ULP_CLASS_HID_0c76] = 542,
+ [BNXT_ULP_CLASS_HID_13e6] = 543,
+ [BNXT_ULP_CLASS_HID_7276] = 544,
+ [BNXT_ULP_CLASS_HID_42d2] = 545,
+ [BNXT_ULP_CLASS_HID_5dee] = 546,
+ [BNXT_ULP_CLASS_HID_59de] = 547,
+ [BNXT_ULP_CLASS_HID_513a] = 548,
+ [BNXT_ULP_CLASS_HID_1c12] = 549,
+ [BNXT_ULP_CLASS_HID_177e] = 550,
+ [BNXT_ULP_CLASS_HID_0e92] = 551,
+ [BNXT_ULP_CLASS_HID_09fe] = 552,
+ [BNXT_ULP_CLASS_HID_5c1a] = 553,
+ [BNXT_ULP_CLASS_HID_5746] = 554,
+ [BNXT_ULP_CLASS_HID_79da] = 555,
+ [BNXT_ULP_CLASS_HID_7106] = 556,
+ [BNXT_ULP_CLASS_HID_3c1e] = 557,
+ [BNXT_ULP_CLASS_HID_377a] = 558,
+ [BNXT_ULP_CLASS_HID_2e9e] = 559,
+ [BNXT_ULP_CLASS_HID_29fa] = 560,
+ [BNXT_ULP_CLASS_HID_14d2] = 561,
+ [BNXT_ULP_CLASS_HID_7742] = 562,
+ [BNXT_ULP_CLASS_HID_3706] = 563,
+ [BNXT_ULP_CLASS_HID_0fe2] = 564,
+ [BNXT_ULP_CLASS_HID_1f7e] = 565,
+ [BNXT_ULP_CLASS_HID_145a] = 566,
+ [BNXT_ULP_CLASS_HID_417e] = 567,
+ [BNXT_ULP_CLASS_HID_5e5a] = 568,
+ [BNXT_ULP_CLASS_HID_29f6] = 569,
+ [BNXT_ULP_CLASS_HID_26d2] = 570,
+ [BNXT_ULP_CLASS_HID_2e42] = 571,
+ [BNXT_ULP_CLASS_HID_271e] = 572,
+ [BNXT_ULP_CLASS_HID_36ba] = 573,
+ [BNXT_ULP_CLASS_HID_0f96] = 574,
+ [BNXT_ULP_CLASS_HID_1006] = 575,
+ [BNXT_ULP_CLASS_HID_7196] = 576,
+ [BNXT_ULP_CLASS_HID_4132] = 577,
+ [BNXT_ULP_CLASS_HID_5e0e] = 578,
+ [BNXT_ULP_CLASS_HID_59fe] = 579,
+ [BNXT_ULP_CLASS_HID_511a] = 580,
+ [BNXT_ULP_CLASS_HID_1c32] = 581,
+ [BNXT_ULP_CLASS_HID_175e] = 582,
+ [BNXT_ULP_CLASS_HID_0eb2] = 583,
+ [BNXT_ULP_CLASS_HID_09de] = 584,
+ [BNXT_ULP_CLASS_HID_5c3a] = 585,
+ [BNXT_ULP_CLASS_HID_5766] = 586,
+ [BNXT_ULP_CLASS_HID_79fa] = 587,
+ [BNXT_ULP_CLASS_HID_7126] = 588,
+ [BNXT_ULP_CLASS_HID_3c3e] = 589,
+ [BNXT_ULP_CLASS_HID_375a] = 590,
+ [BNXT_ULP_CLASS_HID_2ebe] = 591,
+ [BNXT_ULP_CLASS_HID_29da] = 592,
+ [BNXT_ULP_CLASS_HID_14f2] = 593,
+ [BNXT_ULP_CLASS_HID_7762] = 594,
+ [BNXT_ULP_CLASS_HID_19e8] = 595,
+ [BNXT_ULP_CLASS_HID_110c] = 596,
+ [BNXT_ULP_CLASS_HID_4d48] = 597,
+ [BNXT_ULP_CLASS_HID_446c] = 598,
+ [BNXT_ULP_CLASS_HID_0eac] = 599,
+ [BNXT_ULP_CLASS_HID_09c0] = 600,
+ [BNXT_ULP_CLASS_HID_1ad0] = 601,
+ [BNXT_ULP_CLASS_HID_15f4] = 602,
+ [BNXT_ULP_CLASS_HID_39ec] = 603,
+ [BNXT_ULP_CLASS_HID_3100] = 604,
+ [BNXT_ULP_CLASS_HID_0210] = 605,
+ [BNXT_ULP_CLASS_HID_1d34] = 606,
+ [BNXT_ULP_CLASS_HID_2ea0] = 607,
+ [BNXT_ULP_CLASS_HID_29c4] = 608,
+ [BNXT_ULP_CLASS_HID_3ad4] = 609,
+ [BNXT_ULP_CLASS_HID_35e8] = 610,
+ [BNXT_ULP_CLASS_HID_5d80] = 611,
+ [BNXT_ULP_CLASS_HID_54a4] = 612,
+ [BNXT_ULP_CLASS_HID_29b4] = 613,
+ [BNXT_ULP_CLASS_HID_20c8] = 614,
+ [BNXT_ULP_CLASS_HID_7244] = 615,
+ [BNXT_ULP_CLASS_HID_4d98] = 616,
+ [BNXT_ULP_CLASS_HID_5e68] = 617,
+ [BNXT_ULP_CLASS_HID_598c] = 618,
+ [BNXT_ULP_CLASS_HID_1248] = 619,
+ [BNXT_ULP_CLASS_HID_74d8] = 620,
+ [BNXT_ULP_CLASS_HID_49a8] = 621,
+ [BNXT_ULP_CLASS_HID_40cc] = 622,
+ [BNXT_ULP_CLASS_HID_0b0c] = 623,
+ [BNXT_ULP_CLASS_HID_0220] = 624,
+ [BNXT_ULP_CLASS_HID_1730] = 625,
+ [BNXT_ULP_CLASS_HID_7980] = 626,
+ [BNXT_ULP_CLASS_HID_1db0] = 627,
+ [BNXT_ULP_CLASS_HID_1494] = 628,
+ [BNXT_ULP_CLASS_HID_70d0] = 629,
+ [BNXT_ULP_CLASS_HID_4834] = 630,
+ [BNXT_ULP_CLASS_HID_3db4] = 631,
+ [BNXT_ULP_CLASS_HID_3498] = 632,
+ [BNXT_ULP_CLASS_HID_0988] = 633,
+ [BNXT_ULP_CLASS_HID_00ec] = 634,
+ [BNXT_ULP_CLASS_HID_3f44] = 635,
+ [BNXT_ULP_CLASS_HID_36a8] = 636,
+ [BNXT_ULP_CLASS_HID_0b58] = 637,
+ [BNXT_ULP_CLASS_HID_02bc] = 638,
+ [BNXT_ULP_CLASS_HID_5f48] = 639,
+ [BNXT_ULP_CLASS_HID_56ac] = 640,
+ [BNXT_ULP_CLASS_HID_2b5c] = 641,
+ [BNXT_ULP_CLASS_HID_2280] = 642,
+ [BNXT_ULP_CLASS_HID_4000] = 643,
+ [BNXT_ULP_CLASS_HID_5b64] = 644,
+ [BNXT_ULP_CLASS_HID_2c14] = 645,
+ [BNXT_ULP_CLASS_HID_2778] = 646,
+ [BNXT_ULP_CLASS_HID_18f8] = 647,
+ [BNXT_ULP_CLASS_HID_13dc] = 648,
+ [BNXT_ULP_CLASS_HID_4c18] = 649,
+ [BNXT_ULP_CLASS_HID_477c] = 650,
+ [BNXT_ULP_CLASS_HID_1a88] = 651,
+ [BNXT_ULP_CLASS_HID_15ec] = 652,
+ [BNXT_ULP_CLASS_HID_4e28] = 653,
+ [BNXT_ULP_CLASS_HID_490c] = 654,
+ [BNXT_ULP_CLASS_HID_3a8c] = 655,
+ [BNXT_ULP_CLASS_HID_35f0] = 656,
+ [BNXT_ULP_CLASS_HID_06e0] = 657,
+ [BNXT_ULP_CLASS_HID_01c4] = 658,
+ [BNXT_ULP_CLASS_HID_1a08] = 659,
+ [BNXT_ULP_CLASS_HID_12ec] = 660,
+ [BNXT_ULP_CLASS_HID_4ea8] = 661,
+ [BNXT_ULP_CLASS_HID_478c] = 662,
+ [BNXT_ULP_CLASS_HID_0d4c] = 663,
+ [BNXT_ULP_CLASS_HID_0a20] = 664,
+ [BNXT_ULP_CLASS_HID_1930] = 665,
+ [BNXT_ULP_CLASS_HID_1614] = 666,
+ [BNXT_ULP_CLASS_HID_3a0c] = 667,
+ [BNXT_ULP_CLASS_HID_32e0] = 668,
+ [BNXT_ULP_CLASS_HID_01f0] = 669,
+ [BNXT_ULP_CLASS_HID_1ed4] = 670,
+ [BNXT_ULP_CLASS_HID_2d40] = 671,
+ [BNXT_ULP_CLASS_HID_2a24] = 672,
+ [BNXT_ULP_CLASS_HID_3934] = 673,
+ [BNXT_ULP_CLASS_HID_3608] = 674,
+ [BNXT_ULP_CLASS_HID_5e60] = 675,
+ [BNXT_ULP_CLASS_HID_5744] = 676,
+ [BNXT_ULP_CLASS_HID_2a54] = 677,
+ [BNXT_ULP_CLASS_HID_2328] = 678,
+ [BNXT_ULP_CLASS_HID_71a4] = 679,
+ [BNXT_ULP_CLASS_HID_4e78] = 680,
+ [BNXT_ULP_CLASS_HID_5d88] = 681,
+ [BNXT_ULP_CLASS_HID_5a6c] = 682,
+ [BNXT_ULP_CLASS_HID_11a8] = 683,
+ [BNXT_ULP_CLASS_HID_7738] = 684,
+ [BNXT_ULP_CLASS_HID_4a48] = 685,
+ [BNXT_ULP_CLASS_HID_432c] = 686,
+ [BNXT_ULP_CLASS_HID_08ec] = 687,
+ [BNXT_ULP_CLASS_HID_01c0] = 688,
+ [BNXT_ULP_CLASS_HID_14d0] = 689,
+ [BNXT_ULP_CLASS_HID_7a60] = 690,
+ [BNXT_ULP_CLASS_HID_1d90] = 691,
+ [BNXT_ULP_CLASS_HID_14b4] = 692,
+ [BNXT_ULP_CLASS_HID_70f0] = 693,
+ [BNXT_ULP_CLASS_HID_4814] = 694,
+ [BNXT_ULP_CLASS_HID_3d94] = 695,
+ [BNXT_ULP_CLASS_HID_34b8] = 696,
+ [BNXT_ULP_CLASS_HID_09a8] = 697,
+ [BNXT_ULP_CLASS_HID_00cc] = 698,
+ [BNXT_ULP_CLASS_HID_3f64] = 699,
+ [BNXT_ULP_CLASS_HID_3688] = 700,
+ [BNXT_ULP_CLASS_HID_0b78] = 701,
+ [BNXT_ULP_CLASS_HID_029c] = 702,
+ [BNXT_ULP_CLASS_HID_5f68] = 703,
+ [BNXT_ULP_CLASS_HID_568c] = 704,
+ [BNXT_ULP_CLASS_HID_2b7c] = 705,
+ [BNXT_ULP_CLASS_HID_22a0] = 706,
+ [BNXT_ULP_CLASS_HID_4020] = 707,
+ [BNXT_ULP_CLASS_HID_5b44] = 708,
+ [BNXT_ULP_CLASS_HID_2c34] = 709,
+ [BNXT_ULP_CLASS_HID_2758] = 710,
+ [BNXT_ULP_CLASS_HID_18d8] = 711,
+ [BNXT_ULP_CLASS_HID_13fc] = 712,
+ [BNXT_ULP_CLASS_HID_4c38] = 713,
+ [BNXT_ULP_CLASS_HID_475c] = 714,
+ [BNXT_ULP_CLASS_HID_1aa8] = 715,
+ [BNXT_ULP_CLASS_HID_15cc] = 716,
+ [BNXT_ULP_CLASS_HID_4e08] = 717,
+ [BNXT_ULP_CLASS_HID_492c] = 718,
+ [BNXT_ULP_CLASS_HID_3aac] = 719,
+ [BNXT_ULP_CLASS_HID_35d0] = 720,
+ [BNXT_ULP_CLASS_HID_06c0] = 721,
+ [BNXT_ULP_CLASS_HID_01e4] = 722,
+ [BNXT_ULP_CLASS_HID_4d32] = 723,
+ [BNXT_ULP_CLASS_HID_54aa] = 724,
+ [BNXT_ULP_CLASS_HID_0686] = 725,
+ [BNXT_ULP_CLASS_HID_540e] = 726,
+ [BNXT_ULP_CLASS_HID_2e3c] = 727,
+ [BNXT_ULP_CLASS_HID_3a20] = 728,
+ [BNXT_ULP_CLASS_HID_46f0] = 729,
+ [BNXT_ULP_CLASS_HID_52e4] = 730,
+ [BNXT_ULP_CLASS_HID_55e4] = 731,
+ [BNXT_ULP_CLASS_HID_21f8] = 732,
+ [BNXT_ULP_CLASS_HID_75e8] = 733,
+ [BNXT_ULP_CLASS_HID_41fc] = 734,
+ [BNXT_ULP_CLASS_HID_4d12] = 735,
+ [BNXT_ULP_CLASS_HID_548a] = 736,
+ [BNXT_ULP_CLASS_HID_3356] = 737,
+ [BNXT_ULP_CLASS_HID_1ace] = 738,
+ [BNXT_ULP_CLASS_HID_1a9a] = 739,
+ [BNXT_ULP_CLASS_HID_4d46] = 740,
+ [BNXT_ULP_CLASS_HID_2812] = 741,
+ [BNXT_ULP_CLASS_HID_338a] = 742,
+ [BNXT_ULP_CLASS_HID_06e6] = 743,
+ [BNXT_ULP_CLASS_HID_546e] = 744,
+ [BNXT_ULP_CLASS_HID_46ee] = 745,
+ [BNXT_ULP_CLASS_HID_0d22] = 746,
+ [BNXT_ULP_CLASS_HID_26e2] = 747,
+ [BNXT_ULP_CLASS_HID_746a] = 748,
+ [BNXT_ULP_CLASS_HID_1fa6] = 749,
+ [BNXT_ULP_CLASS_HID_2d2e] = 750,
+ [BNXT_ULP_CLASS_HID_4ef2] = 751,
+ [BNXT_ULP_CLASS_HID_576a] = 752,
+ [BNXT_ULP_CLASS_HID_30b6] = 753,
+ [BNXT_ULP_CLASS_HID_192e] = 754,
+ [BNXT_ULP_CLASS_HID_197a] = 755,
+ [BNXT_ULP_CLASS_HID_4ea6] = 756,
+ [BNXT_ULP_CLASS_HID_2bf2] = 757,
+ [BNXT_ULP_CLASS_HID_306a] = 758,
+ [BNXT_ULP_CLASS_HID_06c6] = 759,
+ [BNXT_ULP_CLASS_HID_544e] = 760,
+ [BNXT_ULP_CLASS_HID_46ce] = 761,
+ [BNXT_ULP_CLASS_HID_0d02] = 762,
+ [BNXT_ULP_CLASS_HID_26c2] = 763,
+ [BNXT_ULP_CLASS_HID_744a] = 764,
+ [BNXT_ULP_CLASS_HID_1f86] = 765,
+ [BNXT_ULP_CLASS_HID_2d0e] = 766,
+ [BNXT_ULP_CLASS_HID_2e1c] = 767,
+ [BNXT_ULP_CLASS_HID_3a00] = 768,
+ [BNXT_ULP_CLASS_HID_46d0] = 769,
+ [BNXT_ULP_CLASS_HID_52c4] = 770,
+ [BNXT_ULP_CLASS_HID_4e10] = 771,
+ [BNXT_ULP_CLASS_HID_5a04] = 772,
+ [BNXT_ULP_CLASS_HID_1f98] = 773,
+ [BNXT_ULP_CLASS_HID_72f8] = 774,
+ [BNXT_ULP_CLASS_HID_0a78] = 775,
+ [BNXT_ULP_CLASS_HID_166c] = 776,
+ [BNXT_ULP_CLASS_HID_233c] = 777,
+ [BNXT_ULP_CLASS_HID_0f20] = 778,
+ [BNXT_ULP_CLASS_HID_2a7c] = 779,
+ [BNXT_ULP_CLASS_HID_3660] = 780,
+ [BNXT_ULP_CLASS_HID_4330] = 781,
+ [BNXT_ULP_CLASS_HID_2f24] = 782,
+ [BNXT_ULP_CLASS_HID_5584] = 783,
+ [BNXT_ULP_CLASS_HID_2198] = 784,
+ [BNXT_ULP_CLASS_HID_7588] = 785,
+ [BNXT_ULP_CLASS_HID_419c] = 786,
+ [BNXT_ULP_CLASS_HID_7758] = 787,
+ [BNXT_ULP_CLASS_HID_43ac] = 788,
+ [BNXT_ULP_CLASS_HID_0c10] = 789,
+ [BNXT_ULP_CLASS_HID_1864] = 790,
+ [BNXT_ULP_CLASS_HID_30c8] = 791,
+ [BNXT_ULP_CLASS_HID_1cdc] = 792,
+ [BNXT_ULP_CLASS_HID_50cc] = 793,
+ [BNXT_ULP_CLASS_HID_3d20] = 794,
+ [BNXT_ULP_CLASS_HID_529c] = 795,
+ [BNXT_ULP_CLASS_HID_3ef0] = 796,
+ [BNXT_ULP_CLASS_HID_72e0] = 797,
+ [BNXT_ULP_CLASS_HID_5ef4] = 798,
+ [BNXT_ULP_CLASS_HID_2dfc] = 799,
+ [BNXT_ULP_CLASS_HID_39e0] = 800,
+ [BNXT_ULP_CLASS_HID_4530] = 801,
+ [BNXT_ULP_CLASS_HID_5124] = 802,
+ [BNXT_ULP_CLASS_HID_4df0] = 803,
+ [BNXT_ULP_CLASS_HID_59e4] = 804,
+ [BNXT_ULP_CLASS_HID_1c78] = 805,
+ [BNXT_ULP_CLASS_HID_7118] = 806,
+ [BNXT_ULP_CLASS_HID_0998] = 807,
+ [BNXT_ULP_CLASS_HID_158c] = 808,
+ [BNXT_ULP_CLASS_HID_20dc] = 809,
+ [BNXT_ULP_CLASS_HID_0cc0] = 810,
+ [BNXT_ULP_CLASS_HID_299c] = 811,
+ [BNXT_ULP_CLASS_HID_3580] = 812,
+ [BNXT_ULP_CLASS_HID_40d0] = 813,
+ [BNXT_ULP_CLASS_HID_2cc4] = 814,
+ [BNXT_ULP_CLASS_HID_55a4] = 815,
+ [BNXT_ULP_CLASS_HID_21b8] = 816,
+ [BNXT_ULP_CLASS_HID_75a8] = 817,
+ [BNXT_ULP_CLASS_HID_41bc] = 818,
+ [BNXT_ULP_CLASS_HID_7778] = 819,
+ [BNXT_ULP_CLASS_HID_438c] = 820,
+ [BNXT_ULP_CLASS_HID_0c30] = 821,
+ [BNXT_ULP_CLASS_HID_1844] = 822,
+ [BNXT_ULP_CLASS_HID_30e8] = 823,
+ [BNXT_ULP_CLASS_HID_1cfc] = 824,
+ [BNXT_ULP_CLASS_HID_50ec] = 825,
+ [BNXT_ULP_CLASS_HID_3d00] = 826,
+ [BNXT_ULP_CLASS_HID_52bc] = 827,
+ [BNXT_ULP_CLASS_HID_3ed0] = 828,
+ [BNXT_ULP_CLASS_HID_72c0] = 829,
+ [BNXT_ULP_CLASS_HID_5ed4] = 830,
+ [BNXT_ULP_CLASS_HID_3866] = 831,
+ [BNXT_ULP_CLASS_HID_381e] = 832,
+ [BNXT_ULP_CLASS_HID_3860] = 833,
+ [BNXT_ULP_CLASS_HID_0454] = 834,
+ [BNXT_ULP_CLASS_HID_3818] = 835,
+ [BNXT_ULP_CLASS_HID_042c] = 836,
+ [BNXT_ULP_CLASS_HID_3846] = 837,
+ [BNXT_ULP_CLASS_HID_387e] = 838,
+ [BNXT_ULP_CLASS_HID_3ba6] = 839,
+ [BNXT_ULP_CLASS_HID_385e] = 840,
+ [BNXT_ULP_CLASS_HID_3840] = 841,
+ [BNXT_ULP_CLASS_HID_0474] = 842,
+ [BNXT_ULP_CLASS_HID_3878] = 843,
+ [BNXT_ULP_CLASS_HID_044c] = 844,
+ [BNXT_ULP_CLASS_HID_3ba0] = 845,
+ [BNXT_ULP_CLASS_HID_0794] = 846,
+ [BNXT_ULP_CLASS_HID_3858] = 847,
+ [BNXT_ULP_CLASS_HID_046c] = 848
};
/* Array for the proto matcher list */
@@ -6964,8 +7126,3839 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_12_BITMASK_O_UDP_DST_PORT }
},
[345] = {
- .class_hid = BNXT_ULP_CLASS_HID_34c6,
+ .class_hid = BNXT_ULP_CLASS_HID_3612,
+ .class_tid = 2,
+ .hdr_sig_id = 0,
+ .flow_sig_id = 81920,
+ .flow_pattern_id = 0,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_F1 |
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT }
+ },
+ [346] = {
+ .class_hid = BNXT_ULP_CLASS_HID_66da,
+ .class_tid = 2,
+ .hdr_sig_id = 0,
+ .flow_sig_id = 81928,
+ .flow_pattern_id = 0,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_F1 |
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT }
+ },
+ [347] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6165,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 1313792,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC }
+ },
+ [348] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2aa1,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 1321984,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC }
+ },
+ [349] = {
+ .class_hid = BNXT_ULP_CLASS_HID_09cd,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 3410944,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }
+ },
+ [350] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3845,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 3419136,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }
+ },
+ [351] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11e9,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 2148797440,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [352] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4361,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 2148805632,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [353] = {
+ .class_hid = BNXT_ULP_CLASS_HID_218d,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 2150894592,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [354] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5105,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 2150902784,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [355] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0c89,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 4296281088,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [356] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3e81,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 4296289280,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [357] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1dad,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 4298378240,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [358] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4ca5,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 4298386432,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [359] = {
+ .class_hid = BNXT_ULP_CLASS_HID_25c9,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 6443764736,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [360] = {
+ .class_hid = BNXT_ULP_CLASS_HID_57c1,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 6443772928,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [361] = {
+ .class_hid = BNXT_ULP_CLASS_HID_33ed,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 6445861888,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [362] = {
+ .class_hid = BNXT_ULP_CLASS_HID_65e5,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 6445870080,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [363] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6dd9,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 1313792,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }
+ },
+ [364] = {
+ .class_hid = BNXT_ULP_CLASS_HID_261d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 1321984,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }
+ },
+ [365] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0571,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 3410944,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
+ },
+ [366] = {
+ .class_hid = BNXT_ULP_CLASS_HID_34f9,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 3419136,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
+ },
+ [367] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1d55,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 2148797440,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [368] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4fdd,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 2148805632,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [369] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2d31,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 2150894592,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [370] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5db9,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 2150902784,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [371] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0035,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 4296281088,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [372] = {
+ .class_hid = BNXT_ULP_CLASS_HID_323d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 4296289280,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [373] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1111,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 4298378240,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [374] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4019,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 4298386432,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [375] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2975,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 6443764736,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [376] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5b7d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 6443772928,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [377] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3f51,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 6445861888,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [378] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6959,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 6445870080,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [379] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0e85,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 8591248384,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [380] = {
+ .class_hid = BNXT_ULP_CLASS_HID_380d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 8591256576,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [381] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1f21,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 8593345536,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [382] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4ea9,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 8593353728,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [383] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1705,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 10738732032,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [384] = {
+ .class_hid = BNXT_ULP_CLASS_HID_418d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 10738740224,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [385] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2721,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 10740829184,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [386] = {
+ .class_hid = BNXT_ULP_CLASS_HID_57a9,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 10740837376,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [387] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1a25,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 12886215680,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [388] = {
+ .class_hid = BNXT_ULP_CLASS_HID_342d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 12886223872,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [389] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2b01,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 12888312832,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [390] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5a09,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 12888321024,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [391] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2325,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 15033699328,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [392] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5d2d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 15033707520,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [393] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3101,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 15035796480,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [394] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6309,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 15035804672,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [395] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0bad,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 17181182976,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [396] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2535,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 17181191168,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [397] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1869,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 17183280128,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [398] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4bf1,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 17183288320,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [399] = {
+ .class_hid = BNXT_ULP_CLASS_HID_136d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 19328666624,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [400] = {
+ .class_hid = BNXT_ULP_CLASS_HID_43f5,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 19328674816,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [401] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2129,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 19330763776,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [402] = {
+ .class_hid = BNXT_ULP_CLASS_HID_53b1,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 19330771968,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [403] = {
+ .class_hid = BNXT_ULP_CLASS_HID_072d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 21476150272,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [404] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3135,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 21476158464,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [405] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1429,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 21478247424,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [406] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4731,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 21478255616,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [407] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2f6d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 23623633920,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [408] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5f75,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 23623642112,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [409] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3d69,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 23625731072,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [410] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6f71,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 23625739264,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [411] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0dbd,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 25771117568,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [412] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3f25,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 25771125760,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [413] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1239,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 25773214720,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [414] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4da1,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 25773222912,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [415] = {
+ .class_hid = BNXT_ULP_CLASS_HID_153d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 27918601216,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [416] = {
+ .class_hid = BNXT_ULP_CLASS_HID_45a5,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 27918609408,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [417] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3bb9,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 27920698368,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [418] = {
+ .class_hid = BNXT_ULP_CLASS_HID_55a1,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 27920706560,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [419] = {
+ .class_hid = BNXT_ULP_CLASS_HID_193d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 30066084864,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [420] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4b25,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 30066093056,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [421] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2e39,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 30068182016,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [422] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5921,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 30068190208,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [423] = {
+ .class_hid = BNXT_ULP_CLASS_HID_213d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 32213568512,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [424] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5125,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 32213576704,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [425] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3739,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 32215665664,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [426] = {
+ .class_hid = BNXT_ULP_CLASS_HID_093d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 32215673856,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [427] = {
+ .class_hid = BNXT_ULP_CLASS_HID_684d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1313792,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
+ },
+ [428] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2389,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1321984,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
+ },
+ [429] = {
+ .class_hid = BNXT_ULP_CLASS_HID_00e5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3410944,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
+ },
+ [430] = {
+ .class_hid = BNXT_ULP_CLASS_HID_316d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3419136,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
+ },
+ [431] = {
+ .class_hid = BNXT_ULP_CLASS_HID_18c1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2148797440,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [432] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4a49,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2148805632,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [433] = {
+ .class_hid = BNXT_ULP_CLASS_HID_28a5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2150894592,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [434] = {
+ .class_hid = BNXT_ULP_CLASS_HID_582d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2150902784,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [435] = {
+ .class_hid = BNXT_ULP_CLASS_HID_05a1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4296281088,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [436] = {
+ .class_hid = BNXT_ULP_CLASS_HID_37a9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4296289280,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [437] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1485,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4298378240,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [438] = {
+ .class_hid = BNXT_ULP_CLASS_HID_458d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4298386432,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [439] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2ce1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6443764736,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [440] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5ee9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6443772928,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [441] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3ac5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6445861888,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [442] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6ccd,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6445870080,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [443] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0b11,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8591248384,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [444] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3d99,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8591256576,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [445] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1ab5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8593345536,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [446] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4b3d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8593353728,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [447] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1291,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 10738732032,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [448] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4419,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 10738740224,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [449] = {
+ .class_hid = BNXT_ULP_CLASS_HID_22b5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 10740829184,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [450] = {
+ .class_hid = BNXT_ULP_CLASS_HID_523d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 10740837376,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [451] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1fb1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 12886215680,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [452] = {
+ .class_hid = BNXT_ULP_CLASS_HID_31b9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 12886223872,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [453] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2e95,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 12888312832,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [454] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5f9d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 12888321024,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [455] = {
+ .class_hid = BNXT_ULP_CLASS_HID_26b1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 15033699328,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [456] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58b9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 15033707520,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [457] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3495,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 15035796480,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [458] = {
+ .class_hid = BNXT_ULP_CLASS_HID_669d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 15035804672,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [459] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0e39,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 17181182976,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [460] = {
+ .class_hid = BNXT_ULP_CLASS_HID_20a1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 17181191168,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [461] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1dfd,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 17183280128,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [462] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4e65,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 17183288320,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [463] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16f9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 19328666624,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [464] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4661,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 19328674816,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [465] = {
+ .class_hid = BNXT_ULP_CLASS_HID_24bd,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 19330763776,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [466] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5625,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 19330771968,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [467] = {
+ .class_hid = BNXT_ULP_CLASS_HID_02b9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 21476150272,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [468] = {
+ .class_hid = BNXT_ULP_CLASS_HID_34a1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 21476158464,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [469] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11bd,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 21478247424,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [470] = {
+ .class_hid = BNXT_ULP_CLASS_HID_42a5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 21478255616,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [471] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2af9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 23623633920,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [472] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5ae1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 23623642112,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [473] = {
+ .class_hid = BNXT_ULP_CLASS_HID_38fd,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 23625731072,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [474] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6ae5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 23625739264,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [475] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0829,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 25771117568,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [476] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3ab1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 25771125760,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [477] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17ad,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 25773214720,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [478] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4835,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 25773222912,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [479] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10a9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 27918601216,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [480] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4031,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 27918609408,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [481] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3e2d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 27920698368,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [482] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5035,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 27920706560,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [483] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1ca9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 30066084864,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [484] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4eb1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 30066093056,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [485] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2bad,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 30068182016,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [486] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5cb5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 30068190208,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [487] = {
+ .class_hid = BNXT_ULP_CLASS_HID_24a9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 32213568512,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [488] = {
+ .class_hid = BNXT_ULP_CLASS_HID_54b1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 32213576704,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [489] = {
+ .class_hid = BNXT_ULP_CLASS_HID_32ad,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 32215665664,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [490] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0ca9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 32215673856,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [491] = {
+ .class_hid = BNXT_ULP_CLASS_HID_7f35,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1313792,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ },
+ [492] = {
+ .class_hid = BNXT_ULP_CLASS_HID_34f1,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1321984,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ },
+ [493] = {
+ .class_hid = BNXT_ULP_CLASS_HID_179d,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 3410944,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ },
+ [494] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2615,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 3419136,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ },
+ [495] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0fb9,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2148797440,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [496] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5d31,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2148805632,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [497] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3fdd,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2150894592,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [498] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4f55,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2150902784,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [499] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12d9,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4296281088,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [500] = {
+ .class_hid = BNXT_ULP_CLASS_HID_20d1,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4296289280,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [501] = {
+ .class_hid = BNXT_ULP_CLASS_HID_03fd,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4298378240,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [502] = {
+ .class_hid = BNXT_ULP_CLASS_HID_52f5,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4298386432,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [503] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3b99,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6443764736,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [504] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4991,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6443772928,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [505] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2dbd,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6445861888,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [506] = {
+ .class_hid = BNXT_ULP_CLASS_HID_7bb5,
.class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6445870080,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [507] = {
+ .class_hid = BNXT_ULP_CLASS_HID_34c6,
+ .class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 4096,
.flow_pattern_id = 0,
@@ -6975,12 +10968,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [346] = {
+ [508] = {
.class_hid = BNXT_ULP_CLASS_HID_0c22,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 4100,
.flow_pattern_id = 0,
@@ -6990,13 +10983,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [347] = {
+ [509] = {
.class_hid = BNXT_ULP_CLASS_HID_1cbe,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 6144,
.flow_pattern_id = 0,
@@ -7006,13 +10999,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [348] = {
+ [510] = {
.class_hid = BNXT_ULP_CLASS_HID_179a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 6148,
.flow_pattern_id = 0,
@@ -7022,14 +11015,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [349] = {
+ [511] = {
.class_hid = BNXT_ULP_CLASS_HID_59be,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 16384,
.flow_pattern_id = 0,
@@ -7039,12 +11032,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [350] = {
+ [512] = {
.class_hid = BNXT_ULP_CLASS_HID_515a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 16388,
.flow_pattern_id = 0,
@@ -7054,13 +11047,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [351] = {
+ [513] = {
.class_hid = BNXT_ULP_CLASS_HID_1c72,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 24576,
.flow_pattern_id = 0,
@@ -7070,13 +11063,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [352] = {
+ [514] = {
.class_hid = BNXT_ULP_CLASS_HID_171e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 24580,
.flow_pattern_id = 0,
@@ -7086,14 +11079,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [353] = {
+ [515] = {
.class_hid = BNXT_ULP_CLASS_HID_19c8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32768,
.flow_pattern_id = 0,
@@ -7104,12 +11097,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [354] = {
+ [516] = {
.class_hid = BNXT_ULP_CLASS_HID_112c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32772,
.flow_pattern_id = 0,
@@ -7120,13 +11113,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [355] = {
+ [517] = {
.class_hid = BNXT_ULP_CLASS_HID_4d68,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32832,
.flow_pattern_id = 0,
@@ -7137,13 +11130,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [356] = {
+ [518] = {
.class_hid = BNXT_ULP_CLASS_HID_444c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32836,
.flow_pattern_id = 0,
@@ -7154,14 +11147,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [357] = {
+ [519] = {
.class_hid = BNXT_ULP_CLASS_HID_0e8c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49152,
.flow_pattern_id = 0,
@@ -7172,13 +11165,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [358] = {
+ [520] = {
.class_hid = BNXT_ULP_CLASS_HID_09e0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49156,
.flow_pattern_id = 0,
@@ -7189,14 +11182,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [359] = {
+ [521] = {
.class_hid = BNXT_ULP_CLASS_HID_1af0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49216,
.flow_pattern_id = 0,
@@ -7207,14 +11200,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [360] = {
+ [522] = {
.class_hid = BNXT_ULP_CLASS_HID_15d4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49220,
.flow_pattern_id = 0,
@@ -7225,15 +11218,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [361] = {
+ [523] = {
.class_hid = BNXT_ULP_CLASS_HID_1dd0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131072,
.flow_pattern_id = 0,
@@ -7244,12 +11237,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [362] = {
+ [524] = {
.class_hid = BNXT_ULP_CLASS_HID_14f4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131076,
.flow_pattern_id = 0,
@@ -7260,13 +11253,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [363] = {
+ [525] = {
.class_hid = BNXT_ULP_CLASS_HID_70b0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131136,
.flow_pattern_id = 0,
@@ -7277,13 +11270,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [364] = {
+ [526] = {
.class_hid = BNXT_ULP_CLASS_HID_4854,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131140,
.flow_pattern_id = 0,
@@ -7294,14 +11287,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [365] = {
+ [527] = {
.class_hid = BNXT_ULP_CLASS_HID_3dd4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196608,
.flow_pattern_id = 0,
@@ -7312,13 +11305,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [366] = {
+ [528] = {
.class_hid = BNXT_ULP_CLASS_HID_34f8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196612,
.flow_pattern_id = 0,
@@ -7329,14 +11322,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [367] = {
+ [529] = {
.class_hid = BNXT_ULP_CLASS_HID_09e8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196672,
.flow_pattern_id = 0,
@@ -7347,14 +11340,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [368] = {
+ [530] = {
.class_hid = BNXT_ULP_CLASS_HID_008c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196676,
.flow_pattern_id = 0,
@@ -7365,15 +11358,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [369] = {
+ [531] = {
.class_hid = BNXT_ULP_CLASS_HID_34e6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 4096,
.flow_pattern_id = 0,
@@ -7384,12 +11377,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [370] = {
+ [532] = {
.class_hid = BNXT_ULP_CLASS_HID_0c02,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 4100,
.flow_pattern_id = 0,
@@ -7400,13 +11393,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [371] = {
+ [533] = {
.class_hid = BNXT_ULP_CLASS_HID_1c9e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 6144,
.flow_pattern_id = 0,
@@ -7417,13 +11410,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [372] = {
+ [534] = {
.class_hid = BNXT_ULP_CLASS_HID_17ba,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 6148,
.flow_pattern_id = 0,
@@ -7434,14 +11427,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [373] = {
+ [535] = {
.class_hid = BNXT_ULP_CLASS_HID_429e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 12288,
.flow_pattern_id = 0,
@@ -7452,13 +11445,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [374] = {
+ [536] = {
.class_hid = BNXT_ULP_CLASS_HID_5dba,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 12292,
.flow_pattern_id = 0,
@@ -7469,14 +11462,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [375] = {
+ [537] = {
.class_hid = BNXT_ULP_CLASS_HID_2a16,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 14336,
.flow_pattern_id = 0,
@@ -7487,14 +11480,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [376] = {
+ [538] = {
.class_hid = BNXT_ULP_CLASS_HID_2532,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 14340,
.flow_pattern_id = 0,
@@ -7505,15 +11498,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [377] = {
+ [539] = {
.class_hid = BNXT_ULP_CLASS_HID_2da2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 20480,
.flow_pattern_id = 0,
@@ -7524,13 +11517,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [378] = {
+ [540] = {
.class_hid = BNXT_ULP_CLASS_HID_24fe,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 20484,
.flow_pattern_id = 0,
@@ -7541,14 +11534,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [379] = {
+ [541] = {
.class_hid = BNXT_ULP_CLASS_HID_355a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 22528,
.flow_pattern_id = 0,
@@ -7559,14 +11552,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [380] = {
+ [542] = {
.class_hid = BNXT_ULP_CLASS_HID_0c76,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 22532,
.flow_pattern_id = 0,
@@ -7577,15 +11570,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [381] = {
+ [543] = {
.class_hid = BNXT_ULP_CLASS_HID_13e6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 28672,
.flow_pattern_id = 0,
@@ -7596,14 +11589,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [382] = {
+ [544] = {
.class_hid = BNXT_ULP_CLASS_HID_7276,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 28676,
.flow_pattern_id = 0,
@@ -7614,15 +11607,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [383] = {
+ [545] = {
.class_hid = BNXT_ULP_CLASS_HID_42d2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 30720,
.flow_pattern_id = 0,
@@ -7633,15 +11626,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [384] = {
+ [546] = {
.class_hid = BNXT_ULP_CLASS_HID_5dee,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 30724,
.flow_pattern_id = 0,
@@ -7652,16 +11645,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [385] = {
+ [547] = {
.class_hid = BNXT_ULP_CLASS_HID_59de,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 16384,
.flow_pattern_id = 0,
@@ -7672,12 +11665,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [386] = {
+ [548] = {
.class_hid = BNXT_ULP_CLASS_HID_513a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 16388,
.flow_pattern_id = 0,
@@ -7688,13 +11681,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [387] = {
+ [549] = {
.class_hid = BNXT_ULP_CLASS_HID_1c12,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 24576,
.flow_pattern_id = 0,
@@ -7705,13 +11698,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [388] = {
+ [550] = {
.class_hid = BNXT_ULP_CLASS_HID_177e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 24580,
.flow_pattern_id = 0,
@@ -7722,14 +11715,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [389] = {
+ [551] = {
.class_hid = BNXT_ULP_CLASS_HID_0e92,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 49152,
.flow_pattern_id = 0,
@@ -7740,13 +11733,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [390] = {
+ [552] = {
.class_hid = BNXT_ULP_CLASS_HID_09fe,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 49156,
.flow_pattern_id = 0,
@@ -7757,14 +11750,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [391] = {
+ [553] = {
.class_hid = BNXT_ULP_CLASS_HID_5c1a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 57344,
.flow_pattern_id = 0,
@@ -7775,14 +11768,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [392] = {
+ [554] = {
.class_hid = BNXT_ULP_CLASS_HID_5746,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 57348,
.flow_pattern_id = 0,
@@ -7793,15 +11786,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [393] = {
+ [555] = {
.class_hid = BNXT_ULP_CLASS_HID_79da,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 81920,
.flow_pattern_id = 0,
@@ -7812,13 +11805,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [394] = {
+ [556] = {
.class_hid = BNXT_ULP_CLASS_HID_7106,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 81924,
.flow_pattern_id = 0,
@@ -7829,14 +11822,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [395] = {
+ [557] = {
.class_hid = BNXT_ULP_CLASS_HID_3c1e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 90112,
.flow_pattern_id = 0,
@@ -7847,14 +11840,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [396] = {
+ [558] = {
.class_hid = BNXT_ULP_CLASS_HID_377a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 90116,
.flow_pattern_id = 0,
@@ -7865,15 +11858,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [397] = {
+ [559] = {
.class_hid = BNXT_ULP_CLASS_HID_2e9e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 114688,
.flow_pattern_id = 0,
@@ -7884,14 +11877,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [398] = {
+ [560] = {
.class_hid = BNXT_ULP_CLASS_HID_29fa,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 114692,
.flow_pattern_id = 0,
@@ -7902,15 +11895,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [399] = {
+ [561] = {
.class_hid = BNXT_ULP_CLASS_HID_14d2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 122880,
.flow_pattern_id = 0,
@@ -7921,15 +11914,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [400] = {
+ [562] = {
.class_hid = BNXT_ULP_CLASS_HID_7742,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 122884,
.flow_pattern_id = 0,
@@ -7940,16 +11933,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [401] = {
+ [563] = {
.class_hid = BNXT_ULP_CLASS_HID_3706,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 4096,
.flow_pattern_id = 0,
@@ -7960,12 +11953,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [402] = {
+ [564] = {
.class_hid = BNXT_ULP_CLASS_HID_0fe2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 4100,
.flow_pattern_id = 0,
@@ -7976,13 +11969,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [403] = {
+ [565] = {
.class_hid = BNXT_ULP_CLASS_HID_1f7e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 6144,
.flow_pattern_id = 0,
@@ -7993,13 +11986,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [404] = {
+ [566] = {
.class_hid = BNXT_ULP_CLASS_HID_145a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 6148,
.flow_pattern_id = 0,
@@ -8010,14 +12003,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [405] = {
+ [567] = {
.class_hid = BNXT_ULP_CLASS_HID_417e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 12288,
.flow_pattern_id = 0,
@@ -8028,13 +12021,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [406] = {
+ [568] = {
.class_hid = BNXT_ULP_CLASS_HID_5e5a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 12292,
.flow_pattern_id = 0,
@@ -8045,14 +12038,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [407] = {
+ [569] = {
.class_hid = BNXT_ULP_CLASS_HID_29f6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 14336,
.flow_pattern_id = 0,
@@ -8063,14 +12056,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [408] = {
+ [570] = {
.class_hid = BNXT_ULP_CLASS_HID_26d2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 14340,
.flow_pattern_id = 0,
@@ -8081,15 +12074,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [409] = {
+ [571] = {
.class_hid = BNXT_ULP_CLASS_HID_2e42,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 20480,
.flow_pattern_id = 0,
@@ -8100,13 +12093,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [410] = {
+ [572] = {
.class_hid = BNXT_ULP_CLASS_HID_271e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 20484,
.flow_pattern_id = 0,
@@ -8117,14 +12110,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [411] = {
+ [573] = {
.class_hid = BNXT_ULP_CLASS_HID_36ba,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 22528,
.flow_pattern_id = 0,
@@ -8135,14 +12128,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [412] = {
+ [574] = {
.class_hid = BNXT_ULP_CLASS_HID_0f96,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 22532,
.flow_pattern_id = 0,
@@ -8153,15 +12146,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [413] = {
+ [575] = {
.class_hid = BNXT_ULP_CLASS_HID_1006,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 28672,
.flow_pattern_id = 0,
@@ -8172,14 +12165,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [414] = {
+ [576] = {
.class_hid = BNXT_ULP_CLASS_HID_7196,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 28676,
.flow_pattern_id = 0,
@@ -8190,15 +12183,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [415] = {
+ [577] = {
.class_hid = BNXT_ULP_CLASS_HID_4132,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 30720,
.flow_pattern_id = 0,
@@ -8209,15 +12202,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [416] = {
+ [578] = {
.class_hid = BNXT_ULP_CLASS_HID_5e0e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 30724,
.flow_pattern_id = 0,
@@ -8228,16 +12221,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [417] = {
+ [579] = {
.class_hid = BNXT_ULP_CLASS_HID_59fe,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 16384,
.flow_pattern_id = 0,
@@ -8248,12 +12241,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [418] = {
+ [580] = {
.class_hid = BNXT_ULP_CLASS_HID_511a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 16388,
.flow_pattern_id = 0,
@@ -8264,13 +12257,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [419] = {
+ [581] = {
.class_hid = BNXT_ULP_CLASS_HID_1c32,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 24576,
.flow_pattern_id = 0,
@@ -8281,13 +12274,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [420] = {
+ [582] = {
.class_hid = BNXT_ULP_CLASS_HID_175e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 24580,
.flow_pattern_id = 0,
@@ -8298,14 +12291,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [421] = {
+ [583] = {
.class_hid = BNXT_ULP_CLASS_HID_0eb2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 49152,
.flow_pattern_id = 0,
@@ -8316,13 +12309,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [422] = {
+ [584] = {
.class_hid = BNXT_ULP_CLASS_HID_09de,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 49156,
.flow_pattern_id = 0,
@@ -8333,14 +12326,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [423] = {
+ [585] = {
.class_hid = BNXT_ULP_CLASS_HID_5c3a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 57344,
.flow_pattern_id = 0,
@@ -8351,14 +12344,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [424] = {
+ [586] = {
.class_hid = BNXT_ULP_CLASS_HID_5766,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 57348,
.flow_pattern_id = 0,
@@ -8369,15 +12362,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [425] = {
+ [587] = {
.class_hid = BNXT_ULP_CLASS_HID_79fa,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 81920,
.flow_pattern_id = 0,
@@ -8388,13 +12381,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [426] = {
+ [588] = {
.class_hid = BNXT_ULP_CLASS_HID_7126,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 81924,
.flow_pattern_id = 0,
@@ -8405,14 +12398,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [427] = {
+ [589] = {
.class_hid = BNXT_ULP_CLASS_HID_3c3e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 90112,
.flow_pattern_id = 0,
@@ -8423,14 +12416,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [428] = {
+ [590] = {
.class_hid = BNXT_ULP_CLASS_HID_375a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 90116,
.flow_pattern_id = 0,
@@ -8441,15 +12434,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [429] = {
+ [591] = {
.class_hid = BNXT_ULP_CLASS_HID_2ebe,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 114688,
.flow_pattern_id = 0,
@@ -8460,14 +12453,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [430] = {
+ [592] = {
.class_hid = BNXT_ULP_CLASS_HID_29da,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 114692,
.flow_pattern_id = 0,
@@ -8478,15 +12471,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [431] = {
+ [593] = {
.class_hid = BNXT_ULP_CLASS_HID_14f2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 122880,
.flow_pattern_id = 0,
@@ -8497,15 +12490,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [432] = {
+ [594] = {
.class_hid = BNXT_ULP_CLASS_HID_7762,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 122884,
.flow_pattern_id = 0,
@@ -8516,16 +12509,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [433] = {
+ [595] = {
.class_hid = BNXT_ULP_CLASS_HID_19e8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32768,
.flow_pattern_id = 0,
@@ -8537,12 +12530,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [434] = {
+ [596] = {
.class_hid = BNXT_ULP_CLASS_HID_110c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32772,
.flow_pattern_id = 0,
@@ -8554,13 +12547,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [435] = {
+ [597] = {
.class_hid = BNXT_ULP_CLASS_HID_4d48,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32832,
.flow_pattern_id = 0,
@@ -8572,13 +12565,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [436] = {
+ [598] = {
.class_hid = BNXT_ULP_CLASS_HID_446c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32836,
.flow_pattern_id = 0,
@@ -8590,14 +12583,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [437] = {
+ [599] = {
.class_hid = BNXT_ULP_CLASS_HID_0eac,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49152,
.flow_pattern_id = 0,
@@ -8609,13 +12602,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [438] = {
+ [600] = {
.class_hid = BNXT_ULP_CLASS_HID_09c0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49156,
.flow_pattern_id = 0,
@@ -8627,14 +12620,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [439] = {
+ [601] = {
.class_hid = BNXT_ULP_CLASS_HID_1ad0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49216,
.flow_pattern_id = 0,
@@ -8646,14 +12639,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [440] = {
+ [602] = {
.class_hid = BNXT_ULP_CLASS_HID_15f4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49220,
.flow_pattern_id = 0,
@@ -8665,15 +12658,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [441] = {
+ [603] = {
.class_hid = BNXT_ULP_CLASS_HID_39ec,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98304,
.flow_pattern_id = 0,
@@ -8685,13 +12678,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [442] = {
+ [604] = {
.class_hid = BNXT_ULP_CLASS_HID_3100,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98308,
.flow_pattern_id = 0,
@@ -8703,14 +12696,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [443] = {
+ [605] = {
.class_hid = BNXT_ULP_CLASS_HID_0210,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98368,
.flow_pattern_id = 0,
@@ -8722,14 +12715,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [444] = {
+ [606] = {
.class_hid = BNXT_ULP_CLASS_HID_1d34,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98372,
.flow_pattern_id = 0,
@@ -8741,15 +12734,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [445] = {
+ [607] = {
.class_hid = BNXT_ULP_CLASS_HID_2ea0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114688,
.flow_pattern_id = 0,
@@ -8761,14 +12754,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [446] = {
+ [608] = {
.class_hid = BNXT_ULP_CLASS_HID_29c4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114692,
.flow_pattern_id = 0,
@@ -8780,15 +12773,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [447] = {
+ [609] = {
.class_hid = BNXT_ULP_CLASS_HID_3ad4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114752,
.flow_pattern_id = 0,
@@ -8800,15 +12793,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [448] = {
+ [610] = {
.class_hid = BNXT_ULP_CLASS_HID_35e8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114756,
.flow_pattern_id = 0,
@@ -8820,16 +12813,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [449] = {
+ [611] = {
.class_hid = BNXT_ULP_CLASS_HID_5d80,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163840,
.flow_pattern_id = 0,
@@ -8841,13 +12834,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [450] = {
+ [612] = {
.class_hid = BNXT_ULP_CLASS_HID_54a4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163844,
.flow_pattern_id = 0,
@@ -8859,14 +12852,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [451] = {
+ [613] = {
.class_hid = BNXT_ULP_CLASS_HID_29b4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163904,
.flow_pattern_id = 0,
@@ -8878,14 +12871,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [452] = {
+ [614] = {
.class_hid = BNXT_ULP_CLASS_HID_20c8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163908,
.flow_pattern_id = 0,
@@ -8897,15 +12890,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [453] = {
+ [615] = {
.class_hid = BNXT_ULP_CLASS_HID_7244,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180224,
.flow_pattern_id = 0,
@@ -8917,14 +12910,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [454] = {
+ [616] = {
.class_hid = BNXT_ULP_CLASS_HID_4d98,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180228,
.flow_pattern_id = 0,
@@ -8936,15 +12929,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [455] = {
+ [617] = {
.class_hid = BNXT_ULP_CLASS_HID_5e68,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180288,
.flow_pattern_id = 0,
@@ -8956,15 +12949,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [456] = {
+ [618] = {
.class_hid = BNXT_ULP_CLASS_HID_598c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180292,
.flow_pattern_id = 0,
@@ -8976,16 +12969,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [457] = {
+ [619] = {
.class_hid = BNXT_ULP_CLASS_HID_1248,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229376,
.flow_pattern_id = 0,
@@ -8997,14 +12990,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [458] = {
+ [620] = {
.class_hid = BNXT_ULP_CLASS_HID_74d8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229380,
.flow_pattern_id = 0,
@@ -9016,15 +13009,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [459] = {
+ [621] = {
.class_hid = BNXT_ULP_CLASS_HID_49a8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229440,
.flow_pattern_id = 0,
@@ -9036,15 +13029,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [460] = {
+ [622] = {
.class_hid = BNXT_ULP_CLASS_HID_40cc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229444,
.flow_pattern_id = 0,
@@ -9056,16 +13049,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [461] = {
+ [623] = {
.class_hid = BNXT_ULP_CLASS_HID_0b0c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245760,
.flow_pattern_id = 0,
@@ -9077,15 +13070,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [462] = {
+ [624] = {
.class_hid = BNXT_ULP_CLASS_HID_0220,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245764,
.flow_pattern_id = 0,
@@ -9097,16 +13090,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [463] = {
+ [625] = {
.class_hid = BNXT_ULP_CLASS_HID_1730,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245824,
.flow_pattern_id = 0,
@@ -9118,16 +13111,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [464] = {
+ [626] = {
.class_hid = BNXT_ULP_CLASS_HID_7980,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245828,
.flow_pattern_id = 0,
@@ -9139,17 +13132,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [465] = {
+ [627] = {
.class_hid = BNXT_ULP_CLASS_HID_1db0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131072,
.flow_pattern_id = 0,
@@ -9161,12 +13154,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [466] = {
+ [628] = {
.class_hid = BNXT_ULP_CLASS_HID_1494,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131076,
.flow_pattern_id = 0,
@@ -9178,13 +13171,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [467] = {
+ [629] = {
.class_hid = BNXT_ULP_CLASS_HID_70d0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131136,
.flow_pattern_id = 0,
@@ -9196,13 +13189,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [468] = {
+ [630] = {
.class_hid = BNXT_ULP_CLASS_HID_4834,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131140,
.flow_pattern_id = 0,
@@ -9214,14 +13207,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [469] = {
+ [631] = {
.class_hid = BNXT_ULP_CLASS_HID_3db4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196608,
.flow_pattern_id = 0,
@@ -9233,13 +13226,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [470] = {
+ [632] = {
.class_hid = BNXT_ULP_CLASS_HID_3498,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196612,
.flow_pattern_id = 0,
@@ -9251,14 +13244,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [471] = {
+ [633] = {
.class_hid = BNXT_ULP_CLASS_HID_0988,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196672,
.flow_pattern_id = 0,
@@ -9270,14 +13263,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [472] = {
+ [634] = {
.class_hid = BNXT_ULP_CLASS_HID_00ec,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196676,
.flow_pattern_id = 0,
@@ -9289,15 +13282,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [473] = {
+ [635] = {
.class_hid = BNXT_ULP_CLASS_HID_3f44,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393216,
.flow_pattern_id = 0,
@@ -9309,13 +13302,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [474] = {
+ [636] = {
.class_hid = BNXT_ULP_CLASS_HID_36a8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393220,
.flow_pattern_id = 0,
@@ -9327,14 +13320,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [475] = {
+ [637] = {
.class_hid = BNXT_ULP_CLASS_HID_0b58,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393280,
.flow_pattern_id = 0,
@@ -9346,14 +13339,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [476] = {
+ [638] = {
.class_hid = BNXT_ULP_CLASS_HID_02bc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393284,
.flow_pattern_id = 0,
@@ -9365,15 +13358,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [477] = {
+ [639] = {
.class_hid = BNXT_ULP_CLASS_HID_5f48,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458752,
.flow_pattern_id = 0,
@@ -9385,14 +13378,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [478] = {
+ [640] = {
.class_hid = BNXT_ULP_CLASS_HID_56ac,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458756,
.flow_pattern_id = 0,
@@ -9404,15 +13397,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [479] = {
+ [641] = {
.class_hid = BNXT_ULP_CLASS_HID_2b5c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458816,
.flow_pattern_id = 0,
@@ -9424,15 +13417,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [480] = {
+ [642] = {
.class_hid = BNXT_ULP_CLASS_HID_2280,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458820,
.flow_pattern_id = 0,
@@ -9444,16 +13437,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [481] = {
+ [643] = {
.class_hid = BNXT_ULP_CLASS_HID_4000,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655360,
.flow_pattern_id = 0,
@@ -9465,13 +13458,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [482] = {
+ [644] = {
.class_hid = BNXT_ULP_CLASS_HID_5b64,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655364,
.flow_pattern_id = 0,
@@ -9483,14 +13476,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [483] = {
+ [645] = {
.class_hid = BNXT_ULP_CLASS_HID_2c14,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655424,
.flow_pattern_id = 0,
@@ -9502,14 +13495,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [484] = {
+ [646] = {
.class_hid = BNXT_ULP_CLASS_HID_2778,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655428,
.flow_pattern_id = 0,
@@ -9521,15 +13514,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [485] = {
+ [647] = {
.class_hid = BNXT_ULP_CLASS_HID_18f8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720896,
.flow_pattern_id = 0,
@@ -9541,14 +13534,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [486] = {
+ [648] = {
.class_hid = BNXT_ULP_CLASS_HID_13dc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720900,
.flow_pattern_id = 0,
@@ -9560,15 +13553,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [487] = {
+ [649] = {
.class_hid = BNXT_ULP_CLASS_HID_4c18,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720960,
.flow_pattern_id = 0,
@@ -9580,15 +13573,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [488] = {
+ [650] = {
.class_hid = BNXT_ULP_CLASS_HID_477c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720964,
.flow_pattern_id = 0,
@@ -9600,16 +13593,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [489] = {
+ [651] = {
.class_hid = BNXT_ULP_CLASS_HID_1a88,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917504,
.flow_pattern_id = 0,
@@ -9621,14 +13614,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [490] = {
+ [652] = {
.class_hid = BNXT_ULP_CLASS_HID_15ec,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917508,
.flow_pattern_id = 0,
@@ -9640,15 +13633,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [491] = {
+ [653] = {
.class_hid = BNXT_ULP_CLASS_HID_4e28,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917568,
.flow_pattern_id = 0,
@@ -9660,15 +13653,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [492] = {
+ [654] = {
.class_hid = BNXT_ULP_CLASS_HID_490c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917572,
.flow_pattern_id = 0,
@@ -9680,16 +13673,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [493] = {
+ [655] = {
.class_hid = BNXT_ULP_CLASS_HID_3a8c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983040,
.flow_pattern_id = 0,
@@ -9701,15 +13694,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [494] = {
+ [656] = {
.class_hid = BNXT_ULP_CLASS_HID_35f0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983044,
.flow_pattern_id = 0,
@@ -9721,16 +13714,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [495] = {
+ [657] = {
.class_hid = BNXT_ULP_CLASS_HID_06e0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983104,
.flow_pattern_id = 0,
@@ -9742,16 +13735,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [496] = {
+ [658] = {
.class_hid = BNXT_ULP_CLASS_HID_01c4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983108,
.flow_pattern_id = 0,
@@ -9763,17 +13756,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [497] = {
+ [659] = {
.class_hid = BNXT_ULP_CLASS_HID_1a08,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32768,
.flow_pattern_id = 0,
@@ -9785,12 +13778,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [498] = {
+ [660] = {
.class_hid = BNXT_ULP_CLASS_HID_12ec,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32772,
.flow_pattern_id = 0,
@@ -9802,13 +13795,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [499] = {
+ [661] = {
.class_hid = BNXT_ULP_CLASS_HID_4ea8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32832,
.flow_pattern_id = 0,
@@ -9820,13 +13813,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [500] = {
+ [662] = {
.class_hid = BNXT_ULP_CLASS_HID_478c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32836,
.flow_pattern_id = 0,
@@ -9838,14 +13831,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [501] = {
+ [663] = {
.class_hid = BNXT_ULP_CLASS_HID_0d4c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49152,
.flow_pattern_id = 0,
@@ -9857,13 +13850,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [502] = {
+ [664] = {
.class_hid = BNXT_ULP_CLASS_HID_0a20,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49156,
.flow_pattern_id = 0,
@@ -9875,14 +13868,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [503] = {
+ [665] = {
.class_hid = BNXT_ULP_CLASS_HID_1930,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49216,
.flow_pattern_id = 0,
@@ -9894,14 +13887,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [504] = {
+ [666] = {
.class_hid = BNXT_ULP_CLASS_HID_1614,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49220,
.flow_pattern_id = 0,
@@ -9913,15 +13906,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [505] = {
+ [667] = {
.class_hid = BNXT_ULP_CLASS_HID_3a0c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98304,
.flow_pattern_id = 0,
@@ -9933,13 +13926,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [506] = {
+ [668] = {
.class_hid = BNXT_ULP_CLASS_HID_32e0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98308,
.flow_pattern_id = 0,
@@ -9951,14 +13944,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [507] = {
+ [669] = {
.class_hid = BNXT_ULP_CLASS_HID_01f0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98368,
.flow_pattern_id = 0,
@@ -9970,14 +13963,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [508] = {
+ [670] = {
.class_hid = BNXT_ULP_CLASS_HID_1ed4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98372,
.flow_pattern_id = 0,
@@ -9989,15 +13982,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [509] = {
+ [671] = {
.class_hid = BNXT_ULP_CLASS_HID_2d40,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114688,
.flow_pattern_id = 0,
@@ -10009,14 +14002,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [510] = {
+ [672] = {
.class_hid = BNXT_ULP_CLASS_HID_2a24,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114692,
.flow_pattern_id = 0,
@@ -10028,15 +14021,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [511] = {
+ [673] = {
.class_hid = BNXT_ULP_CLASS_HID_3934,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114752,
.flow_pattern_id = 0,
@@ -10048,15 +14041,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [512] = {
+ [674] = {
.class_hid = BNXT_ULP_CLASS_HID_3608,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114756,
.flow_pattern_id = 0,
@@ -10068,16 +14061,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [513] = {
+ [675] = {
.class_hid = BNXT_ULP_CLASS_HID_5e60,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163840,
.flow_pattern_id = 0,
@@ -10089,13 +14082,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [514] = {
+ [676] = {
.class_hid = BNXT_ULP_CLASS_HID_5744,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163844,
.flow_pattern_id = 0,
@@ -10107,14 +14100,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [515] = {
+ [677] = {
.class_hid = BNXT_ULP_CLASS_HID_2a54,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163904,
.flow_pattern_id = 0,
@@ -10126,14 +14119,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [516] = {
+ [678] = {
.class_hid = BNXT_ULP_CLASS_HID_2328,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163908,
.flow_pattern_id = 0,
@@ -10145,15 +14138,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [517] = {
+ [679] = {
.class_hid = BNXT_ULP_CLASS_HID_71a4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180224,
.flow_pattern_id = 0,
@@ -10165,14 +14158,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [518] = {
+ [680] = {
.class_hid = BNXT_ULP_CLASS_HID_4e78,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180228,
.flow_pattern_id = 0,
@@ -10184,15 +14177,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [519] = {
+ [681] = {
.class_hid = BNXT_ULP_CLASS_HID_5d88,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180288,
.flow_pattern_id = 0,
@@ -10204,15 +14197,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [520] = {
+ [682] = {
.class_hid = BNXT_ULP_CLASS_HID_5a6c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180292,
.flow_pattern_id = 0,
@@ -10224,16 +14217,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [521] = {
+ [683] = {
.class_hid = BNXT_ULP_CLASS_HID_11a8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229376,
.flow_pattern_id = 0,
@@ -10245,14 +14238,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [522] = {
+ [684] = {
.class_hid = BNXT_ULP_CLASS_HID_7738,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229380,
.flow_pattern_id = 0,
@@ -10264,15 +14257,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [523] = {
+ [685] = {
.class_hid = BNXT_ULP_CLASS_HID_4a48,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229440,
.flow_pattern_id = 0,
@@ -10284,15 +14277,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [524] = {
+ [686] = {
.class_hid = BNXT_ULP_CLASS_HID_432c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229444,
.flow_pattern_id = 0,
@@ -10304,16 +14297,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [525] = {
+ [687] = {
.class_hid = BNXT_ULP_CLASS_HID_08ec,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245760,
.flow_pattern_id = 0,
@@ -10325,15 +14318,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [526] = {
+ [688] = {
.class_hid = BNXT_ULP_CLASS_HID_01c0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245764,
.flow_pattern_id = 0,
@@ -10345,16 +14338,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [527] = {
+ [689] = {
.class_hid = BNXT_ULP_CLASS_HID_14d0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245824,
.flow_pattern_id = 0,
@@ -10366,16 +14359,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [528] = {
+ [690] = {
.class_hid = BNXT_ULP_CLASS_HID_7a60,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245828,
.flow_pattern_id = 0,
@@ -10387,17 +14380,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [529] = {
+ [691] = {
.class_hid = BNXT_ULP_CLASS_HID_1d90,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131072,
.flow_pattern_id = 0,
@@ -10409,12 +14402,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [530] = {
+ [692] = {
.class_hid = BNXT_ULP_CLASS_HID_14b4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131076,
.flow_pattern_id = 0,
@@ -10426,13 +14419,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [531] = {
+ [693] = {
.class_hid = BNXT_ULP_CLASS_HID_70f0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131136,
.flow_pattern_id = 0,
@@ -10444,13 +14437,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [532] = {
+ [694] = {
.class_hid = BNXT_ULP_CLASS_HID_4814,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131140,
.flow_pattern_id = 0,
@@ -10462,14 +14455,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [533] = {
+ [695] = {
.class_hid = BNXT_ULP_CLASS_HID_3d94,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196608,
.flow_pattern_id = 0,
@@ -10481,13 +14474,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [534] = {
+ [696] = {
.class_hid = BNXT_ULP_CLASS_HID_34b8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196612,
.flow_pattern_id = 0,
@@ -10499,14 +14492,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [535] = {
+ [697] = {
.class_hid = BNXT_ULP_CLASS_HID_09a8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196672,
.flow_pattern_id = 0,
@@ -10518,14 +14511,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [536] = {
+ [698] = {
.class_hid = BNXT_ULP_CLASS_HID_00cc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196676,
.flow_pattern_id = 0,
@@ -10537,15 +14530,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [537] = {
+ [699] = {
.class_hid = BNXT_ULP_CLASS_HID_3f64,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393216,
.flow_pattern_id = 0,
@@ -10557,13 +14550,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [538] = {
+ [700] = {
.class_hid = BNXT_ULP_CLASS_HID_3688,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393220,
.flow_pattern_id = 0,
@@ -10575,14 +14568,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [539] = {
+ [701] = {
.class_hid = BNXT_ULP_CLASS_HID_0b78,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393280,
.flow_pattern_id = 0,
@@ -10594,14 +14587,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [540] = {
+ [702] = {
.class_hid = BNXT_ULP_CLASS_HID_029c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393284,
.flow_pattern_id = 0,
@@ -10613,15 +14606,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [541] = {
+ [703] = {
.class_hid = BNXT_ULP_CLASS_HID_5f68,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458752,
.flow_pattern_id = 0,
@@ -10633,14 +14626,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [542] = {
+ [704] = {
.class_hid = BNXT_ULP_CLASS_HID_568c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458756,
.flow_pattern_id = 0,
@@ -10652,15 +14645,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [543] = {
+ [705] = {
.class_hid = BNXT_ULP_CLASS_HID_2b7c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458816,
.flow_pattern_id = 0,
@@ -10672,15 +14665,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [544] = {
+ [706] = {
.class_hid = BNXT_ULP_CLASS_HID_22a0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458820,
.flow_pattern_id = 0,
@@ -10692,16 +14685,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [545] = {
+ [707] = {
.class_hid = BNXT_ULP_CLASS_HID_4020,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655360,
.flow_pattern_id = 0,
@@ -10713,13 +14706,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [546] = {
+ [708] = {
.class_hid = BNXT_ULP_CLASS_HID_5b44,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655364,
.flow_pattern_id = 0,
@@ -10731,14 +14724,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [547] = {
+ [709] = {
.class_hid = BNXT_ULP_CLASS_HID_2c34,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655424,
.flow_pattern_id = 0,
@@ -10750,14 +14743,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [548] = {
+ [710] = {
.class_hid = BNXT_ULP_CLASS_HID_2758,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655428,
.flow_pattern_id = 0,
@@ -10769,15 +14762,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [549] = {
+ [711] = {
.class_hid = BNXT_ULP_CLASS_HID_18d8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720896,
.flow_pattern_id = 0,
@@ -10789,14 +14782,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [550] = {
+ [712] = {
.class_hid = BNXT_ULP_CLASS_HID_13fc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720900,
.flow_pattern_id = 0,
@@ -10808,15 +14801,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [551] = {
+ [713] = {
.class_hid = BNXT_ULP_CLASS_HID_4c38,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720960,
.flow_pattern_id = 0,
@@ -10828,15 +14821,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [552] = {
+ [714] = {
.class_hid = BNXT_ULP_CLASS_HID_475c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720964,
.flow_pattern_id = 0,
@@ -10848,16 +14841,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [553] = {
+ [715] = {
.class_hid = BNXT_ULP_CLASS_HID_1aa8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917504,
.flow_pattern_id = 0,
@@ -10869,14 +14862,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [554] = {
+ [716] = {
.class_hid = BNXT_ULP_CLASS_HID_15cc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917508,
.flow_pattern_id = 0,
@@ -10888,15 +14881,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [555] = {
+ [717] = {
.class_hid = BNXT_ULP_CLASS_HID_4e08,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917568,
.flow_pattern_id = 0,
@@ -10908,15 +14901,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [556] = {
+ [718] = {
.class_hid = BNXT_ULP_CLASS_HID_492c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917572,
.flow_pattern_id = 0,
@@ -10928,16 +14921,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [557] = {
+ [719] = {
.class_hid = BNXT_ULP_CLASS_HID_3aac,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983040,
.flow_pattern_id = 0,
@@ -10949,15 +14942,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [558] = {
+ [720] = {
.class_hid = BNXT_ULP_CLASS_HID_35d0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983044,
.flow_pattern_id = 0,
@@ -10969,16 +14962,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [559] = {
+ [721] = {
.class_hid = BNXT_ULP_CLASS_HID_06c0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983104,
.flow_pattern_id = 0,
@@ -10990,16 +14983,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [560] = {
+ [722] = {
.class_hid = BNXT_ULP_CLASS_HID_01e4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983108,
.flow_pattern_id = 0,
@@ -11011,17 +15004,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [561] = {
+ [723] = {
.class_hid = BNXT_ULP_CLASS_HID_4d32,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 4096,
.flow_pattern_id = 1,
@@ -11031,11 +15024,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [562] = {
+ [724] = {
.class_hid = BNXT_ULP_CLASS_HID_54aa,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 6144,
.flow_pattern_id = 1,
@@ -11045,12 +15038,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [563] = {
+ [725] = {
.class_hid = BNXT_ULP_CLASS_HID_0686,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 16384,
.flow_pattern_id = 1,
@@ -11060,11 +15053,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [564] = {
+ [726] = {
.class_hid = BNXT_ULP_CLASS_HID_540e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 24576,
.flow_pattern_id = 1,
@@ -11074,12 +15067,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [565] = {
+ [727] = {
.class_hid = BNXT_ULP_CLASS_HID_2e3c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32768,
.flow_pattern_id = 1,
@@ -11090,11 +15083,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [566] = {
+ [728] = {
.class_hid = BNXT_ULP_CLASS_HID_3a20,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32832,
.flow_pattern_id = 1,
@@ -11105,12 +15098,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [567] = {
+ [729] = {
.class_hid = BNXT_ULP_CLASS_HID_46f0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49152,
.flow_pattern_id = 1,
@@ -11121,12 +15114,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [568] = {
+ [730] = {
.class_hid = BNXT_ULP_CLASS_HID_52e4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49216,
.flow_pattern_id = 1,
@@ -11137,13 +15130,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [569] = {
+ [731] = {
.class_hid = BNXT_ULP_CLASS_HID_55e4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131072,
.flow_pattern_id = 1,
@@ -11154,11 +15147,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [570] = {
+ [732] = {
.class_hid = BNXT_ULP_CLASS_HID_21f8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131136,
.flow_pattern_id = 1,
@@ -11169,12 +15162,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [571] = {
+ [733] = {
.class_hid = BNXT_ULP_CLASS_HID_75e8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196608,
.flow_pattern_id = 1,
@@ -11185,12 +15178,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [572] = {
+ [734] = {
.class_hid = BNXT_ULP_CLASS_HID_41fc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196672,
.flow_pattern_id = 1,
@@ -11201,13 +15194,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [573] = {
+ [735] = {
.class_hid = BNXT_ULP_CLASS_HID_4d12,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 4096,
.flow_pattern_id = 1,
@@ -11218,11 +15211,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [574] = {
+ [736] = {
.class_hid = BNXT_ULP_CLASS_HID_548a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 6144,
.flow_pattern_id = 1,
@@ -11233,12 +15226,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [575] = {
+ [737] = {
.class_hid = BNXT_ULP_CLASS_HID_3356,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 12288,
.flow_pattern_id = 1,
@@ -11249,12 +15242,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [576] = {
+ [738] = {
.class_hid = BNXT_ULP_CLASS_HID_1ace,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 14336,
.flow_pattern_id = 1,
@@ -11265,13 +15258,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [577] = {
+ [739] = {
.class_hid = BNXT_ULP_CLASS_HID_1a9a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 20480,
.flow_pattern_id = 1,
@@ -11282,12 +15275,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [578] = {
+ [740] = {
.class_hid = BNXT_ULP_CLASS_HID_4d46,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 22528,
.flow_pattern_id = 1,
@@ -11298,13 +15291,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [579] = {
+ [741] = {
.class_hid = BNXT_ULP_CLASS_HID_2812,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 28672,
.flow_pattern_id = 1,
@@ -11315,13 +15308,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [580] = {
+ [742] = {
.class_hid = BNXT_ULP_CLASS_HID_338a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 30720,
.flow_pattern_id = 1,
@@ -11332,14 +15325,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [581] = {
+ [743] = {
.class_hid = BNXT_ULP_CLASS_HID_06e6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 16384,
.flow_pattern_id = 1,
@@ -11350,11 +15343,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [582] = {
+ [744] = {
.class_hid = BNXT_ULP_CLASS_HID_546e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 24576,
.flow_pattern_id = 1,
@@ -11365,12 +15358,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [583] = {
+ [745] = {
.class_hid = BNXT_ULP_CLASS_HID_46ee,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 49152,
.flow_pattern_id = 1,
@@ -11381,12 +15374,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [584] = {
+ [746] = {
.class_hid = BNXT_ULP_CLASS_HID_0d22,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 57344,
.flow_pattern_id = 1,
@@ -11397,13 +15390,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [585] = {
+ [747] = {
.class_hid = BNXT_ULP_CLASS_HID_26e2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 81920,
.flow_pattern_id = 1,
@@ -11414,12 +15407,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [586] = {
+ [748] = {
.class_hid = BNXT_ULP_CLASS_HID_746a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 90112,
.flow_pattern_id = 1,
@@ -11430,13 +15423,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [587] = {
+ [749] = {
.class_hid = BNXT_ULP_CLASS_HID_1fa6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 114688,
.flow_pattern_id = 1,
@@ -11447,13 +15440,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [588] = {
+ [750] = {
.class_hid = BNXT_ULP_CLASS_HID_2d2e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 122880,
.flow_pattern_id = 1,
@@ -11464,14 +15457,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [589] = {
+ [751] = {
.class_hid = BNXT_ULP_CLASS_HID_4ef2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 4096,
.flow_pattern_id = 1,
@@ -11482,11 +15475,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [590] = {
+ [752] = {
.class_hid = BNXT_ULP_CLASS_HID_576a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 6144,
.flow_pattern_id = 1,
@@ -11497,12 +15490,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [591] = {
+ [753] = {
.class_hid = BNXT_ULP_CLASS_HID_30b6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 12288,
.flow_pattern_id = 1,
@@ -11513,12 +15506,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [592] = {
+ [754] = {
.class_hid = BNXT_ULP_CLASS_HID_192e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 14336,
.flow_pattern_id = 1,
@@ -11529,13 +15522,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [593] = {
+ [755] = {
.class_hid = BNXT_ULP_CLASS_HID_197a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 20480,
.flow_pattern_id = 1,
@@ -11546,12 +15539,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [594] = {
+ [756] = {
.class_hid = BNXT_ULP_CLASS_HID_4ea6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 22528,
.flow_pattern_id = 1,
@@ -11562,13 +15555,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [595] = {
+ [757] = {
.class_hid = BNXT_ULP_CLASS_HID_2bf2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 28672,
.flow_pattern_id = 1,
@@ -11579,13 +15572,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [596] = {
+ [758] = {
.class_hid = BNXT_ULP_CLASS_HID_306a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 30720,
.flow_pattern_id = 1,
@@ -11596,14 +15589,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [597] = {
+ [759] = {
.class_hid = BNXT_ULP_CLASS_HID_06c6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 16384,
.flow_pattern_id = 1,
@@ -11614,11 +15607,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [598] = {
+ [760] = {
.class_hid = BNXT_ULP_CLASS_HID_544e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 24576,
.flow_pattern_id = 1,
@@ -11629,12 +15622,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [599] = {
+ [761] = {
.class_hid = BNXT_ULP_CLASS_HID_46ce,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 49152,
.flow_pattern_id = 1,
@@ -11645,12 +15638,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [600] = {
+ [762] = {
.class_hid = BNXT_ULP_CLASS_HID_0d02,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 57344,
.flow_pattern_id = 1,
@@ -11661,13 +15654,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [601] = {
+ [763] = {
.class_hid = BNXT_ULP_CLASS_HID_26c2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 81920,
.flow_pattern_id = 1,
@@ -11678,12 +15671,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [602] = {
+ [764] = {
.class_hid = BNXT_ULP_CLASS_HID_744a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 90112,
.flow_pattern_id = 1,
@@ -11694,13 +15687,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [603] = {
+ [765] = {
.class_hid = BNXT_ULP_CLASS_HID_1f86,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 114688,
.flow_pattern_id = 1,
@@ -11711,13 +15704,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [604] = {
+ [766] = {
.class_hid = BNXT_ULP_CLASS_HID_2d0e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 122880,
.flow_pattern_id = 1,
@@ -11728,14 +15721,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [605] = {
+ [767] = {
.class_hid = BNXT_ULP_CLASS_HID_2e1c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32768,
.flow_pattern_id = 1,
@@ -11747,11 +15740,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [606] = {
+ [768] = {
.class_hid = BNXT_ULP_CLASS_HID_3a00,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32832,
.flow_pattern_id = 1,
@@ -11763,12 +15756,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [607] = {
+ [769] = {
.class_hid = BNXT_ULP_CLASS_HID_46d0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49152,
.flow_pattern_id = 1,
@@ -11780,12 +15773,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [608] = {
+ [770] = {
.class_hid = BNXT_ULP_CLASS_HID_52c4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49216,
.flow_pattern_id = 1,
@@ -11797,13 +15790,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [609] = {
+ [771] = {
.class_hid = BNXT_ULP_CLASS_HID_4e10,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98304,
.flow_pattern_id = 1,
@@ -11815,12 +15808,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [610] = {
+ [772] = {
.class_hid = BNXT_ULP_CLASS_HID_5a04,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98368,
.flow_pattern_id = 1,
@@ -11832,13 +15825,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [611] = {
+ [773] = {
.class_hid = BNXT_ULP_CLASS_HID_1f98,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114688,
.flow_pattern_id = 1,
@@ -11850,13 +15843,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [612] = {
+ [774] = {
.class_hid = BNXT_ULP_CLASS_HID_72f8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114752,
.flow_pattern_id = 1,
@@ -11868,14 +15861,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [613] = {
+ [775] = {
.class_hid = BNXT_ULP_CLASS_HID_0a78,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163840,
.flow_pattern_id = 1,
@@ -11887,12 +15880,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [614] = {
+ [776] = {
.class_hid = BNXT_ULP_CLASS_HID_166c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163904,
.flow_pattern_id = 1,
@@ -11904,13 +15897,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [615] = {
+ [777] = {
.class_hid = BNXT_ULP_CLASS_HID_233c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180224,
.flow_pattern_id = 1,
@@ -11922,13 +15915,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [616] = {
+ [778] = {
.class_hid = BNXT_ULP_CLASS_HID_0f20,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180288,
.flow_pattern_id = 1,
@@ -11940,14 +15933,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [617] = {
+ [779] = {
.class_hid = BNXT_ULP_CLASS_HID_2a7c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229376,
.flow_pattern_id = 1,
@@ -11959,13 +15952,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [618] = {
+ [780] = {
.class_hid = BNXT_ULP_CLASS_HID_3660,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229440,
.flow_pattern_id = 1,
@@ -11977,14 +15970,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [619] = {
+ [781] = {
.class_hid = BNXT_ULP_CLASS_HID_4330,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245760,
.flow_pattern_id = 1,
@@ -11996,14 +15989,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [620] = {
+ [782] = {
.class_hid = BNXT_ULP_CLASS_HID_2f24,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245824,
.flow_pattern_id = 1,
@@ -12015,15 +16008,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [621] = {
+ [783] = {
.class_hid = BNXT_ULP_CLASS_HID_5584,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131072,
.flow_pattern_id = 1,
@@ -12035,11 +16028,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [622] = {
+ [784] = {
.class_hid = BNXT_ULP_CLASS_HID_2198,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131136,
.flow_pattern_id = 1,
@@ -12051,12 +16044,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [623] = {
+ [785] = {
.class_hid = BNXT_ULP_CLASS_HID_7588,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196608,
.flow_pattern_id = 1,
@@ -12068,12 +16061,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [624] = {
+ [786] = {
.class_hid = BNXT_ULP_CLASS_HID_419c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196672,
.flow_pattern_id = 1,
@@ -12085,13 +16078,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [625] = {
+ [787] = {
.class_hid = BNXT_ULP_CLASS_HID_7758,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393216,
.flow_pattern_id = 1,
@@ -12103,12 +16096,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [626] = {
+ [788] = {
.class_hid = BNXT_ULP_CLASS_HID_43ac,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393280,
.flow_pattern_id = 1,
@@ -12120,13 +16113,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [627] = {
+ [789] = {
.class_hid = BNXT_ULP_CLASS_HID_0c10,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458752,
.flow_pattern_id = 1,
@@ -12138,13 +16131,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [628] = {
+ [790] = {
.class_hid = BNXT_ULP_CLASS_HID_1864,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458816,
.flow_pattern_id = 1,
@@ -12156,14 +16149,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [629] = {
+ [791] = {
.class_hid = BNXT_ULP_CLASS_HID_30c8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655360,
.flow_pattern_id = 1,
@@ -12175,12 +16168,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [630] = {
+ [792] = {
.class_hid = BNXT_ULP_CLASS_HID_1cdc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655424,
.flow_pattern_id = 1,
@@ -12192,13 +16185,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [631] = {
+ [793] = {
.class_hid = BNXT_ULP_CLASS_HID_50cc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720896,
.flow_pattern_id = 1,
@@ -12210,13 +16203,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [632] = {
+ [794] = {
.class_hid = BNXT_ULP_CLASS_HID_3d20,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720960,
.flow_pattern_id = 1,
@@ -12228,14 +16221,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [633] = {
+ [795] = {
.class_hid = BNXT_ULP_CLASS_HID_529c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917504,
.flow_pattern_id = 1,
@@ -12247,13 +16240,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [634] = {
+ [796] = {
.class_hid = BNXT_ULP_CLASS_HID_3ef0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917568,
.flow_pattern_id = 1,
@@ -12265,14 +16258,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [635] = {
+ [797] = {
.class_hid = BNXT_ULP_CLASS_HID_72e0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983040,
.flow_pattern_id = 1,
@@ -12284,14 +16277,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [636] = {
+ [798] = {
.class_hid = BNXT_ULP_CLASS_HID_5ef4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983104,
.flow_pattern_id = 1,
@@ -12303,15 +16296,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [637] = {
+ [799] = {
.class_hid = BNXT_ULP_CLASS_HID_2dfc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32768,
.flow_pattern_id = 1,
@@ -12323,11 +16316,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [638] = {
+ [800] = {
.class_hid = BNXT_ULP_CLASS_HID_39e0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32832,
.flow_pattern_id = 1,
@@ -12339,12 +16332,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [639] = {
+ [801] = {
.class_hid = BNXT_ULP_CLASS_HID_4530,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49152,
.flow_pattern_id = 1,
@@ -12356,12 +16349,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [640] = {
+ [802] = {
.class_hid = BNXT_ULP_CLASS_HID_5124,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49216,
.flow_pattern_id = 1,
@@ -12373,13 +16366,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [641] = {
+ [803] = {
.class_hid = BNXT_ULP_CLASS_HID_4df0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98304,
.flow_pattern_id = 1,
@@ -12391,12 +16384,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [642] = {
+ [804] = {
.class_hid = BNXT_ULP_CLASS_HID_59e4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98368,
.flow_pattern_id = 1,
@@ -12408,13 +16401,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [643] = {
+ [805] = {
.class_hid = BNXT_ULP_CLASS_HID_1c78,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114688,
.flow_pattern_id = 1,
@@ -12426,13 +16419,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [644] = {
+ [806] = {
.class_hid = BNXT_ULP_CLASS_HID_7118,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114752,
.flow_pattern_id = 1,
@@ -12444,14 +16437,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [645] = {
+ [807] = {
.class_hid = BNXT_ULP_CLASS_HID_0998,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163840,
.flow_pattern_id = 1,
@@ -12463,12 +16456,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [646] = {
+ [808] = {
.class_hid = BNXT_ULP_CLASS_HID_158c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163904,
.flow_pattern_id = 1,
@@ -12480,13 +16473,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [647] = {
+ [809] = {
.class_hid = BNXT_ULP_CLASS_HID_20dc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180224,
.flow_pattern_id = 1,
@@ -12498,13 +16491,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [648] = {
+ [810] = {
.class_hid = BNXT_ULP_CLASS_HID_0cc0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180288,
.flow_pattern_id = 1,
@@ -12516,14 +16509,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [649] = {
+ [811] = {
.class_hid = BNXT_ULP_CLASS_HID_299c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229376,
.flow_pattern_id = 1,
@@ -12535,13 +16528,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [650] = {
+ [812] = {
.class_hid = BNXT_ULP_CLASS_HID_3580,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229440,
.flow_pattern_id = 1,
@@ -12553,14 +16546,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [651] = {
+ [813] = {
.class_hid = BNXT_ULP_CLASS_HID_40d0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245760,
.flow_pattern_id = 1,
@@ -12572,14 +16565,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [652] = {
+ [814] = {
.class_hid = BNXT_ULP_CLASS_HID_2cc4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245824,
.flow_pattern_id = 1,
@@ -12591,15 +16584,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [653] = {
+ [815] = {
.class_hid = BNXT_ULP_CLASS_HID_55a4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131072,
.flow_pattern_id = 1,
@@ -12611,11 +16604,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [654] = {
+ [816] = {
.class_hid = BNXT_ULP_CLASS_HID_21b8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131136,
.flow_pattern_id = 1,
@@ -12627,12 +16620,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [655] = {
+ [817] = {
.class_hid = BNXT_ULP_CLASS_HID_75a8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196608,
.flow_pattern_id = 1,
@@ -12644,12 +16637,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [656] = {
+ [818] = {
.class_hid = BNXT_ULP_CLASS_HID_41bc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196672,
.flow_pattern_id = 1,
@@ -12661,13 +16654,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [657] = {
+ [819] = {
.class_hid = BNXT_ULP_CLASS_HID_7778,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393216,
.flow_pattern_id = 1,
@@ -12679,12 +16672,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [658] = {
+ [820] = {
.class_hid = BNXT_ULP_CLASS_HID_438c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393280,
.flow_pattern_id = 1,
@@ -12696,13 +16689,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [659] = {
+ [821] = {
.class_hid = BNXT_ULP_CLASS_HID_0c30,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458752,
.flow_pattern_id = 1,
@@ -12714,13 +16707,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [660] = {
+ [822] = {
.class_hid = BNXT_ULP_CLASS_HID_1844,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458816,
.flow_pattern_id = 1,
@@ -12732,14 +16725,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [661] = {
+ [823] = {
.class_hid = BNXT_ULP_CLASS_HID_30e8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655360,
.flow_pattern_id = 1,
@@ -12751,12 +16744,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [662] = {
+ [824] = {
.class_hid = BNXT_ULP_CLASS_HID_1cfc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655424,
.flow_pattern_id = 1,
@@ -12768,13 +16761,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [663] = {
+ [825] = {
.class_hid = BNXT_ULP_CLASS_HID_50ec,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720896,
.flow_pattern_id = 1,
@@ -12786,13 +16779,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [664] = {
+ [826] = {
.class_hid = BNXT_ULP_CLASS_HID_3d00,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720960,
.flow_pattern_id = 1,
@@ -12804,14 +16797,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [665] = {
+ [827] = {
.class_hid = BNXT_ULP_CLASS_HID_52bc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917504,
.flow_pattern_id = 1,
@@ -12823,13 +16816,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [666] = {
+ [828] = {
.class_hid = BNXT_ULP_CLASS_HID_3ed0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917568,
.flow_pattern_id = 1,
@@ -12841,14 +16834,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [667] = {
+ [829] = {
.class_hid = BNXT_ULP_CLASS_HID_72c0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983040,
.flow_pattern_id = 1,
@@ -12860,14 +16853,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [668] = {
+ [830] = {
.class_hid = BNXT_ULP_CLASS_HID_5ed4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983104,
.flow_pattern_id = 1,
@@ -12879,15 +16872,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [669] = {
+ [831] = {
.class_hid = BNXT_ULP_CLASS_HID_3866,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -12897,12 +16890,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC }
},
- [670] = {
+ [832] = {
.class_hid = BNXT_ULP_CLASS_HID_381e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -12912,12 +16905,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC }
},
- [671] = {
+ [833] = {
.class_hid = BNXT_ULP_CLASS_HID_3860,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -12928,12 +16921,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC }
},
- [672] = {
+ [834] = {
.class_hid = BNXT_ULP_CLASS_HID_0454,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 68,
.flow_pattern_id = 2,
@@ -12944,13 +16937,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID }
},
- [673] = {
+ [835] = {
.class_hid = BNXT_ULP_CLASS_HID_3818,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -12961,12 +16954,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC }
},
- [674] = {
+ [836] = {
.class_hid = BNXT_ULP_CLASS_HID_042c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 68,
.flow_pattern_id = 2,
@@ -12977,13 +16970,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID }
},
- [675] = {
+ [837] = {
.class_hid = BNXT_ULP_CLASS_HID_3846,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -12994,12 +16987,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC }
},
- [676] = {
+ [838] = {
.class_hid = BNXT_ULP_CLASS_HID_387e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -13010,12 +17003,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC }
},
- [677] = {
+ [839] = {
.class_hid = BNXT_ULP_CLASS_HID_3ba6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -13026,12 +17019,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC }
},
- [678] = {
+ [840] = {
.class_hid = BNXT_ULP_CLASS_HID_385e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -13042,12 +17035,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC }
},
- [679] = {
+ [841] = {
.class_hid = BNXT_ULP_CLASS_HID_3840,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -13059,12 +17052,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC }
},
- [680] = {
+ [842] = {
.class_hid = BNXT_ULP_CLASS_HID_0474,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 68,
.flow_pattern_id = 2,
@@ -13076,13 +17069,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID }
},
- [681] = {
+ [843] = {
.class_hid = BNXT_ULP_CLASS_HID_3878,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -13094,12 +17087,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC }
},
- [682] = {
+ [844] = {
.class_hid = BNXT_ULP_CLASS_HID_044c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 68,
.flow_pattern_id = 2,
@@ -13111,13 +17104,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID }
},
- [683] = {
+ [845] = {
.class_hid = BNXT_ULP_CLASS_HID_3ba0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -13129,12 +17122,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC }
},
- [684] = {
+ [846] = {
.class_hid = BNXT_ULP_CLASS_HID_0794,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 68,
.flow_pattern_id = 2,
@@ -13146,13 +17139,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID }
},
- [685] = {
+ [847] = {
.class_hid = BNXT_ULP_CLASS_HID_3858,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -13164,12 +17157,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC }
},
- [686] = {
+ [848] = {
.class_hid = BNXT_ULP_CLASS_HID_046c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 68,
.flow_pattern_id = 2,
@@ -13181,8 +17174,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID }
}
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
index b6db49cc5d..e55d0923a5 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 13 18:15:56 2021 */
+/* date: Thu May 20 11:56:39 2021 */
#ifndef ULP_TEMPLATE_DB_H_
#define ULP_TEMPLATE_DB_H_
@@ -11,13 +11,13 @@
#define BNXT_ULP_REGFILE_MAX_SZ 40
#define BNXT_ULP_MAX_NUM_DEVICES 4
#define BNXT_ULP_LOG2_MAX_NUM_DEV 2
-#define BNXT_ULP_GEN_TBL_MAX_SZ 10
+#define BNXT_ULP_GEN_TBL_MAX_SZ 12
#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 32768
-#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 687
+#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 849
#define BNXT_ULP_CLASS_HID_LOW_PRIME 6701
#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907
-#define BNXT_ULP_CLASS_HID_SHFTR 23
-#define BNXT_ULP_CLASS_HID_SHFTL 23
+#define BNXT_ULP_CLASS_HID_SHFTR 24
+#define BNXT_ULP_CLASS_HID_SHFTL 24
#define BNXT_ULP_CLASS_HID_MASK 32767
#define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048
#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 86
@@ -36,14 +36,14 @@
#define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7
#define BNXT_ULP_HDR_SIG_ID_SHIFT 4
#define BNXT_ULP_APP_ID_SHIFT 4
-#define BNXT_ULP_GLB_FIELD_TBL_SIZE 5595
-#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 5
-#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 74
-#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 495
-#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 20
-#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 546
-#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 43
-#define ULP_THOR_CLASS_TMPL_LIST_SIZE 5
+#define BNXT_ULP_GLB_FIELD_TBL_SIZE 7643
+#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 6
+#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 89
+#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 600
+#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 26
+#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 619
+#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 49
+#define ULP_THOR_CLASS_TMPL_LIST_SIZE 6
#define ULP_THOR_CLASS_TBL_LIST_SIZE 33
#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 242
#define ULP_THOR_CLASS_IDENT_LIST_SIZE 8
@@ -113,7 +113,8 @@ enum bnxt_ulp_hdr_bit {
BNXT_ULP_HDR_BIT_I_UDP = 0x0000000000010000,
BNXT_ULP_HDR_BIT_I_ICMP = 0x0000000000020000,
BNXT_ULP_HDR_BIT_F1 = 0x0000000000040000,
- BNXT_ULP_HDR_BIT_LAST = 0x0000000000080000
+ BNXT_ULP_HDR_BIT_F2 = 0x0000000000080000,
+ BNXT_ULP_HDR_BIT_LAST = 0x0000000000100000
};
enum bnxt_ulp_accept_opc {
@@ -199,8 +200,10 @@ enum bnxt_ulp_cf_idx {
BNXT_ULP_CF_IDX_FLOW_SIG_ID = 60,
BNXT_ULP_CF_IDX_WC_MATCH = 61,
BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG = 62,
- BNXT_ULP_CF_IDX_F1_DMAC = 63,
- BNXT_ULP_CF_IDX_LAST = 64
+ BNXT_ULP_CF_IDX_TUNNEL_ID = 63,
+ BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID = 64,
+ BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID = 65,
+ BNXT_ULP_CF_IDX_LAST = 66
};
enum bnxt_ulp_cond_list_opc {
@@ -315,7 +318,8 @@ enum bnxt_ulp_func_opc {
BNXT_ULP_FUNC_OPC_COPY_SRC1_TO_RF = 7,
BNXT_ULP_FUNC_OPC_RSS_CONFIG = 8,
BNXT_ULP_FUNC_OPC_GET_PARENT_MAC_ADDR = 9,
- BNXT_ULP_FUNC_OPC_LAST = 10
+ BNXT_ULP_FUNC_OPC_ALLOC_L2_CTX_ID = 10,
+ BNXT_ULP_FUNC_OPC_LAST = 11
};
enum bnxt_ulp_func_src {
@@ -497,7 +501,8 @@ enum bnxt_ulp_tcam_tbl_opc {
BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE = 2,
BNXT_ULP_TCAM_TBL_OPC_ALLOC_REGFILE = 3,
BNXT_ULP_TCAM_TBL_OPC_WR_REGFILE = 4,
- BNXT_ULP_TCAM_TBL_OPC_LAST = 5
+ BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT = 5,
+ BNXT_ULP_TCAM_TBL_OPC_LAST = 6
};
enum bnxt_ulp_template_type {
@@ -549,7 +554,8 @@ enum bnxt_ulp_resource_sub_type {
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM = 1,
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR = 2,
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE = 3,
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE = 4
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE = 4,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE = 5
};
enum bnxt_ulp_act_prop_sz {
@@ -1443,6 +1449,168 @@ enum bnxt_ulp_class_hid {
BNXT_ULP_CLASS_HID_15db = 0x15db,
BNXT_ULP_CLASS_HID_1151 = 0x1151,
BNXT_ULP_CLASS_HID_315d = 0x315d,
+ BNXT_ULP_CLASS_HID_3612 = 0x3612,
+ BNXT_ULP_CLASS_HID_66da = 0x66da,
+ BNXT_ULP_CLASS_HID_6165 = 0x6165,
+ BNXT_ULP_CLASS_HID_2aa1 = 0x2aa1,
+ BNXT_ULP_CLASS_HID_09cd = 0x09cd,
+ BNXT_ULP_CLASS_HID_3845 = 0x3845,
+ BNXT_ULP_CLASS_HID_11e9 = 0x11e9,
+ BNXT_ULP_CLASS_HID_4361 = 0x4361,
+ BNXT_ULP_CLASS_HID_218d = 0x218d,
+ BNXT_ULP_CLASS_HID_5105 = 0x5105,
+ BNXT_ULP_CLASS_HID_0c89 = 0x0c89,
+ BNXT_ULP_CLASS_HID_3e81 = 0x3e81,
+ BNXT_ULP_CLASS_HID_1dad = 0x1dad,
+ BNXT_ULP_CLASS_HID_4ca5 = 0x4ca5,
+ BNXT_ULP_CLASS_HID_25c9 = 0x25c9,
+ BNXT_ULP_CLASS_HID_57c1 = 0x57c1,
+ BNXT_ULP_CLASS_HID_33ed = 0x33ed,
+ BNXT_ULP_CLASS_HID_65e5 = 0x65e5,
+ BNXT_ULP_CLASS_HID_6dd9 = 0x6dd9,
+ BNXT_ULP_CLASS_HID_261d = 0x261d,
+ BNXT_ULP_CLASS_HID_0571 = 0x0571,
+ BNXT_ULP_CLASS_HID_34f9 = 0x34f9,
+ BNXT_ULP_CLASS_HID_1d55 = 0x1d55,
+ BNXT_ULP_CLASS_HID_4fdd = 0x4fdd,
+ BNXT_ULP_CLASS_HID_2d31 = 0x2d31,
+ BNXT_ULP_CLASS_HID_5db9 = 0x5db9,
+ BNXT_ULP_CLASS_HID_0035 = 0x0035,
+ BNXT_ULP_CLASS_HID_323d = 0x323d,
+ BNXT_ULP_CLASS_HID_1111 = 0x1111,
+ BNXT_ULP_CLASS_HID_4019 = 0x4019,
+ BNXT_ULP_CLASS_HID_2975 = 0x2975,
+ BNXT_ULP_CLASS_HID_5b7d = 0x5b7d,
+ BNXT_ULP_CLASS_HID_3f51 = 0x3f51,
+ BNXT_ULP_CLASS_HID_6959 = 0x6959,
+ BNXT_ULP_CLASS_HID_0e85 = 0x0e85,
+ BNXT_ULP_CLASS_HID_380d = 0x380d,
+ BNXT_ULP_CLASS_HID_1f21 = 0x1f21,
+ BNXT_ULP_CLASS_HID_4ea9 = 0x4ea9,
+ BNXT_ULP_CLASS_HID_1705 = 0x1705,
+ BNXT_ULP_CLASS_HID_418d = 0x418d,
+ BNXT_ULP_CLASS_HID_2721 = 0x2721,
+ BNXT_ULP_CLASS_HID_57a9 = 0x57a9,
+ BNXT_ULP_CLASS_HID_1a25 = 0x1a25,
+ BNXT_ULP_CLASS_HID_342d = 0x342d,
+ BNXT_ULP_CLASS_HID_2b01 = 0x2b01,
+ BNXT_ULP_CLASS_HID_5a09 = 0x5a09,
+ BNXT_ULP_CLASS_HID_2325 = 0x2325,
+ BNXT_ULP_CLASS_HID_5d2d = 0x5d2d,
+ BNXT_ULP_CLASS_HID_3101 = 0x3101,
+ BNXT_ULP_CLASS_HID_6309 = 0x6309,
+ BNXT_ULP_CLASS_HID_0bad = 0x0bad,
+ BNXT_ULP_CLASS_HID_2535 = 0x2535,
+ BNXT_ULP_CLASS_HID_1869 = 0x1869,
+ BNXT_ULP_CLASS_HID_4bf1 = 0x4bf1,
+ BNXT_ULP_CLASS_HID_136d = 0x136d,
+ BNXT_ULP_CLASS_HID_43f5 = 0x43f5,
+ BNXT_ULP_CLASS_HID_2129 = 0x2129,
+ BNXT_ULP_CLASS_HID_53b1 = 0x53b1,
+ BNXT_ULP_CLASS_HID_072d = 0x072d,
+ BNXT_ULP_CLASS_HID_3135 = 0x3135,
+ BNXT_ULP_CLASS_HID_1429 = 0x1429,
+ BNXT_ULP_CLASS_HID_4731 = 0x4731,
+ BNXT_ULP_CLASS_HID_2f6d = 0x2f6d,
+ BNXT_ULP_CLASS_HID_5f75 = 0x5f75,
+ BNXT_ULP_CLASS_HID_3d69 = 0x3d69,
+ BNXT_ULP_CLASS_HID_6f71 = 0x6f71,
+ BNXT_ULP_CLASS_HID_0dbd = 0x0dbd,
+ BNXT_ULP_CLASS_HID_3f25 = 0x3f25,
+ BNXT_ULP_CLASS_HID_1239 = 0x1239,
+ BNXT_ULP_CLASS_HID_4da1 = 0x4da1,
+ BNXT_ULP_CLASS_HID_153d = 0x153d,
+ BNXT_ULP_CLASS_HID_45a5 = 0x45a5,
+ BNXT_ULP_CLASS_HID_3bb9 = 0x3bb9,
+ BNXT_ULP_CLASS_HID_55a1 = 0x55a1,
+ BNXT_ULP_CLASS_HID_193d = 0x193d,
+ BNXT_ULP_CLASS_HID_4b25 = 0x4b25,
+ BNXT_ULP_CLASS_HID_2e39 = 0x2e39,
+ BNXT_ULP_CLASS_HID_5921 = 0x5921,
+ BNXT_ULP_CLASS_HID_213d = 0x213d,
+ BNXT_ULP_CLASS_HID_5125 = 0x5125,
+ BNXT_ULP_CLASS_HID_3739 = 0x3739,
+ BNXT_ULP_CLASS_HID_093d = 0x093d,
+ BNXT_ULP_CLASS_HID_684d = 0x684d,
+ BNXT_ULP_CLASS_HID_2389 = 0x2389,
+ BNXT_ULP_CLASS_HID_00e5 = 0x00e5,
+ BNXT_ULP_CLASS_HID_316d = 0x316d,
+ BNXT_ULP_CLASS_HID_18c1 = 0x18c1,
+ BNXT_ULP_CLASS_HID_4a49 = 0x4a49,
+ BNXT_ULP_CLASS_HID_28a5 = 0x28a5,
+ BNXT_ULP_CLASS_HID_582d = 0x582d,
+ BNXT_ULP_CLASS_HID_05a1 = 0x05a1,
+ BNXT_ULP_CLASS_HID_37a9 = 0x37a9,
+ BNXT_ULP_CLASS_HID_1485 = 0x1485,
+ BNXT_ULP_CLASS_HID_458d = 0x458d,
+ BNXT_ULP_CLASS_HID_2ce1 = 0x2ce1,
+ BNXT_ULP_CLASS_HID_5ee9 = 0x5ee9,
+ BNXT_ULP_CLASS_HID_3ac5 = 0x3ac5,
+ BNXT_ULP_CLASS_HID_6ccd = 0x6ccd,
+ BNXT_ULP_CLASS_HID_0b11 = 0x0b11,
+ BNXT_ULP_CLASS_HID_3d99 = 0x3d99,
+ BNXT_ULP_CLASS_HID_1ab5 = 0x1ab5,
+ BNXT_ULP_CLASS_HID_4b3d = 0x4b3d,
+ BNXT_ULP_CLASS_HID_1291 = 0x1291,
+ BNXT_ULP_CLASS_HID_4419 = 0x4419,
+ BNXT_ULP_CLASS_HID_22b5 = 0x22b5,
+ BNXT_ULP_CLASS_HID_523d = 0x523d,
+ BNXT_ULP_CLASS_HID_1fb1 = 0x1fb1,
+ BNXT_ULP_CLASS_HID_31b9 = 0x31b9,
+ BNXT_ULP_CLASS_HID_2e95 = 0x2e95,
+ BNXT_ULP_CLASS_HID_5f9d = 0x5f9d,
+ BNXT_ULP_CLASS_HID_26b1 = 0x26b1,
+ BNXT_ULP_CLASS_HID_58b9 = 0x58b9,
+ BNXT_ULP_CLASS_HID_3495 = 0x3495,
+ BNXT_ULP_CLASS_HID_669d = 0x669d,
+ BNXT_ULP_CLASS_HID_0e39 = 0x0e39,
+ BNXT_ULP_CLASS_HID_20a1 = 0x20a1,
+ BNXT_ULP_CLASS_HID_1dfd = 0x1dfd,
+ BNXT_ULP_CLASS_HID_4e65 = 0x4e65,
+ BNXT_ULP_CLASS_HID_16f9 = 0x16f9,
+ BNXT_ULP_CLASS_HID_4661 = 0x4661,
+ BNXT_ULP_CLASS_HID_24bd = 0x24bd,
+ BNXT_ULP_CLASS_HID_5625 = 0x5625,
+ BNXT_ULP_CLASS_HID_02b9 = 0x02b9,
+ BNXT_ULP_CLASS_HID_34a1 = 0x34a1,
+ BNXT_ULP_CLASS_HID_11bd = 0x11bd,
+ BNXT_ULP_CLASS_HID_42a5 = 0x42a5,
+ BNXT_ULP_CLASS_HID_2af9 = 0x2af9,
+ BNXT_ULP_CLASS_HID_5ae1 = 0x5ae1,
+ BNXT_ULP_CLASS_HID_38fd = 0x38fd,
+ BNXT_ULP_CLASS_HID_6ae5 = 0x6ae5,
+ BNXT_ULP_CLASS_HID_0829 = 0x0829,
+ BNXT_ULP_CLASS_HID_3ab1 = 0x3ab1,
+ BNXT_ULP_CLASS_HID_17ad = 0x17ad,
+ BNXT_ULP_CLASS_HID_4835 = 0x4835,
+ BNXT_ULP_CLASS_HID_10a9 = 0x10a9,
+ BNXT_ULP_CLASS_HID_4031 = 0x4031,
+ BNXT_ULP_CLASS_HID_3e2d = 0x3e2d,
+ BNXT_ULP_CLASS_HID_5035 = 0x5035,
+ BNXT_ULP_CLASS_HID_1ca9 = 0x1ca9,
+ BNXT_ULP_CLASS_HID_4eb1 = 0x4eb1,
+ BNXT_ULP_CLASS_HID_2bad = 0x2bad,
+ BNXT_ULP_CLASS_HID_5cb5 = 0x5cb5,
+ BNXT_ULP_CLASS_HID_24a9 = 0x24a9,
+ BNXT_ULP_CLASS_HID_54b1 = 0x54b1,
+ BNXT_ULP_CLASS_HID_32ad = 0x32ad,
+ BNXT_ULP_CLASS_HID_0ca9 = 0x0ca9,
+ BNXT_ULP_CLASS_HID_7f35 = 0x7f35,
+ BNXT_ULP_CLASS_HID_34f1 = 0x34f1,
+ BNXT_ULP_CLASS_HID_179d = 0x179d,
+ BNXT_ULP_CLASS_HID_2615 = 0x2615,
+ BNXT_ULP_CLASS_HID_0fb9 = 0x0fb9,
+ BNXT_ULP_CLASS_HID_5d31 = 0x5d31,
+ BNXT_ULP_CLASS_HID_3fdd = 0x3fdd,
+ BNXT_ULP_CLASS_HID_4f55 = 0x4f55,
+ BNXT_ULP_CLASS_HID_12d9 = 0x12d9,
+ BNXT_ULP_CLASS_HID_20d1 = 0x20d1,
+ BNXT_ULP_CLASS_HID_03fd = 0x03fd,
+ BNXT_ULP_CLASS_HID_52f5 = 0x52f5,
+ BNXT_ULP_CLASS_HID_3b99 = 0x3b99,
+ BNXT_ULP_CLASS_HID_4991 = 0x4991,
+ BNXT_ULP_CLASS_HID_2dbd = 0x2dbd,
+ BNXT_ULP_CLASS_HID_7bb5 = 0x7bb5,
BNXT_ULP_CLASS_HID_34c6 = 0x34c6,
BNXT_ULP_CLASS_HID_0c22 = 0x0c22,
BNXT_ULP_CLASS_HID_1cbe = 0x1cbe,
@@ -1876,8 +2044,8 @@ enum bnxt_ulp_act_hid {
};
enum bnxt_ulp_df_tpl {
- BNXT_ULP_DF_TPL_DEFAULT_UPLINK_PORT = 3,
- BNXT_ULP_DF_TPL_DEFAULT_VFR = 4
+ BNXT_ULP_DF_TPL_DEFAULT_UPLINK_PORT = 4,
+ BNXT_ULP_DF_TPL_DEFAULT_VFR = 5
};
#endif
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h
index 115bdc644c..1d7bbfe2cc 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Wed Mar 17 11:31:19 2021 */
+/* date: Thu May 20 11:56:39 2021 */
#ifndef ULP_HDR_FIELD_ENUMS_H_
#define ULP_HDR_FIELD_ENUMS_H_
@@ -415,272 +415,460 @@ enum bnxt_ulp_hf_0_2_0_bitmask {
BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_VER = 0x0400000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_TC = 0x0200000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_TTL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_TOS = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_LEN = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_LENGTH = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_CSUM = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_FLAGS = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_RSVD0 = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_VNI = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_RSVD1 = 0x0000020000000000
};
enum bnxt_ulp_hf_0_2_1_bitmask {
BNXT_ULP_HF_0_2_1_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_VER = 0x0400000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TOS = 0x0200000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_LEN = 0x0100000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TTL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000
};
enum bnxt_ulp_hf_0_2_2_bitmask {
BNXT_ULP_HF_0_2_2_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID = 0x0200000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_VER = 0x0080000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_TC = 0x0040000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_TTL = 0x0004000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SENT_SEQ = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_RECV_ACK = 0x0000000008000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DATA_OFF = 0x0000000004000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_TCP_FLAGS = 0x0000000002000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_RX_WIN = 0x0000000001000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_CSUM = 0x0000000000800000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_URP = 0x0000000000400000
};
enum bnxt_ulp_hf_0_2_3_bitmask {
BNXT_ULP_HF_0_2_3_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID = 0x0200000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_VER = 0x0080000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TOS = 0x0040000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_LEN = 0x0020000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TTL = 0x0004000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_LENGTH = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_CSUM = 0x0000000008000000
};
enum bnxt_ulp_hf_0_2_4_bitmask {
BNXT_ULP_HF_0_2_4_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_VER = 0x0400000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_TC = 0x0200000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_TTL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT = 0x0004000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT = 0x0002000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SENT_SEQ = 0x0001000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_RECV_ACK = 0x0000800000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DATA_OFF = 0x0000400000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_TCP_FLAGS = 0x0000200000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_RX_WIN = 0x0000100000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_CSUM = 0x0000080000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_URP = 0x0000040000000000
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_TYPE = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_CODE = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_CSUM = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_IDENT = 0x0000000008000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_SEQ_NUM = 0x0000000004000000
};
-enum bnxt_ulp_hf_0_2_5_bitmask {
- BNXT_ULP_HF_0_2_5_BITMASK_WM = 0x8000000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_VER = 0x0400000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_TOS = 0x0200000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_LEN = 0x0100000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_TTL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT = 0x0000800000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_RX_WIN = 0x0000040000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_CSUM = 0x0000020000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_URP = 0x0000010000000000
+enum bnxt_ulp_hf_0_3_0_bitmask {
+ BNXT_ULP_HF_0_3_0_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_TC = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000
};
-enum bnxt_ulp_hf_0_2_6_bitmask {
- BNXT_ULP_HF_0_2_6_BITMASK_WM = 0x8000000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_VER = 0x0400000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_TC = 0x0200000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_TTL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT = 0x0002000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_LENGTH = 0x0001000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_CSUM = 0x0000800000000000
+enum bnxt_ulp_hf_0_3_1_bitmask {
+ BNXT_ULP_HF_0_3_1_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_TOS = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_LEN = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000
};
-enum bnxt_ulp_hf_0_2_7_bitmask {
- BNXT_ULP_HF_0_2_7_BITMASK_WM = 0x8000000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_VER = 0x0400000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_TOS = 0x0200000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_LEN = 0x0100000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_TTL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT = 0x0000800000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_LENGTH = 0x0000400000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_CSUM = 0x0000200000000000
+enum bnxt_ulp_hf_0_3_2_bitmask {
+ BNXT_ULP_HF_0_3_2_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_VER = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_TC = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_TTL = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000
};
-enum bnxt_ulp_hf_0_2_8_bitmask {
- BNXT_ULP_HF_0_2_8_BITMASK_WM = 0x8000000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID = 0x0200000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_VER = 0x0080000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_TC = 0x0040000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_TTL = 0x0004000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT = 0x0000400000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_RX_WIN = 0x0000020000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_CSUM = 0x0000010000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_URP = 0x0000008000000000
+enum bnxt_ulp_hf_0_3_3_bitmask {
+ BNXT_ULP_HF_0_3_3_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_VER = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_TOS = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_LEN = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_TTL = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000
};
-enum bnxt_ulp_hf_0_2_9_bitmask {
- BNXT_ULP_HF_0_2_9_BITMASK_WM = 0x8000000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID = 0x0200000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_VER = 0x0080000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_TOS = 0x0040000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_LEN = 0x0020000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_TTL = 0x0004000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT = 0x0000100000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_RX_WIN = 0x0000008000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_CSUM = 0x0000004000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_URP = 0x0000002000000000
+enum bnxt_ulp_hf_0_3_4_bitmask {
+ BNXT_ULP_HF_0_3_4_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_TC = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SENT_SEQ = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_RECV_ACK = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DATA_OFF = 0x0000400000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_TCP_FLAGS = 0x0000200000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_RX_WIN = 0x0000100000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_CSUM = 0x0000080000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_URP = 0x0000040000000000
};
-enum bnxt_ulp_hf_0_2_10_bitmask {
- BNXT_ULP_HF_0_2_10_BITMASK_WM = 0x8000000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID = 0x0200000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_VER = 0x0080000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_TC = 0x0040000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_TTL = 0x0004000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT = 0x0000400000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_LENGTH = 0x0000200000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_CSUM = 0x0000100000000000
+enum bnxt_ulp_hf_0_3_5_bitmask {
+ BNXT_ULP_HF_0_3_5_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_TOS = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_LEN = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_RX_WIN = 0x0000040000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_CSUM = 0x0000020000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_URP = 0x0000010000000000
};
-enum bnxt_ulp_hf_0_2_11_bitmask {
- BNXT_ULP_HF_0_2_11_BITMASK_WM = 0x8000000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID = 0x0200000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_VER = 0x0080000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_TOS = 0x0040000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_LEN = 0x0020000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_TTL = 0x0004000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT = 0x0000100000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_LENGTH = 0x0000080000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_CSUM = 0x0000040000000000
+enum bnxt_ulp_hf_0_3_6_bitmask {
+ BNXT_ULP_HF_0_3_6_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_TC = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_LENGTH = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_CSUM = 0x0000800000000000
+};
+
+enum bnxt_ulp_hf_0_3_7_bitmask {
+ BNXT_ULP_HF_0_3_7_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_TOS = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_LEN = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_LENGTH = 0x0000400000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_CSUM = 0x0000200000000000
+};
+
+enum bnxt_ulp_hf_0_3_8_bitmask {
+ BNXT_ULP_HF_0_3_8_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_VER = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_TC = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_TTL = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT = 0x0000400000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_RX_WIN = 0x0000020000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_CSUM = 0x0000010000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_URP = 0x0000008000000000
+};
+
+enum bnxt_ulp_hf_0_3_9_bitmask {
+ BNXT_ULP_HF_0_3_9_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_VER = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_TOS = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_LEN = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_TTL = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT = 0x0000100000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_RX_WIN = 0x0000008000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_CSUM = 0x0000004000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_URP = 0x0000002000000000
+};
+
+enum bnxt_ulp_hf_0_3_10_bitmask {
+ BNXT_ULP_HF_0_3_10_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_VER = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_TC = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_TTL = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT = 0x0000400000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_LENGTH = 0x0000200000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_CSUM = 0x0000100000000000
+};
+
+enum bnxt_ulp_hf_0_3_11_bitmask {
+ BNXT_ULP_HF_0_3_11_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_VER = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_TOS = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_LEN = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_TTL = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT = 0x0000100000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_LENGTH = 0x0000080000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_CSUM = 0x0000040000000000
};
#endif
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
index 2debaea0ca..58b4dba63c 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 13 18:15:56 2021 */
+/* date: Thu May 20 11:56:39 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -111,6 +111,26 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = {
.num_buckets = 0,
.hash_tbl_entries = 0,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE << 1 |
+ BNXT_ULP_DIRECTION_INGRESS] = {
+ .name = "INGRESS GENERIC_TABLE_TUNNEL_CACHE",
+ .result_num_entries = 256,
+ .result_num_bytes = 7,
+ .key_num_bytes = 2,
+ .num_buckets = 8,
+ .hash_tbl_entries = 1024,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE << 1 |
+ BNXT_ULP_DIRECTION_EGRESS] = {
+ .name = "EGRESS GENERIC_TABLE_TUNNEL_CACHE",
+ .result_num_entries = 256,
+ .result_num_bytes = 7,
+ .key_num_bytes = 2,
+ .num_buckets = 8,
+ .hash_tbl_entries = 1024,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
}
};
@@ -3098,238 +3118,411 @@ uint8_t ulp_glb_field_tbl[] = {
[4098] = 2,
[4100] = 3,
[4102] = 4,
- [4136] = 5,
- [4138] = 6,
- [4140] = 7,
- [4142] = 8,
- [4144] = 9,
- [4146] = 10,
- [4148] = 11,
- [4150] = 12,
+ [4116] = 5,
+ [4118] = 6,
+ [4120] = 7,
+ [4122] = 8,
+ [4124] = 9,
+ [4126] = 10,
+ [4128] = 11,
+ [4130] = 12,
+ [4132] = 13,
+ [4134] = 14,
+ [4170] = 15,
+ [4172] = 16,
+ [4174] = 17,
+ [4176] = 18,
+ [4190] = 19,
+ [4191] = 20,
+ [4192] = 21,
+ [4193] = 22,
[4224] = 0,
[4225] = 1,
- [4226] = 2,
- [4228] = 3,
- [4230] = 4,
- [4244] = 5,
- [4246] = 6,
- [4248] = 7,
- [4250] = 8,
- [4252] = 9,
- [4254] = 10,
- [4256] = 11,
- [4258] = 12,
- [4260] = 13,
- [4262] = 14,
+ [4227] = 20,
+ [4229] = 21,
+ [4231] = 22,
+ [4244] = 2,
+ [4245] = 23,
+ [4246] = 3,
+ [4247] = 24,
+ [4248] = 4,
+ [4249] = 25,
+ [4250] = 5,
+ [4251] = 26,
+ [4252] = 6,
+ [4253] = 27,
+ [4254] = 7,
+ [4255] = 28,
+ [4256] = 8,
+ [4257] = 29,
+ [4258] = 9,
+ [4259] = 30,
+ [4260] = 10,
+ [4261] = 31,
+ [4262] = 11,
+ [4263] = 32,
+ [4298] = 12,
+ [4300] = 13,
+ [4302] = 14,
+ [4304] = 15,
+ [4318] = 16,
+ [4319] = 17,
+ [4320] = 18,
+ [4321] = 19,
[4352] = 0,
[4353] = 1,
- [4354] = 2,
- [4356] = 3,
- [4358] = 4,
- [4392] = 8,
- [4394] = 9,
- [4396] = 10,
- [4398] = 11,
- [4400] = 12,
- [4402] = 13,
- [4404] = 14,
- [4406] = 15,
- [4434] = 5,
- [4438] = 6,
- [4442] = 7,
+ [4355] = 20,
+ [4357] = 21,
+ [4359] = 22,
+ [4372] = 2,
+ [4373] = 23,
+ [4374] = 3,
+ [4375] = 24,
+ [4376] = 4,
+ [4377] = 25,
+ [4378] = 5,
+ [4379] = 26,
+ [4380] = 6,
+ [4381] = 27,
+ [4382] = 7,
+ [4383] = 28,
+ [4384] = 8,
+ [4385] = 29,
+ [4386] = 9,
+ [4387] = 30,
+ [4388] = 10,
+ [4389] = 31,
+ [4390] = 11,
+ [4391] = 32,
+ [4409] = 33,
+ [4411] = 34,
+ [4413] = 35,
+ [4415] = 36,
+ [4417] = 37,
+ [4419] = 38,
+ [4421] = 39,
+ [4423] = 40,
+ [4425] = 41,
+ [4426] = 12,
+ [4428] = 13,
+ [4430] = 14,
+ [4432] = 15,
+ [4446] = 16,
+ [4447] = 17,
+ [4448] = 18,
+ [4449] = 19,
[4480] = 0,
[4481] = 1,
- [4482] = 2,
- [4484] = 3,
- [4486] = 4,
- [4500] = 8,
- [4502] = 9,
- [4504] = 10,
- [4506] = 11,
- [4508] = 12,
- [4510] = 13,
- [4512] = 14,
- [4514] = 15,
- [4516] = 16,
- [4518] = 17,
- [4562] = 5,
- [4566] = 6,
- [4570] = 7,
+ [4483] = 20,
+ [4485] = 21,
+ [4487] = 22,
+ [4500] = 2,
+ [4501] = 23,
+ [4502] = 3,
+ [4503] = 24,
+ [4504] = 4,
+ [4505] = 25,
+ [4506] = 5,
+ [4507] = 26,
+ [4508] = 6,
+ [4509] = 27,
+ [4510] = 7,
+ [4511] = 28,
+ [4512] = 8,
+ [4513] = 29,
+ [4514] = 9,
+ [4515] = 30,
+ [4516] = 10,
+ [4517] = 31,
+ [4518] = 11,
+ [4519] = 32,
+ [4554] = 12,
+ [4555] = 33,
+ [4556] = 13,
+ [4557] = 34,
+ [4558] = 14,
+ [4559] = 35,
+ [4560] = 15,
+ [4561] = 36,
+ [4574] = 16,
+ [4575] = 17,
+ [4576] = 18,
+ [4577] = 19,
[4608] = 0,
[4609] = 1,
- [4610] = 2,
- [4612] = 3,
- [4614] = 4,
- [4648] = 5,
- [4650] = 6,
- [4652] = 7,
- [4654] = 8,
- [4656] = 9,
- [4658] = 10,
- [4660] = 11,
- [4662] = 12,
- [4664] = 13,
- [4666] = 14,
- [4668] = 15,
- [4670] = 16,
- [4672] = 17,
- [4674] = 18,
- [4676] = 19,
- [4678] = 20,
- [4680] = 21,
- [4736] = 0,
- [4737] = 1,
- [4738] = 2,
- [4740] = 3,
- [4742] = 4,
- [4756] = 5,
- [4758] = 6,
- [4760] = 7,
- [4762] = 8,
- [4764] = 9,
- [4766] = 10,
- [4768] = 11,
- [4770] = 12,
- [4772] = 13,
- [4774] = 14,
- [4792] = 15,
- [4794] = 16,
- [4796] = 17,
- [4798] = 18,
- [4800] = 19,
- [4802] = 20,
- [4804] = 21,
- [4806] = 22,
- [4808] = 23,
- [4864] = 0,
- [4865] = 1,
- [4866] = 2,
- [4868] = 3,
- [4870] = 4,
- [4904] = 5,
- [4906] = 6,
- [4908] = 7,
- [4910] = 8,
- [4912] = 9,
- [4914] = 10,
- [4916] = 11,
- [4918] = 12,
- [4938] = 13,
- [4940] = 14,
- [4942] = 15,
- [4944] = 16,
- [4992] = 0,
- [4993] = 1,
- [4994] = 2,
- [4996] = 3,
- [4998] = 4,
- [5012] = 5,
- [5014] = 6,
- [5016] = 7,
- [5018] = 8,
- [5020] = 9,
- [5022] = 10,
- [5024] = 11,
- [5026] = 12,
- [5028] = 13,
- [5030] = 14,
- [5066] = 15,
- [5068] = 16,
- [5070] = 17,
- [5072] = 18,
- [5120] = 0,
- [5121] = 1,
- [5122] = 2,
- [5124] = 3,
- [5126] = 4,
- [5160] = 8,
- [5162] = 9,
- [5164] = 10,
- [5166] = 11,
- [5168] = 12,
- [5170] = 13,
- [5172] = 14,
- [5174] = 15,
- [5176] = 16,
- [5178] = 17,
- [5180] = 18,
- [5182] = 19,
- [5184] = 20,
- [5186] = 21,
- [5188] = 22,
- [5190] = 23,
- [5192] = 24,
- [5202] = 5,
- [5206] = 6,
- [5210] = 7,
- [5248] = 0,
- [5249] = 1,
- [5250] = 2,
- [5252] = 3,
- [5254] = 4,
- [5268] = 8,
- [5270] = 9,
- [5272] = 10,
- [5274] = 11,
- [5276] = 12,
- [5278] = 13,
- [5280] = 14,
- [5282] = 15,
- [5284] = 16,
- [5286] = 17,
- [5304] = 18,
- [5306] = 19,
- [5308] = 20,
- [5310] = 21,
- [5312] = 22,
- [5314] = 23,
- [5316] = 24,
- [5318] = 25,
- [5320] = 26,
- [5330] = 5,
- [5334] = 6,
- [5338] = 7,
- [5376] = 0,
- [5377] = 1,
- [5378] = 2,
- [5380] = 3,
- [5382] = 4,
- [5416] = 8,
- [5418] = 9,
- [5420] = 10,
- [5422] = 11,
- [5424] = 12,
- [5426] = 13,
- [5428] = 14,
- [5430] = 15,
- [5450] = 16,
- [5452] = 17,
- [5454] = 18,
- [5456] = 19,
- [5458] = 5,
- [5462] = 6,
- [5466] = 7,
- [5504] = 0,
- [5505] = 1,
- [5506] = 2,
- [5508] = 3,
- [5510] = 4,
- [5524] = 8,
- [5526] = 9,
- [5528] = 10,
- [5530] = 11,
- [5532] = 12,
- [5534] = 13,
- [5536] = 14,
- [5538] = 15,
- [5540] = 16,
- [5542] = 17,
- [5578] = 18,
- [5580] = 19,
- [5582] = 20,
- [5584] = 21,
- [5586] = 5,
- [5590] = 6,
- [5594] = 7
+ [4611] = 20,
+ [4613] = 21,
+ [4615] = 22,
+ [4619] = 33,
+ [4621] = 34,
+ [4623] = 35,
+ [4625] = 36,
+ [4627] = 37,
+ [4628] = 2,
+ [4629] = 23,
+ [4630] = 3,
+ [4631] = 24,
+ [4632] = 4,
+ [4633] = 25,
+ [4634] = 5,
+ [4635] = 26,
+ [4636] = 6,
+ [4637] = 27,
+ [4638] = 7,
+ [4639] = 28,
+ [4640] = 8,
+ [4641] = 29,
+ [4642] = 9,
+ [4643] = 30,
+ [4644] = 10,
+ [4645] = 31,
+ [4646] = 11,
+ [4647] = 32,
+ [4682] = 12,
+ [4684] = 13,
+ [4686] = 14,
+ [4688] = 15,
+ [4702] = 16,
+ [4703] = 17,
+ [4704] = 18,
+ [4705] = 19,
+ [6144] = 0,
+ [6145] = 1,
+ [6146] = 2,
+ [6148] = 3,
+ [6150] = 4,
+ [6184] = 5,
+ [6186] = 6,
+ [6188] = 7,
+ [6190] = 8,
+ [6192] = 9,
+ [6194] = 10,
+ [6196] = 11,
+ [6198] = 12,
+ [6272] = 0,
+ [6273] = 1,
+ [6274] = 2,
+ [6276] = 3,
+ [6278] = 4,
+ [6292] = 5,
+ [6294] = 6,
+ [6296] = 7,
+ [6298] = 8,
+ [6300] = 9,
+ [6302] = 10,
+ [6304] = 11,
+ [6306] = 12,
+ [6308] = 13,
+ [6310] = 14,
+ [6400] = 0,
+ [6401] = 1,
+ [6402] = 2,
+ [6404] = 3,
+ [6406] = 4,
+ [6440] = 8,
+ [6442] = 9,
+ [6444] = 10,
+ [6446] = 11,
+ [6448] = 12,
+ [6450] = 13,
+ [6452] = 14,
+ [6454] = 15,
+ [6482] = 5,
+ [6486] = 6,
+ [6490] = 7,
+ [6528] = 0,
+ [6529] = 1,
+ [6530] = 2,
+ [6532] = 3,
+ [6534] = 4,
+ [6548] = 8,
+ [6550] = 9,
+ [6552] = 10,
+ [6554] = 11,
+ [6556] = 12,
+ [6558] = 13,
+ [6560] = 14,
+ [6562] = 15,
+ [6564] = 16,
+ [6566] = 17,
+ [6610] = 5,
+ [6614] = 6,
+ [6618] = 7,
+ [6656] = 0,
+ [6657] = 1,
+ [6658] = 2,
+ [6660] = 3,
+ [6662] = 4,
+ [6696] = 5,
+ [6698] = 6,
+ [6700] = 7,
+ [6702] = 8,
+ [6704] = 9,
+ [6706] = 10,
+ [6708] = 11,
+ [6710] = 12,
+ [6712] = 13,
+ [6714] = 14,
+ [6716] = 15,
+ [6718] = 16,
+ [6720] = 17,
+ [6722] = 18,
+ [6724] = 19,
+ [6726] = 20,
+ [6728] = 21,
+ [6784] = 0,
+ [6785] = 1,
+ [6786] = 2,
+ [6788] = 3,
+ [6790] = 4,
+ [6804] = 5,
+ [6806] = 6,
+ [6808] = 7,
+ [6810] = 8,
+ [6812] = 9,
+ [6814] = 10,
+ [6816] = 11,
+ [6818] = 12,
+ [6820] = 13,
+ [6822] = 14,
+ [6840] = 15,
+ [6842] = 16,
+ [6844] = 17,
+ [6846] = 18,
+ [6848] = 19,
+ [6850] = 20,
+ [6852] = 21,
+ [6854] = 22,
+ [6856] = 23,
+ [6912] = 0,
+ [6913] = 1,
+ [6914] = 2,
+ [6916] = 3,
+ [6918] = 4,
+ [6952] = 5,
+ [6954] = 6,
+ [6956] = 7,
+ [6958] = 8,
+ [6960] = 9,
+ [6962] = 10,
+ [6964] = 11,
+ [6966] = 12,
+ [6986] = 13,
+ [6988] = 14,
+ [6990] = 15,
+ [6992] = 16,
+ [7040] = 0,
+ [7041] = 1,
+ [7042] = 2,
+ [7044] = 3,
+ [7046] = 4,
+ [7060] = 5,
+ [7062] = 6,
+ [7064] = 7,
+ [7066] = 8,
+ [7068] = 9,
+ [7070] = 10,
+ [7072] = 11,
+ [7074] = 12,
+ [7076] = 13,
+ [7078] = 14,
+ [7114] = 15,
+ [7116] = 16,
+ [7118] = 17,
+ [7120] = 18,
+ [7168] = 0,
+ [7169] = 1,
+ [7170] = 2,
+ [7172] = 3,
+ [7174] = 4,
+ [7208] = 8,
+ [7210] = 9,
+ [7212] = 10,
+ [7214] = 11,
+ [7216] = 12,
+ [7218] = 13,
+ [7220] = 14,
+ [7222] = 15,
+ [7224] = 16,
+ [7226] = 17,
+ [7228] = 18,
+ [7230] = 19,
+ [7232] = 20,
+ [7234] = 21,
+ [7236] = 22,
+ [7238] = 23,
+ [7240] = 24,
+ [7250] = 5,
+ [7254] = 6,
+ [7258] = 7,
+ [7296] = 0,
+ [7297] = 1,
+ [7298] = 2,
+ [7300] = 3,
+ [7302] = 4,
+ [7316] = 8,
+ [7318] = 9,
+ [7320] = 10,
+ [7322] = 11,
+ [7324] = 12,
+ [7326] = 13,
+ [7328] = 14,
+ [7330] = 15,
+ [7332] = 16,
+ [7334] = 17,
+ [7352] = 18,
+ [7354] = 19,
+ [7356] = 20,
+ [7358] = 21,
+ [7360] = 22,
+ [7362] = 23,
+ [7364] = 24,
+ [7366] = 25,
+ [7368] = 26,
+ [7378] = 5,
+ [7382] = 6,
+ [7386] = 7,
+ [7424] = 0,
+ [7425] = 1,
+ [7426] = 2,
+ [7428] = 3,
+ [7430] = 4,
+ [7464] = 8,
+ [7466] = 9,
+ [7468] = 10,
+ [7470] = 11,
+ [7472] = 12,
+ [7474] = 13,
+ [7476] = 14,
+ [7478] = 15,
+ [7498] = 16,
+ [7500] = 17,
+ [7502] = 18,
+ [7504] = 19,
+ [7506] = 5,
+ [7510] = 6,
+ [7514] = 7,
+ [7552] = 0,
+ [7553] = 1,
+ [7554] = 2,
+ [7556] = 3,
+ [7558] = 4,
+ [7572] = 8,
+ [7574] = 9,
+ [7576] = 10,
+ [7578] = 11,
+ [7580] = 12,
+ [7582] = 13,
+ [7584] = 14,
+ [7586] = 15,
+ [7588] = 16,
+ [7590] = 17,
+ [7626] = 18,
+ [7628] = 19,
+ [7630] = 20,
+ [7632] = 21,
+ [7634] = 5,
+ [7638] = 6,
+ [7642] = 7
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
index e342f340d9..d20c4197fa 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 13 18:15:56 2021 */
+/* date: Thu May 20 11:56:39 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -22,8 +22,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {
.cond_start_idx = 0,
.cond_nums = 4 }
},
- /* class_tid: 3, ingress */
- [3] = {
+ /* class_tid: 4, ingress */
+ [4] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
.num_tbls = 15,
.start_tbl_idx = 12,
@@ -32,8 +32,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {
.cond_start_idx = 8,
.cond_nums = 1 }
},
- /* class_tid: 4, egress */
- [4] = {
+ /* class_tid: 5, egress */
+ [5] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
.num_tbls = 6,
.start_tbl_idx = 27,
@@ -306,7 +306,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 38,
.result_num_fields = 5
},
- { /* class_tid: 3, , table: int_full_act_record.0 */
+ { /* class_tid: 4, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@@ -327,7 +327,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 128,
.result_num_fields = 17
},
- { /* class_tid: 3, , table: port_table.wr_0 */
+ { /* class_tid: 4, , table: port_table.wr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
@@ -350,7 +350,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 152,
.result_num_fields = 5
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
@@ -372,7 +372,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.ident_start_idx = 6,
.ident_nums = 0
},
- { /* class_tid: 3, , table: control.ing_0 */
+ { /* class_tid: 4, , table: control.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
@@ -385,7 +385,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
+ { /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.direction = TF_DIR_RX,
@@ -414,7 +414,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.ident_start_idx = 6,
.ident_nums = 1
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
@@ -437,7 +437,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */
+ { /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
.direction = TF_DIR_RX,
@@ -455,7 +455,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */
+ { /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
.direction = TF_DIR_RX,
@@ -473,7 +473,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 3, , table: control.egr_0 */
+ { /* class_tid: 4, , table: control.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
@@ -485,7 +485,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 3, , table: int_full_act_record.egr_0 */
+ { /* class_tid: 4, , table: int_full_act_record.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@@ -507,7 +507,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_num_fields = 17,
.encap_num_fields = 0
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
@@ -529,7 +529,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.ident_start_idx = 7,
.ident_nums = 0
},
- { /* class_tid: 3, , table: control.egr_1 */
+ { /* class_tid: 4, , table: control.egr_1 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
@@ -542,7 +542,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
+ { /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.direction = TF_DIR_TX,
@@ -569,7 +569,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.ident_start_idx = 7,
.ident_nums = 1
},
- { /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */
+ { /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
.direction = TF_DIR_TX,
@@ -587,7 +587,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */
+ { /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
.direction = TF_DIR_TX,
@@ -605,7 +605,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 4, , table: int_full_act_record.loopback */
+ { /* class_tid: 5, , table: int_full_act_record.loopback */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@@ -627,7 +627,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_num_fields = 17,
.encap_num_fields = 0
},
- { /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */
+ { /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
.direction = TF_DIR_TX,
@@ -645,7 +645,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */
+ { /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
.direction = TF_DIR_TX,
@@ -663,7 +663,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 4, , table: int_full_act_record.vf_ing */
+ { /* class_tid: 5, , table: int_full_act_record.vf_ing */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@@ -685,7 +685,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_num_fields = 17,
.encap_num_fields = 0
},
- { /* class_tid: 4, , table: vtag_encap_record.vfr_egr0 */
+ { /* class_tid: 5, , table: vtag_encap_record.vfr_egr0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
.resource_sub_type =
@@ -707,7 +707,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_num_fields = 0,
.encap_num_fields = 11
},
- { /* class_tid: 4, , table: int_full_act_record.vfr_egr0 */
+ { /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@@ -768,27 +768,27 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
.cond_operand = BNXT_ULP_CF_IDX_O_L4
},
- /* cond_reject: thor, class_tid: 3 */
+ /* cond_reject: thor, class_tid: 4 */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
},
- /* cond_execute: class_tid: 3, control.ing_0 */
+ /* cond_execute: class_tid: 4, control.ing_0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 3, control.egr_0 */
+ /* cond_execute: class_tid: 4, control.egr_0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
},
- /* cond_execute: class_tid: 3, control.egr_1 */
+ /* cond_execute: class_tid: 4, control.egr_1 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_reject: thor, class_tid: 4 */
+ /* cond_reject: thor, class_tid: 5 */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
@@ -3612,7 +3612,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
- /* class_tid: 3, , table: port_table.wr_0 */
+ /* class_tid: 4, , table: port_table.wr_0 */
{
.field_info_mask = {
.description = "dev.port_id",
@@ -3633,7 +3633,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
{
.field_info_mask = {
.description = "svif",
@@ -3653,7 +3653,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
.field_info_mask = {
.description = "etype",
@@ -3958,7 +3958,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
1}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
{
.field_info_mask = {
.description = "svif",
@@ -3978,7 +3978,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */
{
.field_info_mask = {
.description = "svif",
@@ -3998,7 +3998,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
.field_info_mask = {
.description = "etype",
@@ -5187,7 +5187,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 3, , table: int_full_act_record.0 */
+ /* class_tid: 4, , table: int_full_act_record.0 */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -5295,7 +5295,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 3, , table: port_table.wr_0 */
+ /* class_tid: 4, , table: port_table.wr_0 */
{
.description = "rid",
.field_bit_size = 32,
@@ -5329,7 +5329,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
- /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
.description = "prof_func_id",
.field_bit_size = 7,
@@ -5380,7 +5380,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -5414,7 +5414,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */
+ /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -5424,7 +5424,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
- /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */
+ /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -5434,7 +5434,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
- /* class_tid: 3, , table: int_full_act_record.egr_0 */
+ /* class_tid: 4, , table: int_full_act_record.egr_0 */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -5542,7 +5542,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
.description = "prof_func_id",
.field_bit_size = 7,
@@ -5593,7 +5593,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
},
- /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */
+ /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -5603,7 +5603,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */
+ /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -5613,7 +5613,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 4, , table: int_full_act_record.loopback */
+ /* class_tid: 5, , table: int_full_act_record.loopback */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -5721,7 +5721,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */
+ /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -5731,7 +5731,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
- /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */
+ /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -5741,7 +5741,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
- /* class_tid: 4, , table: int_full_act_record.vf_ing */
+ /* class_tid: 5, , table: int_full_act_record.vf_ing */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -5849,7 +5849,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 4, , table: vtag_encap_record.vfr_egr0 */
+ /* class_tid: 5, , table: vtag_encap_record.vfr_egr0 */
{
.description = "ecv_tun_type",
.field_bit_size = 3,
@@ -5929,7 +5929,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
},
- /* class_tid: 4, , table: int_full_act_record.vfr_egr0 */
+ /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -6085,7 +6085,7 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 29
},
- /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
.description = "l2_cntxt_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -6094,7 +6094,7 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 29
},
- /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
.description = "l2_cntxt_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
index b6d2afd55b..de924fe81a 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 13 18:15:56 2021 */
+/* date: Mon May 17 15:54:03 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
index 85b8950e49..7b6ee03a4b 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Fri May 14 10:26:31 2021 */
+/* date: Mon May 17 15:54:03 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -22,7 +22,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = {
.cond_start_idx = 0,
.cond_nums = 1 }
},
- /* class_tid: 2, egress */
+ /* class_tid: 2, ingress */
[2] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
.num_tbls = 15,
@@ -32,24 +32,34 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = {
.cond_start_idx = 24,
.cond_nums = 1 }
},
- /* class_tid: 3, ingress */
+ /* class_tid: 3, egress */
[3] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .num_tbls = 22,
+ .num_tbls = 15,
.start_tbl_idx = 33,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 30,
+ .cond_nums = 1 }
+ },
+ /* class_tid: 4, ingress */
+ [4] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 22,
+ .start_tbl_idx = 48,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 35,
+ .cond_start_idx = 41,
.cond_nums = 0 }
},
- /* class_tid: 4, egress */
- [4] = {
+ /* class_tid: 5, egress */
+ [5] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
.num_tbls = 19,
- .start_tbl_idx = 55,
+ .start_tbl_idx = 70,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 41,
+ .cond_start_idx = 47,
.cond_nums = 0 }
}
};
@@ -455,58 +465,133 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.result_bit_size = 64,
.result_num_fields = 9
},
- { /* class_tid: 2, , table: l2_cntxt_tcam_cache.rd */
+ { /* class_tid: 2, , table: tunnel_cache.rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 5,
+ .cond_true_goto = 1,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 25,
- .cond_nums = 1 },
+ .cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 223,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
+ .blob_key_bit_size = 16,
+ .key_bit_size = 16,
+ .key_num_fields = 2,
.ident_start_idx = 9,
.ident_nums = 1
},
+ { /* class_tid: 2, , table: control.tunnel_cache_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 25,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ { /* class_tid: 2, , table: l2_cntxt_tcam.1 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 26,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 225,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 127,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .ident_start_idx = 10,
+ .ident_nums = 1
+ },
+ { /* class_tid: 2, , table: tunnel_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 26,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 238,
+ .blob_key_bit_size = 16,
+ .key_bit_size = 16,
+ .key_num_fields = 2,
+ .result_start_idx = 140,
+ .result_bit_size = 52,
+ .result_num_fields = 3
+ },
+ { /* class_tid: 2, , table: control.flow_type_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 5,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 26,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
{ /* class_tid: 2, , table: mac_addr_cache.rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 26,
+ .cond_start_idx = 27,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 224,
+ .key_start_idx = 240,
.blob_key_bit_size = 73,
.key_bit_size = 73,
.key_num_fields = 5,
- .ident_start_idx = 10,
+ .ident_start_idx = 11,
.ident_nums = 1
},
- { /* class_tid: 2, , table: control.0 */
+ { /* class_tid: 2, , table: control.mac_addr_cache_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 3,
+ .cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 26,
+ .cond_start_idx = 27,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
@@ -515,12 +600,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
{ /* class_tid: 2, , table: l2_cntxt_tcam.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 27,
+ .cond_start_idx = 28,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
@@ -529,323 +614,236 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 229,
+ .key_start_idx = 245,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 127,
+ .result_start_idx = 143,
.result_bit_size = 64,
.result_num_fields = 13,
- .ident_start_idx = 11,
- .ident_nums = 1
+ .ident_start_idx = 12,
+ .ident_nums = 0
},
{ /* class_tid: 2, , table: mac_addr_cache.wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 27,
+ .cond_start_idx = 28,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 242,
+ .key_start_idx = 258,
.blob_key_bit_size = 73,
.key_bit_size = 73,
.key_num_fields = 5,
- .result_start_idx = 140,
+ .result_start_idx = 156,
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 2, , table: profile_tcam_cache.rd */
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 27,
+ .cond_start_idx = 28,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 247,
+ .key_start_idx = 263,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
.ident_start_idx = 12,
.ident_nums = 3
},
- { /* class_tid: 2, , table: control.gen_tbl_miss */
+ { /* class_tid: 2, , table: control.profile_tcam_cache.f2_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 2,
- .cond_false_goto = 1,
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 27,
+ .cond_start_idx = 28,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 2, , table: control.conflict_check */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 4,
- .cond_false_goto = 1023,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 28,
- .cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .func_info = {
- .func_opc = BNXT_ULP_FUNC_OPC_EQ,
- .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
- .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
- .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
- .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
- .func_dst_opr = BNXT_ULP_RF_IDX_CC },
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
- },
- { /* class_tid: 2, , table: profile_tcam.ipv4 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 2,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 29,
- .cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 250,
- .blob_key_bit_size = 81,
- .key_bit_size = 81,
- .key_num_fields = 43,
- .result_start_idx = 144,
- .result_bit_size = 38,
- .result_num_fields = 17,
- .ident_start_idx = 15,
- .ident_nums = 1
- },
- { /* class_tid: 2, , table: profile_tcam.ipv6 */
+ { /* class_tid: 2, , table: profile_tcam.f2 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 30,
+ .cond_start_idx = 29,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 1,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 293,
+ .key_start_idx = 266,
.blob_key_bit_size = 81,
.key_bit_size = 81,
.key_num_fields = 43,
- .result_start_idx = 161,
+ .result_start_idx = 160,
.result_bit_size = 38,
- .result_num_fields = 17,
- .ident_start_idx = 16,
- .ident_nums = 1
+ .result_num_fields = 17
},
- { /* class_tid: 2, , table: profile_tcam_cache.wr */
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 30,
+ .cond_start_idx = 29,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 336,
+ .key_start_idx = 309,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
- .result_start_idx = 178,
+ .result_start_idx = 177,
.result_bit_size = 122,
.result_num_fields = 5
},
- { /* class_tid: 2, , table: em.ipv4 */
+ { /* class_tid: 2, , table: em.tun */
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_MEM_INTERNAL,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 0,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 30,
- .cond_nums = 2 },
+ .cond_start_idx = 29,
+ .cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 339,
- .blob_key_bit_size = 176,
- .key_bit_size = 176,
- .key_num_fields = 10,
- .result_start_idx = 183,
+ .key_start_idx = 312,
+ .blob_key_bit_size = 112,
+ .key_bit_size = 112,
+ .key_num_fields = 8,
+ .result_start_idx = 182,
.result_bit_size = 64,
.result_num_fields = 9
},
- { /* class_tid: 2, , table: eem.ipv4 */
+ { /* class_tid: 2, , table: eem.tun */
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_MEM_EXTERNAL,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 0,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 32,
- .cond_nums = 2 },
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 30,
+ .cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 349,
+ .key_start_idx = 320,
.blob_key_bit_size = 448,
.key_bit_size = 448,
- .key_num_fields = 10,
- .result_start_idx = 192,
+ .key_num_fields = 8,
+ .result_start_idx = 191,
.result_bit_size = 64,
.result_num_fields = 9
},
- { /* class_tid: 2, , table: em.ipv6 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
- .resource_type = TF_MEM_INTERNAL,
+ { /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 0,
+ .cond_true_goto = 5,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 34,
+ .cond_start_idx = 31,
.cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 359,
- .blob_key_bit_size = 416,
- .key_bit_size = 416,
- .key_num_fields = 11,
- .result_start_idx = 201,
- .result_bit_size = 64,
- .result_num_fields = 9
+ .key_start_idx = 328,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 15,
+ .ident_nums = 1
},
- { /* class_tid: 2, , table: eem.ipv6 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
- .resource_type = TF_MEM_EXTERNAL,
+ { /* class_tid: 3, , table: mac_addr_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 0,
- .cond_false_goto = 0,
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 35,
+ .cond_start_idx = 32,
.cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 370,
- .blob_key_bit_size = 448,
- .key_bit_size = 448,
- .key_num_fields = 11,
- .result_start_idx = 210,
- .result_bit_size = 64,
- .result_num_fields = 9
+ .key_start_idx = 329,
+ .blob_key_bit_size = 73,
+ .key_bit_size = 73,
+ .key_num_fields = 5,
+ .ident_start_idx = 16,
+ .ident_nums = 1
},
- { /* class_tid: 3, , table: int_full_act_record.ing_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 35,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 219,
- .result_bit_size = 128,
- .result_num_fields = 26
- },
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 35,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 381,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .ident_start_idx = 17,
- .ident_nums = 0
- },
- { /* class_tid: 3, , table: control.ing_0 */
+ { /* class_tid: 3, , table: control.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_RX,
+ .direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 3,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 35,
+ .cond_start_idx = 32,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
+ { /* class_tid: 3, , table: l2_cntxt_tcam.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .direction = TF_DIR_RX,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 36,
+ .cond_start_idx = 33,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
@@ -853,361 +851,240 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 382,
+ .key_start_idx = 334,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 245,
+ .result_start_idx = 200,
.result_bit_size = 64,
.result_num_fields = 13,
.ident_start_idx = 17,
.ident_nums = 1
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */
+ { /* class_tid: 3, , table: mac_addr_cache.wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
- .direction = TF_DIR_RX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
+ .direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 36,
+ .cond_start_idx = 33,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 395,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .result_start_idx = 258,
+ .key_start_idx = 347,
+ .blob_key_bit_size = 73,
+ .key_bit_size = 73,
+ .key_num_fields = 5,
+ .result_start_idx = 213,
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 3, , table: parif_def_lkup_arec_ptr.ing_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 36,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 262,
- .result_bit_size = 32,
- .result_num_fields = 1
- },
- { /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
- .direction = TF_DIR_RX,
+ { /* class_tid: 3, , table: profile_tcam_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 36,
+ .cond_start_idx = 33,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 263,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .key_start_idx = 352,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .ident_start_idx = 18,
+ .ident_nums = 3
},
- { /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
- .direction = TF_DIR_RX,
+ { /* class_tid: 3, , table: control.gen_tbl_miss */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 2,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 36,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 264,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 33,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 3, , table: control.egr_0 */
+ { /* class_tid: 3, , table: control.conflict_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_RX,
+ .direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 6,
+ .cond_true_goto = 4,
+ .cond_false_goto = 1023,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 36,
+ .cond_start_idx = 34,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .func_info = {
+ .func_opc = BNXT_ULP_FUNC_OPC_EQ,
+ .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
+ .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
+ .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC },
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 3, , table: int_full_act_record.egr_vfr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 37,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 265,
- .result_bit_size = 128,
- .result_num_fields = 26,
- .encap_num_fields = 0
- },
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd_vfr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ { /* class_tid: 3, , table: profile_tcam.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 2,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 37,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 396,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .ident_start_idx = 18,
- .ident_nums = 0
- },
- { /* class_tid: 3, , table: control.egr_1 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 37,
+ .cond_start_idx = 35,
.cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 355,
+ .blob_key_bit_size = 81,
+ .key_bit_size = 81,
+ .key_num_fields = 43,
+ .result_start_idx = 217,
+ .result_bit_size = 38,
+ .result_num_fields = 17,
+ .ident_start_idx = 21,
+ .ident_nums = 1
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_bypass.egr_vfr */
+ { /* class_tid: 3, , table: profile_tcam.ipv6 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 38,
+ .cond_start_idx = 36,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
- .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 397,
- .blob_key_bit_size = 167,
- .key_bit_size = 167,
- .key_num_fields = 13,
- .result_start_idx = 291,
- .result_bit_size = 64,
- .result_num_fields = 13,
- .ident_start_idx = 18,
- .ident_nums = 0
+ .key_start_idx = 398,
+ .blob_key_bit_size = 81,
+ .key_bit_size = 81,
+ .key_num_fields = 43,
+ .result_start_idx = 234,
+ .result_bit_size = 38,
+ .result_num_fields = 17,
+ .ident_start_idx = 22,
+ .ident_nums = 1
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
+ { /* class_tid: 3, , table: profile_tcam_cache.wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 0,
+ .cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 38,
+ .cond_start_idx = 36,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 410,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .result_start_idx = 304,
- .result_bit_size = 62,
- .result_num_fields = 4
+ .key_start_idx = 441,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .result_start_idx = 251,
+ .result_bit_size = 122,
+ .result_num_fields = 5
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ { /* class_tid: 3, , table: em.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_INTERNAL,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 38,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 36,
+ .cond_nums = 2 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 411,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .ident_start_idx = 18,
- .ident_nums = 0
- },
- { /* class_tid: 3, , table: control.egr_2 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 3,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 38,
- .cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
- },
- { /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 39,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 412,
- .blob_key_bit_size = 167,
- .key_bit_size = 167,
- .key_num_fields = 13,
- .result_start_idx = 308,
+ .key_start_idx = 444,
+ .blob_key_bit_size = 176,
+ .key_bit_size = 176,
+ .key_num_fields = 10,
+ .result_start_idx = 256,
.result_bit_size = 64,
- .result_num_fields = 13,
- .ident_start_idx = 18,
- .ident_nums = 1
+ .result_num_fields = 9
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ { /* class_tid: 3, , table: eem.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_EXTERNAL,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 39,
+ .cond_start_idx = 38,
.cond_nums = 2 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 425,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .result_start_idx = 321,
- .result_bit_size = 62,
- .result_num_fields = 4
- },
- { /* class_tid: 3, , table: int_full_act_record.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 41,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 325,
- .result_bit_size = 128,
- .result_num_fields = 26,
- .encap_num_fields = 0
- },
- { /* class_tid: 3, , table: parif_def_lkup_arec_ptr.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 41,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 351,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .key_start_idx = 454,
+ .blob_key_bit_size = 448,
+ .key_bit_size = 448,
+ .key_num_fields = 10,
+ .result_start_idx = 265,
+ .result_bit_size = 64,
+ .result_num_fields = 9
},
- { /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+ { /* class_tid: 3, , table: em.ipv6 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_INTERNAL,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 41,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 40,
+ .cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 352,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .key_start_idx = 464,
+ .blob_key_bit_size = 416,
+ .key_bit_size = 416,
+ .key_num_fields = 11,
+ .result_start_idx = 274,
+ .result_bit_size = 64,
+ .result_num_fields = 9
},
- { /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
+ { /* class_tid: 3, , table: eem.ipv6 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_EXTERNAL,
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 0,
@@ -1215,41 +1092,44 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 41,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 353,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .key_start_idx = 475,
+ .blob_key_bit_size = 448,
+ .key_bit_size = 448,
+ .key_num_fields = 11,
+ .result_start_idx = 283,
+ .result_bit_size = 64,
+ .result_num_fields = 9
},
- { /* class_tid: 4, , table: int_full_act_record.loopback */
+ { /* class_tid: 4, , table: int_full_act_record.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 41,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE,
- .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 354,
+ .result_start_idx = 292,
.result_bit_size = 128,
- .result_num_fields = 26,
- .encap_num_fields = 0
+ .result_num_fields = 26
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_rd_egr */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
@@ -1260,16 +1140,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 426,
+ .key_start_idx = 486,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .ident_start_idx = 19,
+ .ident_start_idx = 23,
.ident_nums = 0
},
- { /* class_tid: 4, , table: control.vf_0 */
+ { /* class_tid: 4, , table: control.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 3,
@@ -1280,10 +1160,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */
+ { /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
@@ -1296,22 +1176,24 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 427,
+ .key_start_idx = 487,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 380,
+ .result_start_idx = 318,
.result_bit_size = 64,
.result_num_fields = 13,
- .ident_start_idx = 19,
+ .ident_start_idx = 23,
.ident_nums = 1
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
@@ -1322,119 +1204,103 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 440,
+ .key_start_idx = 500,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .result_start_idx = 393,
+ .result_start_idx = 331,
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 4, , table: parif_def_lkup_arec_ptr.vf_egr */
+ { /* class_tid: 4, , table: parif_def_lkup_arec_ptr.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 42,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
- .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 397,
+ .result_start_idx = 335,
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */
+ { /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 42,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
- .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 398,
+ .result_start_idx = 336,
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */
+ { /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 42,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
- .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 399,
+ .result_start_idx = 337,
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 4, , table: int_full_act_record.vf_ing */
+ { /* class_tid: 4, , table: control.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 6,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 42,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ { /* class_tid: 4, , table: int_full_act_record.egr_vfr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_RX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 400,
+ .result_start_idx = 338,
.result_bit_size = 128,
.result_num_fields = 26,
.encap_num_fields = 0
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vf_ing */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
- .pri_operand = 0,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 441,
- .blob_key_bit_size = 167,
- .key_bit_size = 167,
- .key_num_fields = 13,
- .result_start_idx = 426,
- .result_bit_size = 64,
- .result_num_fields = 13,
- .ident_start_idx = 20,
- .ident_nums = 0
- },
- { /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_rd_egr0 */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd_vfr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
@@ -1443,33 +1309,33 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 454,
+ .key_start_idx = 501,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .ident_start_idx = 20,
+ .ident_start_idx = 24,
.ident_nums = 0
},
- { /* class_tid: 4, , table: control.vfr_0 */
+ { /* class_tid: 4, , table: control.egr_1 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 3,
+ .cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_egr0 */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.egr_vfr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.direction = TF_DIR_TX,
@@ -1477,7 +1343,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 43,
+ .cond_start_idx = 44,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
@@ -1486,140 +1352,392 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 455,
+ .key_start_idx = 502,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 439,
+ .result_start_idx = 364,
.result_bit_size = 64,
.result_num_fields = 13,
- .ident_start_idx = 20,
+ .ident_start_idx = 24,
.ident_nums = 0
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 43,
+ .cond_start_idx = 44,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 468,
+ .key_start_idx = 515,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .result_start_idx = 452,
+ .result_start_idx = 377,
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 4, , table: int_vtag_encap_record.vfr_egr0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 43,
+ .cond_start_idx = 44,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 456,
- .result_bit_size = 0,
- .result_num_fields = 0,
- .encap_num_fields = 12
+ .key_start_idx = 516,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 24,
+ .ident_nums = 0
},
- { /* class_tid: 4, , table: int_full_act_record.vfr_egr0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
- .execute_info = {
+ { /* class_tid: 4, , table: control.egr_2 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 44,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .direction = TF_DIR_TX,
+ .execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 43,
+ .cond_start_idx = 45,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 517,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 381,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .ident_start_idx = 24,
+ .ident_nums = 1
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 45,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 530,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 394,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 4, , table: int_full_act_record.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 47,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 468,
+ .result_start_idx = 398,
.result_bit_size = 128,
- .result_num_fields = 26
+ .result_num_fields = 26,
+ .encap_num_fields = 0
+ },
+ { /* class_tid: 4, , table: parif_def_lkup_arec_ptr.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 47,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 424,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 47,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 425,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 47,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 426,
+ .result_bit_size = 32,
+ .result_num_fields = 1
},
- { /* class_tid: 4, , table: int_full_act_record.vfr_ing0 */
+ { /* class_tid: 5, , table: int_full_act_record.loopback */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_RX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 43,
+ .cond_start_idx = 47,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 494,
+ .result_start_idx = 427,
.result_bit_size = 128,
- .result_num_fields = 26
+ .result_num_fields = 26,
+ .encap_num_fields = 0
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 47,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 531,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 25,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: control.vf_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 47,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */
+ { /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .direction = TF_DIR_RX,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 43,
+ .cond_start_idx = 48,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 469,
+ .key_start_idx = 532,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 520,
+ .result_start_idx = 453,
.result_bit_size = 64,
.result_num_fields = 13,
- .ident_start_idx = 20,
- .ident_nums = 0
+ .ident_start_idx = 25,
+ .ident_nums = 1
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 545,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 466,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 5, , table: parif_def_lkup_arec_ptr.vf_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
+ .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 470,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
+ .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 471,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
+ .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 472,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 5, , table: int_full_act_record.vf_ing */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 473,
+ .result_bit_size = 128,
+ .result_num_fields = 26,
+ .encap_num_fields = 0
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */
+ { /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vf_ing */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
.direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 0,
- .cond_false_goto = 0,
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 43,
+ .cond_start_idx = 48,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
@@ -1629,19 +1747,224 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 482,
+ .key_start_idx = 546,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 533,
+ .result_start_idx = 499,
.result_bit_size = 64,
.result_num_fields = 13,
- .ident_start_idx = 20,
+ .ident_start_idx = 26,
.ident_nums = 0
- }
-};
-
-struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_rd_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 559,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 26,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: control.vfr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 48,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 560,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 512,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .ident_start_idx = 26,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 573,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 525,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 5, , table: int_vtag_encap_record.vfr_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 529,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 12
+ },
+ { /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 541,
+ .result_bit_size = 128,
+ .result_num_fields = 26
+ },
+ { /* class_tid: 5, , table: int_full_act_record.vfr_ing0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 567,
+ .result_bit_size = 128,
+ .result_num_fields = 26
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 574,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 593,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .ident_start_idx = 26,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 587,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 606,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .ident_start_idx = 26,
+ .ident_nums = 0
+ }
+};
+
+struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {
/* cond_reject: wh_plus, class_tid: 1 */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
@@ -1751,32 +2074,61 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
.cond_operand = BNXT_ULP_CF_IDX_WC_MATCH
},
- /* cond_execute: class_tid: 2, l2_cntxt_tcam_cache.rd */
+ /* cond_execute: class_tid: 2, control.tunnel_cache_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 2, control.flow_type_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_F1
+ },
+ /* cond_execute: class_tid: 2, control.mac_addr_cache_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 2, control.profile_tcam_cache.f2_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 2, em.tun */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET,
+ },
+ /* cond_reject: wh_plus, class_tid: 3 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH
+ },
+ /* cond_execute: class_tid: 3, l2_cntxt_tcam_cache.rd */
{
.cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET,
.cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC
},
- /* cond_execute: class_tid: 2, control.0 */
+ /* cond_execute: class_tid: 3, control.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 2, control.gen_tbl_miss */
+ /* cond_execute: class_tid: 3, control.gen_tbl_miss */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 2, control.conflict_check */
+ /* cond_execute: class_tid: 3, control.conflict_check */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_CC
},
- /* cond_execute: class_tid: 2, profile_tcam.ipv4 */
+ /* cond_execute: class_tid: 3, profile_tcam.ipv4 */
{
.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
},
- /* cond_execute: class_tid: 2, em.ipv4 */
+ /* cond_execute: class_tid: 3, em.ipv4 */
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET,
},
@@ -1784,7 +2136,7 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
},
- /* cond_execute: class_tid: 2, eem.ipv4 */
+ /* cond_execute: class_tid: 3, eem.ipv4 */
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_IS_SET,
},
@@ -1792,31 +2144,31 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
},
- /* cond_execute: class_tid: 2, em.ipv6 */
+ /* cond_execute: class_tid: 3, em.ipv6 */
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET,
},
- /* cond_execute: class_tid: 3, control.ing_0 */
+ /* cond_execute: class_tid: 4, control.ing_0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 3, control.egr_0 */
+ /* cond_execute: class_tid: 4, control.egr_0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
},
- /* cond_execute: class_tid: 3, control.egr_1 */
+ /* cond_execute: class_tid: 4, control.egr_1 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 3, control.egr_2 */
+ /* cond_execute: class_tid: 4, control.egr_2 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 3, l2_cntxt_tcam_cache.egr_wr */
+ /* cond_execute: class_tid: 4, l2_cntxt_tcam_cache.egr_wr */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
@@ -1825,12 +2177,12 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 4, control.vf_0 */
+ /* cond_execute: class_tid: 5, control.vf_0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 4, control.vfr_0 */
+ /* cond_execute: class_tid: 5, control.vfr_0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
@@ -5669,7 +6021,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
}
},
- /* class_tid: 2, , table: l2_cntxt_tcam_cache.rd */
+ /* class_tid: 2, , table: tunnel_cache.rd */
{
.field_info_mask = {
.description = "svif",
@@ -5690,181 +6042,52 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
}
},
- /* class_tid: 2, , table: mac_addr_cache.rd */
{
.field_info_mask = {
- .description = "svif",
+ .description = "tunnel_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ 0xff}
},
.field_info_spec = {
- .description = "svif",
+ .description = "tunnel_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ (BNXT_ULP_CF_IDX_TUNNEL_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_TUNNEL_ID & 0xff}
}
},
+ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
{
.field_info_mask = {
- .description = "tun_hdr",
- .field_bit_size = 4,
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr",
- .field_bit_size = 4,
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "one_tag",
- .field_bit_size = 1,
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "one_tag",
- .field_bit_size = 1,
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
- }
- },
- {
- .field_info_mask = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
- },
- .field_info_spec = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
- }
- },
- /* class_tid: 2, , table: l2_cntxt_tcam.0 */
- {
- .field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -5872,19 +6095,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "mac0_addr",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "mac0_addr",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -5892,19 +6109,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "svif",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "svif",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -5968,18 +6179,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "l2_num_vtags",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l2_num_vtags",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -6046,7 +6252,47 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
1}
}
},
- /* class_tid: 2, , table: mac_addr_cache.wr */
+ /* class_tid: 2, , table: tunnel_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_TUNNEL_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_TUNNEL_ID & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: mac_addr_cache.rd */
{
.field_info_mask = {
.description = "svif",
@@ -6072,17 +6318,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "tun_hdr",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ 0xff}
},
.field_info_spec = {
.description = "tun_hdr",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -6090,60 +6334,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "one_tag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "one_tag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
.description = "vid",
.field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "vid",
.field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -6153,8 +6364,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
},
.field_info_spec = {
.description = "mac_addr",
@@ -6162,204 +6373,166 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
- /* class_tid: 2, , table: profile_tcam_cache.rd */
+ /* class_tid: 2, , table: l2_cntxt_tcam.0 */
{
.field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
+ .description = "mac0_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
+ .description = "mac0_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
- /* class_tid: 2, , table: profile_tcam.ipv4 */
{
.field_info_mask = {
- .description = "l4_hdr_is_udp_tcp",
- .field_bit_size = 1,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
},
.field_info_spec = {
- .description = "l4_hdr_is_udp_tcp",
- .field_bit_size = 1,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
}
},
{
.field_info_mask = {
- .description = "l4_hdr_type",
+ .description = "sparif",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l4_hdr_type",
+ .description = "sparif",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_WP_SYM_L4_HDR_TYPE_TCP},
- .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr3 = {
- ULP_WP_SYM_L4_HDR_TYPE_UDP}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4_hdr_error",
- .field_bit_size = 1,
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l4_hdr_error",
- .field_bit_size = 1,
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4_hdr_valid",
- .field_bit_size = 1,
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l4_hdr_valid",
- .field_bit_size = 1,
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_ipv6_cmp_dst",
- .field_bit_size = 1,
+ .description = "mac1_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_ipv6_cmp_dst",
- .field_bit_size = 1,
+ .description = "mac1_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_hdr_type",
+ .description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
@@ -6367,7 +6540,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "l3_hdr_type",
+ .description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6375,162 +6548,200 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "l3_hdr_error",
- .field_bit_size = 1,
+ .description = "key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_hdr_error",
- .field_bit_size = 1,
+ .description = "key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_hdr_valid",
+ .description = "valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 0xff}
+ 1}
},
.field_info_spec = {
- .description = "l3_hdr_valid",
+ .description = "valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ULP_WP_SYM_L3_HDR_VALID_YES}
+ 1}
}
},
+ /* class_tid: 2, , table: mac_addr_cache.wr */
{
.field_info_mask = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
+ .description = "tun_hdr",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_vtag_present",
+ .description = "one_tag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_vtag_present",
+ .description = "one_tag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_uc_mc_bc",
- .field_bit_size = 2,
+ .description = "vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_uc_mc_bc",
- .field_bit_size = 2,
+ .description = "vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_hdr_type",
- .field_bit_size = 2,
+ .description = "mac_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "l2_hdr_type",
- .field_bit_size = 2,
+ .description = "mac_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
+ /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
{
.field_info_mask = {
- .description = "l2_hdr_error",
- .field_bit_size = 1,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l2_hdr_error",
- .field_bit_size = 1,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_hdr_valid",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l2_hdr_valid",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- ULP_WP_SYM_L2_HDR_VALID_YES}
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "tun_hdr_flags",
- .field_bit_size = 3,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: profile_tcam.f2 */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_flags",
- .field_bit_size = 3,
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
+ .description = "l4_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_type",
+ .description = "l4_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6538,13 +6749,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tun_hdr_err",
+ .description = "l4_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_err",
+ .description = "l4_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6552,15 +6763,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tun_hdr_valid",
+ .description = "l4_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_valid",
+ .description = "l4_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6568,13 +6777,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl4_hdr_is_udp_tcp",
+ .description = "l3_ipv6_cmp_dst",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4_hdr_is_udp_tcp",
+ .description = "l3_ipv6_cmp_dst",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6582,27 +6791,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl4_hdr_type",
- .field_bit_size = 4,
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4_hdr_type",
- .field_bit_size = 4,
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4_hdr_error",
+ .description = "l3_hdr_isIP",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4_hdr_error",
+ .description = "l3_hdr_isIP",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6610,29 +6819,44 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl4_hdr_valid",
- .field_bit_size = 1,
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "tl4_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_WP_SYM_L3_HDR_TYPE_IPV4},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_WP_SYM_L3_HDR_TYPE_IPV6}
}
},
{
.field_info_mask = {
- .description = "tl3_ipv6_cmp_dst",
+ .description = "l3_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3_ipv6_cmp_dst",
+ .description = "l3_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6640,27 +6864,31 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl3_ipv6_cmp_src",
+ .description = "l3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3_ipv6_cmp_src",
+ .description = "l3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_L3_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl3_hdr_isIP",
+ .description = "l2_two_vtags",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3_hdr_isIP",
+ .description = "l2_two_vtags",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6668,57 +6896,55 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl3_hdr_type",
- .field_bit_size = 4,
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3_hdr_type",
- .field_bit_size = 4,
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3_hdr_error",
- .field_bit_size = 1,
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3_hdr_error",
- .field_bit_size = 1,
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3_hdr_valid",
- .field_bit_size = 1,
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3_hdr_valid",
- .field_bit_size = 1,
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_two_vtags",
+ .description = "l2_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_two_vtags",
+ .description = "l2_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6726,13 +6952,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl2_vtag_present",
+ .description = "l2_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_vtag_present",
+ .description = "l2_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6740,35 +6966,37 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl2_uc_mc_bc",
- .field_bit_size = 2,
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_uc_mc_bc",
- .field_bit_size = 2,
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_hdr_type",
- .field_bit_size = 2,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_hdr_type",
- .field_bit_size = 2,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_hdr_valid",
+ .description = "tun_hdr_err",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
@@ -6776,7 +7004,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "tl2_hdr_valid",
+ .description = "tun_hdr_err",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6784,68 +7012,65 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "hrec_next",
+ .description = "tun_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "hrec_next",
+ .description = "tun_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_TUN_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "reserved",
- .field_bit_size = 9,
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "reserved",
- .field_bit_size = 9,
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ ULP_WP_SYM_TL4_HDR_TYPE_UDP}
}
},
{
.field_info_mask = {
- .description = "agg_error",
+ .description = "tl4_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "agg_error",
+ .description = "tl4_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6853,159 +7078,137 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_TL4_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "pkt_type_0",
- .field_bit_size = 2,
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "pkt_type_0",
- .field_bit_size = 2,
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "pkt_type_1",
- .field_bit_size = 2,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "pkt_type_1",
- .field_bit_size = 2,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "valid",
+ .description = "tl3_hdr_isIP",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "valid",
+ .description = "tl3_hdr_isIP",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 2, , table: profile_tcam.ipv6 */
{
.field_info_mask = {
- .description = "l4_hdr_is_udp_tcp",
- .field_bit_size = 1,
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "l4_hdr_is_udp_tcp",
- .field_bit_size = 1,
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ 0xff}
},
.field_info_spec = {
- .description = "l4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_WP_SYM_L4_HDR_TYPE_TCP},
- .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr3 = {
- ULP_WP_SYM_L4_HDR_TYPE_UDP}
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4_hdr_error",
+ .description = "tl3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ 0xff}
},
.field_info_spec = {
- .description = "l4_hdr_error",
+ .description = "tl3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_TL3_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "l4_hdr_valid",
+ .description = "tl2_two_vtags",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l4_hdr_valid",
+ .description = "tl2_two_vtags",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_ipv6_cmp_dst",
+ .description = "tl2_vtag_present",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_ipv6_cmp_dst",
+ .description = "tl2_vtag_present",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -7013,61 +7216,61 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_hdr_type",
- .field_bit_size = 4,
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l3_hdr_type",
- .field_bit_size = 4,
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ULP_WP_SYM_L3_HDR_TYPE_IPV6}
+ ULP_WP_SYM_TL2_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "l3_hdr_error",
+ .description = "hrec_next",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_hdr_error",
+ .description = "hrec_next",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -7075,68 +7278,60 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "l3_hdr_valid",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_hdr_valid",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_L3_HDR_VALID_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "l2_vtag_present",
+ .description = "agg_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_vtag_present",
+ .description = "agg_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_uc_mc_bc",
+ .description = "recycle_cnt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_uc_mc_bc",
+ .description = "recycle_cnt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -7144,15 +7339,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "l2_hdr_type",
+ .description = "pkt_type_0",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_hdr_type",
+ .description = "pkt_type_0",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -7160,1487 +7353,1459 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "l2_hdr_error",
- .field_bit_size = 1,
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_hdr_error",
- .field_bit_size = 1,
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_hdr_valid",
+ .description = "valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 0xff}
+ 1}
},
.field_info_spec = {
- .description = "l2_hdr_valid",
+ .description = "valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ULP_WP_SYM_L2_HDR_VALID_YES}
+ 1}
}
},
+ /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
{
.field_info_mask = {
- .description = "tun_hdr_flags",
- .field_bit_size = 3,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tun_hdr_flags",
- .field_bit_size = 3,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "tun_hdr_err",
- .field_bit_size = 1,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tun_hdr_err",
- .field_bit_size = 1,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
}
},
+ /* class_tid: 2, , table: em.tun */
{
.field_info_mask = {
- .description = "tun_hdr_valid",
- .field_bit_size = 1,
+ .description = "spare",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_valid",
- .field_bit_size = 1,
+ .description = "spare",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4_hdr_is_udp_tcp",
- .field_bit_size = 1,
+ .description = "l2.ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4_hdr_is_udp_tcp",
- .field_bit_size = 1,
+ .description = "l2.ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2.dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "tl4_hdr_type",
- .field_bit_size = 4,
+ .description = "l2.dmac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl4_hdr_error",
- .field_bit_size = 1,
+ .description = "tun_id",
+ .field_bit_size = 24,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}
},
.field_info_spec = {
- .description = "tl4_hdr_error",
- .field_bit_size = 1,
+ .description = "tun_id",
+ .field_bit_size = 24,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl4_hdr_valid",
- .field_bit_size = 1,
+ .description = "tun_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4_hdr_valid",
- .field_bit_size = 1,
+ .description = "tun_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3_ipv6_cmp_dst",
- .field_bit_size = 1,
+ .description = "tun_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3_ipv6_cmp_dst",
- .field_bit_size = 1,
+ .description = "tun_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3_ipv6_cmp_src",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "tl3_ipv6_cmp_src",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl3_hdr_isIP",
- .field_bit_size = 1,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3_hdr_isIP",
- .field_bit_size = 1,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
}
},
+ /* class_tid: 2, , table: eem.tun */
{
.field_info_mask = {
- .description = "tl3_hdr_type",
- .field_bit_size = 4,
+ .description = "spare",
+ .field_bit_size = 339,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3_hdr_type",
- .field_bit_size = 4,
+ .description = "spare",
+ .field_bit_size = 339,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3_hdr_error",
- .field_bit_size = 1,
+ .description = "l2.ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3_hdr_error",
- .field_bit_size = 1,
+ .description = "l2.ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3_hdr_valid",
- .field_bit_size = 1,
+ .description = "l2.dmac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "tl3_hdr_valid",
- .field_bit_size = 1,
+ .description = "l2.dmac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl2_two_vtags",
- .field_bit_size = 1,
+ .description = "tun_id",
+ .field_bit_size = 24,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}
},
.field_info_spec = {
- .description = "tl2_two_vtags",
- .field_bit_size = 1,
+ .description = "tun_id",
+ .field_bit_size = 24,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl2_vtag_present",
- .field_bit_size = 1,
+ .description = "tun_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_vtag_present",
- .field_bit_size = 1,
+ .description = "tun_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_uc_mc_bc",
- .field_bit_size = 2,
+ .description = "tun_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_uc_mc_bc",
- .field_bit_size = 2,
+ .description = "tun_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_hdr_type",
- .field_bit_size = 2,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_hdr_type",
- .field_bit_size = 2,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl2_hdr_valid",
- .field_bit_size = 1,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "tl2_hdr_valid",
- .field_bit_size = 1,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
}
},
+ /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
{
.field_info_mask = {
- .description = "hrec_next",
- .field_bit_size = 1,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
},
.field_info_spec = {
- .description = "hrec_next",
- .field_bit_size = 1,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
}
},
+ /* class_tid: 3, , table: mac_addr_cache.rd */
{
.field_info_mask = {
- .description = "reserved",
- .field_bit_size = 9,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
},
.field_info_spec = {
- .description = "reserved",
- .field_bit_size = 9,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
}
},
{
.field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "tun_hdr",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 0xff}
+ ULP_WP_SYM_TUN_HDR_TYPE_NONE}
},
.field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ ULP_WP_SYM_TUN_HDR_TYPE_NONE}
}
},
{
.field_info_mask = {
- .description = "agg_error",
+ .description = "one_tag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "agg_error",
+ .description = "one_tag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
}
},
{
.field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "pkt_type_0",
- .field_bit_size = 2,
+ .description = "mac_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
},
.field_info_spec = {
- .description = "pkt_type_0",
- .field_bit_size = 2,
+ .description = "mac_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
}
},
+ /* class_tid: 3, , table: l2_cntxt_tcam.0 */
{
.field_info_mask = {
- .description = "pkt_type_1",
- .field_bit_size = 2,
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "pkt_type_1",
- .field_bit_size = 2,
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
+ .description = "mac0_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
},
.field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
+ .description = "mac0_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
}
},
- /* class_tid: 2, , table: profile_tcam_cache.wr */
{
.field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 0xff}
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
},
.field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
}
},
{
.field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "sparif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 2, , table: em.ipv4 */
{
.field_info_mask = {
- .description = "spare",
- .field_bit_size = 3,
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "spare",
- .field_bit_size = 3,
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "mac1_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "mac1_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4.dst",
- .field_bit_size = 16,
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff}
}
},
{
.field_info_mask = {
- .description = "l4.src",
- .field_bit_size = 16,
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3.prot",
- .field_bit_size = 8,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 0xff}
+ ULP_WP_SYM_TUN_HDR_TYPE_NONE}
},
.field_info_spec = {
- .description = "l3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ ULP_WP_SYM_TUN_HDR_TYPE_NONE}
}
},
{
.field_info_mask = {
- .description = "l3.dst",
- .field_bit_size = 32,
+ .description = "key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3.dst",
- .field_bit_size = 32,
+ .description = "key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3.src",
- .field_bit_size = 32,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ 1}
},
.field_info_spec = {
- .description = "l3.src",
- .field_bit_size = 32,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ 1}
}
},
+ /* class_tid: 3, , table: mac_addr_cache.wr */
{
.field_info_mask = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
},
.field_info_spec = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
}
},
{
.field_info_mask = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "tun_hdr",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 0xff,
- 0xff}
+ ULP_WP_SYM_TUN_HDR_TYPE_NONE}
},
.field_info_spec = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "tun_hdr",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ ULP_WP_SYM_TUN_HDR_TYPE_NONE}
}
},
{
.field_info_mask = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "one_tag",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "one_tag",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
}
},
- /* class_tid: 2, , table: eem.ipv4 */
{
.field_info_mask = {
- .description = "spare",
- .field_bit_size = 275,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "spare",
- .field_bit_size = 275,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "mac_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
},
.field_info_spec = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "mac_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
}
},
+ /* class_tid: 3, , table: profile_tcam_cache.rd */
{
.field_info_mask = {
- .description = "l4.dst",
- .field_bit_size = 16,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4.src",
- .field_bit_size = 16,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l4.src",
- .field_bit_size = 16,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "l3.prot",
- .field_bit_size = 8,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
}
},
+ /* class_tid: 3, , table: profile_tcam.ipv4 */
{
.field_info_mask = {
- .description = "l3.dst",
- .field_bit_size = 32,
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3.dst",
- .field_bit_size = 32,
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3.src",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3.src",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_WP_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_WP_SYM_L4_HDR_TYPE_UDP}
}
},
{
.field_info_mask = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
},
.field_info_spec = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 0xff,
- 0xff}
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
},
.field_info_spec = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
}
},
{
.field_info_mask = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 2, , table: em.ipv6 */
{
.field_info_mask = {
- .description = "spare",
- .field_bit_size = 3,
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "spare",
- .field_bit_size = 3,
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4.dst",
- .field_bit_size = 16,
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4.src",
- .field_bit_size = 16,
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3.prot",
- .field_bit_size = 8,
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ ULP_WP_SYM_L3_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "l3.dst",
- .field_bit_size = 128,
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ 0xff}
},
.field_info_spec = {
- .description = "l3.dst",
- .field_bit_size = 128,
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3.src",
- .field_bit_size = 128,
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ 0xff}
},
.field_info_spec = {
- .description = "l3.src",
- .field_bit_size = 128,
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
}
},
{
.field_info_mask = {
- .description = "l2.smac",
- .field_bit_size = 48,
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "l2.smac",
- .field_bit_size = 48,
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ 0xff}
},
.field_info_spec = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ ULP_WP_SYM_L2_HDR_VALID_YES}
}
},
- /* class_tid: 2, , table: eem.ipv6 */
{
.field_info_mask = {
- .description = "spare",
- .field_bit_size = 35,
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "spare",
- .field_bit_size = 35,
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4.dst",
- .field_bit_size = 16,
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l4.src",
- .field_bit_size = 16,
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3.prot",
- .field_bit_size = 8,
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l3.dst",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
- },
- .field_info_spec = {
- .description = "l3.dst",
- .field_bit_size = 128,
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3.src",
- .field_bit_size = 128,
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3.src",
- .field_bit_size = 128,
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2.smac",
- .field_bit_size = 48,
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2.smac",
- .field_bit_size = 48,
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l2_num_vtags",
+ .description = "tl2_hdr_type",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_num_vtags",
+ .description = "tl2_hdr_type",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -8648,491 +8813,511 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "hrec_next",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "hrec_next",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "reserved",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "reserved",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- .field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- }
- },
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */
- {
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd_vfr */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "agg_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "agg_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_bypass.egr_vfr */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 0xff}
+ 1}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ 1}
}
},
+ /* class_tid: 3, , table: profile_tcam.ipv6 */
{
.field_info_mask = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_WP_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_WP_SYM_L4_HDR_TYPE_UDP}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
},
.field_info_spec = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
},
.field_info_spec = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
}
},
{
.field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
+ .description = "l3_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tun_hdr_type",
+ .description = "l3_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_L3_HDR_TYPE_IPV6}
}
},
{
.field_info_mask = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "valid",
+ .description = "l3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 1}
+ 0xff}
},
.field_info_spec = {
- .description = "valid",
+ .description = "l3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ ULP_WP_SYM_L3_HDR_VALID_YES}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
- }
- },
- {
- .field_info_mask = {
- .description = "sparif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "sparif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ ULP_WP_SYM_L2_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
+ .description = "tl4_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_type",
+ .description = "tl4_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -9140,203 +9325,171 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "valid",
+ .description = "tl4_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 1}
+ 0xff}
},
.field_info_spec = {
- .description = "valid",
+ .description = "tl4_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_rd_egr */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "sparif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_num_vtags",
+ .description = "tl2_hdr_type",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_num_vtags",
+ .description = "tl2_hdr_type",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -9344,280 +9497,294 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "hrec_next",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "hrec_next",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "reserved",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "reserved",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 1}
+ 0xff}
},
.field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_egr_wr */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "agg_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "agg_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vf_ing */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 0xff}
+ 1}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ 1}
}
},
+ /* class_tid: 3, , table: profile_tcam_cache.wr */
{
.field_info_mask = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
}
},
+ /* class_tid: 3, , table: em.ipv4 */
{
.field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "spare",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "spare",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "local_cos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "local_cos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "l4.dst",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "l4.src",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "key_type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "key_type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- .field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_rd_egr0 */
{
.field_info_mask = {
- .description = "svif",
+ .description = "l3.prot",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
@@ -9625,211 +9792,305 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "svif",
+ .description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_egr0 */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l3.dst",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l3.dst",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l3.src",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l3.src",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
+ .description = "l2.dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "mac0_addr",
+ .description = "l2.dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
+ 0xff,
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
}
},
{
.field_info_mask = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
}
},
+ /* class_tid: 3, , table: eem.ipv4 */
{
.field_info_mask = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "spare",
+ .field_bit_size = 275,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "spare",
+ .field_bit_size = 275,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "local_cos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "local_cos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "l4.dst",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "l4.src",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "l3.prot",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "l3.dst",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
},
.field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "l3.dst",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
}
},
{
.field_info_mask = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "l3.src",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
},
.field_info_spec = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "l3.src",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
}
},
{
.field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
+ .description = "l2.dmac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
+ .description = "l2.dmac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
{
.field_info_mask = {
- .description = "svif",
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "em_profile_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
@@ -9837,34 +10098,48 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "svif",
+ .description = "em_profile_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */
+ /* class_tid: 3, , table: em.ipv6 */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "spare",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "spare",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "local_cos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "local_cos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
@@ -9872,32 +10147,48 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "l4.src",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "svif",
+ .description = "l3.prot",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
@@ -9905,154 +10196,314 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "svif",
+ .description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "l3.dst",
+ .field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
},
.field_info_spec = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "l3.dst",
+ .field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l3.src",
+ .field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
},
.field_info_spec = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l3.src",
+ .field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l2.smac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l2.smac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac1_addr",
+ .description = "l2.dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "mac1_addr",
+ .description = "l2.dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
{
.field_info_mask = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
+ 0xff,
0xff}
},
.field_info_spec = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- 2}
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
}
},
+ /* class_tid: 3, , table: eem.ipv6 */
{
.field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "spare",
+ .field_bit_size = 35,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "spare",
+ .field_bit_size = 35,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "local_cos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "local_cos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
+ .description = "l4.dst",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 1}
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 1}
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dst",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3.dst",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.src",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3.src",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2.smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2.smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2.dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2.dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
@@ -10060,13 +10511,67 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -10112,8 +10617,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
}
},
{
@@ -10177,17 +10682,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "l2_num_vtags",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l2_num_vtags",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -10249,529 +10750,2581 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.field_opr1 = {
1}
}
- }
-};
-
-struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
- /* class_tid: 1, , table: l2_cntxt_tcam.0 */
- {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
{
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ }
},
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd_vfr */
{
- .description = "l2_byp_lkup_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_bypass.egr_vfr */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vf_ing */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_rd_egr0 */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_egr0 */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 2}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ }
+};
+
+struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
+ /* class_tid: 1, , table: l2_cntxt_tcam.0 */
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}
+ },
+ {
+ .description = "l2_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ },
+ {
+ .description = "allowed_pri",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "default_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "allowed_tpid",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "default_tpid",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "bd_act_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "byp_sp_lkup",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "pri_anti_spoof_ctl",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tpid_anti_spoof_ctl",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: mac_addr_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.ipv4 */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.0",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_mask.1",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ },
+ {
+ .description = "em_key_mask.2",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ },
+ {
+ .description = "em_key_mask.3",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ },
+ {
+ .description = "em_key_mask.4",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}
+ },
+ {
+ .description = "em_key_mask.5",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}
+ },
+ {
+ .description = "em_key_mask.6",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}
+ },
+ {
+ .description = "em_key_mask.7",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.8",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.9",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.ipv6 */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.0",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_mask.1",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.2",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ },
+ {
+ .description = "em_key_mask.3",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
},
{
- .description = "parif",
+ .description = "em_key_mask.4",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ },
+ {
+ .description = "em_key_mask.5",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}
+ },
+ {
+ .description = "em_key_mask.6",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}
+ },
+ {
+ .description = "em_key_mask.7",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}
+ },
+ {
+ .description = "em_key_mask.8",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.9",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 7}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.ipv4_vxlan */
+ {
+ .description = "wc_key_id",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.0",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_mask.1",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.2",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.3",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.4",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_mask.5",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_mask.6",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_mask.7",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.8",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.9",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 20}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
+ /* class_tid: 1, , table: em.ipv4 */
{
- .description = "allowed_pri",
- .field_bit_size = 8,
+ .description = "act_rec_ptr",
+ .field_bit_size = 33,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "default_pri",
- .field_bit_size = 3,
+ .description = "ext_flow_cntr",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "allowed_tpid",
- .field_bit_size = 6,
+ .description = "act_rec_int",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "default_tpid",
- .field_bit_size = 3,
+ .description = "act_rec_size",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "bd_act_en",
- .field_bit_size = 1,
+ .description = "key_size",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
+ .description = "reserved",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "byp_sp_lkup",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ 3}
},
{
- .description = "pri_anti_spoof_ctl",
- .field_bit_size = 2,
+ .description = "l1_cacheable",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tpid_anti_spoof_ctl",
- .field_bit_size = 2,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
- /* class_tid: 1, , table: mac_addr_cache.wr */
+ /* class_tid: 1, , table: eem.ipv4 */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "act_rec_ptr",
+ .field_bit_size = 33,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "l2_cntxt_tcam_index",
- .field_bit_size = 10,
+ .description = "ext_flow_cntr",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "act_rec_int",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "act_rec_size",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "key_size",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ (173 >> 8) & 0xff,
+ 173 & 0xff}
},
- /* class_tid: 1, , table: profile_tcam.ipv4 */
{
- .description = "wc_key_id",
- .field_bit_size = 4,
+ .description = "reserved",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
},
{
- .description = "wc_search_en",
+ .description = "l1_cacheable",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.0",
+ .description = "valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 1, , table: em.ipv6 */
{
- .description = "em_key_mask.1",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 33,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "em_key_mask.2",
+ .description = "ext_flow_cntr",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.3",
+ .description = "act_rec_int",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.4",
- .field_bit_size = 1,
+ .description = "act_rec_size",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "key_size",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}
+ 3}
},
{
- .description = "em_key_mask.5",
+ .description = "l1_cacheable",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.6",
+ .description = "valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}
+ 1}
},
+ /* class_tid: 1, , table: eem.ipv6 */
{
- .description = "em_key_mask.7",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 33,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "em_key_mask.8",
+ .description = "ext_flow_cntr",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.9",
+ .description = "act_rec_int",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
+ .description = "act_rec_size",
.field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- 3}
+ (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "key_size",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ (413 >> 8) & 0xff,
+ 413 & 0xff}
},
{
- .description = "em_search_en",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ 3}
},
{
- .description = "pl_byp_lkup_en",
+ .description = "l1_cacheable",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam.ipv6 */
{
- .description = "wc_key_id",
- .field_bit_size = 4,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 1, , table: em.vxlan */
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "act_rec_ptr",
+ .field_bit_size = 33,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "wc_search_en",
+ .description = "ext_flow_cntr",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.0",
+ .description = "act_rec_int",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.1",
- .field_bit_size = 1,
+ .description = "act_rec_size",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.2",
- .field_bit_size = 1,
+ .description = "key_size",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.3",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.4",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ 3}
},
{
- .description = "em_key_mask.5",
+ .description = "l1_cacheable",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.6",
+ .description = "valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}
+ 1}
},
+ /* class_tid: 1, , table: eem.vxlan */
{
- .description = "em_key_mask.7",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .description = "act_rec_ptr",
+ .field_bit_size = 33,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "em_key_mask.8",
+ .description = "ext_flow_cntr",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.9",
+ .description = "act_rec_int",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
+ .description = "act_rec_size",
.field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 7}
- },
- {
- .description = "em_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}
},
{
- .description = "em_search_en",
- .field_bit_size = 1,
+ .description = "key_size",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
- },
- {
- .description = "pl_byp_lkup_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (197 >> 8) & 0xff,
+ 197 & 0xff}
},
- /* class_tid: 1, , table: profile_tcam.ipv4_vxlan */
{
- .description = "wc_key_id",
- .field_bit_size = 4,
+ .description = "reserved",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
},
{
- .description = "wc_search_en",
+ .description = "l1_cacheable",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.0",
+ .description = "valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
{
- .description = "em_key_mask.1",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.2",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.3",
+ .description = "l2_byp_lkup_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.4",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.5",
- .field_bit_size = 1,
+ .description = "allowed_pri",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.6",
- .field_bit_size = 1,
+ .description = "default_pri",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.7",
- .field_bit_size = 1,
+ .description = "allowed_tpid",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.8",
- .field_bit_size = 1,
+ .description = "default_tpid",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.9",
+ .description = "bd_act_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 20}
- },
- {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_search_en",
+ .description = "byp_sp_lkup",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -10779,12 +13332,18 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
1}
},
{
- .description = "pl_byp_lkup_en",
- .field_bit_size = 1,
+ .description = "pri_anti_spoof_ctl",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam_cache.wr */
+ {
+ .description = "tpid_anti_spoof_ctl",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 2, , table: tunnel_cache.wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -10795,299 +13354,303 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "profile_tcam_index",
+ .description = "l2_cntxt_tcam_index",
.field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
- },
- {
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
+ /* class_tid: 2, , table: l2_cntxt_tcam.0 */
{
- .description = "flow_sig_id",
- .field_bit_size = 64,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
- /* class_tid: 1, , table: em.ipv4 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 33,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
},
{
- .description = "ext_flow_cntr",
+ .description = "l2_byp_lkup_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "act_rec_int",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ },
+ {
+ .description = "allowed_pri",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "act_rec_size",
- .field_bit_size = 5,
+ .description = "default_pri",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "key_size",
- .field_bit_size = 9,
+ .description = "allowed_tpid",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "reserved",
- .field_bit_size = 11,
+ .description = "default_tpid",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "bd_act_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 3}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l1_cacheable",
- .field_bit_size = 1,
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "valid",
+ .description = "byp_sp_lkup",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
- /* class_tid: 1, , table: eem.ipv4 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 33,
+ .description = "pri_anti_spoof_ctl",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ext_flow_cntr",
- .field_bit_size = 1,
+ .description = "tpid_anti_spoof_ctl",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 2, , table: mac_addr_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
{
- .description = "act_rec_int",
- .field_bit_size = 1,
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "act_rec_size",
- .field_bit_size = 5,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,
- BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .description = "key_size",
- .field_bit_size = 9,
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- (173 >> 8) & 0xff,
- 173 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 2, , table: profile_tcam.f2 */
{
- .description = "reserved",
- .field_bit_size = 11,
+ .description = "wc_key_id",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 3}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l1_cacheable",
+ .description = "wc_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "valid",
+ .description = "em_key_mask.0",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
- /* class_tid: 1, , table: em.ipv6 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 33,
+ .description = "em_key_mask.1",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ 1}
},
{
- .description = "ext_flow_cntr",
+ .description = "em_key_mask.2",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "act_rec_int",
+ .description = "em_key_mask.3",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "act_rec_size",
- .field_bit_size = 5,
+ .description = "em_key_mask.4",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "key_size",
- .field_bit_size = 9,
+ .description = "em_key_mask.5",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "reserved",
- .field_bit_size = 11,
+ .description = "em_key_mask.6",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "em_key_mask.7",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 3}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l1_cacheable",
+ .description = "em_key_mask.8",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "valid",
+ .description = "em_key_mask.9",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ 8}
},
- /* class_tid: 1, , table: eem.ipv6 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 33,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
},
{
- .description = "ext_flow_cntr",
+ .description = "em_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "act_rec_int",
+ .description = "pl_byp_lkup_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
{
- .description = "act_rec_size",
- .field_bit_size = 5,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,
- BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "key_size",
- .field_bit_size = 9,
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (413 >> 8) & 0xff,
- 413 & 0xff}
- },
- {
- .description = "reserved",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- 3}
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
},
{
- .description = "l1_cacheable",
- .field_bit_size = 1,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "valid",
- .field_bit_size = 1,
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
- /* class_tid: 1, , table: em.vxlan */
+ /* class_tid: 2, , table: em.tun */
{
.description = "act_rec_ptr",
.field_bit_size = 33,
@@ -11149,7 +13712,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 1, , table: eem.vxlan */
+ /* class_tid: 2, , table: eem.tun */
{
.description = "act_rec_ptr",
.field_bit_size = 33,
@@ -11186,8 +13749,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (197 >> 8) & 0xff,
- 197 & 0xff}
+ (109 >> 8) & 0xff,
+ 109 & 0xff}
},
{
.description = "reserved",
@@ -11217,7 +13780,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 2, , table: l2_cntxt_tcam.0 */
+ /* class_tid: 3, , table: l2_cntxt_tcam.0 */
{
.description = "l2_cntxt_id",
.field_bit_size = 10,
@@ -11317,7 +13880,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: mac_addr_cache.wr */
+ /* class_tid: 3, , table: mac_addr_cache.wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -11351,7 +13914,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: profile_tcam.ipv4 */
+ /* class_tid: 3, , table: profile_tcam.ipv4 */
{
.description = "wc_key_id",
.field_bit_size = 4,
@@ -11497,7 +14060,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: profile_tcam.ipv6 */
+ /* class_tid: 3, , table: profile_tcam.ipv6 */
{
.description = "wc_key_id",
.field_bit_size = 4,
@@ -11643,7 +14206,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: profile_tcam_cache.wr */
+ /* class_tid: 3, , table: profile_tcam_cache.wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -11686,7 +14249,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
- /* class_tid: 2, , table: em.ipv4 */
+ /* class_tid: 3, , table: em.ipv4 */
{
.description = "act_rec_ptr",
.field_bit_size = 33,
@@ -11748,7 +14311,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 2, , table: eem.ipv4 */
+ /* class_tid: 3, , table: eem.ipv4 */
{
.description = "act_rec_ptr",
.field_bit_size = 33,
@@ -11816,7 +14379,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 2, , table: em.ipv6 */
+ /* class_tid: 3, , table: em.ipv6 */
{
.description = "act_rec_ptr",
.field_bit_size = 33,
@@ -11878,7 +14441,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 2, , table: eem.ipv6 */
+ /* class_tid: 3, , table: eem.ipv6 */
{
.description = "act_rec_ptr",
.field_bit_size = 33,
@@ -11946,7 +14509,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 3, , table: int_full_act_record.ing_0 */
+ /* class_tid: 4, , table: int_full_act_record.ing_0 */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -12106,7 +14669,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
.description = "l2_cntxt_id",
.field_bit_size = 10,
@@ -12196,7 +14759,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -12230,7 +14793,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: parif_def_lkup_arec_ptr.ing_0 */
+ /* class_tid: 4, , table: parif_def_lkup_arec_ptr.ing_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -12240,7 +14803,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */
+ /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -12250,7 +14813,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */
+ /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -12260,7 +14823,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 3, , table: int_full_act_record.egr_vfr */
+ /* class_tid: 4, , table: int_full_act_record.egr_vfr */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -12420,7 +14983,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: l2_cntxt_tcam_bypass.egr_vfr */
+ /* class_tid: 4, , table: l2_cntxt_tcam_bypass.egr_vfr */
{
.description = "act_record_ptr",
.field_bit_size = 16,
@@ -12508,7 +15071,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
{
.description = "rid",
.field_bit_size = 32,
@@ -12539,7 +15102,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
.description = "l2_cntxt_id",
.field_bit_size = 10,
@@ -12629,7 +15192,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -12663,7 +15226,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: int_full_act_record.egr_0 */
+ /* class_tid: 4, , table: int_full_act_record.egr_0 */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -12823,7 +15386,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: parif_def_lkup_arec_ptr.egr_0 */
+ /* class_tid: 4, , table: parif_def_lkup_arec_ptr.egr_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -12833,7 +15396,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */
+ /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -12843,7 +15406,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */
+ /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -12853,7 +15416,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 4, , table: int_full_act_record.loopback */
+ /* class_tid: 5, , table: int_full_act_record.loopback */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -13013,7 +15576,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
{
.description = "l2_cntxt_id",
.field_bit_size = 10,
@@ -13102,7 +15665,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -13136,7 +15699,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: parif_def_lkup_arec_ptr.vf_egr */
+ /* class_tid: 5, , table: parif_def_lkup_arec_ptr.vf_egr */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -13146,7 +15709,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
- /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */
+ /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -13156,7 +15719,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
- /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */
+ /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -13166,7 +15729,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
- /* class_tid: 4, , table: int_full_act_record.vf_ing */
+ /* class_tid: 5, , table: int_full_act_record.vf_ing */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -13326,7 +15889,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vf_ing */
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vf_ing */
{
.description = "act_record_ptr",
.field_bit_size = 16,
@@ -13412,7 +15975,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_egr0 */
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_egr0 */
{
.description = "act_record_ptr",
.field_bit_size = 16,
@@ -13497,7 +16060,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
{
.description = "rid",
.field_bit_size = 32,
@@ -13528,7 +16091,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: int_vtag_encap_record.vfr_egr0 */
+ /* class_tid: 5, , table: int_vtag_encap_record.vfr_egr0 */
{
.description = "ecv_tun_type",
.field_bit_size = 3,
@@ -13611,7 +16174,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: int_full_act_record.vfr_egr0 */
+ /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -13774,7 +16337,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: int_full_act_record.vfr_ing0 */
+ /* class_tid: 5, , table: int_full_act_record.vfr_ing0 */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -13936,7 +16499,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */
{
.description = "act_record_ptr",
.field_bit_size = 16,
@@ -14022,7 +16585,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */
{
.description = "act_record_ptr",
.field_bit_size = 16,
@@ -14180,13 +16743,22 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 8,
.ident_bit_pos = 28
},
- /* class_tid: 2, , table: l2_cntxt_tcam_cache.rd */
+ /* class_tid: 2, , table: tunnel_cache.rd */
{
.description = "l2_cntxt_id",
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 42
},
+ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
+ {
+ .description = "l2_cntxt_id",
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 0
+ },
/* class_tid: 2, , table: mac_addr_cache.rd */
{
.description = "l2_cntxt_id",
@@ -14194,7 +16766,40 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 42
},
- /* class_tid: 2, , table: l2_cntxt_tcam.0 */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
+ {
+ .description = "em_profile_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 42
+ },
+ {
+ .description = "flow_sig_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .ident_bit_size = 64,
+ .ident_bit_pos = 58
+ },
+ {
+ .description = "profile_tcam_index",
+ .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ {
+ .description = "l2_cntxt_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 42
+ },
+ /* class_tid: 3, , table: mac_addr_cache.rd */
+ {
+ .description = "l2_cntxt_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 42
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam.0 */
{
.description = "l2_cntxt_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -14203,7 +16808,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 0
},
- /* class_tid: 2, , table: profile_tcam_cache.rd */
+ /* class_tid: 3, , table: profile_tcam_cache.rd */
{
.description = "em_profile_id",
.regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
@@ -14222,7 +16827,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 32
},
- /* class_tid: 2, , table: profile_tcam.ipv4 */
+ /* class_tid: 3, , table: profile_tcam.ipv4 */
{
.description = "em_profile_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -14231,7 +16836,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 8,
.ident_bit_pos = 28
},
- /* class_tid: 2, , table: profile_tcam.ipv6 */
+ /* class_tid: 3, , table: profile_tcam.ipv6 */
{
.description = "em_profile_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -14240,7 +16845,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 8,
.ident_bit_pos = 28
},
- /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
.description = "l2_cntxt_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -14249,7 +16854,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 0
},
- /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
.description = "l2_cntxt_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -14258,7 +16863,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 0
},
- /* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
{
.description = "l2_cntxt_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
index 22c51976ac..73c31b98d9 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
@@ -413,11 +413,13 @@ static int ulp_get_single_flow_stat(struct bnxt_ulp_context *ctxt,
}
/* Update the parent counters if it is child flow */
- if (sw_acc_tbl_entry->parent_flow_id) {
+ if (sw_acc_tbl_entry->pc_flow_idx & FLOW_CNTR_PC_FLOW_VALID) {
+ uint32_t pc_idx;
+
/* Update the parent counters */
t_sw = sw_acc_tbl_entry;
- if (ulp_flow_db_parent_flow_count_update(ctxt,
- t_sw->parent_flow_id,
+ pc_idx = t_sw->pc_flow_idx & ~FLOW_CNTR_PC_FLOW_VALID;
+ if (ulp_flow_db_parent_flow_count_update(ctxt, pc_idx,
t_sw->pkt_count,
t_sw->byte_count)) {
PMD_DRV_LOG(ERR, "Error updating parent counters\n");
@@ -658,6 +660,7 @@ int32_t ulp_fc_mgr_cntr_reset(struct bnxt_ulp_context *ctxt, enum tf_dir dir,
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].hw_cntr_id = 0;
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].pkt_count = 0;
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].byte_count = 0;
+ ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].pc_flow_idx = 0;
ulp_fc_info->num_entries--;
pthread_mutex_unlock(&ulp_fc_info->fc_lock);
@@ -688,6 +691,8 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
uint32_t hw_cntr_id = 0, sw_cntr_idx = 0;
struct sw_acc_counter *sw_acc_tbl_entry;
bool found_cntr_resource = false;
+ bool found_parent_flow = false;
+ uint32_t pc_idx;
ulp_fc_info = bnxt_ulp_cntxt_ptr2_fc_info_get(ctxt);
if (!ulp_fc_info)
@@ -707,12 +712,16 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
(params.resource_sub_type ==
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT ||
params.resource_sub_type ==
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_EXT_COUNT ||
- params.resource_sub_type ==
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC)) {
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_EXT_COUNT)) {
found_cntr_resource = true;
break;
}
+ if (params.resource_func ==
+ BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW) {
+ found_parent_flow = true;
+ pc_idx = params.resource_hndl;
+ }
+
} while (!rc && nxt_resource_index);
bnxt_ulp_cntxt_release_fdb_lock(ctxt);
@@ -722,7 +731,8 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
dir = params.direction;
hw_cntr_id = params.resource_hndl;
- if (params.resource_sub_type ==
+ if (!found_parent_flow &&
+ params.resource_sub_type ==
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT) {
if (!ulp_fc_info->num_counters)
return ulp_fc_tf_flow_stat_get(ctxt, ¶ms, count);
@@ -745,14 +755,17 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
sw_acc_tbl_entry->byte_count = 0;
}
pthread_mutex_unlock(&ulp_fc_info->fc_lock);
- } else if (params.resource_sub_type ==
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC) {
+ } else if (found_parent_flow &&
+ params.resource_sub_type ==
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT) {
/* Get stats from the parent child table */
- ulp_flow_db_parent_flow_count_get(ctxt, flow_id,
+ ulp_flow_db_parent_flow_count_get(ctxt, pc_idx,
&count->hits, &count->bytes,
count->reset);
- count->hits_set = 1;
- count->bytes_set = 1;
+ if (count->hits)
+ count->hits_set = 1;
+ if (count->bytes)
+ count->bytes_set = 1;
} else {
/* TBD: Handle External counters */
rc = -EINVAL;
@@ -770,13 +783,13 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
*
* hw_cntr_id [in] The HW flow counter ID
*
- * fid [in] parent flow id
+ * pc_idx [in] parent child db index
*
*/
int32_t ulp_fc_mgr_cntr_parent_flow_set(struct bnxt_ulp_context *ctxt,
enum tf_dir dir,
uint32_t hw_cntr_id,
- uint32_t fid)
+ uint32_t pc_idx)
{
struct bnxt_ulp_fc_info *ulp_fc_info;
uint32_t sw_cntr_idx;
@@ -789,10 +802,11 @@ int32_t ulp_fc_mgr_cntr_parent_flow_set(struct bnxt_ulp_context *ctxt,
pthread_mutex_lock(&ulp_fc_info->fc_lock);
sw_cntr_idx = hw_cntr_id - ulp_fc_info->shadow_hw_tbl[dir].start_idx;
if (ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].valid) {
- ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].parent_flow_id = fid;
+ pc_idx |= FLOW_CNTR_PC_FLOW_VALID;
+ ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].pc_flow_idx = pc_idx;
} else {
BNXT_TF_DBG(ERR, "Failed to set parent flow id %x:%x\n",
- hw_cntr_id, fid);
+ hw_cntr_id, pc_idx);
rc = -ENOENT;
}
pthread_mutex_unlock(&ulp_fc_info->fc_lock);
diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
index 448d05c118..9825ed2a27 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
@@ -21,12 +21,14 @@
#define FLOW_CNTR_BYTES(v, d) (((v) & (d)->byte_count_mask) >> \
(d)->byte_count_shift)
+#define FLOW_CNTR_PC_FLOW_VALID 0x1000000
+
struct sw_acc_counter {
uint64_t pkt_count;
uint64_t byte_count;
bool valid;
uint32_t hw_cntr_id;
- uint32_t parent_flow_id;
+ uint32_t pc_flow_idx;
};
struct hw_fc_mem_info {
@@ -175,12 +177,12 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ulp_ctx,
*
* hw_cntr_id [in] The HW flow counter ID
*
- * fid [in] parent flow id
+ * pc_idx [in] parent child db index
*
*/
int32_t ulp_fc_mgr_cntr_parent_flow_set(struct bnxt_ulp_context *ctxt,
enum tf_dir dir,
uint32_t hw_cntr_id,
- uint32_t fid);
+ uint32_t pc_idx);
#endif /* _ULP_FC_MGR_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
index 747a360aa0..039c9c2a6b 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
@@ -386,101 +386,6 @@ ulp_flow_db_parent_tbl_deinit(struct bnxt_ulp_flow_db *flow_db)
}
}
-/* internal validation function for parent flow tbl */
-static struct bnxt_ulp_flow_db *
-ulp_flow_db_parent_arg_validation(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t fid)
-{
- struct bnxt_ulp_flow_db *flow_db;
-
- flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
- if (!flow_db) {
- BNXT_TF_DBG(ERR, "Invalid Arguments\n");
- return NULL;
- }
-
- /* check for max flows */
- if (fid >= flow_db->flow_tbl.num_flows || !fid) {
- BNXT_TF_DBG(ERR, "Invalid flow index\n");
- return NULL;
- }
-
- /* No support for parent child db then just exit */
- if (!flow_db->parent_child_db.entries_count) {
- BNXT_TF_DBG(ERR, "parent child db not supported\n");
- return NULL;
- }
-
- return flow_db;
-}
-
-/*
- * Set the tunnel index in the parent flow
- *
- * ulp_ctxt [in] Ptr to ulp_context
- * parent_idx [in] The parent index of the parent flow entry
- *
- * returns index on success and negative on failure.
- */
-static int32_t
-ulp_flow_db_parent_tun_idx_set(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_idx, uint8_t tun_idx)
-{
- struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
-
- flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
- if (!flow_db) {
- BNXT_TF_DBG(ERR, "Invalid Arguments\n");
- return -EINVAL;
- }
-
- /* check for parent idx validity */
- p_pdb = &flow_db->parent_child_db;
- if (parent_idx >= p_pdb->entries_count ||
- !p_pdb->parent_flow_tbl[parent_idx].parent_fid) {
- BNXT_TF_DBG(ERR, "Invalid parent flow index %x\n", parent_idx);
- return -EINVAL;
- }
-
- p_pdb->parent_flow_tbl[parent_idx].tun_idx = tun_idx;
- return 0;
-}
-
-/*
- * Get the tunnel index from the parent flow
- *
- * ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
- *
- * returns 0 if counter accum is set else -1.
- */
-static int32_t
-ulp_flow_db_parent_tun_idx_get(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid, uint8_t *tun_idx)
-{
- struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
- uint32_t idx;
-
- /* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
- if (!flow_db) {
- BNXT_TF_DBG(ERR, "parent child db validation failed\n");
- return -EINVAL;
- }
-
- p_pdb = &flow_db->parent_child_db;
- for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
- *tun_idx = p_pdb->parent_flow_tbl[idx].tun_idx;
- return 0;
- }
- }
-
- return -EINVAL;
-}
-
/*
* Initialize the flow database. Memory is allocated in this
* call and assigned to the flow database.
@@ -783,9 +688,6 @@ ulp_flow_db_resource_del(struct bnxt_ulp_context *ulp_ctxt,
struct bnxt_ulp_flow_tbl *flow_tbl;
struct ulp_fdb_resource_info *nxt_resource, *fid_resource;
uint32_t nxt_idx = 0;
- struct bnxt_tun_cache_entry *tun_tbl;
- uint8_t tun_idx = 0;
- int rc;
flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
if (!flow_db) {
@@ -862,18 +764,6 @@ ulp_flow_db_resource_del(struct bnxt_ulp_context *ulp_ctxt,
params->resource_hndl);
}
- if (params->resource_func == BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW) {
- tun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(ulp_ctxt);
- if (!tun_tbl)
- return -EINVAL;
-
- rc = ulp_flow_db_parent_tun_idx_get(ulp_ctxt, fid, &tun_idx);
- if (rc)
- return rc;
-
- ulp_clear_tun_entry(tun_tbl, tun_idx);
- }
-
/* all good, return success */
return 0;
}
@@ -892,7 +782,6 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt,
enum bnxt_ulp_fdb_type flow_type,
uint32_t fid)
{
- struct bnxt_tun_cache_entry *tun_tbl;
struct bnxt_ulp_flow_tbl *flow_tbl;
struct bnxt_ulp_flow_db *flow_db;
@@ -934,12 +823,6 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt,
if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR)
ulp_flow_db_func_id_set(flow_db, fid, 0);
- tun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(ulp_ctxt);
- if (!tun_tbl)
- return -EINVAL;
-
- ulp_clear_tun_inner_entry(tun_tbl, fid);
-
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
BNXT_TF_DBG(ERR, "flow_id = %u:%u freed\n", flow_type, fid);
#endif
@@ -1307,24 +1190,84 @@ ulp_default_flow_db_cfa_action_get(struct bnxt_ulp_context *ulp_ctx,
return 0;
}
+/* internal validation function for parent flow tbl */
+static struct ulp_fdb_parent_info *
+ulp_flow_db_pc_db_entry_get(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t pc_idx)
+{
+ struct bnxt_ulp_flow_db *flow_db;
+
+ flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
+ if (!flow_db) {
+ BNXT_TF_DBG(ERR, "Invalid Arguments\n");
+ return NULL;
+ }
+
+ /* check for max flows */
+ if (pc_idx >= BNXT_ULP_MAX_TUN_CACHE_ENTRIES) {
+ BNXT_TF_DBG(ERR, "Invalid tunnel index\n");
+ return NULL;
+ }
+
+ /* No support for parent child db then just exit */
+ if (!flow_db->parent_child_db.entries_count) {
+ BNXT_TF_DBG(ERR, "parent child db not supported\n");
+ return NULL;
+ }
+ if (!flow_db->parent_child_db.parent_flow_tbl[pc_idx].valid) {
+ BNXT_TF_DBG(ERR, "Not a valid tunnel index\n");
+ return NULL;
+ }
+
+ return &flow_db->parent_child_db.parent_flow_tbl[pc_idx];
+}
+
+/* internal validation function for parent flow tbl */
+static struct bnxt_ulp_flow_db *
+ulp_flow_db_parent_arg_validation(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t tun_idx)
+{
+ struct bnxt_ulp_flow_db *flow_db;
+
+ flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
+ if (!flow_db) {
+ BNXT_TF_DBG(ERR, "Invalid Arguments\n");
+ return NULL;
+ }
+
+ /* check for max flows */
+ if (tun_idx >= BNXT_ULP_MAX_TUN_CACHE_ENTRIES) {
+ BNXT_TF_DBG(ERR, "Invalid tunnel index\n");
+ return NULL;
+ }
+
+ /* No support for parent child db then just exit */
+ if (!flow_db->parent_child_db.entries_count) {
+ BNXT_TF_DBG(ERR, "parent child db not supported\n");
+ return NULL;
+ }
+
+ return flow_db;
+}
+
/*
* Allocate the entry in the parent-child database
*
* ulp_ctxt [in] Ptr to ulp_context
- * fid [in] The flow id to the flow entry
+ * tun_idx [in] The tunnel index of the flow entry
*
* returns index on success and negative on failure.
*/
-int32_t
-ulp_flow_db_parent_flow_alloc(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t fid)
+static int32_t
+ulp_flow_db_pc_db_idx_alloc(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t tun_idx)
{
struct bnxt_ulp_flow_db *flow_db;
struct ulp_fdb_parent_child_db *p_pdb;
uint32_t idx, free_idx = 0;
/* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, fid);
+ flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, tun_idx);
if (!flow_db) {
BNXT_TF_DBG(ERR, "parent child db validation failed\n");
return -EINVAL;
@@ -1332,11 +1275,11 @@ ulp_flow_db_parent_flow_alloc(struct bnxt_ulp_context *ulp_ctxt,
p_pdb = &flow_db->parent_child_db;
for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == fid) {
- BNXT_TF_DBG(ERR, "fid is already allocated\n");
- return -EINVAL;
+ if (p_pdb->parent_flow_tbl[idx].valid &&
+ p_pdb->parent_flow_tbl[idx].tun_idx == tun_idx) {
+ return idx;
}
- if (!p_pdb->parent_flow_tbl[idx].parent_fid && !free_idx)
+ if (!p_pdb->parent_flow_tbl[idx].valid && !free_idx)
free_idx = idx + 1;
}
/* no free slots */
@@ -1347,132 +1290,148 @@ ulp_flow_db_parent_flow_alloc(struct bnxt_ulp_context *ulp_ctxt,
free_idx -= 1;
/* set the Fid in the parent child */
- p_pdb->parent_flow_tbl[free_idx].parent_fid = fid;
+ p_pdb->parent_flow_tbl[free_idx].tun_idx = tun_idx;
+ p_pdb->parent_flow_tbl[free_idx].valid = 1;
return free_idx;
}
/*
* Free the entry in the parent-child database
*
- * ulp_ctxt [in] Ptr to ulp_context
- * fid [in] The flow id to the flow entry
+ * pc_entry [in] Ptr to parent child db entry
*
- * returns 0 on success and negative on failure.
+ * returns none.
*/
-int32_t
-ulp_flow_db_parent_flow_free(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t fid)
+static void
+ulp_flow_db_pc_db_entry_free(struct bnxt_ulp_context *ulp_ctxt,
+ struct ulp_fdb_parent_info *pc_entry)
{
+ struct bnxt_tun_cache_entry *tun_tbl;
struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
- uint32_t idx;
+ uint64_t *tmp_bitset;
- /* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, fid);
- if (!flow_db) {
- BNXT_TF_DBG(ERR, "parent child db validation failed\n");
- return -EINVAL;
- }
+ /* free the tunnel entry */
+ tun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(ulp_ctxt);
+ if (tun_tbl)
+ ulp_tunnel_offload_entry_clear(tun_tbl, pc_entry->tun_idx);
- p_pdb = &flow_db->parent_child_db;
- for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == fid) {
- /* free the contents */
- p_pdb->parent_flow_tbl[idx].parent_fid = 0;
- memset(p_pdb->parent_flow_tbl[idx].child_fid_bitset,
- 0, p_pdb->child_bitset_size);
- return 0;
- }
- }
- BNXT_TF_DBG(ERR, "parent entry not found = %x\n", fid);
- return -EINVAL;
+ /* free the child bitset*/
+ flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
+ if (flow_db)
+ memset(pc_entry->child_fid_bitset, 0,
+ flow_db->parent_child_db.child_bitset_size);
+
+ /* free the contents */
+ tmp_bitset = pc_entry->child_fid_bitset;
+ memset(pc_entry, 0, sizeof(struct ulp_fdb_parent_info));
+ pc_entry->child_fid_bitset = tmp_bitset;
}
/*
- * Set or reset the child flow in the parent-child database
+ * Set or reset the parent flow in the parent-child database
*
* ulp_ctxt [in] Ptr to ulp_context
+ * pc_idx [in] The index to parent child db
* parent_fid [in] The flow id of the parent flow entry
- * child_fid [in] The flow id of the child flow entry
* set_flag [in] Use 1 for setting child, 0 to reset
*
* returns zero on success and negative on failure.
*/
int32_t
-ulp_flow_db_parent_child_flow_set(struct bnxt_ulp_context *ulp_ctxt,
+ulp_flow_db_pc_db_parent_flow_set(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t pc_idx,
uint32_t parent_fid,
- uint32_t child_fid,
uint32_t set_flag)
{
+ struct ulp_fdb_parent_info *pc_entry;
struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
- uint32_t idx, a_idx;
- uint64_t *t;
- /* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
+ flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
if (!flow_db) {
BNXT_TF_DBG(ERR, "parent child db validation failed\n");
return -EINVAL;
}
/* check for fid validity */
- if (child_fid >= flow_db->flow_tbl.num_flows || !child_fid) {
- BNXT_TF_DBG(ERR, "Invalid child flow index %x\n", child_fid);
+ if (parent_fid >= flow_db->flow_tbl.num_flows || !parent_fid) {
+ BNXT_TF_DBG(ERR, "Invalid parent flow index %x\n", parent_fid);
return -EINVAL;
}
- p_pdb = &flow_db->parent_child_db;
- a_idx = child_fid / ULP_INDEX_BITMAP_SIZE;
- for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
- t = p_pdb->parent_flow_tbl[idx].child_fid_bitset;
- if (set_flag)
- ULP_INDEX_BITMAP_SET(t[a_idx], child_fid);
- else
- ULP_INDEX_BITMAP_RESET(t[a_idx], child_fid);
- return 0;
- }
+ /* validate the arguments and parent child entry */
+ pc_entry = ulp_flow_db_pc_db_entry_get(ulp_ctxt, pc_idx);
+ if (!pc_entry) {
+ BNXT_TF_DBG(ERR, "failed to get the parent child entry\n");
+ return -EINVAL;
}
- BNXT_TF_DBG(ERR, "Unable to set the parent-child flow %x:%x\n",
- parent_fid, child_fid);
- return -1;
+
+ if (set_flag) {
+ pc_entry->parent_fid = parent_fid;
+ } else {
+ if (pc_entry->parent_fid != parent_fid)
+ BNXT_TF_DBG(ERR, "Panic: invalid parent id\n");
+ pc_entry->parent_fid = 0;
+
+ /* Free the parent child db entry if no user present */
+ if (!pc_entry->f2_cnt)
+ ulp_flow_db_pc_db_entry_free(ulp_ctxt, pc_entry);
+ }
+ return 0;
}
/*
- * Get the parent index from the parent-child database
+ * Set or reset the child flow in the parent-child database
*
* ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
- * parent_idx [out] The parent index of parent flow entry
+ * pc_idx [in] The index to parent child db
+ * child_fid [in] The flow id of the child flow entry
+ * set_flag [in] Use 1 for setting child, 0 to reset
*
* returns zero on success and negative on failure.
*/
int32_t
-ulp_flow_db_parent_flow_idx_get(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid,
- uint32_t *parent_idx)
+ulp_flow_db_pc_db_child_flow_set(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t pc_idx,
+ uint32_t child_fid,
+ uint32_t set_flag)
{
+ struct ulp_fdb_parent_info *pc_entry;
struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
- uint32_t idx;
+ uint32_t a_idx;
+ uint64_t *t;
- /* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
+ flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
if (!flow_db) {
BNXT_TF_DBG(ERR, "parent child db validation failed\n");
return -EINVAL;
}
- p_pdb = &flow_db->parent_child_db;
- for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
- *parent_idx = idx;
- return 0;
- }
+ /* check for fid validity */
+ if (child_fid >= flow_db->flow_tbl.num_flows || !child_fid) {
+ BNXT_TF_DBG(ERR, "Invalid child flow index %x\n", child_fid);
+ return -EINVAL;
}
- BNXT_TF_DBG(ERR, "Unable to get the parent flow %x\n", parent_fid);
- return -1;
+
+ /* validate the arguments and parent child entry */
+ pc_entry = ulp_flow_db_pc_db_entry_get(ulp_ctxt, pc_idx);
+ if (!pc_entry) {
+ BNXT_TF_DBG(ERR, "failed to get the parent child entry\n");
+ return -EINVAL;
+ }
+
+ a_idx = child_fid / ULP_INDEX_BITMAP_SIZE;
+ t = pc_entry->child_fid_bitset;
+ if (set_flag) {
+ ULP_INDEX_BITMAP_SET(t[a_idx], child_fid);
+ pc_entry->f2_cnt++;
+ } else {
+ ULP_INDEX_BITMAP_RESET(t[a_idx], child_fid);
+ if (pc_entry->f2_cnt)
+ pc_entry->f2_cnt--;
+ if (!pc_entry->f2_cnt && !pc_entry->parent_fid)
+ ulp_flow_db_pc_db_entry_free(ulp_ctxt, pc_entry);
+ }
+ return 0;
}
/*
@@ -1541,13 +1500,13 @@ ulp_flow_db_parent_child_flow_next_entry_get(struct bnxt_ulp_flow_db *flow_db,
* Set the counter accumulation in the parent flow
*
* ulp_ctxt [in] Ptr to ulp_context
- * parent_idx [in] The parent index of the parent flow entry
+ * pc_idx [in] The parent child index of the parent flow entry
*
* returns index on success and negative on failure.
*/
static int32_t
ulp_flow_db_parent_flow_count_accum_set(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_idx)
+ uint32_t pc_idx)
{
struct bnxt_ulp_flow_db *flow_db;
struct ulp_fdb_parent_child_db *p_pdb;
@@ -1560,50 +1519,16 @@ ulp_flow_db_parent_flow_count_accum_set(struct bnxt_ulp_context *ulp_ctxt,
/* check for parent idx validity */
p_pdb = &flow_db->parent_child_db;
- if (parent_idx >= p_pdb->entries_count ||
- !p_pdb->parent_flow_tbl[parent_idx].parent_fid) {
- BNXT_TF_DBG(ERR, "Invalid parent flow index %x\n", parent_idx);
+ if (pc_idx >= p_pdb->entries_count ||
+ !p_pdb->parent_flow_tbl[pc_idx].parent_fid) {
+ BNXT_TF_DBG(ERR, "Invalid parent child index %x\n", pc_idx);
return -EINVAL;
}
- p_pdb->parent_flow_tbl[parent_idx].counter_acc = 1;
+ p_pdb->parent_flow_tbl[pc_idx].counter_acc = 1;
return 0;
}
-/*
- * Get the counter accumulation in the parent flow
- *
- * ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
- *
- * returns 0 if counter accum is set else -1.
- */
-static int32_t
-ulp_flow_db_parent_flow_count_accum_get(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid)
-{
- struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
- uint32_t idx;
-
- /* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
- if (!flow_db) {
- BNXT_TF_DBG(ERR, "parent child db validation failed\n");
- return -EINVAL;
- }
-
- p_pdb = &flow_db->parent_child_db;
- for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
- if (p_pdb->parent_flow_tbl[idx].counter_acc)
- return 0;
- break;
- }
- }
- return -1;
-}
-
/*
* Orphan the child flow entry
* This is called only for child flows that have
@@ -1677,22 +1602,30 @@ int32_t
ulp_flow_db_parent_flow_create(struct bnxt_ulp_mapper_parms *parms)
{
struct ulp_flow_db_res_params fid_parms;
- uint32_t sub_typ = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC;
+ uint32_t sub_typ = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT;
struct ulp_flow_db_res_params res_params;
- int32_t fid_idx, rc;
+ int32_t pc_idx;
- /* create the child flow entry in parent flow table */
- fid_idx = ulp_flow_db_parent_flow_alloc(parms->ulp_ctx, parms->fid);
- if (fid_idx < 0) {
- BNXT_TF_DBG(ERR, "Error in creating parent flow fid %x\n",
- parms->fid);
- return -1;
+ /* create or get the parent child database */
+ pc_idx = ulp_flow_db_pc_db_idx_alloc(parms->ulp_ctx, parms->tun_idx);
+ if (pc_idx < 0) {
+ BNXT_TF_DBG(ERR, "Error in getting parent child db %x\n",
+ parms->tun_idx);
+ return -EINVAL;
+ }
+
+ /* Update the parent fid */
+ if (ulp_flow_db_pc_db_parent_flow_set(parms->ulp_ctx, pc_idx,
+ parms->fid, 1)) {
+ BNXT_TF_DBG(ERR, "Error in setting parent fid %x\n",
+ parms->tun_idx);
+ return -EINVAL;
}
/* Add the parent details in the resource list of the flow */
memset(&fid_parms, 0, sizeof(fid_parms));
fid_parms.resource_func = BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW;
- fid_parms.resource_hndl = fid_idx;
+ fid_parms.resource_hndl = pc_idx;
fid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO;
if (ulp_flow_db_resource_add(parms->ulp_ctx, BNXT_ULP_FDB_TYPE_REGULAR,
parms->fid, &fid_parms)) {
@@ -1710,20 +1643,13 @@ ulp_flow_db_parent_flow_create(struct bnxt_ulp_mapper_parms *parms)
&res_params)) {
/* Enable the counter accumulation in parent entry */
if (ulp_flow_db_parent_flow_count_accum_set(parms->ulp_ctx,
- fid_idx)) {
+ pc_idx)) {
BNXT_TF_DBG(ERR, "Error in setting counter acc %x\n",
parms->fid);
return -1;
}
}
- rc = ulp_flow_db_parent_tun_idx_set(parms->ulp_ctx, fid_idx,
- parms->tun_idx);
- if (rc) {
- BNXT_TF_DBG(ERR, "Error setting tun_idx in the parent flow\n");
- return rc;
- }
-
return 0;
}
@@ -1741,13 +1667,19 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
uint32_t sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT;
enum bnxt_ulp_resource_func res_fun;
struct ulp_flow_db_res_params res_p;
- uint32_t parent_fid = parms->parent_fid;
- int32_t rc;
+ int32_t rc, pc_idx;
+
+ /* create or get the parent child database */
+ pc_idx = ulp_flow_db_pc_db_idx_alloc(parms->ulp_ctx, parms->tun_idx);
+ if (pc_idx < 0) {
+ BNXT_TF_DBG(ERR, "Error in getting parent child db %x\n",
+ parms->tun_idx);
+ return -1;
+ }
/* create the parent flow entry in parent flow table */
- rc = ulp_flow_db_parent_child_flow_set(parms->ulp_ctx,
- parms->parent_fid,
- parms->fid, 1);
+ rc = ulp_flow_db_pc_db_child_flow_set(parms->ulp_ctx, pc_idx,
+ parms->fid, 1);
if (rc) {
BNXT_TF_DBG(ERR, "Error in setting child fid %x\n", parms->fid);
return rc;
@@ -1756,7 +1688,7 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
/* Add the parent details in the resource list of the flow */
memset(&fid_parms, 0, sizeof(fid_parms));
fid_parms.resource_func = BNXT_ULP_RESOURCE_FUNC_CHILD_FLOW;
- fid_parms.resource_hndl = parms->parent_fid;
+ fid_parms.resource_hndl = pc_idx;
fid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO;
rc = ulp_flow_db_resource_add(parms->ulp_ctx,
BNXT_ULP_FDB_TYPE_REGULAR,
@@ -1767,30 +1699,26 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
return rc;
}
- /* check if accumulation count is set for parent flow */
- rc = ulp_flow_db_parent_flow_count_accum_get(parms->ulp_ctx,
- parms->parent_fid);
+ /* check if internal count action included for this flow.*/
+ res_fun = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE;
+ rc = ulp_flow_db_resource_params_get(parms->ulp_ctx,
+ BNXT_ULP_FDB_TYPE_REGULAR,
+ parms->fid,
+ res_fun,
+ sub_type,
+ &res_p);
if (!rc) {
- /* check if internal count action included for this flow.*/
- res_fun = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE;
- rc = ulp_flow_db_resource_params_get(parms->ulp_ctx,
- BNXT_ULP_FDB_TYPE_REGULAR,
- parms->fid,
- res_fun,
- sub_type,
- &res_p);
- if (!rc) {
- /* update the counter manager to include parent fid */
- if (ulp_fc_mgr_cntr_parent_flow_set(parms->ulp_ctx,
- res_p.direction,
- res_p.resource_hndl,
- parent_fid)) {
- BNXT_TF_DBG(ERR, "Error in setting child %x\n",
- parms->fid);
- return -1;
- }
+ /* update the counter manager to include parent fid */
+ if (ulp_fc_mgr_cntr_parent_flow_set(parms->ulp_ctx,
+ res_p.direction,
+ res_p.resource_hndl,
+ pc_idx)) {
+ BNXT_TF_DBG(ERR, "Error in setting child %x\n",
+ parms->fid);
+ return -1;
}
}
+
/* return success */
return 0;
}
@@ -1799,7 +1727,7 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
* Update the parent counters
*
* ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
+ * pc_idx [in] The parent flow entry idx
* packet_count [in] - packet count
* byte_count [in] - byte count
*
@@ -1807,41 +1735,31 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
*/
int32_t
ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid,
+ uint32_t pc_idx,
uint64_t packet_count,
uint64_t byte_count)
{
- struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
- uint32_t idx;
+ struct ulp_fdb_parent_info *pc_entry;
- /* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
- if (!flow_db) {
- BNXT_TF_DBG(ERR, "parent child db validation failed\n");
+ /* validate the arguments and get parent child entry */
+ pc_entry = ulp_flow_db_pc_db_entry_get(ulp_ctxt, pc_idx);
+ if (!pc_entry) {
+ BNXT_TF_DBG(ERR, "failed to get the parent child entry\n");
return -EINVAL;
}
- p_pdb = &flow_db->parent_child_db;
- for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
- if (p_pdb->parent_flow_tbl[idx].counter_acc) {
- p_pdb->parent_flow_tbl[idx].pkt_count +=
- packet_count;
- p_pdb->parent_flow_tbl[idx].byte_count +=
- byte_count;
- }
- return 0;
- }
+ if (pc_entry->counter_acc) {
+ pc_entry->pkt_count += packet_count;
+ pc_entry->byte_count += byte_count;
}
- return -ENOENT;
+ return 0;
}
/*
* Get the parent accumulation counters
*
* ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
+ * pc_idx [in] The parent flow entry idx
* packet_count [out] - packet count
* byte_count [out] - byte count
*
@@ -1849,37 +1767,27 @@ ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt,
*/
int32_t
ulp_flow_db_parent_flow_count_get(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid, uint64_t *packet_count,
+ uint32_t pc_idx, uint64_t *packet_count,
uint64_t *byte_count, uint8_t count_reset)
{
- struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
- uint32_t idx;
+ struct ulp_fdb_parent_info *pc_entry;
- /* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
- if (!flow_db) {
- BNXT_TF_DBG(ERR, "parent child db validation failed\n");
+ /* validate the arguments and get parent child entry */
+ pc_entry = ulp_flow_db_pc_db_entry_get(ulp_ctxt, pc_idx);
+ if (!pc_entry) {
+ BNXT_TF_DBG(ERR, "failed to get the parent child entry\n");
return -EINVAL;
}
- p_pdb = &flow_db->parent_child_db;
- for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
- if (p_pdb->parent_flow_tbl[idx].counter_acc) {
- *packet_count =
- p_pdb->parent_flow_tbl[idx].pkt_count;
- *byte_count =
- p_pdb->parent_flow_tbl[idx].byte_count;
- if (count_reset) {
- p_pdb->parent_flow_tbl[idx].pkt_count = 0;
- p_pdb->parent_flow_tbl[idx].byte_count = 0;
- }
- }
- return 0;
+ if (pc_entry->counter_acc) {
+ *packet_count = pc_entry->pkt_count;
+ *byte_count = pc_entry->byte_count;
+ if (count_reset) {
+ pc_entry->pkt_count = 0;
+ pc_entry->byte_count = 0;
}
}
- return -ENOENT;
+ return 0;
}
/*
@@ -1897,7 +1805,7 @@ ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt)
uint32_t idx;
/* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, 1);
+ flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
if (!flow_db) {
BNXT_TF_DBG(ERR, "parent child db validation failed\n");
return;
@@ -1905,7 +1813,7 @@ ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt)
p_pdb = &flow_db->parent_child_db;
for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid &&
+ if (p_pdb->parent_flow_tbl[idx].valid &&
p_pdb->parent_flow_tbl[idx].counter_acc) {
p_pdb->parent_flow_tbl[idx].pkt_count = 0;
p_pdb->parent_flow_tbl[idx].byte_count = 0;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
index 0ddfa6f66d..8680ee8f65 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
@@ -58,6 +58,7 @@ struct bnxt_ulp_flow_tbl {
/* Structure to maintain parent-child flow relationships */
struct ulp_fdb_parent_info {
+ uint32_t valid;
uint32_t parent_fid;
uint32_t counter_acc;
uint64_t pkt_count;
@@ -259,45 +260,38 @@ int32_t
ulp_default_flow_db_cfa_action_get(struct bnxt_ulp_context *ulp_ctx,
uint32_t flow_id,
uint16_t *cfa_action);
-/*
- * Allocate the entry in the parent-child database
- *
- * ulp_ctxt [in] Ptr to ulp_context
- * fid [in] The flow id to the flow entry
- *
- * returns index on success and negative on failure.
- */
-int32_t
-ulp_flow_db_parent_flow_alloc(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t fid);
/*
- * Free the entry in the parent-child database
+ * Set or reset the parent flow in the parent-child database
*
* ulp_ctxt [in] Ptr to ulp_context
- * fid [in] The flow id to the flow entry
+ * pc_idx [in] The index to parent child db
+ * parent_fid [in] The flow id of the parent flow entry
+ * set_flag [in] Use 1 for setting child, 0 to reset
*
- * returns 0 on success and negative on failure.
+ * returns zero on success and negative on failure.
*/
int32_t
-ulp_flow_db_parent_flow_free(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t fid);
+ulp_flow_db_pc_db_parent_flow_set(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t pc_idx,
+ uint32_t parent_fid,
+ uint32_t set_flag);
/*
* Set or reset the child flow in the parent-child database
*
* ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
+ * pc_idx [in] The index to parent child db
* child_fid [in] The flow id of the child flow entry
* set_flag [in] Use 1 for setting child, 0 to reset
*
* returns zero on success and negative on failure.
*/
int32_t
-ulp_flow_db_parent_child_flow_set(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid,
- uint32_t child_fid,
- uint32_t set_flag);
+ulp_flow_db_pc_db_child_flow_set(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t pc_idx,
+ uint32_t child_fid,
+ uint32_t set_flag);
/*
* Get the parent index from the parent-child database
@@ -368,7 +362,7 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms);
* Update the parent counters
*
* ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
+ * pc_idx [in] The parent flow entry idx
* packet_count [in] - packet count
* byte_count [in] - byte count
*
@@ -376,14 +370,14 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms);
*/
int32_t
ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid,
+ uint32_t pc_idx,
uint64_t packet_count,
uint64_t byte_count);
/*
* Get the parent accumulation counters
*
* ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
+ * pc_idx [in] The parent flow entry idx
* packet_count [out] - packet count
* byte_count [out] - byte count
*
@@ -391,7 +385,7 @@ ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt,
*/
int32_t
ulp_flow_db_parent_flow_count_get(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid,
+ uint32_t pc_idx,
uint64_t *packet_count,
uint64_t *byte_count,
uint8_t count_reset);
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 7fc3767b33..6d804c7ef9 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -544,34 +544,14 @@ ulp_mapper_parent_flow_free(struct bnxt_ulp_context *ulp,
uint32_t parent_fid,
struct ulp_flow_db_res_params *res)
{
- uint32_t idx, child_fid = 0, parent_idx;
- struct bnxt_ulp_flow_db *flow_db;
+ uint32_t pc_idx;
- parent_idx = (uint32_t)res->resource_hndl;
+ pc_idx = (uint32_t)res->resource_hndl;
- /* check the validity of the parent fid */
- if (ulp_flow_db_parent_flow_idx_get(ulp, parent_fid, &idx) ||
- idx != parent_idx) {
- BNXT_TF_DBG(ERR, "invalid parent flow id %x\n", parent_fid);
- return -EINVAL;
- }
-
- /* Clear all the child flows parent index */
- flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp);
- while (!ulp_flow_db_parent_child_flow_next_entry_get(flow_db, idx,
- &child_fid)) {
- /* update the child flows resource handle */
- if (ulp_flow_db_child_flow_reset(ulp, BNXT_ULP_FDB_TYPE_REGULAR,
- child_fid)) {
- BNXT_TF_DBG(ERR, "failed to reset child flow %x\n",
- child_fid);
- return -EINVAL;
- }
- }
-
- /* free the parent entry in the parent table flow */
- if (ulp_flow_db_parent_flow_free(ulp, parent_fid)) {
- BNXT_TF_DBG(ERR, "failed to free parent flow %x\n", parent_fid);
+ /* reset the child flow bitset*/
+ if (ulp_flow_db_pc_db_parent_flow_set(ulp, pc_idx, parent_fid, 0)) {
+ BNXT_TF_DBG(ERR, "error in reset parent flow bitset %x:%x\n",
+ pc_idx, parent_fid);
return -EINVAL;
}
return 0;
@@ -582,16 +562,14 @@ ulp_mapper_child_flow_free(struct bnxt_ulp_context *ulp,
uint32_t child_fid,
struct ulp_flow_db_res_params *res)
{
- uint32_t parent_fid;
+ uint32_t pc_idx;
- parent_fid = (uint32_t)res->resource_hndl;
- if (!parent_fid)
- return 0; /* Already freed - orphan child*/
+ pc_idx = (uint32_t)res->resource_hndl;
/* reset the child flow bitset*/
- if (ulp_flow_db_parent_child_flow_set(ulp, parent_fid, child_fid, 0)) {
+ if (ulp_flow_db_pc_db_child_flow_set(ulp, pc_idx, child_fid, 0)) {
BNXT_TF_DBG(ERR, "error in resetting child flow bitset %x:%x\n",
- parent_fid, child_fid);
+ pc_idx, child_fid);
return -EINVAL;
}
return 0;
@@ -1944,6 +1922,12 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
+ /* If only allocation of identifier then perform and exit */
+ if (tbl->tbl_opcode == BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT) {
+ rc = ulp_mapper_tcam_tbl_scan_ident_alloc(parms, tbl);
+ return rc;
+ }
+
kflds = ulp_mapper_key_fields_get(parms, tbl, &num_kflds);
if (!kflds || !num_kflds) {
BNXT_TF_DBG(ERR, "Failed to get key fields\n");
@@ -3889,7 +3873,7 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
parms.class_tid = cparms->class_tid;
parms.flow_type = cparms->flow_type;
parms.parent_flow = cparms->parent_flow;
- parms.parent_fid = cparms->parent_fid;
+ parms.child_flow = cparms->child_flow;
parms.fid = cparms->flow_id;
parms.tun_idx = cparms->tun_idx;
parms.app_priority = cparms->app_priority;
@@ -3954,7 +3938,7 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
rc = ulp_flow_db_parent_flow_create(&parms);
if (rc)
goto flow_error;
- } else if (parms.parent_fid) {
+ } else if (parms.child_flow) {
/* create a child flow details */
rc = ulp_flow_db_child_flow_create(&parms);
if (rc)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
index 004e89ac2b..d4d6969bb5 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
@@ -53,7 +53,7 @@ struct bnxt_ulp_mapper_parms {
enum bnxt_ulp_fdb_type flow_type;
struct bnxt_ulp_mapper_data *mapper_data;
struct bnxt_ulp_device_params *device_params;
- uint32_t parent_fid;
+ uint32_t child_flow;
uint32_t parent_flow;
uint8_t tun_idx;
uint32_t app_priority;
@@ -79,8 +79,8 @@ struct bnxt_ulp_mapper_create_parms {
enum bnxt_ulp_fdb_type flow_type;
uint32_t flow_id;
- /* if set then create it as a child flow with parent as parent_fid */
- uint32_t parent_fid;
+ /* if set then create it as a child flow */
+ uint32_t child_flow;
/* if set then create a parent flow */
uint32_t parent_flow;
uint8_t tun_idx;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
index 35e9858727..c43774069a 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
@@ -215,6 +215,21 @@ struct bnxt_ulp_rte_act_info ulp_act_info[] = {
}
};
+struct bnxt_ulp_rte_act_info ulp_vendor_act_info[] = {
+ [BNXT_RTE_FLOW_ITEM_TYPE_END - BNXT_RTE_FLOW_ITEM_TYPE_END] = {
+ .act_type = BNXT_RTE_FLOW_ITEM_TYPE_END,
+ .proto_act_func = NULL
+ },
+ [BNXT_RTE_FLOW_ITEM_TYPE_VXLAN_DECAP - BNXT_RTE_FLOW_ITEM_TYPE_END] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_vendor_vxlan_decap_act_handler
+ },
+ [BNXT_RTE_FLOW_ITEM_TYPE_LAST - BNXT_RTE_FLOW_ITEM_TYPE_END] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ }
+};
+
/*
* This table has to be indexed based on the rte_flow_item_type that is part of
* DPDK. The below array is list of parsing functions for each of the flow items
@@ -414,3 +429,19 @@ struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = {
.proto_hdr_func = NULL
}
};
+
+struct bnxt_ulp_rte_hdr_info ulp_vendor_hdr_info[] = {
+ [BNXT_RTE_FLOW_ITEM_TYPE_END - BNXT_RTE_FLOW_ITEM_TYPE_END] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_END,
+ .proto_hdr_func = NULL
+ },
+ [BNXT_RTE_FLOW_ITEM_TYPE_VXLAN_DECAP - BNXT_RTE_FLOW_ITEM_TYPE_END] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_vendor_vxlan_decap_hdr_handler
+ },
+ [BNXT_RTE_FLOW_ITEM_TYPE_LAST - BNXT_RTE_FLOW_ITEM_TYPE_END] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+
+};
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index 79b9957781..fadcd3873c 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -125,13 +125,21 @@ bnxt_ulp_rte_parser_hdr_parse(const struct rte_flow_item pattern[],
/* Parse all the items in the pattern */
while (item && item->type != RTE_FLOW_ITEM_TYPE_END) {
- /* get the header information from the flow_hdr_info table */
- hdr_info = &ulp_hdr_info[item->type];
+ if (item->type >= (uint32_t)
+ BNXT_RTE_FLOW_ITEM_TYPE_END) {
+ if (item->type >=
+ (uint32_t)BNXT_RTE_FLOW_ITEM_TYPE_LAST)
+ goto hdr_parser_error;
+ /* get the header information */
+ hdr_info = &ulp_vendor_hdr_info[item->type -
+ BNXT_RTE_FLOW_ITEM_TYPE_END];
+ } else {
+ if (item->type > RTE_FLOW_ITEM_TYPE_HIGIG2)
+ goto hdr_parser_error;
+ hdr_info = &ulp_hdr_info[item->type];
+ }
if (hdr_info->hdr_type == BNXT_ULP_HDR_TYPE_NOT_SUPPORTED) {
- BNXT_TF_DBG(ERR,
- "Truflow parser does not support type %d\n",
- item->type);
- return BNXT_TF_RC_PARSE_ERR;
+ goto hdr_parser_error;
} else if (hdr_info->hdr_type == BNXT_ULP_HDR_TYPE_SUPPORTED) {
/* call the registered callback handler */
if (hdr_info->proto_hdr_func) {
@@ -145,6 +153,11 @@ bnxt_ulp_rte_parser_hdr_parse(const struct rte_flow_item pattern[],
}
/* update the implied SVIF */
return ulp_rte_parser_implicit_match_port_process(params);
+
+hdr_parser_error:
+ BNXT_TF_DBG(ERR, "Truflow parser does not support type %d\n",
+ item->type);
+ return BNXT_TF_RC_PARSE_ERR;
}
/*
@@ -160,16 +173,23 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[],
/* Parse all the items in the pattern */
while (action_item && action_item->type != RTE_FLOW_ACTION_TYPE_END) {
- /* get the header information from the flow_hdr_info table */
- hdr_info = &ulp_act_info[action_item->type];
- if (hdr_info->act_type ==
- BNXT_ULP_ACT_TYPE_NOT_SUPPORTED) {
- BNXT_TF_DBG(ERR,
- "Truflow parser does not support act %u\n",
- action_item->type);
- return BNXT_TF_RC_ERROR;
- } else if (hdr_info->act_type ==
- BNXT_ULP_ACT_TYPE_SUPPORTED) {
+ if (action_item->type >=
+ (uint32_t)BNXT_RTE_FLOW_ACTION_TYPE_END) {
+ if (action_item->type >=
+ (uint32_t)BNXT_RTE_FLOW_ACTION_TYPE_LAST)
+ goto act_parser_error;
+ /* get the header information from bnxt actinfo table */
+ hdr_info = &ulp_vendor_act_info[action_item->type -
+ BNXT_RTE_FLOW_ACTION_TYPE_END];
+ } else {
+ if (action_item->type > RTE_FLOW_ACTION_TYPE_SHARED)
+ goto act_parser_error;
+ /* get the header information from the act info table */
+ hdr_info = &ulp_act_info[action_item->type];
+ }
+ if (hdr_info->act_type == BNXT_ULP_ACT_TYPE_NOT_SUPPORTED) {
+ goto act_parser_error;
+ } else if (hdr_info->act_type == BNXT_ULP_ACT_TYPE_SUPPORTED) {
/* call the registered callback handler */
if (hdr_info->proto_act_func) {
if (hdr_info->proto_act_func(action_item,
@@ -184,6 +204,11 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[],
/* update the implied port details */
ulp_rte_parser_implicit_act_port_process(params);
return BNXT_TF_RC_SUCCESS;
+
+act_parser_error:
+ BNXT_TF_DBG(ERR, "Truflow parser does not support act %u\n",
+ action_item->type);
+ return BNXT_TF_RC_ERROR;
}
/*
@@ -325,11 +350,10 @@ ulp_post_process_normal_flow(struct ulp_rte_parser_params *params)
/*
* Function to handle the post processing of the parsing details
*/
-int32_t
+void
bnxt_ulp_rte_parser_post_process(struct ulp_rte_parser_params *params)
{
ulp_post_process_normal_flow(params);
- return ulp_post_process_tun_flow(params);
}
/*
@@ -660,7 +684,7 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item,
{
const struct rte_flow_item_eth *eth_spec = item->spec;
const struct rte_flow_item_eth *eth_mask = item->mask;
- uint32_t idx = 0;
+ uint32_t idx = 0, dmac_idx = 0;
uint32_t size;
uint16_t eth_type = 0;
uint32_t inner_flag = 0;
@@ -686,6 +710,7 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item,
* Copy the rte_flow_item for eth into hdr_field using ethernet
* header fields
*/
+ dmac_idx = idx;
size = sizeof(((struct rte_flow_item_eth *)NULL)->dst.addr_bytes);
ulp_rte_prsr_fld_mask(params, &idx, size,
ulp_deference_struct(eth_spec, dst.addr_bytes),
@@ -719,6 +744,8 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item,
inner_flag = 1;
} else {
ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_ETH);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID,
+ dmac_idx);
}
/* Update the field protocol hdr bitmap */
ulp_rte_l2_proto_type_update(params, eth_type, inner_flag);
@@ -926,7 +953,7 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
const struct rte_flow_item_ipv4 *ipv4_spec = item->spec;
const struct rte_flow_item_ipv4 *ipv4_mask = item->mask;
struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap;
- uint32_t idx = 0;
+ uint32_t idx = 0, dip_idx = 0;
uint32_t size;
uint8_t proto = 0;
uint32_t inner_flag = 0;
@@ -939,22 +966,6 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
return BNXT_TF_RC_ERROR;
}
- if (!ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
- BNXT_ULP_HDR_BIT_O_ETH) &&
- !ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
- BNXT_ULP_HDR_BIT_I_ETH)) {
- /* Since F2 flow does not include eth item, when parser detects
- * IPv4/IPv6 item list and it belongs to the outer header; i.e.,
- * o_ipv4/o_ipv6, check if O_ETH and I_ETH is set. If not set,
- * then add offset sizeof(o_eth/oo_vlan/oi_vlan) to the index.
- * This will allow the parser post processor to update the
- * t_dmac in hdr_field[o_eth.dmac]
- */
- idx += (BNXT_ULP_PROTO_HDR_ETH_NUM +
- BNXT_ULP_PROTO_HDR_VLAN_NUM);
- params->field_idx = idx;
- }
-
if (ulp_rte_prsr_fld_size_validate(params, &idx,
BNXT_ULP_PROTO_HDR_IPV4_NUM)) {
BNXT_TF_DBG(ERR, "Error parsing protocol header\n");
@@ -1033,6 +1044,7 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
ulp_deference_struct(ipv4_mask, hdr.src_addr),
ULP_PRSR_ACT_DEFAULT);
+ dip_idx = idx;
size = sizeof(((struct rte_flow_item_ipv4 *)NULL)->hdr.dst_addr);
ulp_rte_prsr_fld_mask(params, &idx, size,
ulp_deference_struct(ipv4_spec, hdr.dst_addr),
@@ -1048,6 +1060,9 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
} else {
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3, 1);
+ /* Update the tunnel offload dest ip offset */
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID,
+ dip_idx);
}
/* Some of the PMD applications may set the protocol field
@@ -1071,7 +1086,7 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
const struct rte_flow_item_ipv6 *ipv6_spec = item->spec;
const struct rte_flow_item_ipv6 *ipv6_mask = item->mask;
struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap;
- uint32_t idx = 0;
+ uint32_t idx = 0, dip_idx = 0;
uint32_t size;
uint32_t ver_spec = 0, ver_mask = 0;
uint32_t tc_spec = 0, tc_mask = 0;
@@ -1087,22 +1102,6 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
return BNXT_TF_RC_ERROR;
}
- if (!ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
- BNXT_ULP_HDR_BIT_O_ETH) &&
- !ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
- BNXT_ULP_HDR_BIT_I_ETH)) {
- /* Since F2 flow does not include eth item, when parser detects
- * IPv4/IPv6 item list and it belongs to the outer header; i.e.,
- * o_ipv4/o_ipv6, check if O_ETH and I_ETH is set. If not set,
- * then add offset sizeof(o_eth/oo_vlan/oi_vlan) to the index.
- * This will allow the parser post processor to update the
- * t_dmac in hdr_field[o_eth.dmac]
- */
- idx += (BNXT_ULP_PROTO_HDR_ETH_NUM +
- BNXT_ULP_PROTO_HDR_VLAN_NUM);
- params->field_idx = idx;
- }
-
if (ulp_rte_prsr_fld_size_validate(params, &idx,
BNXT_ULP_PROTO_HDR_IPV6_NUM)) {
BNXT_TF_DBG(ERR, "Error parsing protocol header\n");
@@ -1171,6 +1170,7 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
ulp_deference_struct(ipv6_mask, hdr.src_addr),
ULP_PRSR_ACT_DEFAULT);
+ dip_idx = idx;
size = sizeof(((struct rte_flow_item_ipv6 *)NULL)->hdr.dst_addr);
ulp_rte_prsr_fld_mask(params, &idx, size,
ulp_deference_struct(ipv6_spec, hdr.dst_addr),
@@ -1186,6 +1186,9 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
} else {
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3, 1);
+ /* Update the tunnel offload dest ip offset */
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID,
+ dip_idx);
}
/* Update the field protocol hdr bitmap */
@@ -1200,9 +1203,11 @@ static void
ulp_rte_l4_proto_type_update(struct ulp_rte_parser_params *param,
uint16_t dst_port)
{
- if (dst_port == tfp_cpu_to_be_16(ULP_UDP_PORT_VXLAN))
+ if (dst_port == tfp_cpu_to_be_16(ULP_UDP_PORT_VXLAN)) {
ULP_BITMAP_SET(param->hdr_fp_bit.bits,
BNXT_ULP_HDR_BIT_T_VXLAN);
+ ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_L3_TUN, 1);
+ }
if (ULP_BITMAP_ISSET(param->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_T_VXLAN) ||
@@ -2484,3 +2489,24 @@ ulp_rte_sample_act_handler(const struct rte_flow_action *action_item,
return ret;
}
+
+/* Function to handle the parsing of bnxt vendor Flow action vxlan Header. */
+int32_t
+ulp_vendor_vxlan_decap_act_handler(const struct rte_flow_action *action_item,
+ struct ulp_rte_parser_params *params)
+{
+ /* Set the F1 flow header bit */
+ ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F1);
+ return ulp_rte_vxlan_decap_act_handler(action_item, params);
+}
+
+/* Function to handle the parsing of bnxt vendor Flow item vxlan Header. */
+int32_t
+ulp_rte_vendor_vxlan_decap_hdr_handler(const struct rte_flow_item *item,
+ struct ulp_rte_parser_params *params)
+{
+ RTE_SET_USED(item);
+ /* Set the F2 flow header bit */
+ ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F2);
+ return ulp_rte_vxlan_decap_act_handler(NULL, params);
+}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
index 4431f1bbd0..673172c811 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
@@ -75,7 +75,7 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[],
/*
* Function to handle the post processing of the parsing details
*/
-int32_t
+void
bnxt_ulp_rte_parser_post_process(struct ulp_rte_parser_params *params);
/* Function to handle the parsing of RTE Flow item PF Header. */
@@ -270,4 +270,12 @@ int32_t
ulp_rte_shared_act_handler(const struct rte_flow_action *action_item,
struct ulp_rte_parser_params *params);
+int32_t
+ulp_vendor_vxlan_decap_act_handler(const struct rte_flow_action *action_item,
+ struct ulp_rte_parser_params *params);
+
+int32_t
+ulp_rte_vendor_vxlan_decap_hdr_handler(const struct rte_flow_item *item,
+ struct ulp_rte_parser_params *params);
+
#endif /* _ULP_RTE_PARSER_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index 0cbac66237..2685e63432 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -78,17 +78,19 @@ struct ulp_rte_parser_params {
uint32_t priority;
uint32_t fid;
uint32_t parent_flow;
- uint32_t parent_fid;
+ uint32_t child_flow;
uint16_t func_id;
uint16_t port_id;
uint32_t class_id;
uint32_t act_tmpl;
struct bnxt_ulp_context *ulp_ctx;
uint32_t hdr_sig_id;
- uint32_t flow_sig_id;
+ uint64_t flow_sig_id;
uint32_t flow_pattern_id;
uint32_t act_pattern_id;
uint8_t app_id;
+ uint8_t tun_idx;
+
};
/* Flow Parser Header Information Structure */
@@ -101,6 +103,7 @@ struct bnxt_ulp_rte_hdr_info {
/* Flow Parser Header Information Structure Array defined in template source*/
extern struct bnxt_ulp_rte_hdr_info ulp_hdr_info[];
+extern struct bnxt_ulp_rte_hdr_info ulp_vendor_hdr_info[];
/* Flow Parser Action Information Structure */
struct bnxt_ulp_rte_act_info {
@@ -113,6 +116,7 @@ struct bnxt_ulp_rte_act_info {
/* Flow Parser Action Information Structure Array defined in template source*/
extern struct bnxt_ulp_rte_act_info ulp_act_info[];
+extern struct bnxt_ulp_rte_act_info ulp_vendor_act_info[];
/* Flow Matcher structures */
struct bnxt_ulp_header_match_info {
@@ -136,7 +140,7 @@ struct bnxt_ulp_class_match_info {
uint8_t wc_pri;
uint8_t app_sig;
uint32_t hdr_sig_id;
- uint32_t flow_sig_id;
+ uint64_t flow_sig_id;
uint32_t flow_pattern_id;
};
diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.c b/drivers/net/bnxt/tf_ulp/ulp_tun.c
index a1dd5b902c..7ce6740633 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_tun.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_tun.c
@@ -3,225 +3,111 @@
* All rights reserved.
*/
-#include <sys/queue.h>
-
-#include <rte_malloc.h>
-
+#include "bnxt.h"
+#include "bnxt_ulp.h"
#include "ulp_tun.h"
-#include "ulp_rte_parser.h"
-#include "ulp_template_db_enum.h"
-#include "ulp_template_struct.h"
-#include "ulp_matcher.h"
-#include "ulp_mapper.h"
-#include "ulp_flow_db.h"
+#include "ulp_utils.h"
-/* This function programs the outer tunnel flow in the hardware. */
-static int32_t
-ulp_install_outer_tun_flow(struct ulp_rte_parser_params *params,
- struct bnxt_tun_cache_entry *tun_entry,
- uint16_t tun_idx)
+/* returns negative on error, 1 if new entry is allocated or zero if old */
+int32_t
+ulp_app_tun_search_entry(struct bnxt_ulp_context *ulp_ctx,
+ struct rte_flow_tunnel *app_tunnel,
+ struct bnxt_flow_app_tun_ent **tun_entry)
{
- struct bnxt_ulp_mapper_create_parms mparms = { 0 };
- int ret;
-
- /* Reset the JUMP action bit in the action bitmap as we don't
- * offload this action.
- */
- ULP_BITMAP_RESET(params->act_bitmap.bits, BNXT_ULP_ACT_BIT_JUMP);
-
- ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F1);
-
-#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
-#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER
- /* Dump the rte flow pattern */
- ulp_parser_hdr_info_dump(params);
- /* Dump the rte flow action */
- ulp_parser_act_info_dump(params);
-#endif
-#endif
-
- ret = ulp_matcher_pattern_match(params, ¶ms->class_id);
- if (ret != BNXT_TF_RC_SUCCESS)
- goto err;
+ struct bnxt_flow_app_tun_ent *tun_ent_list;
+ int32_t i, rc = 0, free_entry = -1;
- ret = ulp_matcher_action_match(params, ¶ms->act_tmpl);
- if (ret != BNXT_TF_RC_SUCCESS)
- goto err;
-
- params->parent_flow = true;
- bnxt_ulp_init_mapper_params(&mparms, params,
- BNXT_ULP_FDB_TYPE_REGULAR);
- mparms.tun_idx = tun_idx;
-
- /* Call the ulp mapper to create the flow in the hardware. */
- ret = ulp_mapper_flow_create(params->ulp_ctx, &mparms);
- if (ret)
- goto err;
-
- /* Store the tunnel dmac in the tunnel cache table and use it while
- * programming tunnel inner flow.
- */
- memcpy(tun_entry->t_dmac,
- ¶ms->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX].spec,
- RTE_ETHER_ADDR_LEN);
-
- tun_entry->tun_flow_info[params->port_id].state =
- BNXT_ULP_FLOW_STATE_TUN_O_OFFLD;
- tun_entry->outer_tun_flow_id = params->fid;
-
- /* Tunnel outer flow and it's related inner flows are correlated
- * based on Tunnel Destination IP Address.
- */
- if (tun_entry->t_dst_ip_valid)
- goto done;
- if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV4))
- memcpy(&tun_entry->t_dst_ip,
- ¶ms->hdr_field[ULP_TUN_O_IPV4_DIP_INDEX].spec,
- sizeof(rte_be32_t));
- else
- memcpy(tun_entry->t_dst_ip6,
- ¶ms->hdr_field[ULP_TUN_O_IPV6_DIP_INDEX].spec,
- sizeof(tun_entry->t_dst_ip6));
- tun_entry->t_dst_ip_valid = true;
+ tun_ent_list = bnxt_ulp_cntxt_ptr2_app_tun_list_get(ulp_ctx);
+ if (!tun_ent_list) {
+ BNXT_TF_DBG(ERR, "unable to get the app tunnel list\n");
+ return -EINVAL;
+ }
-done:
- return BNXT_TF_RC_FID;
+ for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {
+ if (!tun_ent_list[i].ref_cnt) {
+ if (free_entry < 0)
+ free_entry = i;
+ } else {
+ if (!memcmp(&tun_ent_list[i].app_tunnel,
+ app_tunnel,
+ sizeof(struct rte_flow_tunnel))) {
+ *tun_entry = &tun_ent_list[i];
+ tun_ent_list[free_entry].ref_cnt++;
+ return rc;
+ }
+ }
+ }
+ if (free_entry >= 0) {
+ *tun_entry = &tun_ent_list[free_entry];
+ memcpy(&tun_ent_list[free_entry].app_tunnel, app_tunnel,
+ sizeof(struct rte_flow_tunnel));
+ tun_ent_list[free_entry].ref_cnt = 1;
+ rc = 1;
+ } else {
+ BNXT_TF_DBG(ERR, "ulp app tunnel list is full\n");
+ return -ENOMEM;
+ }
-err:
- memset(tun_entry, 0, sizeof(struct bnxt_tun_cache_entry));
- return BNXT_TF_RC_ERROR;
+ return rc;
}
-/* This function programs the inner tunnel flow in the hardware. */
-static void
-ulp_install_inner_tun_flow(struct bnxt_tun_cache_entry *tun_entry,
- struct ulp_rte_parser_params *tun_o_params)
+void
+ulp_app_tun_entry_delete(struct bnxt_flow_app_tun_ent *tun_entry)
{
- struct bnxt_ulp_mapper_create_parms mparms = { 0 };
- struct ulp_per_port_flow_info *flow_info;
- struct ulp_rte_parser_params *inner_params;
- int ret;
-
- /* Tunnel inner flow doesn't have tunnel dmac, use the tunnel
- * dmac that was stored during F1 programming.
- */
- flow_info = &tun_entry->tun_flow_info[tun_o_params->port_id];
- STAILQ_FOREACH(inner_params, &flow_info->tun_i_prms_list, next) {
- memcpy(&inner_params->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX],
- tun_entry->t_dmac, RTE_ETHER_ADDR_LEN);
- inner_params->parent_fid = tun_entry->outer_tun_flow_id;
-
- bnxt_ulp_init_mapper_params(&mparms, inner_params,
- BNXT_ULP_FDB_TYPE_REGULAR);
-
- ret = ulp_mapper_flow_create(inner_params->ulp_ctx, &mparms);
- if (ret)
- PMD_DRV_LOG(ERR,
- "Failed to create inner tun flow, FID:%u.",
- inner_params->fid);
+ if (tun_entry) {
+ if (tun_entry->ref_cnt) {
+ tun_entry->ref_cnt--;
+ if (!tun_entry->ref_cnt)
+ memset(tun_entry, 0,
+ sizeof(struct bnxt_flow_app_tun_ent));
+ }
}
}
-/* This function either install outer tunnel flow & inner tunnel flow
- * or just the outer tunnel flow based on the flow state.
- */
-static int32_t
-ulp_post_process_outer_tun_flow(struct ulp_rte_parser_params *params,
- struct bnxt_tun_cache_entry *tun_entry,
- uint16_t tun_idx)
+int32_t
+ulp_app_tun_entry_set_decap_action(struct bnxt_flow_app_tun_ent *tun_entry)
{
- int ret;
-
- ret = ulp_install_outer_tun_flow(params, tun_entry, tun_idx);
- if (ret == BNXT_TF_RC_ERROR) {
- PMD_DRV_LOG(ERR, "Failed to create outer tunnel flow.");
- return ret;
- }
+ if (!tun_entry)
+ return -EINVAL;
- /* Install any cached tunnel inner flows that came before tunnel
- * outer flow.
- */
- ulp_install_inner_tun_flow(tun_entry, params);
-
- return BNXT_TF_RC_FID;
+ tun_entry->action.type = (typeof(tun_entry->action.type))
+ BNXT_RTE_FLOW_ACTION_TYPE_VXLAN_DECAP;
+ tun_entry->action.conf = tun_entry;
+ return 0;
}
-/* This function will be called if inner tunnel flow request comes before
- * outer tunnel flow request.
- */
-static int32_t
-ulp_post_process_cache_inner_tun_flow(struct ulp_rte_parser_params *params,
- struct bnxt_tun_cache_entry *tun_entry)
+int32_t
+ulp_app_tun_entry_set_decap_item(struct bnxt_flow_app_tun_ent *tun_entry)
{
- struct ulp_rte_parser_params *inner_tun_params;
- struct ulp_per_port_flow_info *flow_info;
- int ret;
-
-#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
-#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER
- /* Dump the rte flow pattern */
- ulp_parser_hdr_info_dump(params);
- /* Dump the rte flow action */
- ulp_parser_act_info_dump(params);
-#endif
-#endif
-
- ret = ulp_matcher_pattern_match(params, ¶ms->class_id);
- if (ret != BNXT_TF_RC_SUCCESS)
- return BNXT_TF_RC_ERROR;
-
- ret = ulp_matcher_action_match(params, ¶ms->act_tmpl);
- if (ret != BNXT_TF_RC_SUCCESS)
- return BNXT_TF_RC_ERROR;
-
- /* If Tunnel inner flow comes first then we can't install it in the
- * hardware, because, Tunnel inner flow will not have L2 context
- * information. So, just cache the Tunnel inner flow information
- * and program it in the context of F1 flow installation.
- */
- flow_info = &tun_entry->tun_flow_info[params->port_id];
- inner_tun_params = rte_zmalloc("ulp_inner_tun_params",
- sizeof(struct ulp_rte_parser_params), 0);
- if (!inner_tun_params)
- return BNXT_TF_RC_ERROR;
- memcpy(inner_tun_params, params, sizeof(struct ulp_rte_parser_params));
- STAILQ_INSERT_TAIL(&flow_info->tun_i_prms_list, inner_tun_params,
- next);
- flow_info->tun_i_cnt++;
-
- /* F1 and it's related Tunnel inner flows are correlated based on
- * Tunnel Destination IP Address. It could be already set, if
- * the inner flow got offloaded first.
- */
- if (tun_entry->t_dst_ip_valid)
- goto done;
- if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV4))
- memcpy(&tun_entry->t_dst_ip,
- ¶ms->hdr_field[ULP_TUN_O_IPV4_DIP_INDEX].spec,
- sizeof(rte_be32_t));
- else
- memcpy(tun_entry->t_dst_ip6,
- ¶ms->hdr_field[ULP_TUN_O_IPV6_DIP_INDEX].spec,
- sizeof(tun_entry->t_dst_ip6));
- tun_entry->t_dst_ip_valid = true;
-
-done:
- return BNXT_TF_RC_FID;
+ if (!tun_entry)
+ return -EINVAL;
+
+ tun_entry->item.type = (typeof(tun_entry->item.type))
+ BNXT_RTE_FLOW_ITEM_TYPE_VXLAN_DECAP;
+ tun_entry->item.spec = tun_entry;
+ tun_entry->item.last = NULL;
+ tun_entry->item.mask = NULL;
+ return 0;
}
-/* This function will be called if inner tunnel flow request comes after
- * the outer tunnel flow request.
- */
-static int32_t
-ulp_post_process_inner_tun_flow(struct ulp_rte_parser_params *params,
- struct bnxt_tun_cache_entry *tun_entry)
+struct bnxt_flow_app_tun_ent *
+ulp_app_tun_match_entry(struct bnxt_ulp_context *ulp_ctx,
+ const void *ctx)
{
- memcpy(¶ms->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX],
- tun_entry->t_dmac, RTE_ETHER_ADDR_LEN);
+ struct bnxt_flow_app_tun_ent *tun_ent_list;
+ int32_t i;
- params->parent_fid = tun_entry->outer_tun_flow_id;
+ tun_ent_list = bnxt_ulp_cntxt_ptr2_app_tun_list_get(ulp_ctx);
+ if (!tun_ent_list) {
+ BNXT_TF_DBG(ERR, "unable to get the app tunnel list\n");
+ return NULL;
+ }
- return BNXT_TF_RC_NORMAL;
+ for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {
+ if (&tun_ent_list[i] == ctx)
+ return &tun_ent_list[i];
+ }
+ return NULL;
}
static int32_t
@@ -229,203 +115,116 @@ ulp_get_tun_entry(struct ulp_rte_parser_params *params,
struct bnxt_tun_cache_entry **tun_entry,
uint16_t *tun_idx)
{
- int i, first_free_entry = BNXT_ULP_TUN_ENTRY_INVALID;
+ int32_t i, first_free_entry = BNXT_ULP_TUN_ENTRY_INVALID;
struct bnxt_tun_cache_entry *tun_tbl;
- bool tun_entry_found = false, free_entry_found = false;
+ uint32_t dip_idx, dmac_idx, use_ipv4 = 0;
tun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(params->ulp_ctx);
- if (!tun_tbl)
+ if (!tun_tbl) {
+ BNXT_TF_DBG(ERR, "Error: could not get Tunnel table\n");
return BNXT_TF_RC_ERROR;
+ }
+
+ /* get the outer destination ip field index */
+ dip_idx = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID);
+ dmac_idx = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID);
+ if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV4))
+ use_ipv4 = 1;
for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {
- if (!memcmp(&tun_tbl[i].t_dst_ip,
- ¶ms->hdr_field[ULP_TUN_O_IPV4_DIP_INDEX].spec,
- sizeof(rte_be32_t)) ||
- !memcmp(&tun_tbl[i].t_dst_ip6,
- ¶ms->hdr_field[ULP_TUN_O_IPV6_DIP_INDEX].spec,
- 16)) {
- tun_entry_found = true;
- break;
+ if (!tun_tbl[i].t_dst_ip_valid) {
+ if (first_free_entry == BNXT_ULP_TUN_ENTRY_INVALID)
+ first_free_entry = i;
+ continue;
}
-
- if (!tun_tbl[i].t_dst_ip_valid && !free_entry_found) {
- first_free_entry = i;
- free_entry_found = true;
+ /* match on the destination ip of the tunnel */
+ if ((use_ipv4 && !memcmp(&tun_tbl[i].t_dst_ip,
+ params->hdr_field[dip_idx].spec,
+ sizeof(rte_be32_t))) ||
+ (!use_ipv4 &&
+ !memcmp(tun_tbl[i].t_dst_ip6,
+ params->hdr_field[dip_idx].spec,
+ sizeof(((struct bnxt_tun_cache_entry *)
+ NULL)->t_dst_ip6)))) {
+ *tun_entry = &tun_tbl[i];
+ *tun_idx = i;
+ return 0;
}
}
-
- if (tun_entry_found) {
- *tun_entry = &tun_tbl[i];
- *tun_idx = i;
- } else {
- if (first_free_entry == BNXT_ULP_TUN_ENTRY_INVALID)
- return BNXT_TF_RC_ERROR;
- *tun_entry = &tun_tbl[first_free_entry];
- *tun_idx = first_free_entry;
- }
-
- return 0;
-}
-
-int32_t
-ulp_post_process_tun_flow(struct ulp_rte_parser_params *params)
-{
- bool inner_tun_sig, cache_inner_tun_flow;
- bool outer_tun_reject, outer_tun_flow, inner_tun_flow;
- enum bnxt_ulp_tun_flow_state flow_state;
- struct bnxt_tun_cache_entry *tun_entry;
- uint32_t l3_tun, l3_tun_decap;
- uint16_t tun_idx;
- int rc;
-
- /* Computational fields that indicate it's a TUNNEL DECAP flow */
- l3_tun = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_TUN);
- l3_tun_decap = ULP_COMP_FLD_IDX_RD(params,
- BNXT_ULP_CF_IDX_L3_TUN_DECAP);
- if (!l3_tun)
- return BNXT_TF_RC_NORMAL;
-
- rc = ulp_get_tun_entry(params, &tun_entry, &tun_idx);
- if (rc == BNXT_TF_RC_ERROR)
- return rc;
-
- if (params->port_id >= RTE_MAX_ETHPORTS)
+ if (first_free_entry == BNXT_ULP_TUN_ENTRY_INVALID) {
+ BNXT_TF_DBG(ERR, "Error: No entry available in tunnel table\n");
return BNXT_TF_RC_ERROR;
- flow_state = tun_entry->tun_flow_info[params->port_id].state;
- /* Outer tunnel flow validation */
- outer_tun_flow = BNXT_OUTER_TUN_FLOW(l3_tun, params);
- outer_tun_reject = BNXT_REJECT_OUTER_TUN_FLOW(flow_state,
- outer_tun_flow);
-
- /* Inner tunnel flow validation */
- inner_tun_sig = BNXT_INNER_TUN_SIGNATURE(l3_tun, l3_tun_decap, params);
- cache_inner_tun_flow = BNXT_CACHE_INNER_TUN_FLOW(flow_state,
- inner_tun_sig);
- inner_tun_flow = BNXT_INNER_TUN_FLOW(flow_state, inner_tun_sig);
-
- if (outer_tun_reject) {
- tun_entry->outer_tun_rej_cnt++;
- BNXT_TF_DBG(ERR,
- "Tunnel F1 flow rejected, COUNT: %d\n",
- tun_entry->outer_tun_rej_cnt);
}
- if (outer_tun_reject)
- return BNXT_TF_RC_ERROR;
- else if (cache_inner_tun_flow)
- return ulp_post_process_cache_inner_tun_flow(params, tun_entry);
- else if (outer_tun_flow)
- return ulp_post_process_outer_tun_flow(params, tun_entry,
- tun_idx);
- else if (inner_tun_flow)
- return ulp_post_process_inner_tun_flow(params, tun_entry);
- else
- return BNXT_TF_RC_NORMAL;
-}
+ *tun_idx = first_free_entry;
+ *tun_entry = &tun_tbl[first_free_entry];
+ tun_tbl[first_free_entry].t_dst_ip_valid = true;
-void
-ulp_tun_tbl_init(struct bnxt_tun_cache_entry *tun_tbl)
-{
- struct ulp_per_port_flow_info *flow_info;
- int i, j;
+ /* Update the destination ip and mac */
+ if (use_ipv4)
+ memcpy(&tun_tbl[first_free_entry].t_dst_ip,
+ params->hdr_field[dip_idx].spec, sizeof(rte_be32_t));
+ else
+ memcpy(tun_tbl[first_free_entry].t_dst_ip6,
+ params->hdr_field[dip_idx].spec,
+ sizeof(((struct bnxt_tun_cache_entry *)
+ NULL)->t_dst_ip6));
+ memcpy(tun_tbl[first_free_entry].t_dmac,
+ params->hdr_field[dmac_idx].spec, RTE_ETHER_ADDR_LEN);
- for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {
- for (j = 0; j < RTE_MAX_ETHPORTS; j++) {
- flow_info = &tun_tbl[i].tun_flow_info[j];
- STAILQ_INIT(&flow_info->tun_i_prms_list);
- }
- }
+ return 0;
}
+/* Tunnel API to delete the tunnel entry */
void
-ulp_clear_tun_entry(struct bnxt_tun_cache_entry *tun_tbl, uint8_t tun_idx)
+ulp_tunnel_offload_entry_clear(struct bnxt_tun_cache_entry *tun_tbl,
+ uint8_t tun_idx)
{
- struct ulp_rte_parser_params *inner_params;
- struct ulp_per_port_flow_info *flow_info;
- int j;
-
- for (j = 0; j < RTE_MAX_ETHPORTS; j++) {
- flow_info = &tun_tbl[tun_idx].tun_flow_info[j];
- STAILQ_FOREACH(inner_params,
- &flow_info->tun_i_prms_list,
- next) {
- STAILQ_REMOVE(&flow_info->tun_i_prms_list,
- inner_params,
- ulp_rte_parser_params, next);
- rte_free(inner_params);
- }
- }
-
- memset(&tun_tbl[tun_idx], 0,
- sizeof(struct bnxt_tun_cache_entry));
-
- for (j = 0; j < RTE_MAX_ETHPORTS; j++) {
- flow_info = &tun_tbl[tun_idx].tun_flow_info[j];
- STAILQ_INIT(&flow_info->tun_i_prms_list);
- }
+ memset(&tun_tbl[tun_idx], 0, sizeof(struct bnxt_tun_cache_entry));
}
-static bool
-ulp_chk_and_rem_tun_i_flow(struct bnxt_tun_cache_entry *tun_entry,
- struct ulp_per_port_flow_info *flow_info,
- uint32_t fid)
+/* Tunnel API to perform tunnel offload process when there is F1/F2 flows */
+int32_t
+ulp_tunnel_offload_process(struct ulp_rte_parser_params *params)
{
- struct ulp_rte_parser_params *inner_params;
- int j;
-
- STAILQ_FOREACH(inner_params,
- &flow_info->tun_i_prms_list,
- next) {
- if (inner_params->fid == fid) {
- STAILQ_REMOVE(&flow_info->tun_i_prms_list,
- inner_params,
- ulp_rte_parser_params,
- next);
- rte_free(inner_params);
- flow_info->tun_i_cnt--;
- /* When a dpdk application offloads a duplicate
- * tunnel inner flow on a port that it is not
- * destined to, there won't be a tunnel outer flow
- * associated with these duplicate tunnel inner flows.
- * So, when the last tunnel inner flow ages out, the
- * driver has to clear the tunnel entry, otherwise
- * the tunnel entry cannot be reused.
- */
- if (!flow_info->tun_i_cnt &&
- flow_info->state != BNXT_ULP_FLOW_STATE_TUN_O_OFFLD) {
- memset(tun_entry, 0,
- sizeof(struct bnxt_tun_cache_entry));
- for (j = 0; j < RTE_MAX_ETHPORTS; j++)
- STAILQ_INIT(&flow_info->tun_i_prms_list);
- }
- return true;
- }
- }
+ struct bnxt_tun_cache_entry *tun_entry;
+ uint16_t tun_idx;
+ int32_t rc = BNXT_TF_RC_SUCCESS;
- return false;
-}
+ /* Perform the tunnel offload only for F1 and F2 flows */
+ if (!ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
+ BNXT_ULP_HDR_BIT_F1) &&
+ !ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
+ BNXT_ULP_HDR_BIT_F2))
+ return rc;
-/* When a dpdk application offloads the same tunnel inner flow
- * on all the uplink ports, a tunnel inner flow entry is cached
- * even if it is not for the right uplink port. Such tunnel
- * inner flows will eventually get aged out as there won't be
- * any traffic on these ports. When such a flow destroy is
- * called, cleanup the tunnel inner flow entry.
- */
-void
-ulp_clear_tun_inner_entry(struct bnxt_tun_cache_entry *tun_tbl, uint32_t fid)
-{
- struct ulp_per_port_flow_info *flow_info;
- int i, j;
+ /* search for the tunnel entry if not found create one */
+ rc = ulp_get_tun_entry(params, &tun_entry, &tun_idx);
+ if (rc == BNXT_TF_RC_ERROR)
+ return rc;
- for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {
- if (!tun_tbl[i].t_dst_ip_valid)
- continue;
- for (j = 0; j < RTE_MAX_ETHPORTS; j++) {
- flow_info = &tun_tbl[i].tun_flow_info[j];
- if (ulp_chk_and_rem_tun_i_flow(&tun_tbl[i],
- flow_info, fid) == true)
- return;
- }
+ /* Tunnel offload for the outer Tunnel flow */
+ if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
+ BNXT_ULP_HDR_BIT_F1)) {
+ /* Reset the JUMP action bit in the action bitmap as we don't
+ * offload this action.
+ */
+ ULP_BITMAP_RESET(params->act_bitmap.bits,
+ BNXT_ULP_ACT_BIT_JUMP);
+ params->parent_flow = true;
+ params->tun_idx = tun_idx;
+ tun_entry->outer_tun_flow_id = params->fid;
+ } else if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
+ BNXT_ULP_HDR_BIT_F2)) {
+ ULP_BITMAP_RESET(params->hdr_bitmap.bits,
+ BNXT_ULP_HDR_BIT_F2);
+ /* add the vxlan decap action for F2 flows */
+ ULP_BITMAP_SET(params->act_bitmap.bits,
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP);
+ params->child_flow = true;
+ params->tun_idx = tun_idx;
+ params->parent_flow = false;
}
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_TUNNEL_ID, tun_idx);
+ return rc;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.h b/drivers/net/bnxt/tf_ulp/ulp_tun.h
index 898071bfe7..0fc2ac39d1 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_tun.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_tun.h
@@ -8,7 +8,6 @@
#include <inttypes.h>
#include <stdbool.h>
-#include <sys/queue.h>
#include "rte_version.h"
#include "rte_ethdev.h"
@@ -16,60 +15,6 @@
#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
-#define BNXT_OUTER_TUN_FLOW(l3_tun, params) \
- ((l3_tun) && \
- ULP_BITMAP_ISSET((params)->act_bitmap.bits, \
- BNXT_ULP_ACT_BIT_JUMP))
-#define BNXT_INNER_TUN_SIGNATURE(l3_tun, l3_tun_decap, params) \
- ((l3_tun) && (l3_tun_decap) && \
- !ULP_BITMAP_ISSET((params)->hdr_bitmap.bits, \
- BNXT_ULP_HDR_BIT_O_ETH))
-
-#define BNXT_CACHE_INNER_TUN_FLOW(state, inner_tun_sig) \
- ((state) == BNXT_ULP_FLOW_STATE_NORMAL && (inner_tun_sig))
-#define BNXT_INNER_TUN_FLOW(state, inner_tun_sig) \
- ((state) == BNXT_ULP_FLOW_STATE_TUN_O_OFFLD && (inner_tun_sig))
-
-/* It is invalid to get another outer flow offload request
- * for the same tunnel, while the outer flow is already offloaded.
- */
-#define BNXT_REJECT_OUTER_TUN_FLOW(state, outer_tun_sig) \
- ((state) == BNXT_ULP_FLOW_STATE_TUN_O_OFFLD && (outer_tun_sig))
-
-#define ULP_TUN_O_DMAC_HDR_FIELD_INDEX 1
-#define ULP_TUN_O_IPV4_DIP_INDEX 19
-#define ULP_TUN_O_IPV6_DIP_INDEX 17
-
-/* When a flow offload request comes the following state transitions
- * happen based on the order in which the outer & inner flow offload
- * requests arrive.
- *
- * If inner tunnel flow offload request arrives first then the flow
- * state will remain in BNXT_ULP_FLOW_STATE_NORMAL state.
- * The following outer tunnel flow offload request will change the
- * state of the flow to BNXT_ULP_FLOW_STATE_TUN_O_OFFLD from
- * BNXT_ULP_FLOW_STATE_NORMAL.
- *
- * If outer tunnel flow offload request arrives first then the flow state
- * will change from BNXT_ULP_FLOW_STATE_NORMAL to
- * BNXT_ULP_FLOW_STATE_TUN_O_OFFLD.
- *
- * Once the flow state is in BNXT_ULP_FLOW_STATE_TUN_O_OFFLD, any inner
- * tunnel flow offload requests after that point will be treated as a
- * normal flow and the tunnel flow state remains in
- * BNXT_ULP_FLOW_STATE_TUN_O_OFFLD
- */
-enum bnxt_ulp_tun_flow_state {
- BNXT_ULP_FLOW_STATE_NORMAL = 0,
- BNXT_ULP_FLOW_STATE_TUN_O_OFFLD,
-};
-
-struct ulp_per_port_flow_info {
- enum bnxt_ulp_tun_flow_state state;
- uint32_t tun_i_cnt;
- STAILQ_HEAD(, ulp_rte_parser_params) tun_i_prms_list;
-};
-
struct bnxt_tun_cache_entry {
bool t_dst_ip_valid;
uint8_t t_dmac[RTE_ETHER_ADDR_LEN];
@@ -78,17 +23,39 @@ struct bnxt_tun_cache_entry {
uint8_t t_dst_ip6[16];
};
uint32_t outer_tun_flow_id;
- uint16_t outer_tun_rej_cnt;
- struct ulp_per_port_flow_info tun_flow_info[RTE_MAX_ETHPORTS];
};
-void
-ulp_tun_tbl_init(struct bnxt_tun_cache_entry *tun_tbl);
+struct bnxt_flow_app_tun_ent {
+ struct rte_flow_tunnel app_tunnel;
+ uint32_t tun_id;
+ uint32_t ref_cnt;
+ struct rte_flow_action action;
+ struct rte_flow_item item;
+};
+
+int32_t
+ulp_app_tun_search_entry(struct bnxt_ulp_context *ulp_ctx,
+ struct rte_flow_tunnel *app_tunnel,
+ struct bnxt_flow_app_tun_ent **tun_entry);
void
-ulp_clear_tun_entry(struct bnxt_tun_cache_entry *tun_tbl, uint8_t tun_idx);
+ulp_app_tun_entry_delete(struct bnxt_flow_app_tun_ent *tun_entry);
+int32_t
+ulp_app_tun_entry_set_decap_action(struct bnxt_flow_app_tun_ent *tun_entry);
+
+int32_t
+ulp_app_tun_entry_set_decap_item(struct bnxt_flow_app_tun_ent *tun_entry);
+
+struct bnxt_flow_app_tun_ent *
+ulp_app_tun_match_entry(struct bnxt_ulp_context *ulp_ctx, const void *ctx);
+
+/* Tunnel API to delete the tunnel entry */
void
-ulp_clear_tun_inner_entry(struct bnxt_tun_cache_entry *tun_tbl, uint32_t fid);
+ulp_tunnel_offload_entry_clear(struct bnxt_tun_cache_entry *tun_tbl,
+ uint8_t tun_idx);
+
+int32_t
+ulp_tunnel_offload_process(struct ulp_rte_parser_params *params);
#endif
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH 07/14] net/bnxt: add support for dynamic encap action
2021-09-01 14:24 [dpdk-dev] [PATCH 00/14] enhancements to host based flow table management Venkat Duvvuru
` (5 preceding siblings ...)
2021-09-01 14:24 ` [dpdk-dev] [PATCH 06/14] net/bnxt: add support for tunnel offloads Venkat Duvvuru
@ 2021-09-01 14:24 ` Venkat Duvvuru
2021-09-01 14:24 ` [dpdk-dev] [PATCH 08/14] net/bnxt: add wild card TCAM byte order for Thor Venkat Duvvuru
` (7 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-01 14:24 UTC (permalink / raw)
To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
The encapsulation record processing is enhanced to handle data
dynamically. Different combinations of VXLAN encapsulation using
no VLAN or single or double VLAN can be supported and also supports
both IPv4 and IPv6 versions.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
---
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 25 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 2 +
.../generic_templates/ulp_template_db_enum.h | 44 +-
.../generic_templates/ulp_template_db_tbl.c | 8 +-
.../ulp_template_db_thor_act.c | 4 +-
.../ulp_template_db_thor_class.c | 46 +-
.../ulp_template_db_wh_plus_act.c | 1700 ++++++++++++-----
.../ulp_template_db_wh_plus_class.c | 222 +--
drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 6 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 2 +-
drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 152 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.h | 4 +
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 337 ++--
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 2 +
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 10 +-
drivers/net/bnxt/tf_ulp/ulp_utils.c | 73 +-
drivers/net/bnxt/tf_ulp/ulp_utils.h | 27 +-
18 files changed, 1717 insertions(+), 949 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index dfafd9ff5b..3b86410fb1 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -830,13 +830,12 @@ ulp_ctx_init(struct bnxt *bp,
goto error_deinit;
}
- /* TODO: For now we are overriding to APP:1 on this branch*/
- bp->app_id = 1;
rc = bnxt_ulp_cntxt_app_id_set(bp->ulp_ctx, bp->app_id);
if (rc) {
BNXT_TF_DBG(ERR, "Unable to set app_id for ULP init.\n");
goto error_deinit;
}
+ BNXT_TF_DBG(DEBUG, "Ulp initialized with app id %d\n", bp->app_id);
rc = bnxt_ulp_cntxt_app_caps_init(bp->ulp_ctx, bp->app_id, devid);
if (rc) {
@@ -1393,13 +1392,17 @@ bnxt_ulp_port_init(struct bnxt *bp)
uint32_t ulp_flags;
int32_t rc = 0;
- if (!bp || !BNXT_TRUFLOW_EN(bp))
- return rc;
-
if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
BNXT_TF_DBG(ERR,
"Skip ulp init for port: %d, not a TVF or PF\n",
- bp->eth_dev->data->port_id);
+ bp->eth_dev->data->port_id);
+ return rc;
+ }
+
+ if (!BNXT_TRUFLOW_EN(bp)) {
+ BNXT_TF_DBG(ERR,
+ "Skip ulp init for port: %d, truflow is not enabled\n",
+ bp->eth_dev->data->port_id);
return rc;
}
@@ -1520,9 +1523,6 @@ bnxt_ulp_port_deinit(struct bnxt *bp)
struct rte_pci_device *pci_dev;
struct rte_pci_addr *pci_addr;
- if (!BNXT_TRUFLOW_EN(bp))
- return;
-
if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
BNXT_TF_DBG(ERR,
"Skip ULP deinit port:%d, not a TVF or PF\n",
@@ -1530,6 +1530,13 @@ bnxt_ulp_port_deinit(struct bnxt *bp)
return;
}
+ if (!BNXT_TRUFLOW_EN(bp)) {
+ BNXT_TF_DBG(ERR,
+ "Skip ULP deinit for port:%d, truflow is not enabled\n",
+ bp->eth_dev->data->port_id);
+ return;
+ }
+
if (!bp->ulp_ctx) {
BNXT_TF_DBG(DEBUG, "ulp ctx already de-allocated\n");
return;
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
index 3daf5942e8..413e4c3b26 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
@@ -96,7 +96,9 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms,
mapper_cparms->act_tid = params->act_tmpl;
mapper_cparms->func_id = params->func_id;
mapper_cparms->hdr_bitmap = ¶ms->hdr_bitmap;
+ mapper_cparms->enc_hdr_bitmap = ¶ms->enc_hdr_bitmap;
mapper_cparms->hdr_field = params->hdr_field;
+ mapper_cparms->enc_field = params->enc_field;
mapper_cparms->comp_fld = params->comp_fld;
mapper_cparms->act = ¶ms->act_bitmap;
mapper_cparms->act_prop = ¶ms->act_prop;
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
index e55d0923a5..9010d9a749 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 20 11:56:39 2021 */
+/* date: Thu May 27 17:35:19 2021 */
#ifndef ULP_TEMPLATE_DB_H_
#define ULP_TEMPLATE_DB_H_
@@ -41,7 +41,7 @@
#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 89
#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 600
#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 26
-#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 619
+#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 618
#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 49
#define ULP_THOR_CLASS_TMPL_LIST_SIZE 6
#define ULP_THOR_CLASS_TBL_LIST_SIZE 33
@@ -53,7 +53,7 @@
#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 35
#define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2
#define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 1
-#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 512
+#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 527
#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 39
#define ULP_THOR_ACT_TMPL_LIST_SIZE 7
#define ULP_THOR_ACT_TBL_LIST_SIZE 2
@@ -229,7 +229,9 @@ enum bnxt_ulp_cond_opc {
BNXT_ULP_COND_OPC_ACT_PAT_MATCH = 11,
BNXT_ULP_COND_OPC_EXT_MEM_IS_SET = 12,
BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET = 13,
- BNXT_ULP_COND_OPC_LAST = 14
+ BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET = 14,
+ BNXT_ULP_COND_OPC_ENC_HDR_BIT_NOT_SET = 15,
+ BNXT_ULP_COND_OPC_LAST = 16
};
enum bnxt_ulp_critical_resource {
@@ -257,6 +259,36 @@ enum bnxt_ulp_direction {
BNXT_ULP_DIRECTION_LAST = 2
};
+enum bnxt_ulp_enc_field {
+ BNXT_ULP_ENC_FIELD_ETH_DMAC = 0,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC = 1,
+ BNXT_ULP_ENC_FIELD_ETH_TYPE = 2,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TCI = 3,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TYPE = 4,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TCI = 5,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TYPE = 6,
+ BNXT_ULP_ENC_FIELD_IPV4_IHL = 7,
+ BNXT_ULP_ENC_FIELD_IPV4_TOS = 8,
+ BNXT_ULP_ENC_FIELD_IPV4_PKT_ID = 9,
+ BNXT_ULP_ENC_FIELD_IPV4_FRAG = 10,
+ BNXT_ULP_ENC_FIELD_IPV4_TTL = 11,
+ BNXT_ULP_ENC_FIELD_IPV4_PROTO = 12,
+ BNXT_ULP_ENC_FIELD_IPV4_SADDR = 13,
+ BNXT_ULP_ENC_FIELD_IPV4_DADDR = 14,
+ BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW = 15,
+ BNXT_ULP_ENC_FIELD_IPV6_PROTO = 16,
+ BNXT_ULP_ENC_FIELD_IPV6_TTL = 17,
+ BNXT_ULP_ENC_FIELD_IPV6_SADDR = 18,
+ BNXT_ULP_ENC_FIELD_IPV6_DADDR = 19,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT = 20,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT = 21,
+ BNXT_ULP_ENC_FIELD_VXLAN_FLAGS = 22,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 = 23,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI = 24,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 = 25,
+ BNXT_ULP_ENC_FIELD_LAST = 26
+};
+
enum bnxt_ulp_fdb_opc {
BNXT_ULP_FDB_OPC_PUSH_FID = 0,
BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE = 1,
@@ -304,7 +336,9 @@ enum bnxt_ulp_field_src {
BNXT_ULP_FIELD_SRC_SKIP = 13,
BNXT_ULP_FIELD_SRC_REJECT = 14,
BNXT_ULP_FIELD_SRC_PORT_TABLE = 15,
- BNXT_ULP_FIELD_SRC_LAST = 16
+ BNXT_ULP_FIELD_SRC_ENC_HDR_BIT = 16,
+ BNXT_ULP_FIELD_SRC_ENC_FIELD = 17,
+ BNXT_ULP_FIELD_SRC_LAST = 18
};
enum bnxt_ulp_func_opc {
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
index 58b4dba63c..b5bce6f4c7 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
@@ -198,7 +198,9 @@ const struct bnxt_ulp_template_device_tbls ulp_template_thor_tbls[] = {
struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
[BNXT_ULP_DEVICE_ID_WH_PLUS] = {
.description = "Whitney_Plus",
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .encap_byte_order = BNXT_ULP_BYTE_ORDER_BE,
.encap_byte_swap = 1,
.int_flow_db_num_entries = 16384,
.ext_flow_db_num_entries = 32768,
@@ -218,7 +220,9 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
},
[BNXT_ULP_DEVICE_ID_THOR] = {
.description = "Thor",
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .encap_byte_order = BNXT_ULP_BYTE_ORDER_BE,
.encap_byte_swap = 1,
.int_flow_db_num_entries = 16384,
.ext_flow_db_num_entries = 32768,
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
index ce5a70b0c5..9faf25aaf0 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 13 18:15:56 2021 */
+/* date: Wed May 26 15:11:34 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -41,7 +41,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 0,
.result_bit_size = 64,
.result_num_fields = 1
@@ -62,7 +61,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 1,
.result_bit_size = 128,
.result_num_fields = 17
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
index d20c4197fa..ea9b9773a5 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 20 11:56:39 2021 */
+/* date: Wed May 26 15:11:34 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -59,7 +59,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 0,
.blob_key_bit_size = 10,
.key_bit_size = 10,
@@ -82,7 +81,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 1,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -104,7 +102,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 2,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -122,8 +119,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_start_idx = 5,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 1, , table: l2_cntxt_tcam.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -141,7 +137,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 7,
.blob_key_bit_size = 213,
.key_bit_size = 213,
@@ -166,7 +161,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 28,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -189,7 +183,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 33,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -207,8 +200,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_start_idx = 6,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 1, , table: fkb_select.l3_l4_wm */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -223,7 +215,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 10,
.result_bit_size = 106,
.result_num_fields = 106
@@ -246,7 +237,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 36,
.blob_key_bit_size = 94,
.key_bit_size = 94,
@@ -271,7 +261,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 79,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -297,7 +286,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_BE,
.key_start_idx = 82,
.blob_key_bit_size = 0,
.key_bit_size = 0,
@@ -322,7 +310,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 136,
.result_bit_size = 128,
.result_num_fields = 17
@@ -341,7 +328,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 196,
.blob_key_bit_size = 10,
.key_bit_size = 10,
@@ -364,7 +350,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 197,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -382,8 +367,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_start_idx = 9,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -403,7 +387,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 198,
.blob_key_bit_size = 213,
.key_bit_size = 213,
@@ -428,7 +411,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 219,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -450,7 +432,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 168,
.result_bit_size = 32,
.result_num_fields = 1
@@ -468,7 +449,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 169,
.result_bit_size = 32,
.result_num_fields = 1
@@ -482,8 +462,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 10,
.cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
{ /* class_tid: 4, , table: int_full_act_record.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -501,7 +480,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 170,
.result_bit_size = 128,
.result_num_fields = 17,
@@ -521,7 +499,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 220,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -539,8 +516,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_start_idx = 11,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -558,7 +534,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 221,
.blob_key_bit_size = 213,
.key_bit_size = 213,
@@ -582,7 +557,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 193,
.result_bit_size = 32,
.result_num_fields = 1
@@ -600,7 +574,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 194,
.result_bit_size = 32,
.result_num_fields = 1
@@ -621,7 +594,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 195,
.result_bit_size = 128,
.result_num_fields = 17,
@@ -640,7 +612,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 212,
.result_bit_size = 32,
.result_num_fields = 1
@@ -658,7 +629,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 213,
.result_bit_size = 32,
.result_num_fields = 1
@@ -679,7 +649,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 214,
.result_bit_size = 128,
.result_num_fields = 17,
@@ -701,7 +670,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .record_size = 16,
.result_start_idx = 231,
.result_bit_size = 0,
.result_num_fields = 0,
@@ -723,7 +692,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 242,
.result_bit_size = 128,
.result_num_fields = 17
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
index de924fe81a..578ede8bba 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Mon May 17 15:54:03 2021 */
+/* date: Tue Jun 1 16:05:30 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -90,7 +90,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 0,
.blob_key_bit_size = 1,
.key_bit_size = 1,
@@ -114,14 +113,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 0,
.result_bit_size = 64,
.result_num_fields = 1
},
{ /* act_tid: 1, , table: int_vtag_encap_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
.direction = TF_DIR_RX,
@@ -135,11 +133,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .record_size = 8,
.result_start_idx = 1,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 1, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -157,8 +155,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 13,
+ .result_start_idx = 12,
.result_bit_size = 128,
.result_num_fields = 26,
.encap_num_fields = 0
@@ -179,11 +176,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 39,
+ .result_start_idx = 38,
.result_bit_size = 128,
.result_num_fields = 26,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 2, , table: control.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
@@ -195,8 +191,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_start_idx = 14,
.cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* act_tid: 2, , table: mirror_tbl.alloc */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -215,8 +210,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 77,
+ .result_start_idx = 75,
.result_bit_size = 32,
.result_num_fields = 6
},
@@ -237,8 +231,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 83,
+ .result_start_idx = 81,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -259,8 +252,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 84,
+ .result_start_idx = 82,
.result_bit_size = 128,
.result_num_fields = 26,
.encap_num_fields = 0
@@ -282,11 +274,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 110,
+ .result_start_idx = 108,
.result_bit_size = 128,
.result_num_fields = 26,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 2, , table: mirror_tbl.wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -304,8 +295,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 148,
+ .result_start_idx = 145,
.result_bit_size = 32,
.result_num_fields = 6
},
@@ -324,12 +314,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 1,
.blob_key_bit_size = 1,
.key_bit_size = 1,
.key_num_fields = 1,
- .result_start_idx = 154,
+ .result_start_idx = 151,
.result_bit_size = 34,
.result_num_fields = 2
},
@@ -348,8 +337,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 156,
+ .result_start_idx = 153,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -368,8 +356,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 157,
+ .result_start_idx = 154,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -388,8 +375,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 158,
+ .result_start_idx = 155,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -408,11 +394,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 159,
+ .record_size = 16,
+ .result_start_idx = 156,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 3, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -429,8 +415,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 171,
+ .result_start_idx = 167,
.result_bit_size = 128,
.result_num_fields = 26
},
@@ -449,11 +434,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 197,
+ .result_start_idx = 193,
.result_bit_size = 128,
.result_num_fields = 26,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 4, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -470,8 +454,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 235,
+ .result_start_idx = 230,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -490,11 +473,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 236,
+ .record_size = 8,
+ .result_start_idx = 231,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 4, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -511,8 +494,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 248,
+ .result_start_idx = 242,
.result_bit_size = 128,
.result_num_fields = 26
},
@@ -531,11 +513,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 274,
+ .result_start_idx = 268,
.result_bit_size = 128,
.result_num_fields = 26,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 4, , table: ext_full_act_record.one_tag */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -552,11 +533,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 312,
+ .result_start_idx = 305,
.result_bit_size = 128,
.result_num_fields = 26,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 5, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -573,8 +553,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 350,
+ .result_start_idx = 342,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -593,8 +572,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 351,
+ .result_start_idx = 343,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -613,8 +591,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 352,
+ .result_start_idx = 344,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -633,11 +610,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 353,
+ .record_size = 16,
+ .result_start_idx = 345,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 5, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -654,8 +631,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 365,
+ .result_start_idx = 356,
.result_bit_size = 128,
.result_num_fields = 26
},
@@ -674,11 +650,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 391,
+ .result_start_idx = 382,
.result_bit_size = 128,
.result_num_fields = 26,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 6, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -695,8 +670,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 429,
+ .result_start_idx = 419,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -715,11 +689,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 430,
+ .record_size = 16,
+ .result_start_idx = 420,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 3
+ .encap_num_fields = 2
},
{ /* act_tid: 6, , table: sp_smac_ipv6.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -736,11 +710,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 433,
+ .record_size = 24,
+ .result_start_idx = 422,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 3
+ .encap_num_fields = 2
},
{ /* act_tid: 6, , table: int_tun_encap_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -757,11 +731,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 436,
+ .record_size = 64,
+ .result_start_idx = 424,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 12
+ .encap_num_fields = 30
},
{ /* act_tid: 6, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -778,8 +752,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 448,
+ .result_start_idx = 454,
.result_bit_size = 128,
.result_num_fields = 26
},
@@ -798,11 +771,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 474,
+ .result_start_idx = 480,
.result_bit_size = 128,
.result_num_fields = 26,
- .encap_num_fields = 12
+ .encap_num_fields = 30
}
};
@@ -1033,22 +1005,26 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
},
/* act_tid: 1, , table: int_vtag_encap_record.0 */
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
},
{
.description = "ecv_l2_en",
@@ -1057,26 +1033,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "vtag_tpid",
@@ -1088,13 +1060,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
},
{
.description = "vtag_de",
@@ -1103,19 +1075,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
- },
- {
- .description = "spare",
- .field_bit_size = 80,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
},
/* act_tid: 1, , table: int_full_act_record.0 */
{
@@ -1628,20 +1594,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -1649,25 +1617,23 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.description = "ecv_l2_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_L2_EN_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -1678,8 +1644,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -1690,14 +1656,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 0,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2105,20 +2065,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2126,25 +2088,23 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.description = "ecv_l2_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_L2_EN_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2155,8 +2115,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2167,14 +2127,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 0,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2268,20 +2222,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
},
/* act_tid: 3, , table: int_encap_mac_record.0 */
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2294,24 +2250,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
ULP_WP_SYM_ECV_L2_EN_YES}
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "vtag_tpid",
@@ -2320,8 +2274,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2332,14 +2286,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 80,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2806,20 +2754,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2827,25 +2777,23 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.description = "ecv_l2_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_L2_EN_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2856,8 +2804,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2868,14 +2816,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 0,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2888,23 +2830,27 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
},
/* act_tid: 4, , table: int_vtag_encap_record.0 */
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
+ },
{
.description = "ecv_l2_en",
.field_bit_size = 1,
@@ -2912,26 +2858,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "vtag_tpid",
@@ -2943,13 +2885,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
},
{
.description = "vtag_de",
@@ -2958,19 +2900,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
- },
- {
- .description = "spare",
- .field_bit_size = 80,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
},
/* act_tid: 4, , table: int_full_act_record.0 */
{
@@ -3350,20 +3286,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -3371,25 +3309,23 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.description = "ecv_l2_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_L2_EN_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -3400,8 +3336,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -3412,14 +3348,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 0,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -3620,22 +3550,26 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
},
{
.description = "ecv_l2_en",
@@ -3644,26 +3578,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "vtag_tpid",
@@ -3675,13 +3605,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
},
{
.description = "vtag_de",
@@ -3690,19 +3620,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
- },
- {
- .description = "spare",
- .field_bit_size = 0,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
},
/* act_tid: 5, , table: int_flow_counter_tbl.0 */
{
@@ -3733,20 +3657,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
},
/* act_tid: 5, , table: int_encap_mac_record.dummy */
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -3759,24 +3685,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
ULP_WP_SYM_ECV_L2_EN_YES}
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "vtag_tpid",
@@ -3785,8 +3709,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -3797,14 +3721,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 80,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -4271,20 +4189,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -4292,25 +4212,23 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.description = "ecv_l2_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_L2_EN_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -4321,8 +4239,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -4333,14 +4251,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 0,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -4356,76 +4268,62 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.description = "smac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC & 0xff}
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
},
{
.description = "ipv4_src_addr",
.field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC & 0xff}
- },
- {
- .description = "reserved",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}
},
/* act_tid: 6, , table: sp_smac_ipv6.0 */
{
.description = "smac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC & 0xff}
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
},
{
.description = "ipv6_src_addr",
.field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC & 0xff}
- },
- {
- .description = "reserved",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ENC_FIELD_IPV6_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_SADDR & 0xff}
},
/* act_tid: 6, , table: int_tun_encap_record.0 */
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ULP_WP_SYM_ECV_TUN_TYPE_VXLAN}
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
},
{
.description = "ecv_l2_en",
@@ -4433,81 +4331,478 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ ULP_WP_SYM_ECV_L2_EN_YES}
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM}
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ ULP_WP_SYM_ECV_TUN_TYPE_VXLAN}
},
{
- .description = "encap_l2_dmac",
+ .description = "enc_eth_dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC & 0xff}
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
},
{
- .description = "encap_vtag",
- .field_bit_size = 0,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ,
+ .description = "enc_o_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_o_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_ihl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_tos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_pkt_id",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_frag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_daddr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_vtc",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_zero",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG & 0xff,
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ZERO,
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
- .description = "encap_ip",
- .field_bit_size = 0,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ,
+ .description = "enc_ipv6_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_daddr",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_vxlan_flags",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_IP & 0xff,
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
- .description = "encap_udp",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .description = "enc_vxlan_rsvd0",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
- .description = "encap_tun",
- .field_bit_size = 0,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ,
+ .description = "enc_vxlan_vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN & 0xff,
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_vxlan_rsvd1",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
/* act_tid: 6, , table: int_full_act_record.0 */
{
@@ -4857,29 +5152,27 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ULP_WP_SYM_ECV_TUN_TYPE_VXLAN}
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
},
{
.description = "ecv_l2_en",
@@ -4887,79 +5180,478 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ ULP_WP_SYM_ECV_L2_EN_YES}
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM}
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ ULP_WP_SYM_ECV_TUN_TYPE_VXLAN}
},
{
- .description = "encap_l2_dmac",
+ .description = "enc_eth_dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC & 0xff}
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
},
{
- .description = "encap_vtag",
- .field_bit_size = 0,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ,
+ .description = "enc_o_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_o_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_ihl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_tos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_pkt_id",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_frag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_daddr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_vtc",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_zero",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG & 0xff,
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ZERO,
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
- .description = "encap_ip",
- .field_bit_size = 0,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ,
+ .description = "enc_ipv6_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_daddr",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_vxlan_flags",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_vxlan_rsvd0",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_IP & 0xff,
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
- .description = "encap_udp",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .description = "enc_vxlan_vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
- .description = "encap_tun",
- .field_bit_size = 80,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .description = "enc_vxlan_rsvd1",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
index 7b6ee03a4b..7203dcf1fb 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Mon May 17 15:54:03 2021 */
+/* date: Fri May 28 16:46:46 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -80,7 +80,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 0,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -102,7 +101,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 1,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -120,8 +118,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 2,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 1, , table: l2_cntxt_tcam.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -139,7 +136,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 6,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -164,7 +160,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 19,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -188,7 +183,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 24,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -206,8 +200,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 3,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 1, , table: control.2 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
@@ -225,8 +218,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
.func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
.func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
- .func_dst_opr = BNXT_ULP_RF_IDX_CC },
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
},
{ /* class_tid: 1, , table: profile_tcam.ipv4 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -244,7 +236,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 27,
.blob_key_bit_size = 81,
.key_bit_size = 81,
@@ -271,7 +262,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 70,
.blob_key_bit_size = 81,
.key_bit_size = 81,
@@ -298,7 +288,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 113,
.blob_key_bit_size = 81,
.key_bit_size = 81,
@@ -324,7 +313,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 156,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -346,7 +334,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 159,
.blob_key_bit_size = 176,
.key_bit_size = 176,
@@ -368,7 +355,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 169,
.blob_key_bit_size = 448,
.key_bit_size = 448,
@@ -390,7 +376,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 179,
.blob_key_bit_size = 416,
.key_bit_size = 416,
@@ -412,7 +397,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 190,
.blob_key_bit_size = 448,
.key_bit_size = 448,
@@ -434,7 +418,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 201,
.blob_key_bit_size = 200,
.key_bit_size = 200,
@@ -456,7 +439,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 212,
.blob_key_bit_size = 448,
.key_bit_size = 448,
@@ -479,7 +461,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 223,
.blob_key_bit_size = 16,
.key_bit_size = 16,
@@ -497,8 +478,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 25,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -516,7 +496,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 225,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -541,7 +520,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 238,
.blob_key_bit_size = 16,
.key_bit_size = 16,
@@ -559,8 +537,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 26,
.cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
{ /* class_tid: 2, , table: mac_addr_cache.rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
@@ -576,7 +553,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 240,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -594,8 +570,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 27,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 2, , table: l2_cntxt_tcam.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -613,7 +588,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 245,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -638,7 +612,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 258,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -662,7 +635,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 263,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -680,8 +652,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 28,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 2, , table: profile_tcam.f2 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -701,7 +672,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_operand = 1,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 266,
.blob_key_bit_size = 81,
.key_bit_size = 81,
@@ -725,7 +695,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 309,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -747,7 +716,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 312,
.blob_key_bit_size = 112,
.key_bit_size = 112,
@@ -769,7 +737,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 320,
.blob_key_bit_size = 448,
.key_bit_size = 448,
@@ -792,7 +759,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 328,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -814,7 +780,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 329,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -832,8 +797,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 32,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 3, , table: l2_cntxt_tcam.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -851,7 +815,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 334,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -876,7 +839,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 347,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -899,7 +861,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 352,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -917,8 +878,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 33,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 3, , table: control.conflict_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
@@ -936,8 +896,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
.func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
.func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
- .func_dst_opr = BNXT_ULP_RF_IDX_CC },
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
},
{ /* class_tid: 3, , table: profile_tcam.ipv4 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -955,7 +914,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 355,
.blob_key_bit_size = 81,
.key_bit_size = 81,
@@ -982,7 +940,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 398,
.blob_key_bit_size = 81,
.key_bit_size = 81,
@@ -1007,7 +964,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 441,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -1029,7 +985,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 444,
.blob_key_bit_size = 176,
.key_bit_size = 176,
@@ -1051,7 +1006,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 454,
.blob_key_bit_size = 448,
.key_bit_size = 448,
@@ -1073,7 +1027,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 464,
.blob_key_bit_size = 416,
.key_bit_size = 416,
@@ -1095,7 +1048,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 475,
.blob_key_bit_size = 448,
.key_bit_size = 448,
@@ -1120,7 +1072,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 292,
.result_bit_size = 128,
.result_num_fields = 26
@@ -1139,7 +1090,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 486,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1157,8 +1107,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 41,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1178,7 +1127,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 487,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -1203,7 +1151,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 500,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1225,7 +1172,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 335,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1243,7 +1189,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 336,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1261,7 +1206,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 337,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1275,8 +1219,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 42,
.cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
{ /* class_tid: 4, , table: int_full_act_record.egr_vfr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1294,7 +1237,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 338,
.result_bit_size = 128,
.result_num_fields = 26,
@@ -1314,7 +1256,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 501,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1332,8 +1273,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 43,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 4, , table: l2_cntxt_tcam_bypass.egr_vfr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1351,7 +1291,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 502,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -1376,7 +1315,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 515,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1399,7 +1337,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 516,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1417,8 +1354,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 44,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1436,7 +1372,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 517,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -1461,7 +1396,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 530,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1486,7 +1420,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 398,
.result_bit_size = 128,
.result_num_fields = 26,
@@ -1505,7 +1438,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 424,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1523,7 +1455,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 425,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1541,7 +1472,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 426,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1562,7 +1492,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 427,
.result_bit_size = 128,
.result_num_fields = 26,
@@ -1582,7 +1511,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 531,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1600,8 +1528,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 47,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1619,7 +1546,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 532,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -1644,7 +1570,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 545,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1666,7 +1591,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 470,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1684,7 +1608,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 471,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1702,7 +1625,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 472,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1723,7 +1645,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 473,
.result_bit_size = 128,
.result_num_fields = 26,
@@ -1746,7 +1667,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 546,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -1771,7 +1691,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 559,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1789,8 +1708,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 48,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_egr0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1808,7 +1726,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 560,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -1833,7 +1750,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 573,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1858,11 +1774,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .record_size = 8,
.result_start_idx = 529,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1880,8 +1796,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 541,
+ .result_start_idx = 540,
.result_bit_size = 128,
.result_num_fields = 26
},
@@ -1901,8 +1816,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 567,
+ .result_start_idx = 566,
.result_bit_size = 128,
.result_num_fields = 26
},
@@ -1923,12 +1837,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 574,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 593,
+ .result_start_idx = 592,
.result_bit_size = 64,
.result_num_fields = 13,
.ident_start_idx = 26,
@@ -1951,12 +1864,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 587,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 606,
+ .result_start_idx = 605,
.result_bit_size = 64,
.result_num_fields = 13,
.ident_start_idx = 26,
@@ -2522,17 +2434,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -6207,17 +6115,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -8046,17 +7950,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -16093,22 +15993,26 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
},
/* class_tid: 5, , table: int_vtag_encap_record.vfr_egr0 */
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
},
{
.description = "ecv_l2_en",
@@ -16117,26 +16021,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "vtag_tpid",
@@ -16148,13 +16048,10 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
0x00}
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "vtag_de",
@@ -16163,16 +16060,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 80,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
},
/* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
{
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
index 039c9c2a6b..1cb52e9bfa 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
@@ -116,7 +116,7 @@ ulp_flow_db_resource_func_get(struct ulp_fdb_resource_info *res_info)
func = (((res_info->nxt_resource_idx & ULP_FLOW_DB_RES_FUNC_MASK) >>
ULP_FLOW_DB_RES_FUNC_BITS) << ULP_FLOW_DB_RES_FUNC_UPPER);
- /* The reource func is split into upper and lower */
+ /* The resource func is split into upper and lower */
if (func & ULP_FLOW_DB_RES_FUNC_NEED_LOWER)
return (func | res_info->resource_func_lower);
return func;
@@ -622,7 +622,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt,
if (params->critical_resource && fid_resource->resource_em_handle) {
BNXT_TF_DBG(DEBUG, "Ignore multiple critical resources\n");
- /* Ignore the multiple criticial resources */
+ /* Ignore the multiple critical resources */
params->critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO;
}
@@ -674,7 +674,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt,
* flow_type [in] Specify it is regular or default flow
* fid [in] The index to the flow entry
* params [in/out] The contents to be copied into params.
- * Onlythe critical_resource needs to be set by the caller.
+ * Only the critical_resource needs to be set by the caller.
*
* Returns 0 on success and negative on failure.
*/
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
index 8680ee8f65..6dbec92745 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
@@ -18,7 +18,7 @@
/*
* Structure for the flow database resource information
- * The below structure is based on the below paritions
+ * The below structure is based on the below partitions
* nxt_resource_idx = dir[31],resource_func_upper[30:28],nxt_resource_idx[27:0]
* If resource_func is EM_TBL then use resource_em_handle.
* Else the other part of the union is used and
diff --git a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
index bc5627ec5b..5f5b5d639e 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
@@ -185,7 +185,7 @@ ulp_ha_mgr_timer_cb(void *arg __rte_unused)
rc = ulp_ha_mgr_state_get(ulp_ctx, &curr_state);
if (rc) {
/*
- * This shouldn't happen, if it does, resetart the timer
+ * This shouldn't happen, if it does, reset the timer
* and try again next time.
*/
BNXT_TF_DBG(ERR, "Failed(%d) to get state.\n",
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 6d804c7ef9..2687a545f3 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -1010,7 +1010,7 @@ ulp_mapper_field_src_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
idx = tfp_be_to_cpu_16(idx);
- if (idx >= BNXT_ULP_CF_IDX_LAST || bytelen > sizeof(uint32_t)) {
+ if (idx >= BNXT_ULP_CF_IDX_LAST || bytelen > sizeof(uint64_t)) {
BNXT_TF_DBG(ERR, "comp field [%d] read oob %d\n", idx,
bytelen);
return -EINVAL;
@@ -1215,8 +1215,47 @@ ulp_mapper_field_src_process(struct bnxt_ulp_mapper_parms *parms,
BNXT_TF_DBG(ERR, "field port table failed\n");
return -EINVAL;
}
+ break;
+ case BNXT_ULP_FIELD_SRC_ENC_HDR_BIT:
+ if (!ulp_operand_read(field_opr,
+ (uint8_t *)&lregval, sizeof(uint64_t))) {
+ BNXT_TF_DBG(ERR, "Header bit read failed\n");
+ return -EINVAL;
+ }
+ lregval = tfp_be_to_cpu_64(lregval);
+ if (ULP_BITMAP_ISSET(parms->enc_hdr_bitmap->bits, lregval)) {
+ *val = mapper_fld_one;
+ *value = 1;
+ } else {
+ *val = mapper_fld_zeros;
+ }
+ break;
+ case BNXT_ULP_FIELD_SRC_ENC_FIELD:
+ if (!ulp_operand_read(field_opr,
+ (uint8_t *)&idx, sizeof(uint16_t))) {
+ BNXT_TF_DBG(ERR, "Header field read failed\n");
+ return -EINVAL;
+ }
+ idx = tfp_be_to_cpu_16(idx);
+ /* get the index from the global field list */
+ if (idx >= BNXT_ULP_ENC_FIELD_LAST) {
+ BNXT_TF_DBG(ERR, "invalid encap field tbl idx %d\n",
+ idx);
+ return -EINVAL;
+ }
+ buffer = parms->enc_field[idx].spec;
+ field_size = parms->enc_field[idx].size;
+ if (bytelen > field_size) {
+ BNXT_TF_DBG(ERR, "Encap field[%d] size small %u\n",
+ idx, field_size);
+ return -EINVAL;
+ }
+ *val = &buffer[field_size - bytelen];
+ break;
case BNXT_ULP_FIELD_SRC_SKIP:
/* do nothing */
+ *val = mapper_fld_zeros;
+ *val_len = 0;
break;
case BNXT_ULP_FIELD_SRC_REJECT:
return -EINVAL;
@@ -1270,6 +1309,8 @@ static int32_t ulp_mapper_field_blob_write(enum bnxt_ulp_field_src fld_src,
BNXT_TF_DBG(ERR, "encap blob push failed\n");
return -EINVAL;
}
+ } else if (fld_src == BNXT_ULP_FIELD_SRC_SKIP) {
+ /* do nothing */
} else {
if (!ulp_blob_push(blob, val, val_len)) {
BNXT_TF_DBG(ERR, "push of val1 failed\n");
@@ -1465,7 +1506,7 @@ ulp_mapper_field_opc_process(struct bnxt_ulp_mapper_parms *parms,
if (!rc) {
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
- if (fld->field_src1 != BNXT_ULP_FIELD_SRC_ZERO)
+ if (fld->field_src1 != BNXT_ULP_FIELD_SRC_ZERO && val_len)
ulp_mapper_field_dump(name, fld, blob, write_idx, val,
val_len);
#endif
@@ -1489,7 +1530,8 @@ ulp_mapper_tbl_result_build(struct bnxt_ulp_mapper_parms *parms,
const char *name)
{
struct bnxt_ulp_mapper_field_info *dflds;
- uint32_t i, num_flds = 0, encap_flds = 0;
+ uint32_t i = 0, num_flds = 0, encap_flds = 0;
+ struct ulp_blob encap_blob;
int32_t rc = 0;
/* Get the result field list */
@@ -1506,33 +1548,60 @@ ulp_mapper_tbl_result_build(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
- /* process the result fields, loop through them */
- for (i = 0; i < (num_flds + encap_flds); i++) {
- /* set the swap index if encap swap bit is enabled */
- if (parms->device_params->encap_byte_swap && encap_flds &&
- i == num_flds)
- ulp_blob_encap_swap_idx_set(data);
-
- /* Process the result fields */
+ /* process the result fields */
+ for (i = 0; i < num_flds; i++) {
rc = ulp_mapper_field_opc_process(parms, tbl->direction,
&dflds[i], data, 0, name);
if (rc) {
- BNXT_TF_DBG(ERR, "data field failed\n");
+ BNXT_TF_DBG(ERR, "result field processing failed\n");
return rc;
}
}
- /* if encap bit swap is enabled perform the bit swap */
- if (parms->device_params->encap_byte_swap && encap_flds) {
- ulp_blob_perform_encap_swap(data);
+ /* process encap fields if any */
+ if (encap_flds) {
+ uint32_t pad = 0;
+ /* Initialize the encap blob */
+ if (!tbl->record_size) {
+ BNXT_TF_DBG(ERR, "Encap tbl record size incorrect\n");
+ return -EINVAL;
+ }
+ if (!ulp_blob_init(&encap_blob,
+ ULP_BYTE_2_BITS(tbl->record_size),
+ parms->device_params->encap_byte_order)) {
+ BNXT_TF_DBG(ERR, "blob inits failed.\n");
+ return -EINVAL;
+ }
+ for (; i < encap_flds; i++) {
+ rc = ulp_mapper_field_opc_process(parms, tbl->direction,
+ &dflds[i],
+ &encap_blob, 0, name);
+ if (rc) {
+ BNXT_TF_DBG(ERR,
+ "encap field processing failed\n");
+ return rc;
+ }
+ }
+ /* add the dynamic pad push */
+ pad = ULP_BYTE_2_BITS(tbl->record_size) -
+ ulp_blob_data_len_get(&encap_blob);
+ ulp_blob_pad_push(&encap_blob, pad);
+
+ /* perform the 64 bit byte swap */
+ ulp_blob_perform_64B_byte_swap(&encap_blob);
+ /* Append encap blob to the result blob */
+ rc = ulp_blob_buffer_copy(data, &encap_blob);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "encap buffer copy failed\n");
+ return rc;
+ }
+ }
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
- BNXT_TF_DBG(INFO, "Dump after encap swap\n");
- ulp_mapper_blob_dump(data);
+ BNXT_TF_DBG(DEBUG, "Result dump\n");
+ ulp_mapper_blob_dump(data);
#endif
#endif
- }
-
return rc;
}
@@ -1934,11 +2003,14 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
- if (!ulp_blob_init(key, tbl->blob_key_bit_size, tbl->byte_order) ||
- !ulp_blob_init(mask, tbl->blob_key_bit_size, tbl->byte_order) ||
- !ulp_blob_init(&data, tbl->result_bit_size, dparms->byte_order) ||
+ if (!ulp_blob_init(key, tbl->blob_key_bit_size,
+ dparms->key_byte_order) ||
+ !ulp_blob_init(mask, tbl->blob_key_bit_size,
+ dparms->key_byte_order) ||
+ !ulp_blob_init(&data, tbl->result_bit_size,
+ dparms->result_byte_order) ||
!ulp_blob_init(&update_data, tbl->result_bit_size,
- dparms->byte_order)) {
+ dparms->result_byte_order)) {
BNXT_TF_DBG(ERR, "blob inits failed.\n");
return -EINVAL;
}
@@ -2145,9 +2217,9 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
/* Initialize the key/result blobs */
if (!ulp_blob_init(&key, tbl->blob_key_bit_size,
- tbl->byte_order) ||
+ dparms->key_byte_order) ||
!ulp_blob_init(&data, tbl->result_bit_size,
- tbl->byte_order)) {
+ dparms->result_byte_order)) {
BNXT_TF_DBG(ERR, "blob inits failed.\n");
return -EINVAL;
}
@@ -2336,7 +2408,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
/* Initialize the blob data */
if (!ulp_blob_init(&data, bit_size,
- parms->device_params->byte_order)) {
+ parms->device_params->result_byte_order)) {
BNXT_TF_DBG(ERR, "Failed to initialize index table blob\n");
return -EINVAL;
}
@@ -2627,7 +2699,7 @@ ulp_mapper_if_tbl_process(struct bnxt_ulp_mapper_parms *parms,
tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session);
/* Initialize the blob data */
if (!ulp_blob_init(&data, tbl->result_bit_size,
- parms->device_params->byte_order)) {
+ parms->device_params->result_byte_order)) {
BNXT_TF_DBG(ERR, "Failed initial index table blob\n");
return -EINVAL;
}
@@ -2658,7 +2730,7 @@ ulp_mapper_if_tbl_process(struct bnxt_ulp_mapper_parms *parms,
case BNXT_ULP_IF_TBL_OPC_RD_COMP_FIELD:
/* Initialize the result blob */
if (!ulp_blob_init(&res_blob, tbl->result_bit_size,
- parms->device_params->byte_order)) {
+ parms->device_params->result_byte_order)) {
BNXT_TF_DBG(ERR, "Failed initial result blob\n");
return -EINVAL;
}
@@ -2747,7 +2819,7 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms,
}
if (!ulp_blob_init(&key, tbl->key_bit_size,
- parms->device_params->byte_order)) {
+ parms->device_params->key_byte_order)) {
BNXT_TF_DBG(ERR, "Failed to alloc blob\n");
return -EINVAL;
}
@@ -3252,6 +3324,26 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms,
}
*res = (mtype == BNXT_ULP_FLOW_MEM_TYPE_INT) ? 1 : 0;
break;
+ case BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET:
+ if (operand < BNXT_ULP_HDR_BIT_LAST) {
+ *res = ULP_BITMAP_ISSET(parms->enc_hdr_bitmap->bits,
+ operand);
+ } else {
+ BNXT_TF_DBG(ERR, "header bit out of bounds %d\n",
+ operand);
+ rc = -EINVAL;
+ }
+ break;
+ case BNXT_ULP_COND_OPC_ENC_HDR_BIT_NOT_SET:
+ if (operand < BNXT_ULP_HDR_BIT_LAST) {
+ *res = !ULP_BITMAP_ISSET(parms->enc_hdr_bitmap->bits,
+ operand);
+ } else {
+ BNXT_TF_DBG(ERR, "header bit out of bounds %d\n",
+ operand);
+ rc = -EINVAL;
+ }
+ break;
default:
BNXT_TF_DBG(ERR, "Invalid conditional opcode %d\n", opc);
rc = -EINVAL;
@@ -3864,8 +3956,10 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
parms.act_prop = cparms->act_prop;
parms.act_bitmap = cparms->act;
parms.hdr_bitmap = cparms->hdr_bitmap;
+ parms.enc_hdr_bitmap = cparms->enc_hdr_bitmap;
parms.regfile = ®file;
parms.hdr_field = cparms->hdr_field;
+ parms.enc_field = cparms->enc_field;
parms.fld_bitmap = cparms->fld_bitmap;
parms.comp_fld = cparms->comp_fld;
parms.ulp_ctx = ulp_ctx;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
index d4d6969bb5..4d6ba0f73a 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
@@ -44,7 +44,9 @@ struct bnxt_ulp_mapper_parms {
struct ulp_rte_act_prop *act_prop;
struct ulp_rte_act_bitmap *act_bitmap;
struct ulp_rte_hdr_bitmap *hdr_bitmap;
+ struct ulp_rte_hdr_bitmap *enc_hdr_bitmap;
struct ulp_rte_hdr_field *hdr_field;
+ struct ulp_rte_hdr_field *enc_field;
struct ulp_rte_field_bitmap *fld_bitmap;
uint64_t *comp_fld;
struct ulp_regfile *regfile;
@@ -67,7 +69,9 @@ struct bnxt_ulp_mapper_parms {
struct bnxt_ulp_mapper_create_parms {
uint32_t app_priority;
struct ulp_rte_hdr_bitmap *hdr_bitmap;
+ struct ulp_rte_hdr_bitmap *enc_hdr_bitmap;
struct ulp_rte_hdr_field *hdr_field;
+ struct ulp_rte_hdr_field *enc_field;
uint64_t *comp_fld;
struct ulp_rte_act_bitmap *act;
struct ulp_rte_act_prop *act_prop;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index fadcd3873c..4e9968e5fa 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -40,6 +40,18 @@ ulp_rte_item_skip_void(const struct rte_flow_item **item, uint32_t increment)
return 0;
}
+/* Utility function to copy field spec items */
+static struct ulp_rte_hdr_field *
+ulp_rte_parser_fld_copy(struct ulp_rte_hdr_field *field,
+ const void *buffer,
+ uint32_t size)
+{
+ field->size = size;
+ memcpy(field->spec, buffer, field->size);
+ field++;
+ return field;
+}
+
/* Utility function to update the field_bitmap */
static void
ulp_rte_parser_field_bitmap_update(struct ulp_rte_parser_params *params,
@@ -883,7 +895,7 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
BNXT_ULP_HDR_BIT_II_VLAN);
inner_flag = 1;
} else {
- BNXT_TF_DBG(ERR, "Error Parsing:Vlan hdr found withtout eth\n");
+ BNXT_TF_DBG(ERR, "Error Parsing:Vlan hdr found without eth\n");
return BNXT_TF_RC_ERROR;
}
/* Update the field protocol hdr bitmap */
@@ -1726,6 +1738,184 @@ ulp_rte_rss_act_handler(const struct rte_flow_action *action_item,
return BNXT_TF_RC_SUCCESS;
}
+/* Function to handle the parsing of RTE Flow item eth Header. */
+static void
+ulp_rte_enc_eth_hdr_handler(struct ulp_rte_parser_params *params,
+ const struct rte_flow_item_eth *eth_spec)
+{
+ struct ulp_rte_hdr_field *field;
+ uint32_t size;
+
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_ETH_DMAC];
+ size = sizeof(eth_spec->dst.addr_bytes);
+ field = ulp_rte_parser_fld_copy(field, eth_spec->dst.addr_bytes, size);
+
+ size = sizeof(eth_spec->src.addr_bytes);
+ field = ulp_rte_parser_fld_copy(field, eth_spec->src.addr_bytes, size);
+
+ size = sizeof(eth_spec->type);
+ field = ulp_rte_parser_fld_copy(field, ð_spec->type, size);
+
+ ULP_BITMAP_SET(params->enc_hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_ETH);
+}
+
+/* Function to handle the parsing of RTE Flow item vlan Header. */
+static void
+ulp_rte_enc_vlan_hdr_handler(struct ulp_rte_parser_params *params,
+ const struct rte_flow_item_vlan *vlan_spec,
+ uint32_t inner)
+{
+ struct ulp_rte_hdr_field *field;
+ uint32_t size;
+
+ if (!inner) {
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_O_VLAN_TCI];
+ ULP_BITMAP_SET(params->enc_hdr_bitmap.bits,
+ BNXT_ULP_HDR_BIT_OO_VLAN);
+ } else {
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_I_VLAN_TCI];
+ ULP_BITMAP_SET(params->enc_hdr_bitmap.bits,
+ BNXT_ULP_HDR_BIT_OI_VLAN);
+ }
+
+ size = sizeof(vlan_spec->tci);
+ field = ulp_rte_parser_fld_copy(field, &vlan_spec->tci, size);
+
+ size = sizeof(vlan_spec->inner_type);
+ field = ulp_rte_parser_fld_copy(field, &vlan_spec->inner_type, size);
+}
+
+/* Function to handle the parsing of RTE Flow item ipv4 Header. */
+static void
+ulp_rte_enc_ipv4_hdr_handler(struct ulp_rte_parser_params *params,
+ const struct rte_flow_item_ipv4 *ip)
+{
+ struct ulp_rte_hdr_field *field;
+ uint32_t size;
+ uint8_t val8;
+
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_IPV4_IHL];
+ size = sizeof(ip->hdr.version_ihl);
+ if (!ip->hdr.version_ihl)
+ val8 = RTE_IPV4_VHL_DEF;
+ else
+ val8 = ip->hdr.version_ihl;
+ field = ulp_rte_parser_fld_copy(field, &val8, size);
+
+ size = sizeof(ip->hdr.type_of_service);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.type_of_service, size);
+
+ size = sizeof(ip->hdr.packet_id);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.packet_id, size);
+
+ size = sizeof(ip->hdr.fragment_offset);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.fragment_offset, size);
+
+ size = sizeof(ip->hdr.time_to_live);
+ if (!ip->hdr.time_to_live)
+ val8 = BNXT_ULP_DEFAULT_TTL;
+ else
+ val8 = ip->hdr.time_to_live;
+ field = ulp_rte_parser_fld_copy(field, &val8, size);
+
+ size = sizeof(ip->hdr.next_proto_id);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.next_proto_id, size);
+
+ size = sizeof(ip->hdr.src_addr);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.src_addr, size);
+
+ size = sizeof(ip->hdr.dst_addr);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.dst_addr, size);
+
+ ULP_BITMAP_SET(params->enc_hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV4);
+}
+
+/* Function to handle the parsing of RTE Flow item ipv6 Header. */
+static void
+ulp_rte_enc_ipv6_hdr_handler(struct ulp_rte_parser_params *params,
+ const struct rte_flow_item_ipv6 *ip)
+{
+ struct ulp_rte_hdr_field *field;
+ uint32_t size;
+ uint32_t val32;
+ uint8_t val8;
+
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW];
+ size = sizeof(ip->hdr.vtc_flow);
+ if (!ip->hdr.vtc_flow)
+ val32 = rte_cpu_to_be_32(BNXT_ULP_IPV6_DFLT_VER);
+ else
+ val32 = ip->hdr.vtc_flow;
+ field = ulp_rte_parser_fld_copy(field, &val32, size);
+
+ size = sizeof(ip->hdr.proto);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.proto, size);
+
+ size = sizeof(ip->hdr.hop_limits);
+ if (!ip->hdr.hop_limits)
+ val8 = BNXT_ULP_DEFAULT_TTL;
+ else
+ val8 = ip->hdr.hop_limits;
+ field = ulp_rte_parser_fld_copy(field, &val8, size);
+
+ size = sizeof(ip->hdr.src_addr);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.src_addr, size);
+
+ size = sizeof(ip->hdr.dst_addr);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.dst_addr, size);
+
+ ULP_BITMAP_SET(params->enc_hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV6);
+}
+
+/* Function to handle the parsing of RTE Flow item UDP Header. */
+static void
+ulp_rte_enc_udp_hdr_handler(struct ulp_rte_parser_params *params,
+ const struct rte_flow_item_udp *udp_spec)
+{
+ struct ulp_rte_hdr_field *field;
+ uint32_t size;
+ uint8_t type = IPPROTO_UDP;
+
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_UDP_SPORT];
+ size = sizeof(udp_spec->hdr.src_port);
+ field = ulp_rte_parser_fld_copy(field, &udp_spec->hdr.src_port, size);
+
+ size = sizeof(udp_spec->hdr.dst_port);
+ field = ulp_rte_parser_fld_copy(field, &udp_spec->hdr.dst_port, size);
+
+ ULP_BITMAP_SET(params->enc_hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_UDP);
+
+ /* Update thhe ip header protocol */
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_IPV4_PROTO];
+ ulp_rte_parser_fld_copy(field, &type, sizeof(type));
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_IPV6_PROTO];
+ ulp_rte_parser_fld_copy(field, &type, sizeof(type));
+}
+
+/* Function to handle the parsing of RTE Flow item vxlan Header. */
+static void
+ulp_rte_enc_vxlan_hdr_handler(struct ulp_rte_parser_params *params,
+ struct rte_flow_item_vxlan *vxlan_spec)
+{
+ struct ulp_rte_hdr_field *field;
+ uint32_t size;
+
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_VXLAN_FLAGS];
+ size = sizeof(vxlan_spec->flags);
+ field = ulp_rte_parser_fld_copy(field, &vxlan_spec->flags, size);
+
+ size = sizeof(vxlan_spec->rsvd0);
+ field = ulp_rte_parser_fld_copy(field, &vxlan_spec->rsvd0, size);
+
+ size = sizeof(vxlan_spec->vni);
+ field = ulp_rte_parser_fld_copy(field, &vxlan_spec->vni, size);
+
+ size = sizeof(vxlan_spec->rsvd1);
+ field = ulp_rte_parser_fld_copy(field, &vxlan_spec->rsvd1, size);
+
+ ULP_BITMAP_SET(params->enc_hdr_bitmap.bits, BNXT_ULP_HDR_BIT_T_VXLAN);
+}
+
/* Function to handle the parsing of RTE Flow action vxlan_encap Header. */
int32_t
ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
@@ -1733,23 +1923,14 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
{
const struct rte_flow_action_vxlan_encap *vxlan_encap;
const struct rte_flow_item *item;
- const struct rte_flow_item_eth *eth_spec;
const struct rte_flow_item_ipv4 *ipv4_spec;
const struct rte_flow_item_ipv6 *ipv6_spec;
struct rte_flow_item_vxlan vxlan_spec;
uint32_t vlan_num = 0, vlan_size = 0;
uint32_t ip_size = 0, ip_type = 0;
uint32_t vxlan_size = 0;
- uint8_t *buff;
- /* IP header per byte - ver/hlen, TOS, ID, ID, FRAG, FRAG, TTL, PROTO */
- const uint8_t def_ipv4_hdr[] = {0x45, 0x00, 0x00, 0x01, 0x00,
- 0x00, 0x40, 0x11};
- /* IPv6 header per byte - vtc-flow,flow,zero,nexthdr-ttl */
- const uint8_t def_ipv6_hdr[] = {0x60, 0x00, 0x00, 0x01, 0x00,
- 0x00, 0x11, 0xf6};
struct ulp_rte_act_bitmap *act = ¶ms->act_bitmap;
struct ulp_rte_act_prop *ap = ¶ms->act_prop;
- const uint8_t *tmp_buff;
vxlan_encap = action_item->conf;
if (!vxlan_encap) {
@@ -1771,18 +1952,10 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
BNXT_TF_DBG(ERR, "Parse Error:vxlan encap does not have eth\n");
return BNXT_TF_RC_ERROR;
}
- eth_spec = item->spec;
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC];
- ulp_encap_buffer_copy(buff,
- eth_spec->dst.addr_bytes,
- BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_DMAC,
- ULP_BUFFER_ALIGN_8_BYTE);
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC];
- ulp_encap_buffer_copy(buff,
- eth_spec->src.addr_bytes,
- BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_SMAC,
- ULP_BUFFER_ALIGN_8_BYTE);
+ /* Parse the ethernet header */
+ if (item->spec)
+ ulp_rte_enc_eth_hdr_handler(params, item->spec);
/* Goto the next item */
if (!ulp_rte_item_skip_void(&item, 1))
@@ -1791,11 +1964,8 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
/* May have vlan header */
if (item->type == RTE_FLOW_ITEM_TYPE_VLAN) {
vlan_num++;
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG];
- ulp_encap_buffer_copy(buff,
- item->spec,
- sizeof(struct rte_flow_item_vlan),
- ULP_BUFFER_ALIGN_8_BYTE);
+ if (item->spec)
+ ulp_rte_enc_vlan_hdr_handler(params, item->spec, 0);
if (!ulp_rte_item_skip_void(&item, 1))
return BNXT_TF_RC_ERROR;
@@ -1804,13 +1974,13 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
/* may have two vlan headers */
if (item->type == RTE_FLOW_ITEM_TYPE_VLAN) {
vlan_num++;
- memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG +
- sizeof(struct rte_flow_item_vlan)],
- item->spec,
- sizeof(struct rte_flow_item_vlan));
+ if (item->spec)
+ ulp_rte_enc_vlan_hdr_handler(params, item->spec, 1);
+
if (!ulp_rte_item_skip_void(&item, 1))
return BNXT_TF_RC_ERROR;
}
+
/* Update the vlan count and size of more than one */
if (vlan_num) {
vlan_size = vlan_num * sizeof(struct rte_flow_item_vlan);
@@ -1829,49 +1999,6 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
ipv4_spec = item->spec;
ip_size = BNXT_ULP_ENCAP_IPV4_SIZE;
- /* copy the ipv4 details */
- if (ulp_buffer_is_empty(&ipv4_spec->hdr.version_ihl,
- BNXT_ULP_ENCAP_IPV4_VER_HLEN_TOS)) {
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP];
- ulp_encap_buffer_copy(buff,
- def_ipv4_hdr,
- BNXT_ULP_ENCAP_IPV4_VER_HLEN_TOS +
- BNXT_ULP_ENCAP_IPV4_ID_PROTO,
- ULP_BUFFER_ALIGN_8_BYTE);
- } else {
- /* Total length being ignored in the ip hdr. */
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP];
- tmp_buff = (const uint8_t *)&ipv4_spec->hdr.packet_id;
- ulp_encap_buffer_copy(buff,
- tmp_buff,
- BNXT_ULP_ENCAP_IPV4_ID_PROTO,
- ULP_BUFFER_ALIGN_8_BYTE);
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP +
- BNXT_ULP_ENCAP_IPV4_ID_PROTO];
- ulp_encap_buffer_copy(buff,
- &ipv4_spec->hdr.version_ihl,
- BNXT_ULP_ENCAP_IPV4_VER_HLEN_TOS,
- ULP_BUFFER_ALIGN_8_BYTE);
- }
-
- /* Update the dst ip address in ip encap buffer */
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP +
- BNXT_ULP_ENCAP_IPV4_VER_HLEN_TOS +
- BNXT_ULP_ENCAP_IPV4_ID_PROTO];
- ulp_encap_buffer_copy(buff,
- (const uint8_t *)&ipv4_spec->hdr.dst_addr,
- sizeof(ipv4_spec->hdr.dst_addr),
- ULP_BUFFER_ALIGN_8_BYTE);
-
- /* Update the src ip address */
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC +
- BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SRC -
- sizeof(ipv4_spec->hdr.src_addr)];
- ulp_encap_buffer_copy(buff,
- (const uint8_t *)&ipv4_spec->hdr.src_addr,
- sizeof(ipv4_spec->hdr.src_addr),
- ULP_BUFFER_ALIGN_8_BYTE);
-
/* Update the ip size details */
ip_size = tfp_cpu_to_be_32(ip_size);
memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ],
@@ -1885,6 +2012,8 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
/* update the computed field to notify it is ipv4 header */
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG,
1);
+ if (ipv4_spec)
+ ulp_rte_enc_ipv4_hdr_handler(params, ipv4_spec);
if (!ulp_rte_item_skip_void(&item, 1))
return BNXT_TF_RC_ERROR;
@@ -1892,47 +2021,6 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
ipv6_spec = item->spec;
ip_size = BNXT_ULP_ENCAP_IPV6_SIZE;
- /* copy the ipv6 details */
- tmp_buff = (const uint8_t *)&ipv6_spec->hdr.vtc_flow;
- if (ulp_buffer_is_empty(tmp_buff,
- BNXT_ULP_ENCAP_IPV6_VTC_FLOW)) {
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP];
- ulp_encap_buffer_copy(buff,
- def_ipv6_hdr,
- sizeof(def_ipv6_hdr),
- ULP_BUFFER_ALIGN_8_BYTE);
- } else {
- /* The payload length being ignored in the ip hdr. */
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP];
- tmp_buff = (const uint8_t *)&ipv6_spec->hdr.proto;
- ulp_encap_buffer_copy(buff,
- tmp_buff,
- BNXT_ULP_ENCAP_IPV6_PROTO_TTL,
- ULP_BUFFER_ALIGN_8_BYTE);
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP +
- BNXT_ULP_ENCAP_IPV6_PROTO_TTL +
- BNXT_ULP_ENCAP_IPV6_DO];
- tmp_buff = (const uint8_t *)&ipv6_spec->hdr.vtc_flow;
- ulp_encap_buffer_copy(buff,
- tmp_buff,
- BNXT_ULP_ENCAP_IPV6_VTC_FLOW,
- ULP_BUFFER_ALIGN_8_BYTE);
- }
- /* Update the dst ip address in ip encap buffer */
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP +
- sizeof(def_ipv6_hdr)];
- ulp_encap_buffer_copy(buff,
- (const uint8_t *)ipv6_spec->hdr.dst_addr,
- sizeof(ipv6_spec->hdr.dst_addr),
- ULP_BUFFER_ALIGN_8_BYTE);
-
- /* Update the src ip address */
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC];
- ulp_encap_buffer_copy(buff,
- (const uint8_t *)ipv6_spec->hdr.src_addr,
- sizeof(ipv6_spec->hdr.src_addr),
- ULP_BUFFER_ALIGN_16_BYTE);
-
/* Update the ip size details */
ip_size = tfp_cpu_to_be_32(ip_size);
memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ],
@@ -1946,6 +2034,8 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
/* update the computed field to notify it is ipv6 header */
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG,
1);
+ if (ipv6_spec)
+ ulp_rte_enc_ipv6_hdr_handler(params, ipv6_spec);
if (!ulp_rte_item_skip_void(&item, 1))
return BNXT_TF_RC_ERROR;
@@ -1959,10 +2049,8 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
BNXT_TF_DBG(ERR, "vxlan encap does not have udp\n");
return BNXT_TF_RC_ERROR;
}
- /* copy the udp details */
- ulp_encap_buffer_copy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP],
- item->spec, BNXT_ULP_ENCAP_UDP_SIZE,
- ULP_BUFFER_ALIGN_8_BYTE);
+ if (item->spec)
+ ulp_rte_enc_udp_hdr_handler(params, item->spec);
if (!ulp_rte_item_skip_void(&item, 1))
return BNXT_TF_RC_ERROR;
@@ -1976,21 +2064,12 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
/* copy the vxlan details */
memcpy(&vxlan_spec, item->spec, vxlan_size);
vxlan_spec.flags = 0x08;
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN];
- if (ip_type == rte_cpu_to_be_32(BNXT_ULP_ETH_IPV4)) {
- ulp_encap_buffer_copy(buff, (const uint8_t *)&vxlan_spec,
- vxlan_size, ULP_BUFFER_ALIGN_8_BYTE);
- } else {
- ulp_encap_buffer_copy(buff, (const uint8_t *)&vxlan_spec,
- vxlan_size / 2, ULP_BUFFER_ALIGN_8_BYTE);
- ulp_encap_buffer_copy(buff + (vxlan_size / 2),
- (const uint8_t *)&vxlan_spec.vni,
- vxlan_size / 2, ULP_BUFFER_ALIGN_8_BYTE);
- }
vxlan_size = tfp_cpu_to_be_32(vxlan_size);
memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ],
&vxlan_size, sizeof(uint32_t));
+ ulp_rte_enc_vxlan_hdr_handler(params, &vxlan_spec);
+
/* update the hdr_bitmap with vxlan */
ULP_BITMAP_SET(act->bits, BNXT_ULP_ACT_BIT_VXLAN_ENCAP);
return BNXT_TF_RC_SUCCESS;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
index 673172c811..e14f86278a 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
@@ -33,8 +33,10 @@
#define BNXT_ULP_GET_IPV6_FLOWLABEL(vtcf) \
((vtcf) & BNXT_ULP_PARSER_IPV6_FLOW_LABEL)
#define BNXT_ULP_PARSER_IPV6_VER_MASK 0xf0000000
+#define BNXT_ULP_IPV6_DFLT_VER 0x60000000
#define BNXT_ULP_PARSER_IPV6_TC 0x0ff00000
#define BNXT_ULP_PARSER_IPV6_FLOW_LABEL 0x000fffff
+#define BNXT_ULP_DEFAULT_TTL 64
enum bnxt_ulp_prsr_action {
ULP_PRSR_ACT_DEFAULT = 0,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index 2685e63432..904763f27d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -30,6 +30,7 @@
#define BNXT_ULP_PROTO_HDR_GRE_NUM 6
#define BNXT_ULP_PROTO_HDR_ICMP_NUM 5
#define BNXT_ULP_PROTO_HDR_MAX 128
+#define BNXT_ULP_PROTO_HDR_ENCAP_MAX 64
#define BNXT_ULP_PROTO_HDR_FIELD_SVIF_IDX 1
/* Direction attributes */
@@ -64,12 +65,13 @@ struct ulp_rte_act_prop {
/* Structure to be used for passing all the parser functions */
struct ulp_rte_parser_params {
- STAILQ_ENTRY(ulp_rte_parser_params) next;
struct ulp_rte_hdr_bitmap hdr_bitmap;
+ struct ulp_rte_hdr_bitmap enc_hdr_bitmap;
struct ulp_rte_hdr_bitmap hdr_fp_bit;
struct ulp_rte_field_bitmap fld_bitmap;
struct ulp_rte_field_bitmap fld_s_bitmap;
struct ulp_rte_hdr_field hdr_field[BNXT_ULP_PROTO_HDR_MAX];
+ struct ulp_rte_hdr_field enc_field[BNXT_ULP_PROTO_HDR_ENCAP_MAX];
uint64_t comp_fld[BNXT_ULP_CF_IDX_LAST];
uint32_t field_idx;
struct ulp_rte_act_bitmap act_bitmap;
@@ -207,7 +209,9 @@ struct bnxt_ulp_template_device_tbls {
/* Device specific parameters */
struct bnxt_ulp_device_params {
uint8_t description[16];
- enum bnxt_ulp_byte_order byte_order;
+ enum bnxt_ulp_byte_order key_byte_order;
+ enum bnxt_ulp_byte_order result_byte_order;
+ enum bnxt_ulp_byte_order encap_byte_order;
uint8_t encap_byte_swap;
uint8_t num_phy_ports;
uint32_t mark_db_lfid_entries;
@@ -254,7 +258,6 @@ struct bnxt_ulp_mapper_tbl_info {
uint8_t direction;
enum bnxt_ulp_pri_opc pri_opcode;
uint32_t pri_operand;
- enum bnxt_ulp_byte_order byte_order;
/* conflict resolution opcode */
enum bnxt_ulp_accept_opc accept_opcode;
@@ -267,6 +270,7 @@ struct bnxt_ulp_mapper_tbl_info {
uint16_t key_num_fields;
/* Size of the blob that holds the key */
uint16_t blob_key_bit_size;
+ uint16_t record_size;
/* Information for accessing the ulp_class_result_field_list */
uint32_t result_start_idx;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c
index 1649e157f2..fc4f435c97 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c
@@ -62,7 +62,7 @@ ulp_regfile_read(struct ulp_regfile *regfile,
* data [in] The value is written into this variable. It is going to be in the
* same byte order as it was written.
*
- * size [in] The size in bytes of the value beingritten into this
+ * size [in] The size in bytes of the value being written into this
* variable.
*
* returns 0 on success
@@ -295,7 +295,7 @@ ulp_blob_push(struct ulp_blob *blob,
datalen,
data);
if (!rc) {
- BNXT_TF_DBG(ERR, "Failed ro write blob\n");
+ BNXT_TF_DBG(ERR, "Failed to write blob\n");
return 0;
}
blob->write_idx += datalen;
@@ -355,7 +355,7 @@ ulp_blob_insert(struct ulp_blob *blob, uint32_t offset,
datalen,
data);
if (!rc) {
- BNXT_TF_DBG(ERR, "Failed ro write blob\n");
+ BNXT_TF_DBG(ERR, "Failed to write blob\n");
return 0;
}
/* copy the previously stored data */
@@ -409,7 +409,7 @@ ulp_blob_push_64(struct ulp_blob *blob,
*
* data [in] 32-bit value to be added to the blob.
*
- * datalen [in] The number of bits to be added ot the blob.
+ * datalen [in] The number of bits to be added to the blob.
*
* The offset of the data is updated after each push of data.
* NULL returned on error, pointer pushed value otherwise.
@@ -987,6 +987,33 @@ ulp_blob_append(struct ulp_blob *dst, struct ulp_blob *src,
return 0;
}
+/*
+ * Perform the blob buffer copy.
+ * This api makes the src blob merged to the dst blob.
+ *
+ * dst [in] The destination blob, the blob to be merged.
+ * src [in] The src blob.
+ *
+ * returns 0 on success.
+ */
+int32_t
+ulp_blob_buffer_copy(struct ulp_blob *dst, struct ulp_blob *src)
+{
+ if ((dst->write_idx + src->write_idx) > dst->bitlen) {
+ BNXT_TF_DBG(ERR, "source buffer too large\n");
+ return -EINVAL;
+ }
+ if (ULP_BITS_IS_BYTE_NOT_ALIGNED(dst->write_idx) ||
+ ULP_BITS_IS_BYTE_NOT_ALIGNED(src->write_idx)) {
+ BNXT_TF_DBG(ERR, "source buffer is not aligned\n");
+ return -EINVAL;
+ }
+ memcpy(&dst->data[ULP_BITS_2_BYTE_NR(dst->write_idx)],
+ src->data, ULP_BITS_2_BYTE_NR(src->write_idx));
+ dst->write_idx += src->write_idx;
+ return 0;
+}
+
/*
* Read data from the operand
*
@@ -1012,44 +1039,6 @@ ulp_operand_read(uint8_t *operand,
return bytes;
}
-/*
- * copy the buffer in the encap format which is 2 bytes.
- * The MSB of the src is placed at the LSB of dst.
- *
- * dst [out] The destination buffer
- * src [in] The source buffer dst
- * size[in] size of the buffer.
- * align[in] The alignment is either 8 or 16.
- */
-void
-ulp_encap_buffer_copy(uint8_t *dst,
- const uint8_t *src,
- uint16_t size,
- uint16_t align)
-{
- uint16_t idx, tmp_size = 0;
-
- do {
- dst += tmp_size;
- src += tmp_size;
- idx = 0;
- if (size > align) {
- tmp_size = align;
- size -= align;
- } else {
- tmp_size = size;
- size = 0;
- }
- /* copy 2 bytes at a time. Write MSB to LSB */
- while ((idx + sizeof(uint16_t)) <= tmp_size) {
- memcpy(&dst[idx],
- &src[tmp_size - idx - sizeof(uint16_t)],
- sizeof(uint16_t));
- idx += sizeof(uint16_t);
- }
- } while (size);
-}
-
/*
* Check the buffer is empty
*
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.h b/drivers/net/bnxt/tf_ulp/ulp_utils.h
index e1b0e773f3..68a537fa0a 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.h
@@ -475,6 +475,18 @@ int32_t
ulp_blob_append(struct ulp_blob *dst, struct ulp_blob *src,
uint16_t src_offset, uint16_t src_len);
+/*
+ * Perform the blob buffer copy.
+ * This api makes the src blob merged to the dst blob.
+ *
+ * dst [in] The destination blob, the blob to be merged.
+ * src [in] The src blob.
+ *
+ * returns 0 on success.
+ */
+int32_t
+ulp_blob_buffer_copy(struct ulp_blob *dst, struct ulp_blob *src);
+
/*
* Read data from the operand
*
@@ -491,21 +503,6 @@ ulp_operand_read(uint8_t *operand,
uint8_t *val,
uint16_t bitlen);
-/*
- * copy the buffer in the encap format which is 2 bytes.
- * The MSB of the src is placed at the LSB of dst.
- *
- * dst [out] The destination buffer
- * src [in] The source buffer dst
- * size[in] size of the buffer.
- * align[in] The alignment is either 8 or 16.
- */
-void
-ulp_encap_buffer_copy(uint8_t *dst,
- const uint8_t *src,
- uint16_t size,
- uint16_t align);
-
/*
* Check the buffer is empty
*
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH 08/14] net/bnxt: add wild card TCAM byte order for Thor
2021-09-01 14:24 [dpdk-dev] [PATCH 00/14] enhancements to host based flow table management Venkat Duvvuru
` (6 preceding siblings ...)
2021-09-01 14:24 ` [dpdk-dev] [PATCH 07/14] net/bnxt: add support for dynamic encap action Venkat Duvvuru
@ 2021-09-01 14:24 ` Venkat Duvvuru
2021-09-01 14:24 ` [dpdk-dev] [PATCH 09/14] net/bnxt: add flow templates " Venkat Duvvuru
` (6 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-01 14:24 UTC (permalink / raw)
To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
The wild card tcam for Thor platform is different from the profile tcam
byte order.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Shuanglin Wang <shuanglin.wang@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
.../generic_templates/ulp_template_db_tbl.c | 2 ++
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 25 +++++++++++++------
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 1 +
3 files changed, 21 insertions(+), 7 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
index b5bce6f4c7..68f1b5fd00 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
@@ -201,6 +201,7 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
.key_byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE,
.encap_byte_order = BNXT_ULP_BYTE_ORDER_BE,
+ .wc_key_byte_order = BNXT_ULP_BYTE_ORDER_BE,
.encap_byte_swap = 1,
.int_flow_db_num_entries = 16384,
.ext_flow_db_num_entries = 32768,
@@ -223,6 +224,7 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
.key_byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE,
.encap_byte_order = BNXT_ULP_BYTE_ORDER_BE,
+ .wc_key_byte_order = BNXT_ULP_BYTE_ORDER_BE,
.encap_byte_swap = 1,
.int_flow_db_num_entries = 16384,
.ext_flow_db_num_entries = 32768,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 2687a545f3..bcc089b3e1 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -1953,6 +1953,15 @@ static void ulp_mapper_wc_tcam_tbl_post_process(struct ulp_blob *blob)
#endif
}
+static int32_t ulp_mapper_tcam_is_wc_tcam(struct bnxt_ulp_mapper_tbl_info *tbl)
+{
+ if (tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM ||
+ tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM_HIGH ||
+ tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM_LOW)
+ return 1;
+ return 0;
+}
+
static int32_t
ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
struct bnxt_ulp_mapper_tbl_info *tbl)
@@ -1972,6 +1981,7 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
uint32_t hit = 0;
uint16_t tmplen = 0;
uint16_t idx;
+ enum bnxt_ulp_byte_order key_byte_order;
/* Set the key and mask to the original key and mask. */
key = &okey;
@@ -2003,10 +2013,13 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
- if (!ulp_blob_init(key, tbl->blob_key_bit_size,
- dparms->key_byte_order) ||
- !ulp_blob_init(mask, tbl->blob_key_bit_size,
- dparms->key_byte_order) ||
+ if (ulp_mapper_tcam_is_wc_tcam(tbl))
+ key_byte_order = dparms->wc_key_byte_order;
+ else
+ key_byte_order = dparms->key_byte_order;
+
+ if (!ulp_blob_init(key, tbl->blob_key_bit_size, key_byte_order) ||
+ !ulp_blob_init(mask, tbl->blob_key_bit_size, key_byte_order) ||
!ulp_blob_init(&data, tbl->result_bit_size,
dparms->result_byte_order) ||
!ulp_blob_init(&update_data, tbl->result_bit_size,
@@ -2043,9 +2056,7 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
}
/* For wild card tcam perform the post process to swap the blob */
- if (tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM ||
- tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM_HIGH ||
- tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM_LOW) {
+ if (ulp_mapper_tcam_is_wc_tcam(tbl)) {
if (dparms->dynamic_pad_en) {
/* Sets up the slices for writing to the WC TCAM */
rc = ulp_mapper_wc_tcam_tbl_dyn_post_process(dparms,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index 904763f27d..e2a4b81cec 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -212,6 +212,7 @@ struct bnxt_ulp_device_params {
enum bnxt_ulp_byte_order key_byte_order;
enum bnxt_ulp_byte_order result_byte_order;
enum bnxt_ulp_byte_order encap_byte_order;
+ enum bnxt_ulp_byte_order wc_key_byte_order;
uint8_t encap_byte_swap;
uint8_t num_phy_ports;
uint32_t mark_db_lfid_entries;
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH 09/14] net/bnxt: add flow templates for Thor
2021-09-01 14:24 [dpdk-dev] [PATCH 00/14] enhancements to host based flow table management Venkat Duvvuru
` (7 preceding siblings ...)
2021-09-01 14:24 ` [dpdk-dev] [PATCH 08/14] net/bnxt: add wild card TCAM byte order for Thor Venkat Duvvuru
@ 2021-09-01 14:24 ` Venkat Duvvuru
2021-09-01 14:24 ` [dpdk-dev] [PATCH 10/14] net/bnxt: tf core SRAM Manager Venkat Duvvuru
` (5 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-01 14:24 UTC (permalink / raw)
To: dev; +Cc: Kishore Padmanabha, Mike Baucom, Venkat Duvvuru
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
1. Add support for egress flows with port and count action for
Thor platform.
2. Added templates to support VXLAN encapsulation feature for Thor.
3. Added support for VXLAN decap and VLAN pop actions along with
the ingress flow.
4. Added templates to enable VXLAN decap support for f1 and f2 flows.
5. Added templates Thor VF Rep support
6. Added Thor ingress mod table actions for NAT, NAPT, and TTL.
7. Added mirror/sample table support
8. Added supported for IPv6 flows for Thor.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Mike Baucom <michael.baucom@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
Reviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com>
---
drivers/net/bnxt/tf_core/tf_tcam.c | 6 +-
.../generic_templates/ulp_template_db_enum.h | 123 +-
.../generic_templates/ulp_template_db_tbl.c | 182 +-
.../ulp_template_db_thor_act.c | 4329 +-
.../ulp_template_db_thor_class.c | 44219 ++++++++++++++--
.../ulp_template_db_wh_plus_class.c | 4 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 10 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 18 +-
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 1 +
drivers/net/bnxt/tf_ulp/ulp_utils.c | 3 +
10 files changed, 44734 insertions(+), 4161 deletions(-)
diff --git a/drivers/net/bnxt/tf_core/tf_tcam.c b/drivers/net/bnxt/tf_core/tf_tcam.c
index 806af3070a..273f20858b 100644
--- a/drivers/net/bnxt/tf_core/tf_tcam.c
+++ b/drivers/net/bnxt/tf_core/tf_tcam.c
@@ -323,8 +323,12 @@ tf_tcam_alloc(struct tf *tfp,
}
/* return the start index of each row */
- if (i == 0)
+ if (parms->priority == 0) {
+ if (i == 0)
+ parms->idx = index;
+ } else {
parms->idx = index;
+ }
}
return 0;
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
index 9010d9a749..84e3d92f41 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
@@ -3,12 +3,12 @@
* All rights reserved.
*/
-/* date: Thu May 27 17:35:19 2021 */
+/* date: Tue Jul 13 12:36:40 2021 */
#ifndef ULP_TEMPLATE_DB_H_
#define ULP_TEMPLATE_DB_H_
-#define BNXT_ULP_REGFILE_MAX_SZ 40
+#define BNXT_ULP_REGFILE_MAX_SZ 42
#define BNXT_ULP_MAX_NUM_DEVICES 4
#define BNXT_ULP_LOG2_MAX_NUM_DEV 2
#define BNXT_ULP_GEN_TBL_MAX_SZ 12
@@ -27,9 +27,9 @@
#define BNXT_ULP_ACT_HID_SHFTL 26
#define BNXT_ULP_ACT_HID_MASK 2047
#define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 8
-#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 43
+#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 62
#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 50
-#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 204
+#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 206
#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 6
#define BNXT_ULP_COND_GOTO_REJECT 1023
#define BNXT_ULP_COND_GOTO_RF 0x10000
@@ -44,23 +44,23 @@
#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 618
#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 49
#define ULP_THOR_CLASS_TMPL_LIST_SIZE 6
-#define ULP_THOR_CLASS_TBL_LIST_SIZE 33
-#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 242
-#define ULP_THOR_CLASS_IDENT_LIST_SIZE 8
-#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 259
-#define ULP_THOR_CLASS_COND_LIST_SIZE 13
+#define ULP_THOR_CLASS_TBL_LIST_SIZE 114
+#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 2305
+#define ULP_THOR_CLASS_IDENT_LIST_SIZE 39
+#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1192
+#define ULP_THOR_CLASS_COND_LIST_SIZE 55
#define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7
#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 35
#define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2
#define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 1
-#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 527
+#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 536
#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 39
#define ULP_THOR_ACT_TMPL_LIST_SIZE 7
-#define ULP_THOR_ACT_TBL_LIST_SIZE 2
-#define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 0
-#define ULP_THOR_ACT_IDENT_LIST_SIZE 0
-#define ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE 18
-#define ULP_THOR_ACT_COND_LIST_SIZE 5
+#define ULP_THOR_ACT_TBL_LIST_SIZE 28
+#define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 2
+#define ULP_THOR_ACT_IDENT_LIST_SIZE 1
+#define ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE 479
+#define ULP_THOR_ACT_COND_LIST_SIZE 20
enum bnxt_ulp_act_bit {
BNXT_ULP_ACT_BIT_MARK = 0x0000000000000001,
@@ -203,7 +203,11 @@ enum bnxt_ulp_cf_idx {
BNXT_ULP_CF_IDX_TUNNEL_ID = 63,
BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID = 64,
BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID = 65,
- BNXT_ULP_CF_IDX_LAST = 66
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID = 66,
+ BNXT_ULP_CF_IDX_OI_VLAN_FB_VID = 67,
+ BNXT_ULP_CF_IDX_IO_VLAN_FB_VID = 68,
+ BNXT_ULP_CF_IDX_II_VLAN_FB_VID = 69,
+ BNXT_ULP_CF_IDX_LAST = 70
};
enum bnxt_ulp_cond_list_opc {
@@ -386,29 +390,42 @@ enum bnxt_ulp_glb_rf_idx {
BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR = 5,
BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 = 6,
BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 = 7,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0 = 8,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1 = 9,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 = 10,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 = 11,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0 = 12,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1 = 13,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 14,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 = 15,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2 = 16,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 17,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 18,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 19,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 20,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 21,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 22,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 23,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 24,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 25,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 26,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 27,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 28,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 29,
- BNXT_ULP_GLB_RF_IDX_LAST = 30
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 = 8,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 = 9,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 = 10,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 = 11,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0 = 12,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1 = 13,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 = 14,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 = 15,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 = 16,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3 = 17,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4 = 18,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0 = 19,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1 = 20,
+ BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0 = 21,
+ BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_1 = 22,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 = 23,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 = 24,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 = 25,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 26,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 = 27,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2 = 28,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 29,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 30,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 31,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 32,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 33,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 34,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 35,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 36,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 37,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 38,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 39,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 40,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 41,
+ BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID = 42,
+ BNXT_ULP_GLB_RF_IDX_LAST = 43
};
enum bnxt_ulp_hdr_type {
@@ -520,7 +537,9 @@ enum bnxt_ulp_rf_idx {
BNXT_ULP_RF_IDX_CC = 37,
BNXT_ULP_RF_IDX_CF_FLOW_SIG_ID = 38,
BNXT_ULP_RF_IDX_PHY_PORT = 39,
- BNXT_ULP_RF_IDX_LAST = 40
+ BNXT_ULP_RF_IDX_METADATA_PROF = 40,
+ BNXT_ULP_RF_IDX_MODIFY_PTR = 41,
+ BNXT_ULP_RF_IDX_LAST = 42
};
enum bnxt_ulp_shared_session {
@@ -693,6 +712,13 @@ enum bnxt_ulp_act_prop_idx {
};
enum ulp_wp_sym {
+ ULP_WP_SYM_METADATA_OP_NORMAL = 0,
+ ULP_WP_SYM_METADATA_OP_L2_HASH = 0,
+ ULP_WP_SYM_METADATA_OP_L4_HASH = 0,
+ ULP_WP_SYM_FWD_OP_BYPASS_CFA = 0,
+ ULP_WP_SYM_FWD_OP_BYPASS_CFA_ROCE = 0,
+ ULP_WP_SYM_FWD_OP_BYPASS_LKUP = 0,
+ ULP_WP_SYM_FWD_OP_NORMAL_FLOW = 0,
ULP_WP_SYM_CTXT_OPCODE_BYPASS_CFA = 0,
ULP_WP_SYM_CTXT_OPCODE_BYPASS_LKUP = 0,
ULP_WP_SYM_CTXT_OPCODE_META_UPDATE = 0,
@@ -843,6 +869,10 @@ enum ulp_wp_sym {
ULP_WP_SYM_L4_HDR_IS_UDP_TCP_YES = 1,
ULP_WP_SYM_POP_VLAN_NO = 0,
ULP_WP_SYM_POP_VLAN_YES = 1,
+ ULP_WP_SYM_VLAN_DEL_RPT_DISABLED = 0,
+ ULP_WP_SYM_VLAN_DEL_RPT_STRIP_OUTER = 0,
+ ULP_WP_SYM_VLAN_DEL_RPT_STRIP_BOTH = 0,
+ ULP_WP_SYM_VLAN_DEL_RPT_DYN_STRIP = 0,
ULP_WP_SYM_DECAP_FUNC_NONE = 0,
ULP_WP_SYM_DECAP_FUNC_THRU_TL2 = 3,
ULP_WP_SYM_DECAP_FUNC_THRU_TL3 = 8,
@@ -916,6 +946,13 @@ enum ulp_wp_sym {
};
enum ulp_thor_sym {
+ ULP_THOR_SYM_METADATA_OP_NORMAL = 0,
+ ULP_THOR_SYM_METADATA_OP_L2_HASH = 1,
+ ULP_THOR_SYM_METADATA_OP_L4_HASH = 2,
+ ULP_THOR_SYM_FWD_OP_BYPASS_CFA = 0,
+ ULP_THOR_SYM_FWD_OP_BYPASS_CFA_ROCE = 1,
+ ULP_THOR_SYM_FWD_OP_BYPASS_LKUP = 2,
+ ULP_THOR_SYM_FWD_OP_NORMAL_FLOW = 3,
ULP_THOR_SYM_CTXT_OPCODE_BYPASS_CFA = 0,
ULP_THOR_SYM_CTXT_OPCODE_BYPASS_LKUP = 1,
ULP_THOR_SYM_CTXT_OPCODE_META_UPDATE = 2,
@@ -1066,6 +1103,10 @@ enum ulp_thor_sym {
ULP_THOR_SYM_L4_HDR_IS_UDP_TCP_YES = 1,
ULP_THOR_SYM_POP_VLAN_NO = 0,
ULP_THOR_SYM_POP_VLAN_YES = 1,
+ ULP_THOR_SYM_VLAN_DEL_RPT_DISABLED = 0,
+ ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER = 1,
+ ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_BOTH = 2,
+ ULP_THOR_SYM_VLAN_DEL_RPT_DYN_STRIP = 3,
ULP_THOR_SYM_DECAP_FUNC_NONE = 0,
ULP_THOR_SYM_DECAP_FUNC_THRU_TL2 = 3,
ULP_THOR_SYM_DECAP_FUNC_THRU_TL3 = 8,
@@ -1122,7 +1163,7 @@ enum ulp_thor_sym {
ULP_THOR_SYM_ACT_REC_POP_VLAN_NO = 0,
ULP_THOR_SYM_ACT_REC_METER_EN_YES = 1,
ULP_THOR_SYM_ACT_REC_METER_EN_NO = 0,
- ULP_THOR_SYM_LOOPBACK_PORT = 3,
+ ULP_THOR_SYM_LOOPBACK_PORT = 16,
ULP_THOR_SYM_LOOPBACK_PARIF = 15,
ULP_THOR_SYM_EXT_EM_MAX_KEY_SIZE = 0,
ULP_THOR_SYM_MATCH_TYPE_EM = 0,
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
index 68f1b5fd00..3d1e95d18c 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 20 11:56:39 2021 */
+/* date: Thu Jul 8 08:44:00 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -187,6 +187,10 @@ const struct bnxt_ulp_template_device_tbls ulp_template_thor_tbls[] = {
.tmpl_list_size = ULP_THOR_ACT_TMPL_LIST_SIZE,
.tbl_list = ulp_thor_act_tbl_list,
.tbl_list_size = ULP_THOR_ACT_TBL_LIST_SIZE,
+ .key_info_list = ulp_thor_act_key_info_list,
+ .key_info_list_size = ULP_THOR_ACT_KEY_INFO_LIST_SIZE,
+ .ident_list = ulp_thor_act_ident_list,
+ .ident_list_size = ULP_THOR_ACT_IDENT_LIST_SIZE,
.cond_list = ulp_thor_act_cond_list,
.cond_list_size = ULP_THOR_ACT_COND_LIST_SIZE,
.result_field_list = ulp_thor_act_result_field_list,
@@ -202,6 +206,7 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE,
.encap_byte_order = BNXT_ULP_BYTE_ORDER_BE,
.wc_key_byte_order = BNXT_ULP_BYTE_ORDER_BE,
+ .em_byte_order = BNXT_ULP_BYTE_ORDER_LE,
.encap_byte_swap = 1,
.int_flow_db_num_entries = 16384,
.ext_flow_db_num_entries = 32768,
@@ -225,11 +230,12 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE,
.encap_byte_order = BNXT_ULP_BYTE_ORDER_BE,
.wc_key_byte_order = BNXT_ULP_BYTE_ORDER_BE,
+ .em_byte_order = BNXT_ULP_BYTE_ORDER_BE,
.encap_byte_swap = 1,
.int_flow_db_num_entries = 16384,
.ext_flow_db_num_entries = 32768,
- .mark_db_lfid_entries = 0,
- .mark_db_gfid_entries = 0,
+ .mark_db_lfid_entries = 65536,
+ .mark_db_gfid_entries = 65536,
.flow_count_db_entries = 16384,
.fdb_parent_flow_entries = 2,
.num_resources_per_flow = 8,
@@ -909,6 +915,14 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = {
{
.app_id = 0,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
@@ -941,12 +955,156 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = {
{
.app_id = 0,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
.direction = TF_DIR_RX
},
{
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
.app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1204,7 +1362,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 63
+ .count = 15
},
{
.app_id = 0,
@@ -1666,6 +1824,14 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.app_id = 0,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
.count = 200
@@ -1703,6 +1869,14 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 15232
},
{
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .count = 1
+ },
+ {
.app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
index 9faf25aaf0..223ecbf843 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Wed May 26 15:11:34 2021 */
+/* date: Thu Jul 8 08:44:00 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -15,16 +15,88 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {
/* act_tid: 1, ingress */
[1] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 2,
+ .num_tbls = 4,
.start_tbl_idx = 0,
.reject_info = {
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
.cond_start_idx = 0,
- .cond_nums = 4 }
+ .cond_nums = 0 }
+ },
+ /* act_tid: 2, ingress */
+ [2] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 6,
+ .start_tbl_idx = 4,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 3,
+ .cond_nums = 0 }
+ },
+ /* act_tid: 3, ingress */
+ [3] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 4,
+ .start_tbl_idx = 10,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 4,
+ .cond_nums = 0 }
+ },
+ /* act_tid: 4, egress */
+ [4] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 4,
+ .start_tbl_idx = 14,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 7,
+ .cond_nums = 0 }
+ },
+ /* act_tid: 5, egress */
+ [5] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 4,
+ .start_tbl_idx = 18,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 10,
+ .cond_nums = 0 }
+ },
+ /* act_tid: 6, egress */
+ [6] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 6,
+ .start_tbl_idx = 22,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 13,
+ .cond_nums = 0 }
}
};
struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
+ { /* act_tid: 1, , table: shared_mirror_record.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 0,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .key_start_idx = 0,
+ .blob_key_bit_size = 1,
+ .key_bit_size = 1,
+ .key_num_fields = 1,
+ .ident_start_idx = 0,
+ .ident_nums = 1
+ },
{ /* act_tid: 1, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
@@ -35,7 +107,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 4,
+ .cond_start_idx = 1,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
@@ -45,73 +117,4205 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.result_bit_size = 64,
.result_num_fields = 1
},
- { /* act_tid: 1, , table: int_full_act_record.0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 0,
- .cond_false_goto = 0,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 5,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 1,
- .result_bit_size = 128,
- .result_num_fields = 17
- }
-};
-
-struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = {
- /* cond_reject: thor, act_tid: 1 */
+ { /* act_tid: 1, , table: mod_record.ing_ttl */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 2,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 1,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 1, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 3,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 48,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* act_tid: 2, , table: control.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 3,
+ .cond_nums = 0 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* act_tid: 2, , table: mirror_tbl.alloc */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 3,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 65,
+ .result_bit_size = 32,
+ .result_num_fields = 5
+ },
+ { /* act_tid: 2, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 3,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 70,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 2, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 4,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 71,
+ .result_bit_size = 128,
+ .result_num_fields = 17,
+ .encap_num_fields = 0
+ },
+ { /* act_tid: 2, , table: mirror_tbl.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 4,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 88,
+ .result_bit_size = 32,
+ .result_num_fields = 5
+ },
+ { /* act_tid: 2, , table: shared_mirror_record.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 4,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .key_start_idx = 1,
+ .blob_key_bit_size = 1,
+ .key_bit_size = 1,
+ .key_num_fields = 1,
+ .result_start_idx = 93,
+ .result_bit_size = 36,
+ .result_num_fields = 2
+ },
+ { /* act_tid: 3, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 4,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 95,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 3, , table: mod_record.ing_ttl */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 5,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 96,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 3, , table: mod_record.ing_no_ttl */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 6,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 143,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 3, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 7,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 190,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* act_tid: 4, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 7,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 207,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 4, , table: int_vtag_encap_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 8,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 8,
+ .result_start_idx = 208,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 11
+ },
+ { /* act_tid: 4, , table: mod_record.dec_ttl_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 9,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 219,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 4, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 10,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 266,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* act_tid: 5, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 10,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 283,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 5, , table: mod_record.ing_ttl */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 11,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 284,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 5, , table: mod_record.ing_no_ttl */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 12,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 331,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 5, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 13,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 378,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* act_tid: 6, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 13,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 395,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 6, , table: sp_smac_ipv4.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 14,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 16,
+ .result_start_idx = 396,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 3
+ },
+ { /* act_tid: 6, , table: sp_smac_ipv6.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 15,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 32,
+ .result_start_idx = 399,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 3
+ },
+ { /* act_tid: 6, , table: int_tun_encap_record.ipv4_vxlan */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 16,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 402,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 30
+ },
+ { /* act_tid: 6, , table: int_tun_encap_record.ipv6_vxlan */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 18,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 432,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 30
+ },
+ { /* act_tid: 6, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 20,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 462,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ }
+};
+
+struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = {
+ /* cond_execute: act_tid: 1, shared_mirror_record.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+ },
+ /* cond_execute: act_tid: 1, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 1, mod_record.ing_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 2, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 3, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 3, mod_record.ing_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 3, mod_record.ing_no_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 4, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 4, int_vtag_encap_record.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
+ },
+ /* cond_execute: act_tid: 4, mod_record.dec_ttl_egr */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 5, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 5, mod_record.ing_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 5, mod_record.ing_no_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 6, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 6, sp_smac_ipv4.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG
+ },
+ /* cond_execute: act_tid: 6, sp_smac_ipv6.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG
+ },
+ /* cond_execute: act_tid: 6, int_tun_encap_record.ipv4_vxlan */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: act_tid: 6, int_tun_encap_record.ipv6_vxlan */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ }
+};
+
+struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = {
+ /* act_tid: 1, , table: shared_mirror_record.rd */
+ {
+ .field_info_mask = {
+ .description = "shared_index",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "shared_index",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff}
+ }
+ },
+ /* act_tid: 2, , table: shared_mirror_record.wr */
+ {
+ .field_info_mask = {
+ .description = "shared_index",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "shared_index",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
+ }
+ }
+};
+
+struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
+ /* act_tid: 1, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 1, , table: mod_record.ing_ttl */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ /* act_tid: 1, , table: int_full_act_record.0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr2 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_DECAP_FUNC_THRU_TUN},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_DECAP_FUNC_NONE}
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr2 = {
+ (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 2, , table: mirror_tbl.alloc */
+ {
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 13,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ignore_drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "copy_ing_or_egr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "enable",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 2, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 2, , table: int_full_act_record.0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 2, , table: mirror_tbl.wr */
+ {
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 13,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ignore_drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "copy_ing_or_egr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "enable",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 2, , table: shared_mirror_record.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "mirror_id",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
+ },
+ /* act_tid: 3, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 3, , table: mod_record.ing_ttl */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ /* act_tid: 3, , table: mod_record.ing_no_ttl */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ /* act_tid: 3, , table: int_full_act_record.0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 4, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 4, , table: int_vtag_encap_record.0 */
+ {
+ .description = "ecv_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
+ },
+ {
+ .description = "ecv_l2_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vtag_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}
+ },
+ {
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
+ },
+ {
+ .description = "vtag_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vtag_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
+ },
+ /* act_tid: 4, , table: mod_record.dec_ttl_egr */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ /* act_tid: 4, , table: int_full_act_record.0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
+ },
+ {
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 5, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 5, , table: mod_record.ing_ttl */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ /* act_tid: 5, , table: mod_record.ing_no_ttl */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ /* act_tid: 5, , table: int_full_act_record.0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 6, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 6, , table: sp_smac_ipv4.0 */
+ {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
+ },
+ {
+ .description = "ipv4_src_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 6, , table: sp_smac_ipv6.0 */
+ {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
+ },
+ {
+ .description = "ipv6_src_addr",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_SADDR & 0xff}
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 6, , table: int_tun_encap_record.ipv4_vxlan */
+ {
+ .description = "ecv_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_VALID_YES}
+ },
+ {
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
+ },
+ {
+ .description = "ecv_l2_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_L2_EN_YES}
+ },
+ {
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
+ },
+ {
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_L4_TYPE_UDP_CSUM}
+ },
+ {
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_TUN_TYPE_VXLAN}
+ },
+ {
+ .description = "enc_eth_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
+ },
+ {
+ .description = "enc_o_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_o_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_ihl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff}
+ },
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_POP_VLAN
+ .description = "enc_ipv4_tos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff}
},
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ .description = "enc_ipv4_pkt_id",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff}
},
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_VXLAN_DECAP
+ .description = "enc_ipv4_frag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff}
},
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+ .description = "enc_ipv4_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff}
},
- /* cond_execute: act_tid: 1, int_flow_counter_tbl.0 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_COUNT
- }
-};
-
-struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
- /* act_tid: 1, , table: int_flow_counter_tbl.0 */
+ .description = "enc_ipv4_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff}
+ },
{
- .description = "count",
- .field_bit_size = 64,
+ .description = "enc_ipv4_daddr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}
+ },
+ {
+ .description = "enc_ipv6_vtc",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv6_zero",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv6_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv6_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv6_daddr",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
+ },
+ {
+ .description = "enc_udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
+ },
+ {
+ .description = "enc_vxlan_flags",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}
+ },
+ {
+ .description = "enc_vxlan_rsvd0",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}
+ },
+ {
+ .description = "enc_vxlan_vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
+ },
+ {
+ .description = "enc_vxlan_rsvd1",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}
+ },
+ /* act_tid: 6, , table: int_tun_encap_record.ipv6_vxlan */
+ {
+ .description = "ecv_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_VALID_YES}
+ },
+ {
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 1, , table: int_full_act_record.0 */
{
- .description = "sp_rec_ptr",
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
+ },
+ {
+ .description = "ecv_l2_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_L2_EN_YES}
+ },
+ {
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
+ },
+ {
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_L4_TYPE_UDP_CSUM}
+ },
+ {
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_TUN_TYPE_VXLAN}
+ },
+ {
+ .description = "enc_eth_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
+ },
+ {
+ .description = "enc_o_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_o_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_ihl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv4_tos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv4_pkt_id",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv4_frag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv4_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv4_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv4_daddr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv6_vtc",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff}
+ },
+ {
+ .description = "enc_ipv6_zero",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
+ .description = "enc_ipv6_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff}
+ },
+ {
+ .description = "enc_ipv6_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff}
+ },
+ {
+ .description = "enc_ipv6_daddr",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff}
+ },
+ {
+ .description = "enc_udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
+ },
+ {
+ .description = "enc_udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
+ },
+ {
+ .description = "enc_vxlan_flags",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}
+ },
+ {
+ .description = "enc_vxlan_rsvd0",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}
+ },
+ {
+ .description = "enc_vxlan_vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
+ },
+ {
+ .description = "enc_vxlan_rsvd1",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}
+ },
+ /* act_tid: 6, , table: int_full_act_record.0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_SP_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_SP_PTR & 0xff}
+ },
+ {
.description = "encap_ptr",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
},
{
.description = "mod_rec_ptr",
@@ -164,8 +4368,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
},
{
.description = "use_default",
@@ -195,16 +4399,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "drop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "hit",
@@ -221,3 +4416,13 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
1}
}
};
+
+struct bnxt_ulp_mapper_ident_info ulp_thor_act_ident_list[] = {
+ /* act_tid: 1, , table: shared_mirror_record.rd */
+ {
+ .description = "mirror_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_MIRROR_ID_0,
+ .ident_bit_size = 4,
+ .ident_bit_pos = 32
+ }
+};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
index ea9b9773a5..bcb204ae13 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Wed May 26 15:11:34 2021 */
+/* date: Fri Jul 30 09:57:44 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -15,32 +15,52 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {
/* class_tid: 1, ingress */
[1] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 12,
+ .num_tbls = 28,
.start_tbl_idx = 0,
.reject_info = {
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 0,
- .cond_nums = 4 }
+ .cond_nums = 1 }
+ },
+ /* class_tid: 2, ingress */
+ [2] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 17,
+ .start_tbl_idx = 28,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 29,
+ .cond_nums = 0 }
+ },
+ /* class_tid: 3, egress */
+ [3] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 24,
+ .start_tbl_idx = 45,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 36,
+ .cond_nums = 0 }
},
/* class_tid: 4, ingress */
[4] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 15,
- .start_tbl_idx = 12,
+ .num_tbls = 21,
+ .start_tbl_idx = 69,
.reject_info = {
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 8,
- .cond_nums = 1 }
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 }
},
/* class_tid: 5, egress */
[5] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 6,
- .start_tbl_idx = 27,
+ .num_tbls = 24,
+ .start_tbl_idx = 90,
.reject_info = {
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 12,
- .cond_nums = 1 }
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 }
}
};
@@ -54,7 +74,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 4,
+ .cond_start_idx = 1,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
@@ -76,7 +96,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 5,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 4,
+ .cond_start_idx = 1,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
@@ -97,7 +117,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 5,
+ .cond_start_idx = 2,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
@@ -116,7 +136,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 3,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 5,
+ .cond_start_idx = 2,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
@@ -129,7 +149,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 6,
+ .cond_start_idx = 3,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
@@ -156,7 +176,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 6,
+ .cond_start_idx = 3,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
@@ -169,17 +189,28 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 1, , table: profile_tcam_cache.l3_l4_rd */
+ { /* class_tid: 1, , table: control.ipv6_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 8,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 3,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* class_tid: 1, , table: profile_tcam_cache.ipv6_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 6,
- .cond_nums = 0 },
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 4,
+ .cond_nums = 1 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
@@ -188,23 +219,41 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.key_bit_size = 14,
.key_num_fields = 3,
.ident_start_idx = 6,
- .ident_nums = 0
+ .ident_nums = 4
},
- { /* class_tid: 1, , table: control.l3_l4 */
+ { /* class_tid: 1, , table: control.ipv6_prof_cache_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 4,
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 6,
+ .cond_start_idx = 5,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 1, , table: fkb_select.l3_l4_wm */
+ { /* class_tid: 1, , table: control.v6_conflict_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 4,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 6,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .func_info = {
+ .func_opc = BNXT_ULP_FUNC_OPC_EQ,
+ .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
+ .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
+ .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
+ },
+ { /* class_tid: 1, , table: fkb_select.l2_l3_l4_v6_em */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
@@ -212,23 +261,24 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 7,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
- .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
.result_start_idx = 10,
.result_bit_size = 106,
.result_num_fields = 106
},
- { /* class_tid: 1, , table: profile_tcam.l3_l4 */
+ { /* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 7,
- .cond_nums = 0 },
+ .cond_nums = 1 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
@@ -244,11 +294,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_start_idx = 116,
.result_bit_size = 33,
.result_num_fields = 8,
- .ident_start_idx = 6,
- .ident_nums = 0
+ .ident_start_idx = 10,
+ .ident_nums = 1
},
- { /* class_tid: 1, , table: profile_tcam_cache.l3_l4_wr */
+ { /* class_tid: 1, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_RX,
@@ -256,7 +307,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 7,
+ .cond_start_idx = 8,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
@@ -269,4026 +320,39779 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 138,
.result_num_fields = 7
},
- { /* class_tid: 1, , table: wm.l3_l4 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ { /* class_tid: 1, , table: em.l2_l3_l4_v6.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_INTERNAL,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 0,
- .cond_false_goto = 0,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 7,
- .cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 8,
+ .cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
- .pri_operand = 0,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.key_start_idx = 82,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
.result_start_idx = 131,
- .result_bit_size = 38,
- .result_num_fields = 5
+ .result_bit_size = 0,
+ .result_num_fields = 6
},
- { /* class_tid: 4, , table: int_full_act_record.0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ { /* class_tid: 1, , table: profile_tcam_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 9,
+ .cond_start_idx = 8,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 136,
- .result_bit_size = 128,
- .result_num_fields = 17
+ .key_start_idx = 196,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .ident_start_idx = 11,
+ .ident_nums = 2
},
- { /* class_tid: 4, , table: port_table.wr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
+ { /* class_tid: 1, , table: control.gen_tbl_miss */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 9,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 196,
- .blob_key_bit_size = 10,
- .key_bit_size = 10,
- .key_num_fields = 1,
- .result_start_idx = 153,
- .result_bit_size = 152,
- .result_num_fields = 5
+ .cond_false_goto = 6,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 8,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ { /* class_tid: 1, , table: fkb_select.l3_l4_wm */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 9,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 197,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .ident_start_idx = 6,
- .ident_nums = 0
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 137,
+ .result_bit_size = 106,
+ .result_num_fields = 106
},
- { /* class_tid: 4, , table: control.ing_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ { /* class_tid: 1, , table: fkb_select.l3_l4_wm_vxlan */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 3,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 9,
+ .cond_start_idx = 10,
.cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 243,
+ .result_bit_size = 106,
+ .result_num_fields = 106
},
- { /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
+ { /* class_tid: 1, , table: profile_tcam.l3_l4.ip */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 11,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 199,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 349,
+ .result_bit_size = 33,
+ .result_num_fields = 8,
+ .ident_start_idx = 13,
+ .ident_nums = 0
+ },
+ { /* class_tid: 1, , table: profile_tcam.l3_l4.vxlan */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 10,
- .cond_nums = 0 },
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 13,
+ .cond_nums = 1 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 198,
- .blob_key_bit_size = 213,
- .key_bit_size = 213,
- .key_num_fields = 21,
- .result_start_idx = 158,
- .result_bit_size = 43,
- .result_num_fields = 6,
- .ident_start_idx = 6,
- .ident_nums = 1
+ .key_start_idx = 242,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 357,
+ .result_bit_size = 33,
+ .result_num_fields = 8,
+ .ident_start_idx = 13,
+ .ident_nums = 0
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
+ { /* class_tid: 1, , table: profile_tcam_cache.wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 10,
+ .cond_start_idx = 14,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 219,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .result_start_idx = 164,
- .result_bit_size = 62,
- .result_num_fields = 4
+ .key_start_idx = 285,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .result_start_idx = 365,
+ .result_bit_size = 138,
+ .result_num_fields = 7
},
- { /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+ { /* class_tid: 1, , table: wm.l3_l4.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 10,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 168,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 14,
+ .cond_nums = 3 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 288,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 372,
+ .result_bit_size = 38,
+ .result_num_fields = 5
},
- { /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
- .direction = TF_DIR_RX,
+ { /* class_tid: 1, , table: wm.l3_l4.ipv6 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 10,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 169,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 17,
+ .cond_nums = 3 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 402,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 377,
+ .result_bit_size = 38,
+ .result_num_fields = 5
},
- { /* class_tid: 4, , table: control.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ { /* class_tid: 1, , table: wm.l3.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 0,
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 10,
+ .cond_start_idx = 20,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 516,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 382,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 1, , table: wm.l3.ipv6 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 22,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 630,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 387,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 1, , table: wm.l2 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 24,
.cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 744,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 392,
+ .result_bit_size = 38,
+ .result_num_fields = 5
},
- { /* class_tid: 4, , table: int_full_act_record.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ { /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 25,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 858,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 397,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv6 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 27,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 972,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 402,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 2, , table: port_table.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 11,
+ .cond_start_idx = 29,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 170,
- .result_bit_size = 128,
- .result_num_fields = 17,
- .encap_num_fields = 0
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .key_start_idx = 1086,
+ .blob_key_bit_size = 10,
+ .key_bit_size = 10,
+ .key_num_fields = 1,
+ .ident_start_idx = 13,
+ .ident_nums = 3
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */
+ { /* class_tid: 2, , table: tunnel_cache.rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 11,
+ .cond_start_idx = 29,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 220,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .ident_start_idx = 7,
- .ident_nums = 0
+ .key_start_idx = 1087,
+ .blob_key_bit_size = 16,
+ .key_bit_size = 16,
+ .key_num_fields = 2,
+ .ident_start_idx = 16,
+ .ident_nums = 1
},
- { /* class_tid: 4, , table: control.egr_1 */
+ { /* class_tid: 2, , table: control.tunnel_cache_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 2,
+ .cond_false_goto = 3,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 11,
+ .cond_start_idx = 29,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
+ { /* class_tid: 2, , table: l2_cntxt_tcam.1 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .direction = TF_DIR_TX,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 12,
+ .cond_start_idx = 30,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT,
.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 221,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .key_start_idx = 1089,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
- .result_start_idx = 187,
+ .result_start_idx = 407,
.result_bit_size = 43,
.result_num_fields = 6,
- .ident_start_idx = 7,
+ .ident_start_idx = 17,
.ident_nums = 1
},
- { /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
- .direction = TF_DIR_TX,
+ { /* class_tid: 2, , table: tunnel_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 12,
+ .cond_start_idx = 30,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 193,
- .result_bit_size = 32,
- .result_num_fields = 1
- },
- { /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
- .direction = TF_DIR_TX,
+ .key_start_idx = 1110,
+ .blob_key_bit_size = 16,
+ .key_bit_size = 16,
+ .key_num_fields = 2,
+ .result_start_idx = 413,
+ .result_bit_size = 52,
+ .result_num_fields = 3
+ },
+ { /* class_tid: 2, , table: control.flow_type_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 0,
- .cond_false_goto = 0,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 12,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 194,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .cond_true_goto = 1,
+ .cond_false_goto = 5,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 30,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
- { /* class_tid: 5, , table: int_full_act_record.loopback */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ { /* class_tid: 2, , table: mac_addr_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 13,
+ .cond_start_idx = 31,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE,
- .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 195,
- .result_bit_size = 128,
- .result_num_fields = 17,
- .encap_num_fields = 0
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1112,
+ .blob_key_bit_size = 73,
+ .key_bit_size = 73,
+ .key_num_fields = 5,
+ .ident_start_idx = 18,
+ .ident_nums = 1
},
- { /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
- .direction = TF_DIR_TX,
+ { /* class_tid: 2, , table: control.mac_addr_cache_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 31,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 2, , table: l2_cntxt_tcam.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 13,
+ .cond_start_idx = 32,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
- .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 212,
- .result_bit_size = 32,
- .result_num_fields = 1
- },
- { /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
- .direction = TF_DIR_TX,
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .key_start_idx = 1117,
+ .blob_key_bit_size = 213,
+ .key_bit_size = 213,
+ .key_num_fields = 21,
+ .result_start_idx = 416,
+ .result_bit_size = 43,
+ .result_num_fields = 6,
+ .ident_start_idx = 19,
+ .ident_nums = 0
+ },
+ { /* class_tid: 2, , table: mac_addr_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 13,
+ .cond_start_idx = 32,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
- .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 213,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .key_start_idx = 1138,
+ .blob_key_bit_size = 73,
+ .key_bit_size = 73,
+ .key_num_fields = 5,
+ .result_start_idx = 422,
+ .result_bit_size = 62,
+ .result_num_fields = 4
},
- { /* class_tid: 5, , table: int_full_act_record.vf_ing */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 13,
+ .cond_start_idx = 32,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
- .result_start_idx = 214,
- .result_bit_size = 128,
- .result_num_fields = 17,
- .encap_num_fields = 0
+ .key_start_idx = 1143,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .ident_start_idx = 19,
+ .ident_nums = 3
+ },
+ { /* class_tid: 2, , table: control.profile_tcam_cache.f2_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 4,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 32,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 5, , table: vtag_encap_record.vfr_egr0 */
+ { /* class_tid: 2, , table: fkb_select.f2_wm */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 33,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 426,
+ .result_bit_size = 106,
+ .result_num_fields = 106
+ },
+ { /* class_tid: 2, , table: profile_tcam.f2 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 34,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 1,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 1146,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 532,
+ .result_bit_size = 33,
+ .result_num_fields = 8
+ },
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 13,
+ .cond_start_idx = 34,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1189,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .result_start_idx = 540,
+ .result_bit_size = 138,
+ .result_num_fields = 7
+ },
+ { /* class_tid: 2, , table: wm.l3_l4.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 34,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .record_size = 16,
- .result_start_idx = 231,
- .result_bit_size = 0,
- .result_num_fields = 0,
- .encap_num_fields = 11
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 1192,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 547,
+ .result_bit_size = 38,
+ .result_num_fields = 5
},
- { /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
+ { /* class_tid: 2, , table: wm.l3_l4.ipv6 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 0,
.cond_false_goto = 0,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 13,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 35,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 242,
- .result_bit_size = 128,
- .result_num_fields = 17
- }
-};
-
-struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {
- /* cond_reject: thor, class_tid: 1 */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
- .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 1306,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 552,
+ .result_bit_size = 38,
+ .result_num_fields = 5
},
- {
- .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET,
- .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC
+ { /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 6,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 36,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1420,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 22,
+ .ident_nums = 1
},
- {
- .cond_opcode = BNXT_ULP_COND_OPC_FLOW_PAT_MATCH,
- .cond_operand = 2
+ { /* class_tid: 3, , table: mac_addr_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 37,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1421,
+ .blob_key_bit_size = 73,
+ .key_bit_size = 73,
+ .key_num_fields = 5,
+ .ident_start_idx = 23,
+ .ident_nums = 1
},
- {
- .cond_opcode = BNXT_ULP_COND_OPC_FLOW_PAT_MATCH,
- .cond_operand = 3
+ { /* class_tid: 3, , table: control.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 4,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 37,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
- /* cond_execute: class_tid: 1, l2_cntxt_tcam_cache.rd */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET,
- .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC
+ { /* class_tid: 3, , table: port_table.egr.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 38,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .key_start_idx = 1426,
+ .blob_key_bit_size = 10,
+ .key_bit_size = 10,
+ .key_num_fields = 1,
+ .ident_start_idx = 24,
+ .ident_nums = 3
},
- /* cond_execute: class_tid: 1, control.0 */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
- .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ { /* class_tid: 3, , table: l2_cntxt_tcam.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 38,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .key_start_idx = 1427,
+ .blob_key_bit_size = 213,
+ .key_bit_size = 213,
+ .key_num_fields = 21,
+ .result_start_idx = 557,
+ .result_bit_size = 43,
+ .result_num_fields = 6,
+ .ident_start_idx = 27,
+ .ident_nums = 1
},
- /* cond_execute: class_tid: 1, control.l3_l4 */
- {
+ { /* class_tid: 3, , table: mac_addr_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 38,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1448,
+ .blob_key_bit_size = 73,
+ .key_bit_size = 73,
+ .key_num_fields = 5,
+ .result_start_idx = 563,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 3, , table: control.ipv6_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 8,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 38,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* class_tid: 3, , table: profile_tcam_cache.ipv6_rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 39,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1453,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .ident_start_idx = 28,
+ .ident_nums = 4
+ },
+ { /* class_tid: 3, , table: control.ipv6_prof_cache_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 40,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 3, , table: control.v6_conflict_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 4,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 41,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .func_info = {
+ .func_opc = BNXT_ULP_FUNC_OPC_EQ,
+ .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
+ .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
+ .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
+ },
+ { /* class_tid: 3, , table: fkb_select.l2_l3_l4_v6_em */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 42,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .result_start_idx = 567,
+ .result_bit_size = 106,
+ .result_num_fields = 106
+ },
+ { /* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 42,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 1456,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 673,
+ .result_bit_size = 33,
+ .result_num_fields = 8,
+ .ident_start_idx = 32,
+ .ident_nums = 1
+ },
+ { /* class_tid: 3, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 42,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1499,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .result_start_idx = 681,
+ .result_bit_size = 138,
+ .result_num_fields = 7
+ },
+ { /* class_tid: 3, , table: em.l2_l3_l4_v6.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_INTERNAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 42,
+ .cond_nums = 0 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 1502,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 688,
+ .result_bit_size = 0,
+ .result_num_fields = 6
+ },
+ { /* class_tid: 3, , table: profile_tcam_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 42,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1616,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .ident_start_idx = 33,
+ .ident_nums = 2
+ },
+ { /* class_tid: 3, , table: control.gen_tbl_miss */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 42,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 3, , table: control.conflict_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 5,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 43,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .func_info = {
+ .func_opc = BNXT_ULP_FUNC_OPC_EQ,
+ .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
+ .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
+ .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
+ },
+ { /* class_tid: 3, , table: fkb_select.l3_l4_wc */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 44,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 694,
+ .result_bit_size = 106,
+ .result_num_fields = 106
+ },
+ { /* class_tid: 3, , table: profile_tcam.l3_l4.ip */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 44,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 1619,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 800,
+ .result_bit_size = 33,
+ .result_num_fields = 8,
+ .ident_start_idx = 35,
+ .ident_nums = 0
+ },
+ { /* class_tid: 3, , table: profile_tcam.l3_l4.nonip */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 45,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 1662,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 808,
+ .result_bit_size = 33,
+ .result_num_fields = 8,
+ .ident_start_idx = 35,
+ .ident_nums = 0
+ },
+ { /* class_tid: 3, , table: profile_tcam_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 45,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1705,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .result_start_idx = 816,
+ .result_bit_size = 138,
+ .result_num_fields = 7
+ },
+ { /* class_tid: 3, , table: wm.l3_l4.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 45,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 1708,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 823,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 3, , table: wm.l3.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 47,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 1822,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 828,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 3, , table: wm.l2 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 1936,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 833,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 4, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 838,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* class_tid: 4, , table: port_table.ing_wr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2050,
+ .blob_key_bit_size = 10,
+ .key_bit_size = 10,
+ .key_num_fields = 1,
+ .result_start_idx = 855,
+ .result_bit_size = 152,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2051,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 35,
+ .ident_nums = 0
+ },
+ { /* class_tid: 4, , table: control.ing_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 48,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 2052,
+ .blob_key_bit_size = 213,
+ .key_bit_size = 213,
+ .key_num_fields = 21,
+ .result_start_idx = 860,
+ .result_bit_size = 43,
+ .result_num_fields = 6,
+ .ident_start_idx = 35,
+ .ident_nums = 1
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2073,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 866,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 870,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 871,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 4, , table: int_full_act_record.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 872,
+ .result_bit_size = 128,
+ .result_num_fields = 17,
+ .encap_num_fields = 0
+ },
+ { /* class_tid: 4, , table: port_table.egr_wr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2074,
+ .blob_key_bit_size = 10,
+ .key_bit_size = 10,
+ .key_num_fields = 1,
+ .result_start_idx = 889,
+ .result_bit_size = 152,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 4, , table: control.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 5,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 49,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd_vfr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 50,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2075,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 36,
+ .ident_nums = 0
+ },
+ { /* class_tid: 4, , table: control.egr_1 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 50,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 4, , table: ilt_tbl.egr_vfr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_ILT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 51,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .result_start_idx = 894,
+ .result_bit_size = 64,
+ .result_num_fields = 8
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 51,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2076,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 902,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 51,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2077,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 36,
+ .ident_nums = 0
+ },
+ { /* class_tid: 4, , table: control.egr_2 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 51,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 2078,
+ .blob_key_bit_size = 213,
+ .key_bit_size = 213,
+ .key_num_fields = 21,
+ .result_start_idx = 906,
+ .result_bit_size = 43,
+ .result_num_fields = 6,
+ .ident_start_idx = 36,
+ .ident_nums = 1
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2099,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 912,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 916,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 917,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 5, , table: int_full_act_record.loopback */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 918,
+ .result_bit_size = 128,
+ .result_num_fields = 17,
+ .encap_num_fields = 0
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2100,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 37,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: control.vf_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 52,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 53,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .key_start_idx = 2101,
+ .blob_key_bit_size = 213,
+ .key_bit_size = 213,
+ .key_num_fields = 21,
+ .result_start_idx = 935,
+ .result_bit_size = 43,
+ .result_num_fields = 6,
+ .ident_start_idx = 37,
+ .ident_nums = 1
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 53,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2122,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 941,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 53,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
+ .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 945,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 53,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
+ .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 946,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 5, , table: int_full_act_record.vf_ing */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 53,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
+ .result_start_idx = 947,
+ .result_bit_size = 128,
+ .result_num_fields = 17,
+ .encap_num_fields = 0
+ },
+ { /* class_tid: 5, , table: ilt_tbl.vf_ing */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_ILT,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 53,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_SVIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 964,
+ .result_bit_size = 64,
+ .result_num_fields = 8
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.rd_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 53,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2123,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 38,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: control.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 53,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 5, , table: ilt_tbl.vfr_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_ILT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .result_start_idx = 972,
+ .result_bit_size = 64,
+ .result_num_fields = 8
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2124,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 980,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 5, , table: metadata_record.vfr_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 984,
+ .result_bit_size = 16,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 5, , table: mod_record.vfr_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 985,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* class_tid: 5, , table: int_full_act_record.vfr_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 1032,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_rd_vfr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2125,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 38,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: control.ing_rd_vfr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 5,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 54,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam.vfr_ing0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 2126,
+ .blob_key_bit_size = 213,
+ .key_bit_size = 213,
+ .key_num_fields = 21,
+ .result_start_idx = 1049,
+ .result_bit_size = 43,
+ .result_num_fields = 6,
+ .ident_start_idx = 38,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: fkb_select.vfr_em */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 1055,
+ .result_bit_size = 106,
+ .result_num_fields = 106
+ },
+ { /* class_tid: 5, , table: profile_tcam.vfr_ing0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 2147,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 1161,
+ .result_bit_size = 33,
+ .result_num_fields = 8
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_wr_vfr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2190,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 38,
+ .ident_nums = 1
+ },
+ { /* class_tid: 5, , table: int_full_act_record.vfr_ing0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 1169,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* class_tid: 5, , table: em.vfr.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_INTERNAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 2191,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 1186,
+ .result_bit_size = 0,
+ .result_num_fields = 6
+ }
+};
+
+struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {
+ /* cond_reject: thor, class_tid: 1 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH
+ },
+ /* cond_execute: class_tid: 1, l2_cntxt_tcam_cache.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC
+ },
+ /* cond_execute: class_tid: 1, control.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 1, control.ipv6_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ },
+ /* cond_execute: class_tid: 1, profile_tcam_cache.ipv6_rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH
+ },
+ /* cond_execute: class_tid: 1, control.ipv6_prof_cache_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 1, control.v6_conflict_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_CC
+ },
+ /* cond_execute: class_tid: 1, profile_tcam.l2_l3_l4_v6_em */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, control.gen_tbl_miss */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 1, fkb_select.l3_l4_wm */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, fkb_select.l3_l4_wm_vxlan */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, profile_tcam.l3_l4.ip */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_O_L3
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, profile_tcam.l3_l4.vxlan */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, wm.l3_l4.ipv4 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_O_L4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, wm.l3_l4.ipv6 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_O_L4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, wm.l3.ipv4 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, wm.l3.ipv6 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, wm.l2 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, wm.l3_l4.vxlan.ipv4 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ /* cond_execute: class_tid: 1, wm.l3_l4.vxlan.ipv6 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ },
+ /* cond_execute: class_tid: 2, control.tunnel_cache_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 2, control.flow_type_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_F1
+ },
+ /* cond_execute: class_tid: 2, control.mac_addr_cache_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 2, control.profile_tcam_cache.f2_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 2, fkb_select.f2_wm */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 2, wm.l3_l4.ipv4 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ /* cond_execute: class_tid: 2, wm.l3_l4.ipv6 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ },
+ /* cond_execute: class_tid: 3, l2_cntxt_tcam_cache.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC
+ },
+ /* cond_execute: class_tid: 3, control.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 3, control.ipv6_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ },
+ /* cond_execute: class_tid: 3, profile_tcam_cache.ipv6_rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH
+ },
+ /* cond_execute: class_tid: 3, control.ipv6_prof_cache_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 3, control.v6_conflict_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_CC
+ },
+ /* cond_execute: class_tid: 3, control.gen_tbl_miss */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 3, control.conflict_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_CC
+ },
+ /* cond_execute: class_tid: 3, profile_tcam.l3_l4.ip */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_O_L3
+ },
+ /* cond_execute: class_tid: 3, wm.l3_l4.ipv4 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_O_L4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ /* cond_execute: class_tid: 3, wm.l3.ipv4 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ /* cond_execute: class_tid: 4, control.ing_0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 4, control.egr_0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
+ },
+ /* cond_execute: class_tid: 4, control.egr_1 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 4, control.egr_2 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 5, control.vf_0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 5, control.0 */
+ {
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 1, wm.l3_l4 */
+ /* cond_execute: class_tid: 5, control.ing_rd_vfr */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ }
+};
+
+struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
+ /* class_tid: 1, , table: port_table.rd */
+ {
+ .field_info_mask = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: l2_cntxt_tcam_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: mac_addr_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: l2_cntxt_tcam.0 */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 2}
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 1, , table: mac_addr_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.ipv6_rd */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_UDP}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_YES},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_NO}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: em.l2_l3_l4_v6.0 */
+ {
+ .field_info_mask = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: profile_tcam.l3_l4.ip */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_UDP}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L4_HDR_VALID_YES},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L4_HDR_VALID_IGNORE}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV4},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_YES},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_NO}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 1, , table: profile_tcam.l3_l4.vxlan */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL4_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV4},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_TL2_VTAG_PRESENT_YES},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_TL2_VTAG_PRESENT_NO}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: wm.l3_l4.ipv4 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 1, , table: wm.l3_l4.ipv6 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 1, , table: wm.l3.ipv4 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 1, , table: wm.l3.ipv6 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 1, , table: wm.l2 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv4 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv6 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 2, , table: port_table.rd */
+ {
+ .field_info_mask = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: tunnel_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_TUNNEL_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_TUNNEL_ID & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 2, , table: tunnel_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_TUNNEL_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_TUNNEL_ID & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: mac_addr_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: l2_cntxt_tcam.0 */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 2}
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 2, , table: mac_addr_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: profile_tcam.f2 */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL4_HDR_TYPE_UDP}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL4_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: wm.l3_l4.ipv4 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 2, , table: wm.l3_l4.ipv6 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: mac_addr_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: port_table.egr.rd */
+ {
+ .field_info_mask = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam.0 */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 3, , table: mac_addr_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam_cache.ipv6_rd */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_UDP}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_YES},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_NO}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: em.l2_l3_l4_v6.0 */
+ {
+ .field_info_mask = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam.l3_l4.ip */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_UDP}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV4},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_YES},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_NO}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam.l3_l4.nonip */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_YES},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_NO}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: wm.l3_l4.ipv4 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 3, , table: wm.l3.ipv4 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 3, , table: wm.l2 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 4, , table: port_table.ing_wr_0 */
+ {
+ .field_info_mask = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: port_table.egr_wr_0 */
+ {
+ .field_info_mask = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd_vfr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.rd_egr0 */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_rd_vfr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam.vfr_ing0 */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: profile_tcam.vfr_ing0 */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_wr_vfr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: em.vfr.0 */
+ {
+ .field_info_mask = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ }
+};
+
+struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
+ /* class_tid: 1, , table: l2_cntxt_tcam.0 */
+ {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ },
+ {
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ },
+ {
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ },
+ /* class_tid: 1, , table: mac_addr_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: fkb_select.l2_l3_l4_v6_em */
+ {
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "parif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "spif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "lcos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "loopback.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tuntype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tflags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tqos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "terr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ },
+ {
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ },
+ {
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ },
+ {
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}
+ },
+ {
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}
+ },
+ {
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_win.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ },
+ /* class_tid: 1, , table: em.l2_l3_l4_v6.0 */
+ {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: fkb_select.l3_l4_wm */
+ {
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "parif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "spif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "lcos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "loopback.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tuntype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tflags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tqos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "terr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_win.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: fkb_select.l3_l4_wm_vxlan */
+ {
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "parif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "spif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "lcos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "loopback.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tuntype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tflags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tqos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "terr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_win.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.l3_l4.ip */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.l3_l4.vxlan */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 & 0xff}
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ },
+ /* class_tid: 1, , table: wm.l3_l4.ipv4 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 1, , table: wm.l3_l4.ipv6 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 1, , table: wm.l3.ipv4 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 1, , table: wm.l3.ipv6 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 1, , table: wm.l2 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv4 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv6 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
+ {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 2, , table: tunnel_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ /* class_tid: 2, , table: l2_cntxt_tcam.0 */
+ {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
+ },
+ {
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ },
+ {
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ },
+ /* class_tid: 2, , table: mac_addr_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 2, , table: fkb_select.f2_wm */
+ {
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "parif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "spif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "lcos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "loopback.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tuntype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tflags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tqos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "terr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_win.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 2, , table: profile_tcam.f2 */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 & 0xff}
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ },
+ /* class_tid: 2, , table: wm.l3_l4.ipv4 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 2, , table: wm.l3_l4.ipv6 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam.0 */
+ {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}
+ },
+ {
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ },
+ {
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ },
+ /* class_tid: 3, , table: mac_addr_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 3, , table: fkb_select.l2_l3_l4_v6_em */
+ {
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "parif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "spif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "lcos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "loopback.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
{
- .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
- .cond_operand = BNXT_ULP_CF_IDX_O_L4
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_reject: thor, class_tid: 4 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
- .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: class_tid: 4, control.ing_0 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
- .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: class_tid: 4, control.egr_0 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
- .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: class_tid: 4, control.egr_1 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
- .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tuntype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tflags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tqos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "terr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ {
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ },
+ {
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ },
+ {
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_reject: thor, class_tid: 5 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
- .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
- }
-};
-
-struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
- /* class_tid: 1, , table: port_table.rd */
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
{
- .field_info_mask = {
- .description = "dev.port_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "dev.port_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
- }
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: l2_cntxt_tcam_cache.rd */
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- }
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: mac_addr_cache.rd */
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- }
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
- },
- .field_info_spec = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
- }
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
- },
- .field_info_spec = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
- }
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: l2_cntxt_tcam.0 */
{
- .field_info_mask = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}
},
{
- .field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}
},
{
- .field_info_mask = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_win.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
- },
- .field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
- }
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
- },
- .field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
- }
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- }
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 2}
- },
- .field_info_spec = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- .field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- }
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: mac_addr_cache.wr */
+ /* class_tid: 3, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- }
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .field_info_mask = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
- },
- .field_info_spec = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
- }
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "em_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
- },
- .field_info_spec = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
- }
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam_cache.l3_l4_rd */
{
- .field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "wc_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
- }
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
+ /* class_tid: 3, , table: em.l2_l3_l4_v6.0 */
{
- .field_info_mask = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
- }
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
- /* class_tid: 1, , table: profile_tcam.l3_l4 */
{
- .field_info_mask = {
- .description = "l4_hdr_is_udp_tcp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l4_hdr_is_udp_tcp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
},
{
- .field_info_mask = {
- .description = "l4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_THOR_SYM_L4_HDR_TYPE_TCP},
- .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr3 = {
- ULP_THOR_SYM_L4_HDR_TYPE_UDP}
- }
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
- },
- .field_info_spec = {
- .description = "l4_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
- },
- .field_info_spec = {
- .description = "l4_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
- }
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 3, , table: fkb_select.l3_l4_wc */
{
- .field_info_mask = {
- .description = "ieh",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "ieh",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "l3_ipv6_cmp_dst",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l3_ipv6_cmp_dst",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "parif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "spif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "l3_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "lcos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "l3_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "meta.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "l3_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_L3_HDR_VALID_YES}
- }
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "loopback.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_uc_mc_bc",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "l2_uc_mc_bc",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_hdr_type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "l2_hdr_type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "l2_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "l2_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_L2_HDR_VALID_YES}
- }
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tun_hdr_flags",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tun_hdr_flags",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tun_hdr_err",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tun_hdr_err",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tun_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "tun_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4_hdr_is_udp_tcp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl4_hdr_is_udp_tcp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl4_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "tl4_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3_ipv6_cmp_dst",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl3_ipv6_cmp_dst",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3_ipv6_cmp_src",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl3_ipv6_cmp_src",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3_hdr_isIP",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl3_hdr_isIP",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl3_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl3_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "tl3_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl2_two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl2_vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_uc_mc_bc",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl2_uc_mc_bc",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_hdr_type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl2_hdr_type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "tl2_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "hrec_next",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "hrec_next",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
- }
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "agg_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "agg_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "pkt_type_0",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "pkt_type_0",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "pkt_type_1",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "pkt_type_1",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- .field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- }
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam_cache.l3_l4_wr */
{
- .field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
- }
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
- }
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l3_l4 */
{
- .field_info_mask = {
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
- }
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
- }
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "lcos",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "lcos",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "meta",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "meta",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "rcyc_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "rcyc_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tuntype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tflags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_l2type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_l2type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tctxts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_dt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_dt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tctxt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_sa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_sa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tqos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_nvt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_nvt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "terr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "tl2_ovp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ovp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_ovd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ovd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_ovv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ovv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_ovt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ovt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_ivp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ivp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_ivd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ivd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_ivv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ivv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_ivt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ivt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.l3type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.l3type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.sip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.sip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "tl3.sip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.sip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.sip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.sip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.dip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.dip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.dip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.dip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "tl3.dip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.dip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.fid.ipv4",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.fid.ipv4",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.fid.ipv6",
- .field_bit_size = 20,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.fid.ipv6",
- .field_bit_size = 20,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.qos",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.qos",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_nonext",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_nonext",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_esp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_esp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_auth",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_auth",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.l3err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.l3err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "tl4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "tl4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_win.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tuntype",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tuntype",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tflags",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tflags",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tids",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tids",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tid",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tid",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 3, , table: profile_tcam.l3_l4.ip */
{
- .field_info_mask = {
- .description = "tctxts",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tctxts",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 & 0xff}
},
{
- .field_info_mask = {
- .description = "tctxt",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tctxt",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
},
{
- .field_info_mask = {
- .description = "tqos",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tqos",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "terr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "terr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_l2type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_l2type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_dt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_dt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 3, , table: profile_tcam.l3_l4.nonip */
{
- .field_info_mask = {
- .description = "l2_sa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_sa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 & 0xff}
},
{
- .field_info_mask = {
- .description = "l2_nvt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_nvt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
},
{
- .field_info_mask = {
- .description = "l2_ovp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ovp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "l2_ovd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ovd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ovv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ovv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ovt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ovt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ivp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ivp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ivd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ivd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 3, , table: profile_tcam_cache.wr */
{
- .field_info_mask = {
- .description = "l2_ivv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ivv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .field_info_mask = {
- .description = "l2_ivt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ivt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "l2_etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.l3type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.l3type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.sip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
- },
- .field_info_spec = {
- .description = "l3.sip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
- }
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.sip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.sip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.sip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.sip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
+ /* class_tid: 3, , table: wm.l3_l4.ipv4 */
{
- .field_info_mask = {
- .description = "l3.dip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
- },
- .field_info_spec = {
- .description = "l3.dip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
- }
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.dip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.dip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.dip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.dip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .field_info_mask = {
- .description = "l3.ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 3, , table: wm.l3.ipv4 */
{
- .field_info_mask = {
- .description = "l3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}
- }
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.fid.ipv4",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.fid.ipv4",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.fid.ipv6",
- .field_bit_size = 20,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.fid.ipv6",
- .field_bit_size = 20,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.qos",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.qos",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .field_info_mask = {
- .description = "l3.ieh_nonext",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_nonext",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 3, , table: wm.l2 */
{
- .field_info_mask = {
- .description = "l3.ieh_esp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_esp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_auth",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_auth",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .field_info_mask = {
- .description = "l3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 4, , table: int_full_act_record.0 */
{
- .field_info_mask = {
- .description = "l3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.l3err.ipv4",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.l3err.ipv4",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.l3err.ipv6",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.l3err.ipv6",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
- },
- .field_info_spec = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
- }
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
- },
- .field_info_spec = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
- }
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}
},
{
- .field_info_mask = {
- .description = "l4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.ack",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.ack",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.win",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.win",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.tsval",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.tsval",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
- {
- .field_info_mask = {
- .description = "l4.txecr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.txecr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ /* class_tid: 4, , table: port_table.ing_wr_0 */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "drv_func.mac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: port_table.wr_0 */
{
- .field_info_mask = {
- .description = "dev.port_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "dev.port_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
- }
+ .description = "drv_func.parent.mac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
- }
+ .description = "phy_port",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "default_arec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
/* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
- .field_info_mask = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
},
{
- .field_info_mask = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
{
- .field_info_mask = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
},
{
- .field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
},
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
{
- .field_info_mask = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
{
- .field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
+ /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
{
- .field_info_mask = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
+ /* class_tid: 4, , table: int_full_act_record.egr_0 */
{
- .field_info_mask = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
- }
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- .field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- }
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
- }
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
- }
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
- .field_info_mask = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 4, , table: port_table.egr_wr_0 */
{
- .field_info_mask = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "drv_func.mac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "drv_func.parent.mac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "phy_port",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "default_arec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
+ /* class_tid: 4, , table: ilt_tbl.egr_vfr */
{
- .field_info_mask = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "ilt_destination",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "fwd_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_FWD_OP_BYPASS_LKUP}
},
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
- }
+ .description = "en_ilt_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "en_bd_action",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "en_bd_meta",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "reserved",
+ .field_bit_size = 23,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
{
- .field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .field_info_mask = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- .field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- }
- }
-};
-
-struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
- /* class_tid: 1, , table: l2_cntxt_tcam.0 */
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
.description = "prof_func_id",
.field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
},
@@ -4304,8 +40108,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
.description = "ctxt_opcode",
@@ -4330,10 +40134,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
},
- /* class_tid: 1, , table: mac_addr_cache.wr */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -4347,7 +40151,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_cntxt_tcam_index",
.field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
},
{
.description = "l2_cntxt_id",
@@ -4364,461 +40171,494 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: fkb_select.l3_l4_wm */
+ /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
{
- .description = "l2_cntxt_id.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- 1}
- },
- {
- .description = "parif.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spif.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "svif.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "lcos.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "meta.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "rcyc_cnt.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
+ /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
{
- .description = "loopback.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
+ /* class_tid: 5, , table: int_full_act_record.loopback */
{
- .description = "tl2_l2type.en",
- .field_bit_size = 1,
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_dmac.en",
- .field_bit_size = 1,
+ .description = "encap_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_smac.en",
- .field_bit_size = 1,
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_dt.en",
- .field_bit_size = 1,
+ .description = "rsvd1",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_sa.en",
- .field_bit_size = 1,
+ .description = "rsvd0",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_nvt.en",
- .field_bit_size = 1,
+ .description = "decap_func",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovp.en",
- .field_bit_size = 1,
+ .description = "meter",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovd.en",
+ .description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovv.en",
- .field_bit_size = 1,
+ .description = "stats_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovt.en",
- .field_bit_size = 1,
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff,
+ ULP_THOR_SYM_LOOPBACK_PORT & 0xff}
},
{
- .description = "tl2_ivp.en",
+ .description = "use_default",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivd.en",
- .field_bit_size = 1,
+ .description = "mirror",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivv.en",
+ .description = "cond_copy",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivt.en",
- .field_bit_size = 1,
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_etype.en",
+ .description = "drop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_l3type.en",
+ .description = "hit",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_sip.en",
- .field_bit_size = 1,
+ .description = "type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
{
- .description = "tl3_sip_selcmp.en",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
},
{
- .description = "tl3_dip.en",
- .field_bit_size = 1,
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_dip_selcmp.en",
- .field_bit_size = 1,
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
{
- .description = "tl3_ttl.en",
- .field_bit_size = 1,
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
},
{
- .description = "tl3_prot.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .description = "tl3_fid.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_LOOPBACK_PARIF}
},
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
{
- .description = "tl3_qos.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "tl3_ieh_nonext.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
},
{
- .description = "tl3_ieh_esp.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .description = "tl3_ieh_auth.en",
- .field_bit_size = 1,
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
{
- .description = "tl3_ieh_dest.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
+ /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
{
- .description = "tl3_ieh_frag.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
+ /* class_tid: 5, , table: int_full_act_record.vf_ing */
{
- .description = "tl3_ieh_rthdr.en",
- .field_bit_size = 1,
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_hop.en",
- .field_bit_size = 1,
+ .description = "encap_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_1frag.en",
- .field_bit_size = 1,
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_df.en",
- .field_bit_size = 1,
+ .description = "rsvd1",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_l3err.en",
- .field_bit_size = 1,
+ .description = "rsvd0",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_l4type.en",
- .field_bit_size = 1,
+ .description = "decap_func",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_src.en",
- .field_bit_size = 1,
+ .description = "meter",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_dst.en",
+ .description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_flags.en",
- .field_bit_size = 1,
+ .description = "stats_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_seq.en",
- .field_bit_size = 1,
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}
},
{
- .description = "tl4_pa.en",
+ .description = "use_default",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_opt.en",
- .field_bit_size = 1,
+ .description = "mirror",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_tcpts.en",
+ .description = "cond_copy",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_err.en",
- .field_bit_size = 1,
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tuntype.en",
+ .description = "drop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tflags.en",
+ .description = "hit",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tids.en",
- .field_bit_size = 1,
+ .description = "type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 5, , table: ilt_tbl.vf_ing */
{
- .description = "tid.en",
- .field_bit_size = 1,
+ .description = "ilt_destination",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tctxts.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tctxt.en",
- .field_bit_size = 1,
+ .description = "fwd_op",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_FWD_OP_BYPASS_LKUP}
},
{
- .description = "tqos.en",
+ .description = "en_ilt_dest",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "terr.en",
+ .description = "en_bd_action",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_l2type.en",
+ .description = "en_bd_meta",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_dmac.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_smac.en",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 23,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: ilt_tbl.vfr_egr */
{
- .description = "l2_dt.en",
- .field_bit_size = 1,
+ .description = "ilt_destination",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_sa.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_nvt.en",
- .field_bit_size = 1,
+ .description = "fwd_op",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_FWD_OP_BYPASS_LKUP}
},
{
- .description = "l2_ovp.en",
+ .description = "en_ilt_dest",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovd.en",
+ .description = "en_bd_action",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "l2_ovv.en",
+ .description = "en_bd_meta",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovt.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivp.en",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 23,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
{
- .description = "l2_ivd.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "l2_ivv.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivt.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_etype.en",
- .field_bit_size = 1,
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: metadata_record.vfr_egr */
{
- .description = "l3_l3type.en",
- .field_bit_size = 1,
+ .description = "prof_meta_mask",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
+ /* class_tid: 5, , table: mod_record.vfr_egr */
{
- .description = "l3_sip.en",
+ .description = "metadata_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -4826,1078 +40666,1113 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
1}
},
{
- .description = "l3_sip_selcmp.en",
+ .description = "rem_ovlan",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- {
- .description = "l3_dip_selcmp.en",
+ .description = "rem_ivlan",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ttl.en",
+ .description = "rep_add_ivlan",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_prot.en",
+ .description = "rep_add_ovlan",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_fid.en",
+ .description = "ttl_update",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_qos.en",
+ .description = "tun_md_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_nonext.en",
+ .description = "reserved_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_esp.en",
+ .description = "l2_dmac_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_auth.en",
+ .description = "l2_smac_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_dest.en",
+ .description = "l3_sip_ipv6_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_frag.en",
+ .description = "l3_dip_ipv6_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_rthdr.en",
+ .description = "l3_sip_ipv4_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_hop.en",
+ .description = "l3_dip_ipv4_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_1frag.en",
+ .description = "l4_sport_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_df.en",
+ .description = "l4_dport_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_l3err.en",
- .field_bit_size = 1,
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_l4type.en",
- .field_bit_size = 1,
+ .description = "metadata_op",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_src.en",
- .field_bit_size = 1,
+ .description = "metadata_prof",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0 & 0xff}
},
{
- .description = "l4_dst.en",
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_flags.en",
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_seq.en",
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_dec",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_ack.en",
+ .description = "ttl_il3_dec",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_win.en",
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_rdir",
.field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ /* class_tid: 5, , table: int_full_act_record.vfr_egr */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_pa.en",
- .field_bit_size = 1,
+ .description = "encap_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_opt.en",
- .field_bit_size = 1,
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_tcpts.en",
- .field_bit_size = 1,
+ .description = "rsvd0",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_tsval.en",
- .field_bit_size = 1,
+ .description = "decap_func",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_txecr.en",
- .field_bit_size = 1,
+ .description = "meter",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_err.en",
+ .description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam.l3_l4 */
{
- .description = "wc_key_id",
- .field_bit_size = 6,
+ .description = "stats_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff,
+ ULP_THOR_SYM_LOOPBACK_PORT & 0xff}
},
{
- .description = "wc_search_en",
+ .description = "use_default",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_type",
- .field_bit_size = 2,
+ .description = "mirror",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 6,
+ .description = "cond_copy",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_search_en",
+ .description = "drop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "pl_byp_lkup_en",
+ .description = "hit",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam_cache.l3_l4_wr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ 1}
},
+ /* class_tid: 5, , table: l2_cntxt_tcam.vfr_ing0 */
{
- .description = "profile_tcam_index",
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 & 0xff}
+ },
+ {
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ },
+ {
+ .description = "l2_cntxt_id",
.field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
+ },
+ /* class_tid: 5, , table: fkb_select.vfr_em */
+ {
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 8,
+ .description = "parif.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "spif.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_key_id",
- .field_bit_size = 8,
+ .description = "svif.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "flow_sig_id",
- .field_bit_size = 64,
+ .description = "lcos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l3_l4 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "meta.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "loopback.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: int_full_act_record.0 */
{
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "encap_ptr",
- .field_bit_size = 16,
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd1",
- .field_bit_size = 16,
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd0",
- .field_bit_size = 8,
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "decap_func",
- .field_bit_size = 5,
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meter",
- .field_bit_size = 10,
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_op",
+ .description = "tl2_ovt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_ptr",
- .field_bit_size = 16,
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 11,
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "use_default",
+ .description = "tl2_ivv.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mirror",
- .field_bit_size = 4,
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "cond_copy",
+ .description = "tl2_etype.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drop",
+ .description = "tl3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "hit",
+ .description = "tl3_sip_selcmp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "type",
- .field_bit_size = 3,
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: port_table.wr_0 */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drv_func.mac",
- .field_bit_size = 48,
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drv_func.parent.mac",
- .field_bit_size = 48,
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "phy_port",
- .field_bit_size = 8,
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "default_arec_ptr",
- .field_bit_size = 16,
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_tcam_index",
- .field_bit_size = 10,
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: int_full_act_record.egr_0 */
{
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "encap_ptr",
- .field_bit_size = 16,
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd1",
- .field_bit_size = 16,
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd0",
- .field_bit_size = 8,
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "decap_func",
- .field_bit_size = 5,
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meter",
- .field_bit_size = 10,
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_op",
+ .description = "tuntype.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_ptr",
- .field_bit_size = 16,
+ .description = "tflags.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 11,
+ .description = "tids.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "use_default",
+ .description = "tid.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mirror",
- .field_bit_size = 4,
+ .description = "tctxts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "cond_copy",
+ .description = "tctxt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
+ .description = "tqos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drop",
+ .description = "terr.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "hit",
+ .description = "l2_l2type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "type",
- .field_bit_size = 3,
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: int_full_act_record.loopback */
{
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "encap_ptr",
- .field_bit_size = 16,
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd1",
- .field_bit_size = 16,
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd0",
- .field_bit_size = 8,
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "decap_func",
- .field_bit_size = 5,
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meter",
- .field_bit_size = 10,
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_op",
+ .description = "l3_sip_selcmp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_ptr",
- .field_bit_size = 16,
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 11,
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff,
- ULP_THOR_SYM_LOOPBACK_PORT & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "use_default",
+ .description = "l3_ttl.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mirror",
- .field_bit_size = 4,
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "cond_copy",
+ .description = "l3_fid.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drop",
+ .description = "l3_ieh_nonext.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "hit",
+ .description = "l3_ieh_esp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "type",
- .field_bit_size = 3,
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: int_full_act_record.vf_ing */
{
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "encap_ptr",
- .field_bit_size = 16,
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd1",
- .field_bit_size = 16,
+ .description = "l3_df.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd0",
- .field_bit_size = 8,
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "decap_func",
- .field_bit_size = 5,
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meter",
- .field_bit_size = 10,
+ .description = "l4_src.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_op",
+ .description = "l4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_ptr",
- .field_bit_size = 16,
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 11,
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "use_default",
+ .description = "l4_ack.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mirror",
- .field_bit_size = 4,
+ .description = "l4_win.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "cond_copy",
+ .description = "l4_pa.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drop",
+ .description = "l4_tcpts.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "hit",
+ .description = "l4_tsval.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "type",
- .field_bit_size = 3,
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: vtag_encap_record.vfr_egr0 */
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "l4_err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: profile_tcam.vfr_ing0 */
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "wc_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l2_en",
+ .description = "wc_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
- },
- {
- .description = "rsrvd",
- .field_bit_size = 1,
+ .description = "em_key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "em_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 & 0xff}
},
{
- .description = "vtag_tpid",
- .field_bit_size = 16,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- 0x81,
- 0x00}
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 & 0xff}
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "em_search_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ 1}
},
{
- .description = "vtag_de",
+ .description = "pl_byp_lkup_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- {
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
- },
- /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
+ /* class_tid: 5, , table: int_full_act_record.vfr_ing0 */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -5908,10 +41783,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "encap_ptr",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "mod_rec_ptr",
@@ -5959,10 +41831,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "vnic_or_vport",
.field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff,
- ULP_THOR_SYM_LOOPBACK_PORT & 0xff}
+ (BNXT_ULP_CF_IDX_VF_FUNC_VNIC >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_VNIC & 0xff}
},
{
.description = "use_default",
@@ -6007,6 +41879,50 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
+ },
+ /* class_tid: 5, , table: em.vfr.0 */
+ {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
};
@@ -6053,6 +41969,203 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 29
},
+ /* class_tid: 1, , table: profile_tcam_cache.ipv6_rd */
+ {
+ .description = "em_key_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_KEY_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 50
+ },
+ {
+ .description = "em_profile_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 42
+ },
+ {
+ .description = "flow_sig_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .ident_bit_size = 64,
+ .ident_bit_pos = 74
+ },
+ {
+ .description = "profile_tcam_index",
+ .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
+ },
+ /* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */
+ {
+ .description = "em_profile_id",
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_EM_PROF,
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 23
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.rd */
+ {
+ .description = "flow_sig_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .ident_bit_size = 64,
+ .ident_bit_pos = 74
+ },
+ {
+ .description = "profile_tcam_index",
+ .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
+ },
+ /* class_tid: 2, , table: port_table.rd */
+ {
+ .description = "default_arec_ptr",
+ .regfile_idx = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
+ .ident_bit_size = 16,
+ .ident_bit_pos = 136
+ },
+ {
+ .description = "drv_func.parent.mac",
+ .regfile_idx = BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC,
+ .ident_bit_size = 48,
+ .ident_bit_pos = 80
+ },
+ {
+ .description = "phy_port",
+ .regfile_idx = BNXT_ULP_RF_IDX_PHY_PORT,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 128
+ },
+ /* class_tid: 2, , table: tunnel_cache.rd */
+ {
+ .description = "l2_cntxt_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 42
+ },
+ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
+ {
+ .description = "l2_cntxt_id",
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 29
+ },
+ /* class_tid: 2, , table: mac_addr_cache.rd */
+ {
+ .description = "l2_cntxt_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 42
+ },
+ /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
+ {
+ .description = "em_profile_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 42
+ },
+ {
+ .description = "flow_sig_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .ident_bit_size = 64,
+ .ident_bit_pos = 74
+ },
+ {
+ .description = "profile_tcam_index",
+ .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ {
+ .description = "l2_cntxt_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 42
+ },
+ /* class_tid: 3, , table: mac_addr_cache.rd */
+ {
+ .description = "l2_cntxt_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 42
+ },
+ /* class_tid: 3, , table: port_table.egr.rd */
+ {
+ .description = "default_arec_ptr",
+ .regfile_idx = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
+ .ident_bit_size = 16,
+ .ident_bit_pos = 136
+ },
+ {
+ .description = "drv_func.parent.mac",
+ .regfile_idx = BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC,
+ .ident_bit_size = 48,
+ .ident_bit_pos = 80
+ },
+ {
+ .description = "phy_port",
+ .regfile_idx = BNXT_ULP_RF_IDX_PHY_PORT,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 128
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam.0 */
+ {
+ .description = "l2_cntxt_id",
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 29
+ },
+ /* class_tid: 3, , table: profile_tcam_cache.ipv6_rd */
+ {
+ .description = "em_key_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_KEY_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 50
+ },
+ {
+ .description = "em_profile_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 42
+ },
+ {
+ .description = "flow_sig_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .ident_bit_size = 64,
+ .ident_bit_pos = 74
+ },
+ {
+ .description = "profile_tcam_index",
+ .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
+ },
+ /* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */
+ {
+ .description = "em_profile_id",
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_EM_PROF,
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 23
+ },
+ /* class_tid: 3, , table: profile_tcam_cache.rd */
+ {
+ .description = "flow_sig_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .ident_bit_size = 64,
+ .ident_bit_pos = 74
+ },
+ {
+ .description = "profile_tcam_index",
+ .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
+ },
/* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
.description = "l2_cntxt_id",
@@ -6070,5 +42183,21 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 29
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
+ {
+ .description = "l2_cntxt_id",
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 29
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_wr_vfr */
+ {
+ .description = "rid",
+ .regfile_idx = BNXT_ULP_RF_IDX_RID,
+ .ident_bit_size = 32,
+ .ident_bit_pos = 0
}
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
index 7203dcf1fb..2870a0615a 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Fri May 28 16:46:46 2021 */
+/* date: Wed Jun 30 14:36:16 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -1488,7 +1488,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 47,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE,
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index bcc089b3e1..234f7ea2fa 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -2212,6 +2212,7 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
int32_t trc;
int32_t rc = 0;
int32_t pad = 0;
+ enum bnxt_ulp_byte_order key_order, res_order;
tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session);
rc = bnxt_ulp_cntxt_mem_type_get(parms->ulp_ctx, &mtype);
@@ -2226,11 +2227,12 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
+ key_order = dparms->em_byte_order;
+ res_order = dparms->em_byte_order;
+
/* Initialize the key/result blobs */
- if (!ulp_blob_init(&key, tbl->blob_key_bit_size,
- dparms->key_byte_order) ||
- !ulp_blob_init(&data, tbl->result_bit_size,
- dparms->result_byte_order)) {
+ if (!ulp_blob_init(&key, tbl->blob_key_bit_size, key_order) ||
+ !ulp_blob_init(&data, tbl->result_bit_size, res_order)) {
BNXT_TF_DBG(ERR, "blob inits failed.\n");
return -EINVAL;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index 4e9968e5fa..dce95de05c 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -826,12 +826,12 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
*/
ulp_rte_prsr_fld_mask(params, &idx, size,
&priority,
- &priority_mask,
+ (vlan_mask) ? &priority_mask : NULL,
ULP_PRSR_ACT_MASK_IGNORE);
ulp_rte_prsr_fld_mask(params, &idx, size,
&vlan_tag,
- &vlan_tag_mask,
+ (vlan_mask) ? &vlan_tag_mask : NULL,
ULP_PRSR_ACT_DEFAULT);
size = sizeof(((struct rte_flow_item_vlan *)NULL)->inner_type);
@@ -859,6 +859,10 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_ONE_VTAG, 1);
ULP_BITMAP_SET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_OO_VLAN);
+ if (vlan_mask && vlan_tag_mask)
+ ULP_COMP_FLD_IDX_WR(params,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID, 1);
+
} else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) &&
!ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_I_ETH) &&
outer_vtag_num == 1) {
@@ -870,6 +874,10 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_ONE_VTAG, 0);
ULP_BITMAP_SET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_OI_VLAN);
+ if (vlan_mask && vlan_tag_mask)
+ ULP_COMP_FLD_IDX_WR(params,
+ BNXT_ULP_CF_IDX_OI_VLAN_FB_VID, 1);
+
} else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) &&
ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_I_ETH) &&
!inner_vtag_num) {
@@ -881,6 +889,9 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_ONE_VTAG, 1);
ULP_BITMAP_SET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_IO_VLAN);
+ if (vlan_mask && vlan_tag_mask)
+ ULP_COMP_FLD_IDX_WR(params,
+ BNXT_ULP_CF_IDX_IO_VLAN_FB_VID, 1);
inner_flag = 1;
} else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) &&
ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_I_ETH) &&
@@ -893,6 +904,9 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_ONE_VTAG, 0);
ULP_BITMAP_SET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_II_VLAN);
+ if (vlan_mask && vlan_tag_mask)
+ ULP_COMP_FLD_IDX_WR(params,
+ BNXT_ULP_CF_IDX_II_VLAN_FB_VID, 1);
inner_flag = 1;
} else {
BNXT_TF_DBG(ERR, "Error Parsing:Vlan hdr found without eth\n");
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index e2a4b81cec..1683cd7ec4 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -213,6 +213,7 @@ struct bnxt_ulp_device_params {
enum bnxt_ulp_byte_order result_byte_order;
enum bnxt_ulp_byte_order encap_byte_order;
enum bnxt_ulp_byte_order wc_key_byte_order;
+ enum bnxt_ulp_byte_order em_byte_order;
uint8_t encap_byte_swap;
uint8_t num_phy_ports;
uint32_t mark_db_lfid_entries;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c
index fc4f435c97..686b80e456 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c
@@ -964,8 +964,11 @@ ulp_blob_append(struct ulp_blob *dst, struct ulp_blob *src,
ulp_bs_put_msb(dst->data, dst->write_idx,
ULP_BLOB_BYTE, bluff);
dst->write_idx += remaining;
+ src_offset += remaining;
}
+ src_buf += ULP_BITS_2_BYTE_NR(src_offset);
+
/* Push the byte aligned pieces */
for (k = 0; k < ULP_BITS_2_BYTE_NR(src_len); k++) {
ulp_bs_put_msb(dst->data, dst->write_idx, ULP_BLOB_BYTE,
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH 10/14] net/bnxt: tf core SRAM Manager
2021-09-01 14:24 [dpdk-dev] [PATCH 00/14] enhancements to host based flow table management Venkat Duvvuru
` (8 preceding siblings ...)
2021-09-01 14:24 ` [dpdk-dev] [PATCH 09/14] net/bnxt: add flow templates " Venkat Duvvuru
@ 2021-09-01 14:24 ` Venkat Duvvuru
2021-09-01 14:24 ` [dpdk-dev] [PATCH 11/14] net/bnxt: dynamically allocate space for EM defrag function Venkat Duvvuru
` (4 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-01 14:24 UTC (permalink / raw)
To: dev; +Cc: Farah Smith
From: Farah Smith <farah.smith@broadcom.com>
Adjust info message to debug level to prevent excessive
logging.
Signed-off-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
---
drivers/net/bnxt/tf_core/tf_tbl_sram.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.c b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
index ea10afecb6..d7727f7a11 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl_sram.c
+++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
@@ -130,7 +130,7 @@ static int tf_tbl_sram_get_info(struct tf_tbl_sram_get_info_parms *parms)
if (slices)
parms->slice_size = tf_tbl_sram_slices_2_size[slices];
- TFP_DRV_LOG(INFO,
+ TFP_DRV_LOG(DEBUG,
"(%s) bank(%s) slice_size(%s)\n",
tf_tbl_type_2_str(parms->tbl_type),
tf_sram_bank_2_str(parms->bank_id),
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH 11/14] net/bnxt: dynamically allocate space for EM defrag function
2021-09-01 14:24 [dpdk-dev] [PATCH 00/14] enhancements to host based flow table management Venkat Duvvuru
` (9 preceding siblings ...)
2021-09-01 14:24 ` [dpdk-dev] [PATCH 10/14] net/bnxt: tf core SRAM Manager Venkat Duvvuru
@ 2021-09-01 14:24 ` Venkat Duvvuru
2021-09-01 14:24 ` [dpdk-dev] [PATCH 12/14] net/bnxt: sram manager shared session Venkat Duvvuru
` (3 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-01 14:24 UTC (permalink / raw)
To: dev; +Cc: Randy Schacher
From: Randy Schacher <stuart.schacher@broadcom.com>
Alter defrag function to dynamically allocate and delete
free_list and adj_list buffers.
Signed-off-by: Randy Schacher <stuart.schacher@broadcom.com>
Reviewed-by: Peter Spreadborough <peter.spreadborough@broadcom.com>
---
drivers/net/bnxt/tf_core/dpool.c | 38 +++++++++++++++++++++-----------
1 file changed, 25 insertions(+), 13 deletions(-)
diff --git a/drivers/net/bnxt/tf_core/dpool.c b/drivers/net/bnxt/tf_core/dpool.c
index 145efa486f..5c03f775a5 100644
--- a/drivers/net/bnxt/tf_core/dpool.c
+++ b/drivers/net/bnxt/tf_core/dpool.c
@@ -7,9 +7,6 @@
#include <stdbool.h>
#include <stdint.h>
#include <errno.h>
-
-#include <rte_malloc.h>
-
#include "tfp.h"
#include "dpool.h"
@@ -84,13 +81,13 @@ static int dpool_move(struct dpool *dpool,
return 0;
}
-
int dpool_defrag(struct dpool *dpool,
uint32_t entry_size,
uint8_t defrag)
{
struct dpool_free_list *free_list;
struct dpool_adj_list *adj_list;
+ struct tfp_calloc_parms parms;
uint32_t count;
uint32_t index;
uint32_t used;
@@ -103,15 +100,31 @@ int dpool_defrag(struct dpool *dpool,
uint32_t max_size = 0;
int rc;
- free_list = rte_zmalloc("dpool_free_list",
- sizeof(struct dpool_free_list), 0);
+ parms.nitems = 1;
+ parms.size = sizeof(struct dpool_free_list);
+ parms.alignment = 0;
+
+ rc = tfp_calloc(&parms);
+
+ if (rc)
+ return rc;
+
+ free_list = (struct dpool_free_list *)parms.mem_va;
if (free_list == NULL) {
TFP_DRV_LOG(ERR, "dpool free list allocation failed\n");
return -ENOMEM;
}
- adj_list = rte_zmalloc("dpool_adjacent_list",
- sizeof(struct dpool_adj_list), 0);
+ parms.nitems = 1;
+ parms.size = sizeof(struct dpool_adj_list);
+ parms.alignment = 0;
+
+ rc = tfp_calloc(&parms);
+
+ if (rc)
+ return rc;
+
+ adj_list = (struct dpool_adj_list *)parms.mem_va;
if (adj_list == NULL) {
TFP_DRV_LOG(ERR, "dpool adjacent list allocation failed\n");
return -ENOMEM;
@@ -239,8 +252,8 @@ int dpool_defrag(struct dpool *dpool,
free_list->entry[largest_free_index].index,
max_index);
if (rc) {
- rte_free(free_list);
- rte_free(adj_list);
+ tfp_free(free_list);
+ tfp_free(adj_list);
return rc;
}
} else {
@@ -249,12 +262,11 @@ int dpool_defrag(struct dpool *dpool,
}
done:
- rte_free(free_list);
- rte_free(adj_list);
+ tfp_free(free_list);
+ tfp_free(adj_list);
return largest_free_size;
}
-
uint32_t dpool_alloc(struct dpool *dpool,
uint32_t size,
uint8_t defrag)
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH 12/14] net/bnxt: sram manager shared session
2021-09-01 14:24 [dpdk-dev] [PATCH 00/14] enhancements to host based flow table management Venkat Duvvuru
` (10 preceding siblings ...)
2021-09-01 14:24 ` [dpdk-dev] [PATCH 11/14] net/bnxt: dynamically allocate space for EM defrag function Venkat Duvvuru
@ 2021-09-01 14:24 ` Venkat Duvvuru
2021-09-01 14:24 ` [dpdk-dev] [PATCH 13/14] net/bnxt: add enhancements to TF ULP Venkat Duvvuru
` (2 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-01 14:24 UTC (permalink / raw)
To: dev; +Cc: Farah Smith
From: Farah Smith <farah.smith@broadcom.com>
Fix shared session support issues due to SRAM manager
additions. Shared session does not support slices within
RM blocks. Calculate resources required without slices
and determine base addresses using old methods for the
shared session.
Signed-off-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com>
---
drivers/net/bnxt/tf_core/tf_em_internal.c | 5 +-
drivers/net/bnxt/tf_core/tf_rm.c | 134 +++++++++++++++++++---
drivers/net/bnxt/tf_core/tf_tbl_sram.c | 73 +++++++++---
3 files changed, 176 insertions(+), 36 deletions(-)
diff --git a/drivers/net/bnxt/tf_core/tf_em_internal.c b/drivers/net/bnxt/tf_core/tf_em_internal.c
index 2d57595f17..67ba011eae 100644
--- a/drivers/net/bnxt/tf_core/tf_em_internal.c
+++ b/drivers/net/bnxt/tf_core/tf_em_internal.c
@@ -326,8 +326,11 @@ tf_em_int_unbind(struct tf *tfp)
return rc;
if (!tf_session_is_shared_session(tfs)) {
- for (i = 0; i < TF_DIR_MAX; i++)
+ for (i = 0; i < TF_DIR_MAX; i++) {
+ if (tfs->em_pool[i] == NULL)
+ continue;
dpool_free_all(tfs->em_pool[i]);
+ }
}
rc = tf_session_get_db(tfp, TF_MODULE_TYPE_EM, &em_db_ptr);
diff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c
index 03c958a7d6..dd537aaece 100644
--- a/drivers/net/bnxt/tf_core/tf_rm.c
+++ b/drivers/net/bnxt/tf_core/tf_rm.c
@@ -18,6 +18,9 @@
#include "tfp.h"
#include "tf_msg.h"
+/* Logging defines */
+#define TF_RM_DEBUG 0
+
/**
* Generic RM Element data type that an RM DB is build upon.
*/
@@ -207,6 +210,45 @@ tf_rm_adjust_index(struct tf_rm_element *db,
return rc;
}
+/**
+ * Logs an array of found residual entries to the console.
+ *
+ * [in] dir
+ * Receive or transmit direction
+ *
+ * [in] module
+ * Type of Device Module
+ *
+ * [in] count
+ * Number of entries in the residual array
+ *
+ * [in] residuals
+ * Pointer to an array of residual entries. Array is index same as
+ * the DB in which this function is used. Each entry holds residual
+ * value for that entry.
+ */
+#if (TF_RM_DEBUG == 1)
+static void
+tf_rm_log_residuals(enum tf_dir dir,
+ enum tf_module_type module,
+ uint16_t count,
+ uint16_t *residuals)
+{
+ int i;
+
+ /* Walk the residual array and log the types that wasn't
+ * cleaned up to the console.
+ */
+ for (i = 0; i < count; i++) {
+ if (residuals[i] != 0)
+ TFP_DRV_LOG(INFO,
+ "%s, %s was not cleaned up, %d outstanding\n",
+ tf_dir_2_str(dir),
+ tf_module_subtype_2_str(module, i),
+ residuals[i]);
+ }
+}
+#endif /* TF_RM_DEBUG == 1 */
/**
* Performs a check of the passed in DB for any lingering elements. If
* a resource type was found to not have been cleaned up by the caller
@@ -322,6 +364,12 @@ tf_rm_check_residuals(struct tf_rm_new_db *rm_db,
*resv_size = found;
}
+#if (TF_RM_DEBUG == 1)
+ tf_rm_log_residuals(rm_db->dir,
+ rm_db->module,
+ rm_db->num_entries,
+ residuals);
+#endif
tfp_free((void *)residuals);
*resv = local_resv;
@@ -367,7 +415,8 @@ tf_rm_update_parent_reservations(struct tf *tfp,
struct tf_rm_element_cfg *cfg,
uint16_t *alloc_cnt,
uint16_t num_elements,
- uint16_t *req_cnt)
+ uint16_t *req_cnt,
+ bool shared_session)
{
int parent, child;
const char *type_str;
@@ -378,18 +427,28 @@ tf_rm_update_parent_reservations(struct tf *tfp,
/* If I am a parent */
if (cfg[parent].cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_PARENT) {
- /* start with my own count */
- RTE_ASSERT(cfg[parent].slices);
- combined_cnt =
- alloc_cnt[parent] / cfg[parent].slices;
+ uint8_t p_slices = 1;
+
+ /* Shared session doesn't support slices */
+ if (!shared_session)
+ p_slices = cfg[parent].slices;
+
+ RTE_ASSERT(p_slices);
- if (alloc_cnt[parent] % cfg[parent].slices)
+ combined_cnt = alloc_cnt[parent] / p_slices;
+
+ if (alloc_cnt[parent] % p_slices)
combined_cnt++;
if (alloc_cnt[parent]) {
dev->ops->tf_dev_get_resource_str(tfp,
cfg[parent].hcapi_type,
&type_str);
+#if (TF_RM_DEBUG == 1)
+ printf("%s:%s cnt(%d) slices(%d)\n",
+ type_str, tf_tbl_type_2_str(parent),
+ alloc_cnt[parent], p_slices);
+#endif /* (TF_RM_DEBUG == 1) */
}
/* Search again through all the elements */
@@ -399,20 +458,31 @@ tf_rm_update_parent_reservations(struct tf *tfp,
TF_RM_ELEM_CFG_HCAPI_BA_CHILD &&
cfg[child].parent_subtype == parent &&
alloc_cnt[child]) {
+ uint8_t c_slices = 1;
uint16_t cnt = 0;
- RTE_ASSERT(cfg[child].slices);
+
+ if (!shared_session)
+ c_slices = cfg[child].slices;
+
+ RTE_ASSERT(c_slices);
dev->ops->tf_dev_get_resource_str(tfp,
cfg[child].hcapi_type,
&type_str);
+#if (TF_RM_DEBUG == 1)
+ printf("%s:%s cnt(%d) slices(%d)\n",
+ type_str,
+ tf_tbl_type_2_str(child),
+ alloc_cnt[child],
+ c_slices);
+#endif /* (TF_RM_DEBUG == 1) */
/* Increment the parents combined count
* with each child's count adjusted for
- * number of slices per RM allocated item.
+ * number of slices per RM alloc item.
*/
- cnt =
- alloc_cnt[child] / cfg[child].slices;
+ cnt = alloc_cnt[child] / c_slices;
- if (alloc_cnt[child] % cfg[child].slices)
+ if (alloc_cnt[child] % c_slices)
cnt++;
combined_cnt += cnt;
@@ -422,6 +492,10 @@ tf_rm_update_parent_reservations(struct tf *tfp,
}
/* Save the parent count to be requested */
req_cnt[parent] = combined_cnt;
+#if (TF_RM_DEBUG == 1)
+ printf("%s calculated total:%d\n\n",
+ type_str, req_cnt[parent]);
+#endif /* (TF_RM_DEBUG == 1) */
}
}
return 0;
@@ -444,6 +518,7 @@ tf_rm_create_db(struct tf *tfp,
struct tf_rm_new_db *rm_db;
struct tf_rm_element *db;
uint32_t pool_size;
+ bool shared_session = 0;
TF_CHECK_PARMS2(tfp, parms);
@@ -460,7 +535,6 @@ tf_rm_create_db(struct tf *tfp,
/* Need device max number of elements for the RM QCAPS */
rc = dev->ops->tf_dev_get_max_types(tfp, &max_types);
-
/* Allocate memory for RM QCAPS request */
cparms.nitems = max_types;
cparms.size = sizeof(struct tf_rm_resc_req_entry);
@@ -496,12 +570,15 @@ tf_rm_create_db(struct tf *tfp,
tfp_memcpy(req_cnt, parms->alloc_cnt,
parms->num_elements * sizeof(uint16_t));
+ shared_session = tf_session_is_shared_session(tfs);
+
/* Update the req_cnt based upon the element configuration
*/
tf_rm_update_parent_reservations(tfp, dev, parms->cfg,
parms->alloc_cnt,
parms->num_elements,
- req_cnt);
+ req_cnt,
+ shared_session);
/* Process capabilities against DB requirements. However, as a
* DB can hold elements that are not HCAPI we can reduce the
@@ -517,6 +594,12 @@ tf_rm_create_db(struct tf *tfp,
&hcapi_items);
if (hcapi_items == 0) {
+#if (TF_RM_DEBUG == 1)
+ TFP_DRV_LOG(INFO,
+ "%s: module: %s Empty RM DB create request\n",
+ tf_dir_2_str(parms->dir),
+ tf_module_2_str(parms->module));
+#endif
parms->rm_db = NULL;
return -ENOMEM;
}
@@ -565,11 +648,11 @@ tf_rm_create_db(struct tf *tfp,
hcapi_type,
&type_str);
TFP_DRV_LOG(ERR,
- "Failure, %s:%d:%s req:%d avail:%d\n",
- tf_dir_2_str(parms->dir),
- hcapi_type, type_str,
- req_cnt[i],
- query[hcapi_type].max);
+ "Failure, %s:%d:%s req:%d avail:%d\n",
+ tf_dir_2_str(parms->dir),
+ hcapi_type, type_str,
+ req_cnt[i],
+ query[hcapi_type].max);
return -EINVAL;
}
}
@@ -689,6 +772,13 @@ tf_rm_create_db(struct tf *tfp,
rm_db->module = parms->module;
*parms->rm_db = (void *)rm_db;
+#if (TF_RM_DEBUG == 1)
+
+ printf("%s: module:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_module_2_str(parms->module));
+#endif /* (TF_RM_DEBUG == 1) */
+
tfp_free((void *)req);
tfp_free((void *)resv);
tfp_free((void *)req_cnt);
@@ -922,6 +1012,13 @@ tf_rm_create_db_no_reservation(struct tf *tfp,
rm_db->module = parms->module;
*parms->rm_db = (void *)rm_db;
+#if (TF_RM_DEBUG == 1)
+
+ printf("%s: module:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_module_2_str(parms->module));
+#endif /* (TF_RM_DEBUG == 1) */
+
tfp_free((void *)req);
tfp_free((void *)resv);
tfp_free((void *)req_cnt);
@@ -1185,7 +1282,6 @@ tf_rm_is_allocated(struct tf_rm_is_allocated_parms *parms)
cfg_type = rm_db->db[parms->subtype].cfg_type;
-
/* Bail out if not controlled by RM */
if (cfg_type != TF_RM_ELEM_CFG_HCAPI_BA &&
cfg_type != TF_RM_ELEM_CFG_HCAPI_BA_PARENT &&
diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.c b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
index d7727f7a11..167078a8c6 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl_sram.c
+++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
@@ -21,6 +21,10 @@
#define DBG_SRAM 0
+#define TF_TBL_PTR_TO_RM(new_idx, idx, base, shift) { \
+ *(new_idx) = (((idx) >> (shift)) - (base)); \
+}
+
/**
* tf_sram_tbl_get_info_parms parameter definition
*/
@@ -394,6 +398,7 @@ tf_tbl_sram_set(struct tf *tfp,
{
int rc;
bool allocated = 0;
+ int rallocated = 0;
uint16_t hcapi_type;
struct tf_rm_get_hcapi_parms hparms = { 0 };
struct tf_session *tfs;
@@ -402,7 +407,9 @@ tf_tbl_sram_set(struct tf *tfp,
void *tbl_db_ptr = NULL;
struct tf_tbl_sram_get_info_parms iparms = { 0 };
struct tf_sram_mgr_is_allocated_parms aparms = { 0 };
+ struct tf_rm_is_allocated_parms raparms = { 0 };
void *sram_handle = NULL;
+ uint16_t base = 0, shift = 0;
TF_CHECK_PARMS3(tfp, parms, parms->data);
@@ -442,23 +449,57 @@ tf_tbl_sram_set(struct tf *tfp,
return rc;
}
- aparms.sram_offset = parms->idx;
- aparms.slice_size = iparms.slice_size;
- aparms.bank_id = iparms.bank_id;
- aparms.dir = parms->dir;
- aparms.is_allocated = &allocated;
- rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
- if (rc || !allocated) {
- TFP_DRV_LOG(ERR,
- "%s: Entry not allocated:%s idx(%d):(%s)\n",
- tf_dir_2_str(parms->dir),
- tf_tbl_type_2_str(parms->type),
- parms->idx,
- strerror(-rc));
- rc = -ENOMEM;
- return rc;
+ if (tf_session_is_shared_session(tfs)) {
+ /* Only get table info if required for the device */
+ if (dev->ops->tf_dev_get_tbl_info) {
+ rc = dev->ops->tf_dev_get_tbl_info(tfp,
+ tbl_db->tbl_db[parms->dir],
+ parms->type,
+ &base,
+ &shift);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get table info:%d\n",
+ tf_dir_2_str(parms->dir),
+ parms->type);
+ return rc;
+ }
+ }
+ TF_TBL_PTR_TO_RM(&raparms.index, parms->idx, base, shift);
+
+ raparms.rm_db = tbl_db->tbl_db[parms->dir];
+ raparms.subtype = parms->type;
+ raparms.allocated = &rallocated;
+ rc = tf_rm_is_allocated(&raparms);
+ if (rc)
+ return rc;
+
+ if (rallocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
+ TFP_DRV_LOG(ERR,
+ "%s, Invalid or not allocated index, type:%s, idx:%d\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->idx);
+ return -EINVAL;
+ }
+ } else {
+ aparms.sram_offset = parms->idx;
+ aparms.slice_size = iparms.slice_size;
+ aparms.bank_id = iparms.bank_id;
+ aparms.dir = parms->dir;
+ aparms.is_allocated = &allocated;
+ rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
+ if (rc || !allocated) {
+ TFP_DRV_LOG(ERR,
+ "%s: Entry not allocated:%s idx(%d):(%s)\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->idx,
+ strerror(-rc));
+ rc = -ENOMEM;
+ return rc;
+ }
}
-
/* Set the entry */
hparms.rm_db = tbl_db->tbl_db[parms->dir];
hparms.subtype = parms->type;
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH 13/14] net/bnxt: add enhancements to TF ULP
2021-09-01 14:24 [dpdk-dev] [PATCH 00/14] enhancements to host based flow table management Venkat Duvvuru
` (11 preceding siblings ...)
2021-09-01 14:24 ` [dpdk-dev] [PATCH 12/14] net/bnxt: sram manager shared session Venkat Duvvuru
@ 2021-09-01 14:24 ` Venkat Duvvuru
2021-09-01 14:24 ` [dpdk-dev] [PATCH 14/14] net/bnxt: add support for testpmd co-existence Venkat Duvvuru
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 00/13] enhancements to host based flow table management Venkat Duvvuru
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-01 14:24 UTC (permalink / raw)
To: dev; +Cc: Kishore Padmanabha, Mike Baucom, Venkat Duvvuru
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
1. Added support to specify l4 port masks in the template. Also enabled
source mac in the wild card key for ingress flows.
2. Added support to enable offload for ipv6 traffic within the vxlan
tunnel connection.
3. The flow counters is reduced from 7168 to 6912 for Whitney.
The stats operation is updated to reflect counts for packets
at egress from CFA instead of ingress to CFA
4. The miss path for the l2 context table is updated with correct
parif and default action handler to handle the miss path for
egress flows.
5. This support enables allocation of encapsulation, modification and
action records dynamically based on a given flow actions.
6. Reduce the l2context resource requests during open_session. Move the
SMAC from the L2Context to the EM/WM
7. Remap the parif in the bd action in order to eliminate incorrect
replication of broadcast packets. The layer 4 source port mask
was incorrectly updated in the outer layer 4 source port mask
instead of inner layer 4. Add the l3 proto to egress rules, switch
to using computed fields for l4 ports, add internal smac to f1/f2
flows, add l3 proto to ingress ipv6 flows
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Mike Baucom <michael.baucom@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
---
drivers/net/bnxt/tf_core/tf_tbl_sram.c | 7 -
.../generic_templates/ulp_template_db_class.c | 8102 ++++++++++++-----
.../generic_templates/ulp_template_db_enum.h | 675 +-
.../generic_templates/ulp_template_db_field.h | 195 +-
.../generic_templates/ulp_template_db_tbl.c | 2136 ++++-
.../ulp_template_db_thor_act.c | 996 +-
.../ulp_template_db_thor_class.c | 7495 ++++++++-------
.../ulp_template_db_wh_plus_class.c | 14 +-
drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c | 4 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 135 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 175 +-
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 10 +
drivers/net/bnxt/tf_ulp/ulp_utils.c | 3 +-
13 files changed, 13538 insertions(+), 6409 deletions(-)
diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.c b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
index 167078a8c6..636811bc2d 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl_sram.c
+++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
@@ -134,11 +134,6 @@ static int tf_tbl_sram_get_info(struct tf_tbl_sram_get_info_parms *parms)
if (slices)
parms->slice_size = tf_tbl_sram_slices_2_size[slices];
- TFP_DRV_LOG(DEBUG,
- "(%s) bank(%s) slice_size(%s)\n",
- tf_tbl_type_2_str(parms->tbl_type),
- tf_sram_bank_2_str(parms->bank_id),
- tf_sram_slice_2_str(parms->slice_size));
return rc;
}
@@ -373,7 +368,6 @@ tf_tbl_sram_free(struct tf *tfp __rte_unused,
return rc;
}
-
#if (DBG_SRAM == 1)
{
struct tf_sram_mgr_dump_parms dparms;
@@ -411,7 +405,6 @@ tf_tbl_sram_set(struct tf *tfp,
void *sram_handle = NULL;
uint16_t base = 0, shift = 0;
-
TF_CHECK_PARMS3(tfp, parms, parms->data);
/* Retrieve the session information */
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
index f74687acfa..ad3866243d 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 20 11:56:39 2021 */
+/* date: Fri Aug 6 11:15:47 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -362,508 +362,652 @@ uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {
[BNXT_ULP_CLASS_HID_315d] = 344,
[BNXT_ULP_CLASS_HID_3612] = 345,
[BNXT_ULP_CLASS_HID_66da] = 346,
- [BNXT_ULP_CLASS_HID_6165] = 347,
- [BNXT_ULP_CLASS_HID_2aa1] = 348,
- [BNXT_ULP_CLASS_HID_09cd] = 349,
- [BNXT_ULP_CLASS_HID_3845] = 350,
- [BNXT_ULP_CLASS_HID_11e9] = 351,
- [BNXT_ULP_CLASS_HID_4361] = 352,
- [BNXT_ULP_CLASS_HID_218d] = 353,
- [BNXT_ULP_CLASS_HID_5105] = 354,
- [BNXT_ULP_CLASS_HID_0c89] = 355,
- [BNXT_ULP_CLASS_HID_3e81] = 356,
- [BNXT_ULP_CLASS_HID_1dad] = 357,
- [BNXT_ULP_CLASS_HID_4ca5] = 358,
- [BNXT_ULP_CLASS_HID_25c9] = 359,
- [BNXT_ULP_CLASS_HID_57c1] = 360,
- [BNXT_ULP_CLASS_HID_33ed] = 361,
- [BNXT_ULP_CLASS_HID_65e5] = 362,
- [BNXT_ULP_CLASS_HID_6dd9] = 363,
- [BNXT_ULP_CLASS_HID_261d] = 364,
- [BNXT_ULP_CLASS_HID_0571] = 365,
- [BNXT_ULP_CLASS_HID_34f9] = 366,
- [BNXT_ULP_CLASS_HID_1d55] = 367,
- [BNXT_ULP_CLASS_HID_4fdd] = 368,
- [BNXT_ULP_CLASS_HID_2d31] = 369,
- [BNXT_ULP_CLASS_HID_5db9] = 370,
- [BNXT_ULP_CLASS_HID_0035] = 371,
- [BNXT_ULP_CLASS_HID_323d] = 372,
- [BNXT_ULP_CLASS_HID_1111] = 373,
- [BNXT_ULP_CLASS_HID_4019] = 374,
- [BNXT_ULP_CLASS_HID_2975] = 375,
- [BNXT_ULP_CLASS_HID_5b7d] = 376,
- [BNXT_ULP_CLASS_HID_3f51] = 377,
- [BNXT_ULP_CLASS_HID_6959] = 378,
- [BNXT_ULP_CLASS_HID_0e85] = 379,
- [BNXT_ULP_CLASS_HID_380d] = 380,
- [BNXT_ULP_CLASS_HID_1f21] = 381,
- [BNXT_ULP_CLASS_HID_4ea9] = 382,
- [BNXT_ULP_CLASS_HID_1705] = 383,
- [BNXT_ULP_CLASS_HID_418d] = 384,
- [BNXT_ULP_CLASS_HID_2721] = 385,
- [BNXT_ULP_CLASS_HID_57a9] = 386,
- [BNXT_ULP_CLASS_HID_1a25] = 387,
- [BNXT_ULP_CLASS_HID_342d] = 388,
- [BNXT_ULP_CLASS_HID_2b01] = 389,
- [BNXT_ULP_CLASS_HID_5a09] = 390,
- [BNXT_ULP_CLASS_HID_2325] = 391,
- [BNXT_ULP_CLASS_HID_5d2d] = 392,
- [BNXT_ULP_CLASS_HID_3101] = 393,
- [BNXT_ULP_CLASS_HID_6309] = 394,
- [BNXT_ULP_CLASS_HID_0bad] = 395,
- [BNXT_ULP_CLASS_HID_2535] = 396,
- [BNXT_ULP_CLASS_HID_1869] = 397,
- [BNXT_ULP_CLASS_HID_4bf1] = 398,
- [BNXT_ULP_CLASS_HID_136d] = 399,
- [BNXT_ULP_CLASS_HID_43f5] = 400,
- [BNXT_ULP_CLASS_HID_2129] = 401,
- [BNXT_ULP_CLASS_HID_53b1] = 402,
- [BNXT_ULP_CLASS_HID_072d] = 403,
- [BNXT_ULP_CLASS_HID_3135] = 404,
- [BNXT_ULP_CLASS_HID_1429] = 405,
- [BNXT_ULP_CLASS_HID_4731] = 406,
- [BNXT_ULP_CLASS_HID_2f6d] = 407,
- [BNXT_ULP_CLASS_HID_5f75] = 408,
- [BNXT_ULP_CLASS_HID_3d69] = 409,
- [BNXT_ULP_CLASS_HID_6f71] = 410,
- [BNXT_ULP_CLASS_HID_0dbd] = 411,
- [BNXT_ULP_CLASS_HID_3f25] = 412,
- [BNXT_ULP_CLASS_HID_1239] = 413,
- [BNXT_ULP_CLASS_HID_4da1] = 414,
- [BNXT_ULP_CLASS_HID_153d] = 415,
- [BNXT_ULP_CLASS_HID_45a5] = 416,
- [BNXT_ULP_CLASS_HID_3bb9] = 417,
- [BNXT_ULP_CLASS_HID_55a1] = 418,
- [BNXT_ULP_CLASS_HID_193d] = 419,
- [BNXT_ULP_CLASS_HID_4b25] = 420,
- [BNXT_ULP_CLASS_HID_2e39] = 421,
- [BNXT_ULP_CLASS_HID_5921] = 422,
- [BNXT_ULP_CLASS_HID_213d] = 423,
- [BNXT_ULP_CLASS_HID_5125] = 424,
- [BNXT_ULP_CLASS_HID_3739] = 425,
- [BNXT_ULP_CLASS_HID_093d] = 426,
- [BNXT_ULP_CLASS_HID_684d] = 427,
- [BNXT_ULP_CLASS_HID_2389] = 428,
- [BNXT_ULP_CLASS_HID_00e5] = 429,
- [BNXT_ULP_CLASS_HID_316d] = 430,
- [BNXT_ULP_CLASS_HID_18c1] = 431,
- [BNXT_ULP_CLASS_HID_4a49] = 432,
- [BNXT_ULP_CLASS_HID_28a5] = 433,
- [BNXT_ULP_CLASS_HID_582d] = 434,
- [BNXT_ULP_CLASS_HID_05a1] = 435,
- [BNXT_ULP_CLASS_HID_37a9] = 436,
- [BNXT_ULP_CLASS_HID_1485] = 437,
- [BNXT_ULP_CLASS_HID_458d] = 438,
- [BNXT_ULP_CLASS_HID_2ce1] = 439,
- [BNXT_ULP_CLASS_HID_5ee9] = 440,
- [BNXT_ULP_CLASS_HID_3ac5] = 441,
- [BNXT_ULP_CLASS_HID_6ccd] = 442,
- [BNXT_ULP_CLASS_HID_0b11] = 443,
- [BNXT_ULP_CLASS_HID_3d99] = 444,
- [BNXT_ULP_CLASS_HID_1ab5] = 445,
- [BNXT_ULP_CLASS_HID_4b3d] = 446,
- [BNXT_ULP_CLASS_HID_1291] = 447,
- [BNXT_ULP_CLASS_HID_4419] = 448,
- [BNXT_ULP_CLASS_HID_22b5] = 449,
- [BNXT_ULP_CLASS_HID_523d] = 450,
- [BNXT_ULP_CLASS_HID_1fb1] = 451,
- [BNXT_ULP_CLASS_HID_31b9] = 452,
- [BNXT_ULP_CLASS_HID_2e95] = 453,
- [BNXT_ULP_CLASS_HID_5f9d] = 454,
- [BNXT_ULP_CLASS_HID_26b1] = 455,
- [BNXT_ULP_CLASS_HID_58b9] = 456,
- [BNXT_ULP_CLASS_HID_3495] = 457,
- [BNXT_ULP_CLASS_HID_669d] = 458,
- [BNXT_ULP_CLASS_HID_0e39] = 459,
- [BNXT_ULP_CLASS_HID_20a1] = 460,
- [BNXT_ULP_CLASS_HID_1dfd] = 461,
- [BNXT_ULP_CLASS_HID_4e65] = 462,
- [BNXT_ULP_CLASS_HID_16f9] = 463,
- [BNXT_ULP_CLASS_HID_4661] = 464,
- [BNXT_ULP_CLASS_HID_24bd] = 465,
- [BNXT_ULP_CLASS_HID_5625] = 466,
- [BNXT_ULP_CLASS_HID_02b9] = 467,
- [BNXT_ULP_CLASS_HID_34a1] = 468,
- [BNXT_ULP_CLASS_HID_11bd] = 469,
- [BNXT_ULP_CLASS_HID_42a5] = 470,
- [BNXT_ULP_CLASS_HID_2af9] = 471,
- [BNXT_ULP_CLASS_HID_5ae1] = 472,
- [BNXT_ULP_CLASS_HID_38fd] = 473,
- [BNXT_ULP_CLASS_HID_6ae5] = 474,
- [BNXT_ULP_CLASS_HID_0829] = 475,
- [BNXT_ULP_CLASS_HID_3ab1] = 476,
- [BNXT_ULP_CLASS_HID_17ad] = 477,
- [BNXT_ULP_CLASS_HID_4835] = 478,
- [BNXT_ULP_CLASS_HID_10a9] = 479,
- [BNXT_ULP_CLASS_HID_4031] = 480,
- [BNXT_ULP_CLASS_HID_3e2d] = 481,
- [BNXT_ULP_CLASS_HID_5035] = 482,
- [BNXT_ULP_CLASS_HID_1ca9] = 483,
- [BNXT_ULP_CLASS_HID_4eb1] = 484,
- [BNXT_ULP_CLASS_HID_2bad] = 485,
- [BNXT_ULP_CLASS_HID_5cb5] = 486,
- [BNXT_ULP_CLASS_HID_24a9] = 487,
- [BNXT_ULP_CLASS_HID_54b1] = 488,
- [BNXT_ULP_CLASS_HID_32ad] = 489,
- [BNXT_ULP_CLASS_HID_0ca9] = 490,
- [BNXT_ULP_CLASS_HID_7f35] = 491,
- [BNXT_ULP_CLASS_HID_34f1] = 492,
- [BNXT_ULP_CLASS_HID_179d] = 493,
- [BNXT_ULP_CLASS_HID_2615] = 494,
- [BNXT_ULP_CLASS_HID_0fb9] = 495,
- [BNXT_ULP_CLASS_HID_5d31] = 496,
- [BNXT_ULP_CLASS_HID_3fdd] = 497,
- [BNXT_ULP_CLASS_HID_4f55] = 498,
- [BNXT_ULP_CLASS_HID_12d9] = 499,
- [BNXT_ULP_CLASS_HID_20d1] = 500,
- [BNXT_ULP_CLASS_HID_03fd] = 501,
- [BNXT_ULP_CLASS_HID_52f5] = 502,
- [BNXT_ULP_CLASS_HID_3b99] = 503,
- [BNXT_ULP_CLASS_HID_4991] = 504,
- [BNXT_ULP_CLASS_HID_2dbd] = 505,
- [BNXT_ULP_CLASS_HID_7bb5] = 506,
- [BNXT_ULP_CLASS_HID_34c6] = 507,
- [BNXT_ULP_CLASS_HID_0c22] = 508,
- [BNXT_ULP_CLASS_HID_1cbe] = 509,
- [BNXT_ULP_CLASS_HID_179a] = 510,
- [BNXT_ULP_CLASS_HID_59be] = 511,
- [BNXT_ULP_CLASS_HID_515a] = 512,
- [BNXT_ULP_CLASS_HID_1c72] = 513,
- [BNXT_ULP_CLASS_HID_171e] = 514,
- [BNXT_ULP_CLASS_HID_19c8] = 515,
- [BNXT_ULP_CLASS_HID_112c] = 516,
- [BNXT_ULP_CLASS_HID_4d68] = 517,
- [BNXT_ULP_CLASS_HID_444c] = 518,
- [BNXT_ULP_CLASS_HID_0e8c] = 519,
- [BNXT_ULP_CLASS_HID_09e0] = 520,
- [BNXT_ULP_CLASS_HID_1af0] = 521,
- [BNXT_ULP_CLASS_HID_15d4] = 522,
- [BNXT_ULP_CLASS_HID_1dd0] = 523,
- [BNXT_ULP_CLASS_HID_14f4] = 524,
- [BNXT_ULP_CLASS_HID_70b0] = 525,
- [BNXT_ULP_CLASS_HID_4854] = 526,
- [BNXT_ULP_CLASS_HID_3dd4] = 527,
- [BNXT_ULP_CLASS_HID_34f8] = 528,
- [BNXT_ULP_CLASS_HID_09e8] = 529,
- [BNXT_ULP_CLASS_HID_008c] = 530,
- [BNXT_ULP_CLASS_HID_34e6] = 531,
- [BNXT_ULP_CLASS_HID_0c02] = 532,
- [BNXT_ULP_CLASS_HID_1c9e] = 533,
- [BNXT_ULP_CLASS_HID_17ba] = 534,
- [BNXT_ULP_CLASS_HID_429e] = 535,
- [BNXT_ULP_CLASS_HID_5dba] = 536,
- [BNXT_ULP_CLASS_HID_2a16] = 537,
- [BNXT_ULP_CLASS_HID_2532] = 538,
- [BNXT_ULP_CLASS_HID_2da2] = 539,
- [BNXT_ULP_CLASS_HID_24fe] = 540,
- [BNXT_ULP_CLASS_HID_355a] = 541,
- [BNXT_ULP_CLASS_HID_0c76] = 542,
- [BNXT_ULP_CLASS_HID_13e6] = 543,
- [BNXT_ULP_CLASS_HID_7276] = 544,
- [BNXT_ULP_CLASS_HID_42d2] = 545,
- [BNXT_ULP_CLASS_HID_5dee] = 546,
- [BNXT_ULP_CLASS_HID_59de] = 547,
- [BNXT_ULP_CLASS_HID_513a] = 548,
- [BNXT_ULP_CLASS_HID_1c12] = 549,
- [BNXT_ULP_CLASS_HID_177e] = 550,
- [BNXT_ULP_CLASS_HID_0e92] = 551,
- [BNXT_ULP_CLASS_HID_09fe] = 552,
- [BNXT_ULP_CLASS_HID_5c1a] = 553,
- [BNXT_ULP_CLASS_HID_5746] = 554,
- [BNXT_ULP_CLASS_HID_79da] = 555,
- [BNXT_ULP_CLASS_HID_7106] = 556,
- [BNXT_ULP_CLASS_HID_3c1e] = 557,
- [BNXT_ULP_CLASS_HID_377a] = 558,
- [BNXT_ULP_CLASS_HID_2e9e] = 559,
- [BNXT_ULP_CLASS_HID_29fa] = 560,
- [BNXT_ULP_CLASS_HID_14d2] = 561,
- [BNXT_ULP_CLASS_HID_7742] = 562,
- [BNXT_ULP_CLASS_HID_3706] = 563,
- [BNXT_ULP_CLASS_HID_0fe2] = 564,
- [BNXT_ULP_CLASS_HID_1f7e] = 565,
- [BNXT_ULP_CLASS_HID_145a] = 566,
- [BNXT_ULP_CLASS_HID_417e] = 567,
- [BNXT_ULP_CLASS_HID_5e5a] = 568,
- [BNXT_ULP_CLASS_HID_29f6] = 569,
- [BNXT_ULP_CLASS_HID_26d2] = 570,
- [BNXT_ULP_CLASS_HID_2e42] = 571,
- [BNXT_ULP_CLASS_HID_271e] = 572,
- [BNXT_ULP_CLASS_HID_36ba] = 573,
- [BNXT_ULP_CLASS_HID_0f96] = 574,
- [BNXT_ULP_CLASS_HID_1006] = 575,
- [BNXT_ULP_CLASS_HID_7196] = 576,
- [BNXT_ULP_CLASS_HID_4132] = 577,
- [BNXT_ULP_CLASS_HID_5e0e] = 578,
- [BNXT_ULP_CLASS_HID_59fe] = 579,
- [BNXT_ULP_CLASS_HID_511a] = 580,
- [BNXT_ULP_CLASS_HID_1c32] = 581,
- [BNXT_ULP_CLASS_HID_175e] = 582,
- [BNXT_ULP_CLASS_HID_0eb2] = 583,
- [BNXT_ULP_CLASS_HID_09de] = 584,
- [BNXT_ULP_CLASS_HID_5c3a] = 585,
- [BNXT_ULP_CLASS_HID_5766] = 586,
- [BNXT_ULP_CLASS_HID_79fa] = 587,
- [BNXT_ULP_CLASS_HID_7126] = 588,
- [BNXT_ULP_CLASS_HID_3c3e] = 589,
- [BNXT_ULP_CLASS_HID_375a] = 590,
- [BNXT_ULP_CLASS_HID_2ebe] = 591,
- [BNXT_ULP_CLASS_HID_29da] = 592,
- [BNXT_ULP_CLASS_HID_14f2] = 593,
- [BNXT_ULP_CLASS_HID_7762] = 594,
- [BNXT_ULP_CLASS_HID_19e8] = 595,
- [BNXT_ULP_CLASS_HID_110c] = 596,
- [BNXT_ULP_CLASS_HID_4d48] = 597,
- [BNXT_ULP_CLASS_HID_446c] = 598,
- [BNXT_ULP_CLASS_HID_0eac] = 599,
- [BNXT_ULP_CLASS_HID_09c0] = 600,
- [BNXT_ULP_CLASS_HID_1ad0] = 601,
- [BNXT_ULP_CLASS_HID_15f4] = 602,
- [BNXT_ULP_CLASS_HID_39ec] = 603,
- [BNXT_ULP_CLASS_HID_3100] = 604,
- [BNXT_ULP_CLASS_HID_0210] = 605,
- [BNXT_ULP_CLASS_HID_1d34] = 606,
- [BNXT_ULP_CLASS_HID_2ea0] = 607,
- [BNXT_ULP_CLASS_HID_29c4] = 608,
- [BNXT_ULP_CLASS_HID_3ad4] = 609,
- [BNXT_ULP_CLASS_HID_35e8] = 610,
- [BNXT_ULP_CLASS_HID_5d80] = 611,
- [BNXT_ULP_CLASS_HID_54a4] = 612,
- [BNXT_ULP_CLASS_HID_29b4] = 613,
- [BNXT_ULP_CLASS_HID_20c8] = 614,
- [BNXT_ULP_CLASS_HID_7244] = 615,
- [BNXT_ULP_CLASS_HID_4d98] = 616,
- [BNXT_ULP_CLASS_HID_5e68] = 617,
- [BNXT_ULP_CLASS_HID_598c] = 618,
- [BNXT_ULP_CLASS_HID_1248] = 619,
- [BNXT_ULP_CLASS_HID_74d8] = 620,
- [BNXT_ULP_CLASS_HID_49a8] = 621,
- [BNXT_ULP_CLASS_HID_40cc] = 622,
- [BNXT_ULP_CLASS_HID_0b0c] = 623,
- [BNXT_ULP_CLASS_HID_0220] = 624,
- [BNXT_ULP_CLASS_HID_1730] = 625,
- [BNXT_ULP_CLASS_HID_7980] = 626,
- [BNXT_ULP_CLASS_HID_1db0] = 627,
- [BNXT_ULP_CLASS_HID_1494] = 628,
- [BNXT_ULP_CLASS_HID_70d0] = 629,
- [BNXT_ULP_CLASS_HID_4834] = 630,
- [BNXT_ULP_CLASS_HID_3db4] = 631,
- [BNXT_ULP_CLASS_HID_3498] = 632,
- [BNXT_ULP_CLASS_HID_0988] = 633,
- [BNXT_ULP_CLASS_HID_00ec] = 634,
- [BNXT_ULP_CLASS_HID_3f44] = 635,
- [BNXT_ULP_CLASS_HID_36a8] = 636,
- [BNXT_ULP_CLASS_HID_0b58] = 637,
- [BNXT_ULP_CLASS_HID_02bc] = 638,
- [BNXT_ULP_CLASS_HID_5f48] = 639,
- [BNXT_ULP_CLASS_HID_56ac] = 640,
- [BNXT_ULP_CLASS_HID_2b5c] = 641,
- [BNXT_ULP_CLASS_HID_2280] = 642,
- [BNXT_ULP_CLASS_HID_4000] = 643,
- [BNXT_ULP_CLASS_HID_5b64] = 644,
- [BNXT_ULP_CLASS_HID_2c14] = 645,
- [BNXT_ULP_CLASS_HID_2778] = 646,
- [BNXT_ULP_CLASS_HID_18f8] = 647,
- [BNXT_ULP_CLASS_HID_13dc] = 648,
- [BNXT_ULP_CLASS_HID_4c18] = 649,
- [BNXT_ULP_CLASS_HID_477c] = 650,
- [BNXT_ULP_CLASS_HID_1a88] = 651,
- [BNXT_ULP_CLASS_HID_15ec] = 652,
- [BNXT_ULP_CLASS_HID_4e28] = 653,
- [BNXT_ULP_CLASS_HID_490c] = 654,
- [BNXT_ULP_CLASS_HID_3a8c] = 655,
- [BNXT_ULP_CLASS_HID_35f0] = 656,
- [BNXT_ULP_CLASS_HID_06e0] = 657,
- [BNXT_ULP_CLASS_HID_01c4] = 658,
- [BNXT_ULP_CLASS_HID_1a08] = 659,
- [BNXT_ULP_CLASS_HID_12ec] = 660,
- [BNXT_ULP_CLASS_HID_4ea8] = 661,
- [BNXT_ULP_CLASS_HID_478c] = 662,
- [BNXT_ULP_CLASS_HID_0d4c] = 663,
- [BNXT_ULP_CLASS_HID_0a20] = 664,
- [BNXT_ULP_CLASS_HID_1930] = 665,
- [BNXT_ULP_CLASS_HID_1614] = 666,
- [BNXT_ULP_CLASS_HID_3a0c] = 667,
- [BNXT_ULP_CLASS_HID_32e0] = 668,
- [BNXT_ULP_CLASS_HID_01f0] = 669,
- [BNXT_ULP_CLASS_HID_1ed4] = 670,
- [BNXT_ULP_CLASS_HID_2d40] = 671,
- [BNXT_ULP_CLASS_HID_2a24] = 672,
- [BNXT_ULP_CLASS_HID_3934] = 673,
- [BNXT_ULP_CLASS_HID_3608] = 674,
- [BNXT_ULP_CLASS_HID_5e60] = 675,
- [BNXT_ULP_CLASS_HID_5744] = 676,
- [BNXT_ULP_CLASS_HID_2a54] = 677,
- [BNXT_ULP_CLASS_HID_2328] = 678,
- [BNXT_ULP_CLASS_HID_71a4] = 679,
- [BNXT_ULP_CLASS_HID_4e78] = 680,
- [BNXT_ULP_CLASS_HID_5d88] = 681,
- [BNXT_ULP_CLASS_HID_5a6c] = 682,
- [BNXT_ULP_CLASS_HID_11a8] = 683,
- [BNXT_ULP_CLASS_HID_7738] = 684,
- [BNXT_ULP_CLASS_HID_4a48] = 685,
- [BNXT_ULP_CLASS_HID_432c] = 686,
- [BNXT_ULP_CLASS_HID_08ec] = 687,
- [BNXT_ULP_CLASS_HID_01c0] = 688,
- [BNXT_ULP_CLASS_HID_14d0] = 689,
- [BNXT_ULP_CLASS_HID_7a60] = 690,
- [BNXT_ULP_CLASS_HID_1d90] = 691,
- [BNXT_ULP_CLASS_HID_14b4] = 692,
- [BNXT_ULP_CLASS_HID_70f0] = 693,
- [BNXT_ULP_CLASS_HID_4814] = 694,
- [BNXT_ULP_CLASS_HID_3d94] = 695,
- [BNXT_ULP_CLASS_HID_34b8] = 696,
- [BNXT_ULP_CLASS_HID_09a8] = 697,
- [BNXT_ULP_CLASS_HID_00cc] = 698,
- [BNXT_ULP_CLASS_HID_3f64] = 699,
- [BNXT_ULP_CLASS_HID_3688] = 700,
- [BNXT_ULP_CLASS_HID_0b78] = 701,
- [BNXT_ULP_CLASS_HID_029c] = 702,
- [BNXT_ULP_CLASS_HID_5f68] = 703,
- [BNXT_ULP_CLASS_HID_568c] = 704,
- [BNXT_ULP_CLASS_HID_2b7c] = 705,
- [BNXT_ULP_CLASS_HID_22a0] = 706,
- [BNXT_ULP_CLASS_HID_4020] = 707,
- [BNXT_ULP_CLASS_HID_5b44] = 708,
- [BNXT_ULP_CLASS_HID_2c34] = 709,
- [BNXT_ULP_CLASS_HID_2758] = 710,
- [BNXT_ULP_CLASS_HID_18d8] = 711,
- [BNXT_ULP_CLASS_HID_13fc] = 712,
- [BNXT_ULP_CLASS_HID_4c38] = 713,
- [BNXT_ULP_CLASS_HID_475c] = 714,
- [BNXT_ULP_CLASS_HID_1aa8] = 715,
- [BNXT_ULP_CLASS_HID_15cc] = 716,
- [BNXT_ULP_CLASS_HID_4e08] = 717,
- [BNXT_ULP_CLASS_HID_492c] = 718,
- [BNXT_ULP_CLASS_HID_3aac] = 719,
- [BNXT_ULP_CLASS_HID_35d0] = 720,
- [BNXT_ULP_CLASS_HID_06c0] = 721,
- [BNXT_ULP_CLASS_HID_01e4] = 722,
- [BNXT_ULP_CLASS_HID_4d32] = 723,
- [BNXT_ULP_CLASS_HID_54aa] = 724,
- [BNXT_ULP_CLASS_HID_0686] = 725,
- [BNXT_ULP_CLASS_HID_540e] = 726,
- [BNXT_ULP_CLASS_HID_2e3c] = 727,
- [BNXT_ULP_CLASS_HID_3a20] = 728,
- [BNXT_ULP_CLASS_HID_46f0] = 729,
- [BNXT_ULP_CLASS_HID_52e4] = 730,
- [BNXT_ULP_CLASS_HID_55e4] = 731,
- [BNXT_ULP_CLASS_HID_21f8] = 732,
- [BNXT_ULP_CLASS_HID_75e8] = 733,
- [BNXT_ULP_CLASS_HID_41fc] = 734,
- [BNXT_ULP_CLASS_HID_4d12] = 735,
- [BNXT_ULP_CLASS_HID_548a] = 736,
- [BNXT_ULP_CLASS_HID_3356] = 737,
- [BNXT_ULP_CLASS_HID_1ace] = 738,
- [BNXT_ULP_CLASS_HID_1a9a] = 739,
- [BNXT_ULP_CLASS_HID_4d46] = 740,
- [BNXT_ULP_CLASS_HID_2812] = 741,
- [BNXT_ULP_CLASS_HID_338a] = 742,
- [BNXT_ULP_CLASS_HID_06e6] = 743,
- [BNXT_ULP_CLASS_HID_546e] = 744,
- [BNXT_ULP_CLASS_HID_46ee] = 745,
- [BNXT_ULP_CLASS_HID_0d22] = 746,
- [BNXT_ULP_CLASS_HID_26e2] = 747,
- [BNXT_ULP_CLASS_HID_746a] = 748,
- [BNXT_ULP_CLASS_HID_1fa6] = 749,
- [BNXT_ULP_CLASS_HID_2d2e] = 750,
- [BNXT_ULP_CLASS_HID_4ef2] = 751,
- [BNXT_ULP_CLASS_HID_576a] = 752,
- [BNXT_ULP_CLASS_HID_30b6] = 753,
- [BNXT_ULP_CLASS_HID_192e] = 754,
- [BNXT_ULP_CLASS_HID_197a] = 755,
- [BNXT_ULP_CLASS_HID_4ea6] = 756,
- [BNXT_ULP_CLASS_HID_2bf2] = 757,
- [BNXT_ULP_CLASS_HID_306a] = 758,
- [BNXT_ULP_CLASS_HID_06c6] = 759,
- [BNXT_ULP_CLASS_HID_544e] = 760,
- [BNXT_ULP_CLASS_HID_46ce] = 761,
- [BNXT_ULP_CLASS_HID_0d02] = 762,
- [BNXT_ULP_CLASS_HID_26c2] = 763,
- [BNXT_ULP_CLASS_HID_744a] = 764,
- [BNXT_ULP_CLASS_HID_1f86] = 765,
- [BNXT_ULP_CLASS_HID_2d0e] = 766,
- [BNXT_ULP_CLASS_HID_2e1c] = 767,
- [BNXT_ULP_CLASS_HID_3a00] = 768,
- [BNXT_ULP_CLASS_HID_46d0] = 769,
- [BNXT_ULP_CLASS_HID_52c4] = 770,
- [BNXT_ULP_CLASS_HID_4e10] = 771,
- [BNXT_ULP_CLASS_HID_5a04] = 772,
- [BNXT_ULP_CLASS_HID_1f98] = 773,
- [BNXT_ULP_CLASS_HID_72f8] = 774,
- [BNXT_ULP_CLASS_HID_0a78] = 775,
- [BNXT_ULP_CLASS_HID_166c] = 776,
- [BNXT_ULP_CLASS_HID_233c] = 777,
- [BNXT_ULP_CLASS_HID_0f20] = 778,
- [BNXT_ULP_CLASS_HID_2a7c] = 779,
- [BNXT_ULP_CLASS_HID_3660] = 780,
- [BNXT_ULP_CLASS_HID_4330] = 781,
- [BNXT_ULP_CLASS_HID_2f24] = 782,
- [BNXT_ULP_CLASS_HID_5584] = 783,
- [BNXT_ULP_CLASS_HID_2198] = 784,
- [BNXT_ULP_CLASS_HID_7588] = 785,
- [BNXT_ULP_CLASS_HID_419c] = 786,
- [BNXT_ULP_CLASS_HID_7758] = 787,
- [BNXT_ULP_CLASS_HID_43ac] = 788,
- [BNXT_ULP_CLASS_HID_0c10] = 789,
- [BNXT_ULP_CLASS_HID_1864] = 790,
- [BNXT_ULP_CLASS_HID_30c8] = 791,
- [BNXT_ULP_CLASS_HID_1cdc] = 792,
- [BNXT_ULP_CLASS_HID_50cc] = 793,
- [BNXT_ULP_CLASS_HID_3d20] = 794,
- [BNXT_ULP_CLASS_HID_529c] = 795,
- [BNXT_ULP_CLASS_HID_3ef0] = 796,
- [BNXT_ULP_CLASS_HID_72e0] = 797,
- [BNXT_ULP_CLASS_HID_5ef4] = 798,
- [BNXT_ULP_CLASS_HID_2dfc] = 799,
- [BNXT_ULP_CLASS_HID_39e0] = 800,
- [BNXT_ULP_CLASS_HID_4530] = 801,
- [BNXT_ULP_CLASS_HID_5124] = 802,
- [BNXT_ULP_CLASS_HID_4df0] = 803,
- [BNXT_ULP_CLASS_HID_59e4] = 804,
- [BNXT_ULP_CLASS_HID_1c78] = 805,
- [BNXT_ULP_CLASS_HID_7118] = 806,
- [BNXT_ULP_CLASS_HID_0998] = 807,
- [BNXT_ULP_CLASS_HID_158c] = 808,
- [BNXT_ULP_CLASS_HID_20dc] = 809,
- [BNXT_ULP_CLASS_HID_0cc0] = 810,
- [BNXT_ULP_CLASS_HID_299c] = 811,
- [BNXT_ULP_CLASS_HID_3580] = 812,
- [BNXT_ULP_CLASS_HID_40d0] = 813,
- [BNXT_ULP_CLASS_HID_2cc4] = 814,
- [BNXT_ULP_CLASS_HID_55a4] = 815,
- [BNXT_ULP_CLASS_HID_21b8] = 816,
- [BNXT_ULP_CLASS_HID_75a8] = 817,
- [BNXT_ULP_CLASS_HID_41bc] = 818,
- [BNXT_ULP_CLASS_HID_7778] = 819,
- [BNXT_ULP_CLASS_HID_438c] = 820,
- [BNXT_ULP_CLASS_HID_0c30] = 821,
- [BNXT_ULP_CLASS_HID_1844] = 822,
- [BNXT_ULP_CLASS_HID_30e8] = 823,
- [BNXT_ULP_CLASS_HID_1cfc] = 824,
- [BNXT_ULP_CLASS_HID_50ec] = 825,
- [BNXT_ULP_CLASS_HID_3d00] = 826,
- [BNXT_ULP_CLASS_HID_52bc] = 827,
- [BNXT_ULP_CLASS_HID_3ed0] = 828,
- [BNXT_ULP_CLASS_HID_72c0] = 829,
- [BNXT_ULP_CLASS_HID_5ed4] = 830,
- [BNXT_ULP_CLASS_HID_3866] = 831,
- [BNXT_ULP_CLASS_HID_381e] = 832,
- [BNXT_ULP_CLASS_HID_3860] = 833,
- [BNXT_ULP_CLASS_HID_0454] = 834,
- [BNXT_ULP_CLASS_HID_3818] = 835,
- [BNXT_ULP_CLASS_HID_042c] = 836,
- [BNXT_ULP_CLASS_HID_3846] = 837,
- [BNXT_ULP_CLASS_HID_387e] = 838,
- [BNXT_ULP_CLASS_HID_3ba6] = 839,
- [BNXT_ULP_CLASS_HID_385e] = 840,
- [BNXT_ULP_CLASS_HID_3840] = 841,
- [BNXT_ULP_CLASS_HID_0474] = 842,
- [BNXT_ULP_CLASS_HID_3878] = 843,
- [BNXT_ULP_CLASS_HID_044c] = 844,
- [BNXT_ULP_CLASS_HID_3ba0] = 845,
- [BNXT_ULP_CLASS_HID_0794] = 846,
- [BNXT_ULP_CLASS_HID_3858] = 847,
- [BNXT_ULP_CLASS_HID_046c] = 848
+ [BNXT_ULP_CLASS_HID_e082] = 347,
+ [BNXT_ULP_CLASS_HID_ab46] = 348,
+ [BNXT_ULP_CLASS_HID_c82a] = 349,
+ [BNXT_ULP_CLASS_HID_f9a2] = 350,
+ [BNXT_ULP_CLASS_HID_d8ce] = 351,
+ [BNXT_ULP_CLASS_HID_a2d2] = 352,
+ [BNXT_ULP_CLASS_HID_c076] = 353,
+ [BNXT_ULP_CLASS_HID_f1ee] = 354,
+ [BNXT_ULP_CLASS_HID_a96e] = 355,
+ [BNXT_ULP_CLASS_HID_dae6] = 356,
+ [BNXT_ULP_CLASS_HID_c7aa] = 357,
+ [BNXT_ULP_CLASS_HID_c26e] = 358,
+ [BNXT_ULP_CLASS_HID_a0fa] = 359,
+ [BNXT_ULP_CLASS_HID_d272] = 360,
+ [BNXT_ULP_CLASS_HID_fff6] = 361,
+ [BNXT_ULP_CLASS_HID_e16e] = 362,
+ [BNXT_ULP_CLASS_HID_e165] = 363,
+ [BNXT_ULP_CLASS_HID_aaa1] = 364,
+ [BNXT_ULP_CLASS_HID_c9cd] = 365,
+ [BNXT_ULP_CLASS_HID_f845] = 366,
+ [BNXT_ULP_CLASS_HID_90f9] = 367,
+ [BNXT_ULP_CLASS_HID_c371] = 368,
+ [BNXT_ULP_CLASS_HID_e19d] = 369,
+ [BNXT_ULP_CLASS_HID_d015] = 370,
+ [BNXT_ULP_CLASS_HID_8c09] = 371,
+ [BNXT_ULP_CLASS_HID_be89] = 372,
+ [BNXT_ULP_CLASS_HID_ddad] = 373,
+ [BNXT_ULP_CLASS_HID_cc2d] = 374,
+ [BNXT_ULP_CLASS_HID_a4d9] = 375,
+ [BNXT_ULP_CLASS_HID_d759] = 376,
+ [BNXT_ULP_CLASS_HID_f27d] = 377,
+ [BNXT_ULP_CLASS_HID_e4fd] = 378,
+ [BNXT_ULP_CLASS_HID_ecf6] = 379,
+ [BNXT_ULP_CLASS_HID_a732] = 380,
+ [BNXT_ULP_CLASS_HID_c45e] = 381,
+ [BNXT_ULP_CLASS_HID_f5d6] = 382,
+ [BNXT_ULP_CLASS_HID_d4ba] = 383,
+ [BNXT_ULP_CLASS_HID_aea6] = 384,
+ [BNXT_ULP_CLASS_HID_cc02] = 385,
+ [BNXT_ULP_CLASS_HID_fd9a] = 386,
+ [BNXT_ULP_CLASS_HID_a51a] = 387,
+ [BNXT_ULP_CLASS_HID_d692] = 388,
+ [BNXT_ULP_CLASS_HID_cbde] = 389,
+ [BNXT_ULP_CLASS_HID_ce1a] = 390,
+ [BNXT_ULP_CLASS_HID_ac8e] = 391,
+ [BNXT_ULP_CLASS_HID_de06] = 392,
+ [BNXT_ULP_CLASS_HID_f382] = 393,
+ [BNXT_ULP_CLASS_HID_ed1a] = 394,
+ [BNXT_ULP_CLASS_HID_9d6a] = 395,
+ [BNXT_ULP_CLASS_HID_cee2] = 396,
+ [BNXT_ULP_CLASS_HID_ec0e] = 397,
+ [BNXT_ULP_CLASS_HID_dd86] = 398,
+ [BNXT_ULP_CLASS_HID_852e] = 399,
+ [BNXT_ULP_CLASS_HID_b6a6] = 400,
+ [BNXT_ULP_CLASS_HID_eb82] = 401,
+ [BNXT_ULP_CLASS_HID_c50a] = 402,
+ [BNXT_ULP_CLASS_HID_ccca] = 403,
+ [BNXT_ULP_CLASS_HID_8706] = 404,
+ [BNXT_ULP_CLASS_HID_d38e] = 405,
+ [BNXT_ULP_CLASS_HID_d5ca] = 406,
+ [BNXT_ULP_CLASS_HID_b48e] = 407,
+ [BNXT_ULP_CLASS_HID_8e8a] = 408,
+ [BNXT_ULP_CLASS_HID_db02] = 409,
+ [BNXT_ULP_CLASS_HID_dd8e] = 410,
+ [BNXT_ULP_CLASS_HID_819a] = 411,
+ [BNXT_ULP_CLASS_HID_b31a] = 412,
+ [BNXT_ULP_CLASS_HID_d03e] = 413,
+ [BNXT_ULP_CLASS_HID_c1be] = 414,
+ [BNXT_ULP_CLASS_HID_890e] = 415,
+ [BNXT_ULP_CLASS_HID_ba8e] = 416,
+ [BNXT_ULP_CLASS_HID_dfaa] = 417,
+ [BNXT_ULP_CLASS_HID_c93a] = 418,
+ [BNXT_ULP_CLASS_HID_b11a] = 419,
+ [BNXT_ULP_CLASS_HID_8b4e] = 420,
+ [BNXT_ULP_CLASS_HID_c79e] = 421,
+ [BNXT_ULP_CLASS_HID_d9da] = 422,
+ [BNXT_ULP_CLASS_HID_b88e] = 423,
+ [BNXT_ULP_CLASS_HID_ea0e] = 424,
+ [BNXT_ULP_CLASS_HID_cf0a] = 425,
+ [BNXT_ULP_CLASS_HID_c18e] = 426,
+ [BNXT_ULP_CLASS_HID_a94a] = 427,
+ [BNXT_ULP_CLASS_HID_daca] = 428,
+ [BNXT_ULP_CLASS_HID_ffee] = 429,
+ [BNXT_ULP_CLASS_HID_e96e] = 430,
+ [BNXT_ULP_CLASS_HID_910e] = 431,
+ [BNXT_ULP_CLASS_HID_c28e] = 432,
+ [BNXT_ULP_CLASS_HID_e7aa] = 433,
+ [BNXT_ULP_CLASS_HID_d12a] = 434,
+ [BNXT_ULP_CLASS_HID_d8ca] = 435,
+ [BNXT_ULP_CLASS_HID_930e] = 436,
+ [BNXT_ULP_CLASS_HID_ef4e] = 437,
+ [BNXT_ULP_CLASS_HID_e18a] = 438,
+ [BNXT_ULP_CLASS_HID_c08e] = 439,
+ [BNXT_ULP_CLASS_HID_9a8a] = 440,
+ [BNXT_ULP_CLASS_HID_d70a] = 441,
+ [BNXT_ULP_CLASS_HID_e90e] = 442,
+ [BNXT_ULP_CLASS_HID_edd9] = 443,
+ [BNXT_ULP_CLASS_HID_a61d] = 444,
+ [BNXT_ULP_CLASS_HID_c571] = 445,
+ [BNXT_ULP_CLASS_HID_f4f9] = 446,
+ [BNXT_ULP_CLASS_HID_9c45] = 447,
+ [BNXT_ULP_CLASS_HID_cfcd] = 448,
+ [BNXT_ULP_CLASS_HID_ed21] = 449,
+ [BNXT_ULP_CLASS_HID_dca9] = 450,
+ [BNXT_ULP_CLASS_HID_80b5] = 451,
+ [BNXT_ULP_CLASS_HID_b235] = 452,
+ [BNXT_ULP_CLASS_HID_d111] = 453,
+ [BNXT_ULP_CLASS_HID_c091] = 454,
+ [BNXT_ULP_CLASS_HID_a865] = 455,
+ [BNXT_ULP_CLASS_HID_dbe5] = 456,
+ [BNXT_ULP_CLASS_HID_fec1] = 457,
+ [BNXT_ULP_CLASS_HID_e841] = 458,
+ [BNXT_ULP_CLASS_HID_8e85] = 459,
+ [BNXT_ULP_CLASS_HID_b80d] = 460,
+ [BNXT_ULP_CLASS_HID_df65] = 461,
+ [BNXT_ULP_CLASS_HID_ceed] = 462,
+ [BNXT_ULP_CLASS_HID_9645] = 463,
+ [BNXT_ULP_CLASS_HID_c1cd] = 464,
+ [BNXT_ULP_CLASS_HID_e725] = 465,
+ [BNXT_ULP_CLASS_HID_d6ad] = 466,
+ [BNXT_ULP_CLASS_HID_9aa5] = 467,
+ [BNXT_ULP_CLASS_HID_b425] = 468,
+ [BNXT_ULP_CLASS_HID_eb05] = 469,
+ [BNXT_ULP_CLASS_HID_da85] = 470,
+ [BNXT_ULP_CLASS_HID_a265] = 471,
+ [BNXT_ULP_CLASS_HID_dde5] = 472,
+ [BNXT_ULP_CLASS_HID_f0c5] = 473,
+ [BNXT_ULP_CLASS_HID_e245] = 474,
+ [BNXT_ULP_CLASS_HID_8b8f] = 475,
+ [BNXT_ULP_CLASS_HID_a517] = 476,
+ [BNXT_ULP_CLASS_HID_d86b] = 477,
+ [BNXT_ULP_CLASS_HID_cbf3] = 478,
+ [BNXT_ULP_CLASS_HID_934f] = 479,
+ [BNXT_ULP_CLASS_HID_c2c7] = 480,
+ [BNXT_ULP_CLASS_HID_e02b] = 481,
+ [BNXT_ULP_CLASS_HID_d3a3] = 482,
+ [BNXT_ULP_CLASS_HID_87a7] = 483,
+ [BNXT_ULP_CLASS_HID_b137] = 484,
+ [BNXT_ULP_CLASS_HID_d403] = 485,
+ [BNXT_ULP_CLASS_HID_c793] = 486,
+ [BNXT_ULP_CLASS_HID_af67] = 487,
+ [BNXT_ULP_CLASS_HID_dee7] = 488,
+ [BNXT_ULP_CLASS_HID_fdc3] = 489,
+ [BNXT_ULP_CLASS_HID_ef43] = 490,
+ [BNXT_ULP_CLASS_HID_8dbf] = 491,
+ [BNXT_ULP_CLASS_HID_bf07] = 492,
+ [BNXT_ULP_CLASS_HID_d21f] = 493,
+ [BNXT_ULP_CLASS_HID_cde7] = 494,
+ [BNXT_ULP_CLASS_HID_956f] = 495,
+ [BNXT_ULP_CLASS_HID_c4c7] = 496,
+ [BNXT_ULP_CLASS_HID_fbcf] = 497,
+ [BNXT_ULP_CLASS_HID_d5a7] = 498,
+ [BNXT_ULP_CLASS_HID_9957] = 499,
+ [BNXT_ULP_CLASS_HID_cb27] = 500,
+ [BNXT_ULP_CLASS_HID_ee37] = 501,
+ [BNXT_ULP_CLASS_HID_d987] = 502,
+ [BNXT_ULP_CLASS_HID_a107] = 503,
+ [BNXT_ULP_CLASS_HID_d0e7] = 504,
+ [BNXT_ULP_CLASS_HID_f7e7] = 505,
+ [BNXT_ULP_CLASS_HID_c827] = 506,
+ [BNXT_ULP_CLASS_HID_f76a] = 507,
+ [BNXT_ULP_CLASS_HID_bcae] = 508,
+ [BNXT_ULP_CLASS_HID_dfc2] = 509,
+ [BNXT_ULP_CLASS_HID_ee4a] = 510,
+ [BNXT_ULP_CLASS_HID_cf26] = 511,
+ [BNXT_ULP_CLASS_HID_b53a] = 512,
+ [BNXT_ULP_CLASS_HID_d79e] = 513,
+ [BNXT_ULP_CLASS_HID_e606] = 514,
+ [BNXT_ULP_CLASS_HID_be86] = 515,
+ [BNXT_ULP_CLASS_HID_cd0e] = 516,
+ [BNXT_ULP_CLASS_HID_d042] = 517,
+ [BNXT_ULP_CLASS_HID_d586] = 518,
+ [BNXT_ULP_CLASS_HID_b712] = 519,
+ [BNXT_ULP_CLASS_HID_c59a] = 520,
+ [BNXT_ULP_CLASS_HID_e81e] = 521,
+ [BNXT_ULP_CLASS_HID_f686] = 522,
+ [BNXT_ULP_CLASS_HID_86f6] = 523,
+ [BNXT_ULP_CLASS_HID_d57e] = 524,
+ [BNXT_ULP_CLASS_HID_f792] = 525,
+ [BNXT_ULP_CLASS_HID_c61a] = 526,
+ [BNXT_ULP_CLASS_HID_9eb2] = 527,
+ [BNXT_ULP_CLASS_HID_ad3a] = 528,
+ [BNXT_ULP_CLASS_HID_f01e] = 529,
+ [BNXT_ULP_CLASS_HID_de96] = 530,
+ [BNXT_ULP_CLASS_HID_d756] = 531,
+ [BNXT_ULP_CLASS_HID_9c9a] = 532,
+ [BNXT_ULP_CLASS_HID_c812] = 533,
+ [BNXT_ULP_CLASS_HID_ce56] = 534,
+ [BNXT_ULP_CLASS_HID_af12] = 535,
+ [BNXT_ULP_CLASS_HID_9516] = 536,
+ [BNXT_ULP_CLASS_HID_c09e] = 537,
+ [BNXT_ULP_CLASS_HID_c612] = 538,
+ [BNXT_ULP_CLASS_HID_9a06] = 539,
+ [BNXT_ULP_CLASS_HID_a886] = 540,
+ [BNXT_ULP_CLASS_HID_cba2] = 541,
+ [BNXT_ULP_CLASS_HID_da22] = 542,
+ [BNXT_ULP_CLASS_HID_9292] = 543,
+ [BNXT_ULP_CLASS_HID_a112] = 544,
+ [BNXT_ULP_CLASS_HID_c436] = 545,
+ [BNXT_ULP_CLASS_HID_d2a6] = 546,
+ [BNXT_ULP_CLASS_HID_aa86] = 547,
+ [BNXT_ULP_CLASS_HID_90d2] = 548,
+ [BNXT_ULP_CLASS_HID_dc02] = 549,
+ [BNXT_ULP_CLASS_HID_c246] = 550,
+ [BNXT_ULP_CLASS_HID_a312] = 551,
+ [BNXT_ULP_CLASS_HID_f192] = 552,
+ [BNXT_ULP_CLASS_HID_d496] = 553,
+ [BNXT_ULP_CLASS_HID_da12] = 554,
+ [BNXT_ULP_CLASS_HID_b2d6] = 555,
+ [BNXT_ULP_CLASS_HID_c156] = 556,
+ [BNXT_ULP_CLASS_HID_e472] = 557,
+ [BNXT_ULP_CLASS_HID_f2f2] = 558,
+ [BNXT_ULP_CLASS_HID_8a92] = 559,
+ [BNXT_ULP_CLASS_HID_d912] = 560,
+ [BNXT_ULP_CLASS_HID_fc36] = 561,
+ [BNXT_ULP_CLASS_HID_cab6] = 562,
+ [BNXT_ULP_CLASS_HID_c356] = 563,
+ [BNXT_ULP_CLASS_HID_8892] = 564,
+ [BNXT_ULP_CLASS_HID_f4d2] = 565,
+ [BNXT_ULP_CLASS_HID_fa16] = 566,
+ [BNXT_ULP_CLASS_HID_db12] = 567,
+ [BNXT_ULP_CLASS_HID_8116] = 568,
+ [BNXT_ULP_CLASS_HID_cc96] = 569,
+ [BNXT_ULP_CLASS_HID_f292] = 570,
+ [BNXT_ULP_CLASS_HID_e84d] = 571,
+ [BNXT_ULP_CLASS_HID_a389] = 572,
+ [BNXT_ULP_CLASS_HID_c0e5] = 573,
+ [BNXT_ULP_CLASS_HID_f16d] = 574,
+ [BNXT_ULP_CLASS_HID_99d1] = 575,
+ [BNXT_ULP_CLASS_HID_ca59] = 576,
+ [BNXT_ULP_CLASS_HID_e8b5] = 577,
+ [BNXT_ULP_CLASS_HID_d93d] = 578,
+ [BNXT_ULP_CLASS_HID_8521] = 579,
+ [BNXT_ULP_CLASS_HID_b7a1] = 580,
+ [BNXT_ULP_CLASS_HID_d485] = 581,
+ [BNXT_ULP_CLASS_HID_c505] = 582,
+ [BNXT_ULP_CLASS_HID_adf1] = 583,
+ [BNXT_ULP_CLASS_HID_de71] = 584,
+ [BNXT_ULP_CLASS_HID_fb55] = 585,
+ [BNXT_ULP_CLASS_HID_edd5] = 586,
+ [BNXT_ULP_CLASS_HID_8b11] = 587,
+ [BNXT_ULP_CLASS_HID_bd99] = 588,
+ [BNXT_ULP_CLASS_HID_daf1] = 589,
+ [BNXT_ULP_CLASS_HID_cb79] = 590,
+ [BNXT_ULP_CLASS_HID_93d1] = 591,
+ [BNXT_ULP_CLASS_HID_c459] = 592,
+ [BNXT_ULP_CLASS_HID_e2b1] = 593,
+ [BNXT_ULP_CLASS_HID_d339] = 594,
+ [BNXT_ULP_CLASS_HID_9f31] = 595,
+ [BNXT_ULP_CLASS_HID_b1b1] = 596,
+ [BNXT_ULP_CLASS_HID_ee91] = 597,
+ [BNXT_ULP_CLASS_HID_df11] = 598,
+ [BNXT_ULP_CLASS_HID_a7f1] = 599,
+ [BNXT_ULP_CLASS_HID_d871] = 600,
+ [BNXT_ULP_CLASS_HID_f551] = 601,
+ [BNXT_ULP_CLASS_HID_e7d1] = 602,
+ [BNXT_ULP_CLASS_HID_8e1b] = 603,
+ [BNXT_ULP_CLASS_HID_a083] = 604,
+ [BNXT_ULP_CLASS_HID_ddff] = 605,
+ [BNXT_ULP_CLASS_HID_ce67] = 606,
+ [BNXT_ULP_CLASS_HID_96db] = 607,
+ [BNXT_ULP_CLASS_HID_c753] = 608,
+ [BNXT_ULP_CLASS_HID_e5bf] = 609,
+ [BNXT_ULP_CLASS_HID_d637] = 610,
+ [BNXT_ULP_CLASS_HID_8233] = 611,
+ [BNXT_ULP_CLASS_HID_b4a3] = 612,
+ [BNXT_ULP_CLASS_HID_d197] = 613,
+ [BNXT_ULP_CLASS_HID_c207] = 614,
+ [BNXT_ULP_CLASS_HID_aaf3] = 615,
+ [BNXT_ULP_CLASS_HID_db73] = 616,
+ [BNXT_ULP_CLASS_HID_f857] = 617,
+ [BNXT_ULP_CLASS_HID_ead7] = 618,
+ [BNXT_ULP_CLASS_HID_882b] = 619,
+ [BNXT_ULP_CLASS_HID_ba93] = 620,
+ [BNXT_ULP_CLASS_HID_d78b] = 621,
+ [BNXT_ULP_CLASS_HID_c873] = 622,
+ [BNXT_ULP_CLASS_HID_90fb] = 623,
+ [BNXT_ULP_CLASS_HID_c153] = 624,
+ [BNXT_ULP_CLASS_HID_fe5b] = 625,
+ [BNXT_ULP_CLASS_HID_d033] = 626,
+ [BNXT_ULP_CLASS_HID_9cc3] = 627,
+ [BNXT_ULP_CLASS_HID_ceb3] = 628,
+ [BNXT_ULP_CLASS_HID_eba3] = 629,
+ [BNXT_ULP_CLASS_HID_dc13] = 630,
+ [BNXT_ULP_CLASS_HID_a493] = 631,
+ [BNXT_ULP_CLASS_HID_d573] = 632,
+ [BNXT_ULP_CLASS_HID_f273] = 633,
+ [BNXT_ULP_CLASS_HID_cdb3] = 634,
+ [BNXT_ULP_CLASS_HID_ff35] = 635,
+ [BNXT_ULP_CLASS_HID_b4f1] = 636,
+ [BNXT_ULP_CLASS_HID_d79d] = 637,
+ [BNXT_ULP_CLASS_HID_e615] = 638,
+ [BNXT_ULP_CLASS_HID_8ea9] = 639,
+ [BNXT_ULP_CLASS_HID_dd21] = 640,
+ [BNXT_ULP_CLASS_HID_ffcd] = 641,
+ [BNXT_ULP_CLASS_HID_ce45] = 642,
+ [BNXT_ULP_CLASS_HID_9259] = 643,
+ [BNXT_ULP_CLASS_HID_a0d9] = 644,
+ [BNXT_ULP_CLASS_HID_c3fd] = 645,
+ [BNXT_ULP_CLASS_HID_d27d] = 646,
+ [BNXT_ULP_CLASS_HID_ba89] = 647,
+ [BNXT_ULP_CLASS_HID_c909] = 648,
+ [BNXT_ULP_CLASS_HID_ec2d] = 649,
+ [BNXT_ULP_CLASS_HID_faad] = 650,
+ [BNXT_ULP_CLASS_HID_34c6] = 651,
+ [BNXT_ULP_CLASS_HID_0c22] = 652,
+ [BNXT_ULP_CLASS_HID_1cbe] = 653,
+ [BNXT_ULP_CLASS_HID_179a] = 654,
+ [BNXT_ULP_CLASS_HID_59be] = 655,
+ [BNXT_ULP_CLASS_HID_515a] = 656,
+ [BNXT_ULP_CLASS_HID_1c72] = 657,
+ [BNXT_ULP_CLASS_HID_171e] = 658,
+ [BNXT_ULP_CLASS_HID_19c8] = 659,
+ [BNXT_ULP_CLASS_HID_112c] = 660,
+ [BNXT_ULP_CLASS_HID_4d68] = 661,
+ [BNXT_ULP_CLASS_HID_444c] = 662,
+ [BNXT_ULP_CLASS_HID_0e8c] = 663,
+ [BNXT_ULP_CLASS_HID_09e0] = 664,
+ [BNXT_ULP_CLASS_HID_1af0] = 665,
+ [BNXT_ULP_CLASS_HID_15d4] = 666,
+ [BNXT_ULP_CLASS_HID_1dd0] = 667,
+ [BNXT_ULP_CLASS_HID_14f4] = 668,
+ [BNXT_ULP_CLASS_HID_70b0] = 669,
+ [BNXT_ULP_CLASS_HID_4854] = 670,
+ [BNXT_ULP_CLASS_HID_3dd4] = 671,
+ [BNXT_ULP_CLASS_HID_34f8] = 672,
+ [BNXT_ULP_CLASS_HID_09e8] = 673,
+ [BNXT_ULP_CLASS_HID_008c] = 674,
+ [BNXT_ULP_CLASS_HID_34e6] = 675,
+ [BNXT_ULP_CLASS_HID_0c02] = 676,
+ [BNXT_ULP_CLASS_HID_1c9e] = 677,
+ [BNXT_ULP_CLASS_HID_17ba] = 678,
+ [BNXT_ULP_CLASS_HID_429e] = 679,
+ [BNXT_ULP_CLASS_HID_5dba] = 680,
+ [BNXT_ULP_CLASS_HID_2a16] = 681,
+ [BNXT_ULP_CLASS_HID_2532] = 682,
+ [BNXT_ULP_CLASS_HID_2da2] = 683,
+ [BNXT_ULP_CLASS_HID_24fe] = 684,
+ [BNXT_ULP_CLASS_HID_355a] = 685,
+ [BNXT_ULP_CLASS_HID_0c76] = 686,
+ [BNXT_ULP_CLASS_HID_13e6] = 687,
+ [BNXT_ULP_CLASS_HID_7276] = 688,
+ [BNXT_ULP_CLASS_HID_42d2] = 689,
+ [BNXT_ULP_CLASS_HID_5dee] = 690,
+ [BNXT_ULP_CLASS_HID_59de] = 691,
+ [BNXT_ULP_CLASS_HID_513a] = 692,
+ [BNXT_ULP_CLASS_HID_1c12] = 693,
+ [BNXT_ULP_CLASS_HID_177e] = 694,
+ [BNXT_ULP_CLASS_HID_0e92] = 695,
+ [BNXT_ULP_CLASS_HID_09fe] = 696,
+ [BNXT_ULP_CLASS_HID_5c1a] = 697,
+ [BNXT_ULP_CLASS_HID_5746] = 698,
+ [BNXT_ULP_CLASS_HID_79da] = 699,
+ [BNXT_ULP_CLASS_HID_7106] = 700,
+ [BNXT_ULP_CLASS_HID_3c1e] = 701,
+ [BNXT_ULP_CLASS_HID_377a] = 702,
+ [BNXT_ULP_CLASS_HID_2e9e] = 703,
+ [BNXT_ULP_CLASS_HID_29fa] = 704,
+ [BNXT_ULP_CLASS_HID_14d2] = 705,
+ [BNXT_ULP_CLASS_HID_7742] = 706,
+ [BNXT_ULP_CLASS_HID_3706] = 707,
+ [BNXT_ULP_CLASS_HID_0fe2] = 708,
+ [BNXT_ULP_CLASS_HID_1f7e] = 709,
+ [BNXT_ULP_CLASS_HID_145a] = 710,
+ [BNXT_ULP_CLASS_HID_417e] = 711,
+ [BNXT_ULP_CLASS_HID_5e5a] = 712,
+ [BNXT_ULP_CLASS_HID_29f6] = 713,
+ [BNXT_ULP_CLASS_HID_26d2] = 714,
+ [BNXT_ULP_CLASS_HID_2e42] = 715,
+ [BNXT_ULP_CLASS_HID_271e] = 716,
+ [BNXT_ULP_CLASS_HID_36ba] = 717,
+ [BNXT_ULP_CLASS_HID_0f96] = 718,
+ [BNXT_ULP_CLASS_HID_1006] = 719,
+ [BNXT_ULP_CLASS_HID_7196] = 720,
+ [BNXT_ULP_CLASS_HID_4132] = 721,
+ [BNXT_ULP_CLASS_HID_5e0e] = 722,
+ [BNXT_ULP_CLASS_HID_59fe] = 723,
+ [BNXT_ULP_CLASS_HID_511a] = 724,
+ [BNXT_ULP_CLASS_HID_1c32] = 725,
+ [BNXT_ULP_CLASS_HID_175e] = 726,
+ [BNXT_ULP_CLASS_HID_0eb2] = 727,
+ [BNXT_ULP_CLASS_HID_09de] = 728,
+ [BNXT_ULP_CLASS_HID_5c3a] = 729,
+ [BNXT_ULP_CLASS_HID_5766] = 730,
+ [BNXT_ULP_CLASS_HID_79fa] = 731,
+ [BNXT_ULP_CLASS_HID_7126] = 732,
+ [BNXT_ULP_CLASS_HID_3c3e] = 733,
+ [BNXT_ULP_CLASS_HID_375a] = 734,
+ [BNXT_ULP_CLASS_HID_2ebe] = 735,
+ [BNXT_ULP_CLASS_HID_29da] = 736,
+ [BNXT_ULP_CLASS_HID_14f2] = 737,
+ [BNXT_ULP_CLASS_HID_7762] = 738,
+ [BNXT_ULP_CLASS_HID_19e8] = 739,
+ [BNXT_ULP_CLASS_HID_110c] = 740,
+ [BNXT_ULP_CLASS_HID_4d48] = 741,
+ [BNXT_ULP_CLASS_HID_446c] = 742,
+ [BNXT_ULP_CLASS_HID_0eac] = 743,
+ [BNXT_ULP_CLASS_HID_09c0] = 744,
+ [BNXT_ULP_CLASS_HID_1ad0] = 745,
+ [BNXT_ULP_CLASS_HID_15f4] = 746,
+ [BNXT_ULP_CLASS_HID_39ec] = 747,
+ [BNXT_ULP_CLASS_HID_3100] = 748,
+ [BNXT_ULP_CLASS_HID_0210] = 749,
+ [BNXT_ULP_CLASS_HID_1d34] = 750,
+ [BNXT_ULP_CLASS_HID_2ea0] = 751,
+ [BNXT_ULP_CLASS_HID_29c4] = 752,
+ [BNXT_ULP_CLASS_HID_3ad4] = 753,
+ [BNXT_ULP_CLASS_HID_35e8] = 754,
+ [BNXT_ULP_CLASS_HID_5d80] = 755,
+ [BNXT_ULP_CLASS_HID_54a4] = 756,
+ [BNXT_ULP_CLASS_HID_29b4] = 757,
+ [BNXT_ULP_CLASS_HID_20c8] = 758,
+ [BNXT_ULP_CLASS_HID_7244] = 759,
+ [BNXT_ULP_CLASS_HID_4d98] = 760,
+ [BNXT_ULP_CLASS_HID_5e68] = 761,
+ [BNXT_ULP_CLASS_HID_598c] = 762,
+ [BNXT_ULP_CLASS_HID_1248] = 763,
+ [BNXT_ULP_CLASS_HID_74d8] = 764,
+ [BNXT_ULP_CLASS_HID_49a8] = 765,
+ [BNXT_ULP_CLASS_HID_40cc] = 766,
+ [BNXT_ULP_CLASS_HID_0b0c] = 767,
+ [BNXT_ULP_CLASS_HID_0220] = 768,
+ [BNXT_ULP_CLASS_HID_1730] = 769,
+ [BNXT_ULP_CLASS_HID_7980] = 770,
+ [BNXT_ULP_CLASS_HID_1db0] = 771,
+ [BNXT_ULP_CLASS_HID_1494] = 772,
+ [BNXT_ULP_CLASS_HID_70d0] = 773,
+ [BNXT_ULP_CLASS_HID_4834] = 774,
+ [BNXT_ULP_CLASS_HID_3db4] = 775,
+ [BNXT_ULP_CLASS_HID_3498] = 776,
+ [BNXT_ULP_CLASS_HID_0988] = 777,
+ [BNXT_ULP_CLASS_HID_00ec] = 778,
+ [BNXT_ULP_CLASS_HID_3f44] = 779,
+ [BNXT_ULP_CLASS_HID_36a8] = 780,
+ [BNXT_ULP_CLASS_HID_0b58] = 781,
+ [BNXT_ULP_CLASS_HID_02bc] = 782,
+ [BNXT_ULP_CLASS_HID_5f48] = 783,
+ [BNXT_ULP_CLASS_HID_56ac] = 784,
+ [BNXT_ULP_CLASS_HID_2b5c] = 785,
+ [BNXT_ULP_CLASS_HID_2280] = 786,
+ [BNXT_ULP_CLASS_HID_4000] = 787,
+ [BNXT_ULP_CLASS_HID_5b64] = 788,
+ [BNXT_ULP_CLASS_HID_2c14] = 789,
+ [BNXT_ULP_CLASS_HID_2778] = 790,
+ [BNXT_ULP_CLASS_HID_18f8] = 791,
+ [BNXT_ULP_CLASS_HID_13dc] = 792,
+ [BNXT_ULP_CLASS_HID_4c18] = 793,
+ [BNXT_ULP_CLASS_HID_477c] = 794,
+ [BNXT_ULP_CLASS_HID_1a88] = 795,
+ [BNXT_ULP_CLASS_HID_15ec] = 796,
+ [BNXT_ULP_CLASS_HID_4e28] = 797,
+ [BNXT_ULP_CLASS_HID_490c] = 798,
+ [BNXT_ULP_CLASS_HID_3a8c] = 799,
+ [BNXT_ULP_CLASS_HID_35f0] = 800,
+ [BNXT_ULP_CLASS_HID_06e0] = 801,
+ [BNXT_ULP_CLASS_HID_01c4] = 802,
+ [BNXT_ULP_CLASS_HID_1a08] = 803,
+ [BNXT_ULP_CLASS_HID_12ec] = 804,
+ [BNXT_ULP_CLASS_HID_4ea8] = 805,
+ [BNXT_ULP_CLASS_HID_478c] = 806,
+ [BNXT_ULP_CLASS_HID_0d4c] = 807,
+ [BNXT_ULP_CLASS_HID_0a20] = 808,
+ [BNXT_ULP_CLASS_HID_1930] = 809,
+ [BNXT_ULP_CLASS_HID_1614] = 810,
+ [BNXT_ULP_CLASS_HID_3a0c] = 811,
+ [BNXT_ULP_CLASS_HID_32e0] = 812,
+ [BNXT_ULP_CLASS_HID_01f0] = 813,
+ [BNXT_ULP_CLASS_HID_1ed4] = 814,
+ [BNXT_ULP_CLASS_HID_2d40] = 815,
+ [BNXT_ULP_CLASS_HID_2a24] = 816,
+ [BNXT_ULP_CLASS_HID_3934] = 817,
+ [BNXT_ULP_CLASS_HID_3608] = 818,
+ [BNXT_ULP_CLASS_HID_5e60] = 819,
+ [BNXT_ULP_CLASS_HID_5744] = 820,
+ [BNXT_ULP_CLASS_HID_2a54] = 821,
+ [BNXT_ULP_CLASS_HID_2328] = 822,
+ [BNXT_ULP_CLASS_HID_71a4] = 823,
+ [BNXT_ULP_CLASS_HID_4e78] = 824,
+ [BNXT_ULP_CLASS_HID_5d88] = 825,
+ [BNXT_ULP_CLASS_HID_5a6c] = 826,
+ [BNXT_ULP_CLASS_HID_11a8] = 827,
+ [BNXT_ULP_CLASS_HID_7738] = 828,
+ [BNXT_ULP_CLASS_HID_4a48] = 829,
+ [BNXT_ULP_CLASS_HID_432c] = 830,
+ [BNXT_ULP_CLASS_HID_08ec] = 831,
+ [BNXT_ULP_CLASS_HID_01c0] = 832,
+ [BNXT_ULP_CLASS_HID_14d0] = 833,
+ [BNXT_ULP_CLASS_HID_7a60] = 834,
+ [BNXT_ULP_CLASS_HID_1d90] = 835,
+ [BNXT_ULP_CLASS_HID_14b4] = 836,
+ [BNXT_ULP_CLASS_HID_70f0] = 837,
+ [BNXT_ULP_CLASS_HID_4814] = 838,
+ [BNXT_ULP_CLASS_HID_3d94] = 839,
+ [BNXT_ULP_CLASS_HID_34b8] = 840,
+ [BNXT_ULP_CLASS_HID_09a8] = 841,
+ [BNXT_ULP_CLASS_HID_00cc] = 842,
+ [BNXT_ULP_CLASS_HID_3f64] = 843,
+ [BNXT_ULP_CLASS_HID_3688] = 844,
+ [BNXT_ULP_CLASS_HID_0b78] = 845,
+ [BNXT_ULP_CLASS_HID_029c] = 846,
+ [BNXT_ULP_CLASS_HID_5f68] = 847,
+ [BNXT_ULP_CLASS_HID_568c] = 848,
+ [BNXT_ULP_CLASS_HID_2b7c] = 849,
+ [BNXT_ULP_CLASS_HID_22a0] = 850,
+ [BNXT_ULP_CLASS_HID_4020] = 851,
+ [BNXT_ULP_CLASS_HID_5b44] = 852,
+ [BNXT_ULP_CLASS_HID_2c34] = 853,
+ [BNXT_ULP_CLASS_HID_2758] = 854,
+ [BNXT_ULP_CLASS_HID_18d8] = 855,
+ [BNXT_ULP_CLASS_HID_13fc] = 856,
+ [BNXT_ULP_CLASS_HID_4c38] = 857,
+ [BNXT_ULP_CLASS_HID_475c] = 858,
+ [BNXT_ULP_CLASS_HID_1aa8] = 859,
+ [BNXT_ULP_CLASS_HID_15cc] = 860,
+ [BNXT_ULP_CLASS_HID_4e08] = 861,
+ [BNXT_ULP_CLASS_HID_492c] = 862,
+ [BNXT_ULP_CLASS_HID_3aac] = 863,
+ [BNXT_ULP_CLASS_HID_35d0] = 864,
+ [BNXT_ULP_CLASS_HID_06c0] = 865,
+ [BNXT_ULP_CLASS_HID_01e4] = 866,
+ [BNXT_ULP_CLASS_HID_4d32] = 867,
+ [BNXT_ULP_CLASS_HID_54aa] = 868,
+ [BNXT_ULP_CLASS_HID_0686] = 869,
+ [BNXT_ULP_CLASS_HID_540e] = 870,
+ [BNXT_ULP_CLASS_HID_2e3c] = 871,
+ [BNXT_ULP_CLASS_HID_3a20] = 872,
+ [BNXT_ULP_CLASS_HID_46f0] = 873,
+ [BNXT_ULP_CLASS_HID_52e4] = 874,
+ [BNXT_ULP_CLASS_HID_55e4] = 875,
+ [BNXT_ULP_CLASS_HID_21f8] = 876,
+ [BNXT_ULP_CLASS_HID_75e8] = 877,
+ [BNXT_ULP_CLASS_HID_41fc] = 878,
+ [BNXT_ULP_CLASS_HID_4d12] = 879,
+ [BNXT_ULP_CLASS_HID_548a] = 880,
+ [BNXT_ULP_CLASS_HID_3356] = 881,
+ [BNXT_ULP_CLASS_HID_1ace] = 882,
+ [BNXT_ULP_CLASS_HID_1a9a] = 883,
+ [BNXT_ULP_CLASS_HID_4d46] = 884,
+ [BNXT_ULP_CLASS_HID_2812] = 885,
+ [BNXT_ULP_CLASS_HID_338a] = 886,
+ [BNXT_ULP_CLASS_HID_06e6] = 887,
+ [BNXT_ULP_CLASS_HID_546e] = 888,
+ [BNXT_ULP_CLASS_HID_46ee] = 889,
+ [BNXT_ULP_CLASS_HID_0d22] = 890,
+ [BNXT_ULP_CLASS_HID_26e2] = 891,
+ [BNXT_ULP_CLASS_HID_746a] = 892,
+ [BNXT_ULP_CLASS_HID_1fa6] = 893,
+ [BNXT_ULP_CLASS_HID_2d2e] = 894,
+ [BNXT_ULP_CLASS_HID_4ef2] = 895,
+ [BNXT_ULP_CLASS_HID_576a] = 896,
+ [BNXT_ULP_CLASS_HID_30b6] = 897,
+ [BNXT_ULP_CLASS_HID_192e] = 898,
+ [BNXT_ULP_CLASS_HID_197a] = 899,
+ [BNXT_ULP_CLASS_HID_4ea6] = 900,
+ [BNXT_ULP_CLASS_HID_2bf2] = 901,
+ [BNXT_ULP_CLASS_HID_306a] = 902,
+ [BNXT_ULP_CLASS_HID_06c6] = 903,
+ [BNXT_ULP_CLASS_HID_544e] = 904,
+ [BNXT_ULP_CLASS_HID_46ce] = 905,
+ [BNXT_ULP_CLASS_HID_0d02] = 906,
+ [BNXT_ULP_CLASS_HID_26c2] = 907,
+ [BNXT_ULP_CLASS_HID_744a] = 908,
+ [BNXT_ULP_CLASS_HID_1f86] = 909,
+ [BNXT_ULP_CLASS_HID_2d0e] = 910,
+ [BNXT_ULP_CLASS_HID_2e1c] = 911,
+ [BNXT_ULP_CLASS_HID_3a00] = 912,
+ [BNXT_ULP_CLASS_HID_46d0] = 913,
+ [BNXT_ULP_CLASS_HID_52c4] = 914,
+ [BNXT_ULP_CLASS_HID_4e10] = 915,
+ [BNXT_ULP_CLASS_HID_5a04] = 916,
+ [BNXT_ULP_CLASS_HID_1f98] = 917,
+ [BNXT_ULP_CLASS_HID_72f8] = 918,
+ [BNXT_ULP_CLASS_HID_0a78] = 919,
+ [BNXT_ULP_CLASS_HID_166c] = 920,
+ [BNXT_ULP_CLASS_HID_233c] = 921,
+ [BNXT_ULP_CLASS_HID_0f20] = 922,
+ [BNXT_ULP_CLASS_HID_2a7c] = 923,
+ [BNXT_ULP_CLASS_HID_3660] = 924,
+ [BNXT_ULP_CLASS_HID_4330] = 925,
+ [BNXT_ULP_CLASS_HID_2f24] = 926,
+ [BNXT_ULP_CLASS_HID_5584] = 927,
+ [BNXT_ULP_CLASS_HID_2198] = 928,
+ [BNXT_ULP_CLASS_HID_7588] = 929,
+ [BNXT_ULP_CLASS_HID_419c] = 930,
+ [BNXT_ULP_CLASS_HID_7758] = 931,
+ [BNXT_ULP_CLASS_HID_43ac] = 932,
+ [BNXT_ULP_CLASS_HID_0c10] = 933,
+ [BNXT_ULP_CLASS_HID_1864] = 934,
+ [BNXT_ULP_CLASS_HID_30c8] = 935,
+ [BNXT_ULP_CLASS_HID_1cdc] = 936,
+ [BNXT_ULP_CLASS_HID_50cc] = 937,
+ [BNXT_ULP_CLASS_HID_3d20] = 938,
+ [BNXT_ULP_CLASS_HID_529c] = 939,
+ [BNXT_ULP_CLASS_HID_3ef0] = 940,
+ [BNXT_ULP_CLASS_HID_72e0] = 941,
+ [BNXT_ULP_CLASS_HID_5ef4] = 942,
+ [BNXT_ULP_CLASS_HID_2dfc] = 943,
+ [BNXT_ULP_CLASS_HID_39e0] = 944,
+ [BNXT_ULP_CLASS_HID_4530] = 945,
+ [BNXT_ULP_CLASS_HID_5124] = 946,
+ [BNXT_ULP_CLASS_HID_4df0] = 947,
+ [BNXT_ULP_CLASS_HID_59e4] = 948,
+ [BNXT_ULP_CLASS_HID_1c78] = 949,
+ [BNXT_ULP_CLASS_HID_7118] = 950,
+ [BNXT_ULP_CLASS_HID_0998] = 951,
+ [BNXT_ULP_CLASS_HID_158c] = 952,
+ [BNXT_ULP_CLASS_HID_20dc] = 953,
+ [BNXT_ULP_CLASS_HID_0cc0] = 954,
+ [BNXT_ULP_CLASS_HID_299c] = 955,
+ [BNXT_ULP_CLASS_HID_3580] = 956,
+ [BNXT_ULP_CLASS_HID_40d0] = 957,
+ [BNXT_ULP_CLASS_HID_2cc4] = 958,
+ [BNXT_ULP_CLASS_HID_55a4] = 959,
+ [BNXT_ULP_CLASS_HID_21b8] = 960,
+ [BNXT_ULP_CLASS_HID_75a8] = 961,
+ [BNXT_ULP_CLASS_HID_41bc] = 962,
+ [BNXT_ULP_CLASS_HID_7778] = 963,
+ [BNXT_ULP_CLASS_HID_438c] = 964,
+ [BNXT_ULP_CLASS_HID_0c30] = 965,
+ [BNXT_ULP_CLASS_HID_1844] = 966,
+ [BNXT_ULP_CLASS_HID_30e8] = 967,
+ [BNXT_ULP_CLASS_HID_1cfc] = 968,
+ [BNXT_ULP_CLASS_HID_50ec] = 969,
+ [BNXT_ULP_CLASS_HID_3d00] = 970,
+ [BNXT_ULP_CLASS_HID_52bc] = 971,
+ [BNXT_ULP_CLASS_HID_3ed0] = 972,
+ [BNXT_ULP_CLASS_HID_72c0] = 973,
+ [BNXT_ULP_CLASS_HID_5ed4] = 974,
+ [BNXT_ULP_CLASS_HID_3866] = 975,
+ [BNXT_ULP_CLASS_HID_381e] = 976,
+ [BNXT_ULP_CLASS_HID_3860] = 977,
+ [BNXT_ULP_CLASS_HID_0454] = 978,
+ [BNXT_ULP_CLASS_HID_3818] = 979,
+ [BNXT_ULP_CLASS_HID_042c] = 980,
+ [BNXT_ULP_CLASS_HID_3846] = 981,
+ [BNXT_ULP_CLASS_HID_387e] = 982,
+ [BNXT_ULP_CLASS_HID_3ba6] = 983,
+ [BNXT_ULP_CLASS_HID_385e] = 984,
+ [BNXT_ULP_CLASS_HID_3840] = 985,
+ [BNXT_ULP_CLASS_HID_0474] = 986,
+ [BNXT_ULP_CLASS_HID_3878] = 987,
+ [BNXT_ULP_CLASS_HID_044c] = 988,
+ [BNXT_ULP_CLASS_HID_3ba0] = 989,
+ [BNXT_ULP_CLASS_HID_0794] = 990,
+ [BNXT_ULP_CLASS_HID_3858] = 991,
+ [BNXT_ULP_CLASS_HID_046c] = 992
};
/* Array for the proto matcher list */
@@ -7165,7 +7309,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT }
},
[347] = {
- .class_hid = BNXT_ULP_CLASS_HID_6165,
+ .class_hid = BNXT_ULP_CLASS_HID_e082,
.class_tid = 2,
.hdr_sig_id = 1,
.flow_sig_id = 1313792,
@@ -7176,7 +7320,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7185,7 +7329,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC }
},
[348] = {
- .class_hid = BNXT_ULP_CLASS_HID_2aa1,
+ .class_hid = BNXT_ULP_CLASS_HID_ab46,
.class_tid = 2,
.hdr_sig_id = 1,
.flow_sig_id = 1321984,
@@ -7196,7 +7340,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7206,7 +7350,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC }
},
[349] = {
- .class_hid = BNXT_ULP_CLASS_HID_09cd,
+ .class_hid = BNXT_ULP_CLASS_HID_c82a,
.class_tid = 2,
.hdr_sig_id = 1,
.flow_sig_id = 3410944,
@@ -7217,7 +7361,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7227,7 +7371,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }
},
[350] = {
- .class_hid = BNXT_ULP_CLASS_HID_3845,
+ .class_hid = BNXT_ULP_CLASS_HID_f9a2,
.class_tid = 2,
.hdr_sig_id = 1,
.flow_sig_id = 3419136,
@@ -7238,7 +7382,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7249,10 +7393,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }
},
[351] = {
- .class_hid = BNXT_ULP_CLASS_HID_11e9,
+ .class_hid = BNXT_ULP_CLASS_HID_d8ce,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 2148797440,
+ .flow_sig_id = 538184704,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7260,20 +7404,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
},
[352] = {
- .class_hid = BNXT_ULP_CLASS_HID_4361,
+ .class_hid = BNXT_ULP_CLASS_HID_a2d2,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 2148805632,
+ .flow_sig_id = 538192896,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7281,7 +7425,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7289,13 +7433,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
},
[353] = {
- .class_hid = BNXT_ULP_CLASS_HID_218d,
+ .class_hid = BNXT_ULP_CLASS_HID_c076,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 2150894592,
+ .flow_sig_id = 540281856,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7303,7 +7447,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7311,13 +7455,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
},
[354] = {
- .class_hid = BNXT_ULP_CLASS_HID_5105,
+ .class_hid = BNXT_ULP_CLASS_HID_f1ee,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 2150902784,
+ .flow_sig_id = 540290048,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7325,7 +7469,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7334,13 +7478,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
},
[355] = {
- .class_hid = BNXT_ULP_CLASS_HID_0c89,
+ .class_hid = BNXT_ULP_CLASS_HID_a96e,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 4296281088,
+ .flow_sig_id = 1075055616,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7348,20 +7492,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[356] = {
- .class_hid = BNXT_ULP_CLASS_HID_3e81,
+ .class_hid = BNXT_ULP_CLASS_HID_dae6,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 4296289280,
+ .flow_sig_id = 1075063808,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7369,7 +7513,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7377,13 +7521,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[357] = {
- .class_hid = BNXT_ULP_CLASS_HID_1dad,
+ .class_hid = BNXT_ULP_CLASS_HID_c7aa,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 4298378240,
+ .flow_sig_id = 1077152768,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7391,7 +7535,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7399,13 +7543,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[358] = {
- .class_hid = BNXT_ULP_CLASS_HID_4ca5,
+ .class_hid = BNXT_ULP_CLASS_HID_c26e,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 4298386432,
+ .flow_sig_id = 1077160960,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7413,7 +7557,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7422,13 +7566,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[359] = {
- .class_hid = BNXT_ULP_CLASS_HID_25c9,
+ .class_hid = BNXT_ULP_CLASS_HID_a0fa,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 6443764736,
+ .flow_sig_id = 1611926528,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7436,21 +7580,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[360] = {
- .class_hid = BNXT_ULP_CLASS_HID_57c1,
+ .class_hid = BNXT_ULP_CLASS_HID_d272,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 6443772928,
+ .flow_sig_id = 1611934720,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7458,7 +7602,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7466,14 +7610,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[361] = {
- .class_hid = BNXT_ULP_CLASS_HID_33ed,
+ .class_hid = BNXT_ULP_CLASS_HID_fff6,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 6445861888,
+ .flow_sig_id = 1614023680,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7481,7 +7625,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7489,14 +7633,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[362] = {
- .class_hid = BNXT_ULP_CLASS_HID_65e5,
+ .class_hid = BNXT_ULP_CLASS_HID_e16e,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 6445870080,
+ .flow_sig_id = 1614031872,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7504,7 +7648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7513,11 +7657,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[363] = {
- .class_hid = BNXT_ULP_CLASS_HID_6dd9,
+ .class_hid = BNXT_ULP_CLASS_HID_e165,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 1313792,
@@ -7529,7 +7673,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7538,7 +7681,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }
},
[364] = {
- .class_hid = BNXT_ULP_CLASS_HID_261d,
+ .class_hid = BNXT_ULP_CLASS_HID_aaa1,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 1321984,
@@ -7550,7 +7693,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7560,7 +7702,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }
},
[365] = {
- .class_hid = BNXT_ULP_CLASS_HID_0571,
+ .class_hid = BNXT_ULP_CLASS_HID_c9cd,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 3410944,
@@ -7572,7 +7714,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7582,7 +7723,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
},
[366] = {
- .class_hid = BNXT_ULP_CLASS_HID_34f9,
+ .class_hid = BNXT_ULP_CLASS_HID_f845,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 3419136,
@@ -7594,7 +7735,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7605,7 +7745,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
},
[367] = {
- .class_hid = BNXT_ULP_CLASS_HID_1d55,
+ .class_hid = BNXT_ULP_CLASS_HID_90f9,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 2148797440,
@@ -7617,7 +7757,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7627,7 +7766,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
},
[368] = {
- .class_hid = BNXT_ULP_CLASS_HID_4fdd,
+ .class_hid = BNXT_ULP_CLASS_HID_c371,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 2148805632,
@@ -7639,7 +7778,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7650,7 +7788,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
},
[369] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d31,
+ .class_hid = BNXT_ULP_CLASS_HID_e19d,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 2150894592,
@@ -7662,7 +7800,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7673,7 +7810,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
},
[370] = {
- .class_hid = BNXT_ULP_CLASS_HID_5db9,
+ .class_hid = BNXT_ULP_CLASS_HID_d015,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 2150902784,
@@ -7685,7 +7822,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7697,7 +7833,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
},
[371] = {
- .class_hid = BNXT_ULP_CLASS_HID_0035,
+ .class_hid = BNXT_ULP_CLASS_HID_8c09,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 4296281088,
@@ -7709,7 +7845,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7719,7 +7854,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[372] = {
- .class_hid = BNXT_ULP_CLASS_HID_323d,
+ .class_hid = BNXT_ULP_CLASS_HID_be89,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 4296289280,
@@ -7731,7 +7866,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7742,7 +7876,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[373] = {
- .class_hid = BNXT_ULP_CLASS_HID_1111,
+ .class_hid = BNXT_ULP_CLASS_HID_ddad,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 4298378240,
@@ -7754,7 +7888,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7765,7 +7898,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[374] = {
- .class_hid = BNXT_ULP_CLASS_HID_4019,
+ .class_hid = BNXT_ULP_CLASS_HID_cc2d,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 4298386432,
@@ -7777,7 +7910,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7789,7 +7921,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[375] = {
- .class_hid = BNXT_ULP_CLASS_HID_2975,
+ .class_hid = BNXT_ULP_CLASS_HID_a4d9,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 6443764736,
@@ -7801,7 +7933,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7812,7 +7943,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[376] = {
- .class_hid = BNXT_ULP_CLASS_HID_5b7d,
+ .class_hid = BNXT_ULP_CLASS_HID_d759,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 6443772928,
@@ -7824,7 +7955,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7836,7 +7966,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[377] = {
- .class_hid = BNXT_ULP_CLASS_HID_3f51,
+ .class_hid = BNXT_ULP_CLASS_HID_f27d,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 6445861888,
@@ -7848,7 +7978,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7860,7 +7989,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[378] = {
- .class_hid = BNXT_ULP_CLASS_HID_6959,
+ .class_hid = BNXT_ULP_CLASS_HID_e4fd,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 6445870080,
@@ -7872,7 +8001,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7885,10 +8013,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[379] = {
- .class_hid = BNXT_ULP_CLASS_HID_0e85,
+ .class_hid = BNXT_ULP_CLASS_HID_ecf6,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 8591248384,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1313792,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7896,21 +8024,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
},
[380] = {
- .class_hid = BNXT_ULP_CLASS_HID_380d,
+ .class_hid = BNXT_ULP_CLASS_HID_a732,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 8591256576,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1321984,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7918,22 +8045,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
},
[381] = {
- .class_hid = BNXT_ULP_CLASS_HID_1f21,
+ .class_hid = BNXT_ULP_CLASS_HID_c45e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 8593345536,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3410944,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7941,22 +8067,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
},
[382] = {
- .class_hid = BNXT_ULP_CLASS_HID_4ea9,
+ .class_hid = BNXT_ULP_CLASS_HID_f5d6,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 8593353728,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3419136,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7964,23 +8089,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
},
[383] = {
- .class_hid = BNXT_ULP_CLASS_HID_1705,
+ .class_hid = BNXT_ULP_CLASS_HID_d4ba,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 10738732032,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 538184704,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7988,22 +8112,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[384] = {
- .class_hid = BNXT_ULP_CLASS_HID_418d,
+ .class_hid = BNXT_ULP_CLASS_HID_aea6,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 10738740224,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 538192896,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8011,23 +8134,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[385] = {
- .class_hid = BNXT_ULP_CLASS_HID_2721,
+ .class_hid = BNXT_ULP_CLASS_HID_cc02,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 10740829184,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 540281856,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8035,23 +8157,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[386] = {
- .class_hid = BNXT_ULP_CLASS_HID_57a9,
+ .class_hid = BNXT_ULP_CLASS_HID_fd9a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 10740837376,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 540290048,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8059,24 +8180,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[387] = {
- .class_hid = BNXT_ULP_CLASS_HID_1a25,
+ .class_hid = BNXT_ULP_CLASS_HID_a51a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 12886215680,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1075055616,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8084,22 +8204,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[388] = {
- .class_hid = BNXT_ULP_CLASS_HID_342d,
+ .class_hid = BNXT_ULP_CLASS_HID_d692,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 12886223872,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1075063808,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8107,23 +8226,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[389] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b01,
+ .class_hid = BNXT_ULP_CLASS_HID_cbde,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 12888312832,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1077152768,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8131,23 +8249,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[390] = {
- .class_hid = BNXT_ULP_CLASS_HID_5a09,
+ .class_hid = BNXT_ULP_CLASS_HID_ce1a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 12888321024,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1077160960,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8155,24 +8272,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[391] = {
- .class_hid = BNXT_ULP_CLASS_HID_2325,
+ .class_hid = BNXT_ULP_CLASS_HID_ac8e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 15033699328,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1611926528,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8180,23 +8296,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[392] = {
- .class_hid = BNXT_ULP_CLASS_HID_5d2d,
+ .class_hid = BNXT_ULP_CLASS_HID_de06,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 15033707520,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1611934720,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8204,24 +8319,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[393] = {
- .class_hid = BNXT_ULP_CLASS_HID_3101,
+ .class_hid = BNXT_ULP_CLASS_HID_f382,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 15035796480,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1614023680,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8229,24 +8343,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[394] = {
- .class_hid = BNXT_ULP_CLASS_HID_6309,
+ .class_hid = BNXT_ULP_CLASS_HID_ed1a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 15035804672,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1614031872,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8254,25 +8367,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[395] = {
- .class_hid = BNXT_ULP_CLASS_HID_0bad,
+ .class_hid = BNXT_ULP_CLASS_HID_9d6a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 17181182976,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2148797440,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8280,21 +8392,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[396] = {
- .class_hid = BNXT_ULP_CLASS_HID_2535,
+ .class_hid = BNXT_ULP_CLASS_HID_cee2,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 17181191168,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2148805632,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8302,22 +8414,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[397] = {
- .class_hid = BNXT_ULP_CLASS_HID_1869,
+ .class_hid = BNXT_ULP_CLASS_HID_ec0e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 17183280128,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2150894592,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8325,22 +8437,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[398] = {
- .class_hid = BNXT_ULP_CLASS_HID_4bf1,
+ .class_hid = BNXT_ULP_CLASS_HID_dd86,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 17183288320,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2150902784,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8348,23 +8460,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[399] = {
- .class_hid = BNXT_ULP_CLASS_HID_136d,
+ .class_hid = BNXT_ULP_CLASS_HID_852e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 19328666624,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2685668352,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8372,22 +8484,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[400] = {
- .class_hid = BNXT_ULP_CLASS_HID_43f5,
+ .class_hid = BNXT_ULP_CLASS_HID_b6a6,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 19328674816,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2685676544,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8395,23 +8507,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[401] = {
- .class_hid = BNXT_ULP_CLASS_HID_2129,
+ .class_hid = BNXT_ULP_CLASS_HID_eb82,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 19330763776,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2687765504,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8419,23 +8531,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[402] = {
- .class_hid = BNXT_ULP_CLASS_HID_53b1,
+ .class_hid = BNXT_ULP_CLASS_HID_c50a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 19330771968,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2687773696,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8443,24 +8555,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[403] = {
- .class_hid = BNXT_ULP_CLASS_HID_072d,
+ .class_hid = BNXT_ULP_CLASS_HID_ccca,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 21476150272,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3222539264,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8468,22 +8580,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[404] = {
- .class_hid = BNXT_ULP_CLASS_HID_3135,
+ .class_hid = BNXT_ULP_CLASS_HID_8706,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 21476158464,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3222547456,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8491,23 +8603,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[405] = {
- .class_hid = BNXT_ULP_CLASS_HID_1429,
+ .class_hid = BNXT_ULP_CLASS_HID_d38e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 21478247424,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3224636416,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8515,23 +8627,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[406] = {
- .class_hid = BNXT_ULP_CLASS_HID_4731,
+ .class_hid = BNXT_ULP_CLASS_HID_d5ca,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 21478255616,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3224644608,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8539,24 +8651,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[407] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f6d,
+ .class_hid = BNXT_ULP_CLASS_HID_b48e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 23623633920,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3759410176,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8564,23 +8676,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[408] = {
- .class_hid = BNXT_ULP_CLASS_HID_5f75,
+ .class_hid = BNXT_ULP_CLASS_HID_8e8a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 23623642112,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3759418368,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8588,24 +8700,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[409] = {
- .class_hid = BNXT_ULP_CLASS_HID_3d69,
+ .class_hid = BNXT_ULP_CLASS_HID_db02,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 23625731072,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3761507328,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8613,24 +8725,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[410] = {
- .class_hid = BNXT_ULP_CLASS_HID_6f71,
+ .class_hid = BNXT_ULP_CLASS_HID_dd8e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 23625739264,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3761515520,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8638,25 +8750,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
- },
- [411] = {
- .class_hid = BNXT_ULP_CLASS_HID_0dbd,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ },
+ [411] = {
+ .class_hid = BNXT_ULP_CLASS_HID_819a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 25771117568,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4296281088,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8664,22 +8776,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[412] = {
- .class_hid = BNXT_ULP_CLASS_HID_3f25,
+ .class_hid = BNXT_ULP_CLASS_HID_b31a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 25771125760,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4296289280,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8687,23 +8798,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[413] = {
- .class_hid = BNXT_ULP_CLASS_HID_1239,
+ .class_hid = BNXT_ULP_CLASS_HID_d03e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 25773214720,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4298378240,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8711,23 +8821,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[414] = {
- .class_hid = BNXT_ULP_CLASS_HID_4da1,
+ .class_hid = BNXT_ULP_CLASS_HID_c1be,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 25773222912,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4298386432,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8735,24 +8844,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[415] = {
- .class_hid = BNXT_ULP_CLASS_HID_153d,
+ .class_hid = BNXT_ULP_CLASS_HID_890e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 27918601216,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4833152000,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8760,23 +8868,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[416] = {
- .class_hid = BNXT_ULP_CLASS_HID_45a5,
+ .class_hid = BNXT_ULP_CLASS_HID_ba8e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 27918609408,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4833160192,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8784,24 +8891,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[417] = {
- .class_hid = BNXT_ULP_CLASS_HID_3bb9,
+ .class_hid = BNXT_ULP_CLASS_HID_dfaa,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 27920698368,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4835249152,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8809,24 +8915,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[418] = {
- .class_hid = BNXT_ULP_CLASS_HID_55a1,
+ .class_hid = BNXT_ULP_CLASS_HID_c93a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 27920706560,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4835257344,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8834,25 +8939,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[419] = {
- .class_hid = BNXT_ULP_CLASS_HID_193d,
+ .class_hid = BNXT_ULP_CLASS_HID_b11a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 30066084864,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5370022912,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8860,23 +8964,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[420] = {
- .class_hid = BNXT_ULP_CLASS_HID_4b25,
+ .class_hid = BNXT_ULP_CLASS_HID_8b4e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 30066093056,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5370031104,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8884,24 +8987,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[421] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e39,
+ .class_hid = BNXT_ULP_CLASS_HID_c79e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 30068182016,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5372120064,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8909,24 +9011,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[422] = {
- .class_hid = BNXT_ULP_CLASS_HID_5921,
+ .class_hid = BNXT_ULP_CLASS_HID_d9da,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 30068190208,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5372128256,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8934,25 +9035,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[423] = {
- .class_hid = BNXT_ULP_CLASS_HID_213d,
+ .class_hid = BNXT_ULP_CLASS_HID_b88e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 32213568512,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5906893824,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8960,24 +9060,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[424] = {
- .class_hid = BNXT_ULP_CLASS_HID_5125,
+ .class_hid = BNXT_ULP_CLASS_HID_ea0e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 32213576704,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5906902016,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8985,25 +9084,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[425] = {
- .class_hid = BNXT_ULP_CLASS_HID_3739,
+ .class_hid = BNXT_ULP_CLASS_HID_cf0a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 32215665664,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5908990976,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -9011,25 +9109,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[426] = {
- .class_hid = BNXT_ULP_CLASS_HID_093d,
+ .class_hid = BNXT_ULP_CLASS_HID_c18e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 32215673856,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5908999168,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -9037,25 +9134,3496 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [427] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a94a,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6443764736,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [428] = {
+ .class_hid = BNXT_ULP_CLASS_HID_daca,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6443772928,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [429] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ffee,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6445861888,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [430] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e96e,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6445870080,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [431] = {
+ .class_hid = BNXT_ULP_CLASS_HID_910e,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6980635648,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [432] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c28e,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6980643840,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [433] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e7aa,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6982732800,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [434] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d12a,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6982740992,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [435] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d8ca,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 7517506560,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [436] = {
+ .class_hid = BNXT_ULP_CLASS_HID_930e,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 7517514752,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [437] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ef4e,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 7519603712,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [438] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e18a,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 7519611904,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [439] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c08e,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8054377472,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [440] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9a8a,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8054385664,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [441] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d70a,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8056474624,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [442] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e90e,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8056482816,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [443] = {
+ .class_hid = BNXT_ULP_CLASS_HID_edd9,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1313792,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ },
+ [444] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a61d,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1321984,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ },
+ [445] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c571,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 3410944,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ },
+ [446] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f4f9,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 3419136,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ },
+ [447] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9c45,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2148797440,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [448] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cfcd,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2148805632,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [449] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ed21,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2150894592,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [450] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dca9,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2150902784,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [451] = {
+ .class_hid = BNXT_ULP_CLASS_HID_80b5,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4296281088,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [452] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b235,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4296289280,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [453] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d111,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4298378240,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [454] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c091,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4298386432,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [455] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a865,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6443764736,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [456] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dbe5,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6443772928,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [457] = {
+ .class_hid = BNXT_ULP_CLASS_HID_fec1,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6445861888,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [458] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e841,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6445870080,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [459] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8e85,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 8591248384,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [460] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b80d,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 8591256576,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [461] = {
+ .class_hid = BNXT_ULP_CLASS_HID_df65,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 8593345536,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [462] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ceed,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 8593353728,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [463] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9645,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 10738732032,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [464] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1cd,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 10738740224,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [465] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e725,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 10740829184,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [466] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d6ad,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 10740837376,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [467] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9aa5,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 12886215680,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [468] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b425,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 12886223872,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [469] = {
+ .class_hid = BNXT_ULP_CLASS_HID_eb05,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 12888312832,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [470] = {
+ .class_hid = BNXT_ULP_CLASS_HID_da85,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 12888321024,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [471] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a265,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 15033699328,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [472] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dde5,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 15033707520,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [473] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f0c5,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 15035796480,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [474] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e245,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 15035804672,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [475] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8b8f,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 17181182976,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [476] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a517,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 17181191168,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [477] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d86b,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 17183280128,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [478] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cbf3,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 17183288320,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [479] = {
+ .class_hid = BNXT_ULP_CLASS_HID_934f,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 19328666624,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [480] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c2c7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 19328674816,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [481] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e02b,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 19330763776,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [482] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d3a3,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 19330771968,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [483] = {
+ .class_hid = BNXT_ULP_CLASS_HID_87a7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 21476150272,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [484] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b137,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 21476158464,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [485] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d403,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 21478247424,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [486] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c793,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 21478255616,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [487] = {
+ .class_hid = BNXT_ULP_CLASS_HID_af67,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 23623633920,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [488] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dee7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 23623642112,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [489] = {
+ .class_hid = BNXT_ULP_CLASS_HID_fdc3,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 23625731072,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [490] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ef43,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 23625739264,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [491] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8dbf,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 25771117568,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [492] = {
+ .class_hid = BNXT_ULP_CLASS_HID_bf07,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 25771125760,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [493] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d21f,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 25773214720,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [494] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cde7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 25773222912,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [495] = {
+ .class_hid = BNXT_ULP_CLASS_HID_956f,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 27918601216,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [496] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c4c7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 27918609408,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [497] = {
+ .class_hid = BNXT_ULP_CLASS_HID_fbcf,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 27920698368,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [498] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d5a7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 27920706560,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [499] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9957,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 30066084864,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [500] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cb27,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 30066093056,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [501] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ee37,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 30068182016,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [502] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d987,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 30068190208,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [503] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a107,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 32213568512,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [504] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d0e7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 32213576704,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [505] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f7e7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 32215665664,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [506] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c827,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 32215673856,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [507] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f76a,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1313792,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC }
+ },
+ [508] = {
+ .class_hid = BNXT_ULP_CLASS_HID_bcae,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1321984,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC }
+ },
+ [509] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dfc2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3410944,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC }
+ },
+ [510] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ee4a,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3419136,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC }
+ },
+ [511] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cf26,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 538184704,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [512] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b53a,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 538192896,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [513] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d79e,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 540281856,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [514] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e606,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 540290048,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [515] = {
+ .class_hid = BNXT_ULP_CLASS_HID_be86,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1075055616,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [516] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cd0e,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1075063808,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [517] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d042,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1077152768,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [518] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d586,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1077160960,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [519] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b712,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1611926528,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [520] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c59a,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1611934720,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [521] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e81e,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1614023680,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [522] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f686,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1614031872,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [523] = {
+ .class_hid = BNXT_ULP_CLASS_HID_86f6,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2148797440,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [524] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d57e,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2148805632,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [525] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f792,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2150894592,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [526] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c61a,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2150902784,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [527] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9eb2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2685668352,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [528] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ad3a,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2685676544,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [529] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f01e,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2687765504,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [530] = {
+ .class_hid = BNXT_ULP_CLASS_HID_de96,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2687773696,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [531] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d756,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3222539264,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [532] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9c9a,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3222547456,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [533] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c812,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3224636416,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [534] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ce56,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3224644608,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [535] = {
+ .class_hid = BNXT_ULP_CLASS_HID_af12,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3759410176,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [536] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9516,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3759418368,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [537] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c09e,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3761507328,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [538] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c612,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3761515520,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [539] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9a06,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4296281088,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [540] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a886,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4296289280,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [541] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cba2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4298378240,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [542] = {
+ .class_hid = BNXT_ULP_CLASS_HID_da22,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4298386432,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [543] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9292,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4833152000,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [544] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a112,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4833160192,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [545] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c436,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4835249152,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [546] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d2a6,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4835257344,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [547] = {
+ .class_hid = BNXT_ULP_CLASS_HID_aa86,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5370022912,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [548] = {
+ .class_hid = BNXT_ULP_CLASS_HID_90d2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5370031104,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [549] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dc02,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5372120064,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [550] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c246,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5372128256,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [551] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a312,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5906893824,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [552] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f192,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5906902016,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [553] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d496,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5908990976,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [554] = {
+ .class_hid = BNXT_ULP_CLASS_HID_da12,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5908999168,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [555] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b2d6,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6443764736,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [556] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c156,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6443772928,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [557] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e472,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6445861888,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [558] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f2f2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6445870080,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [559] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8a92,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6980635648,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [560] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d912,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6980643840,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [561] = {
+ .class_hid = BNXT_ULP_CLASS_HID_fc36,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6982732800,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [562] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cab6,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6982740992,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [563] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c356,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 7517506560,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [564] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8892,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 7517514752,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [565] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f4d2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 7519603712,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [566] = {
+ .class_hid = BNXT_ULP_CLASS_HID_fa16,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 7519611904,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [567] = {
+ .class_hid = BNXT_ULP_CLASS_HID_db12,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 8054377472,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [568] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8116,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 8054385664,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [569] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cc96,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 8056474624,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [570] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f292,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 8056482816,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
},
- [427] = {
- .class_hid = BNXT_ULP_CLASS_HID_684d,
+ [571] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e84d,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 1313792,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9068,15 +12636,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC }
},
- [428] = {
- .class_hid = BNXT_ULP_CLASS_HID_2389,
+ [572] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a389,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 1321984,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9089,16 +12657,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC }
},
- [429] = {
- .class_hid = BNXT_ULP_CLASS_HID_00e5,
+ [573] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c0e5,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 3410944,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9111,16 +12679,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC }
},
- [430] = {
- .class_hid = BNXT_ULP_CLASS_HID_316d,
+ [574] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f16d,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 3419136,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9133,17 +12701,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC }
},
- [431] = {
- .class_hid = BNXT_ULP_CLASS_HID_18c1,
+ [575] = {
+ .class_hid = BNXT_ULP_CLASS_HID_99d1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 2148797440,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9156,16 +12724,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
},
- [432] = {
- .class_hid = BNXT_ULP_CLASS_HID_4a49,
+ [576] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ca59,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 2148805632,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9178,17 +12746,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
},
- [433] = {
- .class_hid = BNXT_ULP_CLASS_HID_28a5,
+ [577] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e8b5,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 2150894592,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9201,17 +12769,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
},
- [434] = {
- .class_hid = BNXT_ULP_CLASS_HID_582d,
+ [578] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d93d,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 2150902784,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9224,18 +12792,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
},
- [435] = {
- .class_hid = BNXT_ULP_CLASS_HID_05a1,
+ [579] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8521,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 4296281088,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9248,16 +12816,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [436] = {
- .class_hid = BNXT_ULP_CLASS_HID_37a9,
+ [580] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b7a1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 4296289280,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9270,17 +12838,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [437] = {
- .class_hid = BNXT_ULP_CLASS_HID_1485,
+ [581] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d485,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 4298378240,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9293,17 +12861,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [438] = {
- .class_hid = BNXT_ULP_CLASS_HID_458d,
+ [582] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c505,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 4298386432,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9316,18 +12884,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [439] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ce1,
+ [583] = {
+ .class_hid = BNXT_ULP_CLASS_HID_adf1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 6443764736,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9340,17 +12908,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [440] = {
- .class_hid = BNXT_ULP_CLASS_HID_5ee9,
+ [584] = {
+ .class_hid = BNXT_ULP_CLASS_HID_de71,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 6443772928,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9363,18 +12931,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [441] = {
- .class_hid = BNXT_ULP_CLASS_HID_3ac5,
+ [585] = {
+ .class_hid = BNXT_ULP_CLASS_HID_fb55,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 6445861888,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9387,18 +12955,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [442] = {
- .class_hid = BNXT_ULP_CLASS_HID_6ccd,
+ [586] = {
+ .class_hid = BNXT_ULP_CLASS_HID_edd5,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 6445870080,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9411,19 +12979,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [443] = {
- .class_hid = BNXT_ULP_CLASS_HID_0b11,
+ [587] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8b11,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 8591248384,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9436,16 +13004,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [444] = {
- .class_hid = BNXT_ULP_CLASS_HID_3d99,
+ [588] = {
+ .class_hid = BNXT_ULP_CLASS_HID_bd99,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 8591256576,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9458,17 +13026,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [445] = {
- .class_hid = BNXT_ULP_CLASS_HID_1ab5,
+ [589] = {
+ .class_hid = BNXT_ULP_CLASS_HID_daf1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 8593345536,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9481,17 +13049,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [446] = {
- .class_hid = BNXT_ULP_CLASS_HID_4b3d,
+ [590] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cb79,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 8593353728,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9504,18 +13072,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [447] = {
- .class_hid = BNXT_ULP_CLASS_HID_1291,
+ [591] = {
+ .class_hid = BNXT_ULP_CLASS_HID_93d1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 10738732032,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9528,17 +13096,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [448] = {
- .class_hid = BNXT_ULP_CLASS_HID_4419,
+ [592] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c459,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 10738740224,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9551,18 +13119,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [449] = {
- .class_hid = BNXT_ULP_CLASS_HID_22b5,
+ [593] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e2b1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 10740829184,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9575,18 +13143,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [450] = {
- .class_hid = BNXT_ULP_CLASS_HID_523d,
+ [594] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d339,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 10740837376,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9599,19 +13167,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [451] = {
- .class_hid = BNXT_ULP_CLASS_HID_1fb1,
+ [595] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9f31,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 12886215680,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9624,17 +13192,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [452] = {
- .class_hid = BNXT_ULP_CLASS_HID_31b9,
+ [596] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b1b1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 12886223872,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9647,18 +13215,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [453] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e95,
+ [597] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ee91,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 12888312832,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9671,18 +13239,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [454] = {
- .class_hid = BNXT_ULP_CLASS_HID_5f9d,
+ [598] = {
+ .class_hid = BNXT_ULP_CLASS_HID_df11,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 12888321024,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9695,19 +13263,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [455] = {
- .class_hid = BNXT_ULP_CLASS_HID_26b1,
+ [599] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a7f1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 15033699328,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9720,18 +13288,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [456] = {
- .class_hid = BNXT_ULP_CLASS_HID_58b9,
+ [600] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d871,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 15033707520,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9744,19 +13312,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [457] = {
- .class_hid = BNXT_ULP_CLASS_HID_3495,
+ [601] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f551,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 15035796480,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9769,19 +13337,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [458] = {
- .class_hid = BNXT_ULP_CLASS_HID_669d,
+ [602] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e7d1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 15035804672,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9794,20 +13362,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [459] = {
- .class_hid = BNXT_ULP_CLASS_HID_0e39,
+ [603] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8e1b,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 17181182976,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9820,16 +13388,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [460] = {
- .class_hid = BNXT_ULP_CLASS_HID_20a1,
+ [604] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a083,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 17181191168,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9842,17 +13410,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [461] = {
- .class_hid = BNXT_ULP_CLASS_HID_1dfd,
+ [605] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ddff,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 17183280128,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9865,17 +13433,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [462] = {
- .class_hid = BNXT_ULP_CLASS_HID_4e65,
+ [606] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ce67,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 17183288320,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9888,18 +13456,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [463] = {
- .class_hid = BNXT_ULP_CLASS_HID_16f9,
+ [607] = {
+ .class_hid = BNXT_ULP_CLASS_HID_96db,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 19328666624,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9912,17 +13480,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [464] = {
- .class_hid = BNXT_ULP_CLASS_HID_4661,
+ [608] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c753,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 19328674816,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9935,18 +13503,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [465] = {
- .class_hid = BNXT_ULP_CLASS_HID_24bd,
+ [609] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e5bf,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 19330763776,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9959,18 +13527,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [466] = {
- .class_hid = BNXT_ULP_CLASS_HID_5625,
+ [610] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d637,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 19330771968,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9983,19 +13551,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [467] = {
- .class_hid = BNXT_ULP_CLASS_HID_02b9,
+ [611] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8233,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 21476150272,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10008,17 +13576,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [468] = {
- .class_hid = BNXT_ULP_CLASS_HID_34a1,
+ [612] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b4a3,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 21476158464,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10031,18 +13599,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [469] = {
- .class_hid = BNXT_ULP_CLASS_HID_11bd,
+ [613] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d197,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 21478247424,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10055,18 +13623,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [470] = {
- .class_hid = BNXT_ULP_CLASS_HID_42a5,
+ [614] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c207,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 21478255616,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10079,19 +13647,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [471] = {
- .class_hid = BNXT_ULP_CLASS_HID_2af9,
+ [615] = {
+ .class_hid = BNXT_ULP_CLASS_HID_aaf3,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 23623633920,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10104,18 +13672,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [472] = {
- .class_hid = BNXT_ULP_CLASS_HID_5ae1,
+ [616] = {
+ .class_hid = BNXT_ULP_CLASS_HID_db73,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 23623642112,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10128,19 +13696,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [473] = {
- .class_hid = BNXT_ULP_CLASS_HID_38fd,
+ [617] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f857,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 23625731072,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10153,19 +13721,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [474] = {
- .class_hid = BNXT_ULP_CLASS_HID_6ae5,
+ [618] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ead7,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 23625739264,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10178,20 +13746,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [475] = {
- .class_hid = BNXT_ULP_CLASS_HID_0829,
+ [619] = {
+ .class_hid = BNXT_ULP_CLASS_HID_882b,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 25771117568,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10204,17 +13772,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [476] = {
- .class_hid = BNXT_ULP_CLASS_HID_3ab1,
+ [620] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ba93,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 25771125760,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10227,18 +13795,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [477] = {
- .class_hid = BNXT_ULP_CLASS_HID_17ad,
+ [621] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d78b,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 25773214720,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10251,18 +13819,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [478] = {
- .class_hid = BNXT_ULP_CLASS_HID_4835,
+ [622] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c873,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 25773222912,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10275,19 +13843,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [479] = {
- .class_hid = BNXT_ULP_CLASS_HID_10a9,
+ [623] = {
+ .class_hid = BNXT_ULP_CLASS_HID_90fb,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 27918601216,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10300,18 +13868,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [480] = {
- .class_hid = BNXT_ULP_CLASS_HID_4031,
+ [624] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c153,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 27918609408,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10324,19 +13892,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [481] = {
- .class_hid = BNXT_ULP_CLASS_HID_3e2d,
+ [625] = {
+ .class_hid = BNXT_ULP_CLASS_HID_fe5b,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 27920698368,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10349,19 +13917,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [482] = {
- .class_hid = BNXT_ULP_CLASS_HID_5035,
+ [626] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d033,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 27920706560,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10374,20 +13942,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [483] = {
- .class_hid = BNXT_ULP_CLASS_HID_1ca9,
+ [627] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9cc3,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 30066084864,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10400,18 +13968,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [484] = {
- .class_hid = BNXT_ULP_CLASS_HID_4eb1,
+ [628] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ceb3,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 30066093056,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10424,19 +13992,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [485] = {
- .class_hid = BNXT_ULP_CLASS_HID_2bad,
+ [629] = {
+ .class_hid = BNXT_ULP_CLASS_HID_eba3,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 30068182016,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10449,19 +14017,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [486] = {
- .class_hid = BNXT_ULP_CLASS_HID_5cb5,
+ [630] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dc13,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 30068190208,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10474,20 +14042,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [487] = {
- .class_hid = BNXT_ULP_CLASS_HID_24a9,
+ [631] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a493,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 32213568512,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10500,19 +14068,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [488] = {
- .class_hid = BNXT_ULP_CLASS_HID_54b1,
+ [632] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d573,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 32213576704,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10525,20 +14093,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [489] = {
- .class_hid = BNXT_ULP_CLASS_HID_32ad,
+ [633] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f273,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 32215665664,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10551,20 +14119,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [490] = {
- .class_hid = BNXT_ULP_CLASS_HID_0ca9,
+ [634] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cdb3,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 32215673856,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10577,21 +14145,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [491] = {
- .class_hid = BNXT_ULP_CLASS_HID_7f35,
+ [635] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ff35,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 1313792,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10604,15 +14172,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC }
},
- [492] = {
- .class_hid = BNXT_ULP_CLASS_HID_34f1,
+ [636] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b4f1,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 1321984,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10625,16 +14193,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC }
},
- [493] = {
- .class_hid = BNXT_ULP_CLASS_HID_179d,
+ [637] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d79d,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 3410944,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10647,16 +14215,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC }
},
- [494] = {
- .class_hid = BNXT_ULP_CLASS_HID_2615,
+ [638] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e615,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 3419136,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10669,17 +14237,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC }
},
- [495] = {
- .class_hid = BNXT_ULP_CLASS_HID_0fb9,
+ [639] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8ea9,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 2148797440,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10692,16 +14260,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
},
- [496] = {
- .class_hid = BNXT_ULP_CLASS_HID_5d31,
+ [640] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dd21,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 2148805632,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10714,17 +14282,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
},
- [497] = {
- .class_hid = BNXT_ULP_CLASS_HID_3fdd,
+ [641] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ffcd,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 2150894592,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10737,17 +14305,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
},
- [498] = {
- .class_hid = BNXT_ULP_CLASS_HID_4f55,
+ [642] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ce45,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 2150902784,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10760,18 +14328,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
},
- [499] = {
- .class_hid = BNXT_ULP_CLASS_HID_12d9,
+ [643] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9259,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 4296281088,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10784,16 +14352,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [500] = {
- .class_hid = BNXT_ULP_CLASS_HID_20d1,
+ [644] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a0d9,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 4296289280,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10806,17 +14374,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [501] = {
- .class_hid = BNXT_ULP_CLASS_HID_03fd,
+ [645] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c3fd,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 4298378240,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10829,17 +14397,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [502] = {
- .class_hid = BNXT_ULP_CLASS_HID_52f5,
+ [646] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d27d,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 4298386432,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10852,18 +14420,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [503] = {
- .class_hid = BNXT_ULP_CLASS_HID_3b99,
+ [647] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ba89,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 6443764736,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10876,17 +14444,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [504] = {
- .class_hid = BNXT_ULP_CLASS_HID_4991,
+ [648] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c909,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 6443772928,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10899,18 +14467,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [505] = {
- .class_hid = BNXT_ULP_CLASS_HID_2dbd,
+ [649] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ec2d,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 6445861888,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10923,18 +14491,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [506] = {
- .class_hid = BNXT_ULP_CLASS_HID_7bb5,
+ [650] = {
+ .class_hid = BNXT_ULP_CLASS_HID_faad,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 6445870080,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10947,16 +14515,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [507] = {
+ [651] = {
.class_hid = BNXT_ULP_CLASS_HID_34c6,
.class_tid = 3,
.hdr_sig_id = 0,
@@ -10971,7 +14539,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [508] = {
+ [652] = {
.class_hid = BNXT_ULP_CLASS_HID_0c22,
.class_tid = 3,
.hdr_sig_id = 0,
@@ -10987,7 +14555,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [509] = {
+ [653] = {
.class_hid = BNXT_ULP_CLASS_HID_1cbe,
.class_tid = 3,
.hdr_sig_id = 0,
@@ -11003,7 +14571,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [510] = {
+ [654] = {
.class_hid = BNXT_ULP_CLASS_HID_179a,
.class_tid = 3,
.hdr_sig_id = 0,
@@ -11020,7 +14588,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [511] = {
+ [655] = {
.class_hid = BNXT_ULP_CLASS_HID_59be,
.class_tid = 3,
.hdr_sig_id = 1,
@@ -11035,7 +14603,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [512] = {
+ [656] = {
.class_hid = BNXT_ULP_CLASS_HID_515a,
.class_tid = 3,
.hdr_sig_id = 1,
@@ -11051,7 +14619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [513] = {
+ [657] = {
.class_hid = BNXT_ULP_CLASS_HID_1c72,
.class_tid = 3,
.hdr_sig_id = 1,
@@ -11067,7 +14635,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [514] = {
+ [658] = {
.class_hid = BNXT_ULP_CLASS_HID_171e,
.class_tid = 3,
.hdr_sig_id = 1,
@@ -11084,7 +14652,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [515] = {
+ [659] = {
.class_hid = BNXT_ULP_CLASS_HID_19c8,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11100,7 +14668,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [516] = {
+ [660] = {
.class_hid = BNXT_ULP_CLASS_HID_112c,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11117,7 +14685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [517] = {
+ [661] = {
.class_hid = BNXT_ULP_CLASS_HID_4d68,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11134,7 +14702,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [518] = {
+ [662] = {
.class_hid = BNXT_ULP_CLASS_HID_444c,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11152,7 +14720,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [519] = {
+ [663] = {
.class_hid = BNXT_ULP_CLASS_HID_0e8c,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11169,7 +14737,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [520] = {
+ [664] = {
.class_hid = BNXT_ULP_CLASS_HID_09e0,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11187,7 +14755,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [521] = {
+ [665] = {
.class_hid = BNXT_ULP_CLASS_HID_1af0,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11205,7 +14773,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [522] = {
+ [666] = {
.class_hid = BNXT_ULP_CLASS_HID_15d4,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11224,7 +14792,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [523] = {
+ [667] = {
.class_hid = BNXT_ULP_CLASS_HID_1dd0,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11240,7 +14808,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [524] = {
+ [668] = {
.class_hid = BNXT_ULP_CLASS_HID_14f4,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11257,7 +14825,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [525] = {
+ [669] = {
.class_hid = BNXT_ULP_CLASS_HID_70b0,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11274,7 +14842,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [526] = {
+ [670] = {
.class_hid = BNXT_ULP_CLASS_HID_4854,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11292,7 +14860,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [527] = {
+ [671] = {
.class_hid = BNXT_ULP_CLASS_HID_3dd4,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11309,7 +14877,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [528] = {
+ [672] = {
.class_hid = BNXT_ULP_CLASS_HID_34f8,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11327,7 +14895,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [529] = {
+ [673] = {
.class_hid = BNXT_ULP_CLASS_HID_09e8,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11345,7 +14913,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [530] = {
+ [674] = {
.class_hid = BNXT_ULP_CLASS_HID_008c,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11364,7 +14932,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [531] = {
+ [675] = {
.class_hid = BNXT_ULP_CLASS_HID_34e6,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11380,7 +14948,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [532] = {
+ [676] = {
.class_hid = BNXT_ULP_CLASS_HID_0c02,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11397,7 +14965,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [533] = {
+ [677] = {
.class_hid = BNXT_ULP_CLASS_HID_1c9e,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11414,7 +14982,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [534] = {
+ [678] = {
.class_hid = BNXT_ULP_CLASS_HID_17ba,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11432,7 +15000,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [535] = {
+ [679] = {
.class_hid = BNXT_ULP_CLASS_HID_429e,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11449,7 +15017,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [536] = {
+ [680] = {
.class_hid = BNXT_ULP_CLASS_HID_5dba,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11467,7 +15035,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [537] = {
+ [681] = {
.class_hid = BNXT_ULP_CLASS_HID_2a16,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11485,7 +15053,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [538] = {
+ [682] = {
.class_hid = BNXT_ULP_CLASS_HID_2532,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11504,7 +15072,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [539] = {
+ [683] = {
.class_hid = BNXT_ULP_CLASS_HID_2da2,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11521,7 +15089,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [540] = {
+ [684] = {
.class_hid = BNXT_ULP_CLASS_HID_24fe,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11539,7 +15107,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [541] = {
+ [685] = {
.class_hid = BNXT_ULP_CLASS_HID_355a,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11557,7 +15125,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [542] = {
+ [686] = {
.class_hid = BNXT_ULP_CLASS_HID_0c76,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11576,7 +15144,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [543] = {
+ [687] = {
.class_hid = BNXT_ULP_CLASS_HID_13e6,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11594,7 +15162,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [544] = {
+ [688] = {
.class_hid = BNXT_ULP_CLASS_HID_7276,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11613,7 +15181,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [545] = {
+ [689] = {
.class_hid = BNXT_ULP_CLASS_HID_42d2,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11632,7 +15200,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [546] = {
+ [690] = {
.class_hid = BNXT_ULP_CLASS_HID_5dee,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11652,7 +15220,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [547] = {
+ [691] = {
.class_hid = BNXT_ULP_CLASS_HID_59de,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11668,7 +15236,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [548] = {
+ [692] = {
.class_hid = BNXT_ULP_CLASS_HID_513a,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11685,7 +15253,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [549] = {
+ [693] = {
.class_hid = BNXT_ULP_CLASS_HID_1c12,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11702,7 +15270,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [550] = {
+ [694] = {
.class_hid = BNXT_ULP_CLASS_HID_177e,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11720,7 +15288,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [551] = {
+ [695] = {
.class_hid = BNXT_ULP_CLASS_HID_0e92,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11737,7 +15305,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [552] = {
+ [696] = {
.class_hid = BNXT_ULP_CLASS_HID_09fe,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11755,7 +15323,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [553] = {
+ [697] = {
.class_hid = BNXT_ULP_CLASS_HID_5c1a,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11773,7 +15341,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [554] = {
+ [698] = {
.class_hid = BNXT_ULP_CLASS_HID_5746,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11792,7 +15360,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [555] = {
+ [699] = {
.class_hid = BNXT_ULP_CLASS_HID_79da,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11809,7 +15377,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [556] = {
+ [700] = {
.class_hid = BNXT_ULP_CLASS_HID_7106,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11827,7 +15395,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [557] = {
+ [701] = {
.class_hid = BNXT_ULP_CLASS_HID_3c1e,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11845,7 +15413,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [558] = {
+ [702] = {
.class_hid = BNXT_ULP_CLASS_HID_377a,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11864,7 +15432,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [559] = {
+ [703] = {
.class_hid = BNXT_ULP_CLASS_HID_2e9e,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11882,7 +15450,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [560] = {
+ [704] = {
.class_hid = BNXT_ULP_CLASS_HID_29fa,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11901,7 +15469,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [561] = {
+ [705] = {
.class_hid = BNXT_ULP_CLASS_HID_14d2,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11920,7 +15488,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [562] = {
+ [706] = {
.class_hid = BNXT_ULP_CLASS_HID_7742,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11940,7 +15508,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [563] = {
+ [707] = {
.class_hid = BNXT_ULP_CLASS_HID_3706,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -11956,7 +15524,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [564] = {
+ [708] = {
.class_hid = BNXT_ULP_CLASS_HID_0fe2,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -11973,7 +15541,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [565] = {
+ [709] = {
.class_hid = BNXT_ULP_CLASS_HID_1f7e,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -11990,7 +15558,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [566] = {
+ [710] = {
.class_hid = BNXT_ULP_CLASS_HID_145a,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12008,7 +15576,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [567] = {
+ [711] = {
.class_hid = BNXT_ULP_CLASS_HID_417e,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12025,7 +15593,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [568] = {
+ [712] = {
.class_hid = BNXT_ULP_CLASS_HID_5e5a,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12043,7 +15611,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [569] = {
+ [713] = {
.class_hid = BNXT_ULP_CLASS_HID_29f6,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12061,7 +15629,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [570] = {
+ [714] = {
.class_hid = BNXT_ULP_CLASS_HID_26d2,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12080,7 +15648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [571] = {
+ [715] = {
.class_hid = BNXT_ULP_CLASS_HID_2e42,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12097,7 +15665,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [572] = {
+ [716] = {
.class_hid = BNXT_ULP_CLASS_HID_271e,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12115,7 +15683,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [573] = {
+ [717] = {
.class_hid = BNXT_ULP_CLASS_HID_36ba,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12133,7 +15701,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [574] = {
+ [718] = {
.class_hid = BNXT_ULP_CLASS_HID_0f96,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12152,7 +15720,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [575] = {
+ [719] = {
.class_hid = BNXT_ULP_CLASS_HID_1006,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12170,7 +15738,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [576] = {
+ [720] = {
.class_hid = BNXT_ULP_CLASS_HID_7196,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12189,7 +15757,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [577] = {
+ [721] = {
.class_hid = BNXT_ULP_CLASS_HID_4132,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12208,7 +15776,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [578] = {
+ [722] = {
.class_hid = BNXT_ULP_CLASS_HID_5e0e,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12228,7 +15796,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [579] = {
+ [723] = {
.class_hid = BNXT_ULP_CLASS_HID_59fe,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12244,7 +15812,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [580] = {
+ [724] = {
.class_hid = BNXT_ULP_CLASS_HID_511a,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12261,7 +15829,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [581] = {
+ [725] = {
.class_hid = BNXT_ULP_CLASS_HID_1c32,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12278,7 +15846,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [582] = {
+ [726] = {
.class_hid = BNXT_ULP_CLASS_HID_175e,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12296,7 +15864,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [583] = {
+ [727] = {
.class_hid = BNXT_ULP_CLASS_HID_0eb2,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12313,7 +15881,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [584] = {
+ [728] = {
.class_hid = BNXT_ULP_CLASS_HID_09de,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12331,7 +15899,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [585] = {
+ [729] = {
.class_hid = BNXT_ULP_CLASS_HID_5c3a,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12349,7 +15917,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [586] = {
+ [730] = {
.class_hid = BNXT_ULP_CLASS_HID_5766,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12368,7 +15936,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [587] = {
+ [731] = {
.class_hid = BNXT_ULP_CLASS_HID_79fa,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12385,7 +15953,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [588] = {
+ [732] = {
.class_hid = BNXT_ULP_CLASS_HID_7126,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12403,7 +15971,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [589] = {
+ [733] = {
.class_hid = BNXT_ULP_CLASS_HID_3c3e,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12421,7 +15989,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [590] = {
+ [734] = {
.class_hid = BNXT_ULP_CLASS_HID_375a,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12440,7 +16008,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [591] = {
+ [735] = {
.class_hid = BNXT_ULP_CLASS_HID_2ebe,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12458,7 +16026,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [592] = {
+ [736] = {
.class_hid = BNXT_ULP_CLASS_HID_29da,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12477,7 +16045,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [593] = {
+ [737] = {
.class_hid = BNXT_ULP_CLASS_HID_14f2,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12496,7 +16064,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [594] = {
+ [738] = {
.class_hid = BNXT_ULP_CLASS_HID_7762,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12516,7 +16084,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [595] = {
+ [739] = {
.class_hid = BNXT_ULP_CLASS_HID_19e8,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12533,7 +16101,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [596] = {
+ [740] = {
.class_hid = BNXT_ULP_CLASS_HID_110c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12551,7 +16119,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [597] = {
+ [741] = {
.class_hid = BNXT_ULP_CLASS_HID_4d48,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12569,7 +16137,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [598] = {
+ [742] = {
.class_hid = BNXT_ULP_CLASS_HID_446c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12588,7 +16156,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [599] = {
+ [743] = {
.class_hid = BNXT_ULP_CLASS_HID_0eac,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12606,7 +16174,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [600] = {
+ [744] = {
.class_hid = BNXT_ULP_CLASS_HID_09c0,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12625,7 +16193,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [601] = {
+ [745] = {
.class_hid = BNXT_ULP_CLASS_HID_1ad0,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12644,7 +16212,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [602] = {
+ [746] = {
.class_hid = BNXT_ULP_CLASS_HID_15f4,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12664,7 +16232,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [603] = {
+ [747] = {
.class_hid = BNXT_ULP_CLASS_HID_39ec,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12682,7 +16250,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [604] = {
+ [748] = {
.class_hid = BNXT_ULP_CLASS_HID_3100,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12701,7 +16269,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [605] = {
+ [749] = {
.class_hid = BNXT_ULP_CLASS_HID_0210,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12720,7 +16288,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [606] = {
+ [750] = {
.class_hid = BNXT_ULP_CLASS_HID_1d34,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12740,7 +16308,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [607] = {
+ [751] = {
.class_hid = BNXT_ULP_CLASS_HID_2ea0,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12759,7 +16327,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [608] = {
+ [752] = {
.class_hid = BNXT_ULP_CLASS_HID_29c4,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12779,7 +16347,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [609] = {
+ [753] = {
.class_hid = BNXT_ULP_CLASS_HID_3ad4,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12799,7 +16367,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [610] = {
+ [754] = {
.class_hid = BNXT_ULP_CLASS_HID_35e8,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12820,7 +16388,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [611] = {
+ [755] = {
.class_hid = BNXT_ULP_CLASS_HID_5d80,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12838,7 +16406,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [612] = {
+ [756] = {
.class_hid = BNXT_ULP_CLASS_HID_54a4,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12857,7 +16425,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [613] = {
+ [757] = {
.class_hid = BNXT_ULP_CLASS_HID_29b4,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12876,7 +16444,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [614] = {
+ [758] = {
.class_hid = BNXT_ULP_CLASS_HID_20c8,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12896,7 +16464,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [615] = {
+ [759] = {
.class_hid = BNXT_ULP_CLASS_HID_7244,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12915,7 +16483,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [616] = {
+ [760] = {
.class_hid = BNXT_ULP_CLASS_HID_4d98,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12935,7 +16503,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [617] = {
+ [761] = {
.class_hid = BNXT_ULP_CLASS_HID_5e68,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12955,7 +16523,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [618] = {
+ [762] = {
.class_hid = BNXT_ULP_CLASS_HID_598c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12976,7 +16544,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [619] = {
+ [763] = {
.class_hid = BNXT_ULP_CLASS_HID_1248,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12995,7 +16563,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [620] = {
+ [764] = {
.class_hid = BNXT_ULP_CLASS_HID_74d8,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -13015,7 +16583,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [621] = {
+ [765] = {
.class_hid = BNXT_ULP_CLASS_HID_49a8,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -13035,7 +16603,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [622] = {
+ [766] = {
.class_hid = BNXT_ULP_CLASS_HID_40cc,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -13056,7 +16624,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [623] = {
+ [767] = {
.class_hid = BNXT_ULP_CLASS_HID_0b0c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -13076,7 +16644,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [624] = {
+ [768] = {
.class_hid = BNXT_ULP_CLASS_HID_0220,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -13097,7 +16665,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [625] = {
+ [769] = {
.class_hid = BNXT_ULP_CLASS_HID_1730,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -13118,7 +16686,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [626] = {
+ [770] = {
.class_hid = BNXT_ULP_CLASS_HID_7980,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -13140,7 +16708,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [627] = {
+ [771] = {
.class_hid = BNXT_ULP_CLASS_HID_1db0,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13157,7 +16725,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [628] = {
+ [772] = {
.class_hid = BNXT_ULP_CLASS_HID_1494,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13175,7 +16743,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [629] = {
+ [773] = {
.class_hid = BNXT_ULP_CLASS_HID_70d0,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13193,7 +16761,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [630] = {
+ [774] = {
.class_hid = BNXT_ULP_CLASS_HID_4834,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13212,7 +16780,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [631] = {
+ [775] = {
.class_hid = BNXT_ULP_CLASS_HID_3db4,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13230,7 +16798,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [632] = {
+ [776] = {
.class_hid = BNXT_ULP_CLASS_HID_3498,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13249,7 +16817,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [633] = {
+ [777] = {
.class_hid = BNXT_ULP_CLASS_HID_0988,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13268,7 +16836,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [634] = {
+ [778] = {
.class_hid = BNXT_ULP_CLASS_HID_00ec,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13288,7 +16856,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [635] = {
+ [779] = {
.class_hid = BNXT_ULP_CLASS_HID_3f44,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13306,7 +16874,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [636] = {
+ [780] = {
.class_hid = BNXT_ULP_CLASS_HID_36a8,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13325,7 +16893,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [637] = {
+ [781] = {
.class_hid = BNXT_ULP_CLASS_HID_0b58,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13344,7 +16912,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [638] = {
+ [782] = {
.class_hid = BNXT_ULP_CLASS_HID_02bc,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13364,7 +16932,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [639] = {
+ [783] = {
.class_hid = BNXT_ULP_CLASS_HID_5f48,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13383,7 +16951,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [640] = {
+ [784] = {
.class_hid = BNXT_ULP_CLASS_HID_56ac,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13403,7 +16971,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [641] = {
+ [785] = {
.class_hid = BNXT_ULP_CLASS_HID_2b5c,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13423,7 +16991,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [642] = {
+ [786] = {
.class_hid = BNXT_ULP_CLASS_HID_2280,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13444,7 +17012,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [643] = {
+ [787] = {
.class_hid = BNXT_ULP_CLASS_HID_4000,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13462,7 +17030,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [644] = {
+ [788] = {
.class_hid = BNXT_ULP_CLASS_HID_5b64,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13481,7 +17049,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [645] = {
+ [789] = {
.class_hid = BNXT_ULP_CLASS_HID_2c14,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13500,7 +17068,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [646] = {
+ [790] = {
.class_hid = BNXT_ULP_CLASS_HID_2778,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13520,7 +17088,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [647] = {
+ [791] = {
.class_hid = BNXT_ULP_CLASS_HID_18f8,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13539,7 +17107,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [648] = {
+ [792] = {
.class_hid = BNXT_ULP_CLASS_HID_13dc,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13559,7 +17127,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [649] = {
+ [793] = {
.class_hid = BNXT_ULP_CLASS_HID_4c18,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13579,7 +17147,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [650] = {
+ [794] = {
.class_hid = BNXT_ULP_CLASS_HID_477c,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13600,7 +17168,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [651] = {
+ [795] = {
.class_hid = BNXT_ULP_CLASS_HID_1a88,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13619,7 +17187,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [652] = {
+ [796] = {
.class_hid = BNXT_ULP_CLASS_HID_15ec,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13639,7 +17207,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [653] = {
+ [797] = {
.class_hid = BNXT_ULP_CLASS_HID_4e28,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13659,7 +17227,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [654] = {
+ [798] = {
.class_hid = BNXT_ULP_CLASS_HID_490c,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13680,7 +17248,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [655] = {
+ [799] = {
.class_hid = BNXT_ULP_CLASS_HID_3a8c,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13700,7 +17268,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [656] = {
+ [800] = {
.class_hid = BNXT_ULP_CLASS_HID_35f0,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13721,7 +17289,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [657] = {
+ [801] = {
.class_hid = BNXT_ULP_CLASS_HID_06e0,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13742,7 +17310,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [658] = {
+ [802] = {
.class_hid = BNXT_ULP_CLASS_HID_01c4,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13764,7 +17332,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [659] = {
+ [803] = {
.class_hid = BNXT_ULP_CLASS_HID_1a08,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13781,7 +17349,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [660] = {
+ [804] = {
.class_hid = BNXT_ULP_CLASS_HID_12ec,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13799,7 +17367,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [661] = {
+ [805] = {
.class_hid = BNXT_ULP_CLASS_HID_4ea8,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13817,7 +17385,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [662] = {
+ [806] = {
.class_hid = BNXT_ULP_CLASS_HID_478c,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13836,7 +17404,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [663] = {
+ [807] = {
.class_hid = BNXT_ULP_CLASS_HID_0d4c,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13854,7 +17422,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [664] = {
+ [808] = {
.class_hid = BNXT_ULP_CLASS_HID_0a20,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13873,7 +17441,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [665] = {
+ [809] = {
.class_hid = BNXT_ULP_CLASS_HID_1930,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13892,7 +17460,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [666] = {
+ [810] = {
.class_hid = BNXT_ULP_CLASS_HID_1614,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13912,7 +17480,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [667] = {
+ [811] = {
.class_hid = BNXT_ULP_CLASS_HID_3a0c,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13930,7 +17498,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [668] = {
+ [812] = {
.class_hid = BNXT_ULP_CLASS_HID_32e0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13949,7 +17517,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [669] = {
+ [813] = {
.class_hid = BNXT_ULP_CLASS_HID_01f0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13968,7 +17536,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [670] = {
+ [814] = {
.class_hid = BNXT_ULP_CLASS_HID_1ed4,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13988,7 +17556,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [671] = {
+ [815] = {
.class_hid = BNXT_ULP_CLASS_HID_2d40,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14007,7 +17575,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [672] = {
+ [816] = {
.class_hid = BNXT_ULP_CLASS_HID_2a24,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14027,7 +17595,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [673] = {
+ [817] = {
.class_hid = BNXT_ULP_CLASS_HID_3934,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14047,7 +17615,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [674] = {
+ [818] = {
.class_hid = BNXT_ULP_CLASS_HID_3608,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14068,7 +17636,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [675] = {
+ [819] = {
.class_hid = BNXT_ULP_CLASS_HID_5e60,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14086,7 +17654,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [676] = {
+ [820] = {
.class_hid = BNXT_ULP_CLASS_HID_5744,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14105,7 +17673,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [677] = {
+ [821] = {
.class_hid = BNXT_ULP_CLASS_HID_2a54,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14124,7 +17692,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [678] = {
+ [822] = {
.class_hid = BNXT_ULP_CLASS_HID_2328,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14144,7 +17712,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [679] = {
+ [823] = {
.class_hid = BNXT_ULP_CLASS_HID_71a4,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14163,7 +17731,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [680] = {
+ [824] = {
.class_hid = BNXT_ULP_CLASS_HID_4e78,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14183,7 +17751,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [681] = {
+ [825] = {
.class_hid = BNXT_ULP_CLASS_HID_5d88,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14203,7 +17771,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [682] = {
+ [826] = {
.class_hid = BNXT_ULP_CLASS_HID_5a6c,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14224,7 +17792,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [683] = {
+ [827] = {
.class_hid = BNXT_ULP_CLASS_HID_11a8,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14243,7 +17811,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [684] = {
+ [828] = {
.class_hid = BNXT_ULP_CLASS_HID_7738,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14263,7 +17831,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [685] = {
+ [829] = {
.class_hid = BNXT_ULP_CLASS_HID_4a48,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14283,7 +17851,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [686] = {
+ [830] = {
.class_hid = BNXT_ULP_CLASS_HID_432c,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14304,7 +17872,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [687] = {
+ [831] = {
.class_hid = BNXT_ULP_CLASS_HID_08ec,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14324,7 +17892,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [688] = {
+ [832] = {
.class_hid = BNXT_ULP_CLASS_HID_01c0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14345,7 +17913,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [689] = {
+ [833] = {
.class_hid = BNXT_ULP_CLASS_HID_14d0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14366,7 +17934,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [690] = {
+ [834] = {
.class_hid = BNXT_ULP_CLASS_HID_7a60,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14388,7 +17956,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [691] = {
+ [835] = {
.class_hid = BNXT_ULP_CLASS_HID_1d90,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14405,7 +17973,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [692] = {
+ [836] = {
.class_hid = BNXT_ULP_CLASS_HID_14b4,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14423,7 +17991,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [693] = {
+ [837] = {
.class_hid = BNXT_ULP_CLASS_HID_70f0,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14441,7 +18009,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [694] = {
+ [838] = {
.class_hid = BNXT_ULP_CLASS_HID_4814,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14460,7 +18028,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [695] = {
+ [839] = {
.class_hid = BNXT_ULP_CLASS_HID_3d94,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14478,7 +18046,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [696] = {
+ [840] = {
.class_hid = BNXT_ULP_CLASS_HID_34b8,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14497,7 +18065,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [697] = {
+ [841] = {
.class_hid = BNXT_ULP_CLASS_HID_09a8,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14516,7 +18084,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [698] = {
+ [842] = {
.class_hid = BNXT_ULP_CLASS_HID_00cc,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14536,7 +18104,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [699] = {
+ [843] = {
.class_hid = BNXT_ULP_CLASS_HID_3f64,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14554,7 +18122,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [700] = {
+ [844] = {
.class_hid = BNXT_ULP_CLASS_HID_3688,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14573,7 +18141,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [701] = {
+ [845] = {
.class_hid = BNXT_ULP_CLASS_HID_0b78,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14592,7 +18160,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [702] = {
+ [846] = {
.class_hid = BNXT_ULP_CLASS_HID_029c,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14612,7 +18180,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [703] = {
+ [847] = {
.class_hid = BNXT_ULP_CLASS_HID_5f68,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14631,7 +18199,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [704] = {
+ [848] = {
.class_hid = BNXT_ULP_CLASS_HID_568c,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14651,7 +18219,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [705] = {
+ [849] = {
.class_hid = BNXT_ULP_CLASS_HID_2b7c,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14671,7 +18239,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [706] = {
+ [850] = {
.class_hid = BNXT_ULP_CLASS_HID_22a0,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14692,7 +18260,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [707] = {
+ [851] = {
.class_hid = BNXT_ULP_CLASS_HID_4020,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14710,7 +18278,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [708] = {
+ [852] = {
.class_hid = BNXT_ULP_CLASS_HID_5b44,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14729,7 +18297,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [709] = {
+ [853] = {
.class_hid = BNXT_ULP_CLASS_HID_2c34,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14748,7 +18316,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [710] = {
+ [854] = {
.class_hid = BNXT_ULP_CLASS_HID_2758,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14768,7 +18336,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [711] = {
+ [855] = {
.class_hid = BNXT_ULP_CLASS_HID_18d8,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14787,7 +18355,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [712] = {
+ [856] = {
.class_hid = BNXT_ULP_CLASS_HID_13fc,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14807,7 +18375,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [713] = {
+ [857] = {
.class_hid = BNXT_ULP_CLASS_HID_4c38,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14827,7 +18395,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [714] = {
+ [858] = {
.class_hid = BNXT_ULP_CLASS_HID_475c,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14848,7 +18416,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [715] = {
+ [859] = {
.class_hid = BNXT_ULP_CLASS_HID_1aa8,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14867,7 +18435,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [716] = {
+ [860] = {
.class_hid = BNXT_ULP_CLASS_HID_15cc,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14887,7 +18455,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [717] = {
+ [861] = {
.class_hid = BNXT_ULP_CLASS_HID_4e08,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14907,7 +18475,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [718] = {
+ [862] = {
.class_hid = BNXT_ULP_CLASS_HID_492c,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14928,7 +18496,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [719] = {
+ [863] = {
.class_hid = BNXT_ULP_CLASS_HID_3aac,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14948,7 +18516,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [720] = {
+ [864] = {
.class_hid = BNXT_ULP_CLASS_HID_35d0,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14969,7 +18537,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [721] = {
+ [865] = {
.class_hid = BNXT_ULP_CLASS_HID_06c0,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14990,7 +18558,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [722] = {
+ [866] = {
.class_hid = BNXT_ULP_CLASS_HID_01e4,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -15012,7 +18580,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [723] = {
+ [867] = {
.class_hid = BNXT_ULP_CLASS_HID_4d32,
.class_tid = 3,
.hdr_sig_id = 0,
@@ -15026,7 +18594,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [724] = {
+ [868] = {
.class_hid = BNXT_ULP_CLASS_HID_54aa,
.class_tid = 3,
.hdr_sig_id = 0,
@@ -15041,7 +18609,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [725] = {
+ [869] = {
.class_hid = BNXT_ULP_CLASS_HID_0686,
.class_tid = 3,
.hdr_sig_id = 1,
@@ -15055,7 +18623,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [726] = {
+ [870] = {
.class_hid = BNXT_ULP_CLASS_HID_540e,
.class_tid = 3,
.hdr_sig_id = 1,
@@ -15070,7 +18638,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [727] = {
+ [871] = {
.class_hid = BNXT_ULP_CLASS_HID_2e3c,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -15085,7 +18653,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [728] = {
+ [872] = {
.class_hid = BNXT_ULP_CLASS_HID_3a20,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -15101,7 +18669,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [729] = {
+ [873] = {
.class_hid = BNXT_ULP_CLASS_HID_46f0,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -15117,7 +18685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [730] = {
+ [874] = {
.class_hid = BNXT_ULP_CLASS_HID_52e4,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -15134,7 +18702,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [731] = {
+ [875] = {
.class_hid = BNXT_ULP_CLASS_HID_55e4,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -15149,7 +18717,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [732] = {
+ [876] = {
.class_hid = BNXT_ULP_CLASS_HID_21f8,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -15165,7 +18733,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [733] = {
+ [877] = {
.class_hid = BNXT_ULP_CLASS_HID_75e8,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -15181,7 +18749,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [734] = {
+ [878] = {
.class_hid = BNXT_ULP_CLASS_HID_41fc,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -15198,7 +18766,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [735] = {
+ [879] = {
.class_hid = BNXT_ULP_CLASS_HID_4d12,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15213,7 +18781,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [736] = {
+ [880] = {
.class_hid = BNXT_ULP_CLASS_HID_548a,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15229,7 +18797,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [737] = {
+ [881] = {
.class_hid = BNXT_ULP_CLASS_HID_3356,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15245,7 +18813,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [738] = {
+ [882] = {
.class_hid = BNXT_ULP_CLASS_HID_1ace,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15262,7 +18830,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [739] = {
+ [883] = {
.class_hid = BNXT_ULP_CLASS_HID_1a9a,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15278,7 +18846,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [740] = {
+ [884] = {
.class_hid = BNXT_ULP_CLASS_HID_4d46,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15295,7 +18863,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [741] = {
+ [885] = {
.class_hid = BNXT_ULP_CLASS_HID_2812,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15312,7 +18880,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [742] = {
+ [886] = {
.class_hid = BNXT_ULP_CLASS_HID_338a,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15330,7 +18898,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [743] = {
+ [887] = {
.class_hid = BNXT_ULP_CLASS_HID_06e6,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15345,7 +18913,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [744] = {
+ [888] = {
.class_hid = BNXT_ULP_CLASS_HID_546e,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15361,7 +18929,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [745] = {
+ [889] = {
.class_hid = BNXT_ULP_CLASS_HID_46ee,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15377,7 +18945,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [746] = {
+ [890] = {
.class_hid = BNXT_ULP_CLASS_HID_0d22,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15394,7 +18962,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [747] = {
+ [891] = {
.class_hid = BNXT_ULP_CLASS_HID_26e2,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15410,7 +18978,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [748] = {
+ [892] = {
.class_hid = BNXT_ULP_CLASS_HID_746a,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15427,7 +18995,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [749] = {
+ [893] = {
.class_hid = BNXT_ULP_CLASS_HID_1fa6,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15444,7 +19012,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [750] = {
+ [894] = {
.class_hid = BNXT_ULP_CLASS_HID_2d2e,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15462,7 +19030,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [751] = {
+ [895] = {
.class_hid = BNXT_ULP_CLASS_HID_4ef2,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15477,7 +19045,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [752] = {
+ [896] = {
.class_hid = BNXT_ULP_CLASS_HID_576a,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15493,7 +19061,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [753] = {
+ [897] = {
.class_hid = BNXT_ULP_CLASS_HID_30b6,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15509,7 +19077,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [754] = {
+ [898] = {
.class_hid = BNXT_ULP_CLASS_HID_192e,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15526,7 +19094,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [755] = {
+ [899] = {
.class_hid = BNXT_ULP_CLASS_HID_197a,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15542,7 +19110,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [756] = {
+ [900] = {
.class_hid = BNXT_ULP_CLASS_HID_4ea6,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15559,7 +19127,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [757] = {
+ [901] = {
.class_hid = BNXT_ULP_CLASS_HID_2bf2,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15576,7 +19144,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [758] = {
+ [902] = {
.class_hid = BNXT_ULP_CLASS_HID_306a,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15594,7 +19162,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [759] = {
+ [903] = {
.class_hid = BNXT_ULP_CLASS_HID_06c6,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15609,7 +19177,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [760] = {
+ [904] = {
.class_hid = BNXT_ULP_CLASS_HID_544e,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15625,7 +19193,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [761] = {
+ [905] = {
.class_hid = BNXT_ULP_CLASS_HID_46ce,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15641,7 +19209,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [762] = {
+ [906] = {
.class_hid = BNXT_ULP_CLASS_HID_0d02,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15658,7 +19226,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [763] = {
+ [907] = {
.class_hid = BNXT_ULP_CLASS_HID_26c2,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15674,7 +19242,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [764] = {
+ [908] = {
.class_hid = BNXT_ULP_CLASS_HID_744a,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15691,7 +19259,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [765] = {
+ [909] = {
.class_hid = BNXT_ULP_CLASS_HID_1f86,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15708,7 +19276,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [766] = {
+ [910] = {
.class_hid = BNXT_ULP_CLASS_HID_2d0e,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15726,7 +19294,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [767] = {
+ [911] = {
.class_hid = BNXT_ULP_CLASS_HID_2e1c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15742,7 +19310,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [768] = {
+ [912] = {
.class_hid = BNXT_ULP_CLASS_HID_3a00,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15759,7 +19327,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [769] = {
+ [913] = {
.class_hid = BNXT_ULP_CLASS_HID_46d0,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15776,7 +19344,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [770] = {
+ [914] = {
.class_hid = BNXT_ULP_CLASS_HID_52c4,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15794,7 +19362,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [771] = {
+ [915] = {
.class_hid = BNXT_ULP_CLASS_HID_4e10,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15811,7 +19379,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [772] = {
+ [916] = {
.class_hid = BNXT_ULP_CLASS_HID_5a04,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15829,7 +19397,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [773] = {
+ [917] = {
.class_hid = BNXT_ULP_CLASS_HID_1f98,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15847,7 +19415,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [774] = {
+ [918] = {
.class_hid = BNXT_ULP_CLASS_HID_72f8,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15866,7 +19434,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [775] = {
+ [919] = {
.class_hid = BNXT_ULP_CLASS_HID_0a78,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15883,7 +19451,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [776] = {
+ [920] = {
.class_hid = BNXT_ULP_CLASS_HID_166c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15901,7 +19469,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [777] = {
+ [921] = {
.class_hid = BNXT_ULP_CLASS_HID_233c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15919,7 +19487,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [778] = {
+ [922] = {
.class_hid = BNXT_ULP_CLASS_HID_0f20,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15938,7 +19506,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [779] = {
+ [923] = {
.class_hid = BNXT_ULP_CLASS_HID_2a7c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15956,7 +19524,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [780] = {
+ [924] = {
.class_hid = BNXT_ULP_CLASS_HID_3660,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15975,7 +19543,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [781] = {
+ [925] = {
.class_hid = BNXT_ULP_CLASS_HID_4330,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15994,7 +19562,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [782] = {
+ [926] = {
.class_hid = BNXT_ULP_CLASS_HID_2f24,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -16014,7 +19582,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [783] = {
+ [927] = {
.class_hid = BNXT_ULP_CLASS_HID_5584,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16030,7 +19598,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [784] = {
+ [928] = {
.class_hid = BNXT_ULP_CLASS_HID_2198,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16047,7 +19615,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [785] = {
+ [929] = {
.class_hid = BNXT_ULP_CLASS_HID_7588,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16064,7 +19632,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [786] = {
+ [930] = {
.class_hid = BNXT_ULP_CLASS_HID_419c,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16082,7 +19650,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [787] = {
+ [931] = {
.class_hid = BNXT_ULP_CLASS_HID_7758,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16099,7 +19667,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [788] = {
+ [932] = {
.class_hid = BNXT_ULP_CLASS_HID_43ac,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16117,7 +19685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [789] = {
+ [933] = {
.class_hid = BNXT_ULP_CLASS_HID_0c10,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16135,7 +19703,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [790] = {
+ [934] = {
.class_hid = BNXT_ULP_CLASS_HID_1864,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16154,7 +19722,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [791] = {
+ [935] = {
.class_hid = BNXT_ULP_CLASS_HID_30c8,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16171,7 +19739,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [792] = {
+ [936] = {
.class_hid = BNXT_ULP_CLASS_HID_1cdc,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16189,7 +19757,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [793] = {
+ [937] = {
.class_hid = BNXT_ULP_CLASS_HID_50cc,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16207,7 +19775,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [794] = {
+ [938] = {
.class_hid = BNXT_ULP_CLASS_HID_3d20,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16226,7 +19794,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [795] = {
+ [939] = {
.class_hid = BNXT_ULP_CLASS_HID_529c,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16244,7 +19812,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [796] = {
+ [940] = {
.class_hid = BNXT_ULP_CLASS_HID_3ef0,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16263,7 +19831,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [797] = {
+ [941] = {
.class_hid = BNXT_ULP_CLASS_HID_72e0,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16282,7 +19850,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [798] = {
+ [942] = {
.class_hid = BNXT_ULP_CLASS_HID_5ef4,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16302,7 +19870,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [799] = {
+ [943] = {
.class_hid = BNXT_ULP_CLASS_HID_2dfc,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16318,7 +19886,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [800] = {
+ [944] = {
.class_hid = BNXT_ULP_CLASS_HID_39e0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16335,7 +19903,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [801] = {
+ [945] = {
.class_hid = BNXT_ULP_CLASS_HID_4530,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16352,7 +19920,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [802] = {
+ [946] = {
.class_hid = BNXT_ULP_CLASS_HID_5124,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16370,7 +19938,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [803] = {
+ [947] = {
.class_hid = BNXT_ULP_CLASS_HID_4df0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16387,7 +19955,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [804] = {
+ [948] = {
.class_hid = BNXT_ULP_CLASS_HID_59e4,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16405,7 +19973,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [805] = {
+ [949] = {
.class_hid = BNXT_ULP_CLASS_HID_1c78,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16423,7 +19991,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [806] = {
+ [950] = {
.class_hid = BNXT_ULP_CLASS_HID_7118,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16442,7 +20010,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [807] = {
+ [951] = {
.class_hid = BNXT_ULP_CLASS_HID_0998,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16459,7 +20027,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [808] = {
+ [952] = {
.class_hid = BNXT_ULP_CLASS_HID_158c,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16477,7 +20045,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [809] = {
+ [953] = {
.class_hid = BNXT_ULP_CLASS_HID_20dc,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16495,7 +20063,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [810] = {
+ [954] = {
.class_hid = BNXT_ULP_CLASS_HID_0cc0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16514,7 +20082,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [811] = {
+ [955] = {
.class_hid = BNXT_ULP_CLASS_HID_299c,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16532,7 +20100,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [812] = {
+ [956] = {
.class_hid = BNXT_ULP_CLASS_HID_3580,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16551,7 +20119,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [813] = {
+ [957] = {
.class_hid = BNXT_ULP_CLASS_HID_40d0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16570,7 +20138,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [814] = {
+ [958] = {
.class_hid = BNXT_ULP_CLASS_HID_2cc4,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16590,7 +20158,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [815] = {
+ [959] = {
.class_hid = BNXT_ULP_CLASS_HID_55a4,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16606,7 +20174,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [816] = {
+ [960] = {
.class_hid = BNXT_ULP_CLASS_HID_21b8,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16623,7 +20191,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [817] = {
+ [961] = {
.class_hid = BNXT_ULP_CLASS_HID_75a8,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16640,7 +20208,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [818] = {
+ [962] = {
.class_hid = BNXT_ULP_CLASS_HID_41bc,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16658,7 +20226,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [819] = {
+ [963] = {
.class_hid = BNXT_ULP_CLASS_HID_7778,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16675,7 +20243,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [820] = {
+ [964] = {
.class_hid = BNXT_ULP_CLASS_HID_438c,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16693,7 +20261,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [821] = {
+ [965] = {
.class_hid = BNXT_ULP_CLASS_HID_0c30,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16711,7 +20279,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [822] = {
+ [966] = {
.class_hid = BNXT_ULP_CLASS_HID_1844,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16730,7 +20298,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [823] = {
+ [967] = {
.class_hid = BNXT_ULP_CLASS_HID_30e8,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16747,7 +20315,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [824] = {
+ [968] = {
.class_hid = BNXT_ULP_CLASS_HID_1cfc,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16765,7 +20333,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [825] = {
+ [969] = {
.class_hid = BNXT_ULP_CLASS_HID_50ec,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16783,7 +20351,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [826] = {
+ [970] = {
.class_hid = BNXT_ULP_CLASS_HID_3d00,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16802,7 +20370,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [827] = {
+ [971] = {
.class_hid = BNXT_ULP_CLASS_HID_52bc,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16820,7 +20388,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [828] = {
+ [972] = {
.class_hid = BNXT_ULP_CLASS_HID_3ed0,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16839,7 +20407,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [829] = {
+ [973] = {
.class_hid = BNXT_ULP_CLASS_HID_72c0,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16858,7 +20426,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [830] = {
+ [974] = {
.class_hid = BNXT_ULP_CLASS_HID_5ed4,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16878,7 +20446,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [831] = {
+ [975] = {
.class_hid = BNXT_ULP_CLASS_HID_3866,
.class_tid = 3,
.hdr_sig_id = 0,
@@ -16893,7 +20461,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC }
},
- [832] = {
+ [976] = {
.class_hid = BNXT_ULP_CLASS_HID_381e,
.class_tid = 3,
.hdr_sig_id = 1,
@@ -16908,7 +20476,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC }
},
- [833] = {
+ [977] = {
.class_hid = BNXT_ULP_CLASS_HID_3860,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -16924,7 +20492,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC }
},
- [834] = {
+ [978] = {
.class_hid = BNXT_ULP_CLASS_HID_0454,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -16941,7 +20509,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID }
},
- [835] = {
+ [979] = {
.class_hid = BNXT_ULP_CLASS_HID_3818,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -16957,7 +20525,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC }
},
- [836] = {
+ [980] = {
.class_hid = BNXT_ULP_CLASS_HID_042c,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -16974,7 +20542,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID }
},
- [837] = {
+ [981] = {
.class_hid = BNXT_ULP_CLASS_HID_3846,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -16990,7 +20558,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC }
},
- [838] = {
+ [982] = {
.class_hid = BNXT_ULP_CLASS_HID_387e,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -17006,7 +20574,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC }
},
- [839] = {
+ [983] = {
.class_hid = BNXT_ULP_CLASS_HID_3ba6,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -17022,7 +20590,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC }
},
- [840] = {
+ [984] = {
.class_hid = BNXT_ULP_CLASS_HID_385e,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -17038,7 +20606,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC }
},
- [841] = {
+ [985] = {
.class_hid = BNXT_ULP_CLASS_HID_3840,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -17055,7 +20623,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC }
},
- [842] = {
+ [986] = {
.class_hid = BNXT_ULP_CLASS_HID_0474,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -17073,7 +20641,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID }
},
- [843] = {
+ [987] = {
.class_hid = BNXT_ULP_CLASS_HID_3878,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -17090,7 +20658,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC }
},
- [844] = {
+ [988] = {
.class_hid = BNXT_ULP_CLASS_HID_044c,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -17108,7 +20676,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID }
},
- [845] = {
+ [989] = {
.class_hid = BNXT_ULP_CLASS_HID_3ba0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -17125,7 +20693,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC }
},
- [846] = {
+ [990] = {
.class_hid = BNXT_ULP_CLASS_HID_0794,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -17143,7 +20711,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID }
},
- [847] = {
+ [991] = {
.class_hid = BNXT_ULP_CLASS_HID_3858,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -17160,7 +20728,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC }
},
- [848] = {
+ [992] = {
.class_hid = BNXT_ULP_CLASS_HID_046c,
.class_tid = 3,
.hdr_sig_id = 11,
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
index 84e3d92f41..c016e1940a 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Tue Jul 13 12:36:40 2021 */
+/* date: Fri Aug 20 17:59:14 2021 */
#ifndef ULP_TEMPLATE_DB_H_
#define ULP_TEMPLATE_DB_H_
@@ -11,14 +11,14 @@
#define BNXT_ULP_REGFILE_MAX_SZ 42
#define BNXT_ULP_MAX_NUM_DEVICES 4
#define BNXT_ULP_LOG2_MAX_NUM_DEV 2
-#define BNXT_ULP_GEN_TBL_MAX_SZ 12
-#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 32768
-#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 849
+#define BNXT_ULP_GEN_TBL_MAX_SZ 16
+#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 65536
+#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 993
#define BNXT_ULP_CLASS_HID_LOW_PRIME 6701
#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907
-#define BNXT_ULP_CLASS_HID_SHFTR 24
-#define BNXT_ULP_CLASS_HID_SHFTL 24
-#define BNXT_ULP_CLASS_HID_MASK 32767
+#define BNXT_ULP_CLASS_HID_SHFTR 28
+#define BNXT_ULP_CLASS_HID_SHFTL 28
+#define BNXT_ULP_CLASS_HID_MASK 65535
#define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048
#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 86
#define BNXT_ULP_ACT_HID_LOW_PRIME 7919
@@ -27,10 +27,10 @@
#define BNXT_ULP_ACT_HID_SHFTL 26
#define BNXT_ULP_ACT_HID_MASK 2047
#define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 8
-#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 62
+#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 110
#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 50
-#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 206
-#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 6
+#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 278
+#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 8
#define BNXT_ULP_COND_GOTO_REJECT 1023
#define BNXT_ULP_COND_GOTO_RF 0x10000
#define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7
@@ -44,10 +44,10 @@
#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 618
#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 49
#define ULP_THOR_CLASS_TMPL_LIST_SIZE 6
-#define ULP_THOR_CLASS_TBL_LIST_SIZE 114
-#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 2305
-#define ULP_THOR_CLASS_IDENT_LIST_SIZE 39
-#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1192
+#define ULP_THOR_CLASS_TBL_LIST_SIZE 116
+#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 2323
+#define ULP_THOR_CLASS_IDENT_LIST_SIZE 38
+#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1313
#define ULP_THOR_CLASS_COND_LIST_SIZE 55
#define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7
#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 35
@@ -56,11 +56,11 @@
#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 536
#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 39
#define ULP_THOR_ACT_TMPL_LIST_SIZE 7
-#define ULP_THOR_ACT_TBL_LIST_SIZE 28
-#define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 2
-#define ULP_THOR_ACT_IDENT_LIST_SIZE 1
-#define ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE 479
-#define ULP_THOR_ACT_COND_LIST_SIZE 20
+#define ULP_THOR_ACT_TBL_LIST_SIZE 36
+#define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 16
+#define ULP_THOR_ACT_IDENT_LIST_SIZE 3
+#define ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE 505
+#define ULP_THOR_ACT_COND_LIST_SIZE 27
enum bnxt_ulp_act_bit {
BNXT_ULP_ACT_BIT_MARK = 0x0000000000000001,
@@ -158,56 +158,60 @@ enum bnxt_ulp_cf_idx {
BNXT_ULP_CF_IDX_O_L4_DST_PORT = 18,
BNXT_ULP_CF_IDX_I_L4_SRC_PORT = 19,
BNXT_ULP_CF_IDX_I_L4_DST_PORT = 20,
- BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT = 21,
- BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT = 22,
- BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT = 23,
- BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT = 24,
- BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID = 25,
- BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID = 26,
- BNXT_ULP_CF_IDX_O_L3_PROTO_ID = 27,
- BNXT_ULP_CF_IDX_I_L3_PROTO_ID = 28,
- BNXT_ULP_CF_IDX_DEV_PORT_ID = 29,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 30,
- BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 31,
- BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 32,
- BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 33,
- BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 34,
- BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 35,
- BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 36,
- BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 37,
- BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 38,
- BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 39,
- BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 40,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 41,
- BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 42,
- BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG = 43,
- BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG = 44,
- BNXT_ULP_CF_IDX_ACT_DEC_TTL = 45,
- BNXT_ULP_CF_IDX_ACT_T_DEC_TTL = 46,
- BNXT_ULP_CF_IDX_ACT_PORT_IS_SET = 47,
- BNXT_ULP_CF_IDX_ACT_PORT_TYPE = 48,
- BNXT_ULP_CF_IDX_MATCH_PORT_TYPE = 49,
- BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP = 50,
- BNXT_ULP_CF_IDX_MATCH_PORT_IS_PF = 51,
- BNXT_ULP_CF_IDX_VF_TO_VF = 52,
- BNXT_ULP_CF_IDX_L3_HDR_CNT = 53,
- BNXT_ULP_CF_IDX_L4_HDR_CNT = 54,
- BNXT_ULP_CF_IDX_VFR_MODE = 55,
- BNXT_ULP_CF_IDX_L3_TUN = 56,
- BNXT_ULP_CF_IDX_L3_TUN_DECAP = 57,
- BNXT_ULP_CF_IDX_FID = 58,
- BNXT_ULP_CF_IDX_HDR_SIG_ID = 59,
- BNXT_ULP_CF_IDX_FLOW_SIG_ID = 60,
- BNXT_ULP_CF_IDX_WC_MATCH = 61,
- BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG = 62,
- BNXT_ULP_CF_IDX_TUNNEL_ID = 63,
- BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID = 64,
- BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID = 65,
- BNXT_ULP_CF_IDX_OO_VLAN_FB_VID = 66,
- BNXT_ULP_CF_IDX_OI_VLAN_FB_VID = 67,
- BNXT_ULP_CF_IDX_IO_VLAN_FB_VID = 68,
- BNXT_ULP_CF_IDX_II_VLAN_FB_VID = 69,
- BNXT_ULP_CF_IDX_LAST = 70
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK = 21,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK = 22,
+ BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK = 23,
+ BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK = 24,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT = 25,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT = 26,
+ BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT = 27,
+ BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT = 28,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID = 29,
+ BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID = 30,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID = 31,
+ BNXT_ULP_CF_IDX_I_L3_PROTO_ID = 32,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID = 33,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 34,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 35,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 36,
+ BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 37,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 38,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 39,
+ BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 40,
+ BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 41,
+ BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 42,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 43,
+ BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 44,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 45,
+ BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 46,
+ BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG = 47,
+ BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG = 48,
+ BNXT_ULP_CF_IDX_ACT_DEC_TTL = 49,
+ BNXT_ULP_CF_IDX_ACT_T_DEC_TTL = 50,
+ BNXT_ULP_CF_IDX_ACT_PORT_IS_SET = 51,
+ BNXT_ULP_CF_IDX_ACT_PORT_TYPE = 52,
+ BNXT_ULP_CF_IDX_MATCH_PORT_TYPE = 53,
+ BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP = 54,
+ BNXT_ULP_CF_IDX_MATCH_PORT_IS_PF = 55,
+ BNXT_ULP_CF_IDX_VF_TO_VF = 56,
+ BNXT_ULP_CF_IDX_L3_HDR_CNT = 57,
+ BNXT_ULP_CF_IDX_L4_HDR_CNT = 58,
+ BNXT_ULP_CF_IDX_VFR_MODE = 59,
+ BNXT_ULP_CF_IDX_L3_TUN = 60,
+ BNXT_ULP_CF_IDX_L3_TUN_DECAP = 61,
+ BNXT_ULP_CF_IDX_FID = 62,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID = 63,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID = 64,
+ BNXT_ULP_CF_IDX_WC_MATCH = 65,
+ BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG = 66,
+ BNXT_ULP_CF_IDX_TUNNEL_ID = 67,
+ BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID = 68,
+ BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID = 69,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID = 70,
+ BNXT_ULP_CF_IDX_OI_VLAN_FB_VID = 71,
+ BNXT_ULP_CF_IDX_IO_VLAN_FB_VID = 72,
+ BNXT_ULP_CF_IDX_II_VLAN_FB_VID = 73,
+ BNXT_ULP_CF_IDX_LAST = 74
};
enum bnxt_ulp_cond_list_opc {
@@ -394,38 +398,49 @@ enum bnxt_ulp_glb_rf_idx {
BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 = 9,
BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 = 10,
BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 = 11,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0 = 12,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1 = 13,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_6 = 12,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_7 = 13,
BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 = 14,
BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 = 15,
BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 = 16,
BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3 = 17,
BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4 = 18,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0 = 19,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1 = 20,
- BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0 = 21,
- BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_1 = 22,
- BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 = 23,
- BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 = 24,
- BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 = 25,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 26,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 = 27,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2 = 28,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 29,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 30,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 31,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 32,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 33,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 34,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 35,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 36,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 37,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 38,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 39,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 40,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 41,
- BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID = 42,
- BNXT_ULP_GLB_RF_IDX_LAST = 43
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0 = 19,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1 = 20,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2 = 21,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3 = 22,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_4 = 23,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_5 = 24,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_6 = 25,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_7 = 26,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0 = 27,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1 = 28,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2 = 29,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3 = 30,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_4 = 31,
+ BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0 = 32,
+ BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_1 = 33,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 = 34,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 = 35,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 = 36,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 37,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 = 38,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2 = 39,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 40,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 41,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 42,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 43,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 44,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 45,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 46,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 47,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 48,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 49,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 50,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 51,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 52,
+ BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID = 53,
+ BNXT_ULP_GLB_RF_IDX_LAST = 54
};
enum bnxt_ulp_hdr_type {
@@ -608,7 +623,9 @@ enum bnxt_ulp_resource_sub_type {
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR = 2,
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE = 3,
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE = 4,
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE = 5
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE = 5,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE = 6,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE = 7
};
enum bnxt_ulp_act_prop_sz {
@@ -1526,166 +1543,310 @@ enum bnxt_ulp_class_hid {
BNXT_ULP_CLASS_HID_315d = 0x315d,
BNXT_ULP_CLASS_HID_3612 = 0x3612,
BNXT_ULP_CLASS_HID_66da = 0x66da,
- BNXT_ULP_CLASS_HID_6165 = 0x6165,
- BNXT_ULP_CLASS_HID_2aa1 = 0x2aa1,
- BNXT_ULP_CLASS_HID_09cd = 0x09cd,
- BNXT_ULP_CLASS_HID_3845 = 0x3845,
- BNXT_ULP_CLASS_HID_11e9 = 0x11e9,
- BNXT_ULP_CLASS_HID_4361 = 0x4361,
- BNXT_ULP_CLASS_HID_218d = 0x218d,
- BNXT_ULP_CLASS_HID_5105 = 0x5105,
- BNXT_ULP_CLASS_HID_0c89 = 0x0c89,
- BNXT_ULP_CLASS_HID_3e81 = 0x3e81,
- BNXT_ULP_CLASS_HID_1dad = 0x1dad,
- BNXT_ULP_CLASS_HID_4ca5 = 0x4ca5,
- BNXT_ULP_CLASS_HID_25c9 = 0x25c9,
- BNXT_ULP_CLASS_HID_57c1 = 0x57c1,
- BNXT_ULP_CLASS_HID_33ed = 0x33ed,
- BNXT_ULP_CLASS_HID_65e5 = 0x65e5,
- BNXT_ULP_CLASS_HID_6dd9 = 0x6dd9,
- BNXT_ULP_CLASS_HID_261d = 0x261d,
- BNXT_ULP_CLASS_HID_0571 = 0x0571,
- BNXT_ULP_CLASS_HID_34f9 = 0x34f9,
- BNXT_ULP_CLASS_HID_1d55 = 0x1d55,
- BNXT_ULP_CLASS_HID_4fdd = 0x4fdd,
- BNXT_ULP_CLASS_HID_2d31 = 0x2d31,
- BNXT_ULP_CLASS_HID_5db9 = 0x5db9,
- BNXT_ULP_CLASS_HID_0035 = 0x0035,
- BNXT_ULP_CLASS_HID_323d = 0x323d,
- BNXT_ULP_CLASS_HID_1111 = 0x1111,
- BNXT_ULP_CLASS_HID_4019 = 0x4019,
- BNXT_ULP_CLASS_HID_2975 = 0x2975,
- BNXT_ULP_CLASS_HID_5b7d = 0x5b7d,
- BNXT_ULP_CLASS_HID_3f51 = 0x3f51,
- BNXT_ULP_CLASS_HID_6959 = 0x6959,
- BNXT_ULP_CLASS_HID_0e85 = 0x0e85,
- BNXT_ULP_CLASS_HID_380d = 0x380d,
- BNXT_ULP_CLASS_HID_1f21 = 0x1f21,
- BNXT_ULP_CLASS_HID_4ea9 = 0x4ea9,
- BNXT_ULP_CLASS_HID_1705 = 0x1705,
- BNXT_ULP_CLASS_HID_418d = 0x418d,
- BNXT_ULP_CLASS_HID_2721 = 0x2721,
- BNXT_ULP_CLASS_HID_57a9 = 0x57a9,
- BNXT_ULP_CLASS_HID_1a25 = 0x1a25,
- BNXT_ULP_CLASS_HID_342d = 0x342d,
- BNXT_ULP_CLASS_HID_2b01 = 0x2b01,
- BNXT_ULP_CLASS_HID_5a09 = 0x5a09,
- BNXT_ULP_CLASS_HID_2325 = 0x2325,
- BNXT_ULP_CLASS_HID_5d2d = 0x5d2d,
- BNXT_ULP_CLASS_HID_3101 = 0x3101,
- BNXT_ULP_CLASS_HID_6309 = 0x6309,
- BNXT_ULP_CLASS_HID_0bad = 0x0bad,
- BNXT_ULP_CLASS_HID_2535 = 0x2535,
- BNXT_ULP_CLASS_HID_1869 = 0x1869,
- BNXT_ULP_CLASS_HID_4bf1 = 0x4bf1,
- BNXT_ULP_CLASS_HID_136d = 0x136d,
- BNXT_ULP_CLASS_HID_43f5 = 0x43f5,
- BNXT_ULP_CLASS_HID_2129 = 0x2129,
- BNXT_ULP_CLASS_HID_53b1 = 0x53b1,
- BNXT_ULP_CLASS_HID_072d = 0x072d,
- BNXT_ULP_CLASS_HID_3135 = 0x3135,
- BNXT_ULP_CLASS_HID_1429 = 0x1429,
- BNXT_ULP_CLASS_HID_4731 = 0x4731,
- BNXT_ULP_CLASS_HID_2f6d = 0x2f6d,
- BNXT_ULP_CLASS_HID_5f75 = 0x5f75,
- BNXT_ULP_CLASS_HID_3d69 = 0x3d69,
- BNXT_ULP_CLASS_HID_6f71 = 0x6f71,
- BNXT_ULP_CLASS_HID_0dbd = 0x0dbd,
- BNXT_ULP_CLASS_HID_3f25 = 0x3f25,
- BNXT_ULP_CLASS_HID_1239 = 0x1239,
- BNXT_ULP_CLASS_HID_4da1 = 0x4da1,
- BNXT_ULP_CLASS_HID_153d = 0x153d,
- BNXT_ULP_CLASS_HID_45a5 = 0x45a5,
- BNXT_ULP_CLASS_HID_3bb9 = 0x3bb9,
- BNXT_ULP_CLASS_HID_55a1 = 0x55a1,
- BNXT_ULP_CLASS_HID_193d = 0x193d,
- BNXT_ULP_CLASS_HID_4b25 = 0x4b25,
- BNXT_ULP_CLASS_HID_2e39 = 0x2e39,
- BNXT_ULP_CLASS_HID_5921 = 0x5921,
- BNXT_ULP_CLASS_HID_213d = 0x213d,
- BNXT_ULP_CLASS_HID_5125 = 0x5125,
- BNXT_ULP_CLASS_HID_3739 = 0x3739,
- BNXT_ULP_CLASS_HID_093d = 0x093d,
- BNXT_ULP_CLASS_HID_684d = 0x684d,
- BNXT_ULP_CLASS_HID_2389 = 0x2389,
- BNXT_ULP_CLASS_HID_00e5 = 0x00e5,
- BNXT_ULP_CLASS_HID_316d = 0x316d,
- BNXT_ULP_CLASS_HID_18c1 = 0x18c1,
- BNXT_ULP_CLASS_HID_4a49 = 0x4a49,
- BNXT_ULP_CLASS_HID_28a5 = 0x28a5,
- BNXT_ULP_CLASS_HID_582d = 0x582d,
- BNXT_ULP_CLASS_HID_05a1 = 0x05a1,
- BNXT_ULP_CLASS_HID_37a9 = 0x37a9,
- BNXT_ULP_CLASS_HID_1485 = 0x1485,
- BNXT_ULP_CLASS_HID_458d = 0x458d,
- BNXT_ULP_CLASS_HID_2ce1 = 0x2ce1,
- BNXT_ULP_CLASS_HID_5ee9 = 0x5ee9,
- BNXT_ULP_CLASS_HID_3ac5 = 0x3ac5,
- BNXT_ULP_CLASS_HID_6ccd = 0x6ccd,
- BNXT_ULP_CLASS_HID_0b11 = 0x0b11,
- BNXT_ULP_CLASS_HID_3d99 = 0x3d99,
- BNXT_ULP_CLASS_HID_1ab5 = 0x1ab5,
- BNXT_ULP_CLASS_HID_4b3d = 0x4b3d,
- BNXT_ULP_CLASS_HID_1291 = 0x1291,
- BNXT_ULP_CLASS_HID_4419 = 0x4419,
- BNXT_ULP_CLASS_HID_22b5 = 0x22b5,
- BNXT_ULP_CLASS_HID_523d = 0x523d,
- BNXT_ULP_CLASS_HID_1fb1 = 0x1fb1,
- BNXT_ULP_CLASS_HID_31b9 = 0x31b9,
- BNXT_ULP_CLASS_HID_2e95 = 0x2e95,
- BNXT_ULP_CLASS_HID_5f9d = 0x5f9d,
- BNXT_ULP_CLASS_HID_26b1 = 0x26b1,
- BNXT_ULP_CLASS_HID_58b9 = 0x58b9,
- BNXT_ULP_CLASS_HID_3495 = 0x3495,
- BNXT_ULP_CLASS_HID_669d = 0x669d,
- BNXT_ULP_CLASS_HID_0e39 = 0x0e39,
- BNXT_ULP_CLASS_HID_20a1 = 0x20a1,
- BNXT_ULP_CLASS_HID_1dfd = 0x1dfd,
- BNXT_ULP_CLASS_HID_4e65 = 0x4e65,
- BNXT_ULP_CLASS_HID_16f9 = 0x16f9,
- BNXT_ULP_CLASS_HID_4661 = 0x4661,
- BNXT_ULP_CLASS_HID_24bd = 0x24bd,
- BNXT_ULP_CLASS_HID_5625 = 0x5625,
- BNXT_ULP_CLASS_HID_02b9 = 0x02b9,
- BNXT_ULP_CLASS_HID_34a1 = 0x34a1,
- BNXT_ULP_CLASS_HID_11bd = 0x11bd,
- BNXT_ULP_CLASS_HID_42a5 = 0x42a5,
- BNXT_ULP_CLASS_HID_2af9 = 0x2af9,
- BNXT_ULP_CLASS_HID_5ae1 = 0x5ae1,
- BNXT_ULP_CLASS_HID_38fd = 0x38fd,
- BNXT_ULP_CLASS_HID_6ae5 = 0x6ae5,
- BNXT_ULP_CLASS_HID_0829 = 0x0829,
- BNXT_ULP_CLASS_HID_3ab1 = 0x3ab1,
- BNXT_ULP_CLASS_HID_17ad = 0x17ad,
- BNXT_ULP_CLASS_HID_4835 = 0x4835,
- BNXT_ULP_CLASS_HID_10a9 = 0x10a9,
- BNXT_ULP_CLASS_HID_4031 = 0x4031,
- BNXT_ULP_CLASS_HID_3e2d = 0x3e2d,
- BNXT_ULP_CLASS_HID_5035 = 0x5035,
- BNXT_ULP_CLASS_HID_1ca9 = 0x1ca9,
- BNXT_ULP_CLASS_HID_4eb1 = 0x4eb1,
- BNXT_ULP_CLASS_HID_2bad = 0x2bad,
- BNXT_ULP_CLASS_HID_5cb5 = 0x5cb5,
- BNXT_ULP_CLASS_HID_24a9 = 0x24a9,
- BNXT_ULP_CLASS_HID_54b1 = 0x54b1,
- BNXT_ULP_CLASS_HID_32ad = 0x32ad,
- BNXT_ULP_CLASS_HID_0ca9 = 0x0ca9,
- BNXT_ULP_CLASS_HID_7f35 = 0x7f35,
- BNXT_ULP_CLASS_HID_34f1 = 0x34f1,
- BNXT_ULP_CLASS_HID_179d = 0x179d,
- BNXT_ULP_CLASS_HID_2615 = 0x2615,
- BNXT_ULP_CLASS_HID_0fb9 = 0x0fb9,
- BNXT_ULP_CLASS_HID_5d31 = 0x5d31,
- BNXT_ULP_CLASS_HID_3fdd = 0x3fdd,
- BNXT_ULP_CLASS_HID_4f55 = 0x4f55,
- BNXT_ULP_CLASS_HID_12d9 = 0x12d9,
- BNXT_ULP_CLASS_HID_20d1 = 0x20d1,
- BNXT_ULP_CLASS_HID_03fd = 0x03fd,
- BNXT_ULP_CLASS_HID_52f5 = 0x52f5,
- BNXT_ULP_CLASS_HID_3b99 = 0x3b99,
- BNXT_ULP_CLASS_HID_4991 = 0x4991,
- BNXT_ULP_CLASS_HID_2dbd = 0x2dbd,
- BNXT_ULP_CLASS_HID_7bb5 = 0x7bb5,
+ BNXT_ULP_CLASS_HID_e082 = 0xe082,
+ BNXT_ULP_CLASS_HID_ab46 = 0xab46,
+ BNXT_ULP_CLASS_HID_c82a = 0xc82a,
+ BNXT_ULP_CLASS_HID_f9a2 = 0xf9a2,
+ BNXT_ULP_CLASS_HID_d8ce = 0xd8ce,
+ BNXT_ULP_CLASS_HID_a2d2 = 0xa2d2,
+ BNXT_ULP_CLASS_HID_c076 = 0xc076,
+ BNXT_ULP_CLASS_HID_f1ee = 0xf1ee,
+ BNXT_ULP_CLASS_HID_a96e = 0xa96e,
+ BNXT_ULP_CLASS_HID_dae6 = 0xdae6,
+ BNXT_ULP_CLASS_HID_c7aa = 0xc7aa,
+ BNXT_ULP_CLASS_HID_c26e = 0xc26e,
+ BNXT_ULP_CLASS_HID_a0fa = 0xa0fa,
+ BNXT_ULP_CLASS_HID_d272 = 0xd272,
+ BNXT_ULP_CLASS_HID_fff6 = 0xfff6,
+ BNXT_ULP_CLASS_HID_e16e = 0xe16e,
+ BNXT_ULP_CLASS_HID_e165 = 0xe165,
+ BNXT_ULP_CLASS_HID_aaa1 = 0xaaa1,
+ BNXT_ULP_CLASS_HID_c9cd = 0xc9cd,
+ BNXT_ULP_CLASS_HID_f845 = 0xf845,
+ BNXT_ULP_CLASS_HID_90f9 = 0x90f9,
+ BNXT_ULP_CLASS_HID_c371 = 0xc371,
+ BNXT_ULP_CLASS_HID_e19d = 0xe19d,
+ BNXT_ULP_CLASS_HID_d015 = 0xd015,
+ BNXT_ULP_CLASS_HID_8c09 = 0x8c09,
+ BNXT_ULP_CLASS_HID_be89 = 0xbe89,
+ BNXT_ULP_CLASS_HID_ddad = 0xddad,
+ BNXT_ULP_CLASS_HID_cc2d = 0xcc2d,
+ BNXT_ULP_CLASS_HID_a4d9 = 0xa4d9,
+ BNXT_ULP_CLASS_HID_d759 = 0xd759,
+ BNXT_ULP_CLASS_HID_f27d = 0xf27d,
+ BNXT_ULP_CLASS_HID_e4fd = 0xe4fd,
+ BNXT_ULP_CLASS_HID_ecf6 = 0xecf6,
+ BNXT_ULP_CLASS_HID_a732 = 0xa732,
+ BNXT_ULP_CLASS_HID_c45e = 0xc45e,
+ BNXT_ULP_CLASS_HID_f5d6 = 0xf5d6,
+ BNXT_ULP_CLASS_HID_d4ba = 0xd4ba,
+ BNXT_ULP_CLASS_HID_aea6 = 0xaea6,
+ BNXT_ULP_CLASS_HID_cc02 = 0xcc02,
+ BNXT_ULP_CLASS_HID_fd9a = 0xfd9a,
+ BNXT_ULP_CLASS_HID_a51a = 0xa51a,
+ BNXT_ULP_CLASS_HID_d692 = 0xd692,
+ BNXT_ULP_CLASS_HID_cbde = 0xcbde,
+ BNXT_ULP_CLASS_HID_ce1a = 0xce1a,
+ BNXT_ULP_CLASS_HID_ac8e = 0xac8e,
+ BNXT_ULP_CLASS_HID_de06 = 0xde06,
+ BNXT_ULP_CLASS_HID_f382 = 0xf382,
+ BNXT_ULP_CLASS_HID_ed1a = 0xed1a,
+ BNXT_ULP_CLASS_HID_9d6a = 0x9d6a,
+ BNXT_ULP_CLASS_HID_cee2 = 0xcee2,
+ BNXT_ULP_CLASS_HID_ec0e = 0xec0e,
+ BNXT_ULP_CLASS_HID_dd86 = 0xdd86,
+ BNXT_ULP_CLASS_HID_852e = 0x852e,
+ BNXT_ULP_CLASS_HID_b6a6 = 0xb6a6,
+ BNXT_ULP_CLASS_HID_eb82 = 0xeb82,
+ BNXT_ULP_CLASS_HID_c50a = 0xc50a,
+ BNXT_ULP_CLASS_HID_ccca = 0xccca,
+ BNXT_ULP_CLASS_HID_8706 = 0x8706,
+ BNXT_ULP_CLASS_HID_d38e = 0xd38e,
+ BNXT_ULP_CLASS_HID_d5ca = 0xd5ca,
+ BNXT_ULP_CLASS_HID_b48e = 0xb48e,
+ BNXT_ULP_CLASS_HID_8e8a = 0x8e8a,
+ BNXT_ULP_CLASS_HID_db02 = 0xdb02,
+ BNXT_ULP_CLASS_HID_dd8e = 0xdd8e,
+ BNXT_ULP_CLASS_HID_819a = 0x819a,
+ BNXT_ULP_CLASS_HID_b31a = 0xb31a,
+ BNXT_ULP_CLASS_HID_d03e = 0xd03e,
+ BNXT_ULP_CLASS_HID_c1be = 0xc1be,
+ BNXT_ULP_CLASS_HID_890e = 0x890e,
+ BNXT_ULP_CLASS_HID_ba8e = 0xba8e,
+ BNXT_ULP_CLASS_HID_dfaa = 0xdfaa,
+ BNXT_ULP_CLASS_HID_c93a = 0xc93a,
+ BNXT_ULP_CLASS_HID_b11a = 0xb11a,
+ BNXT_ULP_CLASS_HID_8b4e = 0x8b4e,
+ BNXT_ULP_CLASS_HID_c79e = 0xc79e,
+ BNXT_ULP_CLASS_HID_d9da = 0xd9da,
+ BNXT_ULP_CLASS_HID_b88e = 0xb88e,
+ BNXT_ULP_CLASS_HID_ea0e = 0xea0e,
+ BNXT_ULP_CLASS_HID_cf0a = 0xcf0a,
+ BNXT_ULP_CLASS_HID_c18e = 0xc18e,
+ BNXT_ULP_CLASS_HID_a94a = 0xa94a,
+ BNXT_ULP_CLASS_HID_daca = 0xdaca,
+ BNXT_ULP_CLASS_HID_ffee = 0xffee,
+ BNXT_ULP_CLASS_HID_e96e = 0xe96e,
+ BNXT_ULP_CLASS_HID_910e = 0x910e,
+ BNXT_ULP_CLASS_HID_c28e = 0xc28e,
+ BNXT_ULP_CLASS_HID_e7aa = 0xe7aa,
+ BNXT_ULP_CLASS_HID_d12a = 0xd12a,
+ BNXT_ULP_CLASS_HID_d8ca = 0xd8ca,
+ BNXT_ULP_CLASS_HID_930e = 0x930e,
+ BNXT_ULP_CLASS_HID_ef4e = 0xef4e,
+ BNXT_ULP_CLASS_HID_e18a = 0xe18a,
+ BNXT_ULP_CLASS_HID_c08e = 0xc08e,
+ BNXT_ULP_CLASS_HID_9a8a = 0x9a8a,
+ BNXT_ULP_CLASS_HID_d70a = 0xd70a,
+ BNXT_ULP_CLASS_HID_e90e = 0xe90e,
+ BNXT_ULP_CLASS_HID_edd9 = 0xedd9,
+ BNXT_ULP_CLASS_HID_a61d = 0xa61d,
+ BNXT_ULP_CLASS_HID_c571 = 0xc571,
+ BNXT_ULP_CLASS_HID_f4f9 = 0xf4f9,
+ BNXT_ULP_CLASS_HID_9c45 = 0x9c45,
+ BNXT_ULP_CLASS_HID_cfcd = 0xcfcd,
+ BNXT_ULP_CLASS_HID_ed21 = 0xed21,
+ BNXT_ULP_CLASS_HID_dca9 = 0xdca9,
+ BNXT_ULP_CLASS_HID_80b5 = 0x80b5,
+ BNXT_ULP_CLASS_HID_b235 = 0xb235,
+ BNXT_ULP_CLASS_HID_d111 = 0xd111,
+ BNXT_ULP_CLASS_HID_c091 = 0xc091,
+ BNXT_ULP_CLASS_HID_a865 = 0xa865,
+ BNXT_ULP_CLASS_HID_dbe5 = 0xdbe5,
+ BNXT_ULP_CLASS_HID_fec1 = 0xfec1,
+ BNXT_ULP_CLASS_HID_e841 = 0xe841,
+ BNXT_ULP_CLASS_HID_8e85 = 0x8e85,
+ BNXT_ULP_CLASS_HID_b80d = 0xb80d,
+ BNXT_ULP_CLASS_HID_df65 = 0xdf65,
+ BNXT_ULP_CLASS_HID_ceed = 0xceed,
+ BNXT_ULP_CLASS_HID_9645 = 0x9645,
+ BNXT_ULP_CLASS_HID_c1cd = 0xc1cd,
+ BNXT_ULP_CLASS_HID_e725 = 0xe725,
+ BNXT_ULP_CLASS_HID_d6ad = 0xd6ad,
+ BNXT_ULP_CLASS_HID_9aa5 = 0x9aa5,
+ BNXT_ULP_CLASS_HID_b425 = 0xb425,
+ BNXT_ULP_CLASS_HID_eb05 = 0xeb05,
+ BNXT_ULP_CLASS_HID_da85 = 0xda85,
+ BNXT_ULP_CLASS_HID_a265 = 0xa265,
+ BNXT_ULP_CLASS_HID_dde5 = 0xdde5,
+ BNXT_ULP_CLASS_HID_f0c5 = 0xf0c5,
+ BNXT_ULP_CLASS_HID_e245 = 0xe245,
+ BNXT_ULP_CLASS_HID_8b8f = 0x8b8f,
+ BNXT_ULP_CLASS_HID_a517 = 0xa517,
+ BNXT_ULP_CLASS_HID_d86b = 0xd86b,
+ BNXT_ULP_CLASS_HID_cbf3 = 0xcbf3,
+ BNXT_ULP_CLASS_HID_934f = 0x934f,
+ BNXT_ULP_CLASS_HID_c2c7 = 0xc2c7,
+ BNXT_ULP_CLASS_HID_e02b = 0xe02b,
+ BNXT_ULP_CLASS_HID_d3a3 = 0xd3a3,
+ BNXT_ULP_CLASS_HID_87a7 = 0x87a7,
+ BNXT_ULP_CLASS_HID_b137 = 0xb137,
+ BNXT_ULP_CLASS_HID_d403 = 0xd403,
+ BNXT_ULP_CLASS_HID_c793 = 0xc793,
+ BNXT_ULP_CLASS_HID_af67 = 0xaf67,
+ BNXT_ULP_CLASS_HID_dee7 = 0xdee7,
+ BNXT_ULP_CLASS_HID_fdc3 = 0xfdc3,
+ BNXT_ULP_CLASS_HID_ef43 = 0xef43,
+ BNXT_ULP_CLASS_HID_8dbf = 0x8dbf,
+ BNXT_ULP_CLASS_HID_bf07 = 0xbf07,
+ BNXT_ULP_CLASS_HID_d21f = 0xd21f,
+ BNXT_ULP_CLASS_HID_cde7 = 0xcde7,
+ BNXT_ULP_CLASS_HID_956f = 0x956f,
+ BNXT_ULP_CLASS_HID_c4c7 = 0xc4c7,
+ BNXT_ULP_CLASS_HID_fbcf = 0xfbcf,
+ BNXT_ULP_CLASS_HID_d5a7 = 0xd5a7,
+ BNXT_ULP_CLASS_HID_9957 = 0x9957,
+ BNXT_ULP_CLASS_HID_cb27 = 0xcb27,
+ BNXT_ULP_CLASS_HID_ee37 = 0xee37,
+ BNXT_ULP_CLASS_HID_d987 = 0xd987,
+ BNXT_ULP_CLASS_HID_a107 = 0xa107,
+ BNXT_ULP_CLASS_HID_d0e7 = 0xd0e7,
+ BNXT_ULP_CLASS_HID_f7e7 = 0xf7e7,
+ BNXT_ULP_CLASS_HID_c827 = 0xc827,
+ BNXT_ULP_CLASS_HID_f76a = 0xf76a,
+ BNXT_ULP_CLASS_HID_bcae = 0xbcae,
+ BNXT_ULP_CLASS_HID_dfc2 = 0xdfc2,
+ BNXT_ULP_CLASS_HID_ee4a = 0xee4a,
+ BNXT_ULP_CLASS_HID_cf26 = 0xcf26,
+ BNXT_ULP_CLASS_HID_b53a = 0xb53a,
+ BNXT_ULP_CLASS_HID_d79e = 0xd79e,
+ BNXT_ULP_CLASS_HID_e606 = 0xe606,
+ BNXT_ULP_CLASS_HID_be86 = 0xbe86,
+ BNXT_ULP_CLASS_HID_cd0e = 0xcd0e,
+ BNXT_ULP_CLASS_HID_d042 = 0xd042,
+ BNXT_ULP_CLASS_HID_d586 = 0xd586,
+ BNXT_ULP_CLASS_HID_b712 = 0xb712,
+ BNXT_ULP_CLASS_HID_c59a = 0xc59a,
+ BNXT_ULP_CLASS_HID_e81e = 0xe81e,
+ BNXT_ULP_CLASS_HID_f686 = 0xf686,
+ BNXT_ULP_CLASS_HID_86f6 = 0x86f6,
+ BNXT_ULP_CLASS_HID_d57e = 0xd57e,
+ BNXT_ULP_CLASS_HID_f792 = 0xf792,
+ BNXT_ULP_CLASS_HID_c61a = 0xc61a,
+ BNXT_ULP_CLASS_HID_9eb2 = 0x9eb2,
+ BNXT_ULP_CLASS_HID_ad3a = 0xad3a,
+ BNXT_ULP_CLASS_HID_f01e = 0xf01e,
+ BNXT_ULP_CLASS_HID_de96 = 0xde96,
+ BNXT_ULP_CLASS_HID_d756 = 0xd756,
+ BNXT_ULP_CLASS_HID_9c9a = 0x9c9a,
+ BNXT_ULP_CLASS_HID_c812 = 0xc812,
+ BNXT_ULP_CLASS_HID_ce56 = 0xce56,
+ BNXT_ULP_CLASS_HID_af12 = 0xaf12,
+ BNXT_ULP_CLASS_HID_9516 = 0x9516,
+ BNXT_ULP_CLASS_HID_c09e = 0xc09e,
+ BNXT_ULP_CLASS_HID_c612 = 0xc612,
+ BNXT_ULP_CLASS_HID_9a06 = 0x9a06,
+ BNXT_ULP_CLASS_HID_a886 = 0xa886,
+ BNXT_ULP_CLASS_HID_cba2 = 0xcba2,
+ BNXT_ULP_CLASS_HID_da22 = 0xda22,
+ BNXT_ULP_CLASS_HID_9292 = 0x9292,
+ BNXT_ULP_CLASS_HID_a112 = 0xa112,
+ BNXT_ULP_CLASS_HID_c436 = 0xc436,
+ BNXT_ULP_CLASS_HID_d2a6 = 0xd2a6,
+ BNXT_ULP_CLASS_HID_aa86 = 0xaa86,
+ BNXT_ULP_CLASS_HID_90d2 = 0x90d2,
+ BNXT_ULP_CLASS_HID_dc02 = 0xdc02,
+ BNXT_ULP_CLASS_HID_c246 = 0xc246,
+ BNXT_ULP_CLASS_HID_a312 = 0xa312,
+ BNXT_ULP_CLASS_HID_f192 = 0xf192,
+ BNXT_ULP_CLASS_HID_d496 = 0xd496,
+ BNXT_ULP_CLASS_HID_da12 = 0xda12,
+ BNXT_ULP_CLASS_HID_b2d6 = 0xb2d6,
+ BNXT_ULP_CLASS_HID_c156 = 0xc156,
+ BNXT_ULP_CLASS_HID_e472 = 0xe472,
+ BNXT_ULP_CLASS_HID_f2f2 = 0xf2f2,
+ BNXT_ULP_CLASS_HID_8a92 = 0x8a92,
+ BNXT_ULP_CLASS_HID_d912 = 0xd912,
+ BNXT_ULP_CLASS_HID_fc36 = 0xfc36,
+ BNXT_ULP_CLASS_HID_cab6 = 0xcab6,
+ BNXT_ULP_CLASS_HID_c356 = 0xc356,
+ BNXT_ULP_CLASS_HID_8892 = 0x8892,
+ BNXT_ULP_CLASS_HID_f4d2 = 0xf4d2,
+ BNXT_ULP_CLASS_HID_fa16 = 0xfa16,
+ BNXT_ULP_CLASS_HID_db12 = 0xdb12,
+ BNXT_ULP_CLASS_HID_8116 = 0x8116,
+ BNXT_ULP_CLASS_HID_cc96 = 0xcc96,
+ BNXT_ULP_CLASS_HID_f292 = 0xf292,
+ BNXT_ULP_CLASS_HID_e84d = 0xe84d,
+ BNXT_ULP_CLASS_HID_a389 = 0xa389,
+ BNXT_ULP_CLASS_HID_c0e5 = 0xc0e5,
+ BNXT_ULP_CLASS_HID_f16d = 0xf16d,
+ BNXT_ULP_CLASS_HID_99d1 = 0x99d1,
+ BNXT_ULP_CLASS_HID_ca59 = 0xca59,
+ BNXT_ULP_CLASS_HID_e8b5 = 0xe8b5,
+ BNXT_ULP_CLASS_HID_d93d = 0xd93d,
+ BNXT_ULP_CLASS_HID_8521 = 0x8521,
+ BNXT_ULP_CLASS_HID_b7a1 = 0xb7a1,
+ BNXT_ULP_CLASS_HID_d485 = 0xd485,
+ BNXT_ULP_CLASS_HID_c505 = 0xc505,
+ BNXT_ULP_CLASS_HID_adf1 = 0xadf1,
+ BNXT_ULP_CLASS_HID_de71 = 0xde71,
+ BNXT_ULP_CLASS_HID_fb55 = 0xfb55,
+ BNXT_ULP_CLASS_HID_edd5 = 0xedd5,
+ BNXT_ULP_CLASS_HID_8b11 = 0x8b11,
+ BNXT_ULP_CLASS_HID_bd99 = 0xbd99,
+ BNXT_ULP_CLASS_HID_daf1 = 0xdaf1,
+ BNXT_ULP_CLASS_HID_cb79 = 0xcb79,
+ BNXT_ULP_CLASS_HID_93d1 = 0x93d1,
+ BNXT_ULP_CLASS_HID_c459 = 0xc459,
+ BNXT_ULP_CLASS_HID_e2b1 = 0xe2b1,
+ BNXT_ULP_CLASS_HID_d339 = 0xd339,
+ BNXT_ULP_CLASS_HID_9f31 = 0x9f31,
+ BNXT_ULP_CLASS_HID_b1b1 = 0xb1b1,
+ BNXT_ULP_CLASS_HID_ee91 = 0xee91,
+ BNXT_ULP_CLASS_HID_df11 = 0xdf11,
+ BNXT_ULP_CLASS_HID_a7f1 = 0xa7f1,
+ BNXT_ULP_CLASS_HID_d871 = 0xd871,
+ BNXT_ULP_CLASS_HID_f551 = 0xf551,
+ BNXT_ULP_CLASS_HID_e7d1 = 0xe7d1,
+ BNXT_ULP_CLASS_HID_8e1b = 0x8e1b,
+ BNXT_ULP_CLASS_HID_a083 = 0xa083,
+ BNXT_ULP_CLASS_HID_ddff = 0xddff,
+ BNXT_ULP_CLASS_HID_ce67 = 0xce67,
+ BNXT_ULP_CLASS_HID_96db = 0x96db,
+ BNXT_ULP_CLASS_HID_c753 = 0xc753,
+ BNXT_ULP_CLASS_HID_e5bf = 0xe5bf,
+ BNXT_ULP_CLASS_HID_d637 = 0xd637,
+ BNXT_ULP_CLASS_HID_8233 = 0x8233,
+ BNXT_ULP_CLASS_HID_b4a3 = 0xb4a3,
+ BNXT_ULP_CLASS_HID_d197 = 0xd197,
+ BNXT_ULP_CLASS_HID_c207 = 0xc207,
+ BNXT_ULP_CLASS_HID_aaf3 = 0xaaf3,
+ BNXT_ULP_CLASS_HID_db73 = 0xdb73,
+ BNXT_ULP_CLASS_HID_f857 = 0xf857,
+ BNXT_ULP_CLASS_HID_ead7 = 0xead7,
+ BNXT_ULP_CLASS_HID_882b = 0x882b,
+ BNXT_ULP_CLASS_HID_ba93 = 0xba93,
+ BNXT_ULP_CLASS_HID_d78b = 0xd78b,
+ BNXT_ULP_CLASS_HID_c873 = 0xc873,
+ BNXT_ULP_CLASS_HID_90fb = 0x90fb,
+ BNXT_ULP_CLASS_HID_c153 = 0xc153,
+ BNXT_ULP_CLASS_HID_fe5b = 0xfe5b,
+ BNXT_ULP_CLASS_HID_d033 = 0xd033,
+ BNXT_ULP_CLASS_HID_9cc3 = 0x9cc3,
+ BNXT_ULP_CLASS_HID_ceb3 = 0xceb3,
+ BNXT_ULP_CLASS_HID_eba3 = 0xeba3,
+ BNXT_ULP_CLASS_HID_dc13 = 0xdc13,
+ BNXT_ULP_CLASS_HID_a493 = 0xa493,
+ BNXT_ULP_CLASS_HID_d573 = 0xd573,
+ BNXT_ULP_CLASS_HID_f273 = 0xf273,
+ BNXT_ULP_CLASS_HID_cdb3 = 0xcdb3,
+ BNXT_ULP_CLASS_HID_ff35 = 0xff35,
+ BNXT_ULP_CLASS_HID_b4f1 = 0xb4f1,
+ BNXT_ULP_CLASS_HID_d79d = 0xd79d,
+ BNXT_ULP_CLASS_HID_e615 = 0xe615,
+ BNXT_ULP_CLASS_HID_8ea9 = 0x8ea9,
+ BNXT_ULP_CLASS_HID_dd21 = 0xdd21,
+ BNXT_ULP_CLASS_HID_ffcd = 0xffcd,
+ BNXT_ULP_CLASS_HID_ce45 = 0xce45,
+ BNXT_ULP_CLASS_HID_9259 = 0x9259,
+ BNXT_ULP_CLASS_HID_a0d9 = 0xa0d9,
+ BNXT_ULP_CLASS_HID_c3fd = 0xc3fd,
+ BNXT_ULP_CLASS_HID_d27d = 0xd27d,
+ BNXT_ULP_CLASS_HID_ba89 = 0xba89,
+ BNXT_ULP_CLASS_HID_c909 = 0xc909,
+ BNXT_ULP_CLASS_HID_ec2d = 0xec2d,
+ BNXT_ULP_CLASS_HID_faad = 0xfaad,
BNXT_ULP_CLASS_HID_34c6 = 0x34c6,
BNXT_ULP_CLASS_HID_0c22 = 0x0c22,
BNXT_ULP_CLASS_HID_1cbe = 0x1cbe,
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h
index 1d7bbfe2cc..0a5c7e3d6e 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 20 11:56:39 2021 */
+/* date: Fri Aug 6 11:15:47 2021 */
#ifndef ULP_HDR_FIELD_ENUMS_H_
#define ULP_HDR_FIELD_ENUMS_H_
@@ -459,16 +459,14 @@ enum bnxt_ulp_hf_0_2_1_bitmask {
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC = 0x0000080000000000,
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC = 0x0000040000000000,
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_TYPE = 0x0000020000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_VER = 0x0000010000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_TOS = 0x0000008000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_LEN = 0x0000004000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_TTL = 0x0000000800000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_TC = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_FLOW_LABEL = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_PROTO_ID = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR = 0x0000000200000000
};
enum bnxt_ulp_hf_0_2_2_bitmask {
@@ -504,16 +502,7 @@ enum bnxt_ulp_hf_0_2_2_bitmask {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT = 0x0000000040000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT = 0x0000000020000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SENT_SEQ = 0x0000000010000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_RECV_ACK = 0x0000000008000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DATA_OFF = 0x0000000004000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_TCP_FLAGS = 0x0000000002000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_RX_WIN = 0x0000000001000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_CSUM = 0x0000000000800000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_URP = 0x0000000000400000
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000
};
enum bnxt_ulp_hf_0_2_3_bitmask {
@@ -540,20 +529,23 @@ enum bnxt_ulp_hf_0_2_3_bitmask {
BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC = 0x0000080000000000,
BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC = 0x0000040000000000,
BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_TYPE = 0x0000020000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_VER = 0x0000010000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_TOS = 0x0000008000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_LEN = 0x0000004000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_TTL = 0x0000000800000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT = 0x0000000040000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT = 0x0000000020000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_LENGTH = 0x0000000010000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_CSUM = 0x0000000008000000
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_TC = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_FLOW_LABEL = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_PROTO_ID = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SENT_SEQ = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_RECV_ACK = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DATA_OFF = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_TCP_FLAGS = 0x0000000008000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_RX_WIN = 0x0000000004000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_CSUM = 0x0000000002000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_URP = 0x0000000001000000
};
enum bnxt_ulp_hf_0_2_4_bitmask {
@@ -590,11 +582,134 @@ enum bnxt_ulp_hf_0_2_4_bitmask {
BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_TYPE = 0x0000000040000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_CODE = 0x0000000020000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_CSUM = 0x0000000010000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_IDENT = 0x0000000008000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_SEQ_NUM = 0x0000000004000000
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SENT_SEQ = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_RECV_ACK = 0x0000000008000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DATA_OFF = 0x0000000004000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_TCP_FLAGS = 0x0000000002000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_RX_WIN = 0x0000000001000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_CSUM = 0x0000000000800000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_URP = 0x0000000000400000
+};
+
+enum bnxt_ulp_hf_0_2_5_bitmask {
+ BNXT_ULP_HF_0_2_5_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_TC = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_FLOW_LABEL = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_PROTO_ID = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_LENGTH = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_CSUM = 0x0000000020000000
+};
+
+enum bnxt_ulp_hf_0_2_6_bitmask {
+ BNXT_ULP_HF_0_2_6_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_LENGTH = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_CSUM = 0x0000000008000000
+};
+
+enum bnxt_ulp_hf_0_2_7_bitmask {
+ BNXT_ULP_HF_0_2_7_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_TYPE = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_CODE = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_CSUM = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_IDENT = 0x0000000008000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_SEQ_NUM = 0x0000000004000000
};
enum bnxt_ulp_hf_0_3_0_bitmask {
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
index 3d1e95d18c..684fa66f48 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu Jul 8 08:44:00 2021 */
+/* date: Tue Aug 17 12:16:42 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -131,6 +131,46 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = {
.num_buckets = 8,
.hash_tbl_entries = 1024,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE << 1 |
+ BNXT_ULP_DIRECTION_INGRESS] = {
+ .name = "INGRESS GEN_TABLE_SOURCE_PROPERTY_CACHE",
+ .result_num_entries = 0,
+ .result_num_bytes = 6,
+ .key_num_bytes = 10,
+ .num_buckets = 4,
+ .hash_tbl_entries = 0,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE << 1 |
+ BNXT_ULP_DIRECTION_EGRESS] = {
+ .name = "INGRESS GEN_TABLE_SOURCE_PROPERTY_CACHE",
+ .result_num_entries = 128,
+ .result_num_bytes = 6,
+ .key_num_bytes = 10,
+ .num_buckets = 4,
+ .hash_tbl_entries = 512,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE << 1 |
+ BNXT_ULP_DIRECTION_INGRESS] = {
+ .name = "INGRESS GEN_TABLE_VXLAN_ENCAP_REC_CACHE",
+ .result_num_entries = 0,
+ .result_num_bytes = 6,
+ .key_num_bytes = 17,
+ .num_buckets = 8,
+ .hash_tbl_entries = 0,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE << 1 |
+ BNXT_ULP_DIRECTION_EGRESS] = {
+ .name = "INGRESS GEN_TABLE_VXLAN_ENCAP_REC_CACHE",
+ .result_num_entries = 256,
+ .result_num_bytes = 6,
+ .key_num_bytes = 17,
+ .num_buckets = 8,
+ .hash_tbl_entries = 1024,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
}
};
@@ -222,6 +262,7 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
.byte_count_shift = 0,
.packet_count_shift = 36,
.dynamic_pad_en = 0,
+ .dynamic_sram_en = 0,
.dev_tbls = ulp_template_wh_plus_tbls
},
[BNXT_ULP_DEVICE_ID_THOR] = {
@@ -246,12 +287,24 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
.byte_count_shift = 0,
.packet_count_shift = 35,
.dynamic_pad_en = 1,
+ .dynamic_sram_en = 1,
+ .dyn_encap_list_size = 4,
+ .dyn_encap_sizes = {{64, TF_TBL_TYPE_ACT_ENCAP_8B},
+ {128, TF_TBL_TYPE_ACT_ENCAP_16B},
+ {256, TF_TBL_TYPE_ACT_ENCAP_32B},
+ {512, TF_TBL_TYPE_ACT_ENCAP_64B}},
+ .dyn_modify_list_size = 4,
+ .dyn_modify_sizes = {{64, TF_TBL_TYPE_ACT_MODIFY_8B},
+ {128, TF_TBL_TYPE_ACT_MODIFY_16B},
+ {256, TF_TBL_TYPE_ACT_MODIFY_32B},
+ {512, TF_TBL_TYPE_ACT_MODIFY_64B}},
.em_blk_size_bits = 100,
.em_blk_align_bits = 128,
.em_key_align_bytes = 80,
.wc_slice_width = 160,
.wc_max_slices = 4,
- .wc_mode_list = {0x0000000c, 0x0000000e, 0x0000000f, 0x0000000f},
+ .wc_mode_list = {0x0000000c, 0x0000000e,
+ 0x0000000f, 0x0000000f},
.wc_mod_list_max_size = 4,
.wc_ctl_size_bits = 32,
.dev_tbls = ulp_template_thor_tbls
@@ -307,6 +360,16 @@ struct bnxt_ulp_app_capabilities_info ulp_app_cap_info_list[] = {
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.flags = BNXT_ULP_APP_CAP_SHARED_EN |
BNXT_ULP_APP_CAP_UNICAST_ONLY
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY
}
};
@@ -1279,333 +1342,1261 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = {
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
.direction = TF_DIR_TX
- }
-};
-
-/* List of tf resources required to be reserved per app/device */
-struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
+ },
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 422
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 6
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 191
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 63
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 192
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 8192
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 6912
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 1023
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 511
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 15
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
- .count = 255
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
- .count = 1
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 422
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 6
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 960
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 88
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
- .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 13168
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
- .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
- .count = 1
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 292
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 148
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 191
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 63
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 192
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 8192
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_6,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_7,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_6,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_7,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3,
+ .direction = TF_DIR_RX
+ }
+};
+
+/* List of tf resources required to be reserved per app/device */
+struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 422
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 191
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 6912
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 511
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 15
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
+ .count = 255
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 422
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 960
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 88
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 13168
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 292
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 148
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 191
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 6912
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 511
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 223
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 255
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 488
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
+ .count = 511
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 292
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 144
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 960
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 928
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 15232
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 272
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 31
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 64
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 64
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 272
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 128
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4096
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 16384
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 272
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 64
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 100
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 272
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 128
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4096
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 16384
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .count = 1
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 32
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 2
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 128
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 128
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 32
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 2
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 32
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 1024
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 32
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 2
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 128
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 6912
+ .count = 128
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 1023
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 511
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 223
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 255
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 488
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
- .count = 511
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
- .count = 1
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 292
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 144
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 960
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 928
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 15232
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
- .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
- .count = 1
+ .count = 1024
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 422
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 6
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1613,15 +2604,15 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 32
+ .count = 16
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1629,255 +2620,223 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 2048
- },
- {
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 512
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 528
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
- .count = 5
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 256
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 32
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 31
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 64
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 64
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 300
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 6
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 128
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 2048
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 13200
+ .count = 1024
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 26
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 26
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 32
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 63
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 32
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 1023
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_STATS_64,
.count = 512
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
- .count = 5
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 256
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 32
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 32
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 64
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 100
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
- .count = 32
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 200
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 110
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 128
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 2048
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 15232
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_METADATA,
- .count = 1
+ .count = 1024
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1885,7 +2844,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1893,7 +2852,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1901,7 +2860,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1909,7 +2868,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1917,7 +2876,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1925,7 +2884,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 128
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1933,7 +2892,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 128
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1941,7 +2900,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1949,7 +2908,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1957,7 +2916,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1965,7 +2924,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1973,7 +2932,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1981,7 +2940,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1989,15 +2948,15 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 64
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
@@ -2005,7 +2964,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 1024
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2013,7 +2972,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2021,7 +2980,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2029,7 +2988,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2037,7 +2996,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2045,7 +3004,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2053,7 +3012,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 128
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2061,7 +3020,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 128
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2069,7 +3028,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2077,7 +3036,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2085,7 +3044,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2093,7 +3052,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2101,7 +3060,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2109,7 +3068,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2117,7 +3076,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2125,7 +3084,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2133,7 +3092,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2141,7 +3100,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
@@ -2149,7 +3108,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 1024
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2157,7 +3116,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2165,7 +3124,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2173,7 +3132,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2181,7 +3140,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 16
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2189,7 +3148,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2197,7 +3156,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 528
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2205,7 +3164,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 256
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2213,7 +3172,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2221,7 +3180,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2229,7 +3188,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2237,7 +3196,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2245,7 +3204,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2253,7 +3212,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2261,15 +3220,15 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 512
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
@@ -2277,7 +3236,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 1024
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2285,7 +3244,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2293,7 +3252,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2301,7 +3260,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2309,7 +3268,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2317,7 +3276,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2325,7 +3284,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 512
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2333,7 +3292,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 256
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2341,7 +3300,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2349,7 +3308,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2357,7 +3316,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2365,7 +3324,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2373,7 +3332,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2381,7 +3340,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2389,7 +3348,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2397,7 +3356,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
@@ -2405,532 +3364,596 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 1024
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 422
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 191
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 63
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 192
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 128
+ .count = 8192
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 128
+ .count = 7168
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 4
+ .count = 1023
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 4
+ .count = 511
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 4
+ .count = 15
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
- .count = 4
+ .count = 255
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 422
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 960
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 64
+ .count = 88
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 13168
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 292
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 148
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 191
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 63
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 192
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 128
+ .count = 8192
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 128
+ .count = 7168
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 4
+ .count = 1023
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .count = 511
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 4
+ .count = 223
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 4
+ .count = 255
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .count = 488
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
- .count = 4
+ .count = 511
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 292
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 144
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 960
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 928
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 15232
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 16
+ .count = 63
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 528
+ .count = 4096
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 256
+ .count = 1024
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 4
+ .count = 32
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 4
+ .count = 32
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .count = 1024
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .count = 1024
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 1024
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 512
+ .count = 2048
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 6144
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 63
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 512
+ .count = 4096
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 256
+ .count = 1024
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 4
+ .count = 32
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 4
+ .count = 32
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .count = 1024
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .count = 1024
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 1024
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 2048
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 6144
}
};
@@ -3322,25 +4345,23 @@ uint8_t ulp_glb_field_tbl[] = {
[4229] = 21,
[4231] = 22,
[4244] = 2,
- [4245] = 23,
[4246] = 3,
- [4247] = 24,
[4248] = 4,
- [4249] = 25,
[4250] = 5,
- [4251] = 26,
[4252] = 6,
- [4253] = 27,
[4254] = 7,
- [4255] = 28,
[4256] = 8,
- [4257] = 29,
[4258] = 9,
- [4259] = 30,
[4260] = 10,
- [4261] = 31,
[4262] = 11,
- [4263] = 32,
+ [4265] = 23,
+ [4267] = 24,
+ [4269] = 25,
+ [4271] = 26,
+ [4273] = 27,
+ [4275] = 28,
+ [4277] = 29,
+ [4279] = 30,
[4298] = 12,
[4300] = 13,
[4302] = 14,
@@ -3374,15 +4395,6 @@ uint8_t ulp_glb_field_tbl[] = {
[4389] = 31,
[4390] = 11,
[4391] = 32,
- [4409] = 33,
- [4411] = 34,
- [4413] = 35,
- [4415] = 36,
- [4417] = 37,
- [4419] = 38,
- [4421] = 39,
- [4423] = 40,
- [4425] = 41,
[4426] = 12,
[4428] = 13,
[4430] = 14,
@@ -3397,33 +4409,36 @@ uint8_t ulp_glb_field_tbl[] = {
[4485] = 21,
[4487] = 22,
[4500] = 2,
- [4501] = 23,
[4502] = 3,
- [4503] = 24,
[4504] = 4,
- [4505] = 25,
[4506] = 5,
- [4507] = 26,
[4508] = 6,
- [4509] = 27,
[4510] = 7,
- [4511] = 28,
[4512] = 8,
- [4513] = 29,
[4514] = 9,
- [4515] = 30,
[4516] = 10,
- [4517] = 31,
[4518] = 11,
- [4519] = 32,
+ [4521] = 23,
+ [4523] = 24,
+ [4525] = 25,
+ [4527] = 26,
+ [4529] = 27,
+ [4531] = 28,
+ [4533] = 29,
+ [4535] = 30,
+ [4537] = 31,
+ [4539] = 32,
+ [4541] = 33,
+ [4543] = 34,
+ [4545] = 35,
+ [4547] = 36,
+ [4549] = 37,
+ [4551] = 38,
+ [4553] = 39,
[4554] = 12,
- [4555] = 33,
[4556] = 13,
- [4557] = 34,
[4558] = 14,
- [4559] = 35,
[4560] = 15,
- [4561] = 36,
[4574] = 16,
[4575] = 17,
[4576] = 18,
@@ -3433,11 +4448,6 @@ uint8_t ulp_glb_field_tbl[] = {
[4611] = 20,
[4613] = 21,
[4615] = 22,
- [4619] = 33,
- [4621] = 34,
- [4623] = 35,
- [4625] = 36,
- [4627] = 37,
[4628] = 2,
[4629] = 23,
[4630] = 3,
@@ -3458,6 +4468,15 @@ uint8_t ulp_glb_field_tbl[] = {
[4645] = 31,
[4646] = 11,
[4647] = 32,
+ [4665] = 33,
+ [4667] = 34,
+ [4669] = 35,
+ [4671] = 36,
+ [4673] = 37,
+ [4675] = 38,
+ [4677] = 39,
+ [4679] = 40,
+ [4681] = 41,
[4682] = 12,
[4684] = 13,
[4686] = 14,
@@ -3466,6 +4485,116 @@ uint8_t ulp_glb_field_tbl[] = {
[4703] = 17,
[4704] = 18,
[4705] = 19,
+ [4736] = 0,
+ [4737] = 1,
+ [4739] = 20,
+ [4741] = 21,
+ [4743] = 22,
+ [4756] = 2,
+ [4758] = 3,
+ [4760] = 4,
+ [4762] = 5,
+ [4764] = 6,
+ [4766] = 7,
+ [4768] = 8,
+ [4770] = 9,
+ [4772] = 10,
+ [4774] = 11,
+ [4777] = 23,
+ [4779] = 24,
+ [4781] = 25,
+ [4783] = 26,
+ [4785] = 27,
+ [4787] = 28,
+ [4789] = 29,
+ [4791] = 30,
+ [4810] = 12,
+ [4811] = 31,
+ [4812] = 13,
+ [4813] = 32,
+ [4814] = 14,
+ [4815] = 33,
+ [4816] = 15,
+ [4817] = 34,
+ [4830] = 16,
+ [4831] = 17,
+ [4832] = 18,
+ [4833] = 19,
+ [4864] = 0,
+ [4865] = 1,
+ [4867] = 20,
+ [4869] = 21,
+ [4871] = 22,
+ [4884] = 2,
+ [4885] = 23,
+ [4886] = 3,
+ [4887] = 24,
+ [4888] = 4,
+ [4889] = 25,
+ [4890] = 5,
+ [4891] = 26,
+ [4892] = 6,
+ [4893] = 27,
+ [4894] = 7,
+ [4895] = 28,
+ [4896] = 8,
+ [4897] = 29,
+ [4898] = 9,
+ [4899] = 30,
+ [4900] = 10,
+ [4901] = 31,
+ [4902] = 11,
+ [4903] = 32,
+ [4938] = 12,
+ [4939] = 33,
+ [4940] = 13,
+ [4941] = 34,
+ [4942] = 14,
+ [4943] = 35,
+ [4944] = 15,
+ [4945] = 36,
+ [4958] = 16,
+ [4959] = 17,
+ [4960] = 18,
+ [4961] = 19,
+ [4992] = 0,
+ [4993] = 1,
+ [4995] = 20,
+ [4997] = 21,
+ [4999] = 22,
+ [5003] = 33,
+ [5005] = 34,
+ [5007] = 35,
+ [5009] = 36,
+ [5011] = 37,
+ [5012] = 2,
+ [5013] = 23,
+ [5014] = 3,
+ [5015] = 24,
+ [5016] = 4,
+ [5017] = 25,
+ [5018] = 5,
+ [5019] = 26,
+ [5020] = 6,
+ [5021] = 27,
+ [5022] = 7,
+ [5023] = 28,
+ [5024] = 8,
+ [5025] = 29,
+ [5026] = 9,
+ [5027] = 30,
+ [5028] = 10,
+ [5029] = 31,
+ [5030] = 11,
+ [5031] = 32,
+ [5066] = 12,
+ [5068] = 13,
+ [5070] = 14,
+ [5072] = 15,
+ [5086] = 16,
+ [5087] = 17,
+ [5088] = 18,
+ [5089] = 19,
[6144] = 0,
[6145] = 1,
[6146] = 2,
@@ -3705,4 +4834,3 @@ uint8_t ulp_glb_field_tbl[] = {
[7638] = 6,
[7642] = 7
};
-
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
index 223ecbf843..e49c1151d3 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu Jul 8 08:44:00 2021 */
+/* date: Tue Aug 17 12:16:42 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -15,7 +15,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {
/* act_tid: 1, ingress */
[1] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 4,
+ .num_tbls = 5,
.start_tbl_idx = 0,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
@@ -26,7 +26,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {
[2] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
.num_tbls = 6,
- .start_tbl_idx = 4,
+ .start_tbl_idx = 5,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
.cond_start_idx = 3,
@@ -36,7 +36,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {
[3] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
.num_tbls = 4,
- .start_tbl_idx = 10,
+ .start_tbl_idx = 11,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
.cond_start_idx = 4,
@@ -45,8 +45,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {
/* act_tid: 4, egress */
[4] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 4,
- .start_tbl_idx = 14,
+ .num_tbls = 5,
+ .start_tbl_idx = 15,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
.cond_start_idx = 7,
@@ -56,20 +56,20 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {
[5] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
.num_tbls = 4,
- .start_tbl_idx = 18,
+ .start_tbl_idx = 20,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 10,
+ .cond_start_idx = 12,
.cond_nums = 0 }
},
/* act_tid: 6, egress */
[6] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 6,
- .start_tbl_idx = 22,
+ .num_tbls = 12,
+ .start_tbl_idx = 24,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 13,
+ .cond_start_idx = 15,
.cond_nums = 0 }
}
};
@@ -125,14 +125,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
+ .cond_false_goto = 2,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 2,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
.result_start_idx = 1,
.result_bit_size = 0,
.result_num_fields = 0,
@@ -146,7 +145,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 0,
- .cond_false_goto = 0,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 3,
.cond_nums = 0 },
@@ -158,6 +157,26 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.result_bit_size = 128,
.result_num_fields = 17
},
+ { /* act_tid: 1, , table: int_compact_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_COMPACT_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 3,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 65,
+ .result_bit_size = 64,
+ .result_num_fields = 13
+ },
{ /* act_tid: 2, , table: control.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
@@ -187,7 +206,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 65,
+ .result_start_idx = 78,
.result_bit_size = 32,
.result_num_fields = 5
},
@@ -208,13 +227,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 70,
+ .result_start_idx = 83,
.result_bit_size = 64,
.result_num_fields = 1
},
- { /* act_tid: 2, , table: int_full_act_record.0 */
+ { /* act_tid: 2, , table: int_compact_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_type = TF_TBL_TYPE_COMPACT_ACT_RECORD,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
.direction = TF_DIR_RX,
@@ -229,9 +248,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 71,
- .result_bit_size = 128,
- .result_num_fields = 17,
+ .result_start_idx = 84,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
.encap_num_fields = 0
},
{ /* act_tid: 2, , table: mirror_tbl.wr */
@@ -250,7 +269,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 88,
+ .result_start_idx = 97,
.result_bit_size = 32,
.result_num_fields = 5
},
@@ -273,7 +292,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.blob_key_bit_size = 1,
.key_bit_size = 1,
.key_num_fields = 1,
- .result_start_idx = 93,
+ .result_start_idx = 102,
.result_bit_size = 36,
.result_num_fields = 2
},
@@ -292,7 +311,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 95,
+ .result_start_idx = 104,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -311,8 +330,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 96,
+ .result_start_idx = 105,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 47
@@ -332,8 +350,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 143,
+ .result_start_idx = 152,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 47
@@ -353,7 +370,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 190,
+ .result_start_idx = 199,
.result_bit_size = 128,
.result_num_fields = 17
},
@@ -372,7 +389,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 207,
+ .result_start_idx = 216,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -391,8 +408,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 8,
- .result_start_idx = 208,
+ .result_start_idx = 217,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 11
@@ -412,8 +428,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 219,
+ .result_start_idx = 228,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 47
@@ -426,17 +441,36 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 0,
- .cond_false_goto = 0,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
.cond_start_idx = 10,
- .cond_nums = 0 },
+ .cond_nums = 2 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 266,
+ .result_start_idx = 275,
.result_bit_size = 128,
.result_num_fields = 17
},
+ { /* act_tid: 4, , table: int_compact_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_COMPACT_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 12,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 292,
+ .result_bit_size = 64,
+ .result_num_fields = 13
+ },
{ /* act_tid: 5, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
@@ -447,12 +481,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 10,
+ .cond_start_idx = 12,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 283,
+ .result_start_idx = 305,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -466,13 +500,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 2,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 11,
+ .cond_start_idx = 13,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 284,
+ .result_start_idx = 306,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 47
@@ -487,13 +520,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 12,
+ .cond_start_idx = 14,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 331,
+ .result_start_idx = 353,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 47
@@ -508,12 +540,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 13,
+ .cond_start_idx = 15,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 378,
+ .result_start_idx = 400,
.result_bit_size = 128,
.result_num_fields = 17
},
@@ -527,15 +559,48 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 13,
+ .cond_start_idx = 15,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 395,
+ .result_start_idx = 417,
.result_bit_size = 64,
.result_num_fields = 1
},
+ { /* act_tid: 6, , table: source_property_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 16,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2,
+ .blob_key_bit_size = 80,
+ .key_bit_size = 80,
+ .key_num_fields = 2,
+ .ident_start_idx = 1,
+ .ident_nums = 1
+ },
+ { /* act_tid: 6, , table: control.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 17,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
{ /* act_tid: 6, , table: sp_smac_ipv4.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
@@ -546,17 +611,40 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 14,
+ .cond_start_idx = 18,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
.record_size = 16,
- .result_start_idx = 396,
+ .result_start_idx = 418,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 3
},
+ { /* act_tid: 6, , table: source_property_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 19,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 4,
+ .blob_key_bit_size = 80,
+ .key_bit_size = 80,
+ .key_num_fields = 2,
+ .result_start_idx = 421,
+ .result_bit_size = 48,
+ .result_num_fields = 2
+ },
{ /* act_tid: 6, , table: sp_smac_ipv6.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
@@ -567,17 +655,50 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 15,
+ .cond_start_idx = 19,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.record_size = 32,
- .result_start_idx = 399,
+ .result_start_idx = 423,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 3
},
+ { /* act_tid: 6, , table: vxlan_encap_rec_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 20,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 6,
+ .blob_key_bit_size = 136,
+ .key_bit_size = 136,
+ .key_num_fields = 5,
+ .ident_start_idx = 2,
+ .ident_nums = 1
+ },
+ { /* act_tid: 6, , table: control.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 22,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
{ /* act_tid: 6, , table: int_tun_encap_record.ipv4_vxlan */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
@@ -588,17 +709,39 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 16,
+ .cond_start_idx = 23,
.cond_nums = 2 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 402,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .result_start_idx = 426,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 30
},
+ { /* act_tid: 6, , table: vxlan_encap_rec_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 25,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 11,
+ .blob_key_bit_size = 136,
+ .key_bit_size = 136,
+ .key_num_fields = 5,
+ .result_start_idx = 456,
+ .result_bit_size = 48,
+ .result_num_fields = 2
+ },
{ /* act_tid: 6, , table: int_tun_encap_record.ipv6_vxlan */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
@@ -609,13 +752,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 18,
+ .cond_start_idx = 25,
.cond_nums = 2 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 432,
+ .result_start_idx = 458,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 30
@@ -630,13 +772,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 20,
+ .cond_start_idx = 27,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 462,
+ .result_start_idx = 488,
.result_bit_size = 128,
.result_num_fields = 17
}
@@ -693,6 +835,15 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
.cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
},
+ /* cond_execute: act_tid: 4, int_full_act_record.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
+ },
/* cond_execute: act_tid: 5, int_flow_counter_tbl.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
@@ -713,6 +864,16 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
.cond_operand = BNXT_ULP_ACT_BIT_COUNT
},
+ /* cond_execute: act_tid: 6, source_property_cache.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG
+ },
+ /* cond_execute: act_tid: 6, control.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
/* cond_execute: act_tid: 6, sp_smac_ipv4.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
@@ -723,6 +884,20 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
.cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG
},
+ /* cond_execute: act_tid: 6, vxlan_encap_rec_cache.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: act_tid: 6, control.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
/* cond_execute: act_tid: 6, int_tun_encap_record.ipv4_vxlan */
{
.cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
@@ -783,6 +958,316 @@ struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = {
(BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
}
+ },
+ /* act_tid: 6, , table: source_property_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ipv4_src_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "ipv4_src_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}
+ }
+ },
+ /* act_tid: 6, , table: source_property_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ipv4_src_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "ipv4_src_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}
+ }
+ },
+ /* act_tid: 6, , table: vxlan_encap_rec_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ipv4_dst_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "ipv4_dst_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
+ }
+ },
+ /* act_tid: 6, , table: vxlan_encap_rec_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ipv4_dst_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "ipv4_dst_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
+ }
}
};
@@ -1069,38 +1554,178 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "encap_ptr",
- .field_bit_size = 16,
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr2 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_DECAP_FUNC_THRU_TUN},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_DECAP_FUNC_NONE}
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr2 = {
+ (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_RF,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr2 = {
- (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff},
+ ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER},
.field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd1",
- .field_bit_size = 16,
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 1, , table: int_compact_act_record.0 */
+ {
.description = "rsvd0",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
@@ -1137,7 +1762,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -1233,9 +1860,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "type",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
/* act_tid: 2, , table: mirror_tbl.alloc */
{
@@ -1277,31 +1902,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 2, , table: int_full_act_record.0 */
- {
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "encap_ptr",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "rsvd1",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
+ /* act_tid: 2, , table: int_compact_act_record.0 */
{
.description = "rsvd0",
.field_bit_size = 8,
@@ -1324,7 +1925,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -1387,9 +1990,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "type",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
/* act_tid: 2, , table: mirror_tbl.wr */
{
@@ -2250,7 +2851,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -2721,16 +3324,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
+ 1}
},
{
.description = "stats_ptr",
@@ -2803,6 +3399,102 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_opr1 = {
1}
},
+ /* act_tid: 4, , table: int_compact_act_record.0 */
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
/* act_tid: 5, , table: int_flow_counter_tbl.0 */
{
.description = "count",
@@ -3708,6 +4400,25 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* act_tid: 6, , table: source_property_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_SP_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_SP_PTR & 0xff}
+ },
/* act_tid: 6, , table: sp_smac_ipv6.0 */
{
.description = "smac",
@@ -4021,6 +4732,25 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
(BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff,
BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}
},
+ /* act_tid: 6, , table: vxlan_encap_rec_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "enc_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
+ },
/* act_tid: 6, , table: int_tun_encap_record.ipv6_vxlan */
{
.description = "ecv_valid",
@@ -4351,7 +5081,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -4424,5 +5156,19 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_act_ident_list[] = {
.regfile_idx = BNXT_ULP_RF_IDX_MIRROR_ID_0,
.ident_bit_size = 4,
.ident_bit_pos = 32
+ },
+ /* act_tid: 6, , table: source_property_cache.rd */
+ {
+ .description = "sp_rec_ptr",
+ .regfile_idx = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
+ .ident_bit_size = 16,
+ .ident_bit_pos = 32
+ },
+ /* act_tid: 6, , table: vxlan_encap_rec_cache.rd */
+ {
+ .description = "enc_rec_ptr",
+ .regfile_idx = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .ident_bit_size = 16,
+ .ident_bit_pos = 32
}
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
index bcb204ae13..68c1e292b2 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Fri Jul 30 09:57:44 2021 */
+/* date: Fri Aug 20 18:05:25 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -25,7 +25,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {
/* class_tid: 2, ingress */
[2] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 17,
+ .num_tbls = 24,
.start_tbl_idx = 28,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
@@ -35,18 +35,18 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {
/* class_tid: 3, egress */
[3] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 24,
- .start_tbl_idx = 45,
+ .num_tbls = 18,
+ .start_tbl_idx = 52,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 36,
+ .cond_start_idx = 39,
.cond_nums = 0 }
},
/* class_tid: 4, ingress */
[4] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
.num_tbls = 21,
- .start_tbl_idx = 69,
+ .start_tbl_idx = 70,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
.cond_start_idx = 48,
@@ -55,8 +55,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {
/* class_tid: 5, egress */
[5] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 24,
- .start_tbl_idx = 90,
+ .num_tbls = 25,
+ .start_tbl_idx = 91,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
.cond_start_idx = 52,
@@ -855,18 +855,28 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
+ { /* class_tid: 2, , table: control.ipv6_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 8,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 32,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_ipv6_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 32,
- .cond_nums = 0 },
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 33,
+ .cond_nums = 1 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
@@ -875,38 +885,57 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.key_bit_size = 14,
.key_num_fields = 3,
.ident_start_idx = 19,
- .ident_nums = 3
+ .ident_nums = 4
},
- { /* class_tid: 2, , table: control.profile_tcam_cache.f2_check */
+ { /* class_tid: 2, , table: control.f2_ipv6_prof_cache_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 4,
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 32,
+ .cond_start_idx = 34,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 2, , table: fkb_select.f2_wm */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
+ { /* class_tid: 2, , table: control.f2_v6_conflict_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
+ .cond_true_goto = 4,
+ .cond_false_goto = 1023,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 33,
+ .cond_start_idx = 35,
.cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
- .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .func_info = {
+ .func_opc = BNXT_ULP_FUNC_OPC_EQ,
+ .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
+ .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
+ .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
+ },
+ { /* class_tid: 2, , table: fkb_select.f2_l2_l3_l4_v6_em */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 36,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
.result_start_idx = 426,
.result_bit_size = 106,
.result_num_fields = 106
},
- { /* class_tid: 2, , table: profile_tcam.f2 */
+ { /* class_tid: 2, , table: profile_tcam.f2_l2_l3_l4_v6_em */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.direction = TF_DIR_RX,
@@ -914,14 +943,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 34,
+ .cond_start_idx = 36,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
- .pri_operand = 1,
+ .pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.key_start_idx = 1146,
@@ -930,9 +959,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.key_num_fields = 43,
.result_start_idx = 532,
.result_bit_size = 33,
- .result_num_fields = 8
+ .result_num_fields = 8,
+ .ident_start_idx = 23,
+ .ident_nums = 1
},
- { /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_l2_l3_l4_v6_wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
@@ -942,7 +973,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 34,
+ .cond_start_idx = 36,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
@@ -955,135 +986,81 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 138,
.result_num_fields = 7
},
- { /* class_tid: 2, , table: wm.l3_l4.ipv4 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ { /* class_tid: 2, , table: em.f2_l2_l3_l4_v6.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_INTERNAL,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 0,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 34,
- .cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 36,
+ .cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
- .pri_operand = 0,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.key_start_idx = 1192,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
.result_start_idx = 547,
- .result_bit_size = 38,
- .result_num_fields = 5
- },
- { /* class_tid: 2, , table: wm.l3_l4.ipv6 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 0,
- .cond_false_goto = 0,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 35,
- .cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
- .pri_operand = 0,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1306,
- .blob_key_bit_size = 0,
- .key_bit_size = 0,
- .key_num_fields = 114,
- .result_start_idx = 552,
- .result_bit_size = 38,
- .result_num_fields = 5
- },
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 6,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 36,
- .cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1420,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .ident_start_idx = 22,
- .ident_nums = 1
+ .result_bit_size = 0,
+ .result_num_fields = 6
},
- { /* class_tid: 3, , table: mac_addr_cache.rd */
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 37,
+ .cond_start_idx = 36,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1421,
- .blob_key_bit_size = 73,
- .key_bit_size = 73,
- .key_num_fields = 5,
- .ident_start_idx = 23,
- .ident_nums = 1
+ .key_start_idx = 1306,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .ident_start_idx = 24,
+ .ident_nums = 3
},
- { /* class_tid: 3, , table: control.0 */
+ { /* class_tid: 2, , table: control.profile_tcam_cache.f2_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 4,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 37,
+ .cond_start_idx = 36,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 3, , table: port_table.egr.rd */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
- .direction = TF_DIR_TX,
+ { /* class_tid: 2, , table: fkb_select.f2_wm */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 38,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 37,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .key_start_idx = 1426,
- .blob_key_bit_size = 10,
- .key_bit_size = 10,
- .key_num_fields = 1,
- .ident_start_idx = 24,
- .ident_nums = 3
+ .result_start_idx = 553,
+ .result_bit_size = 106,
+ .result_num_fields = 106
},
- { /* class_tid: 3, , table: l2_cntxt_tcam.0 */
+ { /* class_tid: 2, , table: profile_tcam.f2 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .direction = TF_DIR_TX,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
@@ -1091,26 +1068,27 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_start_idx = 38,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
- .pri_operand = 0,
- .key_start_idx = 1427,
- .blob_key_bit_size = 213,
- .key_bit_size = 213,
- .key_num_fields = 21,
- .result_start_idx = 557,
- .result_bit_size = 43,
- .result_num_fields = 6,
- .ident_start_idx = 27,
- .ident_nums = 1
+ .pri_operand = 1,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 1309,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 659,
+ .result_bit_size = 33,
+ .result_num_fields = 8
},
- { /* class_tid: 3, , table: mac_addr_cache.wr */
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
@@ -1118,15 +1096,61 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_start_idx = 38,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1448,
- .blob_key_bit_size = 73,
- .key_bit_size = 73,
- .key_num_fields = 5,
- .result_start_idx = 563,
- .result_bit_size = 62,
- .result_num_fields = 4
+ .key_start_idx = 1352,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .result_start_idx = 667,
+ .result_bit_size = 138,
+ .result_num_fields = 7
+ },
+ { /* class_tid: 2, , table: wm.l3_l4.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 38,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 1355,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 674,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 39,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1469,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 27,
+ .ident_nums = 1
},
{ /* class_tid: 3, , table: control.ipv6_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
@@ -1135,7 +1159,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 8,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 38,
+ .cond_start_idx = 39,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
@@ -1148,12 +1172,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1023,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 39,
+ .cond_start_idx = 40,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1453,
+ .key_start_idx = 1470,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -1167,7 +1191,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 2,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 40,
+ .cond_start_idx = 41,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
@@ -1179,7 +1203,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 4,
.cond_false_goto = 1023,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 41,
+ .cond_start_idx = 42,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.func_info = {
@@ -1198,13 +1222,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .result_start_idx = 567,
+ .result_start_idx = 679,
.result_bit_size = 106,
.result_num_fields = 106
},
@@ -1216,7 +1240,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
@@ -1226,11 +1250,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 1456,
+ .key_start_idx = 1473,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
- .result_start_idx = 673,
+ .result_start_idx = 785,
.result_bit_size = 33,
.result_num_fields = 8,
.ident_start_idx = 32,
@@ -1246,16 +1270,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1499,
+ .key_start_idx = 1516,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
- .result_start_idx = 681,
+ .result_start_idx = 793,
.result_bit_size = 138,
.result_num_fields = 7
},
@@ -1267,15 +1291,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1502,
+ .key_start_idx = 1519,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
- .result_start_idx = 688,
+ .result_start_idx = 800,
.result_bit_size = 0,
.result_num_fields = 6
},
@@ -1288,12 +1312,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1616,
+ .key_start_idx = 1633,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -1304,32 +1328,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 2,
- .cond_false_goto = 1,
+ .cond_true_goto = 1,
+ .cond_false_goto = 5,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 3, , table: control.conflict_check */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 5,
- .cond_false_goto = 1023,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 43,
- .cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .func_info = {
- .func_opc = BNXT_ULP_FUNC_OPC_EQ,
- .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
- .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
- .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
- .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
- .func_dst_opr = BNXT_ULP_RF_IDX_CC }
- },
{ /* class_tid: 3, , table: fkb_select.l3_l4_wc */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
@@ -1343,7 +1349,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 694,
+ .result_start_idx = 806,
.result_bit_size = 106,
.result_num_fields = 106
},
@@ -1365,11 +1371,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 1619,
+ .key_start_idx = 1636,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
- .result_start_idx = 800,
+ .result_start_idx = 912,
.result_bit_size = 33,
.result_num_fields = 8,
.ident_start_idx = 35,
@@ -1393,11 +1399,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 1662,
+ .key_start_idx = 1679,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
- .result_start_idx = 808,
+ .result_start_idx = 920,
.result_bit_size = 33,
.result_num_fields = 8,
.ident_start_idx = 35,
@@ -1418,11 +1424,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1705,
+ .key_start_idx = 1722,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
- .result_start_idx = 816,
+ .result_start_idx = 928,
.result_bit_size = 138,
.result_num_fields = 7
},
@@ -1443,11 +1449,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1708,
+ .key_start_idx = 1725,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
- .result_start_idx = 823,
+ .result_start_idx = 935,
.result_bit_size = 38,
.result_num_fields = 5
},
@@ -1468,11 +1474,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1822,
+ .key_start_idx = 1839,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
- .result_start_idx = 828,
+ .result_start_idx = 940,
.result_bit_size = 38,
.result_num_fields = 5
},
@@ -1493,11 +1499,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1936,
+ .key_start_idx = 1953,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
- .result_start_idx = 833,
+ .result_start_idx = 945,
.result_bit_size = 38,
.result_num_fields = 5
},
@@ -1517,7 +1523,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 838,
+ .result_start_idx = 950,
.result_bit_size = 128,
.result_num_fields = 17
},
@@ -1535,11 +1541,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2050,
+ .key_start_idx = 2067,
.blob_key_bit_size = 10,
.key_bit_size = 10,
.key_num_fields = 1,
- .result_start_idx = 855,
+ .result_start_idx = 967,
.result_bit_size = 152,
.result_num_fields = 5
},
@@ -1557,7 +1563,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2051,
+ .key_start_idx = 2068,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1594,11 +1600,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 2052,
+ .key_start_idx = 2069,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
- .result_start_idx = 860,
+ .result_start_idx = 972,
.result_bit_size = 43,
.result_num_fields = 6,
.ident_start_idx = 35,
@@ -1618,11 +1624,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2073,
+ .key_start_idx = 2090,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .result_start_idx = 866,
+ .result_start_idx = 978,
.result_bit_size = 62,
.result_num_fields = 4
},
@@ -1639,7 +1645,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 870,
+ .result_start_idx = 982,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -1656,7 +1662,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 871,
+ .result_start_idx = 983,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -1676,7 +1682,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 872,
+ .result_start_idx = 984,
.result_bit_size = 128,
.result_num_fields = 17,
.encap_num_fields = 0
@@ -1695,11 +1701,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2074,
+ .key_start_idx = 2091,
.blob_key_bit_size = 10,
.key_bit_size = 10,
.key_num_fields = 1,
- .result_start_idx = 889,
+ .result_start_idx = 1001,
.result_bit_size = 152,
.result_num_fields = 5
},
@@ -1728,7 +1734,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2075,
+ .key_start_idx = 2092,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1761,7 +1767,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .result_start_idx = 894,
+ .result_start_idx = 1006,
.result_bit_size = 64,
.result_num_fields = 8
},
@@ -1779,11 +1785,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2076,
+ .key_start_idx = 2093,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .result_start_idx = 902,
+ .result_start_idx = 1014,
.result_bit_size = 62,
.result_num_fields = 4
},
@@ -1801,7 +1807,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2077,
+ .key_start_idx = 2094,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1836,11 +1842,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 2078,
+ .key_start_idx = 2095,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
- .result_start_idx = 906,
+ .result_start_idx = 1018,
.result_bit_size = 43,
.result_num_fields = 6,
.ident_start_idx = 36,
@@ -1860,11 +1866,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2099,
+ .key_start_idx = 2116,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .result_start_idx = 912,
+ .result_start_idx = 1024,
.result_bit_size = 62,
.result_num_fields = 4
},
@@ -1881,7 +1887,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 916,
+ .result_start_idx = 1028,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -1898,7 +1904,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 917,
+ .result_start_idx = 1029,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -1918,11 +1924,33 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 918,
+ .result_start_idx = 1030,
.result_bit_size = 128,
.result_num_fields = 17,
.encap_num_fields = 0
},
+ { /* class_tid: 5, , table: port_table.egr_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2117,
+ .blob_key_bit_size = 10,
+ .key_bit_size = 10,
+ .key_num_fields = 1,
+ .result_start_idx = 1047,
+ .result_bit_size = 152,
+ .result_num_fields = 5
+ },
{ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
@@ -1937,7 +1965,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2100,
+ .key_start_idx = 2118,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1972,11 +2000,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .key_start_idx = 2101,
+ .key_start_idx = 2119,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
- .result_start_idx = 935,
+ .result_start_idx = 1052,
.result_bit_size = 43,
.result_num_fields = 6,
.ident_start_idx = 37,
@@ -1996,11 +2024,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2122,
+ .key_start_idx = 2140,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .result_start_idx = 941,
+ .result_start_idx = 1058,
.result_bit_size = 62,
.result_num_fields = 4
},
@@ -2017,7 +2045,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 945,
+ .result_start_idx = 1062,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -2034,7 +2062,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 946,
+ .result_start_idx = 1063,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -2054,7 +2082,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
- .result_start_idx = 947,
+ .result_start_idx = 1064,
.result_bit_size = 128,
.result_num_fields = 17,
.encap_num_fields = 0
@@ -2072,7 +2100,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_SVIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 964,
+ .result_start_idx = 1081,
.result_bit_size = 64,
.result_num_fields = 8
},
@@ -2091,7 +2119,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2123,
+ .key_start_idx = 2141,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -2124,7 +2152,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .result_start_idx = 972,
+ .result_start_idx = 1089,
.result_bit_size = 64,
.result_num_fields = 8
},
@@ -2142,11 +2170,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2124,
+ .key_start_idx = 2142,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .result_start_idx = 980,
+ .result_start_idx = 1097,
.result_bit_size = 62,
.result_num_fields = 4
},
@@ -2165,7 +2193,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 984,
+ .result_start_idx = 1101,
.result_bit_size = 16,
.result_num_fields = 1
},
@@ -2184,8 +2212,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 985,
+ .result_start_idx = 1102,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 47
@@ -2206,7 +2233,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 1032,
+ .result_start_idx = 1149,
.result_bit_size = 128,
.result_num_fields = 17
},
@@ -2224,7 +2251,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2125,
+ .key_start_idx = 2143,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -2261,11 +2288,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 2126,
+ .key_start_idx = 2144,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
- .result_start_idx = 1049,
+ .result_start_idx = 1166,
.result_bit_size = 43,
.result_num_fields = 6,
.ident_start_idx = 38,
@@ -2284,7 +2311,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 1055,
+ .result_start_idx = 1172,
.result_bit_size = 106,
.result_num_fields = 106
},
@@ -2306,11 +2333,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 2147,
+ .key_start_idx = 2165,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
- .result_start_idx = 1161,
+ .result_start_idx = 1278,
.result_bit_size = 33,
.result_num_fields = 8
},
@@ -2325,15 +2352,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 55,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2190,
+ .key_start_idx = 2208,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .ident_start_idx = 38,
- .ident_nums = 1
+ .result_start_idx = 1286,
+ .result_bit_size = 62,
+ .result_num_fields = 4
},
{ /* class_tid: 5, , table: int_full_act_record.vfr_ing0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2351,7 +2379,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 1169,
+ .result_start_idx = 1290,
.result_bit_size = 128,
.result_num_fields = 17
},
@@ -2367,11 +2395,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 2191,
+ .key_start_idx = 2209,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
- .result_start_idx = 1186,
+ .result_start_idx = 1307,
.result_bit_size = 0,
.result_num_fields = 6
}
@@ -2529,6 +2557,26 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
+ /* cond_execute: class_tid: 2, control.ipv6_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6
+ },
+ /* cond_execute: class_tid: 2, profile_tcam_cache.f2_ipv6_rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH
+ },
+ /* cond_execute: class_tid: 2, control.f2_ipv6_prof_cache_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 2, control.f2_v6_conflict_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_CC
+ },
/* cond_execute: class_tid: 2, control.profile_tcam_cache.f2_check */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
@@ -2544,21 +2592,6 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
},
- /* cond_execute: class_tid: 2, wm.l3_l4.ipv6 */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
- .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
- },
- /* cond_execute: class_tid: 3, l2_cntxt_tcam_cache.rd */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET,
- .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC
- },
- /* cond_execute: class_tid: 3, control.0 */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
- .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
- },
/* cond_execute: class_tid: 3, control.ipv6_check */
{
.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
@@ -2584,11 +2617,6 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 3, control.conflict_check */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
- .cond_operand = BNXT_ULP_RF_IDX_CC
- },
/* cond_execute: class_tid: 3, profile_tcam.l3_l4.ip */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
@@ -5115,12 +5143,24 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -8346,7 +8386,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr1 = {
(BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
@@ -8373,7 +8416,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr1 = {
(BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
@@ -15050,7 +15096,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr1 = {
(BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
@@ -15077,7 +15126,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr1 = {
(BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
@@ -16551,7 +16603,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr1 = {
(BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
@@ -16578,7 +16633,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr1 = {
(BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
@@ -18283,7 +18341,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
- /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_ipv6_rd */
{
.field_info_mask = {
.description = "recycle_cnt",
@@ -18338,7 +18396,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
}
},
- /* class_tid: 2, , table: profile_tcam.f2 */
+ /* class_tid: 2, , table: profile_tcam.f2_l2_l3_l4_v6_em */
{
.field_info_mask = {
.description = "l4_hdr_is_udp_tcp",
@@ -18357,14 +18415,34 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l4_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l4_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_I_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_UDP}
}
},
{
@@ -18372,7 +18450,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l4_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4 & 0xff}
},
.field_info_spec = {
.description = "l4_hdr_error",
@@ -18386,13 +18467,19 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l4_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4 & 0xff}
},
.field_info_spec = {
.description = "l4_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4 & 0xff}
}
},
{
@@ -18456,13 +18543,17 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l3_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
.description = "l3_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
}
},
{
@@ -18470,7 +18561,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l3_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
.description = "l3_hdr_error",
@@ -18484,13 +18577,17 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
.description = "l3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
}
},
{
@@ -18526,7 +18623,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l2_uc_mc_bc",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
.description = "l2_uc_mc_bc",
@@ -18990,15 +19089,13 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
1}
}
},
- /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_l2_l3_l4_v6_wr */
{
.field_info_mask = {
.description = "recycle_cnt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "recycle_cnt",
@@ -19045,10 +19142,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
}
},
- /* class_tid: 2, , table: wm.l3_l4.ipv4 */
+ /* class_tid: 2, , table: em.f2_l2_l3_l4_v6.0 */
{
.field_info_mask = {
- .description = "wc_profile_id",
+ .description = "em_profile_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
@@ -19056,13 +19153,13 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "wc_profile_id",
+ .description = "em_profile_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 & 0xff}
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
}
},
{
@@ -19401,20 +19498,12 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "tl3.dip.ipv4",
.field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
.description = "tl3.dip.ipv4",
.field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
@@ -19766,7 +19855,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr2 = {
(BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
.field_info_spec = {
.description = "tids",
@@ -19780,7 +19869,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr2 = {
(BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -19879,12 +19968,30 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
.field_info_spec = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -20059,12 +20166,30 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.sip.ipv6",
.field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
.field_info_spec = {
.description = "l3.sip.ipv6",
.field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -20083,42 +20208,42 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.dip.ipv4",
.field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
.description = "l3.dip.ipv4",
.field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
.description = "l3.dip.ipv6",
.field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
.field_info_spec = {
.description = "l3.dip.ipv6",
.field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -20149,12 +20274,24 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -20341,24 +20478,50 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l4.src",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
.description = "l4.src",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
.field_info_mask = {
.description = "l4.dst",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
.description = "l4.dst",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -20481,2254 +20644,2585 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
- /* class_tid: 2, , table: wm.l3_l4.ipv6 */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
{
.field_info_mask = {
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 & 0xff}
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
}
},
+ /* class_tid: 2, , table: profile_tcam.f2 */
{
.field_info_mask = {
- .description = "parif",
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "parif",
+ .description = "l4_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "lcos",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "lcos",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "meta",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "meta",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "rcyc_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "rcyc_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "loopback",
+ .description = "l3_hdr_isIP",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "loopback",
+ .description = "l3_hdr_isIP",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_l2type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_l2type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl2_dt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_dt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_sa",
+ .description = "l2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_sa",
+ .description = "l2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_nvt",
+ .description = "l2_uc_mc_bc",
.field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_nvt",
+ .description = "l2_uc_mc_bc",
.field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ovp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovd",
+ .description = "l2_hdr_error",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ovd",
+ .description = "l2_hdr_error",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ovv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L2_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl2_ovt",
+ .description = "tun_hdr_flags",
.field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovt",
+ .description = "tun_hdr_flags",
.field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ivp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivd",
+ .description = "tun_hdr_err",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ivd",
+ .description = "tun_hdr_err",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl2_ivv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ivv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ivt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl2_etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.l3type",
+ .description = "tl4_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.l3type",
+ .description = "tl4_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL4_HDR_TYPE_UDP}
}
},
{
.field_info_mask = {
- .description = "tl3.sip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.sip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.sip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.sip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL4_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl3.sip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.sip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.dip.ipv4",
- .field_bit_size = 32,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.dip.ipv4",
- .field_bit_size = 32,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.dip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.dip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.dip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.dip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl3.fid.ipv4",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.fid.ipv4",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl3.fid.ipv6",
- .field_bit_size = 20,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.fid.ipv6",
- .field_bit_size = 20,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl3.qos",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.qos",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl3.ieh_nonext",
+ .description = "tl3_hdr_error",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.ieh_nonext",
+ .description = "tl3_hdr_error",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_esp",
+ .description = "tl3_hdr_valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.ieh_esp",
+ .description = "tl3_hdr_valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL3_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_auth",
+ .description = "tl2_two_vtags",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.ieh_auth",
+ .description = "tl2_two_vtags",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_dest",
+ .description = "tl2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.ieh_dest",
+ .description = "tl2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_hop",
+ .description = "tl2_hdr_valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.ieh_hop",
+ .description = "tl2_hdr_valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL2_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_1frag",
+ .description = "hrec_next",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.ieh_1frag",
+ .description = "hrec_next",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl3.l3err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.l3err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
.field_info_spec = {
- .description = "tl4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
}
},
+ /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
{
.field_info_mask = {
- .description = "tl4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
}
},
+ /* class_tid: 2, , table: wm.l3_l4.ipv4 */
{
.field_info_mask = {
- .description = "tl4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "tl4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
}
},
{
.field_info_mask = {
- .description = "tuntype",
+ .description = "parif",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tuntype",
+ .description = "parif",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tflags",
- .field_bit_size = 3,
+ .description = "spif",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tflags",
- .field_bit_size = 3,
+ .description = "spif",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tids",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tids",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "tid",
- .field_bit_size = 32,
+ .description = "svif",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tid",
- .field_bit_size = 32,
+ .description = "svif",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tctxts",
- .field_bit_size = 24,
+ .description = "lcos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tctxts",
- .field_bit_size = 24,
+ .description = "lcos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tctxt",
- .field_bit_size = 32,
+ .description = "meta",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tctxt",
- .field_bit_size = 32,
+ .description = "meta",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tqos",
- .field_bit_size = 3,
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tqos",
- .field_bit_size = 3,
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "terr",
- .field_bit_size = 4,
+ .description = "loopback",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "terr",
- .field_bit_size = 4,
+ .description = "loopback",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_l2type",
+ .description = "tl2_l2type",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_l2type",
+ .description = "tl2_l2type",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_dmac",
+ .description = "tl2_dmac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_dmac",
+ .description = "tl2_dmac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_smac",
+ .description = "tl2_smac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_smac",
+ .description = "tl2_smac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_dt",
+ .description = "tl2_dt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_dt",
+ .description = "tl2_dt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_sa",
+ .description = "tl2_sa",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_sa",
+ .description = "tl2_sa",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_nvt",
+ .description = "tl2_nvt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_nvt",
+ .description = "tl2_nvt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovp",
+ .description = "tl2_ovp",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovp",
+ .description = "tl2_ovp",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovd",
+ .description = "tl2_ovd",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovd",
+ .description = "tl2_ovd",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovv",
+ .description = "tl2_ovv",
.field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovv",
+ .description = "tl2_ovv",
.field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovt",
+ .description = "tl2_ovt",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovt",
+ .description = "tl2_ovt",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivp",
+ .description = "tl2_ivp",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivp",
+ .description = "tl2_ivp",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivd",
+ .description = "tl2_ivd",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivd",
+ .description = "tl2_ivd",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivv",
+ .description = "tl2_ivv",
.field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivv",
+ .description = "tl2_ivv",
.field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivt",
+ .description = "tl2_ivt",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivt",
+ .description = "tl2_ivt",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_etype",
+ .description = "tl2_etype",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_etype",
+ .description = "tl2_etype",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.l3type",
+ .description = "tl3.l3type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.l3type",
+ .description = "tl3.l3type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.sip.ipv4",
+ .description = "tl3.sip.ipv4",
.field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.sip.ipv4",
+ .description = "tl3.sip.ipv4",
.field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.sip.ipv6",
+ .description = "tl3.sip.ipv6",
.field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.sip.ipv6",
+ .description = "tl3.sip.ipv6",
.field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.sip_selcmp.ipv6",
+ .description = "tl3.sip_selcmp.ipv6",
.field_bit_size = 72,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.sip_selcmp.ipv6",
+ .description = "tl3.sip_selcmp.ipv6",
.field_bit_size = 72,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.dip.ipv4",
+ .description = "tl3.dip.ipv4",
.field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.dip.ipv4",
+ .description = "tl3.dip.ipv4",
.field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.dip.ipv6",
+ .description = "tl3.dip.ipv6",
.field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.dip.ipv6",
+ .description = "tl3.dip.ipv6",
.field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.dip_selcmp.ipv6",
+ .description = "tl3.dip_selcmp.ipv6",
.field_bit_size = 72,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.dip_selcmp.ipv6",
+ .description = "tl3.dip_selcmp.ipv6",
.field_bit_size = 72,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ttl",
+ .description = "tl3.ttl",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ttl",
+ .description = "tl3.ttl",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.prot",
+ .description = "tl3.prot",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.prot",
+ .description = "tl3.prot",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.fid.ipv4",
+ .description = "tl3.fid.ipv4",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.fid.ipv4",
+ .description = "tl3.fid.ipv4",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.fid.ipv6",
+ .description = "tl3.fid.ipv6",
.field_bit_size = 20,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.fid.ipv6",
+ .description = "tl3.fid.ipv6",
.field_bit_size = 20,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.qos",
+ .description = "tl3.qos",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.qos",
+ .description = "tl3.qos",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_nonext",
+ .description = "tl3.ieh_nonext",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_nonext",
+ .description = "tl3.ieh_nonext",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_esp",
+ .description = "tl3.ieh_esp",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_esp",
+ .description = "tl3.ieh_esp",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_auth",
+ .description = "tl3.ieh_auth",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_auth",
+ .description = "tl3.ieh_auth",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_dest",
+ .description = "tl3.ieh_dest",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_dest",
+ .description = "tl3.ieh_dest",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_frag",
+ .description = "tl3.ieh_frag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_frag",
+ .description = "tl3.ieh_frag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_rthdr",
+ .description = "tl3.ieh_rthdr",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_rthdr",
+ .description = "tl3.ieh_rthdr",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_hop",
+ .description = "tl3.ieh_hop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_hop",
+ .description = "tl3.ieh_hop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_1frag",
+ .description = "tl3.ieh_1frag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_1frag",
+ .description = "tl3.ieh_1frag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.df",
+ .description = "tl3.df",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.df",
+ .description = "tl3.df",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.l3err.ipv4",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.l3err.ipv4",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "l3.l3err.ipv6",
+ .description = "tl3.l3err",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.l3err.ipv6",
+ .description = "tl3.l3err",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.l4type",
+ .description = "tl4.l4type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.l4type",
+ .description = "tl4.l4type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.src",
+ .description = "tl4.src",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.src",
+ .description = "tl4.src",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.dst",
+ .description = "tl4.dst",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.dst",
+ .description = "tl4.dst",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.flags",
+ .description = "tl4.flags",
.field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.flags",
+ .description = "tl4.flags",
.field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.seq",
+ .description = "tl4.seq",
.field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.seq",
+ .description = "tl4.seq",
.field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.ack",
- .field_bit_size = 32,
+ .description = "tl4.pa",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.ack",
- .field_bit_size = 32,
+ .description = "tl4.pa",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.win",
- .field_bit_size = 16,
+ .description = "tl4.opt",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.win",
- .field_bit_size = 16,
+ .description = "tl4.opt",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.pa",
+ .description = "tl4.tcpts",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.pa",
+ .description = "tl4.tcpts",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.opt",
- .field_bit_size = 1,
+ .description = "tl4.err",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.opt",
- .field_bit_size = 1,
+ .description = "tl4.err",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.tcpts",
- .field_bit_size = 1,
+ .description = "tuntype",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.tcpts",
- .field_bit_size = 1,
+ .description = "tuntype",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.tsval",
- .field_bit_size = 32,
+ .description = "tflags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.tsval",
- .field_bit_size = 32,
+ .description = "tflags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.txecr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l4.txecr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4.err",
- .field_bit_size = 4,
+ .description = "tid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.err",
- .field_bit_size = 4,
+ .description = "tid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
- /* class_tid: 3, , table: mac_addr_cache.rd */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "mac_addr",
+ .description = "l2_dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "mac_addr",
+ .description = "l2_dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
}
},
- /* class_tid: 3, , table: port_table.egr.rd */
{
.field_info_mask = {
- .description = "dev.port_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- 0xff,
- 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "dev.port_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam.0 */
{
.field_info_mask = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_tpid_sel",
+ .description = "l2_ovp",
.field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovlan_tpid_sel",
+ .description = "l2_ovp",
.field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- }
- },
- {
- .field_info_mask = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
- /* class_tid: 3, , table: mac_addr_cache.wr */
{
.field_info_mask = {
- .description = "svif",
+ .description = "l3.ttl",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "svif",
+ .description = "l3.ttl",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ (BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ (BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
- /* class_tid: 3, , table: profile_tcam_cache.ipv6_rd */
{
.field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
- /* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */
{
.field_info_mask = {
- .description = "l4_hdr_is_udp_tcp",
+ .description = "l3.ieh_dest",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4_hdr_is_udp_tcp",
+ .description = "l3.ieh_dest",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_THOR_SYM_L4_HDR_TYPE_TCP},
- .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr3 = {
- ULP_THOR_SYM_L4_HDR_TYPE_UDP}
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4_hdr_error",
+ .description = "l3.ieh_rthdr",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4_hdr_error",
+ .description = "l3.ieh_rthdr",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4_hdr_valid",
+ .description = "l3.ieh_hop",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4_hdr_valid",
+ .description = "l3.ieh_hop",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "ieh",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "ieh",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3_ipv6_cmp_dst",
+ .description = "l3.df",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3_ipv6_cmp_dst",
+ .description = "l3.df",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3_hdr_type",
+ .description = "l4.l4type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3_hdr_type",
+ .description = "l4.l4type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 0xff}
+ (BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 0xff}
+ (BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ULP_THOR_SYM_L3_HDR_VALID_YES}
+ (BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_vtag_present",
- .field_bit_size = 1,
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam_cache.ipv6_rd */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_UDP}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
.field_opr1 = {
@@ -23114,17 +23608,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_spec = {
.description = "prof_func_id",
.field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
@@ -23230,17 +23716,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_spec = {
.description = "prof_func_id",
.field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
@@ -24082,12 +24560,30 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
.field_info_spec = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -24388,12 +24884,24 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -24773,17 +25281,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_spec = {
.description = "prof_func_id",
.field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
@@ -25425,17 +25925,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_spec = {
.description = "prof_func_id",
.field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
@@ -26095,17 +26587,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_spec = {
.description = "prof_func_id",
.field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
@@ -26211,17 +26695,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_spec = {
.description = "prof_func_id",
.field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
@@ -27063,12 +27539,30 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -27349,12 +27843,27 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -27542,47 +28051,29 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l4.src",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
.field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l4.src",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
.field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -27590,47 +28081,29 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l4.dst",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
.field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l4.dst",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
.field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -28571,12 +29044,30 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -28857,12 +29348,27 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -30011,12 +30517,30 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -30285,12 +30809,14 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -31393,227 +31919,11 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
}
},
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
- {
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
- }
- },
- /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
- {
- .field_info_mask = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
+ /* class_tid: 5, , table: port_table.egr_wr */
{
.field_info_mask = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
+ .description = "dev.port_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
@@ -31621,104 +31931,16 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
+ .description = "dev.port_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
- }
- },
- {
- .field_info_mask = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- .field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
}
},
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
{
.field_info_mask = {
.description = "svif",
@@ -31738,67 +31960,392 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
}
},
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.rd_egr0 */
- {
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
- }
- },
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
- {
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
- }
- },
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_rd_vfr */
- {
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
- }
- },
- /* class_tid: 5, , table: l2_cntxt_tcam.vfr_ing0 */
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.rd_egr0 */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_rd_vfr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam.vfr_ing0 */
{
.field_info_mask = {
.description = "etype",
@@ -33860,332 +34407,1091 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
}
},
{
- .field_info_mask = {
- .description = "l3.ieh_auth",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_auth",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ }
+};
+
+struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
+ /* class_tid: 1, , table: l2_cntxt_tcam.0 */
+ {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ },
+ {
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ },
+ {
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ },
+ /* class_tid: 1, , table: mac_addr_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: fkb_select.l2_l3_l4_v6_em */
+ {
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "parif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "spif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "lcos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "loopback.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tuntype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tflags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tqos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "terr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ },
+ {
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ },
+ {
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ },
+ {
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}
+ },
+ {
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.l3err.ipv4",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.l3err.ipv4",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}
},
{
- .field_info_mask = {
- .description = "l3.l3err.ipv6",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.l3err.ipv6",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}
},
{
- .field_info_mask = {
- .description = "l4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_win.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.ack",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.ack",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.win",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.win",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */
{
- .field_info_mask = {
- .description = "l4.tsval",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.tsval",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.txecr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.txecr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- }
-};
-
-struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
- /* class_tid: 1, , table: l2_cntxt_tcam.0 */
- {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "em_key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "em_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "em_search_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ 1}
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: mac_addr_cache.wr */
+ /* class_tid: 1, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -34196,27 +35502,98 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "l2_cntxt_tcam_index",
+ .description = "profile_tcam_index",
.field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "wc_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ },
+ /* class_tid: 1, , table: em.l2_l3_l4_v6.0 */
+ {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: fkb_select.l2_l3_l4_v6_em */
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: fkb_select.l3_l4_wm */
{
.description = "l2_cntxt_id.en",
.field_bit_size = 1,
@@ -34589,10 +35966,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ 1}
},
{
.description = "l2_dt.en",
@@ -34651,22 +36027,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
{
.description = "l2_ivv.en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ 1}
},
{
.description = "l2_ivt.en",
@@ -34690,10 +36054,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ 1}
},
{
.description = "l3_sip_selcmp.en",
@@ -34705,10 +36068,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ 1}
},
{
.description = "l3_dip_selcmp.en",
@@ -34726,7 +36088,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l3_fid.en",
@@ -34810,19 +36174,17 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}
+ 1}
},
{
.description = "l4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}
+ 1}
},
{
.description = "l4_flags.en",
@@ -34884,166 +36246,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */
- {
- .description = "wc_key_id",
- .field_bit_size = 6,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "wc_search_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "em_key_type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "em_key_id",
- .field_bit_size = 6,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
- },
- {
- .description = "em_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
- },
- {
- .description = "em_search_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- {
- .description = "pl_byp_lkup_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- /* class_tid: 1, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
- {
- .description = "rid",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
- },
- {
- .description = "profile_tcam_index",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
- },
- {
- .description = "em_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
- },
- {
- .description = "em_key_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
- },
- {
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "wc_key_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "flow_sig_id",
- .field_bit_size = 64,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
- },
- /* class_tid: 1, , table: em.l2_l3_l4_v6.0 */
- {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- {
- .description = "strength",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 3}
- },
- {
- .description = "data",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
- },
- {
- .description = "opcode",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "meta_prof",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "ctxt_data",
- .field_bit_size = 14,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- /* class_tid: 1, , table: fkb_select.l3_l4_wm */
+ /* class_tid: 1, , table: fkb_select.l3_l4_wm_vxlan */
{
.description = "l2_cntxt_id.en",
.field_bit_size = 1,
@@ -35170,7 +36373,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl2_ivv.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl2_ivt.en",
@@ -35194,7 +36399,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl3_sip_selcmp.en",
@@ -35206,7 +36413,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl3_dip_selcmp.en",
@@ -35224,7 +36433,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl3_fid.en",
@@ -35308,13 +36519,17 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl4_flags.en",
@@ -35478,9 +36693,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_ivv.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l2_ivt.en",
@@ -35504,9 +36717,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l3_sip_selcmp.en",
@@ -35518,9 +36729,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l3_dip_selcmp.en",
@@ -35538,9 +36747,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l3_fid.en",
@@ -35624,17 +36831,13 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l4_flags.en",
@@ -35696,9 +36899,112 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: fkb_select.l3_l4_wm_vxlan */
+ /* class_tid: 1, , table: profile_tcam.l3_l4.ip */
{
- .description = "l2_cntxt_id.en",
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.l3_l4.vxlan */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 & 0xff}
+ },
+ {
+ .description = "wc_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -35706,1131 +37012,1203 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
1}
},
{
- .description = "parif.en",
- .field_bit_size = 1,
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "spif.en",
- .field_bit_size = 1,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "svif.en",
+ .description = "em_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "lcos.en",
+ .description = "pl_byp_lkup_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 1, , table: profile_tcam_cache.wr */
{
- .description = "meta.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "rcyc_cnt.en",
- .field_bit_size = 1,
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
},
{
- .description = "loopback.en",
- .field_bit_size = 1,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_l2type.en",
- .field_bit_size = 1,
+ .description = "em_key_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_dmac.en",
- .field_bit_size = 1,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_smac.en",
- .field_bit_size = 1,
+ .description = "wc_key_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_dt.en",
- .field_bit_size = 1,
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
+ /* class_tid: 1, , table: wm.l3_l4.ipv4 */
{
- .description = "tl2_sa.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_nvt.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovp.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovd.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl2_ovv.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 1, , table: wm.l3_l4.ipv6 */
{
- .description = "tl2_ovt.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivp.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivd.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivv.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 1, , table: wm.l3.ipv4 */
{
- .description = "tl2_ivt.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_etype.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_l3type.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_sip.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 1, , table: wm.l3.ipv6 */
{
- .description = "tl3_sip_selcmp.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_dip.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_dip_selcmp.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ttl.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl3_prot.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 1, , table: wm.l2 */
{
- .description = "tl3_fid.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_qos.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_nonext.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_esp.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl3_ieh_auth.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv4 */
{
- .description = "tl3_ieh_dest.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_frag.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_rthdr.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_hop.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl3_ieh_1frag.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv6 */
{
- .description = "tl3_df.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_l3err.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_l4type.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_src.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl4_dst.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
{
- .description = "tl4_flags.en",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_seq.en",
- .field_bit_size = 1,
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_pa.en",
- .field_bit_size = 1,
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_opt.en",
- .field_bit_size = 1,
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_tcpts.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_err.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 2, , table: tunnel_cache.wr */
{
- .description = "tuntype.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "tflags.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tids.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
+ /* class_tid: 2, , table: l2_cntxt_tcam.0 */
{
- .description = "tid.en",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
},
{
- .description = "tctxts.en",
- .field_bit_size = 1,
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tctxt.en",
- .field_bit_size = 1,
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
{
- .description = "tqos.en",
- .field_bit_size = 1,
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
},
{
- .description = "terr.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .description = "l2_l2type.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
},
+ /* class_tid: 2, , table: mac_addr_cache.wr */
{
- .description = "l2_dmac.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_smac.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 2, , table: fkb_select.f2_l2_l3_l4_v6_em */
{
- .description = "l2_dt.en",
+ .description = "l2_cntxt_id.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "l2_sa.en",
+ .description = "parif.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_nvt.en",
+ .description = "spif.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovp.en",
+ .description = "svif.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovd.en",
+ .description = "lcos.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovv.en",
+ .description = "meta.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovt.en",
+ .description = "rcyc_cnt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivp.en",
+ .description = "loopback.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivd.en",
+ .description = "tl2_l2type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivv.en",
+ .description = "tl2_dmac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivt.en",
+ .description = "tl2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_etype.en",
+ .description = "tl2_dt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_l3type.en",
+ .description = "tl2_sa.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_sip.en",
+ .description = "tl2_nvt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_sip_selcmp.en",
+ .description = "tl2_ovp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip.en",
+ .description = "tl2_ovd.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip_selcmp.en",
+ .description = "tl2_ovv.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ttl.en",
+ .description = "tl2_ovt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_prot.en",
+ .description = "tl2_ivp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_fid.en",
+ .description = "tl2_ivd.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_qos.en",
+ .description = "tl2_ivv.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_nonext.en",
+ .description = "tl2_ivt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_esp.en",
+ .description = "tl2_etype.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_auth.en",
+ .description = "tl3_l3type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_dest.en",
+ .description = "tl3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_frag.en",
+ .description = "tl3_sip_selcmp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_rthdr.en",
+ .description = "tl3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_hop.en",
+ .description = "tl3_dip_selcmp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_1frag.en",
+ .description = "tl3_ttl.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_df.en",
+ .description = "tl3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_l3err.en",
+ .description = "tl3_fid.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_l4type.en",
+ .description = "tl3_qos.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_src.en",
+ .description = "tl3_ieh_nonext.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_dst.en",
+ .description = "tl3_ieh_esp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_flags.en",
+ .description = "tl3_ieh_auth.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_seq.en",
+ .description = "tl3_ieh_dest.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_ack.en",
+ .description = "tl3_ieh_frag.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_win.en",
+ .description = "tl3_ieh_rthdr.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_pa.en",
+ .description = "tl3_ieh_hop.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_opt.en",
+ .description = "tl3_ieh_1frag.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_tcpts.en",
+ .description = "tl3_df.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_tsval.en",
+ .description = "tl3_l3err.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_txecr.en",
+ .description = "tl4_l4type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_err.en",
+ .description = "tl4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam.l3_l4.ip */
{
- .description = "wc_key_id",
- .field_bit_size = 6,
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_search_en",
+ .description = "tl4_seq.en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_type",
- .field_bit_size = 2,
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 6,
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_search_en",
+ .description = "tl4_err.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "pl_byp_lkup_en",
+ .description = "tuntype.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam.l3_l4.vxlan */
{
- .description = "wc_key_id",
- .field_bit_size = 6,
+ .description = "tflags.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 & 0xff}
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}
},
{
- .description = "wc_search_en",
+ .description = "tid.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_type",
- .field_bit_size = 2,
+ .description = "tctxts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 6,
+ .description = "tctxt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "tqos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_search_en",
+ .description = "terr.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "pl_byp_lkup_en",
+ .description = "l2_l2type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam_cache.wr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ 1}
},
{
- .description = "profile_tcam_index",
- .field_bit_size = 10,
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 8,
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_key_id",
- .field_bit_size = 8,
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "flow_sig_id",
- .field_bit_size = 64,
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l3_l4.ipv4 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l3_l4.ipv6 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}
},
- /* class_tid: 1, , table: wm.l3.ipv4 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff}
+ },
+ {
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l3.ipv6 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l2 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l3_df.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ (BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff}
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff}
},
- /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv4 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l4_win.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv6 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l4_err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: l2_cntxt_tcam.1 */
+ /* class_tid: 2, , table: profile_tcam.f2_l2_l3_l4_v6_em */
{
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "wc_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "wc_search_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "em_key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "em_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: tunnel_cache.wr */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_l2_l3_l4_v6_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -36841,99 +38219,94 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "l2_cntxt_tcam_index",
+ .description = "profile_tcam_index",
.field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
},
- /* class_tid: 2, , table: l2_cntxt_tcam.0 */
{
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "em_key_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "wc_key_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
+ /* class_tid: 2, , table: em.f2_l2_l3_l4_v6.0 */
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ 1}
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ 3}
},
- /* class_tid: 2, , table: mac_addr_cache.wr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "l2_cntxt_tcam_index",
- .field_bit_size = 10,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -37100,9 +38473,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "tl3_dip_selcmp.en",
@@ -37316,7 +38687,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l2_dt.en",
@@ -37400,7 +38773,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l3_sip_selcmp.en",
@@ -37432,7 +38807,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l3_fid.en",
@@ -37516,13 +38893,17 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l4_flags.en",
@@ -37743,127 +39124,6 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 2, , table: wm.l3_l4.ipv6 */
- {
- .description = "ctxt_data",
- .field_bit_size = 14,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "meta_prof",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "opcode",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "data",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
- },
- {
- .description = "strength",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- /* class_tid: 3, , table: l2_cntxt_tcam.0 */
- {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}
- },
- {
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "def_ctxt_data",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
- },
- {
- .description = "ctxt_opcode",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
- },
- {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
- },
- {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
- },
- /* class_tid: 3, , table: mac_addr_cache.wr */
- {
- .description = "rid",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
- },
- {
- .description = "l2_cntxt_tcam_index",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
- },
- {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
- },
- {
- .description = "src_property_ptr",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
/* class_tid: 3, , table: fkb_select.l2_l3_l4_v6_em */
{
.description = "l2_cntxt_id.en",
@@ -38240,7 +39500,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
},
{
.description = "l2_dt.en",
@@ -38374,7 +39637,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}
},
{
.description = "l3_fid.en",
@@ -39066,7 +40332,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l2_dt.en",
@@ -39186,7 +40454,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l3_fid.en",
@@ -39663,7 +40933,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -39910,7 +41182,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -40050,7 +41324,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "parif",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
},
{
.description = "reserved",
@@ -40238,7 +41515,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -40299,6 +41578,43 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
+ /* class_tid: 5, , table: port_table.egr_wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drv_func.mac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drv_func.parent.mac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff}
+ },
+ {
+ .description = "phy_port",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "default_arec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
+ },
/* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
{
.description = "prof_func_id",
@@ -40450,7 +41766,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -40610,7 +41928,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "parif",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
},
{
.description = "reserved",
@@ -40970,7 +42291,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -41772,6 +43095,34 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_wr_vfr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
/* class_tid: 5, , table: int_full_act_record.vfr_ing0 */
{
.description = "sp_rec_ptr",
@@ -41819,7 +43170,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -42058,7 +43411,13 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 42
},
- /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_ipv6_rd */
+ {
+ .description = "em_key_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_KEY_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 50
+ },
{
.description = "em_profile_id",
.regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
@@ -42077,47 +43436,40 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 32
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ /* class_tid: 2, , table: profile_tcam.f2_l2_l3_l4_v6_em */
{
- .description = "l2_cntxt_id",
- .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
- .ident_bit_size = 10,
- .ident_bit_pos = 42
+ .description = "em_profile_id",
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_EM_PROF,
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 23
},
- /* class_tid: 3, , table: mac_addr_cache.rd */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
{
- .description = "l2_cntxt_id",
- .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
- .ident_bit_size = 10,
+ .description = "em_profile_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
.ident_bit_pos = 42
},
- /* class_tid: 3, , table: port_table.egr.rd */
- {
- .description = "default_arec_ptr",
- .regfile_idx = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
- .ident_bit_size = 16,
- .ident_bit_pos = 136
- },
{
- .description = "drv_func.parent.mac",
- .regfile_idx = BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC,
- .ident_bit_size = 48,
- .ident_bit_pos = 80
+ .description = "flow_sig_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .ident_bit_size = 64,
+ .ident_bit_pos = 74
},
{
- .description = "phy_port",
- .regfile_idx = BNXT_ULP_RF_IDX_PHY_PORT,
- .ident_bit_size = 8,
- .ident_bit_pos = 128
+ .description = "profile_tcam_index",
+ .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
},
- /* class_tid: 3, , table: l2_cntxt_tcam.0 */
+ /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
{
.description = "l2_cntxt_id",
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
- .ident_bit_pos = 29
+ .ident_bit_pos = 42
},
/* class_tid: 3, , table: profile_tcam_cache.ipv6_rd */
{
@@ -42168,36 +43520,29 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
},
/* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
- .description = "l2_cntxt_id",
+ .description = "l2_cntxt_id_low",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 29
},
/* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
- .description = "l2_cntxt_id",
+ .description = "l2_cntxt_id_low",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 29
},
/* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
{
- .description = "l2_cntxt_id",
+ .description = "l2_cntxt_id_low",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 29
- },
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_wr_vfr */
- {
- .description = "rid",
- .regfile_idx = BNXT_ULP_RF_IDX_RID,
- .ident_bit_size = 32,
- .ident_bit_pos = 0
}
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
index 2870a0615a..4b9cb7fd5b 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Wed Jun 30 14:36:16 2021 */
+/* date: Wed Aug 11 16:00:16 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -16741,27 +16741,27 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
},
/* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
- .description = "l2_cntxt_id",
+ .description = "l2_cntxt_id_low",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 0
},
/* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
- .description = "l2_cntxt_id",
+ .description = "l2_cntxt_id_low",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 0
},
/* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
{
- .description = "l2_cntxt_id",
+ .description = "l2_cntxt_id_low",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 0
diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
index c6b2b1675d..7b6db7a0f8 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
@@ -75,9 +75,9 @@ ulp_mapper_generic_tbl_list_init(struct bnxt_ulp_mapper_data *mapper_data)
entry->container.byte_data = &entry->mem_data[size];
entry->container.byte_order = tbl->result_byte_order;
} else {
- BNXT_TF_DBG(ERR, "%s:Invalid gen table num of ent %d\n",
+ BNXT_TF_DBG(DEBUG, "%s: Unused Gen tbl entry is %d\n",
tbl->name, idx);
- return -EINVAL;
+ /* return -EINVAL; */
}
if (tbl->hash_tbl_entries) {
cparams.key_size = tbl->key_num_bytes;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 234f7ea2fa..059ee99837 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -438,6 +438,77 @@ ulp_mapper_ident_fields_get(struct bnxt_ulp_mapper_parms *mparms,
return &dev_tbls->ident_list[idx];
}
+static enum tf_tbl_type
+ulp_mapper_dyn_tbl_type_get(struct bnxt_ulp_mapper_parms *mparms,
+ struct bnxt_ulp_mapper_tbl_info *tbl,
+ struct ulp_blob *bdata,
+ uint16_t *out_len)
+{
+ struct bnxt_ulp_device_params *d_params = mparms->device_params;
+ uint16_t blob_len = ulp_blob_data_len_get(bdata);
+ struct bnxt_ulp_dyn_size_map *size_map;
+ uint32_t i;
+
+ if (d_params->dynamic_sram_en) {
+ switch (tbl->resource_type) {
+ case TF_TBL_TYPE_ACT_ENCAP_8B:
+ case TF_TBL_TYPE_ACT_ENCAP_16B:
+ case TF_TBL_TYPE_ACT_ENCAP_32B:
+ case TF_TBL_TYPE_ACT_ENCAP_64B:
+ size_map = d_params->dyn_encap_sizes;
+ for (i = 0; i < d_params->dyn_encap_list_size; i++) {
+ if (blob_len <= size_map[i].slab_size) {
+ *out_len = size_map[i].slab_size;
+ return size_map[i].tbl_type;
+ }
+ }
+ break;
+ case TF_TBL_TYPE_ACT_MODIFY_8B:
+ case TF_TBL_TYPE_ACT_MODIFY_16B:
+ case TF_TBL_TYPE_ACT_MODIFY_32B:
+ case TF_TBL_TYPE_ACT_MODIFY_64B:
+ size_map = d_params->dyn_modify_sizes;
+ for (i = 0; i < d_params->dyn_modify_list_size; i++) {
+ if (blob_len <= size_map[i].slab_size) {
+ *out_len = size_map[i].slab_size;
+ return size_map[i].tbl_type;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ }
+ return tbl->resource_type;
+}
+
+static uint16_t
+ulp_mapper_dyn_blob_size_get(struct bnxt_ulp_mapper_parms *mparms,
+ struct bnxt_ulp_mapper_tbl_info *tbl)
+{
+ struct bnxt_ulp_device_params *d_params = mparms->device_params;
+
+ if (d_params->dynamic_sram_en) {
+ switch (tbl->resource_type) {
+ case TF_TBL_TYPE_ACT_ENCAP_8B:
+ case TF_TBL_TYPE_ACT_ENCAP_16B:
+ case TF_TBL_TYPE_ACT_ENCAP_32B:
+ case TF_TBL_TYPE_ACT_ENCAP_64B:
+ case TF_TBL_TYPE_ACT_MODIFY_8B:
+ case TF_TBL_TYPE_ACT_MODIFY_16B:
+ case TF_TBL_TYPE_ACT_MODIFY_32B:
+ case TF_TBL_TYPE_ACT_MODIFY_64B:
+ /* return max size */
+ return BNXT_ULP_FLMP_BLOB_SIZE_IN_BITS;
+ default:
+ break;
+ }
+ } else if (tbl->encap_num_fields) {
+ return BNXT_ULP_FLMP_BLOB_SIZE_IN_BITS;
+ }
+ return tbl->result_bit_size;
+}
+
static inline int32_t
ulp_mapper_tcam_entry_free(struct bnxt_ulp_context *ulp,
struct tf *tfp,
@@ -1562,7 +1633,8 @@ ulp_mapper_tbl_result_build(struct bnxt_ulp_mapper_parms *parms,
if (encap_flds) {
uint32_t pad = 0;
/* Initialize the encap blob */
- if (!tbl->record_size) {
+ if (!tbl->record_size &&
+ !parms->device_params->dynamic_sram_en) {
BNXT_TF_DBG(ERR, "Encap tbl record size incorrect\n");
return -EINVAL;
}
@@ -1583,9 +1655,21 @@ ulp_mapper_tbl_result_build(struct bnxt_ulp_mapper_parms *parms,
}
}
/* add the dynamic pad push */
- pad = ULP_BYTE_2_BITS(tbl->record_size) -
- ulp_blob_data_len_get(&encap_blob);
- ulp_blob_pad_push(&encap_blob, pad);
+ if (parms->device_params->dynamic_sram_en) {
+ uint16_t rec_s = ULP_BYTE_2_BITS(tbl->record_size);
+
+ (void)ulp_mapper_dyn_tbl_type_get(parms, tbl,
+ &encap_blob, &rec_s);
+ pad = rec_s - ulp_blob_data_len_get(&encap_blob);
+ } else {
+ pad = ULP_BYTE_2_BITS(tbl->record_size) -
+ ulp_blob_data_len_get(&encap_blob);
+ }
+ if (ulp_blob_pad_push(&encap_blob, pad) < 0) {
+ BNXT_TF_DBG(ERR, "encap buffer padding failed\n");
+ return -EINVAL;
+ }
+
/* perform the 64 bit byte swap */
ulp_blob_perform_64B_byte_swap(&encap_blob);
@@ -2411,13 +2495,11 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
bool global = false;
uint64_t act_rec_size;
bool shared = false;
+ enum tf_tbl_type tbl_type = tbl->resource_type;
tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session);
- /* use the max size if encap is enabled */
- if (tbl->encap_num_fields)
- bit_size = BNXT_ULP_FLMP_BLOB_SIZE_IN_BITS;
- else
- bit_size = tbl->result_bit_size;
+ /* compute the blob size */
+ bit_size = ulp_mapper_dyn_blob_size_get(parms, tbl);
/* Initialize the blob data */
if (!ulp_blob_init(&data, bit_size,
@@ -2526,7 +2608,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
gparms.dir = tbl->direction;
gparms.type = tbl->resource_type;
gparms.data = ulp_blob_data_get(&data, &tmplen);
- gparms.data_sz_in_bytes = ULP_BITS_2_BYTE(tbl->result_bit_size);
+ gparms.data_sz_in_bytes = ULP_BITS_2_BYTE(tmplen);
gparms.idx = index;
rc = tf_get_tbl_entry(tfp, &gparms);
if (rc) {
@@ -2568,14 +2650,16 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
if (alloc) {
aparms.dir = tbl->direction;
- aparms.type = tbl->resource_type;
+ tbl_type = ulp_mapper_dyn_tbl_type_get(parms, tbl,
+ &data, &tmplen);
+ aparms.type = tbl_type;
aparms.tbl_scope_id = tbl_scope_id;
/* All failures after the alloc succeeds require a free */
rc = tf_alloc_tbl_entry(tfp, &aparms);
if (rc) {
BNXT_TF_DBG(ERR, "Alloc table[%s][%s] failed rc=%d\n",
- tf_tbl_type_2_str(tbl->resource_type),
+ tf_tbl_type_2_str(aparms.type),
tf_dir_2_str(tbl->direction), rc);
return rc;
}
@@ -2619,8 +2703,10 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
if (write) {
sparms.dir = tbl->direction;
- sparms.type = tbl->resource_type;
sparms.data = ulp_blob_data_get(&data, &tmplen);
+ tbl_type = ulp_mapper_dyn_tbl_type_get(parms, tbl, &data,
+ &tmplen);
+ sparms.type = tbl_type;
sparms.data_sz_in_bytes = ULP_BITS_2_BYTE(tmplen);
sparms.idx = index;
sparms.tbl_scope_id = tbl_scope_id;
@@ -2655,7 +2741,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
memset(&fid_parms, 0, sizeof(fid_parms));
fid_parms.direction = tbl->direction;
fid_parms.resource_func = tbl->resource_func;
- fid_parms.resource_type = tbl->resource_type;
+ fid_parms.resource_type = tbl_type;
fid_parms.resource_sub_type = tbl->resource_sub_type;
fid_parms.resource_hndl = index;
fid_parms.critical_resource = tbl->critical_resource;
@@ -2684,7 +2770,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
* write to the entry or link the flow
*/
free_parms.dir = tbl->direction;
- free_parms.type = tbl->resource_type;
+ free_parms.type = tbl_type;
free_parms.idx = index;
free_parms.tbl_scope_id = tbl_scope_id;
@@ -2862,8 +2948,7 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms,
cache_key = ulp_blob_data_get(&key, &tmplen);
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
- BNXT_TF_DBG(DEBUG, "The gen_tbl[%u] key\n", tbl_idx);
- ulp_mapper_blob_dump(&key);
+ ulp_mapper_gen_tbl_dump(tbl->resource_sub_type, tbl->direction, &key);
#endif
#endif
/* get the generic table */
@@ -3310,18 +3395,10 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms,
*res = regval == 0;
break;
case BNXT_ULP_COND_OPC_FLOW_PAT_MATCH:
- if (parms->flow_pattern_id == operand) {
- BNXT_TF_DBG(ERR, "field pattern match failed %x\n",
- parms->flow_pattern_id);
- return -EINVAL;
- }
+ *res = parms->flow_pattern_id == operand;
break;
case BNXT_ULP_COND_OPC_ACT_PAT_MATCH:
- if (parms->act_pattern_id == operand) {
- BNXT_TF_DBG(ERR, "act pattern match failed %x\n",
- parms->act_pattern_id);
- return -EINVAL;
- }
+ *res = parms->act_pattern_id == operand;
break;
case BNXT_ULP_COND_OPC_EXT_MEM_IS_SET:
if (bnxt_ulp_cntxt_mem_type_get(parms->ulp_ctx, &mtype)) {
@@ -3507,7 +3584,6 @@ ulp_mapper_func_info_process(struct bnxt_ulp_mapper_parms *parms,
return rc;
}
-
/*
* Processes a list of conditions and returns both a status and result of the
* list. The status must be checked prior to verifying the result.
@@ -3863,8 +3939,7 @@ ulp_mapper_resources_free(struct bnxt_ulp_context *ulp_ctx,
* Set the critical resource on the first resource del, then iterate
* while status is good
*/
- if (flow_type != BNXT_ULP_FDB_TYPE_RID)
- res_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES;
+ res_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES;
rc = ulp_flow_db_resource_del(ulp_ctx, flow_type, fid, &res_parms);
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index dce95de05c..3a9c9bba27 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -1226,20 +1226,66 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
/* Function to handle the update of proto header based on field values */
static void
-ulp_rte_l4_proto_type_update(struct ulp_rte_parser_params *param,
- uint16_t dst_port)
-{
- if (dst_port == tfp_cpu_to_be_16(ULP_UDP_PORT_VXLAN)) {
- ULP_BITMAP_SET(param->hdr_fp_bit.bits,
- BNXT_ULP_HDR_BIT_T_VXLAN);
- ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_L3_TUN, 1);
+ulp_rte_l4_proto_type_update(struct ulp_rte_parser_params *params,
+ uint16_t src_port, uint16_t src_mask,
+ uint16_t dst_port, uint16_t dst_mask,
+ enum bnxt_ulp_hdr_bit hdr_bit)
+{
+ switch (hdr_bit) {
+ case BNXT_ULP_HDR_BIT_I_UDP:
+ case BNXT_ULP_HDR_BIT_I_TCP:
+ ULP_BITMAP_SET(params->hdr_bitmap.bits, hdr_bit);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4, 1);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_SRC_PORT,
+ (uint64_t)rte_be_to_cpu_16(src_port));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_DST_PORT,
+ (uint64_t)rte_be_to_cpu_16(dst_port));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK,
+ (uint64_t)rte_be_to_cpu_16(src_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK,
+ (uint64_t)rte_be_to_cpu_16(dst_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID,
+ 1);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT,
+ !!(src_port & src_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT,
+ !!(dst_port & dst_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_PROTO_ID,
+ (hdr_bit == BNXT_ULP_HDR_BIT_I_UDP) ?
+ IPPROTO_UDP : IPPROTO_TCP);
+ break;
+ case BNXT_ULP_HDR_BIT_O_UDP:
+ case BNXT_ULP_HDR_BIT_O_TCP:
+ ULP_BITMAP_SET(params->hdr_bitmap.bits, hdr_bit);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4, 1);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_SRC_PORT,
+ (uint64_t)rte_be_to_cpu_16(src_port));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DST_PORT,
+ (uint64_t)rte_be_to_cpu_16(dst_port));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK,
+ (uint64_t)rte_be_to_cpu_16(src_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK,
+ (uint64_t)rte_be_to_cpu_16(dst_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID,
+ 1);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT,
+ !!(src_port & src_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT,
+ !!(dst_port & dst_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_PROTO_ID,
+ (hdr_bit == BNXT_ULP_HDR_BIT_O_UDP) ?
+ IPPROTO_UDP : IPPROTO_TCP);
+ break;
+ default:
+ break;
}
- if (ULP_BITMAP_ISSET(param->hdr_bitmap.bits,
- BNXT_ULP_HDR_BIT_T_VXLAN) ||
- ULP_BITMAP_ISSET(param->hdr_bitmap.bits,
- BNXT_ULP_HDR_BIT_T_GRE))
- ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_L3_TUN, 1);
+ if (hdr_bit == BNXT_ULP_HDR_BIT_O_UDP && dst_port ==
+ tfp_cpu_to_be_16(ULP_UDP_PORT_VXLAN)) {
+ ULP_BITMAP_SET(params->hdr_fp_bit.bits,
+ BNXT_ULP_HDR_BIT_T_VXLAN);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN, 1);
+ }
}
/* Function to handle the parsing of RTE Flow item UDP Header. */
@@ -1253,7 +1299,9 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item,
uint32_t idx = 0;
uint32_t size;
uint16_t dport = 0, sport = 0;
+ uint16_t dport_mask = 0, sport_mask = 0;
uint32_t cnt;
+ enum bnxt_ulp_hdr_bit out_l4 = BNXT_ULP_HDR_BIT_O_UDP;
cnt = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L4_HDR_CNT);
if (cnt == 2) {
@@ -1265,6 +1313,10 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item,
sport = udp_spec->hdr.src_port;
dport = udp_spec->hdr.dst_port;
}
+ if (udp_mask) {
+ sport_mask = udp_mask->hdr.src_port;
+ dport_mask = udp_mask->hdr.dst_port;
+ }
if (ulp_rte_prsr_fld_size_validate(params, &idx,
BNXT_ULP_PROTO_HDR_UDP_NUM)) {
@@ -1302,48 +1354,11 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item,
/* Set the udp header bitmap and computed l4 header bitmaps */
if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP) ||
- ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP)) {
- ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_UDP);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4, 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_SRC_PORT,
- (uint32_t)rte_be_to_cpu_16(sport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_DST_PORT,
- (uint32_t)rte_be_to_cpu_16(dport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID,
- 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_PROTO_ID,
- IPPROTO_UDP);
- if (udp_mask && udp_mask->hdr.src_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT,
- 1);
- if (udp_mask && udp_mask->hdr.dst_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT,
- 1);
- } else {
- ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4, 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_SRC_PORT,
- (uint32_t)rte_be_to_cpu_16(sport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DST_PORT,
- (uint32_t)rte_be_to_cpu_16(dport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID,
- 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_PROTO_ID,
- IPPROTO_UDP);
- if (udp_mask && udp_mask->hdr.src_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT,
- 1);
- if (udp_mask && udp_mask->hdr.dst_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT,
- 1);
+ ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP))
+ out_l4 = BNXT_ULP_HDR_BIT_I_UDP;
- /* Update the field protocol hdr bitmap */
- ulp_rte_l4_proto_type_update(params, dport);
- }
+ ulp_rte_l4_proto_type_update(params, sport, sport_mask, dport,
+ dport_mask, out_l4);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L4_HDR_CNT, ++cnt);
return BNXT_TF_RC_SUCCESS;
}
@@ -1358,8 +1373,10 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item,
struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap;
uint32_t idx = 0;
uint16_t dport = 0, sport = 0;
+ uint16_t dport_mask = 0, sport_mask = 0;
uint32_t size;
uint32_t cnt;
+ enum bnxt_ulp_hdr_bit out_l4 = BNXT_ULP_HDR_BIT_O_TCP;
cnt = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L4_HDR_CNT);
if (cnt == 2) {
@@ -1371,6 +1388,10 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item,
sport = tcp_spec->hdr.src_port;
dport = tcp_spec->hdr.dst_port;
}
+ if (tcp_mask) {
+ sport_mask = tcp_mask->hdr.src_port;
+ dport_mask = tcp_mask->hdr.dst_port;
+ }
if (ulp_rte_prsr_fld_size_validate(params, &idx,
BNXT_ULP_PROTO_HDR_TCP_NUM)) {
@@ -1438,45 +1459,11 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item,
/* Set the udp header bitmap and computed l4 header bitmaps */
if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP) ||
- ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP)) {
- ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_TCP);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4, 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_SRC_PORT,
- (uint32_t)rte_be_to_cpu_16(sport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_DST_PORT,
- (uint32_t)rte_be_to_cpu_16(dport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID,
- 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_PROTO_ID,
- IPPROTO_TCP);
- if (tcp_mask && tcp_mask->hdr.src_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT,
- 1);
- if (tcp_mask && tcp_mask->hdr.dst_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT,
- 1);
- } else {
- ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4, 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_SRC_PORT,
- (uint32_t)rte_be_to_cpu_16(sport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DST_PORT,
- (uint32_t)rte_be_to_cpu_16(dport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID,
- 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_PROTO_ID,
- IPPROTO_TCP);
- if (tcp_mask && tcp_mask->hdr.src_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT,
- 1);
- if (tcp_mask && tcp_mask->hdr.dst_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT,
- 1);
- }
+ ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP))
+ out_l4 = BNXT_ULP_HDR_BIT_I_TCP;
+
+ ulp_rte_l4_proto_type_update(params, sport, sport_mask, dport,
+ dport_mask, out_l4);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L4_HDR_CNT, ++cnt);
return BNXT_TF_RC_SUCCESS;
}
@@ -1528,7 +1515,7 @@ ulp_rte_vxlan_hdr_handler(const struct rte_flow_item *item,
/* Update the hdr_bitmap with vxlan */
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_T_VXLAN);
- ulp_rte_l4_proto_type_update(params, 0);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN, 1);
return BNXT_TF_RC_SUCCESS;
}
@@ -1563,7 +1550,7 @@ ulp_rte_gre_hdr_handler(const struct rte_flow_item *item,
/* Update the hdr_bitmap with GRE */
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_T_GRE);
- ulp_rte_l4_proto_type_update(params, 0);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN, 1);
return BNXT_TF_RC_SUCCESS;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index 1683cd7ec4..d3bfb8c12d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -206,6 +206,11 @@ struct bnxt_ulp_template_device_tbls {
uint32_t cond_list_size;
};
+struct bnxt_ulp_dyn_size_map {
+ uint32_t slab_size;
+ enum tf_tbl_type tbl_type;
+};
+
/* Device specific parameters */
struct bnxt_ulp_device_params {
uint8_t description[16];
@@ -229,6 +234,11 @@ struct bnxt_ulp_device_params {
uint32_t byte_count_shift;
uint32_t packet_count_shift;
uint32_t dynamic_pad_en;
+ uint32_t dynamic_sram_en;
+ uint32_t dyn_encap_list_size;
+ struct bnxt_ulp_dyn_size_map dyn_encap_sizes[4];
+ uint32_t dyn_modify_list_size;
+ struct bnxt_ulp_dyn_size_map dyn_modify_sizes[4];
uint16_t em_blk_size_bits;
uint16_t em_blk_align_bits;
uint16_t em_key_align_bytes;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c
index 686b80e456..df3afaa6fd 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c
@@ -882,7 +882,8 @@ ulp_blob_msb_block_merge(struct ulp_blob *dst, struct ulp_blob *src,
for (i = 0; i < num;) {
if (((dst->write_idx % block_size) + (num - i)) > block_size)
- write_bytes = block_size - dst->write_idx;
+ write_bytes = block_size -
+ (dst->write_idx % block_size);
else
write_bytes = num - i;
for (k = 0; k < ULP_BITS_2_BYTE_NR(write_bytes); k++) {
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH 14/14] net/bnxt: add support for testpmd co-existence
2021-09-01 14:24 [dpdk-dev] [PATCH 00/14] enhancements to host based flow table management Venkat Duvvuru
` (12 preceding siblings ...)
2021-09-01 14:24 ` [dpdk-dev] [PATCH 13/14] net/bnxt: add enhancements to TF ULP Venkat Duvvuru
@ 2021-09-01 14:24 ` Venkat Duvvuru
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 00/13] enhancements to host based flow table management Venkat Duvvuru
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-01 14:24 UTC (permalink / raw)
To: dev; +Cc: Venkat Duvvuru
Currently, testpmd support in ULP is enabled only during compilation
time. This patch adds support for testpmd during runtime using
devarg "testpmd".
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
---
drivers/net/bnxt/bnxt.h | 3 ++
drivers/net/bnxt/bnxt_ethdev.c | 56 +++++++++++++++++++++++++
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 5 +++
drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 4 +-
4 files changed, 67 insertions(+), 1 deletion(-)
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index 494a1eff37..c9adc66fda 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -722,6 +722,9 @@ struct bnxt {
((bp)->flags2 & BNXT_FLAGS2_PTP_TIMESYNC_ENABLED)
#define BNXT_ACCUM_STATS_EN(bp) \
((bp)->flags2 & BNXT_FLAGS2_ACCUM_STATS_EN)
+#define BNXT_FLAGS2_TESTPMD_EN BIT(3)
+#define BNXT_TESTPMD_EN(bp) \
+ ((bp)->flags2 & BNXT_FLAGS2_TESTPMD_EN)
uint16_t chip_num;
#define CHIP_NUM_58818 0xd818
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index de34a2f0bb..20c5b12b53 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -98,6 +98,7 @@ static const struct rte_pci_id bnxt_pci_id_map[] = {
#define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f"
#define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r"
#define BNXT_DEVARG_APP_ID "app-id"
+#define BNXT_DEVARG_TESTPMD "testpmd"
static const char *const bnxt_dev_args[] = {
BNXT_DEVARG_REPRESENTOR,
@@ -111,9 +112,17 @@ static const char *const bnxt_dev_args[] = {
BNXT_DEVARG_REP_FC_R2F,
BNXT_DEVARG_REP_FC_F2R,
BNXT_DEVARG_APP_ID,
+ BNXT_DEVARG_TESTPMD,
NULL
};
+/*
+ * testpmd == false to disable
+ * testpmd == true to enable
+ */
+#define BNXT_DEVARG_TESTPMD_INVALID(truflow) ((testpmd) > 1)
+
+
/*
* accum-stats == false to disable flow counter accumulation
* accum-stats == true to enable flow counter accumulation
@@ -5853,6 +5862,44 @@ bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
return 0;
}
+static int
+bnxt_parse_devarg_testpmd(__rte_unused const char *key,
+ const char *value, void *opaque_arg)
+{
+ struct bnxt *bp = opaque_arg;
+ unsigned long testpmd;
+ char *end = NULL;
+
+ if (!value || !opaque_arg) {
+ PMD_DRV_LOG(ERR,
+ "Invalid parameter passed to testpmd devargs.\n");
+ return -EINVAL;
+ }
+
+ testpmd = strtoul(value, &end, 10);
+ if (end == NULL || *end != '\0' ||
+ (testpmd == ULONG_MAX && errno == ERANGE)) {
+ PMD_DRV_LOG(ERR,
+ "Invalid parameter passed to testpmd devargs.\n");
+ return -EINVAL;
+ }
+
+ if (BNXT_DEVARG_TESTPMD_INVALID(testpmd)) {
+ PMD_DRV_LOG(ERR,
+ "Invalid value passed to testpmd devargs.\n");
+ return -EINVAL;
+ }
+
+ if (testpmd) {
+ bp->flags2 |= BNXT_FLAGS2_TESTPMD_EN;
+ PMD_DRV_LOG(INFO, "Host-based testpmd feature enabled.\n");
+ } else {
+ bp->flags2 &= ~BNXT_FLAGS2_TESTPMD_EN;
+ PMD_DRV_LOG(INFO, "Host-based testpmd feature disabled.\n");
+ }
+
+ return 0;
+}
static int
bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
{
@@ -5890,6 +5937,15 @@ bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
if (ret)
goto err;
+ /*
+ * Handler for "testpmd" devarg.
+ * Invoked as for ex: "-a 0000:00:0d.0,testpmd=1"
+ */
+ ret = rte_kvargs_process(kvlist, BNXT_DEVARG_TESTPMD,
+ bnxt_parse_devarg_testpmd, bp);
+ if (ret)
+ goto err;
+
err:
/*
* Handler for "app-id" devarg.
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 3b86410fb1..2ad662fb17 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -844,6 +844,11 @@ ulp_ctx_init(struct bnxt *bp,
goto error_deinit;
}
+ if (BNXT_TESTPMD_EN(bp)) {
+ ulp_data->ulp_flags &= ~BNXT_ULP_VF_REP_ENABLED;
+ BNXT_TF_DBG(ERR, "Enabled Testpmd forward mode\n");
+ }
+
/*
* Shared session must be created before first regular session but after
* the ulp_ctx is valid.
diff --git a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
index d8336d164e..827fe30acd 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
@@ -526,8 +526,10 @@ bnxt_ulp_create_df_rules(struct bnxt *bp)
rc = ulp_default_flow_db_cfa_action_get(bp->ulp_ctx,
info->def_port_flow_id,
&bp->tx_cfa_action);
- if (rc)
+
+ if (rc || BNXT_TESTPMD_EN(bp))
bp->tx_cfa_action = 0;
+
info->valid = true;
return 0;
}
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v2 00/13] enhancements to host based flow table management
2021-09-01 14:24 [dpdk-dev] [PATCH 00/14] enhancements to host based flow table management Venkat Duvvuru
` (13 preceding siblings ...)
2021-09-01 14:24 ` [dpdk-dev] [PATCH 14/14] net/bnxt: add support for testpmd co-existence Venkat Duvvuru
@ 2021-09-08 5:06 ` Venkat Duvvuru
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 01/13] net/bnxt: tf core index table updates Venkat Duvvuru
` (14 more replies)
14 siblings, 15 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-08 5:06 UTC (permalink / raw)
To: dev; +Cc: Venkat Duvvuru
This patch set adds support for new offload features/enhancments for
Thor adapters like VF representor support, new flow matches/actions
& dynamic SRAM manager support.
v1 ==> v2
=========
1. Fixed compilation issues
2. Abandoned patch 14
Farah Smith (4):
net/bnxt: tf core index table updates
net/bnxt: add Thor SRAM mgr model
net/bnxt: tf core SRAM Manager
net/bnxt: sram manager shared session
Jay Ding (1):
net/bnxt: add flow meter drop counter support
Kishore Padmanabha (6):
net/bnxt: add flow templates support for Thor
net/bnxt: add support for tunnel offloads
net/bnxt: add support for dynamic encap action
net/bnxt: add wild card TCAM byte order for Thor
net/bnxt: add flow templates for Thor
net/bnxt: add enhancements to TF ULP
Peter Spreadborough (1):
net/bnxt: enable dpool allocator
Randy Schacher (1):
net/bnxt: dynamically allocate space for EM defrag function
drivers/net/bnxt/tf_core/cfa_resource_types.h | 5 +-
drivers/net/bnxt/tf_core/dpool.c | 38 +-
drivers/net/bnxt/tf_core/ll.c | 3 +
drivers/net/bnxt/tf_core/ll.h | 50 +-
drivers/net/bnxt/tf_core/meson.build | 2 +
drivers/net/bnxt/tf_core/tf_core.c | 169 +-
drivers/net/bnxt/tf_core/tf_core.h | 159 +-
drivers/net/bnxt/tf_core/tf_device.c | 40 +-
drivers/net/bnxt/tf_core/tf_device.h | 137 +-
drivers/net/bnxt/tf_core/tf_device_p4.c | 77 +-
drivers/net/bnxt/tf_core/tf_device_p4.h | 50 +-
drivers/net/bnxt/tf_core/tf_device_p58.c | 112 +-
drivers/net/bnxt/tf_core/tf_device_p58.h | 70 +-
drivers/net/bnxt/tf_core/tf_em.h | 10 -
drivers/net/bnxt/tf_core/tf_em_common.c | 4 +
.../net/bnxt/tf_core/tf_em_hash_internal.c | 34 -
drivers/net/bnxt/tf_core/tf_em_internal.c | 185 +-
drivers/net/bnxt/tf_core/tf_msg.c | 2 +-
drivers/net/bnxt/tf_core/tf_rm.c | 180 +-
drivers/net/bnxt/tf_core/tf_rm.h | 62 +-
drivers/net/bnxt/tf_core/tf_session.c | 56 +
drivers/net/bnxt/tf_core/tf_session.h | 58 +-
drivers/net/bnxt/tf_core/tf_sram_mgr.c | 971 +
drivers/net/bnxt/tf_core/tf_sram_mgr.h | 317 +
drivers/net/bnxt/tf_core/tf_tbl.c | 259 +-
drivers/net/bnxt/tf_core/tf_tbl.h | 87 +-
drivers/net/bnxt/tf_core/tf_tbl_sram.c | 747 +
drivers/net/bnxt/tf_core/tf_tbl_sram.h | 154 +
drivers/net/bnxt/tf_core/tf_tcam.c | 16 +-
drivers/net/bnxt/tf_core/tf_tcam.h | 7 +
drivers/net/bnxt/tf_core/tf_tcam_shared.c | 28 +-
drivers/net/bnxt/tf_core/tf_util.c | 12 +
drivers/net/bnxt/tf_ulp/bnxt_tf_common.h | 10 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 52 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 20 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 226 +-
.../bnxt/tf_ulp/generic_templates/meson.build | 17 +-
.../generic_templates/ulp_template_db_act.c | 2 +-
.../generic_templates/ulp_template_db_class.c | 12109 +++-
.../generic_templates/ulp_template_db_enum.h | 618 +-
.../generic_templates/ulp_template_db_field.h | 767 +-
.../generic_templates/ulp_template_db_tbl.c | 2757 +-
.../ulp_template_db_thor_act.c | 5079 +-
.../ulp_template_db_thor_class.c | 45573 ++++++++++++++--
.../ulp_template_db_wh_plus_act.c | 1700 +-
.../ulp_template_db_wh_plus_class.c | 8329 ++-
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 48 +-
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h | 8 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 678 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 68 +-
drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c | 9 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 448 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.h | 10 +-
drivers/net/bnxt/tf_ulp/ulp_matcher.c | 13 +
drivers/net/bnxt/tf_ulp/ulp_port_db.c | 15 +-
drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c | 31 +
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 663 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 12 +-
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 32 +-
drivers/net/bnxt/tf_ulp/ulp_tun.c | 521 +-
drivers/net/bnxt/tf_ulp/ulp_tun.h | 89 +-
drivers/net/bnxt/tf_ulp/ulp_utils.c | 71 +-
drivers/net/bnxt/tf_ulp/ulp_utils.h | 27 +-
meson_options.txt | 2 +
64 files changed, 71149 insertions(+), 12956 deletions(-)
create mode 100644 drivers/net/bnxt/tf_core/tf_sram_mgr.c
create mode 100644 drivers/net/bnxt/tf_core/tf_sram_mgr.h
create mode 100644 drivers/net/bnxt/tf_core/tf_tbl_sram.c
create mode 100644 drivers/net/bnxt/tf_core/tf_tbl_sram.h
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v2 01/13] net/bnxt: tf core index table updates
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 00/13] enhancements to host based flow table management Venkat Duvvuru
@ 2021-09-08 5:06 ` Venkat Duvvuru
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 02/13] net/bnxt: enable dpool allocator Venkat Duvvuru
` (13 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-08 5:06 UTC (permalink / raw)
To: dev; +Cc: Farah Smith
From: Farah Smith <farah.smith@broadcom.com>
Remove unused shadow table functionality.
Signed-off-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Peter Spreadborough <peter.spreadborough@broadcom.com>
---
drivers/net/bnxt/tf_core/tf_core.c | 65 --------------
drivers/net/bnxt/tf_core/tf_core.h | 103 +----------------------
drivers/net/bnxt/tf_core/tf_device.h | 22 -----
drivers/net/bnxt/tf_core/tf_device_p4.c | 2 -
drivers/net/bnxt/tf_core/tf_device_p58.c | 2 -
drivers/net/bnxt/tf_core/tf_em_common.c | 4 +
drivers/net/bnxt/tf_core/tf_tbl.c | 21 -----
drivers/net/bnxt/tf_core/tf_tbl.h | 72 ----------------
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 3 +-
9 files changed, 7 insertions(+), 287 deletions(-)
diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c
index 97e6165e92..5458f76e2d 100644
--- a/drivers/net/bnxt/tf_core/tf_core.c
+++ b/drivers/net/bnxt/tf_core/tf_core.c
@@ -1105,71 +1105,6 @@ tf_alloc_tbl_entry(struct tf *tfp,
return 0;
}
-int
-tf_search_tbl_entry(struct tf *tfp,
- struct tf_search_tbl_entry_parms *parms)
-{
- int rc;
- struct tf_session *tfs;
- struct tf_dev_info *dev;
- struct tf_tbl_alloc_search_parms sparms;
-
- TF_CHECK_PARMS2(tfp, parms);
-
- /* Retrieve the session information */
- rc = tf_session_get_session(tfp, &tfs);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed to lookup session, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(-rc));
- return rc;
- }
-
- /* Retrieve the device information */
- rc = tf_session_get_device(tfs, &dev);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed to lookup device, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(-rc));
- return rc;
- }
-
- if (dev->ops->tf_dev_alloc_search_tbl == NULL) {
- rc = -EOPNOTSUPP;
- TFP_DRV_LOG(ERR,
- "%s: Operation not supported, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(-rc));
- return rc;
- }
-
- memset(&sparms, 0, sizeof(struct tf_tbl_alloc_search_parms));
- sparms.dir = parms->dir;
- sparms.type = parms->type;
- sparms.result = parms->result;
- sparms.result_sz_in_bytes = parms->result_sz_in_bytes;
- sparms.alloc = parms->alloc;
- sparms.tbl_scope_id = parms->tbl_scope_id;
- rc = dev->ops->tf_dev_alloc_search_tbl(tfp, &sparms);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: TBL allocation failed, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(-rc));
- return rc;
- }
-
- /* Return the outputs from the search */
- parms->hit = sparms.hit;
- parms->search_status = sparms.search_status;
- parms->ref_cnt = sparms.ref_cnt;
- parms->idx = sparms.idx;
-
- return 0;
-}
-
int
tf_free_tbl_entry(struct tf *tfp,
struct tf_free_tbl_entry_parms *parms)
diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h
index 84b234f0e3..7e0cdf7e0d 100644
--- a/drivers/net/bnxt/tf_core/tf_core.h
+++ b/drivers/net/bnxt/tf_core/tf_core.h
@@ -1622,79 +1622,6 @@ int tf_clear_tcam_shared_entries(struct tf *tfp,
* @ref tf_get_shared_tbl_increment
*/
-/**
- * tf_alloc_tbl_entry parameter definition
- */
-struct tf_search_tbl_entry_parms {
- /**
- * [in] Receive or transmit direction
- */
- enum tf_dir dir;
- /**
- * [in] Type of the allocation
- */
- enum tf_tbl_type type;
- /**
- * [in] Table scope identifier (ignored unless TF_TBL_TYPE_EXT)
- */
- uint32_t tbl_scope_id;
- /**
- * [in] Result data to search for
- */
- uint8_t *result;
- /**
- * [in] Result data size in bytes
- */
- uint16_t result_sz_in_bytes;
- /**
- * [in] Allocate on miss.
- */
- uint8_t alloc;
- /**
- * [out] Set if matching entry found
- */
- uint8_t hit;
- /**
- * [out] Search result status (hit, miss, reject)
- */
- enum tf_search_status search_status;
- /**
- * [out] Current ref count after allocation
- */
- uint16_t ref_cnt;
- /**
- * [out] Idx of allocated entry or found entry
- */
- uint32_t idx;
-};
-
-/**
- * search Table Entry (experimental)
- *
- * This function searches the shadow copy of an index table for a matching
- * entry. The result data must match for hit to be set. Only TruFlow core
- * data is accessed. If shadow_copy is not enabled, an error is returned.
- *
- * Implementation:
- *
- * A hash is performed on the result data and mapped to a shadow copy entry
- * where the result is populated. If the result matches the entry, hit is set,
- * ref_cnt is incremented (if alloc), and the search status indicates what
- * action the caller can take regarding setting the entry.
- *
- * search status should be used as follows:
- * - On MISS, the caller should set the result into the returned index.
- *
- * - On REJECT, the caller should reject the flow since there are no resources.
- *
- * - On Hit, the matching index is returned to the caller. Additionally, the
- * ref_cnt is updated.
- *
- * Also returns success or failure code.
- */
-int tf_search_tbl_entry(struct tf *tfp,
- struct tf_search_tbl_entry_parms *parms);
-
/**
* tf_alloc_tbl_entry parameter definition
*/
@@ -1711,30 +1638,9 @@ struct tf_alloc_tbl_entry_parms {
* [in] Table scope identifier (ignored unless TF_TBL_TYPE_EXT)
*/
uint32_t tbl_scope_id;
+
/**
- * [in] Enable search for matching entry. If the table type is
- * internal the shadow copy will be searched before
- * alloc. Session must be configured with shadow copy enabled.
- */
- uint8_t search_enable;
- /**
- * [in] Result data to search for (if search_enable)
- */
- uint8_t *result;
- /**
- * [in] Result data size in bytes (if search_enable)
- */
- uint16_t result_sz_in_bytes;
- /**
- * [out] If search_enable, set if matching entry found
- */
- uint8_t hit;
- /**
- * [out] Current ref count after allocation (if search_enable)
- */
- uint16_t ref_cnt;
- /**
- * [out] Idx of allocated entry or found entry (if search_enable)
+ * [out] Idx of allocated entry
*/
uint32_t idx;
};
@@ -1790,11 +1696,6 @@ struct tf_free_tbl_entry_parms {
* [in] Index to free
*/
uint32_t idx;
- /**
- * [out] Reference count after free, only valid if session has been
- * created with shadow_copy.
- */
- uint16_t ref_cnt;
};
/**
diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h
index da3f541685..b43cfc6925 100644
--- a/drivers/net/bnxt/tf_core/tf_device.h
+++ b/drivers/net/bnxt/tf_core/tf_device.h
@@ -347,28 +347,6 @@ struct tf_dev_ops {
int (*tf_dev_free_ext_tbl)(struct tf *tfp,
struct tf_tbl_free_parms *parms);
- /**
- * Searches for the specified table type element in a shadow DB.
- *
- * This API searches for the specified table type element in a
- * device specific shadow DB. If the element is found the
- * reference count for the element is updated. If the element
- * is not found a new element is allocated from the table type
- * DB and then inserted into the shadow DB.
- *
- * [in] tfp
- * Pointer to TF handle
- *
- * [in] parms
- * Pointer to table allocation and search parameters
- *
- * Returns
- * - (0) if successful.
- * - (-EINVAL) on failure.
- */
- int (*tf_dev_alloc_search_tbl)(struct tf *tfp,
- struct tf_tbl_alloc_search_parms *parms);
-
/**
* Sets the specified table type element.
*
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c
index 971fab7bda..2e7ccec123 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.c
@@ -236,7 +236,6 @@ const struct tf_dev_ops tf_dev_ops_p4_init = {
.tf_dev_alloc_tbl = NULL,
.tf_dev_free_ext_tbl = NULL,
.tf_dev_free_tbl = NULL,
- .tf_dev_alloc_search_tbl = NULL,
.tf_dev_set_tbl = NULL,
.tf_dev_set_ext_tbl = NULL,
.tf_dev_get_tbl = NULL,
@@ -282,7 +281,6 @@ const struct tf_dev_ops tf_dev_ops_p4 = {
.tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc,
.tf_dev_free_tbl = tf_tbl_free,
.tf_dev_free_ext_tbl = tf_tbl_ext_free,
- .tf_dev_alloc_search_tbl = tf_tbl_alloc_search,
.tf_dev_set_tbl = tf_tbl_set,
.tf_dev_set_ext_tbl = tf_tbl_ext_common_set,
.tf_dev_get_tbl = tf_tbl_get,
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c
index 6bbc5e21e9..ce4d8c661f 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.c
@@ -280,7 +280,6 @@ const struct tf_dev_ops tf_dev_ops_p58_init = {
.tf_dev_alloc_tbl = NULL,
.tf_dev_free_ext_tbl = NULL,
.tf_dev_free_tbl = NULL,
- .tf_dev_alloc_search_tbl = NULL,
.tf_dev_set_tbl = NULL,
.tf_dev_set_ext_tbl = NULL,
.tf_dev_get_tbl = NULL,
@@ -326,7 +325,6 @@ const struct tf_dev_ops tf_dev_ops_p58 = {
.tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc,
.tf_dev_free_tbl = tf_tbl_free,
.tf_dev_free_ext_tbl = tf_tbl_ext_free,
- .tf_dev_alloc_search_tbl = tf_tbl_alloc_search,
.tf_dev_set_tbl = tf_tbl_set,
.tf_dev_set_ext_tbl = tf_tbl_ext_common_set,
.tf_dev_get_tbl = tf_tbl_get,
diff --git a/drivers/net/bnxt/tf_core/tf_em_common.c b/drivers/net/bnxt/tf_core/tf_em_common.c
index 812ccb0d29..3bdfc14e05 100644
--- a/drivers/net/bnxt/tf_core/tf_em_common.c
+++ b/drivers/net/bnxt/tf_core/tf_em_common.c
@@ -23,6 +23,10 @@
#include "bnxt.h"
+
+/** Invalid table scope id */
+#define TF_TBL_SCOPE_INVALID 0xffffffff
+
/* Number of pointers per page_size */
#define MAX_PAGE_PTRS(page_size) ((page_size) / sizeof(void *))
diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c
index ced59130b2..e77399c6bd 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl.c
+++ b/drivers/net/bnxt/tf_core/tf_tbl.c
@@ -26,11 +26,6 @@
struct tf;
-/**
- * Table Shadow DBs
- */
-static void *shadow_tbl_db[TF_DIR_MAX];
-
/**
* Shadow init flag, set on bind and cleared on unbind
*/
@@ -327,22 +322,6 @@ tf_tbl_free(struct tf *tfp __rte_unused,
return 0;
}
-int
-tf_tbl_alloc_search(struct tf *tfp,
- struct tf_tbl_alloc_search_parms *parms)
-{
- int rc = 0;
- TF_CHECK_PARMS2(tfp, parms);
-
- if (!shadow_init || !shadow_tbl_db[parms->dir]) {
- TFP_DRV_LOG(ERR, "%s: Shadow TBL not initialized.\n",
- tf_dir_2_str(parms->dir));
- return -EINVAL;
- }
-
- return rc;
-}
-
int
tf_tbl_set(struct tf *tfp,
struct tf_tbl_set_parms *parms)
diff --git a/drivers/net/bnxt/tf_core/tf_tbl.h b/drivers/net/bnxt/tf_core/tf_tbl.h
index aba46fd161..7e1107ffe7 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl.h
+++ b/drivers/net/bnxt/tf_core/tf_tbl.h
@@ -15,8 +15,6 @@ struct tf;
* The Table module provides processing of Internal TF table types.
*/
-/** Invalid table scope id */
-#define TF_TBL_SCOPE_INVALID 0xffffffff
/**
* Table configuration parameters
@@ -86,57 +84,6 @@ struct tf_tbl_free_parms {
* [in] Index to free
*/
uint32_t idx;
- /**
- * [out] Reference count after free, only valid if session has been
- * created with shadow_copy.
- */
- uint16_t ref_cnt;
-};
-
-/**
- * Table allocate search parameters
- */
-struct tf_tbl_alloc_search_parms {
- /**
- * [in] Receive or transmit direction
- */
- enum tf_dir dir;
- /**
- * [in] Type of the allocation
- */
- enum tf_tbl_type type;
- /**
- * [in] Table scope identifier (ignored unless TF_TBL_TYPE_EXT)
- */
- uint32_t tbl_scope_id;
- /**
- * [in] Result data to search for
- */
- uint8_t *result;
- /**
- * [in] Result data size in bytes
- */
- uint16_t result_sz_in_bytes;
- /**
- * [in] Whether or not to allocate on MISS, 1 is allocate.
- */
- uint8_t alloc;
- /**
- * [out] If search_enable, set if matching entry found
- */
- uint8_t hit;
- /**
- * [out] The status of the search (REJECT, MISS, HIT)
- */
- enum tf_search_status search_status;
- /**
- * [out] Current ref count after allocation
- */
- uint16_t ref_cnt;
- /**
- * [out] Idx of allocated entry or found entry
- */
- uint32_t idx;
};
/**
@@ -326,25 +273,6 @@ int tf_tbl_alloc(struct tf *tfp,
int tf_tbl_free(struct tf *tfp,
struct tf_tbl_free_parms *parms);
-/**
- * Supported if Shadow DB is configured. Searches the Shadow DB for
- * any matching element. If found the refcount in the shadow DB is
- * updated accordingly. If not found a new element is allocated and
- * installed into the shadow DB.
- *
- * [in] tfp
- * Pointer to TF handle, used for HCAPI communication
- *
- * [in] parms
- * Pointer to parameters
- *
- * Returns
- * - (0) if successful.
- * - (-EINVAL) on failure.
- */
-int tf_tbl_alloc_search(struct tf *tfp,
- struct tf_tbl_alloc_search_parms *parms);
-
/**
* Configures the requested element by sending a firmware request which
* then installs it into the device internal structures.
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 871dbad0fe..f3a60cc880 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -189,13 +189,12 @@ ulp_mapper_resource_index_tbl_alloc(struct bnxt_ulp_context *ulp_ctx,
aparms.type = glb_res->resource_type;
aparms.dir = glb_res->direction;
- aparms.search_enable = 0;
aparms.tbl_scope_id = tbl_scope_id;
/* Allocate the index tbl using tf api */
rc = tf_alloc_tbl_entry(tfp, &aparms);
if (rc) {
- BNXT_TF_DBG(ERR, "Failed to alloc identifier [%s][%d]\n",
+ BNXT_TF_DBG(ERR, "Failed to alloc index table [%s][%d]\n",
tf_dir_2_str(aparms.dir), aparms.type);
return rc;
}
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v2 02/13] net/bnxt: enable dpool allocator
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 00/13] enhancements to host based flow table management Venkat Duvvuru
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 01/13] net/bnxt: tf core index table updates Venkat Duvvuru
@ 2021-09-08 5:06 ` Venkat Duvvuru
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 03/13] net/bnxt: add flow meter drop counter support Venkat Duvvuru
` (12 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-08 5:06 UTC (permalink / raw)
To: dev; +Cc: Peter Spreadborough
From: Peter Spreadborough <peter.spreadborough@broadcom.com>
Enable dynamic entry allocator for EM SRAM entries.
Deprecate static entry allocator code.
Signed-off-by: Peter Spreadborough <peter.spreadborough@broadcom.com>
Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
---
drivers/net/bnxt/tf_core/tf_device_p58.c | 4 -
drivers/net/bnxt/tf_core/tf_em.h | 10 -
.../net/bnxt/tf_core/tf_em_hash_internal.c | 34 ----
drivers/net/bnxt/tf_core/tf_em_internal.c | 180 +-----------------
4 files changed, 1 insertion(+), 227 deletions(-)
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c
index ce4d8c661f..808dcb1f77 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.c
@@ -348,11 +348,7 @@ const struct tf_dev_ops tf_dev_ops_p58 = {
.tf_dev_get_tcam_resc_info = tf_tcam_get_resc_info,
.tf_dev_insert_int_em_entry = tf_em_hash_insert_int_entry,
.tf_dev_delete_int_em_entry = tf_em_hash_delete_int_entry,
-#if (TF_EM_ALLOC == 1)
.tf_dev_move_int_em_entry = tf_em_move_int_entry,
-#else
- .tf_dev_move_int_em_entry = NULL,
-#endif
.tf_dev_insert_ext_em_entry = NULL,
.tf_dev_delete_ext_em_entry = NULL,
.tf_dev_get_em_resc_info = tf_em_get_resc_info,
diff --git a/drivers/net/bnxt/tf_core/tf_em.h b/drivers/net/bnxt/tf_core/tf_em.h
index 568071ad8c..074c128651 100644
--- a/drivers/net/bnxt/tf_core/tf_em.h
+++ b/drivers/net/bnxt/tf_core/tf_em.h
@@ -13,16 +13,6 @@
#include "hcapi_cfa_defs.h"
-/**
- * TF_EM_ALLOC
- *
- * 0: Use stack allocator with fixed sized entries
- * (default).
- * 1: Use dpool allocator with variable size
- * entries.
- */
-#define TF_EM_ALLOC 0
-
#define TF_EM_MIN_ENTRIES (1 << 15) /* 32K */
#define TF_EM_MAX_ENTRIES (1 << 27) /* 128M */
diff --git a/drivers/net/bnxt/tf_core/tf_em_hash_internal.c b/drivers/net/bnxt/tf_core/tf_em_hash_internal.c
index 098e8af07e..60273a798c 100644
--- a/drivers/net/bnxt/tf_core/tf_em_hash_internal.c
+++ b/drivers/net/bnxt/tf_core/tf_em_hash_internal.c
@@ -22,9 +22,7 @@
/**
* EM Pool
*/
-#if (TF_EM_ALLOC == 1)
#include "dpool.h"
-#endif
/**
* Insert EM internal entry API
@@ -41,11 +39,7 @@ tf_em_hash_insert_int_entry(struct tf *tfp,
uint16_t rptr_index = 0;
uint8_t rptr_entry = 0;
uint8_t num_of_entries = 0;
-#if (TF_EM_ALLOC == 1)
struct dpool *pool;
-#else
- struct stack *pool;
-#endif
uint32_t index;
uint32_t key0_hash;
uint32_t key1_hash;
@@ -62,7 +56,6 @@ tf_em_hash_insert_int_entry(struct tf *tfp,
rc = tf_session_get_device(tfs, &dev);
if (rc)
return rc;
-#if (TF_EM_ALLOC == 1)
pool = (struct dpool *)tfs->em_pool[parms->dir];
index = dpool_alloc(pool,
parms->em_record_sz_in_bits / 128,
@@ -74,16 +67,6 @@ tf_em_hash_insert_int_entry(struct tf *tfp,
tf_dir_2_str(parms->dir));
return -1;
}
-#else
- pool = (struct stack *)tfs->em_pool[parms->dir];
- rc = stack_pop(pool, &index);
- if (rc) {
- PMD_DRV_LOG(ERR,
- "%s, EM entry index allocation failed\n",
- tf_dir_2_str(parms->dir));
- return rc;
- }
-#endif
if (dev->ops->tf_dev_cfa_key_hash == NULL)
return -EINVAL;
@@ -103,11 +86,7 @@ tf_em_hash_insert_int_entry(struct tf *tfp,
&num_of_entries);
if (rc) {
/* Free the allocated index before returning */
-#if (TF_EM_ALLOC == 1)
dpool_free(pool, index);
-#else
- stack_push(pool, index);
-#endif
return -1;
}
@@ -128,9 +107,7 @@ tf_em_hash_insert_int_entry(struct tf *tfp,
rptr_index,
rptr_entry,
0);
-#if (TF_EM_ALLOC == 1)
dpool_set_entry_data(pool, index, parms->flow_handle);
-#endif
return 0;
}
@@ -146,11 +123,7 @@ tf_em_hash_delete_int_entry(struct tf *tfp,
{
int rc = 0;
struct tf_session *tfs;
-#if (TF_EM_ALLOC == 1)
struct dpool *pool;
-#else
- struct stack *pool;
-#endif
/* Retrieve the session information */
rc = tf_session_get_session(tfp, &tfs);
if (rc) {
@@ -165,19 +138,13 @@ tf_em_hash_delete_int_entry(struct tf *tfp,
/* Return resource to pool */
if (rc == 0) {
-#if (TF_EM_ALLOC == 1)
pool = (struct dpool *)tfs->em_pool[parms->dir];
dpool_free(pool, parms->index);
-#else
- pool = (struct stack *)tfs->em_pool[parms->dir];
- stack_push(pool, parms->index);
-#endif
}
return rc;
}
-#if (TF_EM_ALLOC == 1)
/** Move EM internal entry API
*
* returns:
@@ -212,4 +179,3 @@ tf_em_move_int_entry(struct tf *tfp,
return rc;
}
-#endif
diff --git a/drivers/net/bnxt/tf_core/tf_em_internal.c b/drivers/net/bnxt/tf_core/tf_em_internal.c
index 0720bb905d..2d57595f17 100644
--- a/drivers/net/bnxt/tf_core/tf_em_internal.c
+++ b/drivers/net/bnxt/tf_core/tf_em_internal.c
@@ -22,145 +22,7 @@
/**
* EM Pool
*/
-#if (TF_EM_ALLOC == 1)
#include "dpool.h"
-#else
-
-/**
- * Create EM Tbl pool of memory indexes.
- *
- * [in] dir
- * direction
- * [in] num_entries
- * number of entries to write
- * [in] start
- * starting offset
- *
- * Return:
- * 0 - Success, entry allocated - no search support
- * -ENOMEM -EINVAL -EOPNOTSUPP
- * - Failure, entry not allocated, out of resources
- */
-static int
-tf_create_em_pool(struct tf_session *tfs,
- enum tf_dir dir,
- uint32_t num_entries,
- uint32_t start)
-{
- struct tfp_calloc_parms parms;
- uint32_t i, j;
- int rc = 0;
- struct stack *pool;
-
- /*
- * Allocate stack pool
- */
- parms.nitems = 1;
- parms.size = sizeof(struct stack);
- parms.alignment = 0;
-
- rc = tfp_calloc(&parms);
-
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s, EM stack allocation failure %s\n",
- tf_dir_2_str(dir),
- strerror(-rc));
- return rc;
- }
-
- pool = (struct stack *)parms.mem_va;
- tfs->em_pool[dir] = (void *)pool;
-
- /* Assumes that num_entries has been checked before we get here */
- parms.nitems = num_entries / TF_SESSION_EM_ENTRY_SIZE;
- parms.size = sizeof(uint32_t);
- parms.alignment = 0;
-
- rc = tfp_calloc(&parms);
-
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s, EM pool allocation failure %s\n",
- tf_dir_2_str(dir),
- strerror(-rc));
- return rc;
- }
-
- /* Create empty stack
- */
- rc = stack_init(num_entries / TF_SESSION_EM_ENTRY_SIZE,
- (uint32_t *)parms.mem_va,
- pool);
-
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s, EM pool stack init failure %s\n",
- tf_dir_2_str(dir),
- strerror(-rc));
- goto cleanup;
- }
-
- /* Fill pool with indexes
- */
- j = start + num_entries - TF_SESSION_EM_ENTRY_SIZE;
-
- for (i = 0; i < (num_entries / TF_SESSION_EM_ENTRY_SIZE); i++) {
- rc = stack_push(pool, j);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s, EM pool stack push failure %s\n",
- tf_dir_2_str(dir),
- strerror(-rc));
- goto cleanup;
- }
-
- j -= TF_SESSION_EM_ENTRY_SIZE;
- }
-
- if (!stack_is_full(pool)) {
- rc = -EINVAL;
- TFP_DRV_LOG(ERR,
- "%s, EM pool stack failure %s\n",
- tf_dir_2_str(dir),
- strerror(-rc));
- goto cleanup;
- }
-
- return 0;
-cleanup:
- tfp_free((void *)parms.mem_va);
- tfp_free((void *)tfs->em_pool[dir]);
- tfs->em_pool[dir] = NULL;
- return rc;
-}
-
-/**
- * Create EM Tbl pool of memory indexes.
- *
- * [in] dir
- * direction
- *
- * Return:
- */
-static void
-tf_free_em_pool(struct tf_session *tfs,
- enum tf_dir dir)
-{
- struct stack *pool = (struct stack *)tfs->em_pool[dir];
- uint32_t *ptr;
-
- if (pool != NULL) {
- ptr = stack_items(pool);
-
- if (ptr != NULL)
- tfp_free(ptr);
-
- tfp_free(pool);
- tfs->em_pool[dir] = NULL;
- }
-}
-#endif /* TF_EM_ALLOC != 1 */
/**
* Insert EM internal entry API
@@ -178,11 +40,7 @@ tf_em_insert_int_entry(struct tf *tfp,
uint8_t rptr_entry = 0;
uint8_t num_of_entries = 0;
struct tf_session *tfs;
-#if (TF_EM_ALLOC == 1)
struct dpool *pool;
-#else
- struct stack *pool;
-#endif
uint32_t index;
/* Retrieve the session information */
@@ -195,7 +53,6 @@ tf_em_insert_int_entry(struct tf *tfp,
return rc;
}
-#if (TF_EM_ALLOC == 1)
pool = (struct dpool *)tfs->em_pool[parms->dir];
index = dpool_alloc(pool, TF_SESSION_EM_ENTRY_SIZE, 0);
if (index == DP_INVALID_INDEX) {
@@ -204,16 +61,6 @@ tf_em_insert_int_entry(struct tf *tfp,
tf_dir_2_str(parms->dir));
return -1;
}
-#else
- pool = (struct stack *)tfs->em_pool[parms->dir];
- rc = stack_pop(pool, &index);
- if (rc) {
- PMD_DRV_LOG(ERR,
- "%s, EM entry index allocation failed\n",
- tf_dir_2_str(parms->dir));
- return rc;
- }
-#endif
rptr_index = index;
@@ -224,11 +71,7 @@ tf_em_insert_int_entry(struct tf *tfp,
&num_of_entries);
if (rc) {
/* Free the allocated index before returning */
-#if (TF_EM_ALLOC == 1)
dpool_free(pool, index);
-#else
- stack_push(pool, index);
-#endif
return -1;
}
TF_SET_GFID(gfid,
@@ -264,11 +107,7 @@ tf_em_delete_int_entry(struct tf *tfp,
{
int rc = 0;
struct tf_session *tfs;
-#if (TF_EM_ALLOC == 1)
struct dpool *pool;
-#else
- struct stack *pool;
-#endif
/* Retrieve the session information */
rc = tf_session_get_session(tfp, &tfs);
if (rc) {
@@ -283,19 +122,13 @@ tf_em_delete_int_entry(struct tf *tfp,
/* Return resource to pool */
if (rc == 0) {
-#if (TF_EM_ALLOC == 1)
pool = (struct dpool *)tfs->em_pool[parms->dir];
dpool_free(pool, parms->index);
-#else
- pool = (struct stack *)tfs->em_pool[parms->dir];
- stack_push(pool, parms->index);
-#endif
}
return rc;
}
-#if (TF_EM_ALLOC == 1)
static int
tf_em_move_callback(void *user_data,
uint64_t entry_data,
@@ -342,7 +175,6 @@ tf_em_move_callback(void *user_data,
return rc;
}
-#endif
int
tf_em_int_bind(struct tf *tfp,
@@ -434,7 +266,7 @@ tf_em_int_bind(struct tf *tfp,
tf_dir_2_str(i));
return rc;
}
-#if (TF_EM_ALLOC == 1)
+
/*
* Allocate stack pool
*/
@@ -460,12 +292,6 @@ tf_em_int_bind(struct tf *tfp,
7,
(void *)tfp,
tf_em_move_callback);
-#else
- rc = tf_create_em_pool(tfs,
- i,
- iparms.info->entry.stride,
- iparms.info->entry.start);
-#endif
/* Logging handled in tf_create_em_pool */
if (rc)
return rc;
@@ -501,11 +327,7 @@ tf_em_int_unbind(struct tf *tfp)
if (!tf_session_is_shared_session(tfs)) {
for (i = 0; i < TF_DIR_MAX; i++)
-#if (TF_EM_ALLOC == 1)
dpool_free_all(tfs->em_pool[i]);
-#else
- tf_free_em_pool(tfs, i);
-#endif
}
rc = tf_session_get_db(tfp, TF_MODULE_TYPE_EM, &em_db_ptr);
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v2 03/13] net/bnxt: add flow meter drop counter support
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 00/13] enhancements to host based flow table management Venkat Duvvuru
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 01/13] net/bnxt: tf core index table updates Venkat Duvvuru
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 02/13] net/bnxt: enable dpool allocator Venkat Duvvuru
@ 2021-09-08 5:06 ` Venkat Duvvuru
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 04/13] net/bnxt: add Thor SRAM mgr model Venkat Duvvuru
` (11 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-08 5:06 UTC (permalink / raw)
To: dev; +Cc: Jay Ding
From: Jay Ding <jay.ding@broadcom.com>
- Add flow meter drop counter support for Thor.
Signed-off-by: Jay Ding <jay.ding@broadcom.com>
Reviewed-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/tf_core/cfa_resource_types.h | 5 +-
drivers/net/bnxt/tf_core/tf_core.h | 8 +-
drivers/net/bnxt/tf_core/tf_device_p58.c | 1 +
drivers/net/bnxt/tf_core/tf_device_p58.h | 14 ++++
drivers/net/bnxt/tf_core/tf_tbl.c | 74 +++++++++++--------
drivers/net/bnxt/tf_core/tf_util.c | 2 +
6 files changed, 68 insertions(+), 36 deletions(-)
diff --git a/drivers/net/bnxt/tf_core/cfa_resource_types.h b/drivers/net/bnxt/tf_core/cfa_resource_types.h
index cbab0d0078..36a55d4e17 100644
--- a/drivers/net/bnxt/tf_core/cfa_resource_types.h
+++ b/drivers/net/bnxt/tf_core/cfa_resource_types.h
@@ -104,10 +104,11 @@
#define CFA_RESOURCE_TYPE_P58_WC_FKB 0x12UL
/* VEB TCAM */
#define CFA_RESOURCE_TYPE_P58_VEB_TCAM 0x13UL
+/* Metadata */
+#define CFA_RESOURCE_TYPE_P58_METADATA 0x14UL
/* Meter drop counter */
#define CFA_RESOURCE_TYPE_P58_METER_DROP_CNT 0x15UL
-#define CFA_RESOURCE_TYPE_P58_LAST CFA_RESOURCE_TYPE_P58_METER_DROP_CNT
-
+#define CFA_RESOURCE_TYPE_P58_LAST CFA_RESOURCE_TYPE_P58_METER_DROP_CNT
/* Multicast Group */
#define CFA_RESOURCE_TYPE_P45_MCG 0x0UL
diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h
index 7e0cdf7e0d..af8d13bd7e 100644
--- a/drivers/net/bnxt/tf_core/tf_core.h
+++ b/drivers/net/bnxt/tf_core/tf_core.h
@@ -283,9 +283,9 @@ enum tf_tbl_type {
TF_TBL_TYPE_ACT_MODIFY_32B,
/** TH 64B Modify Record */
TF_TBL_TYPE_ACT_MODIFY_64B,
- /** (Future) Meter Profiles */
+ /** Meter Profiles */
TF_TBL_TYPE_METER_PROF,
- /** (Future) Meter Instance */
+ /** Meter Instance */
TF_TBL_TYPE_METER_INST,
/** Wh+/SR/Th Mirror Config */
TF_TBL_TYPE_MIRROR_CONFIG,
@@ -301,6 +301,8 @@ enum tf_tbl_type {
TF_TBL_TYPE_EM_FKB,
/** TH WC Flexible Key builder */
TF_TBL_TYPE_WC_FKB,
+ /** Meter Drop Counter */
+ TF_TBL_TYPE_METER_DROP_CNT,
/* External */
@@ -2194,6 +2196,8 @@ enum tf_global_config_type {
TF_TUNNEL_ENCAP, /**< Tunnel Encap Config(TECT) */
TF_ACTION_BLOCK, /**< Action Block Config(ABCR) */
TF_COUNTER_CFG, /**< Counter Configuration (CNTRS_CTRL) */
+ TF_METER_CFG, /**< Meter Config(ACTP4_FMTCR) */
+ TF_METER_INTERVAL_CFG, /**< Meter Interval Config(FMTCR_INTERVAL) */
TF_GLOBAL_CFG_TYPE_MAX
};
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c
index 808dcb1f77..a492c62bff 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.c
@@ -43,6 +43,7 @@ const char *tf_resource_str_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = {
[CFA_RESOURCE_TYPE_P58_EM_FKB] = "em_fkb ",
[CFA_RESOURCE_TYPE_P58_WC_FKB] = "wc_fkb ",
[CFA_RESOURCE_TYPE_P58_VEB_TCAM] = "veb ",
+ [CFA_RESOURCE_TYPE_P58_METADATA] = "metadata",
};
/**
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h
index 66b0f4e983..8c2e07aa34 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.h
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.h
@@ -75,10 +75,18 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER,
0, 0, 0
},
+ [TF_TBL_TYPE_METER_DROP_CNT] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT,
+ 0, 0, 0
+ },
[TF_TBL_TYPE_MIRROR_CONFIG] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR,
0, 0, 0
},
+ [TF_TBL_TYPE_METADATA] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA,
+ 0, 0, 0
+ },
/* Policy - ARs in bank 1 */
[TF_TBL_TYPE_FULL_ACT_RECORD] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
@@ -194,5 +202,11 @@ struct tf_global_cfg_cfg tf_global_cfg_p58[TF_GLOBAL_CFG_TYPE_MAX] = {
[TF_COUNTER_CFG] = {
TF_GLOBAL_CFG_CFG_HCAPI, TF_COUNTER_CFG
},
+ [TF_METER_CFG] = {
+ TF_GLOBAL_CFG_CFG_HCAPI, TF_METER_CFG
+ },
+ [TF_METER_INTERVAL_CFG] = {
+ TF_GLOBAL_CFG_CFG_HCAPI, TF_METER_INTERVAL_CFG
+ },
};
#endif /* _TF_DEVICE_P58_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c
index e77399c6bd..7011edcd78 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl.c
+++ b/drivers/net/bnxt/tf_core/tf_tbl.c
@@ -374,23 +374,28 @@ tf_tbl_set(struct tf *tfp,
}
}
- /* Verify that the entry has been previously allocated */
- aparms.rm_db = tbl_db->tbl_db[parms->dir];
- aparms.subtype = parms->type;
- TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift);
-
- aparms.allocated = &allocated;
- rc = tf_rm_is_allocated(&aparms);
- if (rc)
- return rc;
+ /* Do not check meter drop counter because it is not allocated
+ * resources
+ */
+ if (parms->type != TF_TBL_TYPE_METER_DROP_CNT) {
+ /* Verify that the entry has been previously allocated */
+ aparms.rm_db = tbl_db->tbl_db[parms->dir];
+ aparms.subtype = parms->type;
+ TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift);
+
+ aparms.allocated = &allocated;
+ rc = tf_rm_is_allocated(&aparms);
+ if (rc)
+ return rc;
- if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
- TFP_DRV_LOG(ERR,
- "%s, Invalid or not allocated index, type:%d, idx:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type,
- parms->idx);
- return -EINVAL;
+ if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
+ TFP_DRV_LOG(ERR,
+ "%s, Invalid or not allocated index, type:%d, idx:%d\n",
+ tf_dir_2_str(parms->dir),
+ parms->type,
+ parms->idx);
+ return -EINVAL;
+ }
}
/* Set the entry */
@@ -477,23 +482,28 @@ tf_tbl_get(struct tf *tfp,
}
}
- /* Verify that the entry has been previously allocated */
- aparms.rm_db = tbl_db->tbl_db[parms->dir];
- aparms.subtype = parms->type;
- TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift);
-
- aparms.allocated = &allocated;
- rc = tf_rm_is_allocated(&aparms);
- if (rc)
- return rc;
+ /* Do not check meter drop counter because it is not allocated
+ * resources.
+ */
+ if (parms->type != TF_TBL_TYPE_METER_DROP_CNT) {
+ /* Verify that the entry has been previously allocated */
+ aparms.rm_db = tbl_db->tbl_db[parms->dir];
+ aparms.subtype = parms->type;
+ TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift);
+
+ aparms.allocated = &allocated;
+ rc = tf_rm_is_allocated(&aparms);
+ if (rc)
+ return rc;
- if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
- TFP_DRV_LOG(ERR,
- "%s, Invalid or not allocated index, type:%d, idx:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type,
- parms->idx);
- return -EINVAL;
+ if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
+ TFP_DRV_LOG(ERR,
+ "%s, Invalid or not allocated index, type:%d, idx:%d\n",
+ tf_dir_2_str(parms->dir),
+ parms->type,
+ parms->idx);
+ return -EINVAL;
+ }
}
/* Set the entry */
diff --git a/drivers/net/bnxt/tf_core/tf_util.c b/drivers/net/bnxt/tf_core/tf_util.c
index e712816209..d100399d0a 100644
--- a/drivers/net/bnxt/tf_core/tf_util.c
+++ b/drivers/net/bnxt/tf_core/tf_util.c
@@ -112,6 +112,8 @@ tf_tbl_type_2_str(enum tf_tbl_type tbl_type)
return "WC Flexible Key Builder";
case TF_TBL_TYPE_EXT:
return "External";
+ case TF_TBL_TYPE_METER_DROP_CNT:
+ return "Meter drop counter";
default:
return "Invalid tbl type";
}
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v2 04/13] net/bnxt: add Thor SRAM mgr model
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 00/13] enhancements to host based flow table management Venkat Duvvuru
` (2 preceding siblings ...)
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 03/13] net/bnxt: add flow meter drop counter support Venkat Duvvuru
@ 2021-09-08 5:06 ` Venkat Duvvuru
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 05/13] net/bnxt: add flow templates support for Thor Venkat Duvvuru
` (10 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-08 5:06 UTC (permalink / raw)
To: dev; +Cc: Farah Smith
From: Farah Smith <farah.smith@broadcom.com>
Add dynamic SRAM manager allocation support.
Signed-off-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com>
Reviewed-by: Peter Spreadborough <peter.spreadborough@broadcom.com>
---
drivers/net/bnxt/tf_core/ll.c | 3 +
drivers/net/bnxt/tf_core/ll.h | 50 +-
drivers/net/bnxt/tf_core/meson.build | 2 +
drivers/net/bnxt/tf_core/tf_core.c | 104 ++-
drivers/net/bnxt/tf_core/tf_core.h | 48 +-
drivers/net/bnxt/tf_core/tf_device.c | 40 +-
drivers/net/bnxt/tf_core/tf_device.h | 133 ++-
drivers/net/bnxt/tf_core/tf_device_p4.c | 75 +-
drivers/net/bnxt/tf_core/tf_device_p4.h | 50 +-
drivers/net/bnxt/tf_core/tf_device_p58.c | 105 ++-
drivers/net/bnxt/tf_core/tf_device_p58.h | 60 +-
drivers/net/bnxt/tf_core/tf_msg.c | 2 +-
drivers/net/bnxt/tf_core/tf_rm.c | 46 +-
drivers/net/bnxt/tf_core/tf_rm.h | 62 +-
drivers/net/bnxt/tf_core/tf_session.c | 56 ++
drivers/net/bnxt/tf_core/tf_session.h | 58 +-
drivers/net/bnxt/tf_core/tf_sram_mgr.c | 971 ++++++++++++++++++++++
drivers/net/bnxt/tf_core/tf_sram_mgr.h | 317 +++++++
drivers/net/bnxt/tf_core/tf_tbl.c | 186 +----
drivers/net/bnxt/tf_core/tf_tbl.h | 15 +-
drivers/net/bnxt/tf_core/tf_tbl_sram.c | 713 ++++++++++++++++
drivers/net/bnxt/tf_core/tf_tbl_sram.h | 154 ++++
drivers/net/bnxt/tf_core/tf_tcam.c | 10 +-
drivers/net/bnxt/tf_core/tf_tcam.h | 7 +
drivers/net/bnxt/tf_core/tf_tcam_shared.c | 28 +-
drivers/net/bnxt/tf_core/tf_util.c | 10 +
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 23 +
meson_options.txt | 2 +
28 files changed, 2978 insertions(+), 352 deletions(-)
create mode 100644 drivers/net/bnxt/tf_core/tf_sram_mgr.c
create mode 100644 drivers/net/bnxt/tf_core/tf_sram_mgr.h
create mode 100644 drivers/net/bnxt/tf_core/tf_tbl_sram.c
create mode 100644 drivers/net/bnxt/tf_core/tf_tbl_sram.h
diff --git a/drivers/net/bnxt/tf_core/ll.c b/drivers/net/bnxt/tf_core/ll.c
index cd168a7970..f2bdff6b9e 100644
--- a/drivers/net/bnxt/tf_core/ll.c
+++ b/drivers/net/bnxt/tf_core/ll.c
@@ -13,6 +13,7 @@ void ll_init(struct ll *ll)
{
ll->head = NULL;
ll->tail = NULL;
+ ll->cnt = 0;
}
/* insert entry in linked list */
@@ -30,6 +31,7 @@ void ll_insert(struct ll *ll,
entry->next->prev = entry;
ll->head = entry->next->prev;
}
+ ll->cnt++;
}
/* delete entry from linked list */
@@ -49,4 +51,5 @@ void ll_delete(struct ll *ll,
entry->prev->next = entry->next;
entry->next->prev = entry->prev;
}
+ ll->cnt--;
}
diff --git a/drivers/net/bnxt/tf_core/ll.h b/drivers/net/bnxt/tf_core/ll.h
index 239478b4f8..9cf8f64ec2 100644
--- a/drivers/net/bnxt/tf_core/ll.h
+++ b/drivers/net/bnxt/tf_core/ll.h
@@ -8,6 +8,8 @@
#ifndef _LL_H_
#define _LL_H_
+#include <stdint.h>
+
/* linked list entry */
struct ll_entry {
struct ll_entry *prev;
@@ -18,6 +20,7 @@ struct ll_entry {
struct ll {
struct ll_entry *head;
struct ll_entry *tail;
+ uint32_t cnt;
};
/**
@@ -28,7 +31,7 @@ struct ll {
void ll_init(struct ll *ll);
/**
- * Linked list insert
+ * Linked list insert head
*
* [in] ll, linked list where element is inserted
* [in] entry, entry to be added
@@ -43,4 +46,49 @@ void ll_insert(struct ll *ll, struct ll_entry *entry);
*/
void ll_delete(struct ll *ll, struct ll_entry *entry);
+/**
+ * Linked list return next entry without deleting it
+ *
+ * Useful in performing search
+ *
+ * [in] Entry in the list
+ */
+static inline struct ll_entry *ll_next(struct ll_entry *entry)
+{
+ return entry->next;
+}
+
+/**
+ * Linked list return the head of the list without removing it
+ *
+ * Useful in performing search
+ *
+ * [in] ll, linked list
+ */
+static inline struct ll_entry *ll_head(struct ll *ll)
+{
+ return ll->head;
+}
+
+/**
+ * Linked list return the tail of the list without removing it
+ *
+ * Useful in performing search
+ *
+ * [in] ll, linked list
+ */
+static inline struct ll_entry *ll_tail(struct ll *ll)
+{
+ return ll->tail;
+}
+
+/**
+ * Linked list return the number of entries in the list
+ *
+ * [in] ll, linked list
+ */
+static inline uint32_t ll_cnt(struct ll *ll)
+{
+ return ll->cnt;
+}
#endif /* _LL_H_ */
diff --git a/drivers/net/bnxt/tf_core/meson.build b/drivers/net/bnxt/tf_core/meson.build
index f28e77ec2e..b7333a431b 100644
--- a/drivers/net/bnxt/tf_core/meson.build
+++ b/drivers/net/bnxt/tf_core/meson.build
@@ -16,6 +16,8 @@ sources += files(
'stack.c',
'tf_rm.c',
'tf_tbl.c',
+ 'tf_tbl_sram.c',
+ 'tf_sram_mgr.c',
'tf_em_common.c',
'tf_em_host.c',
'tf_em_internal.c',
diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c
index 5458f76e2d..936102c804 100644
--- a/drivers/net/bnxt/tf_core/tf_core.c
+++ b/drivers/net/bnxt/tf_core/tf_core.c
@@ -1079,17 +1079,16 @@ tf_alloc_tbl_entry(struct tf *tfp,
strerror(-rc));
return rc;
}
-
- } else {
- if (dev->ops->tf_dev_alloc_tbl == NULL) {
- rc = -EOPNOTSUPP;
+ } else if (dev->ops->tf_dev_is_sram_managed(tfp, parms->type)) {
+ rc = dev->ops->tf_dev_alloc_sram_tbl(tfp, &aparms);
+ if (rc) {
TFP_DRV_LOG(ERR,
- "%s: Operation not supported, rc:%s\n",
+ "%s: SRAM table allocation failed, rc:%s\n",
tf_dir_2_str(parms->dir),
strerror(-rc));
- return -EOPNOTSUPP;
+ return rc;
}
-
+ } else {
rc = dev->ops->tf_dev_alloc_tbl(tfp, &aparms);
if (rc) {
TFP_DRV_LOG(ERR,
@@ -1162,15 +1161,16 @@ tf_free_tbl_entry(struct tf *tfp,
strerror(-rc));
return rc;
}
- } else {
- if (dev->ops->tf_dev_free_tbl == NULL) {
- rc = -EOPNOTSUPP;
+ } else if (dev->ops->tf_dev_is_sram_managed(tfp, parms->type)) {
+ rc = dev->ops->tf_dev_free_sram_tbl(tfp, &fparms);
+ if (rc) {
TFP_DRV_LOG(ERR,
- "%s: Operation not supported, rc:%s\n",
+ "%s: SRAM table free failed, rc:%s\n",
tf_dir_2_str(parms->dir),
strerror(-rc));
- return -EOPNOTSUPP;
+ return rc;
}
+ } else {
rc = dev->ops->tf_dev_free_tbl(tfp, &fparms);
if (rc) {
@@ -1181,7 +1181,6 @@ tf_free_tbl_entry(struct tf *tfp,
return rc;
}
}
-
return 0;
}
@@ -1244,6 +1243,15 @@ tf_set_tbl_entry(struct tf *tfp,
strerror(-rc));
return rc;
}
+ } else if (dev->ops->tf_dev_is_sram_managed(tfp, parms->type)) {
+ rc = dev->ops->tf_dev_set_sram_tbl(tfp, &sparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: SRAM table set failed, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ strerror(-rc));
+ return rc;
+ }
} else {
if (dev->ops->tf_dev_set_tbl == NULL) {
rc = -EOPNOTSUPP;
@@ -1300,28 +1308,39 @@ tf_get_tbl_entry(struct tf *tfp,
strerror(-rc));
return rc;
}
-
- if (dev->ops->tf_dev_get_tbl == NULL) {
- rc = -EOPNOTSUPP;
- TFP_DRV_LOG(ERR,
- "%s: Operation not supported, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(-rc));
- return -EOPNOTSUPP;
- }
-
gparms.dir = parms->dir;
gparms.type = parms->type;
gparms.data = parms->data;
gparms.data_sz_in_bytes = parms->data_sz_in_bytes;
gparms.idx = parms->idx;
- rc = dev->ops->tf_dev_get_tbl(tfp, &gparms);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Table get failed, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(-rc));
- return rc;
+
+ if (dev->ops->tf_dev_is_sram_managed(tfp, parms->type)) {
+ rc = dev->ops->tf_dev_get_sram_tbl(tfp, &gparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: SRAM table get failed, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ strerror(-rc));
+ return rc;
+ }
+ } else {
+ if (dev->ops->tf_dev_get_tbl == NULL) {
+ rc = -EOPNOTSUPP;
+ TFP_DRV_LOG(ERR,
+ "%s: Operation not supported, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ strerror(-rc));
+ return -EOPNOTSUPP;
+ }
+
+ rc = dev->ops->tf_dev_get_tbl(tfp, &gparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Table get failed, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ strerror(-rc));
+ return rc;
+ }
}
return rc;
@@ -1361,6 +1380,13 @@ tf_bulk_get_tbl_entry(struct tf *tfp,
return rc;
}
+ bparms.dir = parms->dir;
+ bparms.type = parms->type;
+ bparms.starting_idx = parms->starting_idx;
+ bparms.num_entries = parms->num_entries;
+ bparms.entry_sz_in_bytes = parms->entry_sz_in_bytes;
+ bparms.physical_mem_addr = parms->physical_mem_addr;
+
if (parms->type == TF_TBL_TYPE_EXT) {
/* Not supported, yet */
rc = -EOPNOTSUPP;
@@ -1370,10 +1396,17 @@ tf_bulk_get_tbl_entry(struct tf *tfp,
strerror(-rc));
return rc;
+ } else if (dev->ops->tf_dev_is_sram_managed(tfp, parms->type)) {
+ rc = dev->ops->tf_dev_get_bulk_sram_tbl(tfp, &bparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: SRAM table bulk get failed, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ strerror(-rc));
+ }
+ return rc;
}
- /* Internal table type processing */
-
if (dev->ops->tf_dev_get_bulk_tbl == NULL) {
rc = -EOPNOTSUPP;
TFP_DRV_LOG(ERR,
@@ -1383,12 +1416,6 @@ tf_bulk_get_tbl_entry(struct tf *tfp,
return -EOPNOTSUPP;
}
- bparms.dir = parms->dir;
- bparms.type = parms->type;
- bparms.starting_idx = parms->starting_idx;
- bparms.num_entries = parms->num_entries;
- bparms.entry_sz_in_bytes = parms->entry_sz_in_bytes;
- bparms.physical_mem_addr = parms->physical_mem_addr;
rc = dev->ops->tf_dev_get_bulk_tbl(tfp, &bparms);
if (rc) {
TFP_DRV_LOG(ERR,
@@ -1397,7 +1424,6 @@ tf_bulk_get_tbl_entry(struct tf *tfp,
strerror(-rc));
return rc;
}
-
return rc;
}
diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h
index af8d13bd7e..fb02c2b161 100644
--- a/drivers/net/bnxt/tf_core/tf_core.h
+++ b/drivers/net/bnxt/tf_core/tf_core.h
@@ -65,6 +65,16 @@ enum tf_ext_mem_chan_type {
TF_EXT_MEM_CHAN_TYPE_MAX
};
+/**
+ * WC TCAM number of slice per row that devices supported
+ */
+enum tf_wc_num_slice {
+ TF_WC_TCAM_1_SLICE_PER_ROW = 1,
+ TF_WC_TCAM_2_SLICE_PER_ROW = 2,
+ TF_WC_TCAM_4_SLICE_PER_ROW = 4,
+ TF_WC_TCAM_8_SLICE_PER_ROW = 8,
+};
+
/**
* EEM record AR helper
*
@@ -670,6 +680,13 @@ struct tf_open_session_parms {
*/
void *bp;
+ /**
+ * [in]
+ *
+ * The number of slices per row for WC TCAM entry.
+ */
+ enum tf_wc_num_slice wc_num_slices;
+
/**
* [out] shared_session_creator
*
@@ -734,8 +751,6 @@ int tf_open_session(struct tf *tfp,
/**
* General internal resource info
*
- * TODO: remove tf_rm_new_entry structure and use this structure
- * internally.
*/
struct tf_resource_info {
uint16_t start;
@@ -1656,12 +1671,7 @@ struct tf_alloc_tbl_entry_parms {
* entry of the indicated type for this TruFlow session.
*
* Allocates an index table record. This function will attempt to
- * allocate an entry or search an index table for a matching entry if
- * search is enabled (only the shadow copy of the table is accessed).
- *
- * If search is not enabled, the first available free entry is
- * returned. If search is enabled and a matching entry to entry_data
- * is found hit is set to TRUE and success is returned.
+ * allocate an index table entry.
*
* External types:
*
@@ -1670,8 +1680,8 @@ struct tf_alloc_tbl_entry_parms {
* Allocates an external index table action record.
*
* NOTE:
- * Implementation of the internals of this function will be a stack with push
- * and pop.
+ * Implementation of the internals of the external function will be a stack with
+ * push and pop.
*
* Returns success or failure code.
*/
@@ -1707,20 +1717,15 @@ struct tf_free_tbl_entry_parms {
*
* Internal types:
*
- * If session has shadow_copy enabled the shadow DB is searched and if
- * found the element ref_cnt is decremented. If ref_cnt goes to
- * zero then the element is returned to the session pool.
- *
- * If the session does not have a shadow DB the element is free'ed and
- * given back to the session pool.
+ * The element is freed and given back to the session pool.
*
* External types:
*
- * Free's an external index table action record.
+ * Frees an external index table action record.
*
* NOTE:
- * Implementation of the internals of this function will be a stack with push
- * and pop.
+ * Implementation of the internals of the external table will be a stack with
+ * push and pop.
*
* Returns success or failure code.
*/
@@ -1764,9 +1769,8 @@ struct tf_set_tbl_entry_parms {
/**
* set index table entry
*
- * Used to insert an application programmed index table entry into a
- * previous allocated table location. A shadow copy of the table
- * is maintained (if enabled) (only for internal objects)
+ * Used to set an application programmed index table entry into a
+ * previous allocated table location.
*
* Returns success or failure code.
*/
diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c
index 498e668b16..25a7166bbb 100644
--- a/drivers/net/bnxt/tf_core/tf_device.c
+++ b/drivers/net/bnxt/tf_core/tf_device.c
@@ -11,10 +11,14 @@
#include "tf_rm.h"
#ifdef TF_TCAM_SHARED
#include "tf_tcam_shared.h"
+#include "tf_tbl_sram.h"
#endif /* TF_TCAM_SHARED */
struct tf;
+/* Number of slices per row for WC TCAM */
+uint16_t g_wc_num_slices_per_row = TF_WC_TCAM_1_SLICE_PER_ROW;
+
/* Forward declarations */
static int tf_dev_unbind_p4(struct tf *tfp);
static int tf_dev_unbind_p58(struct tf *tfp);
@@ -83,7 +87,8 @@ static int
tf_dev_bind_p4(struct tf *tfp,
bool shadow_copy,
struct tf_session_resources *resources,
- struct tf_dev_info *dev_handle)
+ struct tf_dev_info *dev_handle,
+ enum tf_wc_num_slice wc_num_slices)
{
int rc;
int frc;
@@ -131,7 +136,6 @@ tf_dev_bind_p4(struct tf *tfp,
if (rsv_cnt) {
tbl_cfg.num_elements = TF_TBL_TYPE_MAX;
tbl_cfg.cfg = tf_tbl_p4;
- tbl_cfg.shadow_copy = shadow_copy;
tbl_cfg.resources = resources;
rc = tf_tbl_bind(tfp, &tbl_cfg);
if (rc) {
@@ -151,6 +155,7 @@ tf_dev_bind_p4(struct tf *tfp,
tcam_cfg.cfg = tf_tcam_p4;
tcam_cfg.shadow_copy = shadow_copy;
tcam_cfg.resources = resources;
+ tcam_cfg.wc_num_slices = wc_num_slices;
#ifdef TF_TCAM_SHARED
rc = tf_tcam_shared_bind(tfp, &tcam_cfg);
#else /* !TF_TCAM_SHARED */
@@ -369,7 +374,8 @@ static int
tf_dev_bind_p58(struct tf *tfp,
bool shadow_copy,
struct tf_session_resources *resources,
- struct tf_dev_info *dev_handle)
+ struct tf_dev_info *dev_handle,
+ enum tf_wc_num_slice wc_num_slices)
{
int rc;
int frc;
@@ -414,7 +420,6 @@ tf_dev_bind_p58(struct tf *tfp,
if (rsv_cnt) {
tbl_cfg.num_elements = TF_TBL_TYPE_MAX;
tbl_cfg.cfg = tf_tbl_p58;
- tbl_cfg.shadow_copy = shadow_copy;
tbl_cfg.resources = resources;
rc = tf_tbl_bind(tfp, &tbl_cfg);
if (rc) {
@@ -423,6 +428,13 @@ tf_dev_bind_p58(struct tf *tfp,
goto fail;
}
no_rsv_flag = false;
+
+ rc = tf_tbl_sram_bind(tfp);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "SRAM table initialization failure\n");
+ goto fail;
+ }
}
rsv_cnt = tf_dev_reservation_check(TF_TCAM_TBL_TYPE_MAX,
@@ -433,6 +445,7 @@ tf_dev_bind_p58(struct tf *tfp,
tcam_cfg.cfg = tf_tcam_p58;
tcam_cfg.shadow_copy = shadow_copy;
tcam_cfg.resources = resources;
+ tcam_cfg.wc_num_slices = wc_num_slices;
#ifdef TF_TCAM_SHARED
rc = tf_tcam_shared_bind(tfp, &tcam_cfg);
#else /* !TF_TCAM_SHARED */
@@ -565,6 +578,18 @@ tf_dev_unbind_p58(struct tf *tfp)
fail = true;
}
+ /* Unbind the SRAM table prior to table as the table manager
+ * owns and frees the table DB while the SRAM table manager owns
+ * and manages it's internal data structures. SRAM table manager
+ * relies on the table rm_db to exist.
+ */
+ rc = tf_tbl_sram_unbind(tfp);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Device unbind failed, SRAM table\n");
+ fail = true;
+ }
+
rc = tf_tbl_unbind(tfp);
if (rc) {
TFP_DRV_LOG(INFO,
@@ -606,6 +631,7 @@ tf_dev_bind(struct tf *tfp __rte_unused,
enum tf_device_type type,
bool shadow_copy,
struct tf_session_resources *resources,
+ uint16_t wc_num_slices,
struct tf_dev_info *dev_handle)
{
switch (type) {
@@ -615,13 +641,15 @@ tf_dev_bind(struct tf *tfp __rte_unused,
return tf_dev_bind_p4(tfp,
shadow_copy,
resources,
- dev_handle);
+ dev_handle,
+ wc_num_slices);
case TF_DEVICE_TYPE_THOR:
dev_handle->type = type;
return tf_dev_bind_p58(tfp,
shadow_copy,
resources,
- dev_handle);
+ dev_handle,
+ wc_num_slices);
default:
TFP_DRV_LOG(ERR,
"No such device\n");
diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h
index b43cfc6925..9b0c037db0 100644
--- a/drivers/net/bnxt/tf_core/tf_device.h
+++ b/drivers/net/bnxt/tf_core/tf_device.h
@@ -57,6 +57,9 @@ struct tf_dev_info {
* [in] resources
* Pointer to resource allocation information
*
+ * [in] wc_num_slices
+ * Number of slices per row for WC
+ *
* [out] dev_handle
* Device handle
*
@@ -69,6 +72,7 @@ int tf_dev_bind(struct tf *tfp,
enum tf_device_type type,
bool shadow_copy,
struct tf_session_resources *resources,
+ uint16_t wc_num_slices,
struct tf_dev_info *dev_handle);
/**
@@ -139,6 +143,23 @@ struct tf_dev_ops {
uint16_t resource_id,
const char **resource_str);
+ /**
+ * Set the WC TCAM slice information that the device
+ * supports.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] num_slices_per_row
+ * Number of slices per row the device supports
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+ int (*tf_dev_set_tcam_slice_info)(struct tf *tfp,
+ enum tf_wc_num_slice num_slices_per_row);
+
/**
* Retrieves the WC TCAM slice information that the device
* supports.
@@ -241,6 +262,22 @@ struct tf_dev_ops {
int (*tf_dev_get_ident_resc_info)(struct tf *tfp,
struct tf_identifier_resource_info *parms);
+ /**
+ * Indicates whether the index table type is SRAM managed
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] type
+ * Truflow index table type, e.g. TF_TYPE_FULL_ACT_RECORD
+ *
+ * Returns
+ * - (0) if the table is not managed by the SRAM manager
+ * - (1) if the table is managed by the SRAM manager
+ */
+ bool (*tf_dev_is_sram_managed)(struct tf *tfp,
+ enum tf_tbl_type tbl_type);
+
/**
* Get SRAM table information.
*
@@ -289,6 +326,25 @@ struct tf_dev_ops {
int (*tf_dev_alloc_tbl)(struct tf *tfp,
struct tf_tbl_alloc_parms *parms);
+ /**
+ * Allocation of an SRAM index table type element.
+ *
+ * This API allocates the specified table type element from a
+ * device specific table type DB. The allocated element is
+ * returned.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] parms
+ * Pointer to table allocation parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+ int (*tf_dev_alloc_sram_tbl)(struct tf *tfp,
+ struct tf_tbl_alloc_parms *parms);
/**
* Allocation of a external table type element.
*
@@ -327,7 +383,24 @@ struct tf_dev_ops {
*/
int (*tf_dev_free_tbl)(struct tf *tfp,
struct tf_tbl_free_parms *parms);
-
+ /**
+ * Free of an SRAM table type element.
+ *
+ * This API free's a previous allocated table type element from a
+ * device specific table type DB.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] parms
+ * Pointer to table free parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+ int (*tf_dev_free_sram_tbl)(struct tf *tfp,
+ struct tf_tbl_free_parms *parms);
/**
* Free of a external table type element.
*
@@ -385,6 +458,25 @@ struct tf_dev_ops {
int (*tf_dev_set_ext_tbl)(struct tf *tfp,
struct tf_tbl_set_parms *parms);
+ /**
+ * Sets the specified SRAM table type element.
+ *
+ * This API sets the specified element data by invoking the
+ * firmware.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] parms
+ * Pointer to table set parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+ int (*tf_dev_set_sram_tbl)(struct tf *tfp,
+ struct tf_tbl_set_parms *parms);
+
/**
* Retrieves the specified table type element.
*
@@ -404,6 +496,25 @@ struct tf_dev_ops {
int (*tf_dev_get_tbl)(struct tf *tfp,
struct tf_tbl_get_parms *parms);
+ /**
+ * Retrieves the specified SRAM table type element.
+ *
+ * This API retrieves the specified element data by invoking the
+ * firmware.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] parms
+ * Pointer to table get parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+ int (*tf_dev_get_sram_tbl)(struct tf *tfp,
+ struct tf_tbl_get_parms *parms);
+
/**
* Retrieves the specified table type element using 'bulk'
* mechanism.
@@ -424,6 +535,26 @@ struct tf_dev_ops {
int (*tf_dev_get_bulk_tbl)(struct tf *tfp,
struct tf_tbl_get_bulk_parms *parms);
+ /**
+ * Retrieves the specified SRAM table type element using 'bulk'
+ * mechanism.
+ *
+ * This API retrieves the specified element data by invoking the
+ * firmware.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] parms
+ * Pointer to table get bulk parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+ int (*tf_dev_get_bulk_sram_tbl)(struct tf *tfp,
+ struct tf_tbl_get_bulk_parms *parms);
+
/**
* Gets the increment value to add to the shared session resource
* start offset by for each count in the "stride"
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c
index 2e7ccec123..826cd0cdbc 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.c
@@ -118,14 +118,48 @@ tf_dev_p4_get_resource_str(struct tf *tfp __rte_unused,
}
/**
- * Device specific function that retrieves the WC TCAM slices the
+ * Device specific function that set the WC TCAM slices the
* device supports.
*
* [in] tfp
* Pointer to TF handle
*
- * [out] slice_size
- * Pointer to the WC TCAM slice size
+ * [in] num_slices_per_row
+ * The WC TCAM row slice configuration
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+static int
+tf_dev_p4_set_tcam_slice_info(struct tf *tfp __rte_unused,
+ enum tf_wc_num_slice num_slices_per_row)
+{
+ switch (num_slices_per_row) {
+ case TF_WC_TCAM_1_SLICE_PER_ROW:
+ case TF_WC_TCAM_2_SLICE_PER_ROW:
+ case TF_WC_TCAM_4_SLICE_PER_ROW:
+ g_wc_num_slices_per_row = num_slices_per_row;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/**
+ * Device specific function that retrieves the TCAM slices the
+ * device supports.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] type
+ * TF TCAM type
+ *
+ * [in] key_sz
+ * The key size
*
* [out] num_slices_per_row
* Pointer to the WC TCAM row slice configuration
@@ -141,11 +175,10 @@ tf_dev_p4_get_tcam_slice_info(struct tf *tfp __rte_unused,
uint16_t *num_slices_per_row)
{
/* Single slice support */
-#define CFA_P4_WC_TCAM_SLICES_PER_ROW 1
#define CFA_P4_WC_TCAM_SLICE_SIZE 12
if (type == TF_TCAM_TBL_TYPE_WC_TCAM) {
- *num_slices_per_row = CFA_P4_WC_TCAM_SLICES_PER_ROW;
+ *num_slices_per_row = g_wc_num_slices_per_row;
if (key_sz > *num_slices_per_row * CFA_P4_WC_TCAM_SLICE_SIZE)
return -ENOTSUP;
} else { /* for other type of tcam */
@@ -220,26 +253,51 @@ static int tf_dev_p4_word_align(uint16_t size)
return ((((size) + 31) >> 5) * 4);
}
+/**
+ * Indicates whether the index table type is SRAM managed
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] type
+ * Truflow index table type, e.g. TF_TYPE_FULL_ACT_RECORD
+ *
+ * Returns
+ * - (0) if the table is not managed by the SRAM manager
+ * - (1) if the table is managed by the SRAM manager
+ */
+static bool tf_dev_p4_is_sram_managed(struct tf *tfp __rte_unused,
+ enum tf_tbl_type type __rte_unused)
+{
+ return false;
+}
/**
* Truflow P4 device specific functions
*/
const struct tf_dev_ops tf_dev_ops_p4_init = {
.tf_dev_get_max_types = tf_dev_p4_get_max_types,
.tf_dev_get_resource_str = tf_dev_p4_get_resource_str,
+ .tf_dev_set_tcam_slice_info = tf_dev_p4_set_tcam_slice_info,
.tf_dev_get_tcam_slice_info = tf_dev_p4_get_tcam_slice_info,
.tf_dev_alloc_ident = NULL,
.tf_dev_free_ident = NULL,
.tf_dev_search_ident = NULL,
.tf_dev_get_ident_resc_info = NULL,
.tf_dev_get_tbl_info = NULL,
+ .tf_dev_is_sram_managed = tf_dev_p4_is_sram_managed,
.tf_dev_alloc_ext_tbl = NULL,
.tf_dev_alloc_tbl = NULL,
+ .tf_dev_alloc_sram_tbl = NULL,
.tf_dev_free_ext_tbl = NULL,
.tf_dev_free_tbl = NULL,
+ .tf_dev_free_sram_tbl = NULL,
.tf_dev_set_tbl = NULL,
.tf_dev_set_ext_tbl = NULL,
+ .tf_dev_set_sram_tbl = NULL,
.tf_dev_get_tbl = NULL,
+ .tf_dev_get_sram_tbl = NULL,
.tf_dev_get_bulk_tbl = NULL,
+ .tf_dev_get_bulk_sram_tbl = NULL,
.tf_dev_get_shared_tbl_increment = tf_dev_p4_get_shared_tbl_increment,
.tf_dev_get_tbl_resc_info = NULL,
.tf_dev_alloc_tcam = NULL,
@@ -271,20 +329,27 @@ const struct tf_dev_ops tf_dev_ops_p4_init = {
const struct tf_dev_ops tf_dev_ops_p4 = {
.tf_dev_get_max_types = tf_dev_p4_get_max_types,
.tf_dev_get_resource_str = tf_dev_p4_get_resource_str,
+ .tf_dev_set_tcam_slice_info = tf_dev_p4_set_tcam_slice_info,
.tf_dev_get_tcam_slice_info = tf_dev_p4_get_tcam_slice_info,
.tf_dev_alloc_ident = tf_ident_alloc,
.tf_dev_free_ident = tf_ident_free,
.tf_dev_search_ident = tf_ident_search,
.tf_dev_get_ident_resc_info = tf_ident_get_resc_info,
.tf_dev_get_tbl_info = NULL,
+ .tf_dev_is_sram_managed = tf_dev_p4_is_sram_managed,
.tf_dev_alloc_tbl = tf_tbl_alloc,
.tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc,
+ .tf_dev_alloc_sram_tbl = tf_tbl_alloc,
.tf_dev_free_tbl = tf_tbl_free,
.tf_dev_free_ext_tbl = tf_tbl_ext_free,
+ .tf_dev_free_sram_tbl = tf_tbl_free,
.tf_dev_set_tbl = tf_tbl_set,
.tf_dev_set_ext_tbl = tf_tbl_ext_common_set,
+ .tf_dev_set_sram_tbl = NULL,
.tf_dev_get_tbl = tf_tbl_get,
+ .tf_dev_get_sram_tbl = NULL,
.tf_dev_get_bulk_tbl = tf_tbl_bulk_get,
+ .tf_dev_get_bulk_sram_tbl = NULL,
.tf_dev_get_shared_tbl_increment = tf_dev_p4_get_shared_tbl_increment,
.tf_dev_get_tbl_resc_info = tf_tbl_get_resc_info,
#ifdef TF_TCAM_SHARED
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h
index a73ba3cd70..c1357913f1 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.h
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.h
@@ -15,101 +15,101 @@
struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = {
[TF_IDENT_TYPE_L2_CTXT_HIGH] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_L2_CTXT_LOW] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_PROF_FUNC] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_FUNC,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_WC_PROF] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_EM_PROF] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_EM_PROF_ID,
- 0, 0, 0
+ 0, 0
},
};
struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = {
[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_PROF_TCAM] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_TCAM,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_WC_TCAM] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_SP_TCAM] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_TCAM,
- 0, 0, 0
+ 0, 0
},
};
struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = {
[TF_TBL_TYPE_FULL_ACT_RECORD] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_MCAST_GROUPS] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_ENCAP_8B] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_ENCAP_16B] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_ENCAP_64B] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_SP_SMAC] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_STATS_64] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_MODIFY_IPV4] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_METER_PROF] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_METER_INST] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_MIRROR_CONFIG] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR,
- 0, 0, 0
+ 0, 0
},
};
@@ -117,14 +117,14 @@ struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = {
struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = {
[TF_EM_TBL_TYPE_TBL_SCOPE] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_TBL_SCOPE,
- 0, 0, 0
+ 0, 0
},
};
struct tf_rm_element_cfg tf_em_int_p4[TF_EM_TBL_TYPE_MAX] = {
[TF_EM_TBL_TYPE_EM_RECORD] = {
TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_EM_REC,
- 0, 0, 0
+ 0, 0
},
};
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c
index a492c62bff..47d7836a58 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.c
@@ -17,6 +17,7 @@
#include "tf_if_tbl.h"
#include "tfp.h"
#include "tf_msg_common.h"
+#include "tf_tbl_sram.h"
#define TF_DEV_P58_PARIF_MAX 16
#define TF_DEV_P58_PF_MASK 0xfUL
@@ -105,14 +106,48 @@ tf_dev_p58_get_resource_str(struct tf *tfp __rte_unused,
}
/**
- * Device specific function that retrieves the WC TCAM slices the
+ * Device specific function that set the WC TCAM slices the
* device supports.
*
* [in] tfp
* Pointer to TF handle
*
- * [out] slice_size
- * Pointer to the WC TCAM slice size
+ * [in] num_slices_per_row
+ * The WC TCAM row slice configuration
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+static int
+tf_dev_p58_set_tcam_slice_info(struct tf *tfp __rte_unused,
+ enum tf_wc_num_slice num_slices_per_row)
+{
+ switch (num_slices_per_row) {
+ case TF_WC_TCAM_1_SLICE_PER_ROW:
+ case TF_WC_TCAM_2_SLICE_PER_ROW:
+ case TF_WC_TCAM_4_SLICE_PER_ROW:
+ g_wc_num_slices_per_row = num_slices_per_row;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/**
+ * Device specific function that retrieves the TCAM slices the
+ * device supports.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] type
+ * TF TCAM type
+ *
+ * [in] key_sz
+ * The key size
*
* [out] num_slices_per_row
* Pointer to the WC TCAM row slice configuration
@@ -123,16 +158,13 @@ tf_dev_p58_get_resource_str(struct tf *tfp __rte_unused,
*/
static int
tf_dev_p58_get_tcam_slice_info(struct tf *tfp __rte_unused,
- enum tf_tcam_tbl_type type,
- uint16_t key_sz,
- uint16_t *num_slices_per_row)
+ enum tf_tcam_tbl_type type,
+ uint16_t key_sz,
+ uint16_t *num_slices_per_row)
{
-#define CFA_P58_WC_TCAM_SLICES_PER_ROW 1
#define CFA_P58_WC_TCAM_SLICE_SIZE 24
-
if (type == TF_TCAM_TBL_TYPE_WC_TCAM) {
- /* only support single slice key size now */
- *num_slices_per_row = CFA_P58_WC_TCAM_SLICES_PER_ROW;
+ *num_slices_per_row = g_wc_num_slices_per_row;
if (key_sz > *num_slices_per_row * CFA_P58_WC_TCAM_SLICE_SIZE)
return -ENOTSUP;
} else { /* for other type of tcam */
@@ -194,6 +226,44 @@ static int tf_dev_p58_get_shared_tbl_increment(struct tf *tfp __rte_unused,
return 0;
}
+/**
+ * Indicates whether the index table type is SRAM managed
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] type
+ * Truflow index table type, e.g. TF_TYPE_FULL_ACT_RECORD
+ *
+ * Returns
+ * - (0) if the table is not managed by the SRAM manager
+ * - (1) if the table is managed by the SRAM manager
+ */
+static bool tf_dev_p58_is_sram_managed(struct tf *tfp __rte_unused,
+ enum tf_tbl_type type)
+{
+ switch (type) {
+ case TF_TBL_TYPE_FULL_ACT_RECORD:
+ case TF_TBL_TYPE_COMPACT_ACT_RECORD:
+ case TF_TBL_TYPE_ACT_ENCAP_8B:
+ case TF_TBL_TYPE_ACT_ENCAP_16B:
+ case TF_TBL_TYPE_ACT_ENCAP_32B:
+ case TF_TBL_TYPE_ACT_ENCAP_64B:
+ case TF_TBL_TYPE_ACT_SP_SMAC:
+ case TF_TBL_TYPE_ACT_SP_SMAC_IPV4:
+ case TF_TBL_TYPE_ACT_SP_SMAC_IPV6:
+ case TF_TBL_TYPE_ACT_STATS_64:
+ case TF_TBL_TYPE_ACT_MODIFY_IPV4:
+ case TF_TBL_TYPE_ACT_MODIFY_8B:
+ case TF_TBL_TYPE_ACT_MODIFY_16B:
+ case TF_TBL_TYPE_ACT_MODIFY_32B:
+ case TF_TBL_TYPE_ACT_MODIFY_64B:
+ return true;
+ default:
+ return false;
+ }
+}
+
#define TF_DEV_P58_BANK_SZ_64B 2048
/**
* Get SRAM table information.
@@ -265,26 +335,34 @@ static int tf_dev_p58_get_sram_tbl_info(struct tf *tfp __rte_unused,
}
return 0;
}
+
/**
* Truflow P58 device specific functions
*/
const struct tf_dev_ops tf_dev_ops_p58_init = {
.tf_dev_get_max_types = tf_dev_p58_get_max_types,
.tf_dev_get_resource_str = tf_dev_p58_get_resource_str,
+ .tf_dev_set_tcam_slice_info = tf_dev_p58_set_tcam_slice_info,
.tf_dev_get_tcam_slice_info = tf_dev_p58_get_tcam_slice_info,
.tf_dev_alloc_ident = NULL,
.tf_dev_free_ident = NULL,
.tf_dev_search_ident = NULL,
.tf_dev_get_ident_resc_info = NULL,
.tf_dev_get_tbl_info = NULL,
+ .tf_dev_is_sram_managed = tf_dev_p58_is_sram_managed,
.tf_dev_alloc_ext_tbl = NULL,
.tf_dev_alloc_tbl = NULL,
+ .tf_dev_alloc_sram_tbl = NULL,
.tf_dev_free_ext_tbl = NULL,
.tf_dev_free_tbl = NULL,
+ .tf_dev_free_sram_tbl = NULL,
.tf_dev_set_tbl = NULL,
.tf_dev_set_ext_tbl = NULL,
+ .tf_dev_set_sram_tbl = NULL,
.tf_dev_get_tbl = NULL,
+ .tf_dev_get_sram_tbl = NULL,
.tf_dev_get_bulk_tbl = NULL,
+ .tf_dev_get_bulk_sram_tbl = NULL,
.tf_dev_get_shared_tbl_increment = tf_dev_p58_get_shared_tbl_increment,
.tf_dev_get_tbl_resc_info = NULL,
.tf_dev_alloc_tcam = NULL,
@@ -316,20 +394,27 @@ const struct tf_dev_ops tf_dev_ops_p58_init = {
const struct tf_dev_ops tf_dev_ops_p58 = {
.tf_dev_get_max_types = tf_dev_p58_get_max_types,
.tf_dev_get_resource_str = tf_dev_p58_get_resource_str,
+ .tf_dev_set_tcam_slice_info = tf_dev_p58_set_tcam_slice_info,
.tf_dev_get_tcam_slice_info = tf_dev_p58_get_tcam_slice_info,
.tf_dev_alloc_ident = tf_ident_alloc,
.tf_dev_free_ident = tf_ident_free,
.tf_dev_search_ident = tf_ident_search,
.tf_dev_get_ident_resc_info = tf_ident_get_resc_info,
+ .tf_dev_is_sram_managed = tf_dev_p58_is_sram_managed,
.tf_dev_get_tbl_info = tf_dev_p58_get_sram_tbl_info,
.tf_dev_alloc_tbl = tf_tbl_alloc,
+ .tf_dev_alloc_sram_tbl = tf_tbl_sram_alloc,
.tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc,
.tf_dev_free_tbl = tf_tbl_free,
.tf_dev_free_ext_tbl = tf_tbl_ext_free,
+ .tf_dev_free_sram_tbl = tf_tbl_sram_free,
.tf_dev_set_tbl = tf_tbl_set,
.tf_dev_set_ext_tbl = tf_tbl_ext_common_set,
+ .tf_dev_set_sram_tbl = tf_tbl_sram_set,
.tf_dev_get_tbl = tf_tbl_get,
+ .tf_dev_get_sram_tbl = tf_tbl_sram_get,
.tf_dev_get_bulk_tbl = tf_tbl_bulk_get,
+ .tf_dev_get_bulk_sram_tbl = tf_tbl_sram_bulk_get,
.tf_dev_get_shared_tbl_increment = tf_dev_p58_get_shared_tbl_increment,
.tf_dev_get_tbl_resc_info = tf_tbl_get_resc_info,
#ifdef TF_TCAM_SHARED
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h
index 8c2e07aa34..3e8759f2df 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.h
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.h
@@ -15,107 +15,107 @@
struct tf_rm_element_cfg tf_ident_p58[TF_IDENT_TYPE_MAX] = {
[TF_IDENT_TYPE_L2_CTXT_HIGH] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_L2_CTXT_LOW] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_PROF_FUNC] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_PROF_FUNC,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_WC_PROF] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_EM_PROF] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_PROF_ID,
- 0, 0, 0
+ 0, 0
},
};
struct tf_rm_element_cfg tf_tcam_p58[TF_TCAM_TBL_TYPE_MAX] = {
[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_PROF_TCAM] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_PROF_TCAM,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_WC_TCAM] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_TCAM,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_VEB_TCAM] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_VEB_TCAM,
- 0, 0, 0
+ 0, 0
},
};
struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = {
[TF_TBL_TYPE_EM_FKB] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_WC_FKB] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_METER_PROF] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_METER_INST] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_METER_DROP_CNT] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_MIRROR_CONFIG] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_METADATA] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA,
- 0, 0, 0
+ 0, 0
},
/* Policy - ARs in bank 1 */
[TF_TBL_TYPE_FULL_ACT_RECORD] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
- .slices = 1,
+ .slices = 4,
},
[TF_TBL_TYPE_COMPACT_ACT_RECORD] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
- .slices = 1,
+ .slices = 8,
},
/* Policy - Encaps in bank 2 */
[TF_TBL_TYPE_ACT_ENCAP_8B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 1,
+ .slices = 8,
},
[TF_TBL_TYPE_ACT_ENCAP_16B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 1,
+ .slices = 4,
},
[TF_TBL_TYPE_ACT_ENCAP_32B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 1,
+ .slices = 2,
},
[TF_TBL_TYPE_ACT_ENCAP_64B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
@@ -128,19 +128,19 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 1,
+ .slices = 8,
},
[TF_TBL_TYPE_ACT_MODIFY_16B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 1,
+ .slices = 4,
},
[TF_TBL_TYPE_ACT_MODIFY_32B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 1,
+ .slices = 2,
},
[TF_TBL_TYPE_ACT_MODIFY_64B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
@@ -152,32 +152,32 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = {
[TF_TBL_TYPE_ACT_SP_SMAC] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
- .slices = 1,
+ .slices = 8,
},
[TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
- .slices = 1,
+ .slices = 4,
},
[TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
- .slices = 1,
+ .slices = 2,
},
/* Policy - Stats in bank 3 */
[TF_TBL_TYPE_ACT_STATS_64] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3,
- .slices = 1,
+ .slices = 8,
},
};
struct tf_rm_element_cfg tf_em_int_p58[TF_EM_TBL_TYPE_MAX] = {
[TF_EM_TBL_TYPE_EM_RECORD] = {
TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P58_EM_REC,
- 0, 0, 0
+ 0, 0
},
};
diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c
index e07d9168be..0fbb2fe837 100644
--- a/drivers/net/bnxt/tf_core/tf_msg.c
+++ b/drivers/net/bnxt/tf_core/tf_msg.c
@@ -2231,7 +2231,7 @@ tf_msg_get_if_tbl_entry(struct tf *tfp,
if (rc != 0)
return rc;
- tfp_memcpy(params->data, resp.data, req.size);
+ tfp_memcpy(¶ms->data[0], resp.data, req.size);
return 0;
}
diff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c
index 0a46e2a343..03c958a7d6 100644
--- a/drivers/net/bnxt/tf_core/tf_rm.c
+++ b/drivers/net/bnxt/tf_core/tf_rm.c
@@ -34,6 +34,12 @@ struct tf_rm_element {
*/
uint16_t hcapi_type;
+ /**
+ * Resource slices. How many slices will fit in the
+ * resource pool chunk size.
+ */
+ uint8_t slices;
+
/**
* HCAPI RM allocated range information for the element.
*/
@@ -356,12 +362,15 @@ tf_rm_check_residuals(struct tf_rm_new_db *rm_db,
* - - Failure if negative
*/
static int
-tf_rm_update_parent_reservations(struct tf_rm_element_cfg *cfg,
+tf_rm_update_parent_reservations(struct tf *tfp,
+ struct tf_dev_info *dev,
+ struct tf_rm_element_cfg *cfg,
uint16_t *alloc_cnt,
uint16_t num_elements,
uint16_t *req_cnt)
{
int parent, child;
+ const char *type_str;
/* Search through all the elements */
for (parent = 0; parent < num_elements; parent++) {
@@ -377,15 +386,25 @@ tf_rm_update_parent_reservations(struct tf_rm_element_cfg *cfg,
if (alloc_cnt[parent] % cfg[parent].slices)
combined_cnt++;
+ if (alloc_cnt[parent]) {
+ dev->ops->tf_dev_get_resource_str(tfp,
+ cfg[parent].hcapi_type,
+ &type_str);
+ }
+
/* Search again through all the elements */
for (child = 0; child < num_elements; child++) {
/* If this is one of my children */
if (cfg[child].cfg_type ==
TF_RM_ELEM_CFG_HCAPI_BA_CHILD &&
- cfg[child].parent_subtype == parent) {
+ cfg[child].parent_subtype == parent &&
+ alloc_cnt[child]) {
uint16_t cnt = 0;
RTE_ASSERT(cfg[child].slices);
+ dev->ops->tf_dev_get_resource_str(tfp,
+ cfg[child].hcapi_type,
+ &type_str);
/* Increment the parents combined count
* with each child's count adjusted for
* number of slices per RM allocated item.
@@ -479,7 +498,7 @@ tf_rm_create_db(struct tf *tfp,
/* Update the req_cnt based upon the element configuration
*/
- tf_rm_update_parent_reservations(parms->cfg,
+ tf_rm_update_parent_reservations(tfp, dev, parms->cfg,
parms->alloc_cnt,
parms->num_elements,
req_cnt);
@@ -594,6 +613,7 @@ tf_rm_create_db(struct tf *tfp,
db[i].cfg_type = cfg->cfg_type;
db[i].hcapi_type = cfg->hcapi_type;
+ db[i].slices = cfg->slices;
/* Save the parent subtype for later use to find the pool
*/
@@ -1271,6 +1291,26 @@ tf_rm_get_hcapi_type(struct tf_rm_get_hcapi_parms *parms)
return 0;
}
+int
+tf_rm_get_slices(struct tf_rm_get_slices_parms *parms)
+{
+ struct tf_rm_new_db *rm_db;
+ enum tf_rm_elem_cfg_type cfg_type;
+
+ TF_CHECK_PARMS2(parms, parms->rm_db);
+ rm_db = (struct tf_rm_new_db *)parms->rm_db;
+ TF_CHECK_PARMS1(rm_db->db);
+
+ cfg_type = rm_db->db[parms->subtype].cfg_type;
+
+ /* Bail out if not controlled by HCAPI */
+ if (cfg_type == TF_RM_ELEM_CFG_NULL)
+ return -ENOTSUP;
+
+ *parms->slices = rm_db->db[parms->subtype].slices;
+
+ return 0;
+}
int
tf_rm_get_inuse_count(struct tf_rm_get_inuse_count_parms *parms)
diff --git a/drivers/net/bnxt/tf_core/tf_rm.h b/drivers/net/bnxt/tf_core/tf_rm.h
index 8b984112e8..da7d0c7211 100644
--- a/drivers/net/bnxt/tf_core/tf_rm.h
+++ b/drivers/net/bnxt/tf_core/tf_rm.h
@@ -43,16 +43,6 @@ struct tf;
* support module, not called directly.
*/
-/**
- * Resource reservation single entry result. Used when accessing HCAPI
- * RM on the firmware.
- */
-struct tf_rm_new_entry {
- /** Starting index of the allocated resource */
- uint16_t start;
- /** Number of allocated elements */
- uint16_t stride;
-};
/**
* RM Element configuration enumeration. Used by the Device to
@@ -114,10 +104,6 @@ struct tf_rm_element_cfg {
*/
enum tf_rm_elem_cfg_type cfg_type;
- /* If a HCAPI to TF type conversion is required then TF type
- * can be added here.
- */
-
/**
* HCAPI RM Type for the element. Used for TF to HCAPI type
* conversion.
@@ -125,28 +111,19 @@ struct tf_rm_element_cfg {
uint16_t hcapi_type;
/**
- * if cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_CHILD
+ * if cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_CHILD/PARENT
*
* Parent Truflow module subtype associated with this resource type.
*/
uint16_t parent_subtype;
/**
- * if cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_CHILD
+ * if cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_CHILD/PARENT
*
* Resource slices. How many slices will fit in the
* resource pool chunk size.
*/
uint8_t slices;
-
- /**
- * Pool element divider count
- * If 0 or 1, there is 1:1 correspondence between the RM
- * BA pool resource element and the HCAPI RM firmware
- * resource. If > 1, the RM BA pool element has a 1:n
- * correspondence to the HCAPI RM firmware resource.
- */
- uint8_t divider;
};
/**
@@ -160,7 +137,7 @@ struct tf_rm_alloc_info {
* In case of dynamic allocation support this would have
* to be changed to linked list of tf_rm_entry instead.
*/
- struct tf_rm_new_entry entry;
+ struct tf_resource_info entry;
};
/**
@@ -331,6 +308,25 @@ struct tf_rm_get_hcapi_parms {
*/
uint16_t *hcapi_type;
};
+/**
+ * Get Slices parameters for a single element
+ */
+struct tf_rm_get_slices_parms {
+ /**
+ * [in] RM DB Handle
+ */
+ void *rm_db;
+ /**
+ * [in] TF subtype indicates which DB entry to perform the
+ * action on. (e.g. TF_TBL_TYPE_FULL_ACTION subtype of module
+ * TF_MODULE_TYPE_TABLE)
+ */
+ uint16_t subtype;
+ /**
+ * [in/out] Pointer to number of slices for the given type
+ */
+ uint16_t *slices;
+};
/**
* Get InUse count parameters for single element
@@ -394,6 +390,8 @@ struct tf_rm_check_indexes_in_range_parms {
* @ref tf_rm_get_hcapi_type
*
* @ref tf_rm_get_inuse_count
+ *
+ * @ref tf_rm_get_slice_size
*/
/**
@@ -571,5 +569,17 @@ int tf_rm_get_inuse_count(struct tf_rm_get_inuse_count_parms *parms);
int
tf_rm_check_indexes_in_range(struct tf_rm_check_indexes_in_range_parms *parms);
+/**
+ * Get the number of slices per resource bit allocator for the resource type
+ *
+ * [in] parms
+ * Pointer to get inuse parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int
+tf_rm_get_slices(struct tf_rm_get_slices_parms *parms);
#endif /* TF_RM_NEW_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_session.c b/drivers/net/bnxt/tf_core/tf_session.c
index 90b65c59e6..3e6664e9f2 100644
--- a/drivers/net/bnxt/tf_core/tf_session.c
+++ b/drivers/net/bnxt/tf_core/tf_session.c
@@ -202,6 +202,7 @@ tf_session_create(struct tf *tfp,
parms->open_cfg->device_type,
session->shadow_copy,
&parms->open_cfg->resources,
+ parms->open_cfg->wc_num_slices,
&session->dev);
/* Logging handled by dev_bind */
@@ -705,6 +706,22 @@ tf_session_get_session(struct tf *tfp,
return rc;
}
+int tf_session_get(struct tf *tfp,
+ struct tf_session **tfs,
+ struct tf_dev_info **tfd)
+{
+ int rc;
+ rc = tf_session_get_session_internal(tfp, tfs);
+
+ /* Logging done by tf_session_get_session_internal */
+ if (rc)
+ return rc;
+
+ rc = tf_session_get_device(*tfs, tfd);
+
+ return rc;
+}
+
struct tf_session_client *
tf_session_get_session_client(struct tf_session *tfs,
union tf_session_client_id session_client_id)
@@ -1012,4 +1029,43 @@ tf_session_set_tcam_shared_db(struct tf *tfp,
tfs->tcam_shared_db_handle = tcam_shared_db_handle;
return rc;
}
+
+int
+tf_session_get_sram_db(struct tf *tfp,
+ void **sram_handle)
+{
+ struct tf_session *tfs = NULL;
+ int rc = 0;
+
+ *sram_handle = NULL;
+
+ if (tfp == NULL)
+ return (-EINVAL);
+
+ rc = tf_session_get_session_internal(tfp, &tfs);
+ if (rc)
+ return rc;
+
+ *sram_handle = tfs->sram_handle;
+ return rc;
+}
+
+int
+tf_session_set_sram_db(struct tf *tfp,
+ void *sram_handle)
+{
+ struct tf_session *tfs = NULL;
+ int rc = 0;
+
+ if (tfp == NULL)
+ return (-EINVAL);
+
+ rc = tf_session_get_session_internal(tfp, &tfs);
+ if (rc)
+ return rc;
+
+ tfs->sram_handle = sram_handle;
+ return rc;
+}
+
#endif /* TF_TCAM_SHARED */
diff --git a/drivers/net/bnxt/tf_core/tf_session.h b/drivers/net/bnxt/tf_core/tf_session.h
index d68421cd13..c1d7f70060 100644
--- a/drivers/net/bnxt/tf_core/tf_session.h
+++ b/drivers/net/bnxt/tf_core/tf_session.h
@@ -166,6 +166,10 @@ struct tf_session {
*/
void *tcam_shared_db_handle;
#endif /* TF_TCAM_SHARED */
+ /**
+ * SRAM db reference for the session
+ */
+ void *sram_handle;
};
/**
@@ -278,6 +282,10 @@ struct tf_session_close_session_parms {
*
* @ref tf_session_set_tcam_shared_db
* #endif
+ *
+ * @ref tf_session_get_sram_db
+ *
+ * @ref tf_session_set_sram_db
*/
/**
@@ -435,11 +443,11 @@ tf_session_find_session_client_by_fid(struct tf_session *tfs,
/**
* Looks up the device information from the TF Session.
*
- * [in] tfp
- * Pointer to TF handle
+ * [in] tfs
+ * Pointer to session handle
*
* [out] tfd
- * Pointer pointer to the device
+ * Pointer to the device
*
* Returns
* - (0) if successful.
@@ -448,6 +456,26 @@ tf_session_find_session_client_by_fid(struct tf_session *tfs,
int tf_session_get_device(struct tf_session *tfs,
struct tf_dev_info **tfd);
+/**
+ * Returns the session and the device from the tfp.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [out] tfs
+ * Pointer to the session
+ *
+ * [out] tfd
+ * Pointer to the device
+
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_session_get(struct tf *tfp,
+ struct tf_session **tfs,
+ struct tf_dev_info **tfd);
+
/**
* Looks up the FW Session id the requested TF handle.
*
@@ -614,4 +642,28 @@ int
tf_session_get_tcam_shared_db(struct tf *tfp,
void **tcam_shared_db_handle);
+/**
+ * Set the pointer to the SRAM database
+ *
+ * [in] session, pointer to the session
+ *
+ * Returns:
+ * - the pointer to the parent bnxt struct
+ */
+int
+tf_session_set_sram_db(struct tf *tfp,
+ void *sram_handle);
+
+/**
+ * Get the pointer to the SRAM database
+ *
+ * [in] session, pointer to the session
+ *
+ * Returns:
+ * - the pointer to the parent bnxt struct
+ */
+int
+tf_session_get_sram_db(struct tf *tfp,
+ void **sram_handle);
+
#endif /* _TF_SESSION_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_sram_mgr.c b/drivers/net/bnxt/tf_core/tf_sram_mgr.c
new file mode 100644
index 0000000000..f633a78b25
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/tf_sram_mgr.c
@@ -0,0 +1,971 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019-2021 Broadcom
+ * All rights reserved.
+ */
+#include <stdlib.h>
+#include <stdio.h>
+#include "tf_sram_mgr.h"
+#include "tf_core.h"
+#include "tf_rm.h"
+#include "tf_common.h"
+#include "assert.h"
+#include "tf_util.h"
+#include "tfp.h"
+#if (STATS_CLEAR_ON_READ_SUPPORT == 0)
+#include "tf_msg.h"
+#endif
+/***************************
+ * Internal Data Structures
+ ***************************/
+
+/**
+ * TF SRAM block info
+ *
+ * Contains all the information about a particular 64B SRAM
+ * block and the slices within it.
+ */
+struct tf_sram_block {
+ /* Previous block
+ */
+ struct tf_sram_block *prev;
+ /* Next block
+ */
+ struct tf_sram_block *next;
+
+ /** Bitmap indicating which slices are in use
+ * If a bit is set, it indicates the slice
+ * in the row is in use.
+ */
+ uint8_t in_use_mask;
+
+ /** Block id - this is a 64B offset
+ */
+ uint16_t block_id;
+};
+
+/**
+ * TF SRAM block list
+ *
+ * List of 64B SRAM blocks used for fixed size slices (8, 16, 32, 64B)
+ */
+struct tf_sram_slice_list {
+ /** Pointer to head of linked list of blocks.
+ */
+ struct tf_sram_block *head;
+
+ /** Pointer to tail of linked list of blocks.
+ */
+ struct tf_sram_block *tail;
+
+ /** Total count of blocks
+ */
+ uint32_t cnt;
+
+ /** First non-full block in the list
+ */
+ struct tf_sram_block *first_not_full_block;
+
+ /** Entry slice size for this list
+ */
+ enum tf_sram_slice_size size;
+};
+
+
+/**
+ * TF SRAM bank info consists of lists of different slice sizes per bank
+ */
+struct tf_sram_bank_info {
+ struct tf_sram_slice_list slice[TF_SRAM_SLICE_SIZE_MAX];
+};
+
+/**
+ * SRAM banks consist of SRAM bank information
+ */
+struct tf_sram_bank {
+ struct tf_sram_bank_info bank[TF_SRAM_BANK_ID_MAX];
+};
+
+/**
+ * SRAM banks consist of SRAM bank information
+ */
+struct tf_sram {
+ struct tf_sram_bank dir[TF_DIR_MAX];
+};
+
+/**********************
+ * Internal functions
+ **********************/
+
+/**
+ * Get slice size in string format
+ */
+const char
+*tf_sram_slice_2_str(enum tf_sram_slice_size slice_size)
+{
+ switch (slice_size) {
+ case TF_SRAM_SLICE_SIZE_8B:
+ return "8B slice";
+ case TF_SRAM_SLICE_SIZE_16B:
+ return "16B slice";
+ case TF_SRAM_SLICE_SIZE_32B:
+ return "32B slice";
+ case TF_SRAM_SLICE_SIZE_64B:
+ return "64B slice";
+ default:
+ return "Invalid slice size";
+ }
+}
+
+/**
+ * Get bank in string format
+ */
+const char
+*tf_sram_bank_2_str(enum tf_sram_bank_id bank_id)
+{
+ switch (bank_id) {
+ case TF_SRAM_BANK_ID_0:
+ return "bank_0";
+ case TF_SRAM_BANK_ID_1:
+ return "bank_1";
+ case TF_SRAM_BANK_ID_2:
+ return "bank_2";
+ case TF_SRAM_BANK_ID_3:
+ return "bank_3";
+ default:
+ return "Invalid bank_id";
+ }
+}
+
+/**
+ * TF SRAM get slice list
+ */
+static int
+tf_sram_get_slice_list(struct tf_sram *sram,
+ struct tf_sram_slice_list **slice_list,
+ enum tf_sram_slice_size slice_size,
+ enum tf_dir dir,
+ enum tf_sram_bank_id bank_id)
+{
+ int rc = 0;
+
+ TF_CHECK_PARMS2(sram, slice_list);
+
+ *slice_list = &sram->dir[dir].bank[bank_id].slice[slice_size];
+
+ return rc;
+}
+
+uint16_t tf_sram_bank_2_base_offset[TF_SRAM_BANK_ID_MAX] = {
+ 0,
+ 2048,
+ 4096,
+ 6144
+};
+
+/**
+ * Translate a block id and bank_id to an 8B offset
+ */
+static void
+tf_sram_block_id_2_offset(enum tf_sram_bank_id bank_id, uint16_t block_id,
+ uint16_t *offset)
+{
+ *offset = (block_id + tf_sram_bank_2_base_offset[bank_id]) << 3;
+}
+
+/**
+ * Translates an 8B offset and bank_id to a block_id
+ */
+static void
+tf_sram_offset_2_block_id(enum tf_sram_bank_id bank_id, uint16_t offset,
+ uint16_t *block_id, uint16_t *slice_offset)
+{
+ *slice_offset = offset & 0x7;
+ *block_id = ((offset & ~0x7) >> 3) -
+ tf_sram_bank_2_base_offset[bank_id];
+}
+
+/**
+ * Find a matching block_id within the slice list
+ */
+static struct tf_sram_block
+*tf_sram_find_block(uint16_t block_id, struct tf_sram_slice_list *slice_list)
+{
+ uint32_t cnt;
+ struct tf_sram_block *block;
+
+ cnt = slice_list->cnt;
+ block = slice_list->head;
+
+ while (cnt > 0 && block) {
+ if (block->block_id == block_id)
+ return block;
+ block = block->next;
+ cnt--;
+ }
+ return NULL;
+}
+
+/**
+ * Given the current block get the next block within the slice list
+ *
+ * List is not changed.
+ */
+static struct tf_sram_block
+*tf_sram_get_next_block(struct tf_sram_block *block)
+{
+ struct tf_sram_block *nblock;
+
+ if (block != NULL)
+ nblock = block->next;
+ else
+ nblock = NULL;
+ return nblock;
+}
+
+/**
+ * Free an allocated slice from a block and if the block is empty,
+ * return an indication so that the block can be freed.
+ */
+static int
+tf_sram_free_slice(enum tf_sram_slice_size slice_size,
+ uint16_t slice_offset, struct tf_sram_block *block,
+ bool *block_is_empty)
+{
+ int rc = 0;
+ uint8_t shift;
+ uint8_t slice_mask = 0;
+
+ TF_CHECK_PARMS2(block, block_is_empty);
+
+ switch (slice_size) {
+ case TF_SRAM_SLICE_SIZE_8B:
+ shift = slice_offset >> 0;
+ assert(shift < 8);
+ slice_mask = 1 << shift;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_16B:
+ shift = slice_offset >> 1;
+ assert(shift < 4);
+ slice_mask = 1 << shift;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_32B:
+ shift = slice_offset >> 2;
+ assert(shift < 2);
+ slice_mask = 1 << shift;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_64B:
+ default:
+ shift = slice_offset >> 0;
+ assert(shift < 1);
+ slice_mask = 1 << shift;
+ break;
+ }
+
+ if ((block->in_use_mask & slice_mask) == 0) {
+ rc = -EINVAL;
+ TFP_DRV_LOG(ERR, "block_id(0x%x) slice(%d) was not allocated\n",
+ block->block_id, slice_offset);
+ return rc;
+ }
+
+ block->in_use_mask &= ~slice_mask;
+
+ if (block->in_use_mask == 0)
+ *block_is_empty = true;
+ else
+ *block_is_empty = false;
+
+ return rc;
+}
+
+/**
+ * TF SRAM get next slice
+ *
+ * Gets the next slice_offset available in the block
+ * and updates the in_use_mask.
+ */
+static int
+tf_sram_get_next_slice_in_block(struct tf_sram_block *block,
+ enum tf_sram_slice_size slice_size,
+ uint16_t *slice_offset,
+ bool *block_is_full)
+{
+ int rc, free_id = -1;
+ uint8_t shift, max_slices, mask, i, full_mask;
+
+ TF_CHECK_PARMS3(block, slice_offset, block_is_full);
+
+ switch (slice_size) {
+ case TF_SRAM_SLICE_SIZE_8B:
+ shift = 0;
+ max_slices = 8;
+ full_mask = 0xff;
+ break;
+ case TF_SRAM_SLICE_SIZE_16B:
+ shift = 1;
+ max_slices = 4;
+ full_mask = 0xf;
+ break;
+ case TF_SRAM_SLICE_SIZE_32B:
+ shift = 2;
+ max_slices = 2;
+ full_mask = 0x3;
+ break;
+ case TF_SRAM_SLICE_SIZE_64B:
+ default:
+ shift = 0;
+ max_slices = 1;
+ full_mask = 1;
+ break;
+ }
+
+ mask = block->in_use_mask;
+
+ for (i = 0; i < max_slices; i++) {
+ if ((mask & 1) == 0) {
+ free_id = i;
+ block->in_use_mask |= 1 << free_id;
+ break;
+ }
+ mask = mask >> 1;
+ }
+
+ if (block->in_use_mask == full_mask)
+ *block_is_full = true;
+ else
+ *block_is_full = false;
+
+
+ if (free_id >= 0) {
+ *slice_offset = free_id << shift;
+ rc = 0;
+ } else {
+ *slice_offset = 0;
+ rc = -ENOMEM;
+ }
+
+ return rc;
+}
+
+/**
+ * TF SRAM get indication as to whether the slice offset is
+ * allocated in the block.
+ *
+ */
+static int
+tf_sram_is_slice_allocated_in_block(struct tf_sram_block *block,
+ enum tf_sram_slice_size slice_size,
+ uint16_t slice_offset,
+ bool *is_allocated)
+{
+ int rc = 0;
+ uint8_t shift;
+ uint8_t slice_mask = 0;
+
+ TF_CHECK_PARMS2(block, is_allocated);
+
+ *is_allocated = false;
+
+ switch (slice_size) {
+ case TF_SRAM_SLICE_SIZE_8B:
+ shift = slice_offset >> 0;
+ assert(shift < 8);
+ slice_mask = 1 << shift;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_16B:
+ shift = slice_offset >> 1;
+ assert(shift < 4);
+ slice_mask = 1 << shift;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_32B:
+ shift = slice_offset >> 2;
+ assert(shift < 2);
+ slice_mask = 1 << shift;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_64B:
+ default:
+ shift = slice_offset >> 0;
+ assert(shift < 1);
+ slice_mask = 1 << shift;
+ break;
+ }
+
+ if ((block->in_use_mask & slice_mask) == 0) {
+ TFP_DRV_LOG(ERR, "block_id(0x%x) slice(%d) was not allocated\n",
+ block->block_id, slice_offset);
+ *is_allocated = false;
+ } else {
+ *is_allocated = true;
+ }
+
+ return rc;
+}
+
+/**
+ * Initialize slice list
+ */
+static void
+tf_sram_init_slice_list(struct tf_sram_slice_list *slice_list,
+ enum tf_sram_slice_size slice_size)
+{
+ slice_list->head = NULL;
+ slice_list->tail = NULL;
+ slice_list->cnt = 0;
+ slice_list->size = slice_size;
+}
+
+/**
+ * Get the block count
+ */
+static uint32_t
+tf_sram_get_block_cnt(struct tf_sram_slice_list *slice_list)
+{
+ return slice_list->cnt;
+}
+
+
+/**
+ * Free a block data structure - does not free to the RM
+ */
+static void
+tf_sram_free_block(struct tf_sram_slice_list *slice_list,
+ struct tf_sram_block *block)
+{
+ if (slice_list->head == block && slice_list->tail == block) {
+ slice_list->head = NULL;
+ slice_list->tail = NULL;
+ } else if (slice_list->head == block) {
+ slice_list->head = block->next;
+ slice_list->head->prev = NULL;
+ } else if (slice_list->tail == block) {
+ slice_list->tail = block->prev;
+ slice_list->tail->next = NULL;
+ } else {
+ block->prev->next = block->next;
+ block->next->prev = block->prev;
+ }
+ tfp_free(block);
+ slice_list->cnt--;
+}
+/**
+ * Free the entire slice_list
+ */
+static void
+tf_sram_free_slice_list(struct tf_sram_slice_list *slice_list)
+{
+ uint32_t i, block_cnt;
+ struct tf_sram_block *nblock, *block;
+
+ block_cnt = tf_sram_get_block_cnt(slice_list);
+ block = slice_list->head;
+
+ for (i = 0; i < block_cnt; i++) {
+ nblock = block->next;
+ tf_sram_free_block(slice_list, block);
+ block = nblock;
+ }
+}
+
+/**
+ * Allocate a single SRAM block from memory and add it to the slice list
+ */
+static struct tf_sram_block
+*tf_sram_alloc_block(struct tf_sram_slice_list *slice_list,
+ uint16_t block_id)
+{
+ struct tf_sram_block *block;
+ struct tfp_calloc_parms cparms;
+ int rc;
+
+ cparms.nitems = 1;
+ cparms.size = sizeof(struct tf_sram_block);
+ cparms.alignment = 0;
+ rc = tfp_calloc(&cparms);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "Failed to allocate block, rc:%s\n",
+ strerror(-rc));
+ return NULL;
+ }
+ block = (struct tf_sram_block *)cparms.mem_va;
+ block->block_id = block_id;
+
+ if (slice_list->head == NULL) {
+ slice_list->head = block;
+ slice_list->tail = block;
+ block->next = NULL;
+ block->prev = NULL;
+ } else {
+ block->next = slice_list->head;
+ block->prev = NULL;
+ block->next->prev = block;
+ slice_list->head = block->next->prev;
+ }
+ slice_list->cnt++;
+ return block;
+}
+
+/**
+ * Find the first not full block in the slice list
+ */
+static void
+tf_sram_find_first_not_full_block(struct tf_sram_slice_list *slice_list,
+ enum tf_sram_slice_size slice_size,
+ struct tf_sram_block **first_not_full_block)
+{
+ struct tf_sram_block *block = slice_list->head;
+ uint8_t slice_mask, mask;
+
+ switch (slice_size) {
+ case TF_SRAM_SLICE_SIZE_8B:
+ slice_mask = 0xff;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_16B:
+ slice_mask = 0xf;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_32B:
+ slice_mask = 0x3;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_64B:
+ default:
+ slice_mask = 0x1;
+ break;
+ }
+
+ *first_not_full_block = NULL;
+
+ while (block) {
+ mask = block->in_use_mask & slice_mask;
+ if (mask != slice_mask) {
+ *first_not_full_block = block;
+ break;
+ }
+ block = block->next;
+ }
+}
+static void
+tf_sram_dump_block(struct tf_sram_block *block)
+{
+ TFP_DRV_LOG(INFO, "block_id(0x%x) in_use_mask(0x%02x)\n",
+ block->block_id,
+ block->in_use_mask);
+}
+
+/**********************
+ * External functions
+ **********************/
+int
+tf_sram_mgr_bind(void **sram_handle)
+{
+ int rc = 0;
+ enum tf_sram_bank_id bank_id;
+ enum tf_sram_slice_size slice_size;
+ struct tf_sram *sram;
+ struct tf_sram_slice_list *slice_list;
+ enum tf_dir dir;
+ struct tfp_calloc_parms cparms;
+
+ TF_CHECK_PARMS1(sram_handle);
+
+ cparms.nitems = 1;
+ cparms.size = sizeof(struct tf_sram);
+ cparms.alignment = 0;
+ rc = tfp_calloc(&cparms);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "Failed to allocate SRAM mgmt data, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ sram = (struct tf_sram *)cparms.mem_va;
+
+ /* For each direction
+ */
+ for (dir = 0; dir < TF_DIR_MAX; dir++) {
+ /* For each bank
+ */
+ for (bank_id = TF_SRAM_BANK_ID_0;
+ bank_id < TF_SRAM_BANK_ID_MAX;
+ bank_id++) {
+ /* Create each sized slice empty list
+ */
+ for (slice_size = TF_SRAM_SLICE_SIZE_8B;
+ slice_size < TF_SRAM_SLICE_SIZE_MAX;
+ slice_size++) {
+ rc = tf_sram_get_slice_list(sram, &slice_list,
+ slice_size, dir,
+ bank_id);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "No SRAM slice list, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ tf_sram_init_slice_list(slice_list, slice_size);
+ }
+ }
+ }
+
+ *sram_handle = sram;
+
+ return rc;
+}
+
+int
+tf_sram_mgr_unbind(void *sram_handle)
+{
+ int rc = 0;
+ struct tf_sram *sram;
+ enum tf_sram_bank_id bank_id;
+ enum tf_sram_slice_size slice_size;
+ enum tf_dir dir;
+ struct tf_sram_slice_list *slice_list;
+
+ TF_CHECK_PARMS1(sram_handle);
+
+ sram = (struct tf_sram *)sram_handle;
+
+ for (dir = 0; dir < TF_DIR_MAX; dir++) {
+ /* For each bank
+ */
+ for (bank_id = TF_SRAM_BANK_ID_0;
+ bank_id < TF_SRAM_BANK_ID_MAX;
+ bank_id++) {
+ /* For each slice size
+ */
+ for (slice_size = TF_SRAM_SLICE_SIZE_8B;
+ slice_size < TF_SRAM_SLICE_SIZE_MAX;
+ slice_size++) {
+ rc = tf_sram_get_slice_list(sram, &slice_list,
+ slice_size, dir,
+ bank_id);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "No SRAM slice list, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ if (tf_sram_get_block_cnt(slice_list))
+ tf_sram_free_slice_list(slice_list);
+ }
+ }
+ }
+
+ tfp_free(sram);
+ sram_handle = NULL;
+
+ /* Freeing of the RM resources is handled by the table manager */
+ return rc;
+}
+
+int tf_sram_mgr_alloc(void *sram_handle,
+ struct tf_sram_mgr_alloc_parms *parms)
+{
+ int rc = 0;
+ struct tf_sram *sram;
+ struct tf_sram_slice_list *slice_list;
+ uint16_t block_id, slice_offset = 0;
+ uint32_t index;
+ struct tf_sram_block *block;
+ struct tf_rm_allocate_parms aparms = { 0 };
+ bool block_is_full;
+ uint16_t block_offset;
+
+ TF_CHECK_PARMS3(sram_handle, parms, parms->sram_offset);
+
+ sram = (struct tf_sram *)sram_handle;
+
+ /* Check the current slice list
+ */
+ rc = tf_sram_get_slice_list(sram, &slice_list, parms->slice_size,
+ parms->dir, parms->bank_id);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "No SRAM slice list, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ /* If the list is empty or all entries are full allocate a new block
+ */
+ if (!slice_list->first_not_full_block) {
+ /* Allocate and insert a new block
+ */
+ aparms.index = &index;
+ aparms.subtype = parms->tbl_type;
+ aparms.rm_db = parms->rm_db;
+ rc = tf_rm_allocate(&aparms);
+ if (rc)
+ return rc;
+
+ block_id = index;
+ block = tf_sram_alloc_block(slice_list, block_id);
+ } else {
+ /* Block exists
+ */
+ block =
+ (struct tf_sram_block *)(slice_list->first_not_full_block);
+ }
+ rc = tf_sram_get_next_slice_in_block(block,
+ parms->slice_size,
+ &slice_offset,
+ &block_is_full);
+
+ /* Find the new first non-full block in the list
+ */
+ tf_sram_find_first_not_full_block(slice_list,
+ parms->slice_size,
+ &slice_list->first_not_full_block);
+
+ tf_sram_block_id_2_offset(parms->bank_id, block->block_id,
+ &block_offset);
+
+ *parms->sram_offset = block_offset + slice_offset;
+ return rc;
+}
+
+int
+tf_sram_mgr_free(void *sram_handle,
+ struct tf_sram_mgr_free_parms *parms)
+{
+ int rc = 0;
+ struct tf_sram *sram;
+ struct tf_sram_slice_list *slice_list;
+ uint16_t block_id, slice_offset;
+ struct tf_sram_block *block;
+ bool block_is_empty;
+ struct tf_rm_free_parms fparms = { 0 };
+
+ TF_CHECK_PARMS2(sram_handle, parms);
+
+ sram = (struct tf_sram *)sram_handle;
+
+ /* Check the current slice list
+ */
+ rc = tf_sram_get_slice_list(sram, &slice_list, parms->slice_size,
+ parms->dir, parms->bank_id);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "No SRAM slice list, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ /* Determine the block id and slice offset from the SRAM offset
+ */
+ tf_sram_offset_2_block_id(parms->bank_id, parms->sram_offset, &block_id,
+ &slice_offset);
+
+ /* Search the list of blocks for the matching block id
+ */
+ block = tf_sram_find_block(block_id, slice_list);
+ if (block == NULL) {
+ TFP_DRV_LOG(ERR, "block not found 0x%x\n", block_id);
+ return rc;
+ }
+
+ /* If found, search for the matching SRAM slice in use.
+ */
+ rc = tf_sram_free_slice(parms->slice_size, slice_offset,
+ block, &block_is_empty);
+ if (rc) {
+ TFP_DRV_LOG(ERR, "Error freeing slice (%s)\n", strerror(-rc));
+ return rc;
+ }
+#if (STATS_CLEAR_ON_READ_SUPPORT == 0)
+ /* If this is a counter, clear it. In the future we need to switch to
+ * using the special access registers on Thor to automatically clear on
+ * read.
+ */
+ /* If this is counter table, clear the entry on free */
+ if (parms->tbl_type == TF_TBL_TYPE_ACT_STATS_64) {
+ uint8_t data[8] = { 0 };
+ uint16_t hcapi_type = 0;
+ struct tf_rm_get_hcapi_parms hparms = { 0 };
+
+ /* Get the hcapi type */
+ hparms.rm_db = parms->rm_db;
+ hparms.subtype = parms->tbl_type;
+ hparms.hcapi_type = &hcapi_type;
+ rc = tf_rm_get_hcapi_type(&hparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Failed type lookup, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->tbl_type),
+ strerror(-rc));
+ return rc;
+ }
+ /* Clear the counter
+ */
+ rc = tf_msg_set_tbl_entry(parms->tfp,
+ parms->dir,
+ hcapi_type,
+ sizeof(data),
+ data,
+ parms->sram_offset);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Set failed, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->tbl_type),
+ strerror(-rc));
+ return rc;
+ }
+ }
+#endif
+ /* If the block is empty, free the block to the RM
+ */
+ if (block_is_empty) {
+ fparms.rm_db = parms->rm_db;
+ fparms.subtype = parms->tbl_type;
+ fparms.index = block_id;
+ rc = tf_rm_free(&fparms);
+
+ if (rc) {
+ TFP_DRV_LOG(ERR, "Free block_id(%d) failed error(%s)\n",
+ block_id, strerror(-rc));
+ }
+ /* Free local entry regardless
+ */
+ tf_sram_free_block(slice_list, block);
+
+ /* Find the next non-full block in the list
+ */
+ tf_sram_find_first_not_full_block(slice_list,
+ parms->slice_size,
+ &slice_list->first_not_full_block);
+ }
+
+ return rc;
+}
+
+int
+tf_sram_mgr_dump(void *sram_handle,
+ struct tf_sram_mgr_dump_parms *parms)
+{
+ int rc = 0;
+ struct tf_sram *sram;
+ struct tf_sram_slice_list *slice_list;
+ uint32_t block_cnt, i;
+ struct tf_sram_block *block;
+
+ TF_CHECK_PARMS2(sram_handle, parms);
+
+ sram = (struct tf_sram *)sram_handle;
+
+ rc = tf_sram_get_slice_list(sram, &slice_list, parms->slice_size,
+ parms->dir, parms->bank_id);
+ if (rc)
+ return rc;
+
+ if (slice_list->cnt || slice_list->first_not_full_block) {
+ TFP_DRV_LOG(INFO, "\n********** %s: %s: %s ***********\n",
+ tf_sram_bank_2_str(parms->bank_id),
+ tf_dir_2_str(parms->dir),
+ tf_sram_slice_2_str(parms->slice_size));
+
+ block_cnt = tf_sram_get_block_cnt(slice_list);
+ TFP_DRV_LOG(INFO, "block_cnt(%d)\n", block_cnt);
+ if (slice_list->first_not_full_block)
+ TFP_DRV_LOG(INFO, "first_not_full_block(0x%x)\n",
+ slice_list->first_not_full_block->block_id);
+ block = slice_list->head;
+ for (i = 0; i < block_cnt; i++) {
+ tf_sram_dump_block(block);
+ block = tf_sram_get_next_block(block);
+ }
+ TFP_DRV_LOG(INFO, "*********************************\n");
+ }
+ return rc;
+}
+/**
+ * Validate an SRAM Slice is allocated
+ *
+ * Validate whether the SRAM slice is allocated
+ *
+ * [in] sram_handle
+ * Pointer to SRAM handle
+ *
+ * [in] parms
+ * Pointer to the SRAM alloc parameters
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ *
+ */
+int tf_sram_mgr_is_allocated(void *sram_handle,
+ struct tf_sram_mgr_is_allocated_parms *parms)
+{
+ int rc = 0;
+ struct tf_sram *sram;
+ struct tf_sram_slice_list *slice_list;
+ uint16_t block_id, slice_offset;
+ struct tf_sram_block *block;
+
+ TF_CHECK_PARMS3(sram_handle, parms, parms->is_allocated);
+
+ sram = (struct tf_sram *)sram_handle;
+
+ /* Check the current slice list
+ */
+ rc = tf_sram_get_slice_list(sram, &slice_list, parms->slice_size,
+ parms->dir, parms->bank_id);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "No SRAM slice list, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ /* If the list is empty, then it cannot be allocated
+ */
+ if (!slice_list->cnt) {
+ TFP_DRV_LOG(ERR, "List is empty for %s:%s:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_sram_slice_2_str(parms->slice_size),
+ tf_sram_bank_2_str(parms->bank_id));
+
+ parms->is_allocated = false;
+ goto done;
+ }
+
+ /* Determine the block id and slice offset from the SRAM offset
+ */
+ tf_sram_offset_2_block_id(parms->bank_id, parms->sram_offset, &block_id,
+ &slice_offset);
+
+ /* Search the list of blocks for the matching block id
+ */
+ block = tf_sram_find_block(block_id, slice_list);
+ if (block == NULL) {
+ TFP_DRV_LOG(ERR, "block not found in list 0x%x\n",
+ parms->sram_offset);
+ parms->is_allocated = false;
+ goto done;
+ }
+
+ rc = tf_sram_is_slice_allocated_in_block(block,
+ parms->slice_size,
+ slice_offset,
+ parms->is_allocated);
+done:
+ return rc;
+}
diff --git a/drivers/net/bnxt/tf_core/tf_sram_mgr.h b/drivers/net/bnxt/tf_core/tf_sram_mgr.h
new file mode 100644
index 0000000000..4abe3fb468
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/tf_sram_mgr.h
@@ -0,0 +1,317 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019-2021 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef _TF_SRAM_MGR_H_
+#define _TF_SRAM_MGR_H_
+
+#include <string.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <ctype.h>
+#include <limits.h>
+#include <errno.h>
+#include "tf_core.h"
+#include "tf_rm.h"
+
+/* When special access registers are used to access the SRAM, stats can be
+ * automatically cleared on read by the hardware. This requires additional
+ * support to be added in the firmware to use these registers for statistics.
+ * The support entails using the special access registers to read the stats.
+ * These are stored in bank 3 currently but may move depending upon the
+ * policy defined in tf_device_p58.h
+ */
+#define STATS_CLEAR_ON_READ_SUPPORT 0
+
+#define TF_SRAM_MGR_BLOCK_SZ_BYTES 64
+#define TF_SRAM_MGR_MIN_SLICE_BYTES 8
+/**
+ * Bank identifier
+ */
+enum tf_sram_bank_id {
+ TF_SRAM_BANK_ID_0, /**< SRAM Bank 0 id */
+ TF_SRAM_BANK_ID_1, /**< SRAM Bank 1 id */
+ TF_SRAM_BANK_ID_2, /**< SRAM Bank 2 id */
+ TF_SRAM_BANK_ID_3, /**< SRAM Bank 3 id */
+ TF_SRAM_BANK_ID_MAX /**< SRAM Bank index limit */
+};
+
+/**
+ * TF slice size.
+ *
+ * A slice is part of a 64B row
+ *
+ * Each slice is a multiple of 8B
+ */
+enum tf_sram_slice_size {
+ TF_SRAM_SLICE_SIZE_8B, /**< 8 byte SRAM slice */
+ TF_SRAM_SLICE_SIZE_16B, /**< 16 byte SRAM slice */
+ TF_SRAM_SLICE_SIZE_32B, /**< 32 byte SRAM slice */
+ TF_SRAM_SLICE_SIZE_64B, /**< 64 byte SRAM slice */
+ TF_SRAM_SLICE_SIZE_MAX /**< slice limit */
+};
+
+
+/** Initialize the SRAM slice manager
+ *
+ * The SRAM slice manager manages slices within 64B rows. Slices are of size
+ * tf_sram_slice_size. This function provides a handle to the SRAM manager
+ * data.
+ *
+ * SRAM manager data may dynamically allocate data upon initialization if
+ * running on the host.
+ *
+ * [in/out] sram_handle
+ * Pointer to SRAM handle
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ *
+ * Returns the handle for the SRAM slice manager
+ */
+int tf_sram_mgr_bind(void **sram_handle);
+
+/** Uninitialize the SRAM slice manager
+ *
+ * Frees any dynamically allocated data structures for SRAM slice management.
+ *
+ * [in] sram_handle
+ * Pointer to SRAM handle
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ */
+int tf_sram_mgr_unbind(void *sram_handle);
+
+/**
+ * tf_sram_mgr_alloc_parms parameter definition
+ */
+struct tf_sram_mgr_alloc_parms {
+ /**
+ * [in] dir
+ */
+ enum tf_dir dir;
+ /**
+ * [in] bank
+ *
+ * the SRAM bank to allocate from
+ */
+ enum tf_sram_bank_id bank_id;
+ /**
+ * [in] slice_size
+ *
+ * the slice size to allocate
+ */
+ enum tf_sram_slice_size slice_size;
+ /**
+ * [in/out] sram_slice
+ *
+ * A pointer to be filled with an 8B sram slice offset
+ */
+ uint16_t *sram_offset;
+ /**
+ * [in] RM DB Handle required for RM allocation
+ */
+ void *rm_db;
+ /**
+ * [in] tf table type
+ */
+ enum tf_tbl_type tbl_type;
+};
+
+/**
+ * Allocate an SRAM Slice
+ *
+ * Allocate an SRAM slice from the indicated bank. If successful an 8B SRAM
+ * offset will be returned. Slices are variable sized. This may result in
+ * a row being allocated from the RM SRAM bank pool if required.
+ *
+ * [in] sram_handle
+ * Pointer to SRAM handle
+ *
+ * [in] parms
+ * Pointer to the SRAM alloc parameters
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ *
+ */
+int tf_sram_mgr_alloc(void *sram_handle,
+ struct tf_sram_mgr_alloc_parms *parms);
+/**
+ * tf_sram_mgr_free_parms parameter definition
+ */
+struct tf_sram_mgr_free_parms {
+ /**
+ * [in] dir
+ */
+ enum tf_dir dir;
+ /**
+ * [in] bank
+ *
+ * the SRAM bank to free to
+ */
+ enum tf_sram_bank_id bank_id;
+ /**
+ * [in] slice_size
+ *
+ * the slice size to be returned
+ */
+ enum tf_sram_slice_size slice_size;
+ /**
+ * [in] sram_offset
+ *
+ * the SRAM slice offset (8B) to be returned
+ */
+ uint16_t sram_offset;
+ /**
+ * [in] RM DB Handle required for RM free
+ */
+ void *rm_db;
+ /**
+ * [in] tf table type
+ */
+ enum tf_tbl_type tbl_type;
+#if (STATS_CLEAR_ON_READ_SUPPORT == 0)
+ /**
+ * [in] tfp
+ *
+ * A pointer to the tf handle
+ */
+ void *tfp;
+#endif
+};
+
+/**
+ * Free an SRAM Slice
+ *
+ * Free an SRAM slice to the indicated bank. This may result in a 64B row
+ * being returned to the RM SRAM bank pool.
+ *
+ * [in] sram_handle
+ * Pointer to SRAM handle
+ *
+ * [in] parms
+ * Pointer to the SRAM free parameters
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ *
+ */
+int tf_sram_mgr_free(void *sram_handle,
+ struct tf_sram_mgr_free_parms *parms);
+
+/**
+ * tf_sram_mgr_dump_parms parameter definition
+ */
+struct tf_sram_mgr_dump_parms {
+ /**
+ * [in] dir
+ */
+ enum tf_dir dir;
+ /**
+ * [in] bank
+ *
+ * the SRAM bank to dump
+ */
+ enum tf_sram_bank_id bank_id;
+ /**
+ * [in] slice_size
+ *
+ * the slice size list to be dumped
+ */
+ enum tf_sram_slice_size slice_size;
+};
+
+/**
+ * Dump a slice list
+ *
+ * Dump the slice list given the SRAM bank and the slice size
+ *
+ * [in] sram_handle
+ * Pointer to SRAM handle
+ *
+ * [in] parms
+ * Pointer to the SRAM free parameters
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ *
+ */
+int tf_sram_mgr_dump(void *sram_handle,
+ struct tf_sram_mgr_dump_parms *parms);
+
+/**
+ * tf_sram_mgr_is_allocated_parms parameter definition
+ */
+struct tf_sram_mgr_is_allocated_parms {
+ /**
+ * [in] dir
+ */
+ enum tf_dir dir;
+ /**
+ * [in] bank
+ *
+ * the SRAM bank to allocate from
+ */
+ enum tf_sram_bank_id bank_id;
+ /**
+ * [in] slice_size
+ *
+ * the slice size which was allocated
+ */
+ enum tf_sram_slice_size slice_size;
+ /**
+ * [in] sram_offset
+ *
+ * The sram slice offset to validate
+ */
+ uint16_t sram_offset;
+ /**
+ * [in/out] is_allocated
+ *
+ * Pointer passed in to be filled with indication of allocation
+ */
+ bool *is_allocated;
+};
+
+/**
+ * Validate an SRAM Slice is allocated
+ *
+ * Validate whether the SRAM slice is allocated
+ *
+ * [in] sram_handle
+ * Pointer to SRAM handle
+ *
+ * [in] parms
+ * Pointer to the SRAM alloc parameters
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ *
+ */
+int tf_sram_mgr_is_allocated(void *sram_handle,
+ struct tf_sram_mgr_is_allocated_parms *parms);
+
+/**
+ * Given the slice size, return a char string
+ */
+const char
+*tf_sram_slice_2_str(enum tf_sram_slice_size slice_size);
+
+/**
+ * Given the bank_id, return a char string
+ */
+const char
+*tf_sram_bank_2_str(enum tf_sram_bank_id bank_id);
+
+#endif /* _TF_SRAM_MGR_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c
index 7011edcd78..0a8720e7b6 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl.c
+++ b/drivers/net/bnxt/tf_core/tf_tbl.c
@@ -16,20 +16,11 @@
#include "tf_session.h"
#include "tf_device.h"
-#define TF_TBL_RM_TO_PTR(new_idx, idx, base, shift) { \
- *(new_idx) = (((idx) + (base)) << (shift)); \
-}
-
-#define TF_TBL_PTR_TO_RM(new_idx, idx, base, shift) { \
- *(new_idx) = (((idx) >> (shift)) - (base)); \
-}
-
struct tf;
-/**
- * Shadow init flag, set on bind and cleared on unbind
- */
-static uint8_t shadow_init;
+#define TF_TBL_RM_TO_PTR(new_idx, idx, base, shift) { \
+ *(new_idx) = (((idx) + (base)) << (shift)); \
+}
int
tf_tbl_bind(struct tf *tfp,
@@ -121,8 +112,6 @@ tf_tbl_unbind(struct tf *tfp)
tbl_db->tbl_db[i] = NULL;
}
- shadow_init = 0;
-
return 0;
}
@@ -135,7 +124,6 @@ tf_tbl_alloc(struct tf *tfp __rte_unused,
struct tf_rm_allocate_parms aparms = { 0 };
struct tf_session *tfs;
struct tf_dev_info *dev;
- uint16_t base = 0, shift = 0;
struct tbl_rm_db *tbl_db;
void *tbl_db_ptr = NULL;
@@ -154,28 +142,12 @@ tf_tbl_alloc(struct tf *tfp __rte_unused,
rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr);
if (rc) {
TFP_DRV_LOG(ERR,
- "Failed to get em_ext_db from session, rc:%s\n",
+ "Failed to get tbl_db from session, rc:%s\n",
strerror(-rc));
return rc;
}
tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
- /* Only get table info if required for the device */
- if (dev->ops->tf_dev_get_tbl_info) {
- rc = dev->ops->tf_dev_get_tbl_info(tfp,
- tbl_db->tbl_db[parms->dir],
- parms->type,
- &base,
- &shift);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed to get table info:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type);
- return rc;
- }
- }
-
/* Allocate requested element */
aparms.rm_db = tbl_db->tbl_db[parms->dir];
aparms.subtype = parms->type;
@@ -183,13 +155,12 @@ tf_tbl_alloc(struct tf *tfp __rte_unused,
rc = tf_rm_allocate(&aparms);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s: Failed allocate, type:%d\n",
+ "%s: Failed allocate, type:%s\n",
tf_dir_2_str(parms->dir),
- parms->type);
+ tf_tbl_type_2_str(parms->type));
return rc;
}
- TF_TBL_RM_TO_PTR(&idx, idx, base, shift);
*parms->idx = idx;
return 0;
@@ -205,7 +176,6 @@ tf_tbl_free(struct tf *tfp __rte_unused,
int allocated = 0;
struct tf_session *tfs;
struct tf_dev_info *dev;
- uint16_t base = 0, shift = 0;
struct tbl_rm_db *tbl_db;
void *tbl_db_ptr = NULL;
@@ -230,28 +200,10 @@ tf_tbl_free(struct tf *tfp __rte_unused,
}
tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
- /* Only get table info if required for the device */
- if (dev->ops->tf_dev_get_tbl_info) {
- rc = dev->ops->tf_dev_get_tbl_info(tfp,
- tbl_db->tbl_db[parms->dir],
- parms->type,
- &base,
- &shift);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed to get table info:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type);
- return rc;
- }
- }
-
/* Check if element is in use */
aparms.rm_db = tbl_db->tbl_db[parms->dir];
aparms.subtype = parms->type;
-
- TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift);
-
+ aparms.index = parms->idx;
aparms.allocated = &allocated;
rc = tf_rm_is_allocated(&aparms);
if (rc)
@@ -259,9 +211,9 @@ tf_tbl_free(struct tf *tfp __rte_unused,
if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
TFP_DRV_LOG(ERR,
- "%s: Entry already free, type:%d, index:%d\n",
+ "%s: Entry already free, type:%s, index:%d\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
parms->idx);
return -EINVAL;
}
@@ -279,9 +231,9 @@ tf_tbl_free(struct tf *tfp __rte_unused,
rc = tf_rm_get_hcapi_type(&hparms);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Failed type lookup, type:%d, rc:%s\n",
+ "%s, Failed type lookup, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
return rc;
}
@@ -295,9 +247,9 @@ tf_tbl_free(struct tf *tfp __rte_unused,
parms->idx);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Set failed, type:%d, rc:%s\n",
+ "%s, Set failed, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
return rc;
}
@@ -306,15 +258,13 @@ tf_tbl_free(struct tf *tfp __rte_unused,
/* Free requested element */
fparms.rm_db = tbl_db->tbl_db[parms->dir];
fparms.subtype = parms->type;
-
- TF_TBL_PTR_TO_RM(&fparms.index, parms->idx, base, shift);
-
+ fparms.index = parms->idx;
rc = tf_rm_free(&fparms);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s: Free failed, type:%d, index:%d\n",
+ "%s: Free failed, type:%s, index:%d\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
parms->idx);
return rc;
}
@@ -333,7 +283,6 @@ tf_tbl_set(struct tf *tfp,
struct tf_rm_get_hcapi_parms hparms = { 0 };
struct tf_session *tfs;
struct tf_dev_info *dev;
- uint16_t base = 0, shift = 0;
struct tbl_rm_db *tbl_db;
void *tbl_db_ptr = NULL;
@@ -358,21 +307,6 @@ tf_tbl_set(struct tf *tfp,
}
tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
- /* Only get table info if required for the device */
- if (dev->ops->tf_dev_get_tbl_info) {
- rc = dev->ops->tf_dev_get_tbl_info(tfp,
- tbl_db->tbl_db[parms->dir],
- parms->type,
- &base,
- &shift);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed to get table info:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type);
- return rc;
- }
- }
/* Do not check meter drop counter because it is not allocated
* resources
@@ -381,19 +315,18 @@ tf_tbl_set(struct tf *tfp,
/* Verify that the entry has been previously allocated */
aparms.rm_db = tbl_db->tbl_db[parms->dir];
aparms.subtype = parms->type;
- TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift);
-
aparms.allocated = &allocated;
+ aparms.index = parms->idx;
rc = tf_rm_is_allocated(&aparms);
if (rc)
return rc;
if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
TFP_DRV_LOG(ERR,
- "%s, Invalid or not allocated index, type:%d, idx:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type,
- parms->idx);
+ "%s, Invalid or not allocated, type:%s, idx:%d\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->idx);
return -EINVAL;
}
}
@@ -405,9 +338,9 @@ tf_tbl_set(struct tf *tfp,
rc = tf_rm_get_hcapi_type(&hparms);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Failed type lookup, type:%d, rc:%s\n",
+ "%s, Failed type lookup, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
return rc;
}
@@ -420,9 +353,9 @@ tf_tbl_set(struct tf *tfp,
parms->idx);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Set failed, type:%d, rc:%s\n",
+ "%s, Set failed, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
return rc;
}
@@ -441,7 +374,6 @@ tf_tbl_get(struct tf *tfp,
struct tf_rm_get_hcapi_parms hparms = { 0 };
struct tf_session *tfs;
struct tf_dev_info *dev;
- uint16_t base = 0, shift = 0;
struct tbl_rm_db *tbl_db;
void *tbl_db_ptr = NULL;
@@ -466,22 +398,6 @@ tf_tbl_get(struct tf *tfp,
}
tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
- /* Only get table info if required for the device */
- if (dev->ops->tf_dev_get_tbl_info) {
- rc = dev->ops->tf_dev_get_tbl_info(tfp,
- tbl_db->tbl_db[parms->dir],
- parms->type,
- &base,
- &shift);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed to get table info:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type);
- return rc;
- }
- }
-
/* Do not check meter drop counter because it is not allocated
* resources.
*/
@@ -489,8 +405,7 @@ tf_tbl_get(struct tf *tfp,
/* Verify that the entry has been previously allocated */
aparms.rm_db = tbl_db->tbl_db[parms->dir];
aparms.subtype = parms->type;
- TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift);
-
+ aparms.index = parms->idx;
aparms.allocated = &allocated;
rc = tf_rm_is_allocated(&aparms);
if (rc)
@@ -498,9 +413,9 @@ tf_tbl_get(struct tf *tfp,
if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
TFP_DRV_LOG(ERR,
- "%s, Invalid or not allocated index, type:%d, idx:%d\n",
+ "%s, Invalid or not allocated index, type:%s, idx:%d\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
parms->idx);
return -EINVAL;
}
@@ -513,9 +428,9 @@ tf_tbl_get(struct tf *tfp,
rc = tf_rm_get_hcapi_type(&hparms);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Failed type lookup, type:%d, rc:%s\n",
+ "%s, Failed type lookup, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
return rc;
}
@@ -529,9 +444,9 @@ tf_tbl_get(struct tf *tfp,
parms->idx);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Get failed, type:%d, rc:%s\n",
+ "%s, Get failed, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
return rc;
}
@@ -549,7 +464,6 @@ tf_tbl_bulk_get(struct tf *tfp,
struct tf_rm_check_indexes_in_range_parms cparms = { 0 };
struct tf_session *tfs;
struct tf_dev_info *dev;
- uint16_t base = 0, shift = 0;
struct tbl_rm_db *tbl_db;
void *tbl_db_ptr = NULL;
@@ -574,40 +488,21 @@ tf_tbl_bulk_get(struct tf *tfp,
}
tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
- /* Only get table info if required for the device */
- if (dev->ops->tf_dev_get_tbl_info) {
- rc = dev->ops->tf_dev_get_tbl_info(tfp,
- tbl_db->tbl_db[parms->dir],
- parms->type,
- &base,
- &shift);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed to get table info:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type);
- return rc;
- }
- }
-
/* Verify that the entries are in the range of reserved resources. */
cparms.rm_db = tbl_db->tbl_db[parms->dir];
cparms.subtype = parms->type;
-
- TF_TBL_PTR_TO_RM(&cparms.starting_index, parms->starting_idx,
- base, shift);
-
cparms.num_entries = parms->num_entries;
+ cparms.starting_index = parms->starting_idx;
rc = tf_rm_check_indexes_in_range(&cparms);
if (rc) {
TFP_DRV_LOG(ERR,
"%s, Invalid or %d index starting from %d"
- " not in range, type:%d",
+ " not in range, type:%s",
tf_dir_2_str(parms->dir),
parms->starting_idx,
parms->num_entries,
- parms->type);
+ tf_tbl_type_2_str(parms->type));
return rc;
}
@@ -617,9 +512,9 @@ tf_tbl_bulk_get(struct tf *tfp,
rc = tf_rm_get_hcapi_type(&hparms);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Failed type lookup, type:%d, rc:%s\n",
+ "%s, Failed type lookup, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
return rc;
}
@@ -634,9 +529,9 @@ tf_tbl_bulk_get(struct tf *tfp,
parms->physical_mem_addr);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Bulk get failed, type:%d, rc:%s\n",
+ "%s, Bulk get failed, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
}
@@ -653,9 +548,9 @@ tf_tbl_get_resc_info(struct tf *tfp,
struct tf_rm_get_alloc_info_parms ainfo;
void *tbl_db_ptr = NULL;
struct tbl_rm_db *tbl_db;
- uint16_t base = 0, shift = 0;
struct tf_dev_info *dev;
struct tf_session *tfs;
+ uint16_t base = 0, shift = 0;
TF_CHECK_PARMS2(tfp, tbl);
@@ -677,7 +572,6 @@ tf_tbl_get_resc_info(struct tf *tfp,
tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
- /* check if reserved resource for WC is multiple of num_slices */
for (d = 0; d < TF_DIR_MAX; d++) {
ainfo.rm_db = tbl_db->tbl_db[d];
dinfo = tbl[d].info;
diff --git a/drivers/net/bnxt/tf_core/tf_tbl.h b/drivers/net/bnxt/tf_core/tf_tbl.h
index 7e1107ffe7..2483718e5d 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl.h
+++ b/drivers/net/bnxt/tf_core/tf_tbl.h
@@ -28,14 +28,6 @@ struct tf_tbl_cfg_parms {
* Table Type element configuration array
*/
struct tf_rm_element_cfg *cfg;
- /**
- * Shadow table type configuration array
- */
- struct tf_shadow_tbl_cfg *shadow_cfg;
- /**
- * Boolean controlling the request shadow copy.
- */
- bool shadow_copy;
/**
* Session resource allocations
*/
@@ -197,8 +189,6 @@ struct tbl_rm_db {
*
* @ref tf_tbl_free
*
- * @ref tf_tbl_alloc_search
- *
* @ref tf_tbl_set
*
* @ref tf_tbl_get
@@ -255,10 +245,7 @@ int tf_tbl_alloc(struct tf *tfp,
struct tf_tbl_alloc_parms *parms);
/**
- * Free's the requested table type and returns it to the DB. If shadow
- * DB is enabled its searched first and if found the element refcount
- * is decremented. If refcount goes to 0 then its returned to the
- * table type DB.
+ * Frees the requested table type and returns it to the DB.
*
* [in] tfp
* Pointer to TF handle, used for HCAPI communication
diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.c b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
new file mode 100644
index 0000000000..ea10afecb6
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
@@ -0,0 +1,713 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019-2021 Broadcom
+ * All rights reserved.
+ */
+
+/* Truflow Table APIs and supporting code */
+
+#include <rte_common.h>
+
+#include "tf_tbl.h"
+#include "tf_tbl_sram.h"
+#include "tf_sram_mgr.h"
+#include "tf_common.h"
+#include "tf_rm.h"
+#include "tf_util.h"
+#include "tf_msg.h"
+#include "tfp.h"
+#include "tf_session.h"
+#include "tf_device.h"
+#include "cfa_resource_types.h"
+
+#define DBG_SRAM 0
+
+/**
+ * tf_sram_tbl_get_info_parms parameter definition
+ */
+struct tf_tbl_sram_get_info_parms {
+ /**
+ * [in] table RM database
+ */
+ void *rm_db;
+ /**
+ * [in] Receive or transmit direction
+ */
+ enum tf_dir dir;
+ /**
+ * [in] table_type
+ *
+ * the TF index table type
+ */
+ enum tf_tbl_type tbl_type;
+ /**
+ * [out] bank
+ *
+ * The SRAM bank associated with the type
+ */
+ enum tf_sram_bank_id bank_id;
+ /**
+ * [out] slice_size
+ *
+ * the slice size for the indicated table type
+ */
+ enum tf_sram_slice_size slice_size;
+};
+
+/**
+ * Translate HCAPI type to SRAM Manager bank
+ */
+const uint16_t tf_tbl_sram_hcapi_2_bank[CFA_RESOURCE_TYPE_P58_LAST] = {
+ [CFA_RESOURCE_TYPE_P58_SRAM_BANK_0] = TF_SRAM_BANK_ID_0,
+ [CFA_RESOURCE_TYPE_P58_SRAM_BANK_1] = TF_SRAM_BANK_ID_1,
+ [CFA_RESOURCE_TYPE_P58_SRAM_BANK_2] = TF_SRAM_BANK_ID_2,
+ [CFA_RESOURCE_TYPE_P58_SRAM_BANK_3] = TF_SRAM_BANK_ID_3
+};
+
+#define TF_TBL_SRAM_SLICES_MAX \
+ (TF_SRAM_MGR_BLOCK_SZ_BYTES / TF_SRAM_MGR_MIN_SLICE_BYTES)
+/**
+ * Translate HCAPI type to SRAM Manager bank
+ */
+const uint8_t tf_tbl_sram_slices_2_size[TF_TBL_SRAM_SLICES_MAX + 1] = {
+ [0] = TF_SRAM_SLICE_SIZE_64B, /* if 0 slices assume 1 64B block */
+ [1] = TF_SRAM_SLICE_SIZE_64B, /* 1 slice per 64B block */
+ [2] = TF_SRAM_SLICE_SIZE_32B, /* 2 slices per 64B block */
+ [4] = TF_SRAM_SLICE_SIZE_16B, /* 4 slices per 64B block */
+ [8] = TF_SRAM_SLICE_SIZE_8B /* 8 slices per 64B block */
+};
+
+/**
+ * Get SRAM Table Information for a given index table type
+ *
+ *
+ * [in] sram_handle
+ * Pointer to SRAM handle
+ *
+ * [in] parms
+ * Pointer to the SRAM get info parameters
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ *
+ */
+static int tf_tbl_sram_get_info(struct tf_tbl_sram_get_info_parms *parms)
+{
+ int rc = 0;
+ uint16_t hcapi_type;
+ uint16_t slices;
+ struct tf_rm_get_hcapi_parms hparms;
+ struct tf_rm_get_slices_parms sparms;
+
+ hparms.rm_db = parms->rm_db;
+ hparms.subtype = parms->tbl_type;
+ hparms.hcapi_type = &hcapi_type;
+
+ rc = tf_rm_get_hcapi_type(&hparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get hcapi_type %s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->tbl_type),
+ strerror(-rc));
+ return rc;
+ }
+ parms->bank_id = tf_tbl_sram_hcapi_2_bank[hcapi_type];
+
+ sparms.rm_db = parms->rm_db;
+ sparms.subtype = parms->tbl_type;
+ sparms.slices = &slices;
+
+ rc = tf_rm_get_slices(&sparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get slice cnt %s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->tbl_type),
+ strerror(-rc));
+ return rc;
+ }
+ if (slices)
+ parms->slice_size = tf_tbl_sram_slices_2_size[slices];
+
+ TFP_DRV_LOG(INFO,
+ "(%s) bank(%s) slice_size(%s)\n",
+ tf_tbl_type_2_str(parms->tbl_type),
+ tf_sram_bank_2_str(parms->bank_id),
+ tf_sram_slice_2_str(parms->slice_size));
+ return rc;
+}
+
+int
+tf_tbl_sram_bind(struct tf *tfp __rte_unused)
+{
+ int rc = 0;
+ void *sram_handle = NULL;
+
+ TF_CHECK_PARMS1(tfp);
+
+ rc = tf_sram_mgr_bind(&sram_handle);
+
+ tf_session_set_sram_db(tfp, sram_handle);
+
+ TFP_DRV_LOG(INFO,
+ "SRAM Table - initialized\n");
+
+ return rc;
+}
+
+int
+tf_tbl_sram_unbind(struct tf *tfp __rte_unused)
+{
+ int rc = 0;
+ void *sram_handle = NULL;
+
+ TF_CHECK_PARMS1(tfp);
+
+ rc = tf_session_get_sram_db(tfp, &sram_handle);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get sram_handle from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ if (sram_handle)
+ rc = tf_sram_mgr_unbind(sram_handle);
+
+ TFP_DRV_LOG(INFO,
+ "SRAM Table - deinitialized\n");
+ return rc;
+}
+
+int
+tf_tbl_sram_alloc(struct tf *tfp,
+ struct tf_tbl_alloc_parms *parms)
+{
+ int rc;
+ uint16_t idx;
+ struct tf_session *tfs;
+ struct tf_dev_info *dev;
+ struct tf_tbl_sram_get_info_parms iparms = { 0 };
+ struct tf_sram_mgr_alloc_parms aparms = { 0 };
+ struct tbl_rm_db *tbl_db;
+ void *tbl_db_ptr = NULL;
+ void *sram_handle = NULL;
+
+ TF_CHECK_PARMS2(tfp, parms);
+
+ /* Retrieve the session information */
+ rc = tf_session_get(tfp, &tfs, &dev);
+ if (rc)
+ return rc;
+
+ rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get tbl_db from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
+
+ rc = tf_session_get_sram_db(tfp, &sram_handle);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get sram_handle from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ iparms.rm_db = tbl_db->tbl_db[parms->dir];
+ iparms.dir = parms->dir;
+ iparms.tbl_type = parms->type;
+
+ rc = tf_tbl_sram_get_info(&iparms);
+
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get SRAM info %s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type));
+ return rc;
+ }
+
+ aparms.dir = parms->dir;
+ aparms.bank_id = iparms.bank_id;
+ aparms.slice_size = iparms.slice_size;
+ aparms.sram_offset = &idx;
+ aparms.tbl_type = parms->type;
+ aparms.rm_db = tbl_db->tbl_db[parms->dir];
+
+ rc = tf_sram_mgr_alloc(sram_handle, &aparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to allocate SRAM table:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type));
+ return rc;
+ }
+ *parms->idx = idx;
+
+#if (DBG_SRAM == 1)
+ {
+ struct tf_sram_mgr_dump_parms dparms;
+
+ dparms.dir = parms->dir;
+ dparms.bank_id = iparms.bank_id;
+ dparms.slice_size = iparms.slice_size;
+
+ rc = tf_sram_mgr_dump(sram_handle, &dparms);
+ }
+#endif
+
+ return rc;
+}
+
+int
+tf_tbl_sram_free(struct tf *tfp __rte_unused,
+ struct tf_tbl_free_parms *parms)
+{
+ int rc;
+ struct tf_session *tfs;
+ struct tf_dev_info *dev;
+ struct tbl_rm_db *tbl_db;
+ void *tbl_db_ptr = NULL;
+ struct tf_tbl_sram_get_info_parms iparms = { 0 };
+ struct tf_sram_mgr_free_parms fparms = { 0 };
+ struct tf_sram_mgr_is_allocated_parms aparms = { 0 };
+ bool allocated = false;
+ void *sram_handle = NULL;
+
+ TF_CHECK_PARMS2(tfp, parms);
+
+ /* Retrieve the session information */
+ rc = tf_session_get(tfp, &tfs, &dev);
+ if (rc)
+ return rc;
+
+ rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get em_ext_db from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
+
+ rc = tf_session_get_sram_db(tfp, &sram_handle);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get sram_handle from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ iparms.rm_db = tbl_db->tbl_db[parms->dir];
+ iparms.dir = parms->dir;
+ iparms.tbl_type = parms->type;
+
+ rc = tf_tbl_sram_get_info(&iparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get table info:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type));
+ return rc;
+ }
+
+#if (DBG_SRAM == 1)
+ {
+ struct tf_sram_mgr_dump_parms dparms;
+
+ printf("%s: %s: %s\n", tf_dir_2_str(parms->dir),
+ tf_sram_slice_2_str(iparms.slice_size),
+ tf_sram_bank_2_str(iparms.bank_id));
+
+ dparms.dir = parms->dir;
+ dparms.bank_id = iparms.bank_id;
+ dparms.slice_size = iparms.slice_size;
+
+ rc = tf_sram_mgr_dump(sram_handle, &dparms);
+ }
+#endif
+
+ aparms.sram_offset = parms->idx;
+ aparms.slice_size = iparms.slice_size;
+ aparms.bank_id = iparms.bank_id;
+ aparms.dir = parms->dir;
+ aparms.is_allocated = &allocated;
+
+ rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
+ if (rc || !allocated) {
+ TFP_DRV_LOG(ERR,
+ "%s: Free of invalid entry:%s idx(%d):(%s)\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->idx,
+ strerror(-rc));
+ rc = -ENOMEM;
+ return rc;
+ }
+
+ fparms.rm_db = tbl_db->tbl_db[parms->dir];
+ fparms.tbl_type = parms->type;
+ fparms.sram_offset = parms->idx;
+ fparms.slice_size = iparms.slice_size;
+ fparms.bank_id = iparms.bank_id;
+ fparms.dir = parms->dir;
+#if (STATS_CLEAR_ON_READ_SUPPORT == 0)
+ fparms.tfp = tfp;
+#endif
+ rc = tf_sram_mgr_free(sram_handle, &fparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to free entry:%s idx(%d)\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->idx);
+ return rc;
+ }
+
+
+#if (DBG_SRAM == 1)
+ {
+ struct tf_sram_mgr_dump_parms dparms;
+
+ printf("%s: %s: %s\n", tf_dir_2_str(parms->dir),
+ tf_sram_slice_2_str(iparms.slice_size),
+ tf_sram_bank_2_str(iparms.bank_id));
+
+ dparms.dir = parms->dir;
+ dparms.bank_id = iparms.bank_id;
+ dparms.slice_size = iparms.slice_size;
+
+ rc = tf_sram_mgr_dump(sram_handle, &dparms);
+ }
+#endif
+ return rc;
+}
+
+int
+tf_tbl_sram_set(struct tf *tfp,
+ struct tf_tbl_set_parms *parms)
+{
+ int rc;
+ bool allocated = 0;
+ uint16_t hcapi_type;
+ struct tf_rm_get_hcapi_parms hparms = { 0 };
+ struct tf_session *tfs;
+ struct tf_dev_info *dev;
+ struct tbl_rm_db *tbl_db;
+ void *tbl_db_ptr = NULL;
+ struct tf_tbl_sram_get_info_parms iparms = { 0 };
+ struct tf_sram_mgr_is_allocated_parms aparms = { 0 };
+ void *sram_handle = NULL;
+
+
+ TF_CHECK_PARMS3(tfp, parms, parms->data);
+
+ /* Retrieve the session information */
+ rc = tf_session_get(tfp, &tfs, &dev);
+ if (rc)
+ return rc;
+
+ rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get em_ext_db from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
+
+ rc = tf_session_get_sram_db(tfp, &sram_handle);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get sram_handle from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ iparms.rm_db = tbl_db->tbl_db[parms->dir];
+ iparms.dir = parms->dir;
+ iparms.tbl_type = parms->type;
+
+ rc = tf_tbl_sram_get_info(&iparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get table info:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type));
+ return rc;
+ }
+
+ aparms.sram_offset = parms->idx;
+ aparms.slice_size = iparms.slice_size;
+ aparms.bank_id = iparms.bank_id;
+ aparms.dir = parms->dir;
+ aparms.is_allocated = &allocated;
+ rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
+ if (rc || !allocated) {
+ TFP_DRV_LOG(ERR,
+ "%s: Entry not allocated:%s idx(%d):(%s)\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->idx,
+ strerror(-rc));
+ rc = -ENOMEM;
+ return rc;
+ }
+
+ /* Set the entry */
+ hparms.rm_db = tbl_db->tbl_db[parms->dir];
+ hparms.subtype = parms->type;
+ hparms.hcapi_type = &hcapi_type;
+ rc = tf_rm_get_hcapi_type(&hparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Failed type lookup, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ strerror(-rc));
+ return rc;
+ }
+
+ rc = tf_msg_set_tbl_entry(tfp,
+ parms->dir,
+ hcapi_type,
+ parms->data_sz_in_bytes,
+ parms->data,
+ parms->idx);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Set failed, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ strerror(-rc));
+ return rc;
+ }
+ return rc;
+}
+
+int
+tf_tbl_sram_get(struct tf *tfp,
+ struct tf_tbl_get_parms *parms)
+{
+ int rc;
+ uint16_t hcapi_type;
+ bool allocated = 0;
+ struct tf_rm_get_hcapi_parms hparms = { 0 };
+ struct tf_session *tfs;
+ struct tf_dev_info *dev;
+ struct tbl_rm_db *tbl_db;
+ void *tbl_db_ptr = NULL;
+ struct tf_tbl_sram_get_info_parms iparms = { 0 };
+ struct tf_sram_mgr_is_allocated_parms aparms = { 0 };
+ void *sram_handle = NULL;
+
+ TF_CHECK_PARMS3(tfp, parms, parms->data);
+
+ /* Retrieve the session information */
+ rc = tf_session_get(tfp, &tfs, &dev);
+ if (rc)
+ return rc;
+
+ rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get em_ext_db from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
+
+ rc = tf_session_get_sram_db(tfp, &sram_handle);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get sram_handle from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ iparms.rm_db = tbl_db->tbl_db[parms->dir];
+ iparms.dir = parms->dir;
+ iparms.tbl_type = parms->type;
+
+ rc = tf_tbl_sram_get_info(&iparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get table info:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type));
+ return rc;
+ }
+
+ aparms.sram_offset = parms->idx;
+ aparms.slice_size = iparms.slice_size;
+ aparms.bank_id = iparms.bank_id;
+ aparms.dir = parms->dir;
+ aparms.is_allocated = &allocated;
+
+ rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
+ if (rc || !allocated) {
+ TFP_DRV_LOG(ERR,
+ "%s: Entry not allocated:%s idx(%d):(%s)\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->idx,
+ strerror(-rc));
+ rc = -ENOMEM;
+ return rc;
+ }
+
+ /* Get the entry */
+ hparms.rm_db = tbl_db->tbl_db[parms->dir];
+ hparms.subtype = parms->type;
+ hparms.hcapi_type = &hcapi_type;
+ rc = tf_rm_get_hcapi_type(&hparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Failed type lookup, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ strerror(-rc));
+ return rc;
+ }
+
+ /* Get the entry */
+ rc = tf_msg_get_tbl_entry(tfp,
+ parms->dir,
+ hcapi_type,
+ parms->data_sz_in_bytes,
+ parms->data,
+ parms->idx);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Get failed, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ strerror(-rc));
+ return rc;
+ }
+ return rc;
+}
+
+int
+tf_tbl_sram_bulk_get(struct tf *tfp,
+ struct tf_tbl_get_bulk_parms *parms)
+{
+ int rc;
+ uint16_t hcapi_type;
+ struct tf_rm_get_hcapi_parms hparms = { 0 };
+ struct tf_tbl_sram_get_info_parms iparms = { 0 };
+ struct tf_session *tfs;
+ struct tf_dev_info *dev;
+ struct tbl_rm_db *tbl_db;
+ void *tbl_db_ptr = NULL;
+ uint16_t idx;
+ struct tf_sram_mgr_is_allocated_parms aparms = { 0 };
+ bool allocated = false;
+ void *sram_handle = NULL;
+
+ TF_CHECK_PARMS2(tfp, parms);
+
+ /* Retrieve the session information */
+ rc = tf_session_get(tfp, &tfs, &dev);
+ if (rc)
+ return rc;
+
+ rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get em_ext_db from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
+
+ rc = tf_session_get_sram_db(tfp, &sram_handle);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get sram_handle from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ iparms.rm_db = tbl_db->tbl_db[parms->dir];
+ iparms.dir = parms->dir;
+ iparms.tbl_type = parms->type;
+
+ rc = tf_tbl_sram_get_info(&iparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get table info:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type));
+ return rc;
+ }
+
+ /* Validate the start offset and the end offset is allocated
+ * This API is only used for statistics. 8 Byte entry allocation
+ * is used to verify
+ */
+ aparms.sram_offset = parms->starting_idx;
+ aparms.slice_size = iparms.slice_size;
+ aparms.bank_id = iparms.bank_id;
+ aparms.dir = parms->dir;
+ aparms.is_allocated = &allocated;
+ rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
+ if (rc || !allocated) {
+ TFP_DRV_LOG(ERR,
+ "%s: Entry not allocated:%s starting_idx(%d):(%s)\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->starting_idx,
+ strerror(-rc));
+ rc = -ENOMEM;
+ return rc;
+ }
+ idx = parms->starting_idx + parms->num_entries - 1;
+ aparms.sram_offset = idx;
+ rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
+ if (rc || !allocated) {
+ TFP_DRV_LOG(ERR,
+ "%s: Entry not allocated:%s last_idx(%d):(%s)\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ idx,
+ strerror(-rc));
+ rc = -ENOMEM;
+ return rc;
+ }
+
+ hparms.rm_db = tbl_db->tbl_db[parms->dir];
+ hparms.subtype = parms->type;
+ hparms.hcapi_type = &hcapi_type;
+ rc = tf_rm_get_hcapi_type(&hparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Failed type lookup, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ strerror(-rc));
+ return rc;
+ }
+
+ /* Get the entries */
+ rc = tf_msg_bulk_get_tbl_entry(tfp,
+ parms->dir,
+ hcapi_type,
+ parms->starting_idx,
+ parms->num_entries,
+ parms->entry_sz_in_bytes,
+ parms->physical_mem_addr);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Bulk get failed, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ strerror(-rc));
+ }
+ return rc;
+}
diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.h b/drivers/net/bnxt/tf_core/tf_tbl_sram.h
new file mode 100644
index 0000000000..32001e34a9
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.h
@@ -0,0 +1,154 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019-2021 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef TF_TBL_SRAM_H_
+#define TF_TBL_SRAM_H_
+
+#include "tf_core.h"
+#include "stack.h"
+
+
+/**
+ * The SRAM Table module provides processing of managed SRAM types.
+ */
+
+
+/**
+ * @page tblsram SRAM Table
+ *
+ * @ref tf_tbl_sram_bind
+ *
+ * @ref tf_tbl_sram_unbind
+ *
+ * @ref tf_tbl_sram_alloc
+ *
+ * @ref tf_tbl_sram_free
+ *
+ * @ref tf_tbl_sram_set
+ *
+ * @ref tf_tbl_sram_get
+ *
+ * @ref tf_tbl_sram_bulk_get
+ */
+
+/**
+ * Initializes the Table module with the requested DBs. Must be
+ * invoked as the first thing before any of the access functions.
+ *
+ * [in] tfp
+ * Pointer to TF handle, used for HCAPI communication
+ *
+ * [in] parms
+ * Pointer to Table configuration parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_tbl_sram_bind(struct tf *tfp);
+
+/**
+ * Cleans up the private DBs and releases all the data.
+ *
+ * [in] tfp
+ * Pointer to TF handle, used for HCAPI communication
+ *
+ * [in] parms
+ * Pointer to parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_tbl_sram_unbind(struct tf *tfp);
+
+/**
+ * Allocates the requested table type from the internal RM DB.
+ *
+ * [in] tfp
+ * Pointer to TF handle, used for HCAPI communication
+ *
+ * [in] parms
+ * Pointer to Table allocation parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_tbl_sram_alloc(struct tf *tfp,
+ struct tf_tbl_alloc_parms *parms);
+
+/**
+ * Free's the requested table type and returns it to the DB. If shadow
+ * DB is enabled its searched first and if found the element refcount
+ * is decremented. If refcount goes to 0 then its returned to the
+ * table type DB.
+ *
+ * [in] tfp
+ * Pointer to TF handle, used for HCAPI communication
+ *
+ * [in] parms
+ * Pointer to Table free parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_tbl_sram_free(struct tf *tfp,
+ struct tf_tbl_free_parms *parms);
+
+
+/**
+ * Configures the requested element by sending a firmware request which
+ * then installs it into the device internal structures.
+ *
+ * [in] tfp
+ * Pointer to TF handle, used for HCAPI communication
+ *
+ * [in] parms
+ * Pointer to Table set parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_tbl_sram_set(struct tf *tfp,
+ struct tf_tbl_set_parms *parms);
+
+/**
+ * Retrieves the requested element by sending a firmware request to get
+ * the element.
+ *
+ * [in] tfp
+ * Pointer to TF handle, used for HCAPI communication
+ *
+ * [in] parms
+ * Pointer to Table get parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_tbl_sram_get(struct tf *tfp,
+ struct tf_tbl_get_parms *parms);
+
+/**
+ * Retrieves bulk block of elements by sending a firmware request to
+ * get the elements.
+ *
+ * [in] tfp
+ * Pointer to TF handle, used for HCAPI communication
+ *
+ * [in] parms
+ * Pointer to Table get bulk parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_tbl_sram_bulk_get(struct tf *tfp,
+ struct tf_tbl_get_bulk_parms *parms);
+
+#endif /* TF_TBL_SRAM_H */
diff --git a/drivers/net/bnxt/tf_core/tf_tcam.c b/drivers/net/bnxt/tf_core/tf_tcam.c
index 45206c5992..806af3070a 100644
--- a/drivers/net/bnxt/tf_core/tf_tcam.c
+++ b/drivers/net/bnxt/tf_core/tf_tcam.c
@@ -43,7 +43,7 @@ tf_tcam_bind(struct tf *tfp,
struct tf_shadow_tcam_free_db_parms fshadow;
struct tf_shadow_tcam_cfg_parms shadow_cfg;
struct tf_shadow_tcam_create_db_parms shadow_cdb;
- uint16_t num_slices = 1;
+ uint16_t num_slices = parms->wc_num_slices;
struct tf_session *tfs;
struct tf_dev_info *dev;
struct tcam_rm_db *tcam_db;
@@ -61,7 +61,7 @@ tf_tcam_bind(struct tf *tfp,
if (rc)
return rc;
- if (dev->ops->tf_dev_get_tcam_slice_info == NULL) {
+ if (dev->ops->tf_dev_set_tcam_slice_info == NULL) {
rc = -EOPNOTSUPP;
TFP_DRV_LOG(ERR,
"Operation not supported, rc:%s\n",
@@ -69,10 +69,8 @@ tf_tcam_bind(struct tf *tfp,
return rc;
}
- rc = dev->ops->tf_dev_get_tcam_slice_info(tfp,
- TF_TCAM_TBL_TYPE_WC_TCAM,
- 0,
- &num_slices);
+ rc = dev->ops->tf_dev_set_tcam_slice_info(tfp,
+ num_slices);
if (rc)
return rc;
diff --git a/drivers/net/bnxt/tf_core/tf_tcam.h b/drivers/net/bnxt/tf_core/tf_tcam.h
index bed17af6ae..b1e7a92b0b 100644
--- a/drivers/net/bnxt/tf_core/tf_tcam.h
+++ b/drivers/net/bnxt/tf_core/tf_tcam.h
@@ -12,6 +12,9 @@
* The TCAM module provides processing of Internal TCAM types.
*/
+/* Number of slices per row for WC TCAM */
+extern uint16_t g_wc_num_slices_per_row;
+
/**
* TCAM configuration parameters
*/
@@ -36,6 +39,10 @@ struct tf_tcam_cfg_parms {
* Session resource allocations
*/
struct tf_session_resources *resources;
+ /**
+ * WC number of slices per row.
+ */
+ enum tf_wc_num_slice wc_num_slices;
};
/**
diff --git a/drivers/net/bnxt/tf_core/tf_tcam_shared.c b/drivers/net/bnxt/tf_core/tf_tcam_shared.c
index 83b6fbd5fb..c120c6f577 100644
--- a/drivers/net/bnxt/tf_core/tf_tcam_shared.c
+++ b/drivers/net/bnxt/tf_core/tf_tcam_shared.c
@@ -279,18 +279,6 @@ tf_tcam_shared_bind(struct tf *tfp,
if (rc)
return rc;
- rc = tf_tcam_shared_get_slices(tfp,
- dev,
- &num_slices);
- if (rc)
- return rc;
-
- if (num_slices > 1) {
- TFP_DRV_LOG(ERR,
- "Only single slice supported\n");
- return -EOPNOTSUPP;
- }
-
tf_tcam_shared_create_db(&tcam_shared_wc);
@@ -330,6 +318,18 @@ tf_tcam_shared_bind(struct tf *tfp,
tf_session_set_tcam_shared_db(tfp, (void *)tcam_shared_wc);
}
+
+ rc = tf_tcam_shared_get_slices(tfp,
+ dev,
+ &num_slices);
+ if (rc)
+ return rc;
+
+ if (num_slices > 1) {
+ TFP_DRV_LOG(ERR,
+ "Only single slice supported\n");
+ return -EOPNOTSUPP;
+ }
}
done:
return rc;
@@ -972,9 +972,9 @@ tf_tcam_shared_move_entry(struct tf *tfp,
sparms.idx = dphy_idx;
sparms.key = gparms.key;
sparms.mask = gparms.mask;
- sparms.key_size = gparms.key_size;
+ sparms.key_size = key_sz_bytes;
sparms.result = gparms.result;
- sparms.result_size = gparms.result_size;
+ sparms.result_size = remap_sz_bytes;
rc = tf_msg_tcam_entry_set(tfp, dev, &sparms);
if (rc) {
diff --git a/drivers/net/bnxt/tf_core/tf_util.c b/drivers/net/bnxt/tf_core/tf_util.c
index d100399d0a..c1b9be0755 100644
--- a/drivers/net/bnxt/tf_core/tf_util.c
+++ b/drivers/net/bnxt/tf_core/tf_util.c
@@ -76,6 +76,8 @@ tf_tbl_type_2_str(enum tf_tbl_type tbl_type)
switch (tbl_type) {
case TF_TBL_TYPE_FULL_ACT_RECORD:
return "Full Action record";
+ case TF_TBL_TYPE_COMPACT_ACT_RECORD:
+ return "Compact Action record";
case TF_TBL_TYPE_MCAST_GROUPS:
return "Multicast Groups";
case TF_TBL_TYPE_ACT_ENCAP_8B:
@@ -96,6 +98,14 @@ tf_tbl_type_2_str(enum tf_tbl_type tbl_type)
return "Stats 64B";
case TF_TBL_TYPE_ACT_MODIFY_IPV4:
return "Modify IPv4";
+ case TF_TBL_TYPE_ACT_MODIFY_8B:
+ return "Modify 8B";
+ case TF_TBL_TYPE_ACT_MODIFY_16B:
+ return "Modify 16B";
+ case TF_TBL_TYPE_ACT_MODIFY_32B:
+ return "Modify 32B";
+ case TF_TBL_TYPE_ACT_MODIFY_64B:
+ return "Modify 64B";
case TF_TBL_TYPE_METER_PROF:
return "Meter Profile";
case TF_TBL_TYPE_METER_INST:
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index dbf85e4eda..183bae66c5 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -384,6 +384,7 @@ ulp_ctx_shared_session_open(struct bnxt *bp,
size_t copy_nbytes;
uint32_t ulp_dev_id = BNXT_ULP_DEVICE_ID_LAST;
int32_t rc = 0;
+ uint8_t app_id;
/* only perform this if shared session is enabled. */
if (!bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx))
@@ -422,6 +423,12 @@ ulp_ctx_shared_session_open(struct bnxt *bp,
if (rc)
return rc;
+ rc = bnxt_ulp_cntxt_app_id_get(bp->ulp_ctx, &app_id);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Unable to get the app id from ulp.\n");
+ return -EINVAL;
+ }
+
rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &ulp_dev_id);
if (rc) {
BNXT_TF_DBG(ERR, "Unable to get device id from ulp.\n");
@@ -445,6 +452,10 @@ ulp_ctx_shared_session_open(struct bnxt *bp,
parms.shadow_copy = true;
parms.bp = bp;
+ if (app_id == 0 || app_id == 3)
+ parms.wc_num_slices = TF_WC_TCAM_2_SLICE_PER_ROW;
+ else
+ parms.wc_num_slices = TF_WC_TCAM_1_SLICE_PER_ROW;
/*
* Open the session here, but the collect the resources during the
@@ -516,6 +527,7 @@ ulp_ctx_session_open(struct bnxt *bp,
struct tf_open_session_parms params;
struct tf_session_resources *resources;
uint32_t ulp_dev_id = BNXT_ULP_DEVICE_ID_LAST;
+ uint8_t app_id;
memset(¶ms, 0, sizeof(params));
@@ -529,6 +541,12 @@ ulp_ctx_session_open(struct bnxt *bp,
params.shadow_copy = true;
+ rc = bnxt_ulp_cntxt_app_id_get(bp->ulp_ctx, &app_id);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Unable to get the app id from ulp.\n");
+ return -EINVAL;
+ }
+
rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &ulp_dev_id);
if (rc) {
BNXT_TF_DBG(ERR, "Unable to get device id from ulp.\n");
@@ -556,6 +574,11 @@ ulp_ctx_session_open(struct bnxt *bp,
return rc;
params.bp = bp;
+ if (app_id == 0 || app_id == 3)
+ params.wc_num_slices = TF_WC_TCAM_2_SLICE_PER_ROW;
+ else
+ params.wc_num_slices = TF_WC_TCAM_1_SLICE_PER_ROW;
+
rc = tf_open_session(&bp->tfp, ¶ms);
if (rc) {
BNXT_TF_DBG(ERR, "Failed to open TF session - %s, rc = %d\n",
diff --git a/meson_options.txt b/meson_options.txt
index 0e92734c49..f686e6d92a 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -46,3 +46,5 @@ option('tests', type: 'boolean', value: true, description:
'build unit tests')
option('use_hpet', type: 'boolean', value: false, description:
'use HPET timer in EAL')
+option('bnxt_tf_wc_slices', type: 'integer', min: 1, max: 4, value: 2,
+ description: 'Number of slices per WC TCAM entry')
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v2 05/13] net/bnxt: add flow templates support for Thor
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 00/13] enhancements to host based flow table management Venkat Duvvuru
` (3 preceding siblings ...)
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 04/13] net/bnxt: add Thor SRAM mgr model Venkat Duvvuru
@ 2021-09-08 5:06 ` Venkat Duvvuru
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 06/13] net/bnxt: add support for tunnel offloads Venkat Duvvuru
` (9 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-08 5:06 UTC (permalink / raw)
To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Template adds non-VFR based support for testpmd with:
matches to include
- DMAC, SIP, DIP, Proto, Sport, Dport
- SIP, DIP, Proto, Sport, Dport
actions:
- count, drop
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
---
drivers/net/bnxt/tf_ulp/bnxt_tf_common.h | 6 +
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 36 +++---
drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 12 ++
.../bnxt/tf_ulp/generic_templates/meson.build | 17 ++-
.../ulp_template_db_thor_class.c | 1 -
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 122 +++++++++++++++++-
drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 26 +++-
drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c | 5 +
drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 111 +++++++++++++++-
drivers/net/bnxt/tf_ulp/ulp_matcher.c | 13 ++
drivers/net/bnxt/tf_ulp/ulp_port_db.c | 15 ++-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 9 +-
drivers/net/bnxt/tf_ulp/ulp_tun.c | 20 +++
drivers/net/bnxt/tf_ulp/ulp_utils.c | 8 +-
16 files changed, 356 insertions(+), 49 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
index f59da41e54..e0ebed3fed 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
@@ -13,6 +13,12 @@
#define BNXT_TF_DBG(lvl, fmt, args...) PMD_DRV_LOG(lvl, fmt, ## args)
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#define BNXT_TF_INF(fmt, args...) PMD_DRV_LOG(INFO, fmt, ## args)
+#else
+#define BNXT_TF_INF(fmt, args...)
+#endif
+
#define BNXT_ULP_EM_FLOWS 8192
#define BNXT_ULP_1M_FLOWS 1000000
#define BNXT_EEM_RX_GLOBAL_ID_MASK (BNXT_ULP_1M_FLOWS - 1)
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 183bae66c5..475c7a6cdf 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -698,6 +698,11 @@ ulp_eem_tbl_scope_init(struct bnxt *bp)
rc);
return rc;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+ BNXT_TF_DBG(DEBUG, "TableScope=0x%0x %d\n",
+ params.tbl_scope_id,
+ params.tbl_scope_id);
+#endif
rc = bnxt_ulp_cntxt_tbl_scope_id_set(bp->ulp_ctx, params.tbl_scope_id);
if (rc) {
BNXT_TF_DBG(ERR, "Unable to set table scope id\n");
@@ -825,6 +830,8 @@ ulp_ctx_init(struct bnxt *bp,
goto error_deinit;
}
+ /* TODO: For now we are overriding to APP:1 on this branch*/
+ bp->app_id = 1;
rc = bnxt_ulp_cntxt_app_id_set(bp->ulp_ctx, bp->app_id);
if (rc) {
BNXT_TF_DBG(ERR, "Unable to set app_id for ULP init.\n");
@@ -838,11 +845,6 @@ ulp_ctx_init(struct bnxt *bp,
goto error_deinit;
}
- if (devid == BNXT_ULP_DEVICE_ID_THOR) {
- ulp_data->ulp_flags &= ~BNXT_ULP_VF_REP_ENABLED;
- BNXT_TF_DBG(ERR, "Enabled non-VFR mode\n");
- }
-
/*
* Shared session must be created before first regular session but after
* the ulp_ctx is valid.
@@ -902,7 +904,7 @@ ulp_dparms_init(struct bnxt *bp, struct bnxt_ulp_context *ulp_ctx)
dparms->ext_flow_db_num_entries = bp->max_num_kflows * 1024;
/* GFID = 2 * num_flows */
dparms->mark_db_gfid_entries = dparms->ext_flow_db_num_entries * 2;
- BNXT_TF_DBG(DEBUG, "Set the number of flows = %"PRIu64"\n",
+ BNXT_TF_DBG(DEBUG, "Set the number of flows = %" PRIu64 "\n",
dparms->ext_flow_db_num_entries);
return 0;
@@ -1393,17 +1395,13 @@ bnxt_ulp_port_init(struct bnxt *bp)
uint32_t ulp_flags;
int32_t rc = 0;
+ if (!bp || !BNXT_TRUFLOW_EN(bp))
+ return rc;
+
if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
BNXT_TF_DBG(ERR,
"Skip ulp init for port: %d, not a TVF or PF\n",
- bp->eth_dev->data->port_id);
- return rc;
- }
-
- if (!BNXT_TRUFLOW_EN(bp)) {
- BNXT_TF_DBG(DEBUG,
- "Skip ulp init for port: %d, truflow is not enabled\n",
- bp->eth_dev->data->port_id);
+ bp->eth_dev->data->port_id);
return rc;
}
@@ -1524,6 +1522,9 @@ bnxt_ulp_port_deinit(struct bnxt *bp)
struct rte_pci_device *pci_dev;
struct rte_pci_addr *pci_addr;
+ if (!BNXT_TRUFLOW_EN(bp))
+ return;
+
if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
BNXT_TF_DBG(ERR,
"Skip ULP deinit port:%d, not a TVF or PF\n",
@@ -1531,13 +1532,6 @@ bnxt_ulp_port_deinit(struct bnxt *bp)
return;
}
- if (!BNXT_TRUFLOW_EN(bp)) {
- BNXT_TF_DBG(DEBUG,
- "Skip ULP deinit for port:%d, truflow is not enabled\n",
- bp->eth_dev->data->port_id);
- return;
- }
-
if (!bp->ulp_ctx) {
BNXT_TF_DBG(DEBUG, "ulp ctx already de-allocated\n");
return;
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
index 19e9dba356..238b1d9657 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
@@ -13,6 +13,9 @@
#include "ulp_port_db.h"
#include "ulp_ha_mgr.h"
#include <rte_malloc.h>
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#include "ulp_template_debug_proto.h"
+#endif
static int32_t
bnxt_ulp_flow_validate_args(const struct rte_flow_attr *attr,
@@ -222,6 +225,15 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
else if (ret == BNXT_TF_RC_FID)
goto return_fid;
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER
+ /* Dump the rte flow pattern */
+ ulp_parser_hdr_info_dump(¶ms);
+ /* Dump the rte flow action */
+ ulp_parser_act_info_dump(¶ms);
+#endif
+#endif
+
ret = ulp_matcher_pattern_match(¶ms, ¶ms.class_id);
if (ret != BNXT_TF_RC_SUCCESS)
goto free_fid;
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/meson.build b/drivers/net/bnxt/tf_ulp/generic_templates/meson.build
index b1e7b8cc32..16b27a2e24 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/meson.build
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/meson.build
@@ -2,12 +2,15 @@
# Copyright(c) 2018 Intel Corporation
# Copyright(c) 2020 Broadcom
+#Include the folder for headers
includes += include_directories('.')
+
+#Add the source files
sources += files(
- 'ulp_template_db_class.c',
- 'ulp_template_db_act.c',
- 'ulp_template_db_tbl.c',
- 'ulp_template_db_wh_plus_act.c',
- 'ulp_template_db_wh_plus_class.c',
- 'ulp_template_db_thor_act.c',
- 'ulp_template_db_thor_class.c')
+ 'ulp_template_db_class.c',
+ 'ulp_template_db_act.c',
+ 'ulp_template_db_tbl.c',
+ 'ulp_template_db_wh_plus_act.c',
+ 'ulp_template_db_wh_plus_class.c',
+ 'ulp_template_db_thor_act.c',
+ 'ulp_template_db_thor_class.c')
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
index 83f6152700..e342f340d9 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
@@ -6104,4 +6104,3 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.ident_bit_pos = 29
}
};
-
diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
index 13f71ed83b..22c51976ac 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
@@ -35,7 +35,7 @@ ulp_fc_mgr_shadow_mem_alloc(struct hw_fc_mem_info *parms, int size)
rte_mem_lock_page(parms->mem_va);
parms->mem_pa = (void *)(uintptr_t)rte_mem_virt2phy(parms->mem_va);
- if (parms->mem_pa == (void *)(uintptr_t)RTE_BAD_IOVA) {
+ if (parms->mem_pa == (void *)RTE_BAD_IOVA) {
BNXT_TF_DBG(ERR, "Allocate failed mem_pa\n");
return -ENOMEM;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
index ab6013f0e3..747a360aa0 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
@@ -116,7 +116,7 @@ ulp_flow_db_resource_func_get(struct ulp_fdb_resource_info *res_info)
func = (((res_info->nxt_resource_idx & ULP_FLOW_DB_RES_FUNC_MASK) >>
ULP_FLOW_DB_RES_FUNC_BITS) << ULP_FLOW_DB_RES_FUNC_UPPER);
- /* The resource func is split into upper and lower */
+ /* The reource func is split into upper and lower */
if (func & ULP_FLOW_DB_RES_FUNC_NEED_LOWER)
return (func | res_info->resource_func_lower);
return func;
@@ -654,6 +654,9 @@ ulp_flow_db_fid_alloc(struct bnxt_ulp_context *ulp_ctxt,
if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR)
ulp_flow_db_func_id_set(flow_db, *fid, func_id);
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+ BNXT_TF_DBG(ERR, "flow_id = %u:%u allocated\n", flow_type, *fid);
+#endif
/* return success */
return 0;
}
@@ -714,7 +717,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt,
if (params->critical_resource && fid_resource->resource_em_handle) {
BNXT_TF_DBG(DEBUG, "Ignore multiple critical resources\n");
- /* Ignore the multiple critical resources */
+ /* Ignore the multiple criticial resources */
params->critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO;
}
@@ -766,7 +769,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt,
* flow_type [in] Specify it is regular or default flow
* fid [in] The index to the flow entry
* params [in/out] The contents to be copied into params.
- * Only the critical_resource needs to be set by the caller.
+ * Onlythe critical_resource needs to be set by the caller.
*
* Returns 0 on success and negative on failure.
*/
@@ -937,6 +940,9 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt,
ulp_clear_tun_inner_entry(tun_tbl, fid);
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+ BNXT_TF_DBG(ERR, "flow_id = %u:%u freed\n", flow_type, fid);
+#endif
/* all good, return success */
return 0;
}
@@ -1921,3 +1927,113 @@ void ulp_flow_db_shared_session_set(struct ulp_flow_db_res_params *res,
if (res && (shared & BNXT_ULP_SHARED_SESSION_YES))
res->fdb_flags |= ULP_FDB_FLAG_SHARED_SESSION;
}
+
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+/*
+ * Dump the entry details
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ *
+ * returns none
+ */
+static void ulp_flow_db_res_dump(struct ulp_fdb_resource_info *r,
+ uint32_t *nxt_res)
+{
+ uint8_t res_func = ulp_flow_db_resource_func_get(r);
+
+ BNXT_TF_DBG(DEBUG, "Resource func = %x, nxt_resource_idx = %x\n",
+ res_func, (ULP_FLOW_DB_RES_NXT_MASK & r->nxt_resource_idx));
+ if (res_func == BNXT_ULP_RESOURCE_FUNC_EM_TABLE)
+ BNXT_TF_DBG(DEBUG, "EM Handle = 0x%016" PRIX64 "\n",
+ r->resource_em_handle);
+ else
+ BNXT_TF_DBG(DEBUG, "Handle = 0x%08x\n", r->resource_hndl);
+
+ *nxt_res = 0;
+ ULP_FLOW_DB_RES_NXT_SET(*nxt_res,
+ r->nxt_resource_idx);
+}
+
+/*
+ * Dump the flow entry details
+ *
+ * flow_db [in] Ptr to flow db
+ * fid [in] flow id
+ *
+ * returns none
+ */
+void
+ulp_flow_db_debug_fid_dump(struct bnxt_ulp_flow_db *flow_db, uint32_t fid)
+{
+ struct ulp_fdb_resource_info *r;
+ struct bnxt_ulp_flow_tbl *flow_tbl;
+ uint32_t nxt_res = 0;
+ uint32_t def_flag = 0, reg_flag = 0;
+
+ flow_tbl = &flow_db->flow_tbl;
+ if (ulp_flow_db_active_flows_bit_is_set(flow_db,
+ BNXT_ULP_FDB_TYPE_REGULAR, fid))
+ reg_flag = 1;
+ if (ulp_flow_db_active_flows_bit_is_set(flow_db,
+ BNXT_ULP_FDB_TYPE_DEFAULT, fid))
+ def_flag = 1;
+
+ if (reg_flag && def_flag)
+ BNXT_TF_DBG(DEBUG, "RID = %u\n", fid);
+ else if (reg_flag)
+ BNXT_TF_DBG(DEBUG, "Regular fid = %u and func id = %u\n",
+ fid, flow_db->func_id_tbl[fid]);
+ else if (def_flag)
+ BNXT_TF_DBG(DEBUG, "Default fid = %u\n", fid);
+ else
+ return;
+ /* iterate the resource */
+ nxt_res = fid;
+ do {
+ r = &flow_tbl->flow_resources[nxt_res];
+ ulp_flow_db_res_dump(r, &nxt_res);
+ } while (nxt_res);
+}
+
+/*
+ * Dump the flow database entry details
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ * flow_id [in] if zero then all fids are dumped.
+ *
+ * returns none
+ */
+int32_t ulp_flow_db_debug_dump(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t flow_id)
+{
+ struct bnxt_ulp_flow_db *flow_db;
+ struct bnxt_ulp_flow_tbl *flow_tbl;
+ uint32_t fid;
+
+ if (!ulp_ctxt || !ulp_ctxt->cfg_data) {
+ BNXT_TF_DBG(ERR, "Invalid Arguments\n");
+ return -EINVAL;
+ }
+ flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
+ if (!flow_db) {
+ BNXT_TF_DBG(ERR, "Invalid Arguments\n");
+ return -EINVAL;
+ }
+
+ flow_tbl = &flow_db->flow_tbl;
+ if (flow_id) {
+ ulp_flow_db_debug_fid_dump(flow_db, flow_id);
+ return 0;
+ }
+
+ BNXT_TF_DBG(DEBUG, "Dump flows = %u:%u\n",
+ flow_tbl->num_flows,
+ flow_tbl->num_resources);
+ BNXT_TF_DBG(DEBUG, "Head_index = %u, Tail_index = %u\n",
+ flow_tbl->head_index, flow_tbl->tail_index);
+ for (fid = 1; fid < flow_tbl->num_flows; fid++)
+ ulp_flow_db_debug_fid_dump(flow_db, fid);
+ BNXT_TF_DBG(DEBUG, "Done.\n");
+ return 0;
+}
+#endif
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
index 67afca8872..0ddfa6f66d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
@@ -18,7 +18,7 @@
/*
* Structure for the flow database resource information
- * The below structure is based on the below partitions
+ * The below structure is based on the below paritions
* nxt_resource_idx = dir[31],resource_func_upper[30:28],nxt_resource_idx[27:0]
* If resource_func is EM_TBL then use resource_em_handle.
* Else the other part of the union is used and
@@ -417,4 +417,28 @@ ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt);
void ulp_flow_db_shared_session_set(struct ulp_flow_db_res_params *res,
enum bnxt_ulp_shared_session shared);
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+/*
+ * Dump the flow entry details
+ *
+ * flow_db [in] Ptr to flow db
+ * fid [in] flow id
+ *
+ * returns none
+ */
+void
+ulp_flow_db_debug_fid_dump(struct bnxt_ulp_flow_db *flow_db, uint32_t fid);
+
+/*
+ * Dump the flow database entry details
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ * flow_id [in] if zero then all fids are dumped.
+ *
+ * returns none
+ */
+int32_t ulp_flow_db_debug_dump(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t flow_id);
+#endif
+
#endif /* _ULP_FLOW_DB_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
index 3c1af0b007..c6b2b1675d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
@@ -10,6 +10,11 @@
#include "ulp_mapper.h"
#include "ulp_flow_db.h"
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#include "ulp_template_debug_proto.h"
+#include "ulp_tf_debug.h"
+#endif
+
/* Retrieve the generic table initialization parameters for the tbl_idx */
static struct bnxt_ulp_generic_tbl_params*
ulp_mapper_gen_tbl_params_get(uint32_t tbl_idx)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
index 5f5b5d639e..bc5627ec5b 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
@@ -185,7 +185,7 @@ ulp_ha_mgr_timer_cb(void *arg __rte_unused)
rc = ulp_ha_mgr_state_get(ulp_ctx, &curr_state);
if (rc) {
/*
- * This shouldn't happen, if it does, reset the timer
+ * This shouldn't happen, if it does, resetart the timer
* and try again next time.
*/
BNXT_TF_DBG(ERR, "Failed(%d) to get state.\n",
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index f3a60cc880..7fc3767b33 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -22,6 +22,11 @@
#include "ulp_ha_mgr.h"
#include "bnxt_tf_pmd_shim.h"
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#include "ulp_template_debug_proto.h"
+#include "ulp_tf_debug.h"
+#endif
+
static uint8_t mapper_fld_zeros[16] = { 0 };
static uint8_t mapper_fld_ones[16] = {
@@ -156,6 +161,13 @@ ulp_mapper_resource_ident_allocate(struct bnxt_ulp_context *ulp_ctx,
tf_free_identifier(tfp, &fparms);
return rc;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ BNXT_TF_DBG(DEBUG, "Allocated Glb Res Ident [%s][%d][%d] = 0x%04x\n",
+ tf_dir_2_str(iparms.dir),
+ glb_res->glb_regfile_index, iparms.ident_type, iparms.id);
+#endif
+#endif
return rc;
}
@@ -216,6 +228,13 @@ ulp_mapper_resource_index_tbl_alloc(struct bnxt_ulp_context *ulp_ctx,
tf_free_tbl_entry(tfp, &free_parms);
return rc;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ BNXT_TF_DBG(DEBUG, "Allocated Glb Res Index [%s][%d][%d] = 0x%04x\n",
+ tf_dir_2_str(aparms.dir),
+ glb_res->glb_regfile_index, aparms.type, aparms.idx);
+#endif
+#endif
return rc;
}
@@ -784,6 +803,9 @@ ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms,
tf_ident_2_str(iparms.ident_type));
return rc;
}
+ BNXT_TF_INF("Alloc ident %s:%s.success.\n",
+ tf_dir_2_str(iparms.dir),
+ tf_ident_2_str(iparms.ident_type));
id = (uint64_t)tfp_cpu_to_be_64(iparms.id);
if (ulp_regfile_write(parms->regfile, idx, id)) {
@@ -813,6 +835,11 @@ ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms,
} else {
*val = iparms.id;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_ident_field_dump("Ident", ident, tbl, iparms.id);
+#endif
+#endif
return 0;
error:
@@ -877,6 +904,10 @@ ulp_mapper_ident_extract(struct bnxt_ulp_mapper_parms *parms,
sparms.search_id);
return rc;
}
+ BNXT_TF_INF("Search ident %s:%s:%x.success.\n",
+ tf_dir_2_str(sparms.dir),
+ tf_tbl_type_2_str(sparms.ident_type),
+ sparms.search_id);
/* Write it to the regfile */
id = (uint64_t)tfp_cpu_to_be_64(sparms.search_id);
@@ -904,6 +935,11 @@ ulp_mapper_ident_extract(struct bnxt_ulp_mapper_parms *parms,
goto error;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_ident_field_dump("Ident", ident, tbl, sparms.search_id);
+#endif
+#endif
return 0;
error:
@@ -996,7 +1032,7 @@ ulp_mapper_field_src_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
idx = tfp_be_to_cpu_16(idx);
- if (idx >= BNXT_ULP_CF_IDX_LAST || bytelen > sizeof(uint64_t)) {
+ if (idx >= BNXT_ULP_CF_IDX_LAST || bytelen > sizeof(uint32_t)) {
BNXT_TF_DBG(ERR, "comp field [%d] read oob %d\n", idx,
bytelen);
return -EINVAL;
@@ -1448,7 +1484,16 @@ ulp_mapper_field_opc_process(struct bnxt_ulp_mapper_parms *parms,
break;
}
- return rc;
+ if (!rc) {
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ if (fld->field_src1 != BNXT_ULP_FIELD_SRC_ZERO)
+ ulp_mapper_field_dump(name, fld, blob, write_idx, val,
+ val_len);
+#endif
+#endif
+ return rc;
+ }
error:
BNXT_TF_DBG(ERR, "Error in %s:%s process %u:%u\n", name,
fld->description, (val) ? write_idx : 0, val_len);
@@ -1500,8 +1545,15 @@ ulp_mapper_tbl_result_build(struct bnxt_ulp_mapper_parms *parms,
}
/* if encap bit swap is enabled perform the bit swap */
- if (parms->device_params->encap_byte_swap && encap_flds)
+ if (parms->device_params->encap_byte_swap && encap_flds) {
ulp_blob_perform_encap_swap(data);
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ BNXT_TF_DBG(INFO, "Dump after encap swap\n");
+ ulp_mapper_blob_dump(data);
+#endif
+#endif
+ }
return rc;
}
@@ -1725,6 +1777,9 @@ ulp_mapper_tcam_tbl_entry_write(struct bnxt_ulp_mapper_parms *parms,
tf_dir_2_str(sparms.dir), sparms.idx);
return -EIO;
}
+ BNXT_TF_INF("tcam[%s][%s][%x] write success.\n",
+ tf_tcam_tbl_2_str(sparms.tcam_tbl_type),
+ tf_dir_2_str(sparms.dir), sparms.idx);
/* Mark action */
rc = ulp_mapper_mark_act_ptr_process(parms, tbl);
@@ -1733,6 +1788,11 @@ ulp_mapper_tcam_tbl_entry_write(struct bnxt_ulp_mapper_parms *parms,
return rc;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_tcam_entry_dump("TCAM", idx, tbl, key, mask, data);
+#endif
+#endif
return rc;
}
@@ -1838,6 +1898,12 @@ static void ulp_mapper_wc_tcam_tbl_post_process(struct ulp_blob *blob)
{
ulp_blob_perform_64B_word_swap(blob);
ulp_blob_perform_64B_byte_swap(blob);
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ BNXT_TF_DBG(INFO, "Dump after wc tcam post process\n");
+ ulp_mapper_blob_dump(blob);
+#endif
+#endif
}
static int32_t
@@ -2134,6 +2200,11 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
BNXT_TF_DBG(ERR, "Failed to build the result blob\n");
return rc;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_result_dump("EM Result", tbl, &data);
+#endif
+#endif
if (dparms->dynamic_pad_en) {
uint32_t abits = dparms->em_blk_align_bits;
@@ -2148,6 +2219,11 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
ulp_blob_pad_align(&data, abits);
ulp_blob_perform_byte_reverse(&data, ULP_BITS_2_BYTE(abits));
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_result_dump("EM Merged Result", tbl, &data);
+#endif
+#endif
}
/* do the transpose for the internal EM keys */
@@ -2160,6 +2236,11 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
}
tmplen = ulp_blob_data_len_get(&key);
ulp_blob_perform_byte_reverse(&key, ULP_BITS_2_BYTE(tmplen));
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_result_dump("EM Key Transpose", tbl, &key);
+#endif
+#endif
}
rc = bnxt_ulp_cntxt_tbl_scope_id_get(parms->ulp_ctx,
@@ -2190,6 +2271,12 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return rc;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_em_dump("EM", &key, &data, &iparms);
+ /* tf_dump_tables(tfp, iparms.tbl_scope_id); */
+#endif
+#endif
/* Mark action process */
if (mtype == BNXT_ULP_FLOW_MEM_TYPE_EXT &&
tbl->resource_type == TF_MEM_EXTERNAL)
@@ -2479,6 +2566,9 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
sparms.idx, rc);
goto error;
}
+ BNXT_TF_INF("Index table[%s][%s][%x] write successful.\n",
+ tf_tbl_type_2_str(sparms.type),
+ tf_dir_2_str(sparms.dir), sparms.idx);
/* Calculate action record size */
if (tbl->resource_type == TF_TBL_TYPE_EXT) {
@@ -2635,6 +2725,10 @@ ulp_mapper_if_tbl_process(struct bnxt_ulp_mapper_parms *parms,
iftbl_params.idx, rc);
return rc;
}
+ BNXT_TF_INF("Set table[%s][%s][%x] success.\n",
+ tf_if_tbl_2_str(iftbl_params.type),
+ tf_dir_2_str(iftbl_params.dir),
+ iftbl_params.idx);
/*
* TBD: Need to look at the need to store idx in flow db for restore
@@ -2697,6 +2791,12 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms,
/* The_key is a byte array convert it to a search index */
cache_key = ulp_blob_data_get(&key, &tmplen);
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ BNXT_TF_DBG(DEBUG, "The gen_tbl[%u] key\n", tbl_idx);
+ ulp_mapper_blob_dump(&key);
+#endif
+#endif
/* get the generic table */
gen_tbl_list = &parms->mapper_data->gen_tbl_list[tbl_idx];
@@ -3495,6 +3595,11 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid)
for (tbl_idx = 0; tbl_idx < num_tbls && cond_goto;) {
tbl = &tbls[tbl_idx];
cond_goto = tbl->execute_info.cond_true_goto;
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_table_dump(tbl, tbl_idx);
+#endif
+#endif
/* Process the conditional func code opcodes */
if (ulp_mapper_func_info_process(parms, tbl)) {
BNXT_TF_DBG(ERR, "Failed to process cond update\n");
diff --git a/drivers/net/bnxt/tf_ulp/ulp_matcher.c b/drivers/net/bnxt/tf_ulp/ulp_matcher.c
index 67fa61fc7c..e06d8f6287 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_matcher.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_matcher.c
@@ -6,6 +6,10 @@
#include "ulp_matcher.h"
#include "ulp_utils.h"
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#include "ulp_template_debug_proto.h"
+#endif
+
/* Utility function to calculate the class matcher hash */
static uint32_t
ulp_matcher_class_hash_calculate(uint64_t hi_sig, uint64_t lo_sig)
@@ -95,6 +99,11 @@ ulp_matcher_pattern_match(struct ulp_rte_parser_params *params,
error:
BNXT_TF_DBG(DEBUG, "Did not find any matching template\n");
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+ BNXT_TF_DBG(DEBUG, "class_hid:0x%x, Hdr:%" PRIX64 " Fld:%" PRIX64 "\n",
+ class_hid, params->hdr_bitmap.bits,
+ params->fld_bitmap.bits);
+#endif
*class_id = 0;
return BNXT_TF_RC_ERROR;
}
@@ -142,6 +151,10 @@ ulp_matcher_action_match(struct ulp_rte_parser_params *params,
error:
BNXT_TF_DBG(DEBUG, "Did not find any matching action template\n");
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+ BNXT_TF_DBG(DEBUG, "act_hid:0x%x, Hdr:%" PRIX64 "\n",
+ act_hid, params->act_bitmap.bits);
+#endif
*act_id = 0;
return BNXT_TF_RC_ERROR;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.c b/drivers/net/bnxt/tf_ulp/ulp_port_db.c
index 4045473097..7d9865b3e3 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_port_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.c
@@ -7,9 +7,13 @@
#include "bnxt.h"
#include "bnxt_vnic.h"
#include "bnxt_tf_common.h"
+#include "bnxt_tf_pmd_shim.h"
#include "ulp_port_db.h"
#include "tfp.h"
-#include "bnxt_tf_pmd_shim.h"
+
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#include "ulp_tf_debug.h"
+#endif
static uint32_t
ulp_port_db_allocate_ifindex(struct bnxt_ulp_port_db *port_db)
@@ -151,12 +155,12 @@ int32_t ulp_port_db_dev_port_intf_update(struct bnxt_ulp_context *ulp_ctxt,
intf->type = bnxt_pmd_get_interface_type(port_id);
intf->drv_func_id = bnxt_pmd_get_fw_func_id(port_id,
- BNXT_ULP_INTF_TYPE_INVALID);
+ BNXT_ULP_INTF_TYPE_INVALID);
func = &port_db->ulp_func_id_tbl[intf->drv_func_id];
if (!func->func_valid) {
func->func_svif = bnxt_pmd_get_svif(port_id, true,
- BNXT_ULP_INTF_TYPE_INVALID);
+ BNXT_ULP_INTF_TYPE_INVALID);
func->func_spif = bnxt_pmd_get_phy_port_id(port_id);
func->func_parif =
bnxt_pmd_get_parif(port_id, BNXT_ULP_INTF_TYPE_INVALID);
@@ -202,6 +206,11 @@ int32_t ulp_port_db_dev_port_intf_update(struct bnxt_ulp_context *ulp_ctxt,
port_data->port_vport = bnxt_pmd_get_vport(port_id);
port_data->port_valid = true;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PORT
+ ulp_port_db_dump(port_db, intf, port_id);
+#endif
+#endif
return 0;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index 5fd52b8f36..79b9957781 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -8,6 +8,7 @@
#include "ulp_template_struct.h"
#include "bnxt_ulp.h"
#include "bnxt_tf_common.h"
+#include "bnxt_tf_pmd_shim.h"
#include "ulp_rte_parser.h"
#include "ulp_matcher.h"
#include "ulp_utils.h"
@@ -855,7 +856,7 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
BNXT_ULP_HDR_BIT_II_VLAN);
inner_flag = 1;
} else {
- BNXT_TF_DBG(ERR, "Error Parsing:Vlan hdr found without eth\n");
+ BNXT_TF_DBG(ERR, "Error Parsing:Vlan hdr found withtout eth\n");
return BNXT_TF_RC_ERROR;
}
/* Update the field protocol hdr bitmap */
@@ -1135,8 +1136,8 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
ulp_rte_prsr_fld_mask(params, &idx, size, &ver_spec, &ver_mask,
ULP_PRSR_ACT_DEFAULT);
/*
- * The TC and flow label field are ignored since OVS is setting
- * it for match and it is not supported.
+ * The TC and flow label field are ignored since OVS is
+ * setting it for match and it is not supported.
* This is a work around and
* shall be addressed in the future.
*/
@@ -2138,7 +2139,7 @@ ulp_rte_vf_act_handler(const struct rte_flow_action *action_item,
return BNXT_TF_RC_PARSE_ERR;
}
- bp = bnxt_get_bp(params->port_id);
+ bp = bnxt_pmd_get_bp(params->port_id);
if (bp == NULL) {
BNXT_TF_DBG(ERR, "Invalid bp\n");
return BNXT_TF_RC_ERROR;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.c b/drivers/net/bnxt/tf_ulp/ulp_tun.c
index cb8530d791..a1dd5b902c 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_tun.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_tun.c
@@ -3,6 +3,8 @@
* All rights reserved.
*/
+#include <sys/queue.h>
+
#include <rte_malloc.h>
#include "ulp_tun.h"
@@ -29,6 +31,15 @@ ulp_install_outer_tun_flow(struct ulp_rte_parser_params *params,
ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F1);
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER
+ /* Dump the rte flow pattern */
+ ulp_parser_hdr_info_dump(params);
+ /* Dump the rte flow action */
+ ulp_parser_act_info_dump(params);
+#endif
+#endif
+
ret = ulp_matcher_pattern_match(params, ¶ms->class_id);
if (ret != BNXT_TF_RC_SUCCESS)
goto err;
@@ -146,6 +157,15 @@ ulp_post_process_cache_inner_tun_flow(struct ulp_rte_parser_params *params,
struct ulp_per_port_flow_info *flow_info;
int ret;
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER
+ /* Dump the rte flow pattern */
+ ulp_parser_hdr_info_dump(params);
+ /* Dump the rte flow action */
+ ulp_parser_act_info_dump(params);
+#endif
+#endif
+
ret = ulp_matcher_pattern_match(params, ¶ms->class_id);
if (ret != BNXT_TF_RC_SUCCESS)
return BNXT_TF_RC_ERROR;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c
index bafb539c8d..1649e157f2 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c
@@ -62,7 +62,7 @@ ulp_regfile_read(struct ulp_regfile *regfile,
* data [in] The value is written into this variable. It is going to be in the
* same byte order as it was written.
*
- * size [in] The size in bytes of the value being written into this
+ * size [in] The size in bytes of the value beingritten into this
* variable.
*
* returns 0 on success
@@ -295,7 +295,7 @@ ulp_blob_push(struct ulp_blob *blob,
datalen,
data);
if (!rc) {
- BNXT_TF_DBG(ERR, "Failed to write blob\n");
+ BNXT_TF_DBG(ERR, "Failed ro write blob\n");
return 0;
}
blob->write_idx += datalen;
@@ -355,7 +355,7 @@ ulp_blob_insert(struct ulp_blob *blob, uint32_t offset,
datalen,
data);
if (!rc) {
- BNXT_TF_DBG(ERR, "Failed to write blob\n");
+ BNXT_TF_DBG(ERR, "Failed ro write blob\n");
return 0;
}
/* copy the previously stored data */
@@ -409,7 +409,7 @@ ulp_blob_push_64(struct ulp_blob *blob,
*
* data [in] 32-bit value to be added to the blob.
*
- * datalen [in] The number of bits to be added to the blob.
+ * datalen [in] The number of bits to be added ot the blob.
*
* The offset of the data is updated after each push of data.
* NULL returned on error, pointer pushed value otherwise.
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v2 06/13] net/bnxt: add support for tunnel offloads
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 00/13] enhancements to host based flow table management Venkat Duvvuru
` (4 preceding siblings ...)
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 05/13] net/bnxt: add flow templates support for Thor Venkat Duvvuru
@ 2021-09-08 5:06 ` Venkat Duvvuru
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 07/13] net/bnxt: add support for dynamic encap action Venkat Duvvuru
` (8 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-08 5:06 UTC (permalink / raw)
To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Added support for tunnel offloads, this includes the support for
VXLAN decap action where two flows indicate tunnel offload rule. The
first flow indicate the tunnel properties and second flow indicates the
inner packet structure. The templates are updated to support this
feature.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com>
---
drivers/net/bnxt/tf_ulp/bnxt_tf_common.h | 4 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 12 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 20 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 212 +-
.../generic_templates/ulp_template_db_act.c | 2 +-
.../generic_templates/ulp_template_db_class.c | 8541 +++++++++++-----
.../generic_templates/ulp_template_db_enum.h | 210 +-
.../generic_templates/ulp_template_db_field.h | 654 +-
.../generic_templates/ulp_template_db_tbl.c | 645 +-
.../ulp_template_db_thor_class.c | 110 +-
.../ulp_template_db_wh_plus_act.c | 2 +-
.../ulp_template_db_wh_plus_class.c | 8577 +++++++++++------
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 46 +-
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h | 8 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 562 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 44 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 52 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.h | 6 +-
drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c | 31 +
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 134 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 10 +-
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 10 +-
drivers/net/bnxt/tf_ulp/ulp_tun.c | 541 +-
drivers/net/bnxt/tf_ulp/ulp_tun.h | 89 +-
24 files changed, 13810 insertions(+), 6712 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
index e0ebed3fed..6c4bcd2d90 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
@@ -37,9 +37,7 @@
enum bnxt_tf_rc {
BNXT_TF_RC_PARSE_ERR = -2,
BNXT_TF_RC_ERROR = -1,
- BNXT_TF_RC_SUCCESS = 0,
- BNXT_TF_RC_NORMAL = 1,
- BNXT_TF_RC_FID = 2,
+ BNXT_TF_RC_SUCCESS = 0
};
/* eth IPv4 Type */
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 475c7a6cdf..dfafd9ff5b 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -860,8 +860,6 @@ ulp_ctx_init(struct bnxt *bp,
if (rc)
goto error_deinit;
- ulp_tun_tbl_init(ulp_data->tun_tbl);
-
bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, &bp->tfp);
return rc;
@@ -2064,3 +2062,13 @@ bnxt_ulp_cntxt_entry_release(void)
{
rte_spinlock_unlock(&bnxt_ulp_ctxt_lock);
}
+
+/* Function to get the app tunnel details from the ulp context. */
+struct bnxt_flow_app_tun_ent *
+bnxt_ulp_cntxt_ptr2_app_tun_list_get(struct bnxt_ulp_context *ulp)
+{
+ if (!ulp || !ulp->cfg_data)
+ return NULL;
+
+ return ulp->cfg_data->app_tun;
+}
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
index 082ca501b6..006df9cbc5 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
@@ -47,6 +47,18 @@ enum bnxt_ulp_flow_mem_type {
BNXT_ULP_FLOW_MEM_TYPE_LAST = 3
};
+enum bnxt_rte_flow_item_type {
+ BNXT_RTE_FLOW_ITEM_TYPE_END = (uint32_t)INT_MIN,
+ BNXT_RTE_FLOW_ITEM_TYPE_VXLAN_DECAP,
+ BNXT_RTE_FLOW_ITEM_TYPE_LAST
+};
+
+enum bnxt_rte_flow_action_type {
+ BNXT_RTE_FLOW_ACTION_TYPE_END = (uint32_t)INT_MIN,
+ BNXT_RTE_FLOW_ACTION_TYPE_VXLAN_DECAP,
+ BNXT_RTE_FLOW_ACTION_TYPE_LAST
+};
+
struct bnxt_ulp_df_rule_info {
uint32_t def_port_flow_id;
uint8_t valid;
@@ -79,6 +91,7 @@ struct bnxt_ulp_data {
bool accum_stats;
uint8_t app_id;
uint8_t num_shared_clients;
+ struct bnxt_flow_app_tun_ent app_tun[BNXT_ULP_MAX_TUN_CACHE_ENTRIES];
};
struct bnxt_ulp_context {
@@ -258,9 +271,6 @@ bnxt_ulp_cntxt_acquire_fdb_lock(struct bnxt_ulp_context *ulp_ctx);
void
bnxt_ulp_cntxt_release_fdb_lock(struct bnxt_ulp_context *ulp_ctx);
-int32_t
-ulp_post_process_tun_flow(struct ulp_rte_parser_params *params);
-
struct bnxt_ulp_glb_resource_info *
bnxt_ulp_app_glb_resource_info_list_get(uint32_t *num_entries);
@@ -301,4 +311,8 @@ bnxt_ulp_cntxt_entry_release(void);
uint8_t
bnxt_ulp_cntxt_num_shared_clients_get(struct bnxt_ulp_context *ulp_ctx);
+
+struct bnxt_flow_app_tun_ent *
+bnxt_ulp_cntxt_ptr2_app_tun_list_get(struct bnxt_ulp_context *ulp);
+
#endif /* _BNXT_ULP_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
index 238b1d9657..3daf5942e8 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
@@ -12,6 +12,7 @@
#include "ulp_fc_mgr.h"
#include "ulp_port_db.h"
#include "ulp_ha_mgr.h"
+#include "ulp_tun.h"
#include <rte_malloc.h>
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
#include "ulp_template_debug_proto.h"
@@ -101,12 +102,13 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms,
mapper_cparms->act_prop = ¶ms->act_prop;
mapper_cparms->flow_id = params->fid;
mapper_cparms->parent_flow = params->parent_flow;
- mapper_cparms->parent_fid = params->parent_fid;
+ mapper_cparms->child_flow = params->child_flow;
mapper_cparms->fld_bitmap = ¶ms->fld_bitmap;
mapper_cparms->flow_pattern_id = params->flow_pattern_id;
mapper_cparms->act_pattern_id = params->act_pattern_id;
mapper_cparms->app_id = params->app_id;
mapper_cparms->port_id = params->port_id;
+ mapper_cparms->tun_idx = params->tun_idx;
/* update the signature fields into the computed field list */
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_HDR_SIG_ID,
@@ -218,12 +220,14 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
params.func_id = func_id;
params.priority = attr->priority;
params.port_id = dev->data->port_id;
+
/* Perform the rte flow post process */
- ret = bnxt_ulp_rte_parser_post_process(¶ms);
+ bnxt_ulp_rte_parser_post_process(¶ms);
+
+ /* do the tunnel offload process if any */
+ ret = ulp_tunnel_offload_process(¶ms);
if (ret == BNXT_TF_RC_ERROR)
goto free_fid;
- else if (ret == BNXT_TF_RC_FID)
- goto return_fid;
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER
@@ -249,7 +253,6 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
if (ret)
goto free_fid;
-return_fid:
bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
flow_id = (struct rte_flow *)((uintptr_t)fid);
@@ -314,11 +317,12 @@ bnxt_ulp_flow_validate(struct rte_eth_dev *dev,
goto parse_error;
/* Perform the rte flow post process */
- ret = bnxt_ulp_rte_parser_post_process(¶ms);
+ bnxt_ulp_rte_parser_post_process(¶ms);
+
+ /* do the tunnel offload process if any */
+ ret = ulp_tunnel_offload_process(¶ms);
if (ret == BNXT_TF_RC_ERROR)
goto parse_error;
- else if (ret == BNXT_TF_RC_FID)
- return 0;
ret = ulp_matcher_pattern_match(¶ms, &class_id);
@@ -475,11 +479,201 @@ bnxt_ulp_flow_query(struct rte_eth_dev *eth_dev,
return rc;
}
+/* Tunnel offload Apis */
+#define BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS 1
+
+static int
+bnxt_ulp_tunnel_decap_set(struct rte_eth_dev *eth_dev,
+ struct rte_flow_tunnel *tunnel,
+ struct rte_flow_action **pmd_actions,
+ uint32_t *num_of_actions,
+ struct rte_flow_error *error)
+{
+ struct bnxt_ulp_context *ulp_ctx;
+ struct bnxt_flow_app_tun_ent *tun_entry;
+ int32_t rc = 0;
+
+ ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev);
+ if (ulp_ctx == NULL) {
+ BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
+ "ULP context uninitialized");
+ return -EINVAL;
+ }
+
+ if (tunnel == NULL) {
+ BNXT_TF_DBG(ERR, "No tunnel specified\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "no tunnel specified");
+ return -EINVAL;
+ }
+
+ if (tunnel->type != RTE_FLOW_ITEM_TYPE_VXLAN) {
+ BNXT_TF_DBG(ERR, "Tunnel type unsupported\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "tunnel type unsupported");
+ return -EINVAL;
+ }
+
+ rc = ulp_app_tun_search_entry(ulp_ctx, tunnel, &tun_entry);
+ if (rc < 0) {
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "tunnel decap set failed");
+ return -EINVAL;
+ }
+
+ rc = ulp_app_tun_entry_set_decap_action(tun_entry);
+ if (rc < 0) {
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "tunnel decap set failed");
+ return -EINVAL;
+ }
+
+ *pmd_actions = &tun_entry->action;
+ *num_of_actions = BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS;
+ return 0;
+}
+
+static int
+bnxt_ulp_tunnel_match(struct rte_eth_dev *eth_dev,
+ struct rte_flow_tunnel *tunnel,
+ struct rte_flow_item **pmd_items,
+ uint32_t *num_of_items,
+ struct rte_flow_error *error)
+{
+ struct bnxt_ulp_context *ulp_ctx;
+ struct bnxt_flow_app_tun_ent *tun_entry;
+ int32_t rc = 0;
+
+ ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev);
+ if (ulp_ctx == NULL) {
+ BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
+ "ULP context uninitialized");
+ return -EINVAL;
+ }
+
+ if (tunnel == NULL) {
+ BNXT_TF_DBG(ERR, "No tunnel specified\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
+ "no tunnel specified");
+ return -EINVAL;
+ }
+
+ if (tunnel->type != RTE_FLOW_ITEM_TYPE_VXLAN) {
+ BNXT_TF_DBG(ERR, "Tunnel type unsupported\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
+ "tunnel type unsupported");
+ return -EINVAL;
+ }
+
+ rc = ulp_app_tun_search_entry(ulp_ctx, tunnel, &tun_entry);
+ if (rc < 0) {
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "tunnel match set failed");
+ return -EINVAL;
+ }
+
+ rc = ulp_app_tun_entry_set_decap_item(tun_entry);
+ if (rc < 0) {
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "tunnel match set failed");
+ return -EINVAL;
+ }
+
+ *pmd_items = &tun_entry->item;
+ *num_of_items = BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS;
+ return 0;
+}
+
+static int
+bnxt_ulp_tunnel_decap_release(struct rte_eth_dev *eth_dev,
+ struct rte_flow_action *pmd_actions,
+ uint32_t num_actions,
+ struct rte_flow_error *error)
+{
+ struct bnxt_ulp_context *ulp_ctx;
+ struct bnxt_flow_app_tun_ent *tun_entry;
+ const struct rte_flow_action *action_item = pmd_actions;
+
+ ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev);
+ if (ulp_ctx == NULL) {
+ BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
+ "ULP context uninitialized");
+ return -EINVAL;
+ }
+ if (num_actions != BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS) {
+ BNXT_TF_DBG(ERR, "num actions is invalid\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "num actions is invalid");
+ return -EINVAL;
+ }
+ while (action_item && action_item->type != RTE_FLOW_ACTION_TYPE_END) {
+ if (action_item->type == (typeof(tun_entry->action.type))
+ BNXT_RTE_FLOW_ACTION_TYPE_VXLAN_DECAP) {
+ tun_entry = ulp_app_tun_match_entry(ulp_ctx,
+ action_item->conf);
+ ulp_app_tun_entry_delete(tun_entry);
+ }
+ action_item++;
+ }
+ return 0;
+}
+
+static int
+bnxt_ulp_tunnel_item_release(struct rte_eth_dev *eth_dev,
+ struct rte_flow_item *pmd_items,
+ uint32_t num_items,
+ struct rte_flow_error *error)
+{
+ struct bnxt_ulp_context *ulp_ctx;
+ struct bnxt_flow_app_tun_ent *tun_entry;
+
+ ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev);
+ if (ulp_ctx == NULL) {
+ BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
+ "ULP context uninitialized");
+ return -EINVAL;
+ }
+ if (num_items != BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS) {
+ BNXT_TF_DBG(ERR, "num items is invalid\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "num items is invalid");
+ return -EINVAL;
+ }
+
+ tun_entry = ulp_app_tun_match_entry(ulp_ctx, pmd_items->spec);
+ ulp_app_tun_entry_delete(tun_entry);
+ return 0;
+}
+
const struct rte_flow_ops bnxt_ulp_rte_flow_ops = {
.validate = bnxt_ulp_flow_validate,
.create = bnxt_ulp_flow_create,
.destroy = bnxt_ulp_flow_destroy,
.flush = bnxt_ulp_flow_flush,
.query = bnxt_ulp_flow_query,
- .isolate = NULL
+ .isolate = NULL,
+ /* Tunnel offload callbacks */
+ .tunnel_decap_set = bnxt_ulp_tunnel_decap_set,
+ .tunnel_match = bnxt_ulp_tunnel_match,
+ .tunnel_action_decap_release = bnxt_ulp_tunnel_decap_release,
+ .tunnel_item_release = bnxt_ulp_tunnel_item_release,
+ .get_restore_info = NULL
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c
index e18f314856..0da6070d7d 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Wed Mar 17 11:31:19 2021 */
+/* date: Mon May 17 15:30:41 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
index 9c419f6a15..f74687acfa 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Wed Mar 17 11:31:19 2021 */
+/* date: Thu May 20 11:56:39 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -360,348 +360,510 @@ uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {
[BNXT_ULP_CLASS_HID_15db] = 342,
[BNXT_ULP_CLASS_HID_1151] = 343,
[BNXT_ULP_CLASS_HID_315d] = 344,
- [BNXT_ULP_CLASS_HID_34c6] = 345,
- [BNXT_ULP_CLASS_HID_0c22] = 346,
- [BNXT_ULP_CLASS_HID_1cbe] = 347,
- [BNXT_ULP_CLASS_HID_179a] = 348,
- [BNXT_ULP_CLASS_HID_59be] = 349,
- [BNXT_ULP_CLASS_HID_515a] = 350,
- [BNXT_ULP_CLASS_HID_1c72] = 351,
- [BNXT_ULP_CLASS_HID_171e] = 352,
- [BNXT_ULP_CLASS_HID_19c8] = 353,
- [BNXT_ULP_CLASS_HID_112c] = 354,
- [BNXT_ULP_CLASS_HID_4d68] = 355,
- [BNXT_ULP_CLASS_HID_444c] = 356,
- [BNXT_ULP_CLASS_HID_0e8c] = 357,
- [BNXT_ULP_CLASS_HID_09e0] = 358,
- [BNXT_ULP_CLASS_HID_1af0] = 359,
- [BNXT_ULP_CLASS_HID_15d4] = 360,
- [BNXT_ULP_CLASS_HID_1dd0] = 361,
- [BNXT_ULP_CLASS_HID_14f4] = 362,
- [BNXT_ULP_CLASS_HID_70b0] = 363,
- [BNXT_ULP_CLASS_HID_4854] = 364,
- [BNXT_ULP_CLASS_HID_3dd4] = 365,
- [BNXT_ULP_CLASS_HID_34f8] = 366,
- [BNXT_ULP_CLASS_HID_09e8] = 367,
- [BNXT_ULP_CLASS_HID_008c] = 368,
- [BNXT_ULP_CLASS_HID_34e6] = 369,
- [BNXT_ULP_CLASS_HID_0c02] = 370,
- [BNXT_ULP_CLASS_HID_1c9e] = 371,
- [BNXT_ULP_CLASS_HID_17ba] = 372,
- [BNXT_ULP_CLASS_HID_429e] = 373,
- [BNXT_ULP_CLASS_HID_5dba] = 374,
- [BNXT_ULP_CLASS_HID_2a16] = 375,
- [BNXT_ULP_CLASS_HID_2532] = 376,
- [BNXT_ULP_CLASS_HID_2da2] = 377,
- [BNXT_ULP_CLASS_HID_24fe] = 378,
- [BNXT_ULP_CLASS_HID_355a] = 379,
- [BNXT_ULP_CLASS_HID_0c76] = 380,
- [BNXT_ULP_CLASS_HID_13e6] = 381,
- [BNXT_ULP_CLASS_HID_7276] = 382,
- [BNXT_ULP_CLASS_HID_42d2] = 383,
- [BNXT_ULP_CLASS_HID_5dee] = 384,
- [BNXT_ULP_CLASS_HID_59de] = 385,
- [BNXT_ULP_CLASS_HID_513a] = 386,
- [BNXT_ULP_CLASS_HID_1c12] = 387,
- [BNXT_ULP_CLASS_HID_177e] = 388,
- [BNXT_ULP_CLASS_HID_0e92] = 389,
- [BNXT_ULP_CLASS_HID_09fe] = 390,
- [BNXT_ULP_CLASS_HID_5c1a] = 391,
- [BNXT_ULP_CLASS_HID_5746] = 392,
- [BNXT_ULP_CLASS_HID_79da] = 393,
- [BNXT_ULP_CLASS_HID_7106] = 394,
- [BNXT_ULP_CLASS_HID_3c1e] = 395,
- [BNXT_ULP_CLASS_HID_377a] = 396,
- [BNXT_ULP_CLASS_HID_2e9e] = 397,
- [BNXT_ULP_CLASS_HID_29fa] = 398,
- [BNXT_ULP_CLASS_HID_14d2] = 399,
- [BNXT_ULP_CLASS_HID_7742] = 400,
- [BNXT_ULP_CLASS_HID_3706] = 401,
- [BNXT_ULP_CLASS_HID_0fe2] = 402,
- [BNXT_ULP_CLASS_HID_1f7e] = 403,
- [BNXT_ULP_CLASS_HID_145a] = 404,
- [BNXT_ULP_CLASS_HID_417e] = 405,
- [BNXT_ULP_CLASS_HID_5e5a] = 406,
- [BNXT_ULP_CLASS_HID_29f6] = 407,
- [BNXT_ULP_CLASS_HID_26d2] = 408,
- [BNXT_ULP_CLASS_HID_2e42] = 409,
- [BNXT_ULP_CLASS_HID_271e] = 410,
- [BNXT_ULP_CLASS_HID_36ba] = 411,
- [BNXT_ULP_CLASS_HID_0f96] = 412,
- [BNXT_ULP_CLASS_HID_1006] = 413,
- [BNXT_ULP_CLASS_HID_7196] = 414,
- [BNXT_ULP_CLASS_HID_4132] = 415,
- [BNXT_ULP_CLASS_HID_5e0e] = 416,
- [BNXT_ULP_CLASS_HID_59fe] = 417,
- [BNXT_ULP_CLASS_HID_511a] = 418,
- [BNXT_ULP_CLASS_HID_1c32] = 419,
- [BNXT_ULP_CLASS_HID_175e] = 420,
- [BNXT_ULP_CLASS_HID_0eb2] = 421,
- [BNXT_ULP_CLASS_HID_09de] = 422,
- [BNXT_ULP_CLASS_HID_5c3a] = 423,
- [BNXT_ULP_CLASS_HID_5766] = 424,
- [BNXT_ULP_CLASS_HID_79fa] = 425,
- [BNXT_ULP_CLASS_HID_7126] = 426,
- [BNXT_ULP_CLASS_HID_3c3e] = 427,
- [BNXT_ULP_CLASS_HID_375a] = 428,
- [BNXT_ULP_CLASS_HID_2ebe] = 429,
- [BNXT_ULP_CLASS_HID_29da] = 430,
- [BNXT_ULP_CLASS_HID_14f2] = 431,
- [BNXT_ULP_CLASS_HID_7762] = 432,
- [BNXT_ULP_CLASS_HID_19e8] = 433,
- [BNXT_ULP_CLASS_HID_110c] = 434,
- [BNXT_ULP_CLASS_HID_4d48] = 435,
- [BNXT_ULP_CLASS_HID_446c] = 436,
- [BNXT_ULP_CLASS_HID_0eac] = 437,
- [BNXT_ULP_CLASS_HID_09c0] = 438,
- [BNXT_ULP_CLASS_HID_1ad0] = 439,
- [BNXT_ULP_CLASS_HID_15f4] = 440,
- [BNXT_ULP_CLASS_HID_39ec] = 441,
- [BNXT_ULP_CLASS_HID_3100] = 442,
- [BNXT_ULP_CLASS_HID_0210] = 443,
- [BNXT_ULP_CLASS_HID_1d34] = 444,
- [BNXT_ULP_CLASS_HID_2ea0] = 445,
- [BNXT_ULP_CLASS_HID_29c4] = 446,
- [BNXT_ULP_CLASS_HID_3ad4] = 447,
- [BNXT_ULP_CLASS_HID_35e8] = 448,
- [BNXT_ULP_CLASS_HID_5d80] = 449,
- [BNXT_ULP_CLASS_HID_54a4] = 450,
- [BNXT_ULP_CLASS_HID_29b4] = 451,
- [BNXT_ULP_CLASS_HID_20c8] = 452,
- [BNXT_ULP_CLASS_HID_7244] = 453,
- [BNXT_ULP_CLASS_HID_4d98] = 454,
- [BNXT_ULP_CLASS_HID_5e68] = 455,
- [BNXT_ULP_CLASS_HID_598c] = 456,
- [BNXT_ULP_CLASS_HID_1248] = 457,
- [BNXT_ULP_CLASS_HID_74d8] = 458,
- [BNXT_ULP_CLASS_HID_49a8] = 459,
- [BNXT_ULP_CLASS_HID_40cc] = 460,
- [BNXT_ULP_CLASS_HID_0b0c] = 461,
- [BNXT_ULP_CLASS_HID_0220] = 462,
- [BNXT_ULP_CLASS_HID_1730] = 463,
- [BNXT_ULP_CLASS_HID_7980] = 464,
- [BNXT_ULP_CLASS_HID_1db0] = 465,
- [BNXT_ULP_CLASS_HID_1494] = 466,
- [BNXT_ULP_CLASS_HID_70d0] = 467,
- [BNXT_ULP_CLASS_HID_4834] = 468,
- [BNXT_ULP_CLASS_HID_3db4] = 469,
- [BNXT_ULP_CLASS_HID_3498] = 470,
- [BNXT_ULP_CLASS_HID_0988] = 471,
- [BNXT_ULP_CLASS_HID_00ec] = 472,
- [BNXT_ULP_CLASS_HID_3f44] = 473,
- [BNXT_ULP_CLASS_HID_36a8] = 474,
- [BNXT_ULP_CLASS_HID_0b58] = 475,
- [BNXT_ULP_CLASS_HID_02bc] = 476,
- [BNXT_ULP_CLASS_HID_5f48] = 477,
- [BNXT_ULP_CLASS_HID_56ac] = 478,
- [BNXT_ULP_CLASS_HID_2b5c] = 479,
- [BNXT_ULP_CLASS_HID_2280] = 480,
- [BNXT_ULP_CLASS_HID_4000] = 481,
- [BNXT_ULP_CLASS_HID_5b64] = 482,
- [BNXT_ULP_CLASS_HID_2c14] = 483,
- [BNXT_ULP_CLASS_HID_2778] = 484,
- [BNXT_ULP_CLASS_HID_18f8] = 485,
- [BNXT_ULP_CLASS_HID_13dc] = 486,
- [BNXT_ULP_CLASS_HID_4c18] = 487,
- [BNXT_ULP_CLASS_HID_477c] = 488,
- [BNXT_ULP_CLASS_HID_1a88] = 489,
- [BNXT_ULP_CLASS_HID_15ec] = 490,
- [BNXT_ULP_CLASS_HID_4e28] = 491,
- [BNXT_ULP_CLASS_HID_490c] = 492,
- [BNXT_ULP_CLASS_HID_3a8c] = 493,
- [BNXT_ULP_CLASS_HID_35f0] = 494,
- [BNXT_ULP_CLASS_HID_06e0] = 495,
- [BNXT_ULP_CLASS_HID_01c4] = 496,
- [BNXT_ULP_CLASS_HID_1a08] = 497,
- [BNXT_ULP_CLASS_HID_12ec] = 498,
- [BNXT_ULP_CLASS_HID_4ea8] = 499,
- [BNXT_ULP_CLASS_HID_478c] = 500,
- [BNXT_ULP_CLASS_HID_0d4c] = 501,
- [BNXT_ULP_CLASS_HID_0a20] = 502,
- [BNXT_ULP_CLASS_HID_1930] = 503,
- [BNXT_ULP_CLASS_HID_1614] = 504,
- [BNXT_ULP_CLASS_HID_3a0c] = 505,
- [BNXT_ULP_CLASS_HID_32e0] = 506,
- [BNXT_ULP_CLASS_HID_01f0] = 507,
- [BNXT_ULP_CLASS_HID_1ed4] = 508,
- [BNXT_ULP_CLASS_HID_2d40] = 509,
- [BNXT_ULP_CLASS_HID_2a24] = 510,
- [BNXT_ULP_CLASS_HID_3934] = 511,
- [BNXT_ULP_CLASS_HID_3608] = 512,
- [BNXT_ULP_CLASS_HID_5e60] = 513,
- [BNXT_ULP_CLASS_HID_5744] = 514,
- [BNXT_ULP_CLASS_HID_2a54] = 515,
- [BNXT_ULP_CLASS_HID_2328] = 516,
- [BNXT_ULP_CLASS_HID_71a4] = 517,
- [BNXT_ULP_CLASS_HID_4e78] = 518,
- [BNXT_ULP_CLASS_HID_5d88] = 519,
- [BNXT_ULP_CLASS_HID_5a6c] = 520,
- [BNXT_ULP_CLASS_HID_11a8] = 521,
- [BNXT_ULP_CLASS_HID_7738] = 522,
- [BNXT_ULP_CLASS_HID_4a48] = 523,
- [BNXT_ULP_CLASS_HID_432c] = 524,
- [BNXT_ULP_CLASS_HID_08ec] = 525,
- [BNXT_ULP_CLASS_HID_01c0] = 526,
- [BNXT_ULP_CLASS_HID_14d0] = 527,
- [BNXT_ULP_CLASS_HID_7a60] = 528,
- [BNXT_ULP_CLASS_HID_1d90] = 529,
- [BNXT_ULP_CLASS_HID_14b4] = 530,
- [BNXT_ULP_CLASS_HID_70f0] = 531,
- [BNXT_ULP_CLASS_HID_4814] = 532,
- [BNXT_ULP_CLASS_HID_3d94] = 533,
- [BNXT_ULP_CLASS_HID_34b8] = 534,
- [BNXT_ULP_CLASS_HID_09a8] = 535,
- [BNXT_ULP_CLASS_HID_00cc] = 536,
- [BNXT_ULP_CLASS_HID_3f64] = 537,
- [BNXT_ULP_CLASS_HID_3688] = 538,
- [BNXT_ULP_CLASS_HID_0b78] = 539,
- [BNXT_ULP_CLASS_HID_029c] = 540,
- [BNXT_ULP_CLASS_HID_5f68] = 541,
- [BNXT_ULP_CLASS_HID_568c] = 542,
- [BNXT_ULP_CLASS_HID_2b7c] = 543,
- [BNXT_ULP_CLASS_HID_22a0] = 544,
- [BNXT_ULP_CLASS_HID_4020] = 545,
- [BNXT_ULP_CLASS_HID_5b44] = 546,
- [BNXT_ULP_CLASS_HID_2c34] = 547,
- [BNXT_ULP_CLASS_HID_2758] = 548,
- [BNXT_ULP_CLASS_HID_18d8] = 549,
- [BNXT_ULP_CLASS_HID_13fc] = 550,
- [BNXT_ULP_CLASS_HID_4c38] = 551,
- [BNXT_ULP_CLASS_HID_475c] = 552,
- [BNXT_ULP_CLASS_HID_1aa8] = 553,
- [BNXT_ULP_CLASS_HID_15cc] = 554,
- [BNXT_ULP_CLASS_HID_4e08] = 555,
- [BNXT_ULP_CLASS_HID_492c] = 556,
- [BNXT_ULP_CLASS_HID_3aac] = 557,
- [BNXT_ULP_CLASS_HID_35d0] = 558,
- [BNXT_ULP_CLASS_HID_06c0] = 559,
- [BNXT_ULP_CLASS_HID_01e4] = 560,
- [BNXT_ULP_CLASS_HID_4d32] = 561,
- [BNXT_ULP_CLASS_HID_54aa] = 562,
- [BNXT_ULP_CLASS_HID_0686] = 563,
- [BNXT_ULP_CLASS_HID_540e] = 564,
- [BNXT_ULP_CLASS_HID_2e3c] = 565,
- [BNXT_ULP_CLASS_HID_3a20] = 566,
- [BNXT_ULP_CLASS_HID_46f0] = 567,
- [BNXT_ULP_CLASS_HID_52e4] = 568,
- [BNXT_ULP_CLASS_HID_55e4] = 569,
- [BNXT_ULP_CLASS_HID_21f8] = 570,
- [BNXT_ULP_CLASS_HID_75e8] = 571,
- [BNXT_ULP_CLASS_HID_41fc] = 572,
- [BNXT_ULP_CLASS_HID_4d12] = 573,
- [BNXT_ULP_CLASS_HID_548a] = 574,
- [BNXT_ULP_CLASS_HID_3356] = 575,
- [BNXT_ULP_CLASS_HID_1ace] = 576,
- [BNXT_ULP_CLASS_HID_1a9a] = 577,
- [BNXT_ULP_CLASS_HID_4d46] = 578,
- [BNXT_ULP_CLASS_HID_2812] = 579,
- [BNXT_ULP_CLASS_HID_338a] = 580,
- [BNXT_ULP_CLASS_HID_06e6] = 581,
- [BNXT_ULP_CLASS_HID_546e] = 582,
- [BNXT_ULP_CLASS_HID_46ee] = 583,
- [BNXT_ULP_CLASS_HID_0d22] = 584,
- [BNXT_ULP_CLASS_HID_26e2] = 585,
- [BNXT_ULP_CLASS_HID_746a] = 586,
- [BNXT_ULP_CLASS_HID_1fa6] = 587,
- [BNXT_ULP_CLASS_HID_2d2e] = 588,
- [BNXT_ULP_CLASS_HID_4ef2] = 589,
- [BNXT_ULP_CLASS_HID_576a] = 590,
- [BNXT_ULP_CLASS_HID_30b6] = 591,
- [BNXT_ULP_CLASS_HID_192e] = 592,
- [BNXT_ULP_CLASS_HID_197a] = 593,
- [BNXT_ULP_CLASS_HID_4ea6] = 594,
- [BNXT_ULP_CLASS_HID_2bf2] = 595,
- [BNXT_ULP_CLASS_HID_306a] = 596,
- [BNXT_ULP_CLASS_HID_06c6] = 597,
- [BNXT_ULP_CLASS_HID_544e] = 598,
- [BNXT_ULP_CLASS_HID_46ce] = 599,
- [BNXT_ULP_CLASS_HID_0d02] = 600,
- [BNXT_ULP_CLASS_HID_26c2] = 601,
- [BNXT_ULP_CLASS_HID_744a] = 602,
- [BNXT_ULP_CLASS_HID_1f86] = 603,
- [BNXT_ULP_CLASS_HID_2d0e] = 604,
- [BNXT_ULP_CLASS_HID_2e1c] = 605,
- [BNXT_ULP_CLASS_HID_3a00] = 606,
- [BNXT_ULP_CLASS_HID_46d0] = 607,
- [BNXT_ULP_CLASS_HID_52c4] = 608,
- [BNXT_ULP_CLASS_HID_4e10] = 609,
- [BNXT_ULP_CLASS_HID_5a04] = 610,
- [BNXT_ULP_CLASS_HID_1f98] = 611,
- [BNXT_ULP_CLASS_HID_72f8] = 612,
- [BNXT_ULP_CLASS_HID_0a78] = 613,
- [BNXT_ULP_CLASS_HID_166c] = 614,
- [BNXT_ULP_CLASS_HID_233c] = 615,
- [BNXT_ULP_CLASS_HID_0f20] = 616,
- [BNXT_ULP_CLASS_HID_2a7c] = 617,
- [BNXT_ULP_CLASS_HID_3660] = 618,
- [BNXT_ULP_CLASS_HID_4330] = 619,
- [BNXT_ULP_CLASS_HID_2f24] = 620,
- [BNXT_ULP_CLASS_HID_5584] = 621,
- [BNXT_ULP_CLASS_HID_2198] = 622,
- [BNXT_ULP_CLASS_HID_7588] = 623,
- [BNXT_ULP_CLASS_HID_419c] = 624,
- [BNXT_ULP_CLASS_HID_7758] = 625,
- [BNXT_ULP_CLASS_HID_43ac] = 626,
- [BNXT_ULP_CLASS_HID_0c10] = 627,
- [BNXT_ULP_CLASS_HID_1864] = 628,
- [BNXT_ULP_CLASS_HID_30c8] = 629,
- [BNXT_ULP_CLASS_HID_1cdc] = 630,
- [BNXT_ULP_CLASS_HID_50cc] = 631,
- [BNXT_ULP_CLASS_HID_3d20] = 632,
- [BNXT_ULP_CLASS_HID_529c] = 633,
- [BNXT_ULP_CLASS_HID_3ef0] = 634,
- [BNXT_ULP_CLASS_HID_72e0] = 635,
- [BNXT_ULP_CLASS_HID_5ef4] = 636,
- [BNXT_ULP_CLASS_HID_2dfc] = 637,
- [BNXT_ULP_CLASS_HID_39e0] = 638,
- [BNXT_ULP_CLASS_HID_4530] = 639,
- [BNXT_ULP_CLASS_HID_5124] = 640,
- [BNXT_ULP_CLASS_HID_4df0] = 641,
- [BNXT_ULP_CLASS_HID_59e4] = 642,
- [BNXT_ULP_CLASS_HID_1c78] = 643,
- [BNXT_ULP_CLASS_HID_7118] = 644,
- [BNXT_ULP_CLASS_HID_0998] = 645,
- [BNXT_ULP_CLASS_HID_158c] = 646,
- [BNXT_ULP_CLASS_HID_20dc] = 647,
- [BNXT_ULP_CLASS_HID_0cc0] = 648,
- [BNXT_ULP_CLASS_HID_299c] = 649,
- [BNXT_ULP_CLASS_HID_3580] = 650,
- [BNXT_ULP_CLASS_HID_40d0] = 651,
- [BNXT_ULP_CLASS_HID_2cc4] = 652,
- [BNXT_ULP_CLASS_HID_55a4] = 653,
- [BNXT_ULP_CLASS_HID_21b8] = 654,
- [BNXT_ULP_CLASS_HID_75a8] = 655,
- [BNXT_ULP_CLASS_HID_41bc] = 656,
- [BNXT_ULP_CLASS_HID_7778] = 657,
- [BNXT_ULP_CLASS_HID_438c] = 658,
- [BNXT_ULP_CLASS_HID_0c30] = 659,
- [BNXT_ULP_CLASS_HID_1844] = 660,
- [BNXT_ULP_CLASS_HID_30e8] = 661,
- [BNXT_ULP_CLASS_HID_1cfc] = 662,
- [BNXT_ULP_CLASS_HID_50ec] = 663,
- [BNXT_ULP_CLASS_HID_3d00] = 664,
- [BNXT_ULP_CLASS_HID_52bc] = 665,
- [BNXT_ULP_CLASS_HID_3ed0] = 666,
- [BNXT_ULP_CLASS_HID_72c0] = 667,
- [BNXT_ULP_CLASS_HID_5ed4] = 668,
- [BNXT_ULP_CLASS_HID_3866] = 669,
- [BNXT_ULP_CLASS_HID_381e] = 670,
- [BNXT_ULP_CLASS_HID_3860] = 671,
- [BNXT_ULP_CLASS_HID_0454] = 672,
- [BNXT_ULP_CLASS_HID_3818] = 673,
- [BNXT_ULP_CLASS_HID_042c] = 674,
- [BNXT_ULP_CLASS_HID_3846] = 675,
- [BNXT_ULP_CLASS_HID_387e] = 676,
- [BNXT_ULP_CLASS_HID_3ba6] = 677,
- [BNXT_ULP_CLASS_HID_385e] = 678,
- [BNXT_ULP_CLASS_HID_3840] = 679,
- [BNXT_ULP_CLASS_HID_0474] = 680,
- [BNXT_ULP_CLASS_HID_3878] = 681,
- [BNXT_ULP_CLASS_HID_044c] = 682,
- [BNXT_ULP_CLASS_HID_3ba0] = 683,
- [BNXT_ULP_CLASS_HID_0794] = 684,
- [BNXT_ULP_CLASS_HID_3858] = 685,
- [BNXT_ULP_CLASS_HID_046c] = 686
+ [BNXT_ULP_CLASS_HID_3612] = 345,
+ [BNXT_ULP_CLASS_HID_66da] = 346,
+ [BNXT_ULP_CLASS_HID_6165] = 347,
+ [BNXT_ULP_CLASS_HID_2aa1] = 348,
+ [BNXT_ULP_CLASS_HID_09cd] = 349,
+ [BNXT_ULP_CLASS_HID_3845] = 350,
+ [BNXT_ULP_CLASS_HID_11e9] = 351,
+ [BNXT_ULP_CLASS_HID_4361] = 352,
+ [BNXT_ULP_CLASS_HID_218d] = 353,
+ [BNXT_ULP_CLASS_HID_5105] = 354,
+ [BNXT_ULP_CLASS_HID_0c89] = 355,
+ [BNXT_ULP_CLASS_HID_3e81] = 356,
+ [BNXT_ULP_CLASS_HID_1dad] = 357,
+ [BNXT_ULP_CLASS_HID_4ca5] = 358,
+ [BNXT_ULP_CLASS_HID_25c9] = 359,
+ [BNXT_ULP_CLASS_HID_57c1] = 360,
+ [BNXT_ULP_CLASS_HID_33ed] = 361,
+ [BNXT_ULP_CLASS_HID_65e5] = 362,
+ [BNXT_ULP_CLASS_HID_6dd9] = 363,
+ [BNXT_ULP_CLASS_HID_261d] = 364,
+ [BNXT_ULP_CLASS_HID_0571] = 365,
+ [BNXT_ULP_CLASS_HID_34f9] = 366,
+ [BNXT_ULP_CLASS_HID_1d55] = 367,
+ [BNXT_ULP_CLASS_HID_4fdd] = 368,
+ [BNXT_ULP_CLASS_HID_2d31] = 369,
+ [BNXT_ULP_CLASS_HID_5db9] = 370,
+ [BNXT_ULP_CLASS_HID_0035] = 371,
+ [BNXT_ULP_CLASS_HID_323d] = 372,
+ [BNXT_ULP_CLASS_HID_1111] = 373,
+ [BNXT_ULP_CLASS_HID_4019] = 374,
+ [BNXT_ULP_CLASS_HID_2975] = 375,
+ [BNXT_ULP_CLASS_HID_5b7d] = 376,
+ [BNXT_ULP_CLASS_HID_3f51] = 377,
+ [BNXT_ULP_CLASS_HID_6959] = 378,
+ [BNXT_ULP_CLASS_HID_0e85] = 379,
+ [BNXT_ULP_CLASS_HID_380d] = 380,
+ [BNXT_ULP_CLASS_HID_1f21] = 381,
+ [BNXT_ULP_CLASS_HID_4ea9] = 382,
+ [BNXT_ULP_CLASS_HID_1705] = 383,
+ [BNXT_ULP_CLASS_HID_418d] = 384,
+ [BNXT_ULP_CLASS_HID_2721] = 385,
+ [BNXT_ULP_CLASS_HID_57a9] = 386,
+ [BNXT_ULP_CLASS_HID_1a25] = 387,
+ [BNXT_ULP_CLASS_HID_342d] = 388,
+ [BNXT_ULP_CLASS_HID_2b01] = 389,
+ [BNXT_ULP_CLASS_HID_5a09] = 390,
+ [BNXT_ULP_CLASS_HID_2325] = 391,
+ [BNXT_ULP_CLASS_HID_5d2d] = 392,
+ [BNXT_ULP_CLASS_HID_3101] = 393,
+ [BNXT_ULP_CLASS_HID_6309] = 394,
+ [BNXT_ULP_CLASS_HID_0bad] = 395,
+ [BNXT_ULP_CLASS_HID_2535] = 396,
+ [BNXT_ULP_CLASS_HID_1869] = 397,
+ [BNXT_ULP_CLASS_HID_4bf1] = 398,
+ [BNXT_ULP_CLASS_HID_136d] = 399,
+ [BNXT_ULP_CLASS_HID_43f5] = 400,
+ [BNXT_ULP_CLASS_HID_2129] = 401,
+ [BNXT_ULP_CLASS_HID_53b1] = 402,
+ [BNXT_ULP_CLASS_HID_072d] = 403,
+ [BNXT_ULP_CLASS_HID_3135] = 404,
+ [BNXT_ULP_CLASS_HID_1429] = 405,
+ [BNXT_ULP_CLASS_HID_4731] = 406,
+ [BNXT_ULP_CLASS_HID_2f6d] = 407,
+ [BNXT_ULP_CLASS_HID_5f75] = 408,
+ [BNXT_ULP_CLASS_HID_3d69] = 409,
+ [BNXT_ULP_CLASS_HID_6f71] = 410,
+ [BNXT_ULP_CLASS_HID_0dbd] = 411,
+ [BNXT_ULP_CLASS_HID_3f25] = 412,
+ [BNXT_ULP_CLASS_HID_1239] = 413,
+ [BNXT_ULP_CLASS_HID_4da1] = 414,
+ [BNXT_ULP_CLASS_HID_153d] = 415,
+ [BNXT_ULP_CLASS_HID_45a5] = 416,
+ [BNXT_ULP_CLASS_HID_3bb9] = 417,
+ [BNXT_ULP_CLASS_HID_55a1] = 418,
+ [BNXT_ULP_CLASS_HID_193d] = 419,
+ [BNXT_ULP_CLASS_HID_4b25] = 420,
+ [BNXT_ULP_CLASS_HID_2e39] = 421,
+ [BNXT_ULP_CLASS_HID_5921] = 422,
+ [BNXT_ULP_CLASS_HID_213d] = 423,
+ [BNXT_ULP_CLASS_HID_5125] = 424,
+ [BNXT_ULP_CLASS_HID_3739] = 425,
+ [BNXT_ULP_CLASS_HID_093d] = 426,
+ [BNXT_ULP_CLASS_HID_684d] = 427,
+ [BNXT_ULP_CLASS_HID_2389] = 428,
+ [BNXT_ULP_CLASS_HID_00e5] = 429,
+ [BNXT_ULP_CLASS_HID_316d] = 430,
+ [BNXT_ULP_CLASS_HID_18c1] = 431,
+ [BNXT_ULP_CLASS_HID_4a49] = 432,
+ [BNXT_ULP_CLASS_HID_28a5] = 433,
+ [BNXT_ULP_CLASS_HID_582d] = 434,
+ [BNXT_ULP_CLASS_HID_05a1] = 435,
+ [BNXT_ULP_CLASS_HID_37a9] = 436,
+ [BNXT_ULP_CLASS_HID_1485] = 437,
+ [BNXT_ULP_CLASS_HID_458d] = 438,
+ [BNXT_ULP_CLASS_HID_2ce1] = 439,
+ [BNXT_ULP_CLASS_HID_5ee9] = 440,
+ [BNXT_ULP_CLASS_HID_3ac5] = 441,
+ [BNXT_ULP_CLASS_HID_6ccd] = 442,
+ [BNXT_ULP_CLASS_HID_0b11] = 443,
+ [BNXT_ULP_CLASS_HID_3d99] = 444,
+ [BNXT_ULP_CLASS_HID_1ab5] = 445,
+ [BNXT_ULP_CLASS_HID_4b3d] = 446,
+ [BNXT_ULP_CLASS_HID_1291] = 447,
+ [BNXT_ULP_CLASS_HID_4419] = 448,
+ [BNXT_ULP_CLASS_HID_22b5] = 449,
+ [BNXT_ULP_CLASS_HID_523d] = 450,
+ [BNXT_ULP_CLASS_HID_1fb1] = 451,
+ [BNXT_ULP_CLASS_HID_31b9] = 452,
+ [BNXT_ULP_CLASS_HID_2e95] = 453,
+ [BNXT_ULP_CLASS_HID_5f9d] = 454,
+ [BNXT_ULP_CLASS_HID_26b1] = 455,
+ [BNXT_ULP_CLASS_HID_58b9] = 456,
+ [BNXT_ULP_CLASS_HID_3495] = 457,
+ [BNXT_ULP_CLASS_HID_669d] = 458,
+ [BNXT_ULP_CLASS_HID_0e39] = 459,
+ [BNXT_ULP_CLASS_HID_20a1] = 460,
+ [BNXT_ULP_CLASS_HID_1dfd] = 461,
+ [BNXT_ULP_CLASS_HID_4e65] = 462,
+ [BNXT_ULP_CLASS_HID_16f9] = 463,
+ [BNXT_ULP_CLASS_HID_4661] = 464,
+ [BNXT_ULP_CLASS_HID_24bd] = 465,
+ [BNXT_ULP_CLASS_HID_5625] = 466,
+ [BNXT_ULP_CLASS_HID_02b9] = 467,
+ [BNXT_ULP_CLASS_HID_34a1] = 468,
+ [BNXT_ULP_CLASS_HID_11bd] = 469,
+ [BNXT_ULP_CLASS_HID_42a5] = 470,
+ [BNXT_ULP_CLASS_HID_2af9] = 471,
+ [BNXT_ULP_CLASS_HID_5ae1] = 472,
+ [BNXT_ULP_CLASS_HID_38fd] = 473,
+ [BNXT_ULP_CLASS_HID_6ae5] = 474,
+ [BNXT_ULP_CLASS_HID_0829] = 475,
+ [BNXT_ULP_CLASS_HID_3ab1] = 476,
+ [BNXT_ULP_CLASS_HID_17ad] = 477,
+ [BNXT_ULP_CLASS_HID_4835] = 478,
+ [BNXT_ULP_CLASS_HID_10a9] = 479,
+ [BNXT_ULP_CLASS_HID_4031] = 480,
+ [BNXT_ULP_CLASS_HID_3e2d] = 481,
+ [BNXT_ULP_CLASS_HID_5035] = 482,
+ [BNXT_ULP_CLASS_HID_1ca9] = 483,
+ [BNXT_ULP_CLASS_HID_4eb1] = 484,
+ [BNXT_ULP_CLASS_HID_2bad] = 485,
+ [BNXT_ULP_CLASS_HID_5cb5] = 486,
+ [BNXT_ULP_CLASS_HID_24a9] = 487,
+ [BNXT_ULP_CLASS_HID_54b1] = 488,
+ [BNXT_ULP_CLASS_HID_32ad] = 489,
+ [BNXT_ULP_CLASS_HID_0ca9] = 490,
+ [BNXT_ULP_CLASS_HID_7f35] = 491,
+ [BNXT_ULP_CLASS_HID_34f1] = 492,
+ [BNXT_ULP_CLASS_HID_179d] = 493,
+ [BNXT_ULP_CLASS_HID_2615] = 494,
+ [BNXT_ULP_CLASS_HID_0fb9] = 495,
+ [BNXT_ULP_CLASS_HID_5d31] = 496,
+ [BNXT_ULP_CLASS_HID_3fdd] = 497,
+ [BNXT_ULP_CLASS_HID_4f55] = 498,
+ [BNXT_ULP_CLASS_HID_12d9] = 499,
+ [BNXT_ULP_CLASS_HID_20d1] = 500,
+ [BNXT_ULP_CLASS_HID_03fd] = 501,
+ [BNXT_ULP_CLASS_HID_52f5] = 502,
+ [BNXT_ULP_CLASS_HID_3b99] = 503,
+ [BNXT_ULP_CLASS_HID_4991] = 504,
+ [BNXT_ULP_CLASS_HID_2dbd] = 505,
+ [BNXT_ULP_CLASS_HID_7bb5] = 506,
+ [BNXT_ULP_CLASS_HID_34c6] = 507,
+ [BNXT_ULP_CLASS_HID_0c22] = 508,
+ [BNXT_ULP_CLASS_HID_1cbe] = 509,
+ [BNXT_ULP_CLASS_HID_179a] = 510,
+ [BNXT_ULP_CLASS_HID_59be] = 511,
+ [BNXT_ULP_CLASS_HID_515a] = 512,
+ [BNXT_ULP_CLASS_HID_1c72] = 513,
+ [BNXT_ULP_CLASS_HID_171e] = 514,
+ [BNXT_ULP_CLASS_HID_19c8] = 515,
+ [BNXT_ULP_CLASS_HID_112c] = 516,
+ [BNXT_ULP_CLASS_HID_4d68] = 517,
+ [BNXT_ULP_CLASS_HID_444c] = 518,
+ [BNXT_ULP_CLASS_HID_0e8c] = 519,
+ [BNXT_ULP_CLASS_HID_09e0] = 520,
+ [BNXT_ULP_CLASS_HID_1af0] = 521,
+ [BNXT_ULP_CLASS_HID_15d4] = 522,
+ [BNXT_ULP_CLASS_HID_1dd0] = 523,
+ [BNXT_ULP_CLASS_HID_14f4] = 524,
+ [BNXT_ULP_CLASS_HID_70b0] = 525,
+ [BNXT_ULP_CLASS_HID_4854] = 526,
+ [BNXT_ULP_CLASS_HID_3dd4] = 527,
+ [BNXT_ULP_CLASS_HID_34f8] = 528,
+ [BNXT_ULP_CLASS_HID_09e8] = 529,
+ [BNXT_ULP_CLASS_HID_008c] = 530,
+ [BNXT_ULP_CLASS_HID_34e6] = 531,
+ [BNXT_ULP_CLASS_HID_0c02] = 532,
+ [BNXT_ULP_CLASS_HID_1c9e] = 533,
+ [BNXT_ULP_CLASS_HID_17ba] = 534,
+ [BNXT_ULP_CLASS_HID_429e] = 535,
+ [BNXT_ULP_CLASS_HID_5dba] = 536,
+ [BNXT_ULP_CLASS_HID_2a16] = 537,
+ [BNXT_ULP_CLASS_HID_2532] = 538,
+ [BNXT_ULP_CLASS_HID_2da2] = 539,
+ [BNXT_ULP_CLASS_HID_24fe] = 540,
+ [BNXT_ULP_CLASS_HID_355a] = 541,
+ [BNXT_ULP_CLASS_HID_0c76] = 542,
+ [BNXT_ULP_CLASS_HID_13e6] = 543,
+ [BNXT_ULP_CLASS_HID_7276] = 544,
+ [BNXT_ULP_CLASS_HID_42d2] = 545,
+ [BNXT_ULP_CLASS_HID_5dee] = 546,
+ [BNXT_ULP_CLASS_HID_59de] = 547,
+ [BNXT_ULP_CLASS_HID_513a] = 548,
+ [BNXT_ULP_CLASS_HID_1c12] = 549,
+ [BNXT_ULP_CLASS_HID_177e] = 550,
+ [BNXT_ULP_CLASS_HID_0e92] = 551,
+ [BNXT_ULP_CLASS_HID_09fe] = 552,
+ [BNXT_ULP_CLASS_HID_5c1a] = 553,
+ [BNXT_ULP_CLASS_HID_5746] = 554,
+ [BNXT_ULP_CLASS_HID_79da] = 555,
+ [BNXT_ULP_CLASS_HID_7106] = 556,
+ [BNXT_ULP_CLASS_HID_3c1e] = 557,
+ [BNXT_ULP_CLASS_HID_377a] = 558,
+ [BNXT_ULP_CLASS_HID_2e9e] = 559,
+ [BNXT_ULP_CLASS_HID_29fa] = 560,
+ [BNXT_ULP_CLASS_HID_14d2] = 561,
+ [BNXT_ULP_CLASS_HID_7742] = 562,
+ [BNXT_ULP_CLASS_HID_3706] = 563,
+ [BNXT_ULP_CLASS_HID_0fe2] = 564,
+ [BNXT_ULP_CLASS_HID_1f7e] = 565,
+ [BNXT_ULP_CLASS_HID_145a] = 566,
+ [BNXT_ULP_CLASS_HID_417e] = 567,
+ [BNXT_ULP_CLASS_HID_5e5a] = 568,
+ [BNXT_ULP_CLASS_HID_29f6] = 569,
+ [BNXT_ULP_CLASS_HID_26d2] = 570,
+ [BNXT_ULP_CLASS_HID_2e42] = 571,
+ [BNXT_ULP_CLASS_HID_271e] = 572,
+ [BNXT_ULP_CLASS_HID_36ba] = 573,
+ [BNXT_ULP_CLASS_HID_0f96] = 574,
+ [BNXT_ULP_CLASS_HID_1006] = 575,
+ [BNXT_ULP_CLASS_HID_7196] = 576,
+ [BNXT_ULP_CLASS_HID_4132] = 577,
+ [BNXT_ULP_CLASS_HID_5e0e] = 578,
+ [BNXT_ULP_CLASS_HID_59fe] = 579,
+ [BNXT_ULP_CLASS_HID_511a] = 580,
+ [BNXT_ULP_CLASS_HID_1c32] = 581,
+ [BNXT_ULP_CLASS_HID_175e] = 582,
+ [BNXT_ULP_CLASS_HID_0eb2] = 583,
+ [BNXT_ULP_CLASS_HID_09de] = 584,
+ [BNXT_ULP_CLASS_HID_5c3a] = 585,
+ [BNXT_ULP_CLASS_HID_5766] = 586,
+ [BNXT_ULP_CLASS_HID_79fa] = 587,
+ [BNXT_ULP_CLASS_HID_7126] = 588,
+ [BNXT_ULP_CLASS_HID_3c3e] = 589,
+ [BNXT_ULP_CLASS_HID_375a] = 590,
+ [BNXT_ULP_CLASS_HID_2ebe] = 591,
+ [BNXT_ULP_CLASS_HID_29da] = 592,
+ [BNXT_ULP_CLASS_HID_14f2] = 593,
+ [BNXT_ULP_CLASS_HID_7762] = 594,
+ [BNXT_ULP_CLASS_HID_19e8] = 595,
+ [BNXT_ULP_CLASS_HID_110c] = 596,
+ [BNXT_ULP_CLASS_HID_4d48] = 597,
+ [BNXT_ULP_CLASS_HID_446c] = 598,
+ [BNXT_ULP_CLASS_HID_0eac] = 599,
+ [BNXT_ULP_CLASS_HID_09c0] = 600,
+ [BNXT_ULP_CLASS_HID_1ad0] = 601,
+ [BNXT_ULP_CLASS_HID_15f4] = 602,
+ [BNXT_ULP_CLASS_HID_39ec] = 603,
+ [BNXT_ULP_CLASS_HID_3100] = 604,
+ [BNXT_ULP_CLASS_HID_0210] = 605,
+ [BNXT_ULP_CLASS_HID_1d34] = 606,
+ [BNXT_ULP_CLASS_HID_2ea0] = 607,
+ [BNXT_ULP_CLASS_HID_29c4] = 608,
+ [BNXT_ULP_CLASS_HID_3ad4] = 609,
+ [BNXT_ULP_CLASS_HID_35e8] = 610,
+ [BNXT_ULP_CLASS_HID_5d80] = 611,
+ [BNXT_ULP_CLASS_HID_54a4] = 612,
+ [BNXT_ULP_CLASS_HID_29b4] = 613,
+ [BNXT_ULP_CLASS_HID_20c8] = 614,
+ [BNXT_ULP_CLASS_HID_7244] = 615,
+ [BNXT_ULP_CLASS_HID_4d98] = 616,
+ [BNXT_ULP_CLASS_HID_5e68] = 617,
+ [BNXT_ULP_CLASS_HID_598c] = 618,
+ [BNXT_ULP_CLASS_HID_1248] = 619,
+ [BNXT_ULP_CLASS_HID_74d8] = 620,
+ [BNXT_ULP_CLASS_HID_49a8] = 621,
+ [BNXT_ULP_CLASS_HID_40cc] = 622,
+ [BNXT_ULP_CLASS_HID_0b0c] = 623,
+ [BNXT_ULP_CLASS_HID_0220] = 624,
+ [BNXT_ULP_CLASS_HID_1730] = 625,
+ [BNXT_ULP_CLASS_HID_7980] = 626,
+ [BNXT_ULP_CLASS_HID_1db0] = 627,
+ [BNXT_ULP_CLASS_HID_1494] = 628,
+ [BNXT_ULP_CLASS_HID_70d0] = 629,
+ [BNXT_ULP_CLASS_HID_4834] = 630,
+ [BNXT_ULP_CLASS_HID_3db4] = 631,
+ [BNXT_ULP_CLASS_HID_3498] = 632,
+ [BNXT_ULP_CLASS_HID_0988] = 633,
+ [BNXT_ULP_CLASS_HID_00ec] = 634,
+ [BNXT_ULP_CLASS_HID_3f44] = 635,
+ [BNXT_ULP_CLASS_HID_36a8] = 636,
+ [BNXT_ULP_CLASS_HID_0b58] = 637,
+ [BNXT_ULP_CLASS_HID_02bc] = 638,
+ [BNXT_ULP_CLASS_HID_5f48] = 639,
+ [BNXT_ULP_CLASS_HID_56ac] = 640,
+ [BNXT_ULP_CLASS_HID_2b5c] = 641,
+ [BNXT_ULP_CLASS_HID_2280] = 642,
+ [BNXT_ULP_CLASS_HID_4000] = 643,
+ [BNXT_ULP_CLASS_HID_5b64] = 644,
+ [BNXT_ULP_CLASS_HID_2c14] = 645,
+ [BNXT_ULP_CLASS_HID_2778] = 646,
+ [BNXT_ULP_CLASS_HID_18f8] = 647,
+ [BNXT_ULP_CLASS_HID_13dc] = 648,
+ [BNXT_ULP_CLASS_HID_4c18] = 649,
+ [BNXT_ULP_CLASS_HID_477c] = 650,
+ [BNXT_ULP_CLASS_HID_1a88] = 651,
+ [BNXT_ULP_CLASS_HID_15ec] = 652,
+ [BNXT_ULP_CLASS_HID_4e28] = 653,
+ [BNXT_ULP_CLASS_HID_490c] = 654,
+ [BNXT_ULP_CLASS_HID_3a8c] = 655,
+ [BNXT_ULP_CLASS_HID_35f0] = 656,
+ [BNXT_ULP_CLASS_HID_06e0] = 657,
+ [BNXT_ULP_CLASS_HID_01c4] = 658,
+ [BNXT_ULP_CLASS_HID_1a08] = 659,
+ [BNXT_ULP_CLASS_HID_12ec] = 660,
+ [BNXT_ULP_CLASS_HID_4ea8] = 661,
+ [BNXT_ULP_CLASS_HID_478c] = 662,
+ [BNXT_ULP_CLASS_HID_0d4c] = 663,
+ [BNXT_ULP_CLASS_HID_0a20] = 664,
+ [BNXT_ULP_CLASS_HID_1930] = 665,
+ [BNXT_ULP_CLASS_HID_1614] = 666,
+ [BNXT_ULP_CLASS_HID_3a0c] = 667,
+ [BNXT_ULP_CLASS_HID_32e0] = 668,
+ [BNXT_ULP_CLASS_HID_01f0] = 669,
+ [BNXT_ULP_CLASS_HID_1ed4] = 670,
+ [BNXT_ULP_CLASS_HID_2d40] = 671,
+ [BNXT_ULP_CLASS_HID_2a24] = 672,
+ [BNXT_ULP_CLASS_HID_3934] = 673,
+ [BNXT_ULP_CLASS_HID_3608] = 674,
+ [BNXT_ULP_CLASS_HID_5e60] = 675,
+ [BNXT_ULP_CLASS_HID_5744] = 676,
+ [BNXT_ULP_CLASS_HID_2a54] = 677,
+ [BNXT_ULP_CLASS_HID_2328] = 678,
+ [BNXT_ULP_CLASS_HID_71a4] = 679,
+ [BNXT_ULP_CLASS_HID_4e78] = 680,
+ [BNXT_ULP_CLASS_HID_5d88] = 681,
+ [BNXT_ULP_CLASS_HID_5a6c] = 682,
+ [BNXT_ULP_CLASS_HID_11a8] = 683,
+ [BNXT_ULP_CLASS_HID_7738] = 684,
+ [BNXT_ULP_CLASS_HID_4a48] = 685,
+ [BNXT_ULP_CLASS_HID_432c] = 686,
+ [BNXT_ULP_CLASS_HID_08ec] = 687,
+ [BNXT_ULP_CLASS_HID_01c0] = 688,
+ [BNXT_ULP_CLASS_HID_14d0] = 689,
+ [BNXT_ULP_CLASS_HID_7a60] = 690,
+ [BNXT_ULP_CLASS_HID_1d90] = 691,
+ [BNXT_ULP_CLASS_HID_14b4] = 692,
+ [BNXT_ULP_CLASS_HID_70f0] = 693,
+ [BNXT_ULP_CLASS_HID_4814] = 694,
+ [BNXT_ULP_CLASS_HID_3d94] = 695,
+ [BNXT_ULP_CLASS_HID_34b8] = 696,
+ [BNXT_ULP_CLASS_HID_09a8] = 697,
+ [BNXT_ULP_CLASS_HID_00cc] = 698,
+ [BNXT_ULP_CLASS_HID_3f64] = 699,
+ [BNXT_ULP_CLASS_HID_3688] = 700,
+ [BNXT_ULP_CLASS_HID_0b78] = 701,
+ [BNXT_ULP_CLASS_HID_029c] = 702,
+ [BNXT_ULP_CLASS_HID_5f68] = 703,
+ [BNXT_ULP_CLASS_HID_568c] = 704,
+ [BNXT_ULP_CLASS_HID_2b7c] = 705,
+ [BNXT_ULP_CLASS_HID_22a0] = 706,
+ [BNXT_ULP_CLASS_HID_4020] = 707,
+ [BNXT_ULP_CLASS_HID_5b44] = 708,
+ [BNXT_ULP_CLASS_HID_2c34] = 709,
+ [BNXT_ULP_CLASS_HID_2758] = 710,
+ [BNXT_ULP_CLASS_HID_18d8] = 711,
+ [BNXT_ULP_CLASS_HID_13fc] = 712,
+ [BNXT_ULP_CLASS_HID_4c38] = 713,
+ [BNXT_ULP_CLASS_HID_475c] = 714,
+ [BNXT_ULP_CLASS_HID_1aa8] = 715,
+ [BNXT_ULP_CLASS_HID_15cc] = 716,
+ [BNXT_ULP_CLASS_HID_4e08] = 717,
+ [BNXT_ULP_CLASS_HID_492c] = 718,
+ [BNXT_ULP_CLASS_HID_3aac] = 719,
+ [BNXT_ULP_CLASS_HID_35d0] = 720,
+ [BNXT_ULP_CLASS_HID_06c0] = 721,
+ [BNXT_ULP_CLASS_HID_01e4] = 722,
+ [BNXT_ULP_CLASS_HID_4d32] = 723,
+ [BNXT_ULP_CLASS_HID_54aa] = 724,
+ [BNXT_ULP_CLASS_HID_0686] = 725,
+ [BNXT_ULP_CLASS_HID_540e] = 726,
+ [BNXT_ULP_CLASS_HID_2e3c] = 727,
+ [BNXT_ULP_CLASS_HID_3a20] = 728,
+ [BNXT_ULP_CLASS_HID_46f0] = 729,
+ [BNXT_ULP_CLASS_HID_52e4] = 730,
+ [BNXT_ULP_CLASS_HID_55e4] = 731,
+ [BNXT_ULP_CLASS_HID_21f8] = 732,
+ [BNXT_ULP_CLASS_HID_75e8] = 733,
+ [BNXT_ULP_CLASS_HID_41fc] = 734,
+ [BNXT_ULP_CLASS_HID_4d12] = 735,
+ [BNXT_ULP_CLASS_HID_548a] = 736,
+ [BNXT_ULP_CLASS_HID_3356] = 737,
+ [BNXT_ULP_CLASS_HID_1ace] = 738,
+ [BNXT_ULP_CLASS_HID_1a9a] = 739,
+ [BNXT_ULP_CLASS_HID_4d46] = 740,
+ [BNXT_ULP_CLASS_HID_2812] = 741,
+ [BNXT_ULP_CLASS_HID_338a] = 742,
+ [BNXT_ULP_CLASS_HID_06e6] = 743,
+ [BNXT_ULP_CLASS_HID_546e] = 744,
+ [BNXT_ULP_CLASS_HID_46ee] = 745,
+ [BNXT_ULP_CLASS_HID_0d22] = 746,
+ [BNXT_ULP_CLASS_HID_26e2] = 747,
+ [BNXT_ULP_CLASS_HID_746a] = 748,
+ [BNXT_ULP_CLASS_HID_1fa6] = 749,
+ [BNXT_ULP_CLASS_HID_2d2e] = 750,
+ [BNXT_ULP_CLASS_HID_4ef2] = 751,
+ [BNXT_ULP_CLASS_HID_576a] = 752,
+ [BNXT_ULP_CLASS_HID_30b6] = 753,
+ [BNXT_ULP_CLASS_HID_192e] = 754,
+ [BNXT_ULP_CLASS_HID_197a] = 755,
+ [BNXT_ULP_CLASS_HID_4ea6] = 756,
+ [BNXT_ULP_CLASS_HID_2bf2] = 757,
+ [BNXT_ULP_CLASS_HID_306a] = 758,
+ [BNXT_ULP_CLASS_HID_06c6] = 759,
+ [BNXT_ULP_CLASS_HID_544e] = 760,
+ [BNXT_ULP_CLASS_HID_46ce] = 761,
+ [BNXT_ULP_CLASS_HID_0d02] = 762,
+ [BNXT_ULP_CLASS_HID_26c2] = 763,
+ [BNXT_ULP_CLASS_HID_744a] = 764,
+ [BNXT_ULP_CLASS_HID_1f86] = 765,
+ [BNXT_ULP_CLASS_HID_2d0e] = 766,
+ [BNXT_ULP_CLASS_HID_2e1c] = 767,
+ [BNXT_ULP_CLASS_HID_3a00] = 768,
+ [BNXT_ULP_CLASS_HID_46d0] = 769,
+ [BNXT_ULP_CLASS_HID_52c4] = 770,
+ [BNXT_ULP_CLASS_HID_4e10] = 771,
+ [BNXT_ULP_CLASS_HID_5a04] = 772,
+ [BNXT_ULP_CLASS_HID_1f98] = 773,
+ [BNXT_ULP_CLASS_HID_72f8] = 774,
+ [BNXT_ULP_CLASS_HID_0a78] = 775,
+ [BNXT_ULP_CLASS_HID_166c] = 776,
+ [BNXT_ULP_CLASS_HID_233c] = 777,
+ [BNXT_ULP_CLASS_HID_0f20] = 778,
+ [BNXT_ULP_CLASS_HID_2a7c] = 779,
+ [BNXT_ULP_CLASS_HID_3660] = 780,
+ [BNXT_ULP_CLASS_HID_4330] = 781,
+ [BNXT_ULP_CLASS_HID_2f24] = 782,
+ [BNXT_ULP_CLASS_HID_5584] = 783,
+ [BNXT_ULP_CLASS_HID_2198] = 784,
+ [BNXT_ULP_CLASS_HID_7588] = 785,
+ [BNXT_ULP_CLASS_HID_419c] = 786,
+ [BNXT_ULP_CLASS_HID_7758] = 787,
+ [BNXT_ULP_CLASS_HID_43ac] = 788,
+ [BNXT_ULP_CLASS_HID_0c10] = 789,
+ [BNXT_ULP_CLASS_HID_1864] = 790,
+ [BNXT_ULP_CLASS_HID_30c8] = 791,
+ [BNXT_ULP_CLASS_HID_1cdc] = 792,
+ [BNXT_ULP_CLASS_HID_50cc] = 793,
+ [BNXT_ULP_CLASS_HID_3d20] = 794,
+ [BNXT_ULP_CLASS_HID_529c] = 795,
+ [BNXT_ULP_CLASS_HID_3ef0] = 796,
+ [BNXT_ULP_CLASS_HID_72e0] = 797,
+ [BNXT_ULP_CLASS_HID_5ef4] = 798,
+ [BNXT_ULP_CLASS_HID_2dfc] = 799,
+ [BNXT_ULP_CLASS_HID_39e0] = 800,
+ [BNXT_ULP_CLASS_HID_4530] = 801,
+ [BNXT_ULP_CLASS_HID_5124] = 802,
+ [BNXT_ULP_CLASS_HID_4df0] = 803,
+ [BNXT_ULP_CLASS_HID_59e4] = 804,
+ [BNXT_ULP_CLASS_HID_1c78] = 805,
+ [BNXT_ULP_CLASS_HID_7118] = 806,
+ [BNXT_ULP_CLASS_HID_0998] = 807,
+ [BNXT_ULP_CLASS_HID_158c] = 808,
+ [BNXT_ULP_CLASS_HID_20dc] = 809,
+ [BNXT_ULP_CLASS_HID_0cc0] = 810,
+ [BNXT_ULP_CLASS_HID_299c] = 811,
+ [BNXT_ULP_CLASS_HID_3580] = 812,
+ [BNXT_ULP_CLASS_HID_40d0] = 813,
+ [BNXT_ULP_CLASS_HID_2cc4] = 814,
+ [BNXT_ULP_CLASS_HID_55a4] = 815,
+ [BNXT_ULP_CLASS_HID_21b8] = 816,
+ [BNXT_ULP_CLASS_HID_75a8] = 817,
+ [BNXT_ULP_CLASS_HID_41bc] = 818,
+ [BNXT_ULP_CLASS_HID_7778] = 819,
+ [BNXT_ULP_CLASS_HID_438c] = 820,
+ [BNXT_ULP_CLASS_HID_0c30] = 821,
+ [BNXT_ULP_CLASS_HID_1844] = 822,
+ [BNXT_ULP_CLASS_HID_30e8] = 823,
+ [BNXT_ULP_CLASS_HID_1cfc] = 824,
+ [BNXT_ULP_CLASS_HID_50ec] = 825,
+ [BNXT_ULP_CLASS_HID_3d00] = 826,
+ [BNXT_ULP_CLASS_HID_52bc] = 827,
+ [BNXT_ULP_CLASS_HID_3ed0] = 828,
+ [BNXT_ULP_CLASS_HID_72c0] = 829,
+ [BNXT_ULP_CLASS_HID_5ed4] = 830,
+ [BNXT_ULP_CLASS_HID_3866] = 831,
+ [BNXT_ULP_CLASS_HID_381e] = 832,
+ [BNXT_ULP_CLASS_HID_3860] = 833,
+ [BNXT_ULP_CLASS_HID_0454] = 834,
+ [BNXT_ULP_CLASS_HID_3818] = 835,
+ [BNXT_ULP_CLASS_HID_042c] = 836,
+ [BNXT_ULP_CLASS_HID_3846] = 837,
+ [BNXT_ULP_CLASS_HID_387e] = 838,
+ [BNXT_ULP_CLASS_HID_3ba6] = 839,
+ [BNXT_ULP_CLASS_HID_385e] = 840,
+ [BNXT_ULP_CLASS_HID_3840] = 841,
+ [BNXT_ULP_CLASS_HID_0474] = 842,
+ [BNXT_ULP_CLASS_HID_3878] = 843,
+ [BNXT_ULP_CLASS_HID_044c] = 844,
+ [BNXT_ULP_CLASS_HID_3ba0] = 845,
+ [BNXT_ULP_CLASS_HID_0794] = 846,
+ [BNXT_ULP_CLASS_HID_3858] = 847,
+ [BNXT_ULP_CLASS_HID_046c] = 848
};
/* Array for the proto matcher list */
@@ -6964,8 +7126,3839 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_12_BITMASK_O_UDP_DST_PORT }
},
[345] = {
- .class_hid = BNXT_ULP_CLASS_HID_34c6,
+ .class_hid = BNXT_ULP_CLASS_HID_3612,
+ .class_tid = 2,
+ .hdr_sig_id = 0,
+ .flow_sig_id = 81920,
+ .flow_pattern_id = 0,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_F1 |
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT }
+ },
+ [346] = {
+ .class_hid = BNXT_ULP_CLASS_HID_66da,
+ .class_tid = 2,
+ .hdr_sig_id = 0,
+ .flow_sig_id = 81928,
+ .flow_pattern_id = 0,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_F1 |
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT }
+ },
+ [347] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6165,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 1313792,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC }
+ },
+ [348] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2aa1,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 1321984,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC }
+ },
+ [349] = {
+ .class_hid = BNXT_ULP_CLASS_HID_09cd,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 3410944,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }
+ },
+ [350] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3845,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 3419136,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }
+ },
+ [351] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11e9,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 2148797440,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [352] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4361,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 2148805632,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [353] = {
+ .class_hid = BNXT_ULP_CLASS_HID_218d,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 2150894592,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [354] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5105,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 2150902784,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [355] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0c89,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 4296281088,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [356] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3e81,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 4296289280,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [357] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1dad,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 4298378240,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [358] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4ca5,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 4298386432,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [359] = {
+ .class_hid = BNXT_ULP_CLASS_HID_25c9,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 6443764736,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [360] = {
+ .class_hid = BNXT_ULP_CLASS_HID_57c1,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 6443772928,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [361] = {
+ .class_hid = BNXT_ULP_CLASS_HID_33ed,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 6445861888,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [362] = {
+ .class_hid = BNXT_ULP_CLASS_HID_65e5,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 6445870080,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [363] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6dd9,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 1313792,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }
+ },
+ [364] = {
+ .class_hid = BNXT_ULP_CLASS_HID_261d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 1321984,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }
+ },
+ [365] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0571,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 3410944,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
+ },
+ [366] = {
+ .class_hid = BNXT_ULP_CLASS_HID_34f9,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 3419136,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
+ },
+ [367] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1d55,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 2148797440,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [368] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4fdd,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 2148805632,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [369] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2d31,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 2150894592,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [370] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5db9,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 2150902784,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [371] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0035,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 4296281088,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [372] = {
+ .class_hid = BNXT_ULP_CLASS_HID_323d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 4296289280,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [373] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1111,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 4298378240,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [374] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4019,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 4298386432,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [375] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2975,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 6443764736,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [376] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5b7d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 6443772928,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [377] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3f51,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 6445861888,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [378] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6959,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 6445870080,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [379] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0e85,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 8591248384,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [380] = {
+ .class_hid = BNXT_ULP_CLASS_HID_380d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 8591256576,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [381] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1f21,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 8593345536,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [382] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4ea9,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 8593353728,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [383] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1705,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 10738732032,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [384] = {
+ .class_hid = BNXT_ULP_CLASS_HID_418d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 10738740224,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [385] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2721,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 10740829184,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [386] = {
+ .class_hid = BNXT_ULP_CLASS_HID_57a9,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 10740837376,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [387] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1a25,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 12886215680,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [388] = {
+ .class_hid = BNXT_ULP_CLASS_HID_342d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 12886223872,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [389] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2b01,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 12888312832,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [390] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5a09,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 12888321024,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [391] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2325,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 15033699328,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [392] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5d2d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 15033707520,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [393] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3101,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 15035796480,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [394] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6309,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 15035804672,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [395] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0bad,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 17181182976,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [396] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2535,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 17181191168,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [397] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1869,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 17183280128,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [398] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4bf1,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 17183288320,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [399] = {
+ .class_hid = BNXT_ULP_CLASS_HID_136d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 19328666624,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [400] = {
+ .class_hid = BNXT_ULP_CLASS_HID_43f5,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 19328674816,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [401] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2129,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 19330763776,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [402] = {
+ .class_hid = BNXT_ULP_CLASS_HID_53b1,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 19330771968,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [403] = {
+ .class_hid = BNXT_ULP_CLASS_HID_072d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 21476150272,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [404] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3135,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 21476158464,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [405] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1429,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 21478247424,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [406] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4731,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 21478255616,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [407] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2f6d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 23623633920,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [408] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5f75,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 23623642112,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [409] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3d69,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 23625731072,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [410] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6f71,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 23625739264,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [411] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0dbd,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 25771117568,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [412] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3f25,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 25771125760,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [413] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1239,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 25773214720,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [414] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4da1,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 25773222912,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [415] = {
+ .class_hid = BNXT_ULP_CLASS_HID_153d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 27918601216,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [416] = {
+ .class_hid = BNXT_ULP_CLASS_HID_45a5,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 27918609408,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [417] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3bb9,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 27920698368,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [418] = {
+ .class_hid = BNXT_ULP_CLASS_HID_55a1,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 27920706560,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [419] = {
+ .class_hid = BNXT_ULP_CLASS_HID_193d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 30066084864,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [420] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4b25,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 30066093056,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [421] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2e39,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 30068182016,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [422] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5921,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 30068190208,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [423] = {
+ .class_hid = BNXT_ULP_CLASS_HID_213d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 32213568512,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [424] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5125,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 32213576704,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [425] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3739,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 32215665664,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [426] = {
+ .class_hid = BNXT_ULP_CLASS_HID_093d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 32215673856,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [427] = {
+ .class_hid = BNXT_ULP_CLASS_HID_684d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1313792,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
+ },
+ [428] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2389,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1321984,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
+ },
+ [429] = {
+ .class_hid = BNXT_ULP_CLASS_HID_00e5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3410944,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
+ },
+ [430] = {
+ .class_hid = BNXT_ULP_CLASS_HID_316d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3419136,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
+ },
+ [431] = {
+ .class_hid = BNXT_ULP_CLASS_HID_18c1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2148797440,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [432] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4a49,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2148805632,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [433] = {
+ .class_hid = BNXT_ULP_CLASS_HID_28a5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2150894592,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [434] = {
+ .class_hid = BNXT_ULP_CLASS_HID_582d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2150902784,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [435] = {
+ .class_hid = BNXT_ULP_CLASS_HID_05a1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4296281088,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [436] = {
+ .class_hid = BNXT_ULP_CLASS_HID_37a9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4296289280,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [437] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1485,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4298378240,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [438] = {
+ .class_hid = BNXT_ULP_CLASS_HID_458d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4298386432,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [439] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2ce1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6443764736,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [440] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5ee9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6443772928,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [441] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3ac5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6445861888,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [442] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6ccd,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6445870080,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [443] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0b11,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8591248384,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [444] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3d99,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8591256576,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [445] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1ab5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8593345536,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [446] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4b3d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8593353728,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [447] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1291,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 10738732032,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [448] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4419,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 10738740224,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [449] = {
+ .class_hid = BNXT_ULP_CLASS_HID_22b5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 10740829184,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [450] = {
+ .class_hid = BNXT_ULP_CLASS_HID_523d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 10740837376,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [451] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1fb1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 12886215680,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [452] = {
+ .class_hid = BNXT_ULP_CLASS_HID_31b9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 12886223872,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [453] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2e95,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 12888312832,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [454] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5f9d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 12888321024,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [455] = {
+ .class_hid = BNXT_ULP_CLASS_HID_26b1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 15033699328,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [456] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58b9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 15033707520,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [457] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3495,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 15035796480,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [458] = {
+ .class_hid = BNXT_ULP_CLASS_HID_669d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 15035804672,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [459] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0e39,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 17181182976,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [460] = {
+ .class_hid = BNXT_ULP_CLASS_HID_20a1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 17181191168,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [461] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1dfd,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 17183280128,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [462] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4e65,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 17183288320,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [463] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16f9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 19328666624,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [464] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4661,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 19328674816,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [465] = {
+ .class_hid = BNXT_ULP_CLASS_HID_24bd,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 19330763776,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [466] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5625,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 19330771968,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [467] = {
+ .class_hid = BNXT_ULP_CLASS_HID_02b9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 21476150272,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [468] = {
+ .class_hid = BNXT_ULP_CLASS_HID_34a1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 21476158464,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [469] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11bd,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 21478247424,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [470] = {
+ .class_hid = BNXT_ULP_CLASS_HID_42a5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 21478255616,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [471] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2af9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 23623633920,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [472] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5ae1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 23623642112,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [473] = {
+ .class_hid = BNXT_ULP_CLASS_HID_38fd,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 23625731072,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [474] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6ae5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 23625739264,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [475] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0829,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 25771117568,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [476] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3ab1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 25771125760,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [477] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17ad,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 25773214720,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [478] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4835,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 25773222912,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [479] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10a9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 27918601216,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [480] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4031,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 27918609408,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [481] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3e2d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 27920698368,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [482] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5035,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 27920706560,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [483] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1ca9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 30066084864,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [484] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4eb1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 30066093056,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [485] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2bad,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 30068182016,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [486] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5cb5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 30068190208,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [487] = {
+ .class_hid = BNXT_ULP_CLASS_HID_24a9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 32213568512,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [488] = {
+ .class_hid = BNXT_ULP_CLASS_HID_54b1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 32213576704,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [489] = {
+ .class_hid = BNXT_ULP_CLASS_HID_32ad,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 32215665664,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [490] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0ca9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 32215673856,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [491] = {
+ .class_hid = BNXT_ULP_CLASS_HID_7f35,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1313792,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ },
+ [492] = {
+ .class_hid = BNXT_ULP_CLASS_HID_34f1,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1321984,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ },
+ [493] = {
+ .class_hid = BNXT_ULP_CLASS_HID_179d,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 3410944,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ },
+ [494] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2615,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 3419136,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ },
+ [495] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0fb9,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2148797440,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [496] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5d31,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2148805632,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [497] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3fdd,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2150894592,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [498] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4f55,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2150902784,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [499] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12d9,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4296281088,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [500] = {
+ .class_hid = BNXT_ULP_CLASS_HID_20d1,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4296289280,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [501] = {
+ .class_hid = BNXT_ULP_CLASS_HID_03fd,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4298378240,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [502] = {
+ .class_hid = BNXT_ULP_CLASS_HID_52f5,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4298386432,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [503] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3b99,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6443764736,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [504] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4991,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6443772928,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [505] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2dbd,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6445861888,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [506] = {
+ .class_hid = BNXT_ULP_CLASS_HID_7bb5,
.class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6445870080,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [507] = {
+ .class_hid = BNXT_ULP_CLASS_HID_34c6,
+ .class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 4096,
.flow_pattern_id = 0,
@@ -6975,12 +10968,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [346] = {
+ [508] = {
.class_hid = BNXT_ULP_CLASS_HID_0c22,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 4100,
.flow_pattern_id = 0,
@@ -6990,13 +10983,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [347] = {
+ [509] = {
.class_hid = BNXT_ULP_CLASS_HID_1cbe,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 6144,
.flow_pattern_id = 0,
@@ -7006,13 +10999,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [348] = {
+ [510] = {
.class_hid = BNXT_ULP_CLASS_HID_179a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 6148,
.flow_pattern_id = 0,
@@ -7022,14 +11015,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [349] = {
+ [511] = {
.class_hid = BNXT_ULP_CLASS_HID_59be,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 16384,
.flow_pattern_id = 0,
@@ -7039,12 +11032,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [350] = {
+ [512] = {
.class_hid = BNXT_ULP_CLASS_HID_515a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 16388,
.flow_pattern_id = 0,
@@ -7054,13 +11047,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [351] = {
+ [513] = {
.class_hid = BNXT_ULP_CLASS_HID_1c72,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 24576,
.flow_pattern_id = 0,
@@ -7070,13 +11063,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [352] = {
+ [514] = {
.class_hid = BNXT_ULP_CLASS_HID_171e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 24580,
.flow_pattern_id = 0,
@@ -7086,14 +11079,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [353] = {
+ [515] = {
.class_hid = BNXT_ULP_CLASS_HID_19c8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32768,
.flow_pattern_id = 0,
@@ -7104,12 +11097,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [354] = {
+ [516] = {
.class_hid = BNXT_ULP_CLASS_HID_112c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32772,
.flow_pattern_id = 0,
@@ -7120,13 +11113,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [355] = {
+ [517] = {
.class_hid = BNXT_ULP_CLASS_HID_4d68,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32832,
.flow_pattern_id = 0,
@@ -7137,13 +11130,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [356] = {
+ [518] = {
.class_hid = BNXT_ULP_CLASS_HID_444c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32836,
.flow_pattern_id = 0,
@@ -7154,14 +11147,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [357] = {
+ [519] = {
.class_hid = BNXT_ULP_CLASS_HID_0e8c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49152,
.flow_pattern_id = 0,
@@ -7172,13 +11165,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [358] = {
+ [520] = {
.class_hid = BNXT_ULP_CLASS_HID_09e0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49156,
.flow_pattern_id = 0,
@@ -7189,14 +11182,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [359] = {
+ [521] = {
.class_hid = BNXT_ULP_CLASS_HID_1af0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49216,
.flow_pattern_id = 0,
@@ -7207,14 +11200,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [360] = {
+ [522] = {
.class_hid = BNXT_ULP_CLASS_HID_15d4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49220,
.flow_pattern_id = 0,
@@ -7225,15 +11218,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [361] = {
+ [523] = {
.class_hid = BNXT_ULP_CLASS_HID_1dd0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131072,
.flow_pattern_id = 0,
@@ -7244,12 +11237,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [362] = {
+ [524] = {
.class_hid = BNXT_ULP_CLASS_HID_14f4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131076,
.flow_pattern_id = 0,
@@ -7260,13 +11253,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [363] = {
+ [525] = {
.class_hid = BNXT_ULP_CLASS_HID_70b0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131136,
.flow_pattern_id = 0,
@@ -7277,13 +11270,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [364] = {
+ [526] = {
.class_hid = BNXT_ULP_CLASS_HID_4854,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131140,
.flow_pattern_id = 0,
@@ -7294,14 +11287,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [365] = {
+ [527] = {
.class_hid = BNXT_ULP_CLASS_HID_3dd4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196608,
.flow_pattern_id = 0,
@@ -7312,13 +11305,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [366] = {
+ [528] = {
.class_hid = BNXT_ULP_CLASS_HID_34f8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196612,
.flow_pattern_id = 0,
@@ -7329,14 +11322,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [367] = {
+ [529] = {
.class_hid = BNXT_ULP_CLASS_HID_09e8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196672,
.flow_pattern_id = 0,
@@ -7347,14 +11340,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [368] = {
+ [530] = {
.class_hid = BNXT_ULP_CLASS_HID_008c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196676,
.flow_pattern_id = 0,
@@ -7365,15 +11358,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [369] = {
+ [531] = {
.class_hid = BNXT_ULP_CLASS_HID_34e6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 4096,
.flow_pattern_id = 0,
@@ -7384,12 +11377,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [370] = {
+ [532] = {
.class_hid = BNXT_ULP_CLASS_HID_0c02,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 4100,
.flow_pattern_id = 0,
@@ -7400,13 +11393,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [371] = {
+ [533] = {
.class_hid = BNXT_ULP_CLASS_HID_1c9e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 6144,
.flow_pattern_id = 0,
@@ -7417,13 +11410,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [372] = {
+ [534] = {
.class_hid = BNXT_ULP_CLASS_HID_17ba,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 6148,
.flow_pattern_id = 0,
@@ -7434,14 +11427,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [373] = {
+ [535] = {
.class_hid = BNXT_ULP_CLASS_HID_429e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 12288,
.flow_pattern_id = 0,
@@ -7452,13 +11445,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [374] = {
+ [536] = {
.class_hid = BNXT_ULP_CLASS_HID_5dba,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 12292,
.flow_pattern_id = 0,
@@ -7469,14 +11462,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [375] = {
+ [537] = {
.class_hid = BNXT_ULP_CLASS_HID_2a16,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 14336,
.flow_pattern_id = 0,
@@ -7487,14 +11480,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [376] = {
+ [538] = {
.class_hid = BNXT_ULP_CLASS_HID_2532,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 14340,
.flow_pattern_id = 0,
@@ -7505,15 +11498,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [377] = {
+ [539] = {
.class_hid = BNXT_ULP_CLASS_HID_2da2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 20480,
.flow_pattern_id = 0,
@@ -7524,13 +11517,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [378] = {
+ [540] = {
.class_hid = BNXT_ULP_CLASS_HID_24fe,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 20484,
.flow_pattern_id = 0,
@@ -7541,14 +11534,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [379] = {
+ [541] = {
.class_hid = BNXT_ULP_CLASS_HID_355a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 22528,
.flow_pattern_id = 0,
@@ -7559,14 +11552,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [380] = {
+ [542] = {
.class_hid = BNXT_ULP_CLASS_HID_0c76,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 22532,
.flow_pattern_id = 0,
@@ -7577,15 +11570,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [381] = {
+ [543] = {
.class_hid = BNXT_ULP_CLASS_HID_13e6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 28672,
.flow_pattern_id = 0,
@@ -7596,14 +11589,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [382] = {
+ [544] = {
.class_hid = BNXT_ULP_CLASS_HID_7276,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 28676,
.flow_pattern_id = 0,
@@ -7614,15 +11607,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [383] = {
+ [545] = {
.class_hid = BNXT_ULP_CLASS_HID_42d2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 30720,
.flow_pattern_id = 0,
@@ -7633,15 +11626,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [384] = {
+ [546] = {
.class_hid = BNXT_ULP_CLASS_HID_5dee,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 30724,
.flow_pattern_id = 0,
@@ -7652,16 +11645,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [385] = {
+ [547] = {
.class_hid = BNXT_ULP_CLASS_HID_59de,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 16384,
.flow_pattern_id = 0,
@@ -7672,12 +11665,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [386] = {
+ [548] = {
.class_hid = BNXT_ULP_CLASS_HID_513a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 16388,
.flow_pattern_id = 0,
@@ -7688,13 +11681,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [387] = {
+ [549] = {
.class_hid = BNXT_ULP_CLASS_HID_1c12,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 24576,
.flow_pattern_id = 0,
@@ -7705,13 +11698,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [388] = {
+ [550] = {
.class_hid = BNXT_ULP_CLASS_HID_177e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 24580,
.flow_pattern_id = 0,
@@ -7722,14 +11715,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [389] = {
+ [551] = {
.class_hid = BNXT_ULP_CLASS_HID_0e92,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 49152,
.flow_pattern_id = 0,
@@ -7740,13 +11733,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [390] = {
+ [552] = {
.class_hid = BNXT_ULP_CLASS_HID_09fe,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 49156,
.flow_pattern_id = 0,
@@ -7757,14 +11750,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [391] = {
+ [553] = {
.class_hid = BNXT_ULP_CLASS_HID_5c1a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 57344,
.flow_pattern_id = 0,
@@ -7775,14 +11768,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [392] = {
+ [554] = {
.class_hid = BNXT_ULP_CLASS_HID_5746,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 57348,
.flow_pattern_id = 0,
@@ -7793,15 +11786,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [393] = {
+ [555] = {
.class_hid = BNXT_ULP_CLASS_HID_79da,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 81920,
.flow_pattern_id = 0,
@@ -7812,13 +11805,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [394] = {
+ [556] = {
.class_hid = BNXT_ULP_CLASS_HID_7106,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 81924,
.flow_pattern_id = 0,
@@ -7829,14 +11822,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [395] = {
+ [557] = {
.class_hid = BNXT_ULP_CLASS_HID_3c1e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 90112,
.flow_pattern_id = 0,
@@ -7847,14 +11840,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [396] = {
+ [558] = {
.class_hid = BNXT_ULP_CLASS_HID_377a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 90116,
.flow_pattern_id = 0,
@@ -7865,15 +11858,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [397] = {
+ [559] = {
.class_hid = BNXT_ULP_CLASS_HID_2e9e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 114688,
.flow_pattern_id = 0,
@@ -7884,14 +11877,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [398] = {
+ [560] = {
.class_hid = BNXT_ULP_CLASS_HID_29fa,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 114692,
.flow_pattern_id = 0,
@@ -7902,15 +11895,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [399] = {
+ [561] = {
.class_hid = BNXT_ULP_CLASS_HID_14d2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 122880,
.flow_pattern_id = 0,
@@ -7921,15 +11914,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [400] = {
+ [562] = {
.class_hid = BNXT_ULP_CLASS_HID_7742,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 122884,
.flow_pattern_id = 0,
@@ -7940,16 +11933,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [401] = {
+ [563] = {
.class_hid = BNXT_ULP_CLASS_HID_3706,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 4096,
.flow_pattern_id = 0,
@@ -7960,12 +11953,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [402] = {
+ [564] = {
.class_hid = BNXT_ULP_CLASS_HID_0fe2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 4100,
.flow_pattern_id = 0,
@@ -7976,13 +11969,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [403] = {
+ [565] = {
.class_hid = BNXT_ULP_CLASS_HID_1f7e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 6144,
.flow_pattern_id = 0,
@@ -7993,13 +11986,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [404] = {
+ [566] = {
.class_hid = BNXT_ULP_CLASS_HID_145a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 6148,
.flow_pattern_id = 0,
@@ -8010,14 +12003,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [405] = {
+ [567] = {
.class_hid = BNXT_ULP_CLASS_HID_417e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 12288,
.flow_pattern_id = 0,
@@ -8028,13 +12021,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [406] = {
+ [568] = {
.class_hid = BNXT_ULP_CLASS_HID_5e5a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 12292,
.flow_pattern_id = 0,
@@ -8045,14 +12038,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [407] = {
+ [569] = {
.class_hid = BNXT_ULP_CLASS_HID_29f6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 14336,
.flow_pattern_id = 0,
@@ -8063,14 +12056,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [408] = {
+ [570] = {
.class_hid = BNXT_ULP_CLASS_HID_26d2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 14340,
.flow_pattern_id = 0,
@@ -8081,15 +12074,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [409] = {
+ [571] = {
.class_hid = BNXT_ULP_CLASS_HID_2e42,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 20480,
.flow_pattern_id = 0,
@@ -8100,13 +12093,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [410] = {
+ [572] = {
.class_hid = BNXT_ULP_CLASS_HID_271e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 20484,
.flow_pattern_id = 0,
@@ -8117,14 +12110,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [411] = {
+ [573] = {
.class_hid = BNXT_ULP_CLASS_HID_36ba,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 22528,
.flow_pattern_id = 0,
@@ -8135,14 +12128,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [412] = {
+ [574] = {
.class_hid = BNXT_ULP_CLASS_HID_0f96,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 22532,
.flow_pattern_id = 0,
@@ -8153,15 +12146,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [413] = {
+ [575] = {
.class_hid = BNXT_ULP_CLASS_HID_1006,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 28672,
.flow_pattern_id = 0,
@@ -8172,14 +12165,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [414] = {
+ [576] = {
.class_hid = BNXT_ULP_CLASS_HID_7196,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 28676,
.flow_pattern_id = 0,
@@ -8190,15 +12183,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [415] = {
+ [577] = {
.class_hid = BNXT_ULP_CLASS_HID_4132,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 30720,
.flow_pattern_id = 0,
@@ -8209,15 +12202,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [416] = {
+ [578] = {
.class_hid = BNXT_ULP_CLASS_HID_5e0e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 30724,
.flow_pattern_id = 0,
@@ -8228,16 +12221,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [417] = {
+ [579] = {
.class_hid = BNXT_ULP_CLASS_HID_59fe,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 16384,
.flow_pattern_id = 0,
@@ -8248,12 +12241,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [418] = {
+ [580] = {
.class_hid = BNXT_ULP_CLASS_HID_511a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 16388,
.flow_pattern_id = 0,
@@ -8264,13 +12257,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [419] = {
+ [581] = {
.class_hid = BNXT_ULP_CLASS_HID_1c32,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 24576,
.flow_pattern_id = 0,
@@ -8281,13 +12274,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [420] = {
+ [582] = {
.class_hid = BNXT_ULP_CLASS_HID_175e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 24580,
.flow_pattern_id = 0,
@@ -8298,14 +12291,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [421] = {
+ [583] = {
.class_hid = BNXT_ULP_CLASS_HID_0eb2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 49152,
.flow_pattern_id = 0,
@@ -8316,13 +12309,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [422] = {
+ [584] = {
.class_hid = BNXT_ULP_CLASS_HID_09de,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 49156,
.flow_pattern_id = 0,
@@ -8333,14 +12326,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [423] = {
+ [585] = {
.class_hid = BNXT_ULP_CLASS_HID_5c3a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 57344,
.flow_pattern_id = 0,
@@ -8351,14 +12344,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [424] = {
+ [586] = {
.class_hid = BNXT_ULP_CLASS_HID_5766,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 57348,
.flow_pattern_id = 0,
@@ -8369,15 +12362,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [425] = {
+ [587] = {
.class_hid = BNXT_ULP_CLASS_HID_79fa,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 81920,
.flow_pattern_id = 0,
@@ -8388,13 +12381,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [426] = {
+ [588] = {
.class_hid = BNXT_ULP_CLASS_HID_7126,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 81924,
.flow_pattern_id = 0,
@@ -8405,14 +12398,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [427] = {
+ [589] = {
.class_hid = BNXT_ULP_CLASS_HID_3c3e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 90112,
.flow_pattern_id = 0,
@@ -8423,14 +12416,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [428] = {
+ [590] = {
.class_hid = BNXT_ULP_CLASS_HID_375a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 90116,
.flow_pattern_id = 0,
@@ -8441,15 +12434,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [429] = {
+ [591] = {
.class_hid = BNXT_ULP_CLASS_HID_2ebe,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 114688,
.flow_pattern_id = 0,
@@ -8460,14 +12453,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [430] = {
+ [592] = {
.class_hid = BNXT_ULP_CLASS_HID_29da,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 114692,
.flow_pattern_id = 0,
@@ -8478,15 +12471,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [431] = {
+ [593] = {
.class_hid = BNXT_ULP_CLASS_HID_14f2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 122880,
.flow_pattern_id = 0,
@@ -8497,15 +12490,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [432] = {
+ [594] = {
.class_hid = BNXT_ULP_CLASS_HID_7762,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 122884,
.flow_pattern_id = 0,
@@ -8516,16 +12509,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [433] = {
+ [595] = {
.class_hid = BNXT_ULP_CLASS_HID_19e8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32768,
.flow_pattern_id = 0,
@@ -8537,12 +12530,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [434] = {
+ [596] = {
.class_hid = BNXT_ULP_CLASS_HID_110c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32772,
.flow_pattern_id = 0,
@@ -8554,13 +12547,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [435] = {
+ [597] = {
.class_hid = BNXT_ULP_CLASS_HID_4d48,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32832,
.flow_pattern_id = 0,
@@ -8572,13 +12565,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [436] = {
+ [598] = {
.class_hid = BNXT_ULP_CLASS_HID_446c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32836,
.flow_pattern_id = 0,
@@ -8590,14 +12583,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [437] = {
+ [599] = {
.class_hid = BNXT_ULP_CLASS_HID_0eac,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49152,
.flow_pattern_id = 0,
@@ -8609,13 +12602,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [438] = {
+ [600] = {
.class_hid = BNXT_ULP_CLASS_HID_09c0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49156,
.flow_pattern_id = 0,
@@ -8627,14 +12620,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [439] = {
+ [601] = {
.class_hid = BNXT_ULP_CLASS_HID_1ad0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49216,
.flow_pattern_id = 0,
@@ -8646,14 +12639,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [440] = {
+ [602] = {
.class_hid = BNXT_ULP_CLASS_HID_15f4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49220,
.flow_pattern_id = 0,
@@ -8665,15 +12658,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [441] = {
+ [603] = {
.class_hid = BNXT_ULP_CLASS_HID_39ec,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98304,
.flow_pattern_id = 0,
@@ -8685,13 +12678,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [442] = {
+ [604] = {
.class_hid = BNXT_ULP_CLASS_HID_3100,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98308,
.flow_pattern_id = 0,
@@ -8703,14 +12696,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [443] = {
+ [605] = {
.class_hid = BNXT_ULP_CLASS_HID_0210,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98368,
.flow_pattern_id = 0,
@@ -8722,14 +12715,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [444] = {
+ [606] = {
.class_hid = BNXT_ULP_CLASS_HID_1d34,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98372,
.flow_pattern_id = 0,
@@ -8741,15 +12734,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [445] = {
+ [607] = {
.class_hid = BNXT_ULP_CLASS_HID_2ea0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114688,
.flow_pattern_id = 0,
@@ -8761,14 +12754,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [446] = {
+ [608] = {
.class_hid = BNXT_ULP_CLASS_HID_29c4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114692,
.flow_pattern_id = 0,
@@ -8780,15 +12773,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [447] = {
+ [609] = {
.class_hid = BNXT_ULP_CLASS_HID_3ad4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114752,
.flow_pattern_id = 0,
@@ -8800,15 +12793,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [448] = {
+ [610] = {
.class_hid = BNXT_ULP_CLASS_HID_35e8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114756,
.flow_pattern_id = 0,
@@ -8820,16 +12813,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [449] = {
+ [611] = {
.class_hid = BNXT_ULP_CLASS_HID_5d80,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163840,
.flow_pattern_id = 0,
@@ -8841,13 +12834,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [450] = {
+ [612] = {
.class_hid = BNXT_ULP_CLASS_HID_54a4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163844,
.flow_pattern_id = 0,
@@ -8859,14 +12852,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [451] = {
+ [613] = {
.class_hid = BNXT_ULP_CLASS_HID_29b4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163904,
.flow_pattern_id = 0,
@@ -8878,14 +12871,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [452] = {
+ [614] = {
.class_hid = BNXT_ULP_CLASS_HID_20c8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163908,
.flow_pattern_id = 0,
@@ -8897,15 +12890,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [453] = {
+ [615] = {
.class_hid = BNXT_ULP_CLASS_HID_7244,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180224,
.flow_pattern_id = 0,
@@ -8917,14 +12910,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [454] = {
+ [616] = {
.class_hid = BNXT_ULP_CLASS_HID_4d98,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180228,
.flow_pattern_id = 0,
@@ -8936,15 +12929,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [455] = {
+ [617] = {
.class_hid = BNXT_ULP_CLASS_HID_5e68,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180288,
.flow_pattern_id = 0,
@@ -8956,15 +12949,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [456] = {
+ [618] = {
.class_hid = BNXT_ULP_CLASS_HID_598c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180292,
.flow_pattern_id = 0,
@@ -8976,16 +12969,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [457] = {
+ [619] = {
.class_hid = BNXT_ULP_CLASS_HID_1248,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229376,
.flow_pattern_id = 0,
@@ -8997,14 +12990,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [458] = {
+ [620] = {
.class_hid = BNXT_ULP_CLASS_HID_74d8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229380,
.flow_pattern_id = 0,
@@ -9016,15 +13009,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [459] = {
+ [621] = {
.class_hid = BNXT_ULP_CLASS_HID_49a8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229440,
.flow_pattern_id = 0,
@@ -9036,15 +13029,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [460] = {
+ [622] = {
.class_hid = BNXT_ULP_CLASS_HID_40cc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229444,
.flow_pattern_id = 0,
@@ -9056,16 +13049,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [461] = {
+ [623] = {
.class_hid = BNXT_ULP_CLASS_HID_0b0c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245760,
.flow_pattern_id = 0,
@@ -9077,15 +13070,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [462] = {
+ [624] = {
.class_hid = BNXT_ULP_CLASS_HID_0220,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245764,
.flow_pattern_id = 0,
@@ -9097,16 +13090,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [463] = {
+ [625] = {
.class_hid = BNXT_ULP_CLASS_HID_1730,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245824,
.flow_pattern_id = 0,
@@ -9118,16 +13111,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [464] = {
+ [626] = {
.class_hid = BNXT_ULP_CLASS_HID_7980,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245828,
.flow_pattern_id = 0,
@@ -9139,17 +13132,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [465] = {
+ [627] = {
.class_hid = BNXT_ULP_CLASS_HID_1db0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131072,
.flow_pattern_id = 0,
@@ -9161,12 +13154,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [466] = {
+ [628] = {
.class_hid = BNXT_ULP_CLASS_HID_1494,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131076,
.flow_pattern_id = 0,
@@ -9178,13 +13171,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [467] = {
+ [629] = {
.class_hid = BNXT_ULP_CLASS_HID_70d0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131136,
.flow_pattern_id = 0,
@@ -9196,13 +13189,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [468] = {
+ [630] = {
.class_hid = BNXT_ULP_CLASS_HID_4834,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131140,
.flow_pattern_id = 0,
@@ -9214,14 +13207,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [469] = {
+ [631] = {
.class_hid = BNXT_ULP_CLASS_HID_3db4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196608,
.flow_pattern_id = 0,
@@ -9233,13 +13226,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [470] = {
+ [632] = {
.class_hid = BNXT_ULP_CLASS_HID_3498,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196612,
.flow_pattern_id = 0,
@@ -9251,14 +13244,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [471] = {
+ [633] = {
.class_hid = BNXT_ULP_CLASS_HID_0988,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196672,
.flow_pattern_id = 0,
@@ -9270,14 +13263,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [472] = {
+ [634] = {
.class_hid = BNXT_ULP_CLASS_HID_00ec,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196676,
.flow_pattern_id = 0,
@@ -9289,15 +13282,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [473] = {
+ [635] = {
.class_hid = BNXT_ULP_CLASS_HID_3f44,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393216,
.flow_pattern_id = 0,
@@ -9309,13 +13302,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [474] = {
+ [636] = {
.class_hid = BNXT_ULP_CLASS_HID_36a8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393220,
.flow_pattern_id = 0,
@@ -9327,14 +13320,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [475] = {
+ [637] = {
.class_hid = BNXT_ULP_CLASS_HID_0b58,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393280,
.flow_pattern_id = 0,
@@ -9346,14 +13339,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [476] = {
+ [638] = {
.class_hid = BNXT_ULP_CLASS_HID_02bc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393284,
.flow_pattern_id = 0,
@@ -9365,15 +13358,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [477] = {
+ [639] = {
.class_hid = BNXT_ULP_CLASS_HID_5f48,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458752,
.flow_pattern_id = 0,
@@ -9385,14 +13378,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [478] = {
+ [640] = {
.class_hid = BNXT_ULP_CLASS_HID_56ac,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458756,
.flow_pattern_id = 0,
@@ -9404,15 +13397,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [479] = {
+ [641] = {
.class_hid = BNXT_ULP_CLASS_HID_2b5c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458816,
.flow_pattern_id = 0,
@@ -9424,15 +13417,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [480] = {
+ [642] = {
.class_hid = BNXT_ULP_CLASS_HID_2280,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458820,
.flow_pattern_id = 0,
@@ -9444,16 +13437,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [481] = {
+ [643] = {
.class_hid = BNXT_ULP_CLASS_HID_4000,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655360,
.flow_pattern_id = 0,
@@ -9465,13 +13458,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [482] = {
+ [644] = {
.class_hid = BNXT_ULP_CLASS_HID_5b64,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655364,
.flow_pattern_id = 0,
@@ -9483,14 +13476,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [483] = {
+ [645] = {
.class_hid = BNXT_ULP_CLASS_HID_2c14,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655424,
.flow_pattern_id = 0,
@@ -9502,14 +13495,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [484] = {
+ [646] = {
.class_hid = BNXT_ULP_CLASS_HID_2778,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655428,
.flow_pattern_id = 0,
@@ -9521,15 +13514,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [485] = {
+ [647] = {
.class_hid = BNXT_ULP_CLASS_HID_18f8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720896,
.flow_pattern_id = 0,
@@ -9541,14 +13534,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [486] = {
+ [648] = {
.class_hid = BNXT_ULP_CLASS_HID_13dc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720900,
.flow_pattern_id = 0,
@@ -9560,15 +13553,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [487] = {
+ [649] = {
.class_hid = BNXT_ULP_CLASS_HID_4c18,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720960,
.flow_pattern_id = 0,
@@ -9580,15 +13573,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [488] = {
+ [650] = {
.class_hid = BNXT_ULP_CLASS_HID_477c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720964,
.flow_pattern_id = 0,
@@ -9600,16 +13593,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [489] = {
+ [651] = {
.class_hid = BNXT_ULP_CLASS_HID_1a88,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917504,
.flow_pattern_id = 0,
@@ -9621,14 +13614,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [490] = {
+ [652] = {
.class_hid = BNXT_ULP_CLASS_HID_15ec,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917508,
.flow_pattern_id = 0,
@@ -9640,15 +13633,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [491] = {
+ [653] = {
.class_hid = BNXT_ULP_CLASS_HID_4e28,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917568,
.flow_pattern_id = 0,
@@ -9660,15 +13653,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [492] = {
+ [654] = {
.class_hid = BNXT_ULP_CLASS_HID_490c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917572,
.flow_pattern_id = 0,
@@ -9680,16 +13673,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [493] = {
+ [655] = {
.class_hid = BNXT_ULP_CLASS_HID_3a8c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983040,
.flow_pattern_id = 0,
@@ -9701,15 +13694,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [494] = {
+ [656] = {
.class_hid = BNXT_ULP_CLASS_HID_35f0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983044,
.flow_pattern_id = 0,
@@ -9721,16 +13714,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [495] = {
+ [657] = {
.class_hid = BNXT_ULP_CLASS_HID_06e0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983104,
.flow_pattern_id = 0,
@@ -9742,16 +13735,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [496] = {
+ [658] = {
.class_hid = BNXT_ULP_CLASS_HID_01c4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983108,
.flow_pattern_id = 0,
@@ -9763,17 +13756,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [497] = {
+ [659] = {
.class_hid = BNXT_ULP_CLASS_HID_1a08,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32768,
.flow_pattern_id = 0,
@@ -9785,12 +13778,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [498] = {
+ [660] = {
.class_hid = BNXT_ULP_CLASS_HID_12ec,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32772,
.flow_pattern_id = 0,
@@ -9802,13 +13795,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [499] = {
+ [661] = {
.class_hid = BNXT_ULP_CLASS_HID_4ea8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32832,
.flow_pattern_id = 0,
@@ -9820,13 +13813,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [500] = {
+ [662] = {
.class_hid = BNXT_ULP_CLASS_HID_478c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32836,
.flow_pattern_id = 0,
@@ -9838,14 +13831,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [501] = {
+ [663] = {
.class_hid = BNXT_ULP_CLASS_HID_0d4c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49152,
.flow_pattern_id = 0,
@@ -9857,13 +13850,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [502] = {
+ [664] = {
.class_hid = BNXT_ULP_CLASS_HID_0a20,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49156,
.flow_pattern_id = 0,
@@ -9875,14 +13868,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [503] = {
+ [665] = {
.class_hid = BNXT_ULP_CLASS_HID_1930,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49216,
.flow_pattern_id = 0,
@@ -9894,14 +13887,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [504] = {
+ [666] = {
.class_hid = BNXT_ULP_CLASS_HID_1614,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49220,
.flow_pattern_id = 0,
@@ -9913,15 +13906,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [505] = {
+ [667] = {
.class_hid = BNXT_ULP_CLASS_HID_3a0c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98304,
.flow_pattern_id = 0,
@@ -9933,13 +13926,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [506] = {
+ [668] = {
.class_hid = BNXT_ULP_CLASS_HID_32e0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98308,
.flow_pattern_id = 0,
@@ -9951,14 +13944,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [507] = {
+ [669] = {
.class_hid = BNXT_ULP_CLASS_HID_01f0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98368,
.flow_pattern_id = 0,
@@ -9970,14 +13963,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [508] = {
+ [670] = {
.class_hid = BNXT_ULP_CLASS_HID_1ed4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98372,
.flow_pattern_id = 0,
@@ -9989,15 +13982,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [509] = {
+ [671] = {
.class_hid = BNXT_ULP_CLASS_HID_2d40,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114688,
.flow_pattern_id = 0,
@@ -10009,14 +14002,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [510] = {
+ [672] = {
.class_hid = BNXT_ULP_CLASS_HID_2a24,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114692,
.flow_pattern_id = 0,
@@ -10028,15 +14021,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [511] = {
+ [673] = {
.class_hid = BNXT_ULP_CLASS_HID_3934,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114752,
.flow_pattern_id = 0,
@@ -10048,15 +14041,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [512] = {
+ [674] = {
.class_hid = BNXT_ULP_CLASS_HID_3608,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114756,
.flow_pattern_id = 0,
@@ -10068,16 +14061,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [513] = {
+ [675] = {
.class_hid = BNXT_ULP_CLASS_HID_5e60,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163840,
.flow_pattern_id = 0,
@@ -10089,13 +14082,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [514] = {
+ [676] = {
.class_hid = BNXT_ULP_CLASS_HID_5744,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163844,
.flow_pattern_id = 0,
@@ -10107,14 +14100,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [515] = {
+ [677] = {
.class_hid = BNXT_ULP_CLASS_HID_2a54,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163904,
.flow_pattern_id = 0,
@@ -10126,14 +14119,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [516] = {
+ [678] = {
.class_hid = BNXT_ULP_CLASS_HID_2328,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163908,
.flow_pattern_id = 0,
@@ -10145,15 +14138,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [517] = {
+ [679] = {
.class_hid = BNXT_ULP_CLASS_HID_71a4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180224,
.flow_pattern_id = 0,
@@ -10165,14 +14158,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [518] = {
+ [680] = {
.class_hid = BNXT_ULP_CLASS_HID_4e78,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180228,
.flow_pattern_id = 0,
@@ -10184,15 +14177,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [519] = {
+ [681] = {
.class_hid = BNXT_ULP_CLASS_HID_5d88,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180288,
.flow_pattern_id = 0,
@@ -10204,15 +14197,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [520] = {
+ [682] = {
.class_hid = BNXT_ULP_CLASS_HID_5a6c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180292,
.flow_pattern_id = 0,
@@ -10224,16 +14217,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [521] = {
+ [683] = {
.class_hid = BNXT_ULP_CLASS_HID_11a8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229376,
.flow_pattern_id = 0,
@@ -10245,14 +14238,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [522] = {
+ [684] = {
.class_hid = BNXT_ULP_CLASS_HID_7738,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229380,
.flow_pattern_id = 0,
@@ -10264,15 +14257,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [523] = {
+ [685] = {
.class_hid = BNXT_ULP_CLASS_HID_4a48,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229440,
.flow_pattern_id = 0,
@@ -10284,15 +14277,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [524] = {
+ [686] = {
.class_hid = BNXT_ULP_CLASS_HID_432c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229444,
.flow_pattern_id = 0,
@@ -10304,16 +14297,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [525] = {
+ [687] = {
.class_hid = BNXT_ULP_CLASS_HID_08ec,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245760,
.flow_pattern_id = 0,
@@ -10325,15 +14318,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [526] = {
+ [688] = {
.class_hid = BNXT_ULP_CLASS_HID_01c0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245764,
.flow_pattern_id = 0,
@@ -10345,16 +14338,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [527] = {
+ [689] = {
.class_hid = BNXT_ULP_CLASS_HID_14d0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245824,
.flow_pattern_id = 0,
@@ -10366,16 +14359,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [528] = {
+ [690] = {
.class_hid = BNXT_ULP_CLASS_HID_7a60,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245828,
.flow_pattern_id = 0,
@@ -10387,17 +14380,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [529] = {
+ [691] = {
.class_hid = BNXT_ULP_CLASS_HID_1d90,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131072,
.flow_pattern_id = 0,
@@ -10409,12 +14402,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [530] = {
+ [692] = {
.class_hid = BNXT_ULP_CLASS_HID_14b4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131076,
.flow_pattern_id = 0,
@@ -10426,13 +14419,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [531] = {
+ [693] = {
.class_hid = BNXT_ULP_CLASS_HID_70f0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131136,
.flow_pattern_id = 0,
@@ -10444,13 +14437,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [532] = {
+ [694] = {
.class_hid = BNXT_ULP_CLASS_HID_4814,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131140,
.flow_pattern_id = 0,
@@ -10462,14 +14455,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [533] = {
+ [695] = {
.class_hid = BNXT_ULP_CLASS_HID_3d94,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196608,
.flow_pattern_id = 0,
@@ -10481,13 +14474,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [534] = {
+ [696] = {
.class_hid = BNXT_ULP_CLASS_HID_34b8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196612,
.flow_pattern_id = 0,
@@ -10499,14 +14492,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [535] = {
+ [697] = {
.class_hid = BNXT_ULP_CLASS_HID_09a8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196672,
.flow_pattern_id = 0,
@@ -10518,14 +14511,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [536] = {
+ [698] = {
.class_hid = BNXT_ULP_CLASS_HID_00cc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196676,
.flow_pattern_id = 0,
@@ -10537,15 +14530,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [537] = {
+ [699] = {
.class_hid = BNXT_ULP_CLASS_HID_3f64,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393216,
.flow_pattern_id = 0,
@@ -10557,13 +14550,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [538] = {
+ [700] = {
.class_hid = BNXT_ULP_CLASS_HID_3688,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393220,
.flow_pattern_id = 0,
@@ -10575,14 +14568,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [539] = {
+ [701] = {
.class_hid = BNXT_ULP_CLASS_HID_0b78,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393280,
.flow_pattern_id = 0,
@@ -10594,14 +14587,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [540] = {
+ [702] = {
.class_hid = BNXT_ULP_CLASS_HID_029c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393284,
.flow_pattern_id = 0,
@@ -10613,15 +14606,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [541] = {
+ [703] = {
.class_hid = BNXT_ULP_CLASS_HID_5f68,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458752,
.flow_pattern_id = 0,
@@ -10633,14 +14626,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [542] = {
+ [704] = {
.class_hid = BNXT_ULP_CLASS_HID_568c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458756,
.flow_pattern_id = 0,
@@ -10652,15 +14645,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [543] = {
+ [705] = {
.class_hid = BNXT_ULP_CLASS_HID_2b7c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458816,
.flow_pattern_id = 0,
@@ -10672,15 +14665,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [544] = {
+ [706] = {
.class_hid = BNXT_ULP_CLASS_HID_22a0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458820,
.flow_pattern_id = 0,
@@ -10692,16 +14685,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [545] = {
+ [707] = {
.class_hid = BNXT_ULP_CLASS_HID_4020,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655360,
.flow_pattern_id = 0,
@@ -10713,13 +14706,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [546] = {
+ [708] = {
.class_hid = BNXT_ULP_CLASS_HID_5b44,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655364,
.flow_pattern_id = 0,
@@ -10731,14 +14724,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [547] = {
+ [709] = {
.class_hid = BNXT_ULP_CLASS_HID_2c34,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655424,
.flow_pattern_id = 0,
@@ -10750,14 +14743,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [548] = {
+ [710] = {
.class_hid = BNXT_ULP_CLASS_HID_2758,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655428,
.flow_pattern_id = 0,
@@ -10769,15 +14762,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [549] = {
+ [711] = {
.class_hid = BNXT_ULP_CLASS_HID_18d8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720896,
.flow_pattern_id = 0,
@@ -10789,14 +14782,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [550] = {
+ [712] = {
.class_hid = BNXT_ULP_CLASS_HID_13fc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720900,
.flow_pattern_id = 0,
@@ -10808,15 +14801,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [551] = {
+ [713] = {
.class_hid = BNXT_ULP_CLASS_HID_4c38,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720960,
.flow_pattern_id = 0,
@@ -10828,15 +14821,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [552] = {
+ [714] = {
.class_hid = BNXT_ULP_CLASS_HID_475c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720964,
.flow_pattern_id = 0,
@@ -10848,16 +14841,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [553] = {
+ [715] = {
.class_hid = BNXT_ULP_CLASS_HID_1aa8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917504,
.flow_pattern_id = 0,
@@ -10869,14 +14862,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [554] = {
+ [716] = {
.class_hid = BNXT_ULP_CLASS_HID_15cc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917508,
.flow_pattern_id = 0,
@@ -10888,15 +14881,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [555] = {
+ [717] = {
.class_hid = BNXT_ULP_CLASS_HID_4e08,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917568,
.flow_pattern_id = 0,
@@ -10908,15 +14901,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [556] = {
+ [718] = {
.class_hid = BNXT_ULP_CLASS_HID_492c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917572,
.flow_pattern_id = 0,
@@ -10928,16 +14921,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [557] = {
+ [719] = {
.class_hid = BNXT_ULP_CLASS_HID_3aac,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983040,
.flow_pattern_id = 0,
@@ -10949,15 +14942,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [558] = {
+ [720] = {
.class_hid = BNXT_ULP_CLASS_HID_35d0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983044,
.flow_pattern_id = 0,
@@ -10969,16 +14962,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [559] = {
+ [721] = {
.class_hid = BNXT_ULP_CLASS_HID_06c0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983104,
.flow_pattern_id = 0,
@@ -10990,16 +14983,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [560] = {
+ [722] = {
.class_hid = BNXT_ULP_CLASS_HID_01e4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983108,
.flow_pattern_id = 0,
@@ -11011,17 +15004,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [561] = {
+ [723] = {
.class_hid = BNXT_ULP_CLASS_HID_4d32,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 4096,
.flow_pattern_id = 1,
@@ -11031,11 +15024,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [562] = {
+ [724] = {
.class_hid = BNXT_ULP_CLASS_HID_54aa,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 6144,
.flow_pattern_id = 1,
@@ -11045,12 +15038,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [563] = {
+ [725] = {
.class_hid = BNXT_ULP_CLASS_HID_0686,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 16384,
.flow_pattern_id = 1,
@@ -11060,11 +15053,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [564] = {
+ [726] = {
.class_hid = BNXT_ULP_CLASS_HID_540e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 24576,
.flow_pattern_id = 1,
@@ -11074,12 +15067,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [565] = {
+ [727] = {
.class_hid = BNXT_ULP_CLASS_HID_2e3c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32768,
.flow_pattern_id = 1,
@@ -11090,11 +15083,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [566] = {
+ [728] = {
.class_hid = BNXT_ULP_CLASS_HID_3a20,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32832,
.flow_pattern_id = 1,
@@ -11105,12 +15098,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [567] = {
+ [729] = {
.class_hid = BNXT_ULP_CLASS_HID_46f0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49152,
.flow_pattern_id = 1,
@@ -11121,12 +15114,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [568] = {
+ [730] = {
.class_hid = BNXT_ULP_CLASS_HID_52e4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49216,
.flow_pattern_id = 1,
@@ -11137,13 +15130,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [569] = {
+ [731] = {
.class_hid = BNXT_ULP_CLASS_HID_55e4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131072,
.flow_pattern_id = 1,
@@ -11154,11 +15147,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [570] = {
+ [732] = {
.class_hid = BNXT_ULP_CLASS_HID_21f8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131136,
.flow_pattern_id = 1,
@@ -11169,12 +15162,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [571] = {
+ [733] = {
.class_hid = BNXT_ULP_CLASS_HID_75e8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196608,
.flow_pattern_id = 1,
@@ -11185,12 +15178,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [572] = {
+ [734] = {
.class_hid = BNXT_ULP_CLASS_HID_41fc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196672,
.flow_pattern_id = 1,
@@ -11201,13 +15194,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [573] = {
+ [735] = {
.class_hid = BNXT_ULP_CLASS_HID_4d12,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 4096,
.flow_pattern_id = 1,
@@ -11218,11 +15211,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [574] = {
+ [736] = {
.class_hid = BNXT_ULP_CLASS_HID_548a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 6144,
.flow_pattern_id = 1,
@@ -11233,12 +15226,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [575] = {
+ [737] = {
.class_hid = BNXT_ULP_CLASS_HID_3356,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 12288,
.flow_pattern_id = 1,
@@ -11249,12 +15242,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [576] = {
+ [738] = {
.class_hid = BNXT_ULP_CLASS_HID_1ace,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 14336,
.flow_pattern_id = 1,
@@ -11265,13 +15258,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [577] = {
+ [739] = {
.class_hid = BNXT_ULP_CLASS_HID_1a9a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 20480,
.flow_pattern_id = 1,
@@ -11282,12 +15275,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [578] = {
+ [740] = {
.class_hid = BNXT_ULP_CLASS_HID_4d46,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 22528,
.flow_pattern_id = 1,
@@ -11298,13 +15291,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [579] = {
+ [741] = {
.class_hid = BNXT_ULP_CLASS_HID_2812,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 28672,
.flow_pattern_id = 1,
@@ -11315,13 +15308,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [580] = {
+ [742] = {
.class_hid = BNXT_ULP_CLASS_HID_338a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 30720,
.flow_pattern_id = 1,
@@ -11332,14 +15325,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [581] = {
+ [743] = {
.class_hid = BNXT_ULP_CLASS_HID_06e6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 16384,
.flow_pattern_id = 1,
@@ -11350,11 +15343,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [582] = {
+ [744] = {
.class_hid = BNXT_ULP_CLASS_HID_546e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 24576,
.flow_pattern_id = 1,
@@ -11365,12 +15358,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [583] = {
+ [745] = {
.class_hid = BNXT_ULP_CLASS_HID_46ee,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 49152,
.flow_pattern_id = 1,
@@ -11381,12 +15374,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [584] = {
+ [746] = {
.class_hid = BNXT_ULP_CLASS_HID_0d22,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 57344,
.flow_pattern_id = 1,
@@ -11397,13 +15390,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [585] = {
+ [747] = {
.class_hid = BNXT_ULP_CLASS_HID_26e2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 81920,
.flow_pattern_id = 1,
@@ -11414,12 +15407,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [586] = {
+ [748] = {
.class_hid = BNXT_ULP_CLASS_HID_746a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 90112,
.flow_pattern_id = 1,
@@ -11430,13 +15423,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [587] = {
+ [749] = {
.class_hid = BNXT_ULP_CLASS_HID_1fa6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 114688,
.flow_pattern_id = 1,
@@ -11447,13 +15440,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [588] = {
+ [750] = {
.class_hid = BNXT_ULP_CLASS_HID_2d2e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 122880,
.flow_pattern_id = 1,
@@ -11464,14 +15457,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [589] = {
+ [751] = {
.class_hid = BNXT_ULP_CLASS_HID_4ef2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 4096,
.flow_pattern_id = 1,
@@ -11482,11 +15475,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [590] = {
+ [752] = {
.class_hid = BNXT_ULP_CLASS_HID_576a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 6144,
.flow_pattern_id = 1,
@@ -11497,12 +15490,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [591] = {
+ [753] = {
.class_hid = BNXT_ULP_CLASS_HID_30b6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 12288,
.flow_pattern_id = 1,
@@ -11513,12 +15506,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [592] = {
+ [754] = {
.class_hid = BNXT_ULP_CLASS_HID_192e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 14336,
.flow_pattern_id = 1,
@@ -11529,13 +15522,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [593] = {
+ [755] = {
.class_hid = BNXT_ULP_CLASS_HID_197a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 20480,
.flow_pattern_id = 1,
@@ -11546,12 +15539,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [594] = {
+ [756] = {
.class_hid = BNXT_ULP_CLASS_HID_4ea6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 22528,
.flow_pattern_id = 1,
@@ -11562,13 +15555,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [595] = {
+ [757] = {
.class_hid = BNXT_ULP_CLASS_HID_2bf2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 28672,
.flow_pattern_id = 1,
@@ -11579,13 +15572,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [596] = {
+ [758] = {
.class_hid = BNXT_ULP_CLASS_HID_306a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 30720,
.flow_pattern_id = 1,
@@ -11596,14 +15589,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [597] = {
+ [759] = {
.class_hid = BNXT_ULP_CLASS_HID_06c6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 16384,
.flow_pattern_id = 1,
@@ -11614,11 +15607,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [598] = {
+ [760] = {
.class_hid = BNXT_ULP_CLASS_HID_544e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 24576,
.flow_pattern_id = 1,
@@ -11629,12 +15622,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [599] = {
+ [761] = {
.class_hid = BNXT_ULP_CLASS_HID_46ce,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 49152,
.flow_pattern_id = 1,
@@ -11645,12 +15638,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [600] = {
+ [762] = {
.class_hid = BNXT_ULP_CLASS_HID_0d02,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 57344,
.flow_pattern_id = 1,
@@ -11661,13 +15654,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [601] = {
+ [763] = {
.class_hid = BNXT_ULP_CLASS_HID_26c2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 81920,
.flow_pattern_id = 1,
@@ -11678,12 +15671,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [602] = {
+ [764] = {
.class_hid = BNXT_ULP_CLASS_HID_744a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 90112,
.flow_pattern_id = 1,
@@ -11694,13 +15687,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [603] = {
+ [765] = {
.class_hid = BNXT_ULP_CLASS_HID_1f86,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 114688,
.flow_pattern_id = 1,
@@ -11711,13 +15704,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [604] = {
+ [766] = {
.class_hid = BNXT_ULP_CLASS_HID_2d0e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 122880,
.flow_pattern_id = 1,
@@ -11728,14 +15721,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [605] = {
+ [767] = {
.class_hid = BNXT_ULP_CLASS_HID_2e1c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32768,
.flow_pattern_id = 1,
@@ -11747,11 +15740,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [606] = {
+ [768] = {
.class_hid = BNXT_ULP_CLASS_HID_3a00,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32832,
.flow_pattern_id = 1,
@@ -11763,12 +15756,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [607] = {
+ [769] = {
.class_hid = BNXT_ULP_CLASS_HID_46d0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49152,
.flow_pattern_id = 1,
@@ -11780,12 +15773,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [608] = {
+ [770] = {
.class_hid = BNXT_ULP_CLASS_HID_52c4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49216,
.flow_pattern_id = 1,
@@ -11797,13 +15790,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [609] = {
+ [771] = {
.class_hid = BNXT_ULP_CLASS_HID_4e10,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98304,
.flow_pattern_id = 1,
@@ -11815,12 +15808,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [610] = {
+ [772] = {
.class_hid = BNXT_ULP_CLASS_HID_5a04,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98368,
.flow_pattern_id = 1,
@@ -11832,13 +15825,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [611] = {
+ [773] = {
.class_hid = BNXT_ULP_CLASS_HID_1f98,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114688,
.flow_pattern_id = 1,
@@ -11850,13 +15843,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [612] = {
+ [774] = {
.class_hid = BNXT_ULP_CLASS_HID_72f8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114752,
.flow_pattern_id = 1,
@@ -11868,14 +15861,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [613] = {
+ [775] = {
.class_hid = BNXT_ULP_CLASS_HID_0a78,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163840,
.flow_pattern_id = 1,
@@ -11887,12 +15880,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [614] = {
+ [776] = {
.class_hid = BNXT_ULP_CLASS_HID_166c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163904,
.flow_pattern_id = 1,
@@ -11904,13 +15897,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [615] = {
+ [777] = {
.class_hid = BNXT_ULP_CLASS_HID_233c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180224,
.flow_pattern_id = 1,
@@ -11922,13 +15915,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [616] = {
+ [778] = {
.class_hid = BNXT_ULP_CLASS_HID_0f20,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180288,
.flow_pattern_id = 1,
@@ -11940,14 +15933,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [617] = {
+ [779] = {
.class_hid = BNXT_ULP_CLASS_HID_2a7c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229376,
.flow_pattern_id = 1,
@@ -11959,13 +15952,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [618] = {
+ [780] = {
.class_hid = BNXT_ULP_CLASS_HID_3660,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229440,
.flow_pattern_id = 1,
@@ -11977,14 +15970,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [619] = {
+ [781] = {
.class_hid = BNXT_ULP_CLASS_HID_4330,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245760,
.flow_pattern_id = 1,
@@ -11996,14 +15989,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [620] = {
+ [782] = {
.class_hid = BNXT_ULP_CLASS_HID_2f24,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245824,
.flow_pattern_id = 1,
@@ -12015,15 +16008,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [621] = {
+ [783] = {
.class_hid = BNXT_ULP_CLASS_HID_5584,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131072,
.flow_pattern_id = 1,
@@ -12035,11 +16028,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [622] = {
+ [784] = {
.class_hid = BNXT_ULP_CLASS_HID_2198,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131136,
.flow_pattern_id = 1,
@@ -12051,12 +16044,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [623] = {
+ [785] = {
.class_hid = BNXT_ULP_CLASS_HID_7588,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196608,
.flow_pattern_id = 1,
@@ -12068,12 +16061,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [624] = {
+ [786] = {
.class_hid = BNXT_ULP_CLASS_HID_419c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196672,
.flow_pattern_id = 1,
@@ -12085,13 +16078,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [625] = {
+ [787] = {
.class_hid = BNXT_ULP_CLASS_HID_7758,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393216,
.flow_pattern_id = 1,
@@ -12103,12 +16096,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [626] = {
+ [788] = {
.class_hid = BNXT_ULP_CLASS_HID_43ac,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393280,
.flow_pattern_id = 1,
@@ -12120,13 +16113,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [627] = {
+ [789] = {
.class_hid = BNXT_ULP_CLASS_HID_0c10,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458752,
.flow_pattern_id = 1,
@@ -12138,13 +16131,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [628] = {
+ [790] = {
.class_hid = BNXT_ULP_CLASS_HID_1864,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458816,
.flow_pattern_id = 1,
@@ -12156,14 +16149,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [629] = {
+ [791] = {
.class_hid = BNXT_ULP_CLASS_HID_30c8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655360,
.flow_pattern_id = 1,
@@ -12175,12 +16168,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [630] = {
+ [792] = {
.class_hid = BNXT_ULP_CLASS_HID_1cdc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655424,
.flow_pattern_id = 1,
@@ -12192,13 +16185,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [631] = {
+ [793] = {
.class_hid = BNXT_ULP_CLASS_HID_50cc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720896,
.flow_pattern_id = 1,
@@ -12210,13 +16203,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [632] = {
+ [794] = {
.class_hid = BNXT_ULP_CLASS_HID_3d20,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720960,
.flow_pattern_id = 1,
@@ -12228,14 +16221,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [633] = {
+ [795] = {
.class_hid = BNXT_ULP_CLASS_HID_529c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917504,
.flow_pattern_id = 1,
@@ -12247,13 +16240,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [634] = {
+ [796] = {
.class_hid = BNXT_ULP_CLASS_HID_3ef0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917568,
.flow_pattern_id = 1,
@@ -12265,14 +16258,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [635] = {
+ [797] = {
.class_hid = BNXT_ULP_CLASS_HID_72e0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983040,
.flow_pattern_id = 1,
@@ -12284,14 +16277,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [636] = {
+ [798] = {
.class_hid = BNXT_ULP_CLASS_HID_5ef4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983104,
.flow_pattern_id = 1,
@@ -12303,15 +16296,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [637] = {
+ [799] = {
.class_hid = BNXT_ULP_CLASS_HID_2dfc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32768,
.flow_pattern_id = 1,
@@ -12323,11 +16316,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [638] = {
+ [800] = {
.class_hid = BNXT_ULP_CLASS_HID_39e0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32832,
.flow_pattern_id = 1,
@@ -12339,12 +16332,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [639] = {
+ [801] = {
.class_hid = BNXT_ULP_CLASS_HID_4530,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49152,
.flow_pattern_id = 1,
@@ -12356,12 +16349,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [640] = {
+ [802] = {
.class_hid = BNXT_ULP_CLASS_HID_5124,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49216,
.flow_pattern_id = 1,
@@ -12373,13 +16366,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [641] = {
+ [803] = {
.class_hid = BNXT_ULP_CLASS_HID_4df0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98304,
.flow_pattern_id = 1,
@@ -12391,12 +16384,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [642] = {
+ [804] = {
.class_hid = BNXT_ULP_CLASS_HID_59e4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98368,
.flow_pattern_id = 1,
@@ -12408,13 +16401,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [643] = {
+ [805] = {
.class_hid = BNXT_ULP_CLASS_HID_1c78,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114688,
.flow_pattern_id = 1,
@@ -12426,13 +16419,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [644] = {
+ [806] = {
.class_hid = BNXT_ULP_CLASS_HID_7118,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114752,
.flow_pattern_id = 1,
@@ -12444,14 +16437,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [645] = {
+ [807] = {
.class_hid = BNXT_ULP_CLASS_HID_0998,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163840,
.flow_pattern_id = 1,
@@ -12463,12 +16456,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [646] = {
+ [808] = {
.class_hid = BNXT_ULP_CLASS_HID_158c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163904,
.flow_pattern_id = 1,
@@ -12480,13 +16473,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [647] = {
+ [809] = {
.class_hid = BNXT_ULP_CLASS_HID_20dc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180224,
.flow_pattern_id = 1,
@@ -12498,13 +16491,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [648] = {
+ [810] = {
.class_hid = BNXT_ULP_CLASS_HID_0cc0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180288,
.flow_pattern_id = 1,
@@ -12516,14 +16509,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [649] = {
+ [811] = {
.class_hid = BNXT_ULP_CLASS_HID_299c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229376,
.flow_pattern_id = 1,
@@ -12535,13 +16528,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [650] = {
+ [812] = {
.class_hid = BNXT_ULP_CLASS_HID_3580,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229440,
.flow_pattern_id = 1,
@@ -12553,14 +16546,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [651] = {
+ [813] = {
.class_hid = BNXT_ULP_CLASS_HID_40d0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245760,
.flow_pattern_id = 1,
@@ -12572,14 +16565,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [652] = {
+ [814] = {
.class_hid = BNXT_ULP_CLASS_HID_2cc4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245824,
.flow_pattern_id = 1,
@@ -12591,15 +16584,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [653] = {
+ [815] = {
.class_hid = BNXT_ULP_CLASS_HID_55a4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131072,
.flow_pattern_id = 1,
@@ -12611,11 +16604,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [654] = {
+ [816] = {
.class_hid = BNXT_ULP_CLASS_HID_21b8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131136,
.flow_pattern_id = 1,
@@ -12627,12 +16620,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [655] = {
+ [817] = {
.class_hid = BNXT_ULP_CLASS_HID_75a8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196608,
.flow_pattern_id = 1,
@@ -12644,12 +16637,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [656] = {
+ [818] = {
.class_hid = BNXT_ULP_CLASS_HID_41bc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196672,
.flow_pattern_id = 1,
@@ -12661,13 +16654,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [657] = {
+ [819] = {
.class_hid = BNXT_ULP_CLASS_HID_7778,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393216,
.flow_pattern_id = 1,
@@ -12679,12 +16672,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [658] = {
+ [820] = {
.class_hid = BNXT_ULP_CLASS_HID_438c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393280,
.flow_pattern_id = 1,
@@ -12696,13 +16689,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [659] = {
+ [821] = {
.class_hid = BNXT_ULP_CLASS_HID_0c30,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458752,
.flow_pattern_id = 1,
@@ -12714,13 +16707,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [660] = {
+ [822] = {
.class_hid = BNXT_ULP_CLASS_HID_1844,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458816,
.flow_pattern_id = 1,
@@ -12732,14 +16725,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [661] = {
+ [823] = {
.class_hid = BNXT_ULP_CLASS_HID_30e8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655360,
.flow_pattern_id = 1,
@@ -12751,12 +16744,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [662] = {
+ [824] = {
.class_hid = BNXT_ULP_CLASS_HID_1cfc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655424,
.flow_pattern_id = 1,
@@ -12768,13 +16761,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [663] = {
+ [825] = {
.class_hid = BNXT_ULP_CLASS_HID_50ec,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720896,
.flow_pattern_id = 1,
@@ -12786,13 +16779,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [664] = {
+ [826] = {
.class_hid = BNXT_ULP_CLASS_HID_3d00,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720960,
.flow_pattern_id = 1,
@@ -12804,14 +16797,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [665] = {
+ [827] = {
.class_hid = BNXT_ULP_CLASS_HID_52bc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917504,
.flow_pattern_id = 1,
@@ -12823,13 +16816,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [666] = {
+ [828] = {
.class_hid = BNXT_ULP_CLASS_HID_3ed0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917568,
.flow_pattern_id = 1,
@@ -12841,14 +16834,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [667] = {
+ [829] = {
.class_hid = BNXT_ULP_CLASS_HID_72c0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983040,
.flow_pattern_id = 1,
@@ -12860,14 +16853,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [668] = {
+ [830] = {
.class_hid = BNXT_ULP_CLASS_HID_5ed4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983104,
.flow_pattern_id = 1,
@@ -12879,15 +16872,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [669] = {
+ [831] = {
.class_hid = BNXT_ULP_CLASS_HID_3866,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -12897,12 +16890,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC }
},
- [670] = {
+ [832] = {
.class_hid = BNXT_ULP_CLASS_HID_381e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -12912,12 +16905,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC }
},
- [671] = {
+ [833] = {
.class_hid = BNXT_ULP_CLASS_HID_3860,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -12928,12 +16921,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC }
},
- [672] = {
+ [834] = {
.class_hid = BNXT_ULP_CLASS_HID_0454,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 68,
.flow_pattern_id = 2,
@@ -12944,13 +16937,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID }
},
- [673] = {
+ [835] = {
.class_hid = BNXT_ULP_CLASS_HID_3818,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -12961,12 +16954,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC }
},
- [674] = {
+ [836] = {
.class_hid = BNXT_ULP_CLASS_HID_042c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 68,
.flow_pattern_id = 2,
@@ -12977,13 +16970,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID }
},
- [675] = {
+ [837] = {
.class_hid = BNXT_ULP_CLASS_HID_3846,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -12994,12 +16987,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC }
},
- [676] = {
+ [838] = {
.class_hid = BNXT_ULP_CLASS_HID_387e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -13010,12 +17003,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC }
},
- [677] = {
+ [839] = {
.class_hid = BNXT_ULP_CLASS_HID_3ba6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -13026,12 +17019,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC }
},
- [678] = {
+ [840] = {
.class_hid = BNXT_ULP_CLASS_HID_385e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -13042,12 +17035,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC }
},
- [679] = {
+ [841] = {
.class_hid = BNXT_ULP_CLASS_HID_3840,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -13059,12 +17052,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC }
},
- [680] = {
+ [842] = {
.class_hid = BNXT_ULP_CLASS_HID_0474,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 68,
.flow_pattern_id = 2,
@@ -13076,13 +17069,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID }
},
- [681] = {
+ [843] = {
.class_hid = BNXT_ULP_CLASS_HID_3878,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -13094,12 +17087,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC }
},
- [682] = {
+ [844] = {
.class_hid = BNXT_ULP_CLASS_HID_044c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 68,
.flow_pattern_id = 2,
@@ -13111,13 +17104,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID }
},
- [683] = {
+ [845] = {
.class_hid = BNXT_ULP_CLASS_HID_3ba0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -13129,12 +17122,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC }
},
- [684] = {
+ [846] = {
.class_hid = BNXT_ULP_CLASS_HID_0794,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 68,
.flow_pattern_id = 2,
@@ -13146,13 +17139,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID }
},
- [685] = {
+ [847] = {
.class_hid = BNXT_ULP_CLASS_HID_3858,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -13164,12 +17157,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC }
},
- [686] = {
+ [848] = {
.class_hid = BNXT_ULP_CLASS_HID_046c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 68,
.flow_pattern_id = 2,
@@ -13181,8 +17174,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID }
}
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
index b6db49cc5d..e55d0923a5 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 13 18:15:56 2021 */
+/* date: Thu May 20 11:56:39 2021 */
#ifndef ULP_TEMPLATE_DB_H_
#define ULP_TEMPLATE_DB_H_
@@ -11,13 +11,13 @@
#define BNXT_ULP_REGFILE_MAX_SZ 40
#define BNXT_ULP_MAX_NUM_DEVICES 4
#define BNXT_ULP_LOG2_MAX_NUM_DEV 2
-#define BNXT_ULP_GEN_TBL_MAX_SZ 10
+#define BNXT_ULP_GEN_TBL_MAX_SZ 12
#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 32768
-#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 687
+#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 849
#define BNXT_ULP_CLASS_HID_LOW_PRIME 6701
#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907
-#define BNXT_ULP_CLASS_HID_SHFTR 23
-#define BNXT_ULP_CLASS_HID_SHFTL 23
+#define BNXT_ULP_CLASS_HID_SHFTR 24
+#define BNXT_ULP_CLASS_HID_SHFTL 24
#define BNXT_ULP_CLASS_HID_MASK 32767
#define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048
#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 86
@@ -36,14 +36,14 @@
#define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7
#define BNXT_ULP_HDR_SIG_ID_SHIFT 4
#define BNXT_ULP_APP_ID_SHIFT 4
-#define BNXT_ULP_GLB_FIELD_TBL_SIZE 5595
-#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 5
-#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 74
-#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 495
-#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 20
-#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 546
-#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 43
-#define ULP_THOR_CLASS_TMPL_LIST_SIZE 5
+#define BNXT_ULP_GLB_FIELD_TBL_SIZE 7643
+#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 6
+#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 89
+#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 600
+#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 26
+#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 619
+#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 49
+#define ULP_THOR_CLASS_TMPL_LIST_SIZE 6
#define ULP_THOR_CLASS_TBL_LIST_SIZE 33
#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 242
#define ULP_THOR_CLASS_IDENT_LIST_SIZE 8
@@ -113,7 +113,8 @@ enum bnxt_ulp_hdr_bit {
BNXT_ULP_HDR_BIT_I_UDP = 0x0000000000010000,
BNXT_ULP_HDR_BIT_I_ICMP = 0x0000000000020000,
BNXT_ULP_HDR_BIT_F1 = 0x0000000000040000,
- BNXT_ULP_HDR_BIT_LAST = 0x0000000000080000
+ BNXT_ULP_HDR_BIT_F2 = 0x0000000000080000,
+ BNXT_ULP_HDR_BIT_LAST = 0x0000000000100000
};
enum bnxt_ulp_accept_opc {
@@ -199,8 +200,10 @@ enum bnxt_ulp_cf_idx {
BNXT_ULP_CF_IDX_FLOW_SIG_ID = 60,
BNXT_ULP_CF_IDX_WC_MATCH = 61,
BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG = 62,
- BNXT_ULP_CF_IDX_F1_DMAC = 63,
- BNXT_ULP_CF_IDX_LAST = 64
+ BNXT_ULP_CF_IDX_TUNNEL_ID = 63,
+ BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID = 64,
+ BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID = 65,
+ BNXT_ULP_CF_IDX_LAST = 66
};
enum bnxt_ulp_cond_list_opc {
@@ -315,7 +318,8 @@ enum bnxt_ulp_func_opc {
BNXT_ULP_FUNC_OPC_COPY_SRC1_TO_RF = 7,
BNXT_ULP_FUNC_OPC_RSS_CONFIG = 8,
BNXT_ULP_FUNC_OPC_GET_PARENT_MAC_ADDR = 9,
- BNXT_ULP_FUNC_OPC_LAST = 10
+ BNXT_ULP_FUNC_OPC_ALLOC_L2_CTX_ID = 10,
+ BNXT_ULP_FUNC_OPC_LAST = 11
};
enum bnxt_ulp_func_src {
@@ -497,7 +501,8 @@ enum bnxt_ulp_tcam_tbl_opc {
BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE = 2,
BNXT_ULP_TCAM_TBL_OPC_ALLOC_REGFILE = 3,
BNXT_ULP_TCAM_TBL_OPC_WR_REGFILE = 4,
- BNXT_ULP_TCAM_TBL_OPC_LAST = 5
+ BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT = 5,
+ BNXT_ULP_TCAM_TBL_OPC_LAST = 6
};
enum bnxt_ulp_template_type {
@@ -549,7 +554,8 @@ enum bnxt_ulp_resource_sub_type {
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM = 1,
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR = 2,
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE = 3,
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE = 4
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE = 4,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE = 5
};
enum bnxt_ulp_act_prop_sz {
@@ -1443,6 +1449,168 @@ enum bnxt_ulp_class_hid {
BNXT_ULP_CLASS_HID_15db = 0x15db,
BNXT_ULP_CLASS_HID_1151 = 0x1151,
BNXT_ULP_CLASS_HID_315d = 0x315d,
+ BNXT_ULP_CLASS_HID_3612 = 0x3612,
+ BNXT_ULP_CLASS_HID_66da = 0x66da,
+ BNXT_ULP_CLASS_HID_6165 = 0x6165,
+ BNXT_ULP_CLASS_HID_2aa1 = 0x2aa1,
+ BNXT_ULP_CLASS_HID_09cd = 0x09cd,
+ BNXT_ULP_CLASS_HID_3845 = 0x3845,
+ BNXT_ULP_CLASS_HID_11e9 = 0x11e9,
+ BNXT_ULP_CLASS_HID_4361 = 0x4361,
+ BNXT_ULP_CLASS_HID_218d = 0x218d,
+ BNXT_ULP_CLASS_HID_5105 = 0x5105,
+ BNXT_ULP_CLASS_HID_0c89 = 0x0c89,
+ BNXT_ULP_CLASS_HID_3e81 = 0x3e81,
+ BNXT_ULP_CLASS_HID_1dad = 0x1dad,
+ BNXT_ULP_CLASS_HID_4ca5 = 0x4ca5,
+ BNXT_ULP_CLASS_HID_25c9 = 0x25c9,
+ BNXT_ULP_CLASS_HID_57c1 = 0x57c1,
+ BNXT_ULP_CLASS_HID_33ed = 0x33ed,
+ BNXT_ULP_CLASS_HID_65e5 = 0x65e5,
+ BNXT_ULP_CLASS_HID_6dd9 = 0x6dd9,
+ BNXT_ULP_CLASS_HID_261d = 0x261d,
+ BNXT_ULP_CLASS_HID_0571 = 0x0571,
+ BNXT_ULP_CLASS_HID_34f9 = 0x34f9,
+ BNXT_ULP_CLASS_HID_1d55 = 0x1d55,
+ BNXT_ULP_CLASS_HID_4fdd = 0x4fdd,
+ BNXT_ULP_CLASS_HID_2d31 = 0x2d31,
+ BNXT_ULP_CLASS_HID_5db9 = 0x5db9,
+ BNXT_ULP_CLASS_HID_0035 = 0x0035,
+ BNXT_ULP_CLASS_HID_323d = 0x323d,
+ BNXT_ULP_CLASS_HID_1111 = 0x1111,
+ BNXT_ULP_CLASS_HID_4019 = 0x4019,
+ BNXT_ULP_CLASS_HID_2975 = 0x2975,
+ BNXT_ULP_CLASS_HID_5b7d = 0x5b7d,
+ BNXT_ULP_CLASS_HID_3f51 = 0x3f51,
+ BNXT_ULP_CLASS_HID_6959 = 0x6959,
+ BNXT_ULP_CLASS_HID_0e85 = 0x0e85,
+ BNXT_ULP_CLASS_HID_380d = 0x380d,
+ BNXT_ULP_CLASS_HID_1f21 = 0x1f21,
+ BNXT_ULP_CLASS_HID_4ea9 = 0x4ea9,
+ BNXT_ULP_CLASS_HID_1705 = 0x1705,
+ BNXT_ULP_CLASS_HID_418d = 0x418d,
+ BNXT_ULP_CLASS_HID_2721 = 0x2721,
+ BNXT_ULP_CLASS_HID_57a9 = 0x57a9,
+ BNXT_ULP_CLASS_HID_1a25 = 0x1a25,
+ BNXT_ULP_CLASS_HID_342d = 0x342d,
+ BNXT_ULP_CLASS_HID_2b01 = 0x2b01,
+ BNXT_ULP_CLASS_HID_5a09 = 0x5a09,
+ BNXT_ULP_CLASS_HID_2325 = 0x2325,
+ BNXT_ULP_CLASS_HID_5d2d = 0x5d2d,
+ BNXT_ULP_CLASS_HID_3101 = 0x3101,
+ BNXT_ULP_CLASS_HID_6309 = 0x6309,
+ BNXT_ULP_CLASS_HID_0bad = 0x0bad,
+ BNXT_ULP_CLASS_HID_2535 = 0x2535,
+ BNXT_ULP_CLASS_HID_1869 = 0x1869,
+ BNXT_ULP_CLASS_HID_4bf1 = 0x4bf1,
+ BNXT_ULP_CLASS_HID_136d = 0x136d,
+ BNXT_ULP_CLASS_HID_43f5 = 0x43f5,
+ BNXT_ULP_CLASS_HID_2129 = 0x2129,
+ BNXT_ULP_CLASS_HID_53b1 = 0x53b1,
+ BNXT_ULP_CLASS_HID_072d = 0x072d,
+ BNXT_ULP_CLASS_HID_3135 = 0x3135,
+ BNXT_ULP_CLASS_HID_1429 = 0x1429,
+ BNXT_ULP_CLASS_HID_4731 = 0x4731,
+ BNXT_ULP_CLASS_HID_2f6d = 0x2f6d,
+ BNXT_ULP_CLASS_HID_5f75 = 0x5f75,
+ BNXT_ULP_CLASS_HID_3d69 = 0x3d69,
+ BNXT_ULP_CLASS_HID_6f71 = 0x6f71,
+ BNXT_ULP_CLASS_HID_0dbd = 0x0dbd,
+ BNXT_ULP_CLASS_HID_3f25 = 0x3f25,
+ BNXT_ULP_CLASS_HID_1239 = 0x1239,
+ BNXT_ULP_CLASS_HID_4da1 = 0x4da1,
+ BNXT_ULP_CLASS_HID_153d = 0x153d,
+ BNXT_ULP_CLASS_HID_45a5 = 0x45a5,
+ BNXT_ULP_CLASS_HID_3bb9 = 0x3bb9,
+ BNXT_ULP_CLASS_HID_55a1 = 0x55a1,
+ BNXT_ULP_CLASS_HID_193d = 0x193d,
+ BNXT_ULP_CLASS_HID_4b25 = 0x4b25,
+ BNXT_ULP_CLASS_HID_2e39 = 0x2e39,
+ BNXT_ULP_CLASS_HID_5921 = 0x5921,
+ BNXT_ULP_CLASS_HID_213d = 0x213d,
+ BNXT_ULP_CLASS_HID_5125 = 0x5125,
+ BNXT_ULP_CLASS_HID_3739 = 0x3739,
+ BNXT_ULP_CLASS_HID_093d = 0x093d,
+ BNXT_ULP_CLASS_HID_684d = 0x684d,
+ BNXT_ULP_CLASS_HID_2389 = 0x2389,
+ BNXT_ULP_CLASS_HID_00e5 = 0x00e5,
+ BNXT_ULP_CLASS_HID_316d = 0x316d,
+ BNXT_ULP_CLASS_HID_18c1 = 0x18c1,
+ BNXT_ULP_CLASS_HID_4a49 = 0x4a49,
+ BNXT_ULP_CLASS_HID_28a5 = 0x28a5,
+ BNXT_ULP_CLASS_HID_582d = 0x582d,
+ BNXT_ULP_CLASS_HID_05a1 = 0x05a1,
+ BNXT_ULP_CLASS_HID_37a9 = 0x37a9,
+ BNXT_ULP_CLASS_HID_1485 = 0x1485,
+ BNXT_ULP_CLASS_HID_458d = 0x458d,
+ BNXT_ULP_CLASS_HID_2ce1 = 0x2ce1,
+ BNXT_ULP_CLASS_HID_5ee9 = 0x5ee9,
+ BNXT_ULP_CLASS_HID_3ac5 = 0x3ac5,
+ BNXT_ULP_CLASS_HID_6ccd = 0x6ccd,
+ BNXT_ULP_CLASS_HID_0b11 = 0x0b11,
+ BNXT_ULP_CLASS_HID_3d99 = 0x3d99,
+ BNXT_ULP_CLASS_HID_1ab5 = 0x1ab5,
+ BNXT_ULP_CLASS_HID_4b3d = 0x4b3d,
+ BNXT_ULP_CLASS_HID_1291 = 0x1291,
+ BNXT_ULP_CLASS_HID_4419 = 0x4419,
+ BNXT_ULP_CLASS_HID_22b5 = 0x22b5,
+ BNXT_ULP_CLASS_HID_523d = 0x523d,
+ BNXT_ULP_CLASS_HID_1fb1 = 0x1fb1,
+ BNXT_ULP_CLASS_HID_31b9 = 0x31b9,
+ BNXT_ULP_CLASS_HID_2e95 = 0x2e95,
+ BNXT_ULP_CLASS_HID_5f9d = 0x5f9d,
+ BNXT_ULP_CLASS_HID_26b1 = 0x26b1,
+ BNXT_ULP_CLASS_HID_58b9 = 0x58b9,
+ BNXT_ULP_CLASS_HID_3495 = 0x3495,
+ BNXT_ULP_CLASS_HID_669d = 0x669d,
+ BNXT_ULP_CLASS_HID_0e39 = 0x0e39,
+ BNXT_ULP_CLASS_HID_20a1 = 0x20a1,
+ BNXT_ULP_CLASS_HID_1dfd = 0x1dfd,
+ BNXT_ULP_CLASS_HID_4e65 = 0x4e65,
+ BNXT_ULP_CLASS_HID_16f9 = 0x16f9,
+ BNXT_ULP_CLASS_HID_4661 = 0x4661,
+ BNXT_ULP_CLASS_HID_24bd = 0x24bd,
+ BNXT_ULP_CLASS_HID_5625 = 0x5625,
+ BNXT_ULP_CLASS_HID_02b9 = 0x02b9,
+ BNXT_ULP_CLASS_HID_34a1 = 0x34a1,
+ BNXT_ULP_CLASS_HID_11bd = 0x11bd,
+ BNXT_ULP_CLASS_HID_42a5 = 0x42a5,
+ BNXT_ULP_CLASS_HID_2af9 = 0x2af9,
+ BNXT_ULP_CLASS_HID_5ae1 = 0x5ae1,
+ BNXT_ULP_CLASS_HID_38fd = 0x38fd,
+ BNXT_ULP_CLASS_HID_6ae5 = 0x6ae5,
+ BNXT_ULP_CLASS_HID_0829 = 0x0829,
+ BNXT_ULP_CLASS_HID_3ab1 = 0x3ab1,
+ BNXT_ULP_CLASS_HID_17ad = 0x17ad,
+ BNXT_ULP_CLASS_HID_4835 = 0x4835,
+ BNXT_ULP_CLASS_HID_10a9 = 0x10a9,
+ BNXT_ULP_CLASS_HID_4031 = 0x4031,
+ BNXT_ULP_CLASS_HID_3e2d = 0x3e2d,
+ BNXT_ULP_CLASS_HID_5035 = 0x5035,
+ BNXT_ULP_CLASS_HID_1ca9 = 0x1ca9,
+ BNXT_ULP_CLASS_HID_4eb1 = 0x4eb1,
+ BNXT_ULP_CLASS_HID_2bad = 0x2bad,
+ BNXT_ULP_CLASS_HID_5cb5 = 0x5cb5,
+ BNXT_ULP_CLASS_HID_24a9 = 0x24a9,
+ BNXT_ULP_CLASS_HID_54b1 = 0x54b1,
+ BNXT_ULP_CLASS_HID_32ad = 0x32ad,
+ BNXT_ULP_CLASS_HID_0ca9 = 0x0ca9,
+ BNXT_ULP_CLASS_HID_7f35 = 0x7f35,
+ BNXT_ULP_CLASS_HID_34f1 = 0x34f1,
+ BNXT_ULP_CLASS_HID_179d = 0x179d,
+ BNXT_ULP_CLASS_HID_2615 = 0x2615,
+ BNXT_ULP_CLASS_HID_0fb9 = 0x0fb9,
+ BNXT_ULP_CLASS_HID_5d31 = 0x5d31,
+ BNXT_ULP_CLASS_HID_3fdd = 0x3fdd,
+ BNXT_ULP_CLASS_HID_4f55 = 0x4f55,
+ BNXT_ULP_CLASS_HID_12d9 = 0x12d9,
+ BNXT_ULP_CLASS_HID_20d1 = 0x20d1,
+ BNXT_ULP_CLASS_HID_03fd = 0x03fd,
+ BNXT_ULP_CLASS_HID_52f5 = 0x52f5,
+ BNXT_ULP_CLASS_HID_3b99 = 0x3b99,
+ BNXT_ULP_CLASS_HID_4991 = 0x4991,
+ BNXT_ULP_CLASS_HID_2dbd = 0x2dbd,
+ BNXT_ULP_CLASS_HID_7bb5 = 0x7bb5,
BNXT_ULP_CLASS_HID_34c6 = 0x34c6,
BNXT_ULP_CLASS_HID_0c22 = 0x0c22,
BNXT_ULP_CLASS_HID_1cbe = 0x1cbe,
@@ -1876,8 +2044,8 @@ enum bnxt_ulp_act_hid {
};
enum bnxt_ulp_df_tpl {
- BNXT_ULP_DF_TPL_DEFAULT_UPLINK_PORT = 3,
- BNXT_ULP_DF_TPL_DEFAULT_VFR = 4
+ BNXT_ULP_DF_TPL_DEFAULT_UPLINK_PORT = 4,
+ BNXT_ULP_DF_TPL_DEFAULT_VFR = 5
};
#endif
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h
index 115bdc644c..1d7bbfe2cc 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Wed Mar 17 11:31:19 2021 */
+/* date: Thu May 20 11:56:39 2021 */
#ifndef ULP_HDR_FIELD_ENUMS_H_
#define ULP_HDR_FIELD_ENUMS_H_
@@ -415,272 +415,460 @@ enum bnxt_ulp_hf_0_2_0_bitmask {
BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_VER = 0x0400000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_TC = 0x0200000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_TTL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_TOS = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_LEN = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_LENGTH = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_CSUM = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_FLAGS = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_RSVD0 = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_VNI = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_RSVD1 = 0x0000020000000000
};
enum bnxt_ulp_hf_0_2_1_bitmask {
BNXT_ULP_HF_0_2_1_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_VER = 0x0400000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TOS = 0x0200000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_LEN = 0x0100000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TTL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000
};
enum bnxt_ulp_hf_0_2_2_bitmask {
BNXT_ULP_HF_0_2_2_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID = 0x0200000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_VER = 0x0080000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_TC = 0x0040000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_TTL = 0x0004000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SENT_SEQ = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_RECV_ACK = 0x0000000008000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DATA_OFF = 0x0000000004000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_TCP_FLAGS = 0x0000000002000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_RX_WIN = 0x0000000001000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_CSUM = 0x0000000000800000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_URP = 0x0000000000400000
};
enum bnxt_ulp_hf_0_2_3_bitmask {
BNXT_ULP_HF_0_2_3_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID = 0x0200000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_VER = 0x0080000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TOS = 0x0040000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_LEN = 0x0020000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TTL = 0x0004000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_LENGTH = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_CSUM = 0x0000000008000000
};
enum bnxt_ulp_hf_0_2_4_bitmask {
BNXT_ULP_HF_0_2_4_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_VER = 0x0400000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_TC = 0x0200000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_TTL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT = 0x0004000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT = 0x0002000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SENT_SEQ = 0x0001000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_RECV_ACK = 0x0000800000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DATA_OFF = 0x0000400000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_TCP_FLAGS = 0x0000200000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_RX_WIN = 0x0000100000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_CSUM = 0x0000080000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_URP = 0x0000040000000000
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_TYPE = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_CODE = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_CSUM = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_IDENT = 0x0000000008000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_SEQ_NUM = 0x0000000004000000
};
-enum bnxt_ulp_hf_0_2_5_bitmask {
- BNXT_ULP_HF_0_2_5_BITMASK_WM = 0x8000000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_VER = 0x0400000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_TOS = 0x0200000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_LEN = 0x0100000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_TTL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT = 0x0000800000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_RX_WIN = 0x0000040000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_CSUM = 0x0000020000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_URP = 0x0000010000000000
+enum bnxt_ulp_hf_0_3_0_bitmask {
+ BNXT_ULP_HF_0_3_0_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_TC = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000
};
-enum bnxt_ulp_hf_0_2_6_bitmask {
- BNXT_ULP_HF_0_2_6_BITMASK_WM = 0x8000000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_VER = 0x0400000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_TC = 0x0200000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_TTL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT = 0x0002000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_LENGTH = 0x0001000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_CSUM = 0x0000800000000000
+enum bnxt_ulp_hf_0_3_1_bitmask {
+ BNXT_ULP_HF_0_3_1_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_TOS = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_LEN = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000
};
-enum bnxt_ulp_hf_0_2_7_bitmask {
- BNXT_ULP_HF_0_2_7_BITMASK_WM = 0x8000000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_VER = 0x0400000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_TOS = 0x0200000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_LEN = 0x0100000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_TTL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT = 0x0000800000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_LENGTH = 0x0000400000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_CSUM = 0x0000200000000000
+enum bnxt_ulp_hf_0_3_2_bitmask {
+ BNXT_ULP_HF_0_3_2_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_VER = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_TC = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_TTL = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000
};
-enum bnxt_ulp_hf_0_2_8_bitmask {
- BNXT_ULP_HF_0_2_8_BITMASK_WM = 0x8000000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID = 0x0200000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_VER = 0x0080000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_TC = 0x0040000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_TTL = 0x0004000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT = 0x0000400000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_RX_WIN = 0x0000020000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_CSUM = 0x0000010000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_URP = 0x0000008000000000
+enum bnxt_ulp_hf_0_3_3_bitmask {
+ BNXT_ULP_HF_0_3_3_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_VER = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_TOS = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_LEN = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_TTL = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000
};
-enum bnxt_ulp_hf_0_2_9_bitmask {
- BNXT_ULP_HF_0_2_9_BITMASK_WM = 0x8000000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID = 0x0200000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_VER = 0x0080000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_TOS = 0x0040000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_LEN = 0x0020000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_TTL = 0x0004000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT = 0x0000100000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_RX_WIN = 0x0000008000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_CSUM = 0x0000004000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_URP = 0x0000002000000000
+enum bnxt_ulp_hf_0_3_4_bitmask {
+ BNXT_ULP_HF_0_3_4_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_TC = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SENT_SEQ = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_RECV_ACK = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DATA_OFF = 0x0000400000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_TCP_FLAGS = 0x0000200000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_RX_WIN = 0x0000100000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_CSUM = 0x0000080000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_URP = 0x0000040000000000
};
-enum bnxt_ulp_hf_0_2_10_bitmask {
- BNXT_ULP_HF_0_2_10_BITMASK_WM = 0x8000000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID = 0x0200000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_VER = 0x0080000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_TC = 0x0040000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_TTL = 0x0004000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT = 0x0000400000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_LENGTH = 0x0000200000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_CSUM = 0x0000100000000000
+enum bnxt_ulp_hf_0_3_5_bitmask {
+ BNXT_ULP_HF_0_3_5_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_TOS = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_LEN = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_RX_WIN = 0x0000040000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_CSUM = 0x0000020000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_URP = 0x0000010000000000
};
-enum bnxt_ulp_hf_0_2_11_bitmask {
- BNXT_ULP_HF_0_2_11_BITMASK_WM = 0x8000000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID = 0x0200000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_VER = 0x0080000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_TOS = 0x0040000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_LEN = 0x0020000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_TTL = 0x0004000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT = 0x0000100000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_LENGTH = 0x0000080000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_CSUM = 0x0000040000000000
+enum bnxt_ulp_hf_0_3_6_bitmask {
+ BNXT_ULP_HF_0_3_6_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_TC = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_LENGTH = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_CSUM = 0x0000800000000000
+};
+
+enum bnxt_ulp_hf_0_3_7_bitmask {
+ BNXT_ULP_HF_0_3_7_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_TOS = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_LEN = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_LENGTH = 0x0000400000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_CSUM = 0x0000200000000000
+};
+
+enum bnxt_ulp_hf_0_3_8_bitmask {
+ BNXT_ULP_HF_0_3_8_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_VER = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_TC = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_TTL = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT = 0x0000400000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_RX_WIN = 0x0000020000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_CSUM = 0x0000010000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_URP = 0x0000008000000000
+};
+
+enum bnxt_ulp_hf_0_3_9_bitmask {
+ BNXT_ULP_HF_0_3_9_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_VER = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_TOS = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_LEN = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_TTL = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT = 0x0000100000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_RX_WIN = 0x0000008000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_CSUM = 0x0000004000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_URP = 0x0000002000000000
+};
+
+enum bnxt_ulp_hf_0_3_10_bitmask {
+ BNXT_ULP_HF_0_3_10_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_VER = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_TC = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_TTL = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT = 0x0000400000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_LENGTH = 0x0000200000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_CSUM = 0x0000100000000000
+};
+
+enum bnxt_ulp_hf_0_3_11_bitmask {
+ BNXT_ULP_HF_0_3_11_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_VER = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_TOS = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_LEN = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_TTL = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT = 0x0000100000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_LENGTH = 0x0000080000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_CSUM = 0x0000040000000000
};
#endif
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
index 2debaea0ca..58b4dba63c 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 13 18:15:56 2021 */
+/* date: Thu May 20 11:56:39 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -111,6 +111,26 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = {
.num_buckets = 0,
.hash_tbl_entries = 0,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE << 1 |
+ BNXT_ULP_DIRECTION_INGRESS] = {
+ .name = "INGRESS GENERIC_TABLE_TUNNEL_CACHE",
+ .result_num_entries = 256,
+ .result_num_bytes = 7,
+ .key_num_bytes = 2,
+ .num_buckets = 8,
+ .hash_tbl_entries = 1024,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE << 1 |
+ BNXT_ULP_DIRECTION_EGRESS] = {
+ .name = "EGRESS GENERIC_TABLE_TUNNEL_CACHE",
+ .result_num_entries = 256,
+ .result_num_bytes = 7,
+ .key_num_bytes = 2,
+ .num_buckets = 8,
+ .hash_tbl_entries = 1024,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
}
};
@@ -3098,238 +3118,411 @@ uint8_t ulp_glb_field_tbl[] = {
[4098] = 2,
[4100] = 3,
[4102] = 4,
- [4136] = 5,
- [4138] = 6,
- [4140] = 7,
- [4142] = 8,
- [4144] = 9,
- [4146] = 10,
- [4148] = 11,
- [4150] = 12,
+ [4116] = 5,
+ [4118] = 6,
+ [4120] = 7,
+ [4122] = 8,
+ [4124] = 9,
+ [4126] = 10,
+ [4128] = 11,
+ [4130] = 12,
+ [4132] = 13,
+ [4134] = 14,
+ [4170] = 15,
+ [4172] = 16,
+ [4174] = 17,
+ [4176] = 18,
+ [4190] = 19,
+ [4191] = 20,
+ [4192] = 21,
+ [4193] = 22,
[4224] = 0,
[4225] = 1,
- [4226] = 2,
- [4228] = 3,
- [4230] = 4,
- [4244] = 5,
- [4246] = 6,
- [4248] = 7,
- [4250] = 8,
- [4252] = 9,
- [4254] = 10,
- [4256] = 11,
- [4258] = 12,
- [4260] = 13,
- [4262] = 14,
+ [4227] = 20,
+ [4229] = 21,
+ [4231] = 22,
+ [4244] = 2,
+ [4245] = 23,
+ [4246] = 3,
+ [4247] = 24,
+ [4248] = 4,
+ [4249] = 25,
+ [4250] = 5,
+ [4251] = 26,
+ [4252] = 6,
+ [4253] = 27,
+ [4254] = 7,
+ [4255] = 28,
+ [4256] = 8,
+ [4257] = 29,
+ [4258] = 9,
+ [4259] = 30,
+ [4260] = 10,
+ [4261] = 31,
+ [4262] = 11,
+ [4263] = 32,
+ [4298] = 12,
+ [4300] = 13,
+ [4302] = 14,
+ [4304] = 15,
+ [4318] = 16,
+ [4319] = 17,
+ [4320] = 18,
+ [4321] = 19,
[4352] = 0,
[4353] = 1,
- [4354] = 2,
- [4356] = 3,
- [4358] = 4,
- [4392] = 8,
- [4394] = 9,
- [4396] = 10,
- [4398] = 11,
- [4400] = 12,
- [4402] = 13,
- [4404] = 14,
- [4406] = 15,
- [4434] = 5,
- [4438] = 6,
- [4442] = 7,
+ [4355] = 20,
+ [4357] = 21,
+ [4359] = 22,
+ [4372] = 2,
+ [4373] = 23,
+ [4374] = 3,
+ [4375] = 24,
+ [4376] = 4,
+ [4377] = 25,
+ [4378] = 5,
+ [4379] = 26,
+ [4380] = 6,
+ [4381] = 27,
+ [4382] = 7,
+ [4383] = 28,
+ [4384] = 8,
+ [4385] = 29,
+ [4386] = 9,
+ [4387] = 30,
+ [4388] = 10,
+ [4389] = 31,
+ [4390] = 11,
+ [4391] = 32,
+ [4409] = 33,
+ [4411] = 34,
+ [4413] = 35,
+ [4415] = 36,
+ [4417] = 37,
+ [4419] = 38,
+ [4421] = 39,
+ [4423] = 40,
+ [4425] = 41,
+ [4426] = 12,
+ [4428] = 13,
+ [4430] = 14,
+ [4432] = 15,
+ [4446] = 16,
+ [4447] = 17,
+ [4448] = 18,
+ [4449] = 19,
[4480] = 0,
[4481] = 1,
- [4482] = 2,
- [4484] = 3,
- [4486] = 4,
- [4500] = 8,
- [4502] = 9,
- [4504] = 10,
- [4506] = 11,
- [4508] = 12,
- [4510] = 13,
- [4512] = 14,
- [4514] = 15,
- [4516] = 16,
- [4518] = 17,
- [4562] = 5,
- [4566] = 6,
- [4570] = 7,
+ [4483] = 20,
+ [4485] = 21,
+ [4487] = 22,
+ [4500] = 2,
+ [4501] = 23,
+ [4502] = 3,
+ [4503] = 24,
+ [4504] = 4,
+ [4505] = 25,
+ [4506] = 5,
+ [4507] = 26,
+ [4508] = 6,
+ [4509] = 27,
+ [4510] = 7,
+ [4511] = 28,
+ [4512] = 8,
+ [4513] = 29,
+ [4514] = 9,
+ [4515] = 30,
+ [4516] = 10,
+ [4517] = 31,
+ [4518] = 11,
+ [4519] = 32,
+ [4554] = 12,
+ [4555] = 33,
+ [4556] = 13,
+ [4557] = 34,
+ [4558] = 14,
+ [4559] = 35,
+ [4560] = 15,
+ [4561] = 36,
+ [4574] = 16,
+ [4575] = 17,
+ [4576] = 18,
+ [4577] = 19,
[4608] = 0,
[4609] = 1,
- [4610] = 2,
- [4612] = 3,
- [4614] = 4,
- [4648] = 5,
- [4650] = 6,
- [4652] = 7,
- [4654] = 8,
- [4656] = 9,
- [4658] = 10,
- [4660] = 11,
- [4662] = 12,
- [4664] = 13,
- [4666] = 14,
- [4668] = 15,
- [4670] = 16,
- [4672] = 17,
- [4674] = 18,
- [4676] = 19,
- [4678] = 20,
- [4680] = 21,
- [4736] = 0,
- [4737] = 1,
- [4738] = 2,
- [4740] = 3,
- [4742] = 4,
- [4756] = 5,
- [4758] = 6,
- [4760] = 7,
- [4762] = 8,
- [4764] = 9,
- [4766] = 10,
- [4768] = 11,
- [4770] = 12,
- [4772] = 13,
- [4774] = 14,
- [4792] = 15,
- [4794] = 16,
- [4796] = 17,
- [4798] = 18,
- [4800] = 19,
- [4802] = 20,
- [4804] = 21,
- [4806] = 22,
- [4808] = 23,
- [4864] = 0,
- [4865] = 1,
- [4866] = 2,
- [4868] = 3,
- [4870] = 4,
- [4904] = 5,
- [4906] = 6,
- [4908] = 7,
- [4910] = 8,
- [4912] = 9,
- [4914] = 10,
- [4916] = 11,
- [4918] = 12,
- [4938] = 13,
- [4940] = 14,
- [4942] = 15,
- [4944] = 16,
- [4992] = 0,
- [4993] = 1,
- [4994] = 2,
- [4996] = 3,
- [4998] = 4,
- [5012] = 5,
- [5014] = 6,
- [5016] = 7,
- [5018] = 8,
- [5020] = 9,
- [5022] = 10,
- [5024] = 11,
- [5026] = 12,
- [5028] = 13,
- [5030] = 14,
- [5066] = 15,
- [5068] = 16,
- [5070] = 17,
- [5072] = 18,
- [5120] = 0,
- [5121] = 1,
- [5122] = 2,
- [5124] = 3,
- [5126] = 4,
- [5160] = 8,
- [5162] = 9,
- [5164] = 10,
- [5166] = 11,
- [5168] = 12,
- [5170] = 13,
- [5172] = 14,
- [5174] = 15,
- [5176] = 16,
- [5178] = 17,
- [5180] = 18,
- [5182] = 19,
- [5184] = 20,
- [5186] = 21,
- [5188] = 22,
- [5190] = 23,
- [5192] = 24,
- [5202] = 5,
- [5206] = 6,
- [5210] = 7,
- [5248] = 0,
- [5249] = 1,
- [5250] = 2,
- [5252] = 3,
- [5254] = 4,
- [5268] = 8,
- [5270] = 9,
- [5272] = 10,
- [5274] = 11,
- [5276] = 12,
- [5278] = 13,
- [5280] = 14,
- [5282] = 15,
- [5284] = 16,
- [5286] = 17,
- [5304] = 18,
- [5306] = 19,
- [5308] = 20,
- [5310] = 21,
- [5312] = 22,
- [5314] = 23,
- [5316] = 24,
- [5318] = 25,
- [5320] = 26,
- [5330] = 5,
- [5334] = 6,
- [5338] = 7,
- [5376] = 0,
- [5377] = 1,
- [5378] = 2,
- [5380] = 3,
- [5382] = 4,
- [5416] = 8,
- [5418] = 9,
- [5420] = 10,
- [5422] = 11,
- [5424] = 12,
- [5426] = 13,
- [5428] = 14,
- [5430] = 15,
- [5450] = 16,
- [5452] = 17,
- [5454] = 18,
- [5456] = 19,
- [5458] = 5,
- [5462] = 6,
- [5466] = 7,
- [5504] = 0,
- [5505] = 1,
- [5506] = 2,
- [5508] = 3,
- [5510] = 4,
- [5524] = 8,
- [5526] = 9,
- [5528] = 10,
- [5530] = 11,
- [5532] = 12,
- [5534] = 13,
- [5536] = 14,
- [5538] = 15,
- [5540] = 16,
- [5542] = 17,
- [5578] = 18,
- [5580] = 19,
- [5582] = 20,
- [5584] = 21,
- [5586] = 5,
- [5590] = 6,
- [5594] = 7
+ [4611] = 20,
+ [4613] = 21,
+ [4615] = 22,
+ [4619] = 33,
+ [4621] = 34,
+ [4623] = 35,
+ [4625] = 36,
+ [4627] = 37,
+ [4628] = 2,
+ [4629] = 23,
+ [4630] = 3,
+ [4631] = 24,
+ [4632] = 4,
+ [4633] = 25,
+ [4634] = 5,
+ [4635] = 26,
+ [4636] = 6,
+ [4637] = 27,
+ [4638] = 7,
+ [4639] = 28,
+ [4640] = 8,
+ [4641] = 29,
+ [4642] = 9,
+ [4643] = 30,
+ [4644] = 10,
+ [4645] = 31,
+ [4646] = 11,
+ [4647] = 32,
+ [4682] = 12,
+ [4684] = 13,
+ [4686] = 14,
+ [4688] = 15,
+ [4702] = 16,
+ [4703] = 17,
+ [4704] = 18,
+ [4705] = 19,
+ [6144] = 0,
+ [6145] = 1,
+ [6146] = 2,
+ [6148] = 3,
+ [6150] = 4,
+ [6184] = 5,
+ [6186] = 6,
+ [6188] = 7,
+ [6190] = 8,
+ [6192] = 9,
+ [6194] = 10,
+ [6196] = 11,
+ [6198] = 12,
+ [6272] = 0,
+ [6273] = 1,
+ [6274] = 2,
+ [6276] = 3,
+ [6278] = 4,
+ [6292] = 5,
+ [6294] = 6,
+ [6296] = 7,
+ [6298] = 8,
+ [6300] = 9,
+ [6302] = 10,
+ [6304] = 11,
+ [6306] = 12,
+ [6308] = 13,
+ [6310] = 14,
+ [6400] = 0,
+ [6401] = 1,
+ [6402] = 2,
+ [6404] = 3,
+ [6406] = 4,
+ [6440] = 8,
+ [6442] = 9,
+ [6444] = 10,
+ [6446] = 11,
+ [6448] = 12,
+ [6450] = 13,
+ [6452] = 14,
+ [6454] = 15,
+ [6482] = 5,
+ [6486] = 6,
+ [6490] = 7,
+ [6528] = 0,
+ [6529] = 1,
+ [6530] = 2,
+ [6532] = 3,
+ [6534] = 4,
+ [6548] = 8,
+ [6550] = 9,
+ [6552] = 10,
+ [6554] = 11,
+ [6556] = 12,
+ [6558] = 13,
+ [6560] = 14,
+ [6562] = 15,
+ [6564] = 16,
+ [6566] = 17,
+ [6610] = 5,
+ [6614] = 6,
+ [6618] = 7,
+ [6656] = 0,
+ [6657] = 1,
+ [6658] = 2,
+ [6660] = 3,
+ [6662] = 4,
+ [6696] = 5,
+ [6698] = 6,
+ [6700] = 7,
+ [6702] = 8,
+ [6704] = 9,
+ [6706] = 10,
+ [6708] = 11,
+ [6710] = 12,
+ [6712] = 13,
+ [6714] = 14,
+ [6716] = 15,
+ [6718] = 16,
+ [6720] = 17,
+ [6722] = 18,
+ [6724] = 19,
+ [6726] = 20,
+ [6728] = 21,
+ [6784] = 0,
+ [6785] = 1,
+ [6786] = 2,
+ [6788] = 3,
+ [6790] = 4,
+ [6804] = 5,
+ [6806] = 6,
+ [6808] = 7,
+ [6810] = 8,
+ [6812] = 9,
+ [6814] = 10,
+ [6816] = 11,
+ [6818] = 12,
+ [6820] = 13,
+ [6822] = 14,
+ [6840] = 15,
+ [6842] = 16,
+ [6844] = 17,
+ [6846] = 18,
+ [6848] = 19,
+ [6850] = 20,
+ [6852] = 21,
+ [6854] = 22,
+ [6856] = 23,
+ [6912] = 0,
+ [6913] = 1,
+ [6914] = 2,
+ [6916] = 3,
+ [6918] = 4,
+ [6952] = 5,
+ [6954] = 6,
+ [6956] = 7,
+ [6958] = 8,
+ [6960] = 9,
+ [6962] = 10,
+ [6964] = 11,
+ [6966] = 12,
+ [6986] = 13,
+ [6988] = 14,
+ [6990] = 15,
+ [6992] = 16,
+ [7040] = 0,
+ [7041] = 1,
+ [7042] = 2,
+ [7044] = 3,
+ [7046] = 4,
+ [7060] = 5,
+ [7062] = 6,
+ [7064] = 7,
+ [7066] = 8,
+ [7068] = 9,
+ [7070] = 10,
+ [7072] = 11,
+ [7074] = 12,
+ [7076] = 13,
+ [7078] = 14,
+ [7114] = 15,
+ [7116] = 16,
+ [7118] = 17,
+ [7120] = 18,
+ [7168] = 0,
+ [7169] = 1,
+ [7170] = 2,
+ [7172] = 3,
+ [7174] = 4,
+ [7208] = 8,
+ [7210] = 9,
+ [7212] = 10,
+ [7214] = 11,
+ [7216] = 12,
+ [7218] = 13,
+ [7220] = 14,
+ [7222] = 15,
+ [7224] = 16,
+ [7226] = 17,
+ [7228] = 18,
+ [7230] = 19,
+ [7232] = 20,
+ [7234] = 21,
+ [7236] = 22,
+ [7238] = 23,
+ [7240] = 24,
+ [7250] = 5,
+ [7254] = 6,
+ [7258] = 7,
+ [7296] = 0,
+ [7297] = 1,
+ [7298] = 2,
+ [7300] = 3,
+ [7302] = 4,
+ [7316] = 8,
+ [7318] = 9,
+ [7320] = 10,
+ [7322] = 11,
+ [7324] = 12,
+ [7326] = 13,
+ [7328] = 14,
+ [7330] = 15,
+ [7332] = 16,
+ [7334] = 17,
+ [7352] = 18,
+ [7354] = 19,
+ [7356] = 20,
+ [7358] = 21,
+ [7360] = 22,
+ [7362] = 23,
+ [7364] = 24,
+ [7366] = 25,
+ [7368] = 26,
+ [7378] = 5,
+ [7382] = 6,
+ [7386] = 7,
+ [7424] = 0,
+ [7425] = 1,
+ [7426] = 2,
+ [7428] = 3,
+ [7430] = 4,
+ [7464] = 8,
+ [7466] = 9,
+ [7468] = 10,
+ [7470] = 11,
+ [7472] = 12,
+ [7474] = 13,
+ [7476] = 14,
+ [7478] = 15,
+ [7498] = 16,
+ [7500] = 17,
+ [7502] = 18,
+ [7504] = 19,
+ [7506] = 5,
+ [7510] = 6,
+ [7514] = 7,
+ [7552] = 0,
+ [7553] = 1,
+ [7554] = 2,
+ [7556] = 3,
+ [7558] = 4,
+ [7572] = 8,
+ [7574] = 9,
+ [7576] = 10,
+ [7578] = 11,
+ [7580] = 12,
+ [7582] = 13,
+ [7584] = 14,
+ [7586] = 15,
+ [7588] = 16,
+ [7590] = 17,
+ [7626] = 18,
+ [7628] = 19,
+ [7630] = 20,
+ [7632] = 21,
+ [7634] = 5,
+ [7638] = 6,
+ [7642] = 7
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
index e342f340d9..d20c4197fa 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 13 18:15:56 2021 */
+/* date: Thu May 20 11:56:39 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -22,8 +22,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {
.cond_start_idx = 0,
.cond_nums = 4 }
},
- /* class_tid: 3, ingress */
- [3] = {
+ /* class_tid: 4, ingress */
+ [4] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
.num_tbls = 15,
.start_tbl_idx = 12,
@@ -32,8 +32,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {
.cond_start_idx = 8,
.cond_nums = 1 }
},
- /* class_tid: 4, egress */
- [4] = {
+ /* class_tid: 5, egress */
+ [5] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
.num_tbls = 6,
.start_tbl_idx = 27,
@@ -306,7 +306,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 38,
.result_num_fields = 5
},
- { /* class_tid: 3, , table: int_full_act_record.0 */
+ { /* class_tid: 4, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@@ -327,7 +327,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 128,
.result_num_fields = 17
},
- { /* class_tid: 3, , table: port_table.wr_0 */
+ { /* class_tid: 4, , table: port_table.wr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
@@ -350,7 +350,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 152,
.result_num_fields = 5
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
@@ -372,7 +372,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.ident_start_idx = 6,
.ident_nums = 0
},
- { /* class_tid: 3, , table: control.ing_0 */
+ { /* class_tid: 4, , table: control.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
@@ -385,7 +385,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
+ { /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.direction = TF_DIR_RX,
@@ -414,7 +414,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.ident_start_idx = 6,
.ident_nums = 1
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
@@ -437,7 +437,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */
+ { /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
.direction = TF_DIR_RX,
@@ -455,7 +455,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */
+ { /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
.direction = TF_DIR_RX,
@@ -473,7 +473,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 3, , table: control.egr_0 */
+ { /* class_tid: 4, , table: control.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
@@ -485,7 +485,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 3, , table: int_full_act_record.egr_0 */
+ { /* class_tid: 4, , table: int_full_act_record.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@@ -507,7 +507,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_num_fields = 17,
.encap_num_fields = 0
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
@@ -529,7 +529,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.ident_start_idx = 7,
.ident_nums = 0
},
- { /* class_tid: 3, , table: control.egr_1 */
+ { /* class_tid: 4, , table: control.egr_1 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
@@ -542,7 +542,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
+ { /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.direction = TF_DIR_TX,
@@ -569,7 +569,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.ident_start_idx = 7,
.ident_nums = 1
},
- { /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */
+ { /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
.direction = TF_DIR_TX,
@@ -587,7 +587,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */
+ { /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
.direction = TF_DIR_TX,
@@ -605,7 +605,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 4, , table: int_full_act_record.loopback */
+ { /* class_tid: 5, , table: int_full_act_record.loopback */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@@ -627,7 +627,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_num_fields = 17,
.encap_num_fields = 0
},
- { /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */
+ { /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
.direction = TF_DIR_TX,
@@ -645,7 +645,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */
+ { /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
.direction = TF_DIR_TX,
@@ -663,7 +663,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 4, , table: int_full_act_record.vf_ing */
+ { /* class_tid: 5, , table: int_full_act_record.vf_ing */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@@ -685,7 +685,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_num_fields = 17,
.encap_num_fields = 0
},
- { /* class_tid: 4, , table: vtag_encap_record.vfr_egr0 */
+ { /* class_tid: 5, , table: vtag_encap_record.vfr_egr0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
.resource_sub_type =
@@ -707,7 +707,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_num_fields = 0,
.encap_num_fields = 11
},
- { /* class_tid: 4, , table: int_full_act_record.vfr_egr0 */
+ { /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@@ -768,27 +768,27 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
.cond_operand = BNXT_ULP_CF_IDX_O_L4
},
- /* cond_reject: thor, class_tid: 3 */
+ /* cond_reject: thor, class_tid: 4 */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
},
- /* cond_execute: class_tid: 3, control.ing_0 */
+ /* cond_execute: class_tid: 4, control.ing_0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 3, control.egr_0 */
+ /* cond_execute: class_tid: 4, control.egr_0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
},
- /* cond_execute: class_tid: 3, control.egr_1 */
+ /* cond_execute: class_tid: 4, control.egr_1 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_reject: thor, class_tid: 4 */
+ /* cond_reject: thor, class_tid: 5 */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
@@ -3612,7 +3612,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
- /* class_tid: 3, , table: port_table.wr_0 */
+ /* class_tid: 4, , table: port_table.wr_0 */
{
.field_info_mask = {
.description = "dev.port_id",
@@ -3633,7 +3633,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
{
.field_info_mask = {
.description = "svif",
@@ -3653,7 +3653,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
.field_info_mask = {
.description = "etype",
@@ -3958,7 +3958,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
1}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
{
.field_info_mask = {
.description = "svif",
@@ -3978,7 +3978,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */
{
.field_info_mask = {
.description = "svif",
@@ -3998,7 +3998,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
.field_info_mask = {
.description = "etype",
@@ -5187,7 +5187,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 3, , table: int_full_act_record.0 */
+ /* class_tid: 4, , table: int_full_act_record.0 */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -5295,7 +5295,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 3, , table: port_table.wr_0 */
+ /* class_tid: 4, , table: port_table.wr_0 */
{
.description = "rid",
.field_bit_size = 32,
@@ -5329,7 +5329,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
- /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
.description = "prof_func_id",
.field_bit_size = 7,
@@ -5380,7 +5380,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -5414,7 +5414,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */
+ /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -5424,7 +5424,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
- /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */
+ /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -5434,7 +5434,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
- /* class_tid: 3, , table: int_full_act_record.egr_0 */
+ /* class_tid: 4, , table: int_full_act_record.egr_0 */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -5542,7 +5542,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
.description = "prof_func_id",
.field_bit_size = 7,
@@ -5593,7 +5593,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
},
- /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */
+ /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -5603,7 +5603,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */
+ /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -5613,7 +5613,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 4, , table: int_full_act_record.loopback */
+ /* class_tid: 5, , table: int_full_act_record.loopback */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -5721,7 +5721,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */
+ /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -5731,7 +5731,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
- /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */
+ /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -5741,7 +5741,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
- /* class_tid: 4, , table: int_full_act_record.vf_ing */
+ /* class_tid: 5, , table: int_full_act_record.vf_ing */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -5849,7 +5849,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 4, , table: vtag_encap_record.vfr_egr0 */
+ /* class_tid: 5, , table: vtag_encap_record.vfr_egr0 */
{
.description = "ecv_tun_type",
.field_bit_size = 3,
@@ -5929,7 +5929,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
},
- /* class_tid: 4, , table: int_full_act_record.vfr_egr0 */
+ /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -6085,7 +6085,7 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 29
},
- /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
.description = "l2_cntxt_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -6094,7 +6094,7 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 29
},
- /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
.description = "l2_cntxt_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
index b6d2afd55b..de924fe81a 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 13 18:15:56 2021 */
+/* date: Mon May 17 15:54:03 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
index 85b8950e49..7b6ee03a4b 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Fri May 14 10:26:31 2021 */
+/* date: Mon May 17 15:54:03 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -22,7 +22,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = {
.cond_start_idx = 0,
.cond_nums = 1 }
},
- /* class_tid: 2, egress */
+ /* class_tid: 2, ingress */
[2] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
.num_tbls = 15,
@@ -32,24 +32,34 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = {
.cond_start_idx = 24,
.cond_nums = 1 }
},
- /* class_tid: 3, ingress */
+ /* class_tid: 3, egress */
[3] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .num_tbls = 22,
+ .num_tbls = 15,
.start_tbl_idx = 33,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 30,
+ .cond_nums = 1 }
+ },
+ /* class_tid: 4, ingress */
+ [4] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 22,
+ .start_tbl_idx = 48,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 35,
+ .cond_start_idx = 41,
.cond_nums = 0 }
},
- /* class_tid: 4, egress */
- [4] = {
+ /* class_tid: 5, egress */
+ [5] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
.num_tbls = 19,
- .start_tbl_idx = 55,
+ .start_tbl_idx = 70,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 41,
+ .cond_start_idx = 47,
.cond_nums = 0 }
}
};
@@ -455,58 +465,133 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.result_bit_size = 64,
.result_num_fields = 9
},
- { /* class_tid: 2, , table: l2_cntxt_tcam_cache.rd */
+ { /* class_tid: 2, , table: tunnel_cache.rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 5,
+ .cond_true_goto = 1,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 25,
- .cond_nums = 1 },
+ .cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 223,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
+ .blob_key_bit_size = 16,
+ .key_bit_size = 16,
+ .key_num_fields = 2,
.ident_start_idx = 9,
.ident_nums = 1
},
+ { /* class_tid: 2, , table: control.tunnel_cache_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 25,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ { /* class_tid: 2, , table: l2_cntxt_tcam.1 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 26,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 225,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 127,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .ident_start_idx = 10,
+ .ident_nums = 1
+ },
+ { /* class_tid: 2, , table: tunnel_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 26,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 238,
+ .blob_key_bit_size = 16,
+ .key_bit_size = 16,
+ .key_num_fields = 2,
+ .result_start_idx = 140,
+ .result_bit_size = 52,
+ .result_num_fields = 3
+ },
+ { /* class_tid: 2, , table: control.flow_type_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 5,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 26,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
{ /* class_tid: 2, , table: mac_addr_cache.rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 26,
+ .cond_start_idx = 27,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 224,
+ .key_start_idx = 240,
.blob_key_bit_size = 73,
.key_bit_size = 73,
.key_num_fields = 5,
- .ident_start_idx = 10,
+ .ident_start_idx = 11,
.ident_nums = 1
},
- { /* class_tid: 2, , table: control.0 */
+ { /* class_tid: 2, , table: control.mac_addr_cache_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 3,
+ .cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 26,
+ .cond_start_idx = 27,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
@@ -515,12 +600,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
{ /* class_tid: 2, , table: l2_cntxt_tcam.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 27,
+ .cond_start_idx = 28,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
@@ -529,323 +614,236 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 229,
+ .key_start_idx = 245,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 127,
+ .result_start_idx = 143,
.result_bit_size = 64,
.result_num_fields = 13,
- .ident_start_idx = 11,
- .ident_nums = 1
+ .ident_start_idx = 12,
+ .ident_nums = 0
},
{ /* class_tid: 2, , table: mac_addr_cache.wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 27,
+ .cond_start_idx = 28,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 242,
+ .key_start_idx = 258,
.blob_key_bit_size = 73,
.key_bit_size = 73,
.key_num_fields = 5,
- .result_start_idx = 140,
+ .result_start_idx = 156,
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 2, , table: profile_tcam_cache.rd */
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 27,
+ .cond_start_idx = 28,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 247,
+ .key_start_idx = 263,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
.ident_start_idx = 12,
.ident_nums = 3
},
- { /* class_tid: 2, , table: control.gen_tbl_miss */
+ { /* class_tid: 2, , table: control.profile_tcam_cache.f2_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 2,
- .cond_false_goto = 1,
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 27,
+ .cond_start_idx = 28,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 2, , table: control.conflict_check */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 4,
- .cond_false_goto = 1023,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 28,
- .cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .func_info = {
- .func_opc = BNXT_ULP_FUNC_OPC_EQ,
- .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
- .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
- .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
- .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
- .func_dst_opr = BNXT_ULP_RF_IDX_CC },
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
- },
- { /* class_tid: 2, , table: profile_tcam.ipv4 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 2,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 29,
- .cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 250,
- .blob_key_bit_size = 81,
- .key_bit_size = 81,
- .key_num_fields = 43,
- .result_start_idx = 144,
- .result_bit_size = 38,
- .result_num_fields = 17,
- .ident_start_idx = 15,
- .ident_nums = 1
- },
- { /* class_tid: 2, , table: profile_tcam.ipv6 */
+ { /* class_tid: 2, , table: profile_tcam.f2 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 30,
+ .cond_start_idx = 29,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 1,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 293,
+ .key_start_idx = 266,
.blob_key_bit_size = 81,
.key_bit_size = 81,
.key_num_fields = 43,
- .result_start_idx = 161,
+ .result_start_idx = 160,
.result_bit_size = 38,
- .result_num_fields = 17,
- .ident_start_idx = 16,
- .ident_nums = 1
+ .result_num_fields = 17
},
- { /* class_tid: 2, , table: profile_tcam_cache.wr */
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 30,
+ .cond_start_idx = 29,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 336,
+ .key_start_idx = 309,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
- .result_start_idx = 178,
+ .result_start_idx = 177,
.result_bit_size = 122,
.result_num_fields = 5
},
- { /* class_tid: 2, , table: em.ipv4 */
+ { /* class_tid: 2, , table: em.tun */
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_MEM_INTERNAL,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 0,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 30,
- .cond_nums = 2 },
+ .cond_start_idx = 29,
+ .cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 339,
- .blob_key_bit_size = 176,
- .key_bit_size = 176,
- .key_num_fields = 10,
- .result_start_idx = 183,
+ .key_start_idx = 312,
+ .blob_key_bit_size = 112,
+ .key_bit_size = 112,
+ .key_num_fields = 8,
+ .result_start_idx = 182,
.result_bit_size = 64,
.result_num_fields = 9
},
- { /* class_tid: 2, , table: eem.ipv4 */
+ { /* class_tid: 2, , table: eem.tun */
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_MEM_EXTERNAL,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 0,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 32,
- .cond_nums = 2 },
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 30,
+ .cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 349,
+ .key_start_idx = 320,
.blob_key_bit_size = 448,
.key_bit_size = 448,
- .key_num_fields = 10,
- .result_start_idx = 192,
+ .key_num_fields = 8,
+ .result_start_idx = 191,
.result_bit_size = 64,
.result_num_fields = 9
},
- { /* class_tid: 2, , table: em.ipv6 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
- .resource_type = TF_MEM_INTERNAL,
+ { /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 0,
+ .cond_true_goto = 5,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 34,
+ .cond_start_idx = 31,
.cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 359,
- .blob_key_bit_size = 416,
- .key_bit_size = 416,
- .key_num_fields = 11,
- .result_start_idx = 201,
- .result_bit_size = 64,
- .result_num_fields = 9
+ .key_start_idx = 328,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 15,
+ .ident_nums = 1
},
- { /* class_tid: 2, , table: eem.ipv6 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
- .resource_type = TF_MEM_EXTERNAL,
+ { /* class_tid: 3, , table: mac_addr_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 0,
- .cond_false_goto = 0,
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 35,
+ .cond_start_idx = 32,
.cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 370,
- .blob_key_bit_size = 448,
- .key_bit_size = 448,
- .key_num_fields = 11,
- .result_start_idx = 210,
- .result_bit_size = 64,
- .result_num_fields = 9
+ .key_start_idx = 329,
+ .blob_key_bit_size = 73,
+ .key_bit_size = 73,
+ .key_num_fields = 5,
+ .ident_start_idx = 16,
+ .ident_nums = 1
},
- { /* class_tid: 3, , table: int_full_act_record.ing_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 35,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 219,
- .result_bit_size = 128,
- .result_num_fields = 26
- },
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 35,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 381,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .ident_start_idx = 17,
- .ident_nums = 0
- },
- { /* class_tid: 3, , table: control.ing_0 */
+ { /* class_tid: 3, , table: control.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_RX,
+ .direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 3,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 35,
+ .cond_start_idx = 32,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
+ { /* class_tid: 3, , table: l2_cntxt_tcam.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .direction = TF_DIR_RX,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 36,
+ .cond_start_idx = 33,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
@@ -853,361 +851,240 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 382,
+ .key_start_idx = 334,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 245,
+ .result_start_idx = 200,
.result_bit_size = 64,
.result_num_fields = 13,
.ident_start_idx = 17,
.ident_nums = 1
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */
+ { /* class_tid: 3, , table: mac_addr_cache.wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
- .direction = TF_DIR_RX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
+ .direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 36,
+ .cond_start_idx = 33,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 395,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .result_start_idx = 258,
+ .key_start_idx = 347,
+ .blob_key_bit_size = 73,
+ .key_bit_size = 73,
+ .key_num_fields = 5,
+ .result_start_idx = 213,
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 3, , table: parif_def_lkup_arec_ptr.ing_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 36,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 262,
- .result_bit_size = 32,
- .result_num_fields = 1
- },
- { /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
- .direction = TF_DIR_RX,
+ { /* class_tid: 3, , table: profile_tcam_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 36,
+ .cond_start_idx = 33,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 263,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .key_start_idx = 352,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .ident_start_idx = 18,
+ .ident_nums = 3
},
- { /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
- .direction = TF_DIR_RX,
+ { /* class_tid: 3, , table: control.gen_tbl_miss */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 2,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 36,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 264,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 33,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 3, , table: control.egr_0 */
+ { /* class_tid: 3, , table: control.conflict_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_RX,
+ .direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 6,
+ .cond_true_goto = 4,
+ .cond_false_goto = 1023,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 36,
+ .cond_start_idx = 34,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .func_info = {
+ .func_opc = BNXT_ULP_FUNC_OPC_EQ,
+ .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
+ .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
+ .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC },
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 3, , table: int_full_act_record.egr_vfr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 37,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 265,
- .result_bit_size = 128,
- .result_num_fields = 26,
- .encap_num_fields = 0
- },
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd_vfr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ { /* class_tid: 3, , table: profile_tcam.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 2,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 37,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 396,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .ident_start_idx = 18,
- .ident_nums = 0
- },
- { /* class_tid: 3, , table: control.egr_1 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 37,
+ .cond_start_idx = 35,
.cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 355,
+ .blob_key_bit_size = 81,
+ .key_bit_size = 81,
+ .key_num_fields = 43,
+ .result_start_idx = 217,
+ .result_bit_size = 38,
+ .result_num_fields = 17,
+ .ident_start_idx = 21,
+ .ident_nums = 1
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_bypass.egr_vfr */
+ { /* class_tid: 3, , table: profile_tcam.ipv6 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 38,
+ .cond_start_idx = 36,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
- .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 397,
- .blob_key_bit_size = 167,
- .key_bit_size = 167,
- .key_num_fields = 13,
- .result_start_idx = 291,
- .result_bit_size = 64,
- .result_num_fields = 13,
- .ident_start_idx = 18,
- .ident_nums = 0
+ .key_start_idx = 398,
+ .blob_key_bit_size = 81,
+ .key_bit_size = 81,
+ .key_num_fields = 43,
+ .result_start_idx = 234,
+ .result_bit_size = 38,
+ .result_num_fields = 17,
+ .ident_start_idx = 22,
+ .ident_nums = 1
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
+ { /* class_tid: 3, , table: profile_tcam_cache.wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 0,
+ .cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 38,
+ .cond_start_idx = 36,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 410,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .result_start_idx = 304,
- .result_bit_size = 62,
- .result_num_fields = 4
+ .key_start_idx = 441,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .result_start_idx = 251,
+ .result_bit_size = 122,
+ .result_num_fields = 5
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ { /* class_tid: 3, , table: em.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_INTERNAL,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 38,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 36,
+ .cond_nums = 2 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 411,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .ident_start_idx = 18,
- .ident_nums = 0
- },
- { /* class_tid: 3, , table: control.egr_2 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 3,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 38,
- .cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
- },
- { /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 39,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 412,
- .blob_key_bit_size = 167,
- .key_bit_size = 167,
- .key_num_fields = 13,
- .result_start_idx = 308,
+ .key_start_idx = 444,
+ .blob_key_bit_size = 176,
+ .key_bit_size = 176,
+ .key_num_fields = 10,
+ .result_start_idx = 256,
.result_bit_size = 64,
- .result_num_fields = 13,
- .ident_start_idx = 18,
- .ident_nums = 1
+ .result_num_fields = 9
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ { /* class_tid: 3, , table: eem.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_EXTERNAL,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 39,
+ .cond_start_idx = 38,
.cond_nums = 2 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 425,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .result_start_idx = 321,
- .result_bit_size = 62,
- .result_num_fields = 4
- },
- { /* class_tid: 3, , table: int_full_act_record.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 41,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 325,
- .result_bit_size = 128,
- .result_num_fields = 26,
- .encap_num_fields = 0
- },
- { /* class_tid: 3, , table: parif_def_lkup_arec_ptr.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 41,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 351,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .key_start_idx = 454,
+ .blob_key_bit_size = 448,
+ .key_bit_size = 448,
+ .key_num_fields = 10,
+ .result_start_idx = 265,
+ .result_bit_size = 64,
+ .result_num_fields = 9
},
- { /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+ { /* class_tid: 3, , table: em.ipv6 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_INTERNAL,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 41,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 40,
+ .cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 352,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .key_start_idx = 464,
+ .blob_key_bit_size = 416,
+ .key_bit_size = 416,
+ .key_num_fields = 11,
+ .result_start_idx = 274,
+ .result_bit_size = 64,
+ .result_num_fields = 9
},
- { /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
+ { /* class_tid: 3, , table: eem.ipv6 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_EXTERNAL,
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 0,
@@ -1215,41 +1092,44 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 41,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 353,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .key_start_idx = 475,
+ .blob_key_bit_size = 448,
+ .key_bit_size = 448,
+ .key_num_fields = 11,
+ .result_start_idx = 283,
+ .result_bit_size = 64,
+ .result_num_fields = 9
},
- { /* class_tid: 4, , table: int_full_act_record.loopback */
+ { /* class_tid: 4, , table: int_full_act_record.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 41,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE,
- .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 354,
+ .result_start_idx = 292,
.result_bit_size = 128,
- .result_num_fields = 26,
- .encap_num_fields = 0
+ .result_num_fields = 26
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_rd_egr */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
@@ -1260,16 +1140,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 426,
+ .key_start_idx = 486,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .ident_start_idx = 19,
+ .ident_start_idx = 23,
.ident_nums = 0
},
- { /* class_tid: 4, , table: control.vf_0 */
+ { /* class_tid: 4, , table: control.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 3,
@@ -1280,10 +1160,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */
+ { /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
@@ -1296,22 +1176,24 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 427,
+ .key_start_idx = 487,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 380,
+ .result_start_idx = 318,
.result_bit_size = 64,
.result_num_fields = 13,
- .ident_start_idx = 19,
+ .ident_start_idx = 23,
.ident_nums = 1
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
@@ -1322,119 +1204,103 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 440,
+ .key_start_idx = 500,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .result_start_idx = 393,
+ .result_start_idx = 331,
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 4, , table: parif_def_lkup_arec_ptr.vf_egr */
+ { /* class_tid: 4, , table: parif_def_lkup_arec_ptr.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 42,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
- .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 397,
+ .result_start_idx = 335,
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */
+ { /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 42,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
- .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 398,
+ .result_start_idx = 336,
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */
+ { /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 42,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
- .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 399,
+ .result_start_idx = 337,
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 4, , table: int_full_act_record.vf_ing */
+ { /* class_tid: 4, , table: control.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 6,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 42,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ { /* class_tid: 4, , table: int_full_act_record.egr_vfr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_RX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 400,
+ .result_start_idx = 338,
.result_bit_size = 128,
.result_num_fields = 26,
.encap_num_fields = 0
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vf_ing */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
- .pri_operand = 0,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 441,
- .blob_key_bit_size = 167,
- .key_bit_size = 167,
- .key_num_fields = 13,
- .result_start_idx = 426,
- .result_bit_size = 64,
- .result_num_fields = 13,
- .ident_start_idx = 20,
- .ident_nums = 0
- },
- { /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_rd_egr0 */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd_vfr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
@@ -1443,33 +1309,33 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 454,
+ .key_start_idx = 501,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .ident_start_idx = 20,
+ .ident_start_idx = 24,
.ident_nums = 0
},
- { /* class_tid: 4, , table: control.vfr_0 */
+ { /* class_tid: 4, , table: control.egr_1 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 3,
+ .cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_egr0 */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.egr_vfr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.direction = TF_DIR_TX,
@@ -1477,7 +1343,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 43,
+ .cond_start_idx = 44,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
@@ -1486,140 +1352,392 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 455,
+ .key_start_idx = 502,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 439,
+ .result_start_idx = 364,
.result_bit_size = 64,
.result_num_fields = 13,
- .ident_start_idx = 20,
+ .ident_start_idx = 24,
.ident_nums = 0
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 43,
+ .cond_start_idx = 44,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 468,
+ .key_start_idx = 515,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .result_start_idx = 452,
+ .result_start_idx = 377,
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 4, , table: int_vtag_encap_record.vfr_egr0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 43,
+ .cond_start_idx = 44,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 456,
- .result_bit_size = 0,
- .result_num_fields = 0,
- .encap_num_fields = 12
+ .key_start_idx = 516,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 24,
+ .ident_nums = 0
},
- { /* class_tid: 4, , table: int_full_act_record.vfr_egr0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
- .execute_info = {
+ { /* class_tid: 4, , table: control.egr_2 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 44,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .direction = TF_DIR_TX,
+ .execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 43,
+ .cond_start_idx = 45,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 517,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 381,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .ident_start_idx = 24,
+ .ident_nums = 1
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 45,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 530,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 394,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 4, , table: int_full_act_record.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 47,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 468,
+ .result_start_idx = 398,
.result_bit_size = 128,
- .result_num_fields = 26
+ .result_num_fields = 26,
+ .encap_num_fields = 0
+ },
+ { /* class_tid: 4, , table: parif_def_lkup_arec_ptr.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 47,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 424,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 47,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 425,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 47,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 426,
+ .result_bit_size = 32,
+ .result_num_fields = 1
},
- { /* class_tid: 4, , table: int_full_act_record.vfr_ing0 */
+ { /* class_tid: 5, , table: int_full_act_record.loopback */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_RX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 43,
+ .cond_start_idx = 47,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 494,
+ .result_start_idx = 427,
.result_bit_size = 128,
- .result_num_fields = 26
+ .result_num_fields = 26,
+ .encap_num_fields = 0
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 47,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 531,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 25,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: control.vf_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 47,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */
+ { /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .direction = TF_DIR_RX,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 43,
+ .cond_start_idx = 48,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 469,
+ .key_start_idx = 532,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 520,
+ .result_start_idx = 453,
.result_bit_size = 64,
.result_num_fields = 13,
- .ident_start_idx = 20,
- .ident_nums = 0
+ .ident_start_idx = 25,
+ .ident_nums = 1
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 545,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 466,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 5, , table: parif_def_lkup_arec_ptr.vf_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
+ .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 470,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
+ .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 471,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
+ .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 472,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 5, , table: int_full_act_record.vf_ing */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 473,
+ .result_bit_size = 128,
+ .result_num_fields = 26,
+ .encap_num_fields = 0
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */
+ { /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vf_ing */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
.direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 0,
- .cond_false_goto = 0,
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 43,
+ .cond_start_idx = 48,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
@@ -1629,19 +1747,224 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 482,
+ .key_start_idx = 546,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 533,
+ .result_start_idx = 499,
.result_bit_size = 64,
.result_num_fields = 13,
- .ident_start_idx = 20,
+ .ident_start_idx = 26,
.ident_nums = 0
- }
-};
-
-struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_rd_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 559,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 26,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: control.vfr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 48,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 560,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 512,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .ident_start_idx = 26,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 573,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 525,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 5, , table: int_vtag_encap_record.vfr_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 529,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 12
+ },
+ { /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 541,
+ .result_bit_size = 128,
+ .result_num_fields = 26
+ },
+ { /* class_tid: 5, , table: int_full_act_record.vfr_ing0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 567,
+ .result_bit_size = 128,
+ .result_num_fields = 26
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 574,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 593,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .ident_start_idx = 26,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 587,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 606,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .ident_start_idx = 26,
+ .ident_nums = 0
+ }
+};
+
+struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {
/* cond_reject: wh_plus, class_tid: 1 */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
@@ -1751,32 +2074,61 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
.cond_operand = BNXT_ULP_CF_IDX_WC_MATCH
},
- /* cond_execute: class_tid: 2, l2_cntxt_tcam_cache.rd */
+ /* cond_execute: class_tid: 2, control.tunnel_cache_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 2, control.flow_type_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_F1
+ },
+ /* cond_execute: class_tid: 2, control.mac_addr_cache_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 2, control.profile_tcam_cache.f2_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 2, em.tun */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET,
+ },
+ /* cond_reject: wh_plus, class_tid: 3 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH
+ },
+ /* cond_execute: class_tid: 3, l2_cntxt_tcam_cache.rd */
{
.cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET,
.cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC
},
- /* cond_execute: class_tid: 2, control.0 */
+ /* cond_execute: class_tid: 3, control.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 2, control.gen_tbl_miss */
+ /* cond_execute: class_tid: 3, control.gen_tbl_miss */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 2, control.conflict_check */
+ /* cond_execute: class_tid: 3, control.conflict_check */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_CC
},
- /* cond_execute: class_tid: 2, profile_tcam.ipv4 */
+ /* cond_execute: class_tid: 3, profile_tcam.ipv4 */
{
.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
},
- /* cond_execute: class_tid: 2, em.ipv4 */
+ /* cond_execute: class_tid: 3, em.ipv4 */
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET,
},
@@ -1784,7 +2136,7 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
},
- /* cond_execute: class_tid: 2, eem.ipv4 */
+ /* cond_execute: class_tid: 3, eem.ipv4 */
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_IS_SET,
},
@@ -1792,31 +2144,31 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
},
- /* cond_execute: class_tid: 2, em.ipv6 */
+ /* cond_execute: class_tid: 3, em.ipv6 */
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET,
},
- /* cond_execute: class_tid: 3, control.ing_0 */
+ /* cond_execute: class_tid: 4, control.ing_0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 3, control.egr_0 */
+ /* cond_execute: class_tid: 4, control.egr_0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
},
- /* cond_execute: class_tid: 3, control.egr_1 */
+ /* cond_execute: class_tid: 4, control.egr_1 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 3, control.egr_2 */
+ /* cond_execute: class_tid: 4, control.egr_2 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 3, l2_cntxt_tcam_cache.egr_wr */
+ /* cond_execute: class_tid: 4, l2_cntxt_tcam_cache.egr_wr */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
@@ -1825,12 +2177,12 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 4, control.vf_0 */
+ /* cond_execute: class_tid: 5, control.vf_0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 4, control.vfr_0 */
+ /* cond_execute: class_tid: 5, control.vfr_0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
@@ -5669,7 +6021,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
}
},
- /* class_tid: 2, , table: l2_cntxt_tcam_cache.rd */
+ /* class_tid: 2, , table: tunnel_cache.rd */
{
.field_info_mask = {
.description = "svif",
@@ -5690,181 +6042,52 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
}
},
- /* class_tid: 2, , table: mac_addr_cache.rd */
{
.field_info_mask = {
- .description = "svif",
+ .description = "tunnel_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ 0xff}
},
.field_info_spec = {
- .description = "svif",
+ .description = "tunnel_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ (BNXT_ULP_CF_IDX_TUNNEL_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_TUNNEL_ID & 0xff}
}
},
+ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
{
.field_info_mask = {
- .description = "tun_hdr",
- .field_bit_size = 4,
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr",
- .field_bit_size = 4,
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "one_tag",
- .field_bit_size = 1,
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "one_tag",
- .field_bit_size = 1,
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
- }
- },
- {
- .field_info_mask = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
- },
- .field_info_spec = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
- }
- },
- /* class_tid: 2, , table: l2_cntxt_tcam.0 */
- {
- .field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -5872,19 +6095,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "mac0_addr",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "mac0_addr",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -5892,19 +6109,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "svif",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "svif",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -5968,18 +6179,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "l2_num_vtags",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l2_num_vtags",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -6046,7 +6252,47 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
1}
}
},
- /* class_tid: 2, , table: mac_addr_cache.wr */
+ /* class_tid: 2, , table: tunnel_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_TUNNEL_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_TUNNEL_ID & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: mac_addr_cache.rd */
{
.field_info_mask = {
.description = "svif",
@@ -6072,17 +6318,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "tun_hdr",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ 0xff}
},
.field_info_spec = {
.description = "tun_hdr",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -6090,60 +6334,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "one_tag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "one_tag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
.description = "vid",
.field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "vid",
.field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -6153,8 +6364,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
},
.field_info_spec = {
.description = "mac_addr",
@@ -6162,204 +6373,166 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
- /* class_tid: 2, , table: profile_tcam_cache.rd */
+ /* class_tid: 2, , table: l2_cntxt_tcam.0 */
{
.field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
+ .description = "mac0_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
+ .description = "mac0_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
- /* class_tid: 2, , table: profile_tcam.ipv4 */
{
.field_info_mask = {
- .description = "l4_hdr_is_udp_tcp",
- .field_bit_size = 1,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
},
.field_info_spec = {
- .description = "l4_hdr_is_udp_tcp",
- .field_bit_size = 1,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
}
},
{
.field_info_mask = {
- .description = "l4_hdr_type",
+ .description = "sparif",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l4_hdr_type",
+ .description = "sparif",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_WP_SYM_L4_HDR_TYPE_TCP},
- .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr3 = {
- ULP_WP_SYM_L4_HDR_TYPE_UDP}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4_hdr_error",
- .field_bit_size = 1,
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l4_hdr_error",
- .field_bit_size = 1,
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4_hdr_valid",
- .field_bit_size = 1,
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l4_hdr_valid",
- .field_bit_size = 1,
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_ipv6_cmp_dst",
- .field_bit_size = 1,
+ .description = "mac1_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_ipv6_cmp_dst",
- .field_bit_size = 1,
+ .description = "mac1_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_hdr_type",
+ .description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
@@ -6367,7 +6540,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "l3_hdr_type",
+ .description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6375,162 +6548,200 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "l3_hdr_error",
- .field_bit_size = 1,
+ .description = "key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_hdr_error",
- .field_bit_size = 1,
+ .description = "key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_hdr_valid",
+ .description = "valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 0xff}
+ 1}
},
.field_info_spec = {
- .description = "l3_hdr_valid",
+ .description = "valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ULP_WP_SYM_L3_HDR_VALID_YES}
+ 1}
}
},
+ /* class_tid: 2, , table: mac_addr_cache.wr */
{
.field_info_mask = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
+ .description = "tun_hdr",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_vtag_present",
+ .description = "one_tag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_vtag_present",
+ .description = "one_tag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_uc_mc_bc",
- .field_bit_size = 2,
+ .description = "vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_uc_mc_bc",
- .field_bit_size = 2,
+ .description = "vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_hdr_type",
- .field_bit_size = 2,
+ .description = "mac_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "l2_hdr_type",
- .field_bit_size = 2,
+ .description = "mac_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
+ /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
{
.field_info_mask = {
- .description = "l2_hdr_error",
- .field_bit_size = 1,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l2_hdr_error",
- .field_bit_size = 1,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_hdr_valid",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l2_hdr_valid",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- ULP_WP_SYM_L2_HDR_VALID_YES}
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "tun_hdr_flags",
- .field_bit_size = 3,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: profile_tcam.f2 */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_flags",
- .field_bit_size = 3,
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
+ .description = "l4_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_type",
+ .description = "l4_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6538,13 +6749,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tun_hdr_err",
+ .description = "l4_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_err",
+ .description = "l4_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6552,15 +6763,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tun_hdr_valid",
+ .description = "l4_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_valid",
+ .description = "l4_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6568,13 +6777,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl4_hdr_is_udp_tcp",
+ .description = "l3_ipv6_cmp_dst",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4_hdr_is_udp_tcp",
+ .description = "l3_ipv6_cmp_dst",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6582,27 +6791,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl4_hdr_type",
- .field_bit_size = 4,
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4_hdr_type",
- .field_bit_size = 4,
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4_hdr_error",
+ .description = "l3_hdr_isIP",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4_hdr_error",
+ .description = "l3_hdr_isIP",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6610,29 +6819,44 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl4_hdr_valid",
- .field_bit_size = 1,
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "tl4_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_WP_SYM_L3_HDR_TYPE_IPV4},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_WP_SYM_L3_HDR_TYPE_IPV6}
}
},
{
.field_info_mask = {
- .description = "tl3_ipv6_cmp_dst",
+ .description = "l3_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3_ipv6_cmp_dst",
+ .description = "l3_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6640,27 +6864,31 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl3_ipv6_cmp_src",
+ .description = "l3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3_ipv6_cmp_src",
+ .description = "l3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_L3_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl3_hdr_isIP",
+ .description = "l2_two_vtags",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3_hdr_isIP",
+ .description = "l2_two_vtags",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6668,57 +6896,55 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl3_hdr_type",
- .field_bit_size = 4,
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3_hdr_type",
- .field_bit_size = 4,
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3_hdr_error",
- .field_bit_size = 1,
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3_hdr_error",
- .field_bit_size = 1,
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3_hdr_valid",
- .field_bit_size = 1,
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3_hdr_valid",
- .field_bit_size = 1,
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_two_vtags",
+ .description = "l2_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_two_vtags",
+ .description = "l2_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6726,13 +6952,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl2_vtag_present",
+ .description = "l2_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_vtag_present",
+ .description = "l2_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6740,35 +6966,37 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl2_uc_mc_bc",
- .field_bit_size = 2,
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_uc_mc_bc",
- .field_bit_size = 2,
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_hdr_type",
- .field_bit_size = 2,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_hdr_type",
- .field_bit_size = 2,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_hdr_valid",
+ .description = "tun_hdr_err",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
@@ -6776,7 +7004,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "tl2_hdr_valid",
+ .description = "tun_hdr_err",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6784,68 +7012,65 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "hrec_next",
+ .description = "tun_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "hrec_next",
+ .description = "tun_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_TUN_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "reserved",
- .field_bit_size = 9,
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "reserved",
- .field_bit_size = 9,
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ ULP_WP_SYM_TL4_HDR_TYPE_UDP}
}
},
{
.field_info_mask = {
- .description = "agg_error",
+ .description = "tl4_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "agg_error",
+ .description = "tl4_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6853,159 +7078,137 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_TL4_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "pkt_type_0",
- .field_bit_size = 2,
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "pkt_type_0",
- .field_bit_size = 2,
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "pkt_type_1",
- .field_bit_size = 2,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "pkt_type_1",
- .field_bit_size = 2,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "valid",
+ .description = "tl3_hdr_isIP",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "valid",
+ .description = "tl3_hdr_isIP",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 2, , table: profile_tcam.ipv6 */
{
.field_info_mask = {
- .description = "l4_hdr_is_udp_tcp",
- .field_bit_size = 1,
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "l4_hdr_is_udp_tcp",
- .field_bit_size = 1,
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ 0xff}
},
.field_info_spec = {
- .description = "l4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_WP_SYM_L4_HDR_TYPE_TCP},
- .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr3 = {
- ULP_WP_SYM_L4_HDR_TYPE_UDP}
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4_hdr_error",
+ .description = "tl3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ 0xff}
},
.field_info_spec = {
- .description = "l4_hdr_error",
+ .description = "tl3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_TL3_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "l4_hdr_valid",
+ .description = "tl2_two_vtags",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l4_hdr_valid",
+ .description = "tl2_two_vtags",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_ipv6_cmp_dst",
+ .description = "tl2_vtag_present",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_ipv6_cmp_dst",
+ .description = "tl2_vtag_present",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -7013,61 +7216,61 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_hdr_type",
- .field_bit_size = 4,
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l3_hdr_type",
- .field_bit_size = 4,
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ULP_WP_SYM_L3_HDR_TYPE_IPV6}
+ ULP_WP_SYM_TL2_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "l3_hdr_error",
+ .description = "hrec_next",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_hdr_error",
+ .description = "hrec_next",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -7075,68 +7278,60 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "l3_hdr_valid",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_hdr_valid",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_L3_HDR_VALID_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "l2_vtag_present",
+ .description = "agg_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_vtag_present",
+ .description = "agg_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_uc_mc_bc",
+ .description = "recycle_cnt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_uc_mc_bc",
+ .description = "recycle_cnt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -7144,15 +7339,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "l2_hdr_type",
+ .description = "pkt_type_0",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_hdr_type",
+ .description = "pkt_type_0",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -7160,1487 +7353,1459 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "l2_hdr_error",
- .field_bit_size = 1,
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_hdr_error",
- .field_bit_size = 1,
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_hdr_valid",
+ .description = "valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 0xff}
+ 1}
},
.field_info_spec = {
- .description = "l2_hdr_valid",
+ .description = "valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ULP_WP_SYM_L2_HDR_VALID_YES}
+ 1}
}
},
+ /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
{
.field_info_mask = {
- .description = "tun_hdr_flags",
- .field_bit_size = 3,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tun_hdr_flags",
- .field_bit_size = 3,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "tun_hdr_err",
- .field_bit_size = 1,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tun_hdr_err",
- .field_bit_size = 1,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
}
},
+ /* class_tid: 2, , table: em.tun */
{
.field_info_mask = {
- .description = "tun_hdr_valid",
- .field_bit_size = 1,
+ .description = "spare",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_valid",
- .field_bit_size = 1,
+ .description = "spare",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4_hdr_is_udp_tcp",
- .field_bit_size = 1,
+ .description = "l2.ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4_hdr_is_udp_tcp",
- .field_bit_size = 1,
+ .description = "l2.ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2.dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "tl4_hdr_type",
- .field_bit_size = 4,
+ .description = "l2.dmac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl4_hdr_error",
- .field_bit_size = 1,
+ .description = "tun_id",
+ .field_bit_size = 24,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}
},
.field_info_spec = {
- .description = "tl4_hdr_error",
- .field_bit_size = 1,
+ .description = "tun_id",
+ .field_bit_size = 24,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl4_hdr_valid",
- .field_bit_size = 1,
+ .description = "tun_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4_hdr_valid",
- .field_bit_size = 1,
+ .description = "tun_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3_ipv6_cmp_dst",
- .field_bit_size = 1,
+ .description = "tun_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3_ipv6_cmp_dst",
- .field_bit_size = 1,
+ .description = "tun_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3_ipv6_cmp_src",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "tl3_ipv6_cmp_src",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl3_hdr_isIP",
- .field_bit_size = 1,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3_hdr_isIP",
- .field_bit_size = 1,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
}
},
+ /* class_tid: 2, , table: eem.tun */
{
.field_info_mask = {
- .description = "tl3_hdr_type",
- .field_bit_size = 4,
+ .description = "spare",
+ .field_bit_size = 339,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3_hdr_type",
- .field_bit_size = 4,
+ .description = "spare",
+ .field_bit_size = 339,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3_hdr_error",
- .field_bit_size = 1,
+ .description = "l2.ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3_hdr_error",
- .field_bit_size = 1,
+ .description = "l2.ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3_hdr_valid",
- .field_bit_size = 1,
+ .description = "l2.dmac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "tl3_hdr_valid",
- .field_bit_size = 1,
+ .description = "l2.dmac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl2_two_vtags",
- .field_bit_size = 1,
+ .description = "tun_id",
+ .field_bit_size = 24,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}
},
.field_info_spec = {
- .description = "tl2_two_vtags",
- .field_bit_size = 1,
+ .description = "tun_id",
+ .field_bit_size = 24,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl2_vtag_present",
- .field_bit_size = 1,
+ .description = "tun_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_vtag_present",
- .field_bit_size = 1,
+ .description = "tun_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_uc_mc_bc",
- .field_bit_size = 2,
+ .description = "tun_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_uc_mc_bc",
- .field_bit_size = 2,
+ .description = "tun_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_hdr_type",
- .field_bit_size = 2,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_hdr_type",
- .field_bit_size = 2,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl2_hdr_valid",
- .field_bit_size = 1,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "tl2_hdr_valid",
- .field_bit_size = 1,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
}
},
+ /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
{
.field_info_mask = {
- .description = "hrec_next",
- .field_bit_size = 1,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
},
.field_info_spec = {
- .description = "hrec_next",
- .field_bit_size = 1,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
}
},
+ /* class_tid: 3, , table: mac_addr_cache.rd */
{
.field_info_mask = {
- .description = "reserved",
- .field_bit_size = 9,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
},
.field_info_spec = {
- .description = "reserved",
- .field_bit_size = 9,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
}
},
{
.field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "tun_hdr",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 0xff}
+ ULP_WP_SYM_TUN_HDR_TYPE_NONE}
},
.field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ ULP_WP_SYM_TUN_HDR_TYPE_NONE}
}
},
{
.field_info_mask = {
- .description = "agg_error",
+ .description = "one_tag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "agg_error",
+ .description = "one_tag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
}
},
{
.field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "pkt_type_0",
- .field_bit_size = 2,
+ .description = "mac_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
},
.field_info_spec = {
- .description = "pkt_type_0",
- .field_bit_size = 2,
+ .description = "mac_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
}
},
+ /* class_tid: 3, , table: l2_cntxt_tcam.0 */
{
.field_info_mask = {
- .description = "pkt_type_1",
- .field_bit_size = 2,
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "pkt_type_1",
- .field_bit_size = 2,
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
+ .description = "mac0_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
},
.field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
+ .description = "mac0_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
}
},
- /* class_tid: 2, , table: profile_tcam_cache.wr */
{
.field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 0xff}
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
},
.field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
}
},
{
.field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "sparif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 2, , table: em.ipv4 */
{
.field_info_mask = {
- .description = "spare",
- .field_bit_size = 3,
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "spare",
- .field_bit_size = 3,
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "mac1_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "mac1_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4.dst",
- .field_bit_size = 16,
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff}
}
},
{
.field_info_mask = {
- .description = "l4.src",
- .field_bit_size = 16,
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3.prot",
- .field_bit_size = 8,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 0xff}
+ ULP_WP_SYM_TUN_HDR_TYPE_NONE}
},
.field_info_spec = {
- .description = "l3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ ULP_WP_SYM_TUN_HDR_TYPE_NONE}
}
},
{
.field_info_mask = {
- .description = "l3.dst",
- .field_bit_size = 32,
+ .description = "key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3.dst",
- .field_bit_size = 32,
+ .description = "key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3.src",
- .field_bit_size = 32,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ 1}
},
.field_info_spec = {
- .description = "l3.src",
- .field_bit_size = 32,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ 1}
}
},
+ /* class_tid: 3, , table: mac_addr_cache.wr */
{
.field_info_mask = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
},
.field_info_spec = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
}
},
{
.field_info_mask = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "tun_hdr",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 0xff,
- 0xff}
+ ULP_WP_SYM_TUN_HDR_TYPE_NONE}
},
.field_info_spec = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "tun_hdr",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ ULP_WP_SYM_TUN_HDR_TYPE_NONE}
}
},
{
.field_info_mask = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "one_tag",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "one_tag",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
}
},
- /* class_tid: 2, , table: eem.ipv4 */
{
.field_info_mask = {
- .description = "spare",
- .field_bit_size = 275,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "spare",
- .field_bit_size = 275,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "mac_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
},
.field_info_spec = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "mac_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
}
},
+ /* class_tid: 3, , table: profile_tcam_cache.rd */
{
.field_info_mask = {
- .description = "l4.dst",
- .field_bit_size = 16,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4.src",
- .field_bit_size = 16,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l4.src",
- .field_bit_size = 16,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "l3.prot",
- .field_bit_size = 8,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
}
},
+ /* class_tid: 3, , table: profile_tcam.ipv4 */
{
.field_info_mask = {
- .description = "l3.dst",
- .field_bit_size = 32,
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3.dst",
- .field_bit_size = 32,
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3.src",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3.src",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_WP_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_WP_SYM_L4_HDR_TYPE_UDP}
}
},
{
.field_info_mask = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
},
.field_info_spec = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 0xff,
- 0xff}
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
},
.field_info_spec = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
}
},
{
.field_info_mask = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 2, , table: em.ipv6 */
{
.field_info_mask = {
- .description = "spare",
- .field_bit_size = 3,
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "spare",
- .field_bit_size = 3,
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4.dst",
- .field_bit_size = 16,
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4.src",
- .field_bit_size = 16,
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3.prot",
- .field_bit_size = 8,
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ ULP_WP_SYM_L3_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "l3.dst",
- .field_bit_size = 128,
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ 0xff}
},
.field_info_spec = {
- .description = "l3.dst",
- .field_bit_size = 128,
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3.src",
- .field_bit_size = 128,
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ 0xff}
},
.field_info_spec = {
- .description = "l3.src",
- .field_bit_size = 128,
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
}
},
{
.field_info_mask = {
- .description = "l2.smac",
- .field_bit_size = 48,
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "l2.smac",
- .field_bit_size = 48,
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ 0xff}
},
.field_info_spec = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ ULP_WP_SYM_L2_HDR_VALID_YES}
}
},
- /* class_tid: 2, , table: eem.ipv6 */
{
.field_info_mask = {
- .description = "spare",
- .field_bit_size = 35,
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "spare",
- .field_bit_size = 35,
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4.dst",
- .field_bit_size = 16,
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l4.src",
- .field_bit_size = 16,
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3.prot",
- .field_bit_size = 8,
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l3.dst",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
- },
- .field_info_spec = {
- .description = "l3.dst",
- .field_bit_size = 128,
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3.src",
- .field_bit_size = 128,
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3.src",
- .field_bit_size = 128,
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2.smac",
- .field_bit_size = 48,
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2.smac",
- .field_bit_size = 48,
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l2_num_vtags",
+ .description = "tl2_hdr_type",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_num_vtags",
+ .description = "tl2_hdr_type",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -8648,491 +8813,511 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "hrec_next",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "hrec_next",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "reserved",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "reserved",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- .field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- }
- },
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */
- {
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd_vfr */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "agg_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "agg_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_bypass.egr_vfr */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 0xff}
+ 1}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ 1}
}
},
+ /* class_tid: 3, , table: profile_tcam.ipv6 */
{
.field_info_mask = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_WP_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_WP_SYM_L4_HDR_TYPE_UDP}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
},
.field_info_spec = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
},
.field_info_spec = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
}
},
{
.field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
+ .description = "l3_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tun_hdr_type",
+ .description = "l3_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_L3_HDR_TYPE_IPV6}
}
},
{
.field_info_mask = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "valid",
+ .description = "l3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 1}
+ 0xff}
},
.field_info_spec = {
- .description = "valid",
+ .description = "l3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ ULP_WP_SYM_L3_HDR_VALID_YES}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
- }
- },
- {
- .field_info_mask = {
- .description = "sparif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "sparif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ ULP_WP_SYM_L2_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
+ .description = "tl4_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_type",
+ .description = "tl4_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -9140,203 +9325,171 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "valid",
+ .description = "tl4_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 1}
+ 0xff}
},
.field_info_spec = {
- .description = "valid",
+ .description = "tl4_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_rd_egr */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "sparif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_num_vtags",
+ .description = "tl2_hdr_type",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_num_vtags",
+ .description = "tl2_hdr_type",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -9344,280 +9497,294 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "hrec_next",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "hrec_next",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "reserved",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "reserved",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 1}
+ 0xff}
},
.field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_egr_wr */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "agg_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "agg_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vf_ing */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 0xff}
+ 1}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ 1}
}
},
+ /* class_tid: 3, , table: profile_tcam_cache.wr */
{
.field_info_mask = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
}
},
+ /* class_tid: 3, , table: em.ipv4 */
{
.field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "spare",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "spare",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "local_cos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "local_cos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "l4.dst",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "l4.src",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "key_type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "key_type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- .field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_rd_egr0 */
{
.field_info_mask = {
- .description = "svif",
+ .description = "l3.prot",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
@@ -9625,211 +9792,305 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "svif",
+ .description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_egr0 */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l3.dst",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l3.dst",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l3.src",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l3.src",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
+ .description = "l2.dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "mac0_addr",
+ .description = "l2.dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
+ 0xff,
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
}
},
{
.field_info_mask = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
}
},
+ /* class_tid: 3, , table: eem.ipv4 */
{
.field_info_mask = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "spare",
+ .field_bit_size = 275,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "spare",
+ .field_bit_size = 275,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "local_cos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "local_cos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "l4.dst",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "l4.src",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "l3.prot",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "l3.dst",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
},
.field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "l3.dst",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
}
},
{
.field_info_mask = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "l3.src",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
},
.field_info_spec = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "l3.src",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
}
},
{
.field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
+ .description = "l2.dmac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
+ .description = "l2.dmac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
{
.field_info_mask = {
- .description = "svif",
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "em_profile_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
@@ -9837,34 +10098,48 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "svif",
+ .description = "em_profile_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */
+ /* class_tid: 3, , table: em.ipv6 */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "spare",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "spare",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "local_cos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "local_cos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
@@ -9872,32 +10147,48 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "l4.src",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "svif",
+ .description = "l3.prot",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
@@ -9905,154 +10196,314 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "svif",
+ .description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "l3.dst",
+ .field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
},
.field_info_spec = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "l3.dst",
+ .field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l3.src",
+ .field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
},
.field_info_spec = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l3.src",
+ .field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l2.smac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l2.smac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac1_addr",
+ .description = "l2.dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "mac1_addr",
+ .description = "l2.dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
{
.field_info_mask = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
+ 0xff,
0xff}
},
.field_info_spec = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- 2}
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
}
},
+ /* class_tid: 3, , table: eem.ipv6 */
{
.field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "spare",
+ .field_bit_size = 35,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "spare",
+ .field_bit_size = 35,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "local_cos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "local_cos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
+ .description = "l4.dst",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 1}
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 1}
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dst",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3.dst",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.src",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3.src",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2.smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2.smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2.dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2.dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
@@ -10060,13 +10511,67 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -10112,8 +10617,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
}
},
{
@@ -10177,17 +10682,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "l2_num_vtags",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l2_num_vtags",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -10249,529 +10750,2581 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.field_opr1 = {
1}
}
- }
-};
-
-struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
- /* class_tid: 1, , table: l2_cntxt_tcam.0 */
- {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
{
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ }
},
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd_vfr */
{
- .description = "l2_byp_lkup_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_bypass.egr_vfr */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vf_ing */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_rd_egr0 */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_egr0 */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 2}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ }
+};
+
+struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
+ /* class_tid: 1, , table: l2_cntxt_tcam.0 */
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}
+ },
+ {
+ .description = "l2_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ },
+ {
+ .description = "allowed_pri",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "default_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "allowed_tpid",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "default_tpid",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "bd_act_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "byp_sp_lkup",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "pri_anti_spoof_ctl",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tpid_anti_spoof_ctl",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: mac_addr_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.ipv4 */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.0",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_mask.1",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ },
+ {
+ .description = "em_key_mask.2",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ },
+ {
+ .description = "em_key_mask.3",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ },
+ {
+ .description = "em_key_mask.4",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}
+ },
+ {
+ .description = "em_key_mask.5",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}
+ },
+ {
+ .description = "em_key_mask.6",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}
+ },
+ {
+ .description = "em_key_mask.7",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.8",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.9",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.ipv6 */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.0",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_mask.1",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.2",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ },
+ {
+ .description = "em_key_mask.3",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
},
{
- .description = "parif",
+ .description = "em_key_mask.4",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ },
+ {
+ .description = "em_key_mask.5",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}
+ },
+ {
+ .description = "em_key_mask.6",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}
+ },
+ {
+ .description = "em_key_mask.7",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}
+ },
+ {
+ .description = "em_key_mask.8",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.9",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 7}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.ipv4_vxlan */
+ {
+ .description = "wc_key_id",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.0",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_mask.1",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.2",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.3",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.4",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_mask.5",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_mask.6",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_mask.7",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.8",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.9",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 20}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
+ /* class_tid: 1, , table: em.ipv4 */
{
- .description = "allowed_pri",
- .field_bit_size = 8,
+ .description = "act_rec_ptr",
+ .field_bit_size = 33,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "default_pri",
- .field_bit_size = 3,
+ .description = "ext_flow_cntr",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "allowed_tpid",
- .field_bit_size = 6,
+ .description = "act_rec_int",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "default_tpid",
- .field_bit_size = 3,
+ .description = "act_rec_size",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "bd_act_en",
- .field_bit_size = 1,
+ .description = "key_size",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
+ .description = "reserved",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "byp_sp_lkup",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ 3}
},
{
- .description = "pri_anti_spoof_ctl",
- .field_bit_size = 2,
+ .description = "l1_cacheable",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tpid_anti_spoof_ctl",
- .field_bit_size = 2,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
- /* class_tid: 1, , table: mac_addr_cache.wr */
+ /* class_tid: 1, , table: eem.ipv4 */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "act_rec_ptr",
+ .field_bit_size = 33,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "l2_cntxt_tcam_index",
- .field_bit_size = 10,
+ .description = "ext_flow_cntr",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "act_rec_int",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "act_rec_size",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "key_size",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ (173 >> 8) & 0xff,
+ 173 & 0xff}
},
- /* class_tid: 1, , table: profile_tcam.ipv4 */
{
- .description = "wc_key_id",
- .field_bit_size = 4,
+ .description = "reserved",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
},
{
- .description = "wc_search_en",
+ .description = "l1_cacheable",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.0",
+ .description = "valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 1, , table: em.ipv6 */
{
- .description = "em_key_mask.1",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 33,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "em_key_mask.2",
+ .description = "ext_flow_cntr",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.3",
+ .description = "act_rec_int",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.4",
- .field_bit_size = 1,
+ .description = "act_rec_size",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "key_size",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}
+ 3}
},
{
- .description = "em_key_mask.5",
+ .description = "l1_cacheable",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.6",
+ .description = "valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}
+ 1}
},
+ /* class_tid: 1, , table: eem.ipv6 */
{
- .description = "em_key_mask.7",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 33,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "em_key_mask.8",
+ .description = "ext_flow_cntr",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.9",
+ .description = "act_rec_int",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
+ .description = "act_rec_size",
.field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- 3}
+ (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "key_size",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ (413 >> 8) & 0xff,
+ 413 & 0xff}
},
{
- .description = "em_search_en",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ 3}
},
{
- .description = "pl_byp_lkup_en",
+ .description = "l1_cacheable",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam.ipv6 */
{
- .description = "wc_key_id",
- .field_bit_size = 4,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 1, , table: em.vxlan */
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "act_rec_ptr",
+ .field_bit_size = 33,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "wc_search_en",
+ .description = "ext_flow_cntr",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.0",
+ .description = "act_rec_int",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.1",
- .field_bit_size = 1,
+ .description = "act_rec_size",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.2",
- .field_bit_size = 1,
+ .description = "key_size",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.3",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.4",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ 3}
},
{
- .description = "em_key_mask.5",
+ .description = "l1_cacheable",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.6",
+ .description = "valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}
+ 1}
},
+ /* class_tid: 1, , table: eem.vxlan */
{
- .description = "em_key_mask.7",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .description = "act_rec_ptr",
+ .field_bit_size = 33,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "em_key_mask.8",
+ .description = "ext_flow_cntr",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.9",
+ .description = "act_rec_int",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
+ .description = "act_rec_size",
.field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 7}
- },
- {
- .description = "em_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}
},
{
- .description = "em_search_en",
- .field_bit_size = 1,
+ .description = "key_size",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
- },
- {
- .description = "pl_byp_lkup_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (197 >> 8) & 0xff,
+ 197 & 0xff}
},
- /* class_tid: 1, , table: profile_tcam.ipv4_vxlan */
{
- .description = "wc_key_id",
- .field_bit_size = 4,
+ .description = "reserved",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
},
{
- .description = "wc_search_en",
+ .description = "l1_cacheable",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.0",
+ .description = "valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
{
- .description = "em_key_mask.1",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.2",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.3",
+ .description = "l2_byp_lkup_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.4",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.5",
- .field_bit_size = 1,
+ .description = "allowed_pri",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.6",
- .field_bit_size = 1,
+ .description = "default_pri",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.7",
- .field_bit_size = 1,
+ .description = "allowed_tpid",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.8",
- .field_bit_size = 1,
+ .description = "default_tpid",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.9",
+ .description = "bd_act_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 20}
- },
- {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_search_en",
+ .description = "byp_sp_lkup",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -10779,12 +13332,18 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
1}
},
{
- .description = "pl_byp_lkup_en",
- .field_bit_size = 1,
+ .description = "pri_anti_spoof_ctl",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam_cache.wr */
+ {
+ .description = "tpid_anti_spoof_ctl",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 2, , table: tunnel_cache.wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -10795,299 +13354,303 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "profile_tcam_index",
+ .description = "l2_cntxt_tcam_index",
.field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
- },
- {
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
+ /* class_tid: 2, , table: l2_cntxt_tcam.0 */
{
- .description = "flow_sig_id",
- .field_bit_size = 64,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
- /* class_tid: 1, , table: em.ipv4 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 33,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
},
{
- .description = "ext_flow_cntr",
+ .description = "l2_byp_lkup_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "act_rec_int",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ },
+ {
+ .description = "allowed_pri",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "act_rec_size",
- .field_bit_size = 5,
+ .description = "default_pri",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "key_size",
- .field_bit_size = 9,
+ .description = "allowed_tpid",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "reserved",
- .field_bit_size = 11,
+ .description = "default_tpid",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "bd_act_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 3}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l1_cacheable",
- .field_bit_size = 1,
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "valid",
+ .description = "byp_sp_lkup",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
- /* class_tid: 1, , table: eem.ipv4 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 33,
+ .description = "pri_anti_spoof_ctl",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ext_flow_cntr",
- .field_bit_size = 1,
+ .description = "tpid_anti_spoof_ctl",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 2, , table: mac_addr_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
{
- .description = "act_rec_int",
- .field_bit_size = 1,
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "act_rec_size",
- .field_bit_size = 5,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,
- BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .description = "key_size",
- .field_bit_size = 9,
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- (173 >> 8) & 0xff,
- 173 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 2, , table: profile_tcam.f2 */
{
- .description = "reserved",
- .field_bit_size = 11,
+ .description = "wc_key_id",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 3}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l1_cacheable",
+ .description = "wc_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "valid",
+ .description = "em_key_mask.0",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
- /* class_tid: 1, , table: em.ipv6 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 33,
+ .description = "em_key_mask.1",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ 1}
},
{
- .description = "ext_flow_cntr",
+ .description = "em_key_mask.2",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "act_rec_int",
+ .description = "em_key_mask.3",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "act_rec_size",
- .field_bit_size = 5,
+ .description = "em_key_mask.4",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "key_size",
- .field_bit_size = 9,
+ .description = "em_key_mask.5",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "reserved",
- .field_bit_size = 11,
+ .description = "em_key_mask.6",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "em_key_mask.7",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 3}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l1_cacheable",
+ .description = "em_key_mask.8",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "valid",
+ .description = "em_key_mask.9",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ 8}
},
- /* class_tid: 1, , table: eem.ipv6 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 33,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
},
{
- .description = "ext_flow_cntr",
+ .description = "em_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "act_rec_int",
+ .description = "pl_byp_lkup_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
{
- .description = "act_rec_size",
- .field_bit_size = 5,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,
- BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "key_size",
- .field_bit_size = 9,
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (413 >> 8) & 0xff,
- 413 & 0xff}
- },
- {
- .description = "reserved",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- 3}
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
},
{
- .description = "l1_cacheable",
- .field_bit_size = 1,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "valid",
- .field_bit_size = 1,
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
- /* class_tid: 1, , table: em.vxlan */
+ /* class_tid: 2, , table: em.tun */
{
.description = "act_rec_ptr",
.field_bit_size = 33,
@@ -11149,7 +13712,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 1, , table: eem.vxlan */
+ /* class_tid: 2, , table: eem.tun */
{
.description = "act_rec_ptr",
.field_bit_size = 33,
@@ -11186,8 +13749,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (197 >> 8) & 0xff,
- 197 & 0xff}
+ (109 >> 8) & 0xff,
+ 109 & 0xff}
},
{
.description = "reserved",
@@ -11217,7 +13780,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 2, , table: l2_cntxt_tcam.0 */
+ /* class_tid: 3, , table: l2_cntxt_tcam.0 */
{
.description = "l2_cntxt_id",
.field_bit_size = 10,
@@ -11317,7 +13880,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: mac_addr_cache.wr */
+ /* class_tid: 3, , table: mac_addr_cache.wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -11351,7 +13914,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: profile_tcam.ipv4 */
+ /* class_tid: 3, , table: profile_tcam.ipv4 */
{
.description = "wc_key_id",
.field_bit_size = 4,
@@ -11497,7 +14060,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: profile_tcam.ipv6 */
+ /* class_tid: 3, , table: profile_tcam.ipv6 */
{
.description = "wc_key_id",
.field_bit_size = 4,
@@ -11643,7 +14206,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: profile_tcam_cache.wr */
+ /* class_tid: 3, , table: profile_tcam_cache.wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -11686,7 +14249,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
- /* class_tid: 2, , table: em.ipv4 */
+ /* class_tid: 3, , table: em.ipv4 */
{
.description = "act_rec_ptr",
.field_bit_size = 33,
@@ -11748,7 +14311,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 2, , table: eem.ipv4 */
+ /* class_tid: 3, , table: eem.ipv4 */
{
.description = "act_rec_ptr",
.field_bit_size = 33,
@@ -11816,7 +14379,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 2, , table: em.ipv6 */
+ /* class_tid: 3, , table: em.ipv6 */
{
.description = "act_rec_ptr",
.field_bit_size = 33,
@@ -11878,7 +14441,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 2, , table: eem.ipv6 */
+ /* class_tid: 3, , table: eem.ipv6 */
{
.description = "act_rec_ptr",
.field_bit_size = 33,
@@ -11946,7 +14509,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 3, , table: int_full_act_record.ing_0 */
+ /* class_tid: 4, , table: int_full_act_record.ing_0 */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -12106,7 +14669,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
.description = "l2_cntxt_id",
.field_bit_size = 10,
@@ -12196,7 +14759,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -12230,7 +14793,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: parif_def_lkup_arec_ptr.ing_0 */
+ /* class_tid: 4, , table: parif_def_lkup_arec_ptr.ing_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -12240,7 +14803,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */
+ /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -12250,7 +14813,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */
+ /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -12260,7 +14823,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 3, , table: int_full_act_record.egr_vfr */
+ /* class_tid: 4, , table: int_full_act_record.egr_vfr */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -12420,7 +14983,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: l2_cntxt_tcam_bypass.egr_vfr */
+ /* class_tid: 4, , table: l2_cntxt_tcam_bypass.egr_vfr */
{
.description = "act_record_ptr",
.field_bit_size = 16,
@@ -12508,7 +15071,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
{
.description = "rid",
.field_bit_size = 32,
@@ -12539,7 +15102,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
.description = "l2_cntxt_id",
.field_bit_size = 10,
@@ -12629,7 +15192,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -12663,7 +15226,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: int_full_act_record.egr_0 */
+ /* class_tid: 4, , table: int_full_act_record.egr_0 */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -12823,7 +15386,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: parif_def_lkup_arec_ptr.egr_0 */
+ /* class_tid: 4, , table: parif_def_lkup_arec_ptr.egr_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -12833,7 +15396,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */
+ /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -12843,7 +15406,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */
+ /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -12853,7 +15416,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 4, , table: int_full_act_record.loopback */
+ /* class_tid: 5, , table: int_full_act_record.loopback */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -13013,7 +15576,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
{
.description = "l2_cntxt_id",
.field_bit_size = 10,
@@ -13102,7 +15665,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -13136,7 +15699,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: parif_def_lkup_arec_ptr.vf_egr */
+ /* class_tid: 5, , table: parif_def_lkup_arec_ptr.vf_egr */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -13146,7 +15709,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
- /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */
+ /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -13156,7 +15719,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
- /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */
+ /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -13166,7 +15729,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
- /* class_tid: 4, , table: int_full_act_record.vf_ing */
+ /* class_tid: 5, , table: int_full_act_record.vf_ing */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -13326,7 +15889,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vf_ing */
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vf_ing */
{
.description = "act_record_ptr",
.field_bit_size = 16,
@@ -13412,7 +15975,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_egr0 */
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_egr0 */
{
.description = "act_record_ptr",
.field_bit_size = 16,
@@ -13497,7 +16060,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
{
.description = "rid",
.field_bit_size = 32,
@@ -13528,7 +16091,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: int_vtag_encap_record.vfr_egr0 */
+ /* class_tid: 5, , table: int_vtag_encap_record.vfr_egr0 */
{
.description = "ecv_tun_type",
.field_bit_size = 3,
@@ -13611,7 +16174,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: int_full_act_record.vfr_egr0 */
+ /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -13774,7 +16337,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: int_full_act_record.vfr_ing0 */
+ /* class_tid: 5, , table: int_full_act_record.vfr_ing0 */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -13936,7 +16499,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */
{
.description = "act_record_ptr",
.field_bit_size = 16,
@@ -14022,7 +16585,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */
{
.description = "act_record_ptr",
.field_bit_size = 16,
@@ -14180,13 +16743,22 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 8,
.ident_bit_pos = 28
},
- /* class_tid: 2, , table: l2_cntxt_tcam_cache.rd */
+ /* class_tid: 2, , table: tunnel_cache.rd */
{
.description = "l2_cntxt_id",
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 42
},
+ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
+ {
+ .description = "l2_cntxt_id",
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 0
+ },
/* class_tid: 2, , table: mac_addr_cache.rd */
{
.description = "l2_cntxt_id",
@@ -14194,7 +16766,40 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 42
},
- /* class_tid: 2, , table: l2_cntxt_tcam.0 */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
+ {
+ .description = "em_profile_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 42
+ },
+ {
+ .description = "flow_sig_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .ident_bit_size = 64,
+ .ident_bit_pos = 58
+ },
+ {
+ .description = "profile_tcam_index",
+ .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ {
+ .description = "l2_cntxt_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 42
+ },
+ /* class_tid: 3, , table: mac_addr_cache.rd */
+ {
+ .description = "l2_cntxt_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 42
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam.0 */
{
.description = "l2_cntxt_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -14203,7 +16808,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 0
},
- /* class_tid: 2, , table: profile_tcam_cache.rd */
+ /* class_tid: 3, , table: profile_tcam_cache.rd */
{
.description = "em_profile_id",
.regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
@@ -14222,7 +16827,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 32
},
- /* class_tid: 2, , table: profile_tcam.ipv4 */
+ /* class_tid: 3, , table: profile_tcam.ipv4 */
{
.description = "em_profile_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -14231,7 +16836,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 8,
.ident_bit_pos = 28
},
- /* class_tid: 2, , table: profile_tcam.ipv6 */
+ /* class_tid: 3, , table: profile_tcam.ipv6 */
{
.description = "em_profile_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -14240,7 +16845,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 8,
.ident_bit_pos = 28
},
- /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
.description = "l2_cntxt_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -14249,7 +16854,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 0
},
- /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
.description = "l2_cntxt_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -14258,7 +16863,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 0
},
- /* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
{
.description = "l2_cntxt_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
index 22c51976ac..73c31b98d9 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
@@ -413,11 +413,13 @@ static int ulp_get_single_flow_stat(struct bnxt_ulp_context *ctxt,
}
/* Update the parent counters if it is child flow */
- if (sw_acc_tbl_entry->parent_flow_id) {
+ if (sw_acc_tbl_entry->pc_flow_idx & FLOW_CNTR_PC_FLOW_VALID) {
+ uint32_t pc_idx;
+
/* Update the parent counters */
t_sw = sw_acc_tbl_entry;
- if (ulp_flow_db_parent_flow_count_update(ctxt,
- t_sw->parent_flow_id,
+ pc_idx = t_sw->pc_flow_idx & ~FLOW_CNTR_PC_FLOW_VALID;
+ if (ulp_flow_db_parent_flow_count_update(ctxt, pc_idx,
t_sw->pkt_count,
t_sw->byte_count)) {
PMD_DRV_LOG(ERR, "Error updating parent counters\n");
@@ -658,6 +660,7 @@ int32_t ulp_fc_mgr_cntr_reset(struct bnxt_ulp_context *ctxt, enum tf_dir dir,
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].hw_cntr_id = 0;
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].pkt_count = 0;
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].byte_count = 0;
+ ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].pc_flow_idx = 0;
ulp_fc_info->num_entries--;
pthread_mutex_unlock(&ulp_fc_info->fc_lock);
@@ -688,6 +691,8 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
uint32_t hw_cntr_id = 0, sw_cntr_idx = 0;
struct sw_acc_counter *sw_acc_tbl_entry;
bool found_cntr_resource = false;
+ bool found_parent_flow = false;
+ uint32_t pc_idx;
ulp_fc_info = bnxt_ulp_cntxt_ptr2_fc_info_get(ctxt);
if (!ulp_fc_info)
@@ -707,12 +712,16 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
(params.resource_sub_type ==
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT ||
params.resource_sub_type ==
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_EXT_COUNT ||
- params.resource_sub_type ==
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC)) {
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_EXT_COUNT)) {
found_cntr_resource = true;
break;
}
+ if (params.resource_func ==
+ BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW) {
+ found_parent_flow = true;
+ pc_idx = params.resource_hndl;
+ }
+
} while (!rc && nxt_resource_index);
bnxt_ulp_cntxt_release_fdb_lock(ctxt);
@@ -722,7 +731,8 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
dir = params.direction;
hw_cntr_id = params.resource_hndl;
- if (params.resource_sub_type ==
+ if (!found_parent_flow &&
+ params.resource_sub_type ==
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT) {
if (!ulp_fc_info->num_counters)
return ulp_fc_tf_flow_stat_get(ctxt, ¶ms, count);
@@ -745,14 +755,17 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
sw_acc_tbl_entry->byte_count = 0;
}
pthread_mutex_unlock(&ulp_fc_info->fc_lock);
- } else if (params.resource_sub_type ==
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC) {
+ } else if (found_parent_flow &&
+ params.resource_sub_type ==
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT) {
/* Get stats from the parent child table */
- ulp_flow_db_parent_flow_count_get(ctxt, flow_id,
+ ulp_flow_db_parent_flow_count_get(ctxt, pc_idx,
&count->hits, &count->bytes,
count->reset);
- count->hits_set = 1;
- count->bytes_set = 1;
+ if (count->hits)
+ count->hits_set = 1;
+ if (count->bytes)
+ count->bytes_set = 1;
} else {
/* TBD: Handle External counters */
rc = -EINVAL;
@@ -770,13 +783,13 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
*
* hw_cntr_id [in] The HW flow counter ID
*
- * fid [in] parent flow id
+ * pc_idx [in] parent child db index
*
*/
int32_t ulp_fc_mgr_cntr_parent_flow_set(struct bnxt_ulp_context *ctxt,
enum tf_dir dir,
uint32_t hw_cntr_id,
- uint32_t fid)
+ uint32_t pc_idx)
{
struct bnxt_ulp_fc_info *ulp_fc_info;
uint32_t sw_cntr_idx;
@@ -789,10 +802,11 @@ int32_t ulp_fc_mgr_cntr_parent_flow_set(struct bnxt_ulp_context *ctxt,
pthread_mutex_lock(&ulp_fc_info->fc_lock);
sw_cntr_idx = hw_cntr_id - ulp_fc_info->shadow_hw_tbl[dir].start_idx;
if (ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].valid) {
- ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].parent_flow_id = fid;
+ pc_idx |= FLOW_CNTR_PC_FLOW_VALID;
+ ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].pc_flow_idx = pc_idx;
} else {
BNXT_TF_DBG(ERR, "Failed to set parent flow id %x:%x\n",
- hw_cntr_id, fid);
+ hw_cntr_id, pc_idx);
rc = -ENOENT;
}
pthread_mutex_unlock(&ulp_fc_info->fc_lock);
diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
index 448d05c118..9825ed2a27 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
@@ -21,12 +21,14 @@
#define FLOW_CNTR_BYTES(v, d) (((v) & (d)->byte_count_mask) >> \
(d)->byte_count_shift)
+#define FLOW_CNTR_PC_FLOW_VALID 0x1000000
+
struct sw_acc_counter {
uint64_t pkt_count;
uint64_t byte_count;
bool valid;
uint32_t hw_cntr_id;
- uint32_t parent_flow_id;
+ uint32_t pc_flow_idx;
};
struct hw_fc_mem_info {
@@ -175,12 +177,12 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ulp_ctx,
*
* hw_cntr_id [in] The HW flow counter ID
*
- * fid [in] parent flow id
+ * pc_idx [in] parent child db index
*
*/
int32_t ulp_fc_mgr_cntr_parent_flow_set(struct bnxt_ulp_context *ctxt,
enum tf_dir dir,
uint32_t hw_cntr_id,
- uint32_t fid);
+ uint32_t pc_idx);
#endif /* _ULP_FC_MGR_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
index 747a360aa0..039c9c2a6b 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
@@ -386,101 +386,6 @@ ulp_flow_db_parent_tbl_deinit(struct bnxt_ulp_flow_db *flow_db)
}
}
-/* internal validation function for parent flow tbl */
-static struct bnxt_ulp_flow_db *
-ulp_flow_db_parent_arg_validation(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t fid)
-{
- struct bnxt_ulp_flow_db *flow_db;
-
- flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
- if (!flow_db) {
- BNXT_TF_DBG(ERR, "Invalid Arguments\n");
- return NULL;
- }
-
- /* check for max flows */
- if (fid >= flow_db->flow_tbl.num_flows || !fid) {
- BNXT_TF_DBG(ERR, "Invalid flow index\n");
- return NULL;
- }
-
- /* No support for parent child db then just exit */
- if (!flow_db->parent_child_db.entries_count) {
- BNXT_TF_DBG(ERR, "parent child db not supported\n");
- return NULL;
- }
-
- return flow_db;
-}
-
-/*
- * Set the tunnel index in the parent flow
- *
- * ulp_ctxt [in] Ptr to ulp_context
- * parent_idx [in] The parent index of the parent flow entry
- *
- * returns index on success and negative on failure.
- */
-static int32_t
-ulp_flow_db_parent_tun_idx_set(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_idx, uint8_t tun_idx)
-{
- struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
-
- flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
- if (!flow_db) {
- BNXT_TF_DBG(ERR, "Invalid Arguments\n");
- return -EINVAL;
- }
-
- /* check for parent idx validity */
- p_pdb = &flow_db->parent_child_db;
- if (parent_idx >= p_pdb->entries_count ||
- !p_pdb->parent_flow_tbl[parent_idx].parent_fid) {
- BNXT_TF_DBG(ERR, "Invalid parent flow index %x\n", parent_idx);
- return -EINVAL;
- }
-
- p_pdb->parent_flow_tbl[parent_idx].tun_idx = tun_idx;
- return 0;
-}
-
-/*
- * Get the tunnel index from the parent flow
- *
- * ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
- *
- * returns 0 if counter accum is set else -1.
- */
-static int32_t
-ulp_flow_db_parent_tun_idx_get(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid, uint8_t *tun_idx)
-{
- struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
- uint32_t idx;
-
- /* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
- if (!flow_db) {
- BNXT_TF_DBG(ERR, "parent child db validation failed\n");
- return -EINVAL;
- }
-
- p_pdb = &flow_db->parent_child_db;
- for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
- *tun_idx = p_pdb->parent_flow_tbl[idx].tun_idx;
- return 0;
- }
- }
-
- return -EINVAL;
-}
-
/*
* Initialize the flow database. Memory is allocated in this
* call and assigned to the flow database.
@@ -783,9 +688,6 @@ ulp_flow_db_resource_del(struct bnxt_ulp_context *ulp_ctxt,
struct bnxt_ulp_flow_tbl *flow_tbl;
struct ulp_fdb_resource_info *nxt_resource, *fid_resource;
uint32_t nxt_idx = 0;
- struct bnxt_tun_cache_entry *tun_tbl;
- uint8_t tun_idx = 0;
- int rc;
flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
if (!flow_db) {
@@ -862,18 +764,6 @@ ulp_flow_db_resource_del(struct bnxt_ulp_context *ulp_ctxt,
params->resource_hndl);
}
- if (params->resource_func == BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW) {
- tun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(ulp_ctxt);
- if (!tun_tbl)
- return -EINVAL;
-
- rc = ulp_flow_db_parent_tun_idx_get(ulp_ctxt, fid, &tun_idx);
- if (rc)
- return rc;
-
- ulp_clear_tun_entry(tun_tbl, tun_idx);
- }
-
/* all good, return success */
return 0;
}
@@ -892,7 +782,6 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt,
enum bnxt_ulp_fdb_type flow_type,
uint32_t fid)
{
- struct bnxt_tun_cache_entry *tun_tbl;
struct bnxt_ulp_flow_tbl *flow_tbl;
struct bnxt_ulp_flow_db *flow_db;
@@ -934,12 +823,6 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt,
if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR)
ulp_flow_db_func_id_set(flow_db, fid, 0);
- tun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(ulp_ctxt);
- if (!tun_tbl)
- return -EINVAL;
-
- ulp_clear_tun_inner_entry(tun_tbl, fid);
-
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
BNXT_TF_DBG(ERR, "flow_id = %u:%u freed\n", flow_type, fid);
#endif
@@ -1307,24 +1190,84 @@ ulp_default_flow_db_cfa_action_get(struct bnxt_ulp_context *ulp_ctx,
return 0;
}
+/* internal validation function for parent flow tbl */
+static struct ulp_fdb_parent_info *
+ulp_flow_db_pc_db_entry_get(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t pc_idx)
+{
+ struct bnxt_ulp_flow_db *flow_db;
+
+ flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
+ if (!flow_db) {
+ BNXT_TF_DBG(ERR, "Invalid Arguments\n");
+ return NULL;
+ }
+
+ /* check for max flows */
+ if (pc_idx >= BNXT_ULP_MAX_TUN_CACHE_ENTRIES) {
+ BNXT_TF_DBG(ERR, "Invalid tunnel index\n");
+ return NULL;
+ }
+
+ /* No support for parent child db then just exit */
+ if (!flow_db->parent_child_db.entries_count) {
+ BNXT_TF_DBG(ERR, "parent child db not supported\n");
+ return NULL;
+ }
+ if (!flow_db->parent_child_db.parent_flow_tbl[pc_idx].valid) {
+ BNXT_TF_DBG(ERR, "Not a valid tunnel index\n");
+ return NULL;
+ }
+
+ return &flow_db->parent_child_db.parent_flow_tbl[pc_idx];
+}
+
+/* internal validation function for parent flow tbl */
+static struct bnxt_ulp_flow_db *
+ulp_flow_db_parent_arg_validation(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t tun_idx)
+{
+ struct bnxt_ulp_flow_db *flow_db;
+
+ flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
+ if (!flow_db) {
+ BNXT_TF_DBG(ERR, "Invalid Arguments\n");
+ return NULL;
+ }
+
+ /* check for max flows */
+ if (tun_idx >= BNXT_ULP_MAX_TUN_CACHE_ENTRIES) {
+ BNXT_TF_DBG(ERR, "Invalid tunnel index\n");
+ return NULL;
+ }
+
+ /* No support for parent child db then just exit */
+ if (!flow_db->parent_child_db.entries_count) {
+ BNXT_TF_DBG(ERR, "parent child db not supported\n");
+ return NULL;
+ }
+
+ return flow_db;
+}
+
/*
* Allocate the entry in the parent-child database
*
* ulp_ctxt [in] Ptr to ulp_context
- * fid [in] The flow id to the flow entry
+ * tun_idx [in] The tunnel index of the flow entry
*
* returns index on success and negative on failure.
*/
-int32_t
-ulp_flow_db_parent_flow_alloc(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t fid)
+static int32_t
+ulp_flow_db_pc_db_idx_alloc(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t tun_idx)
{
struct bnxt_ulp_flow_db *flow_db;
struct ulp_fdb_parent_child_db *p_pdb;
uint32_t idx, free_idx = 0;
/* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, fid);
+ flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, tun_idx);
if (!flow_db) {
BNXT_TF_DBG(ERR, "parent child db validation failed\n");
return -EINVAL;
@@ -1332,11 +1275,11 @@ ulp_flow_db_parent_flow_alloc(struct bnxt_ulp_context *ulp_ctxt,
p_pdb = &flow_db->parent_child_db;
for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == fid) {
- BNXT_TF_DBG(ERR, "fid is already allocated\n");
- return -EINVAL;
+ if (p_pdb->parent_flow_tbl[idx].valid &&
+ p_pdb->parent_flow_tbl[idx].tun_idx == tun_idx) {
+ return idx;
}
- if (!p_pdb->parent_flow_tbl[idx].parent_fid && !free_idx)
+ if (!p_pdb->parent_flow_tbl[idx].valid && !free_idx)
free_idx = idx + 1;
}
/* no free slots */
@@ -1347,132 +1290,148 @@ ulp_flow_db_parent_flow_alloc(struct bnxt_ulp_context *ulp_ctxt,
free_idx -= 1;
/* set the Fid in the parent child */
- p_pdb->parent_flow_tbl[free_idx].parent_fid = fid;
+ p_pdb->parent_flow_tbl[free_idx].tun_idx = tun_idx;
+ p_pdb->parent_flow_tbl[free_idx].valid = 1;
return free_idx;
}
/*
* Free the entry in the parent-child database
*
- * ulp_ctxt [in] Ptr to ulp_context
- * fid [in] The flow id to the flow entry
+ * pc_entry [in] Ptr to parent child db entry
*
- * returns 0 on success and negative on failure.
+ * returns none.
*/
-int32_t
-ulp_flow_db_parent_flow_free(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t fid)
+static void
+ulp_flow_db_pc_db_entry_free(struct bnxt_ulp_context *ulp_ctxt,
+ struct ulp_fdb_parent_info *pc_entry)
{
+ struct bnxt_tun_cache_entry *tun_tbl;
struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
- uint32_t idx;
+ uint64_t *tmp_bitset;
- /* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, fid);
- if (!flow_db) {
- BNXT_TF_DBG(ERR, "parent child db validation failed\n");
- return -EINVAL;
- }
+ /* free the tunnel entry */
+ tun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(ulp_ctxt);
+ if (tun_tbl)
+ ulp_tunnel_offload_entry_clear(tun_tbl, pc_entry->tun_idx);
- p_pdb = &flow_db->parent_child_db;
- for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == fid) {
- /* free the contents */
- p_pdb->parent_flow_tbl[idx].parent_fid = 0;
- memset(p_pdb->parent_flow_tbl[idx].child_fid_bitset,
- 0, p_pdb->child_bitset_size);
- return 0;
- }
- }
- BNXT_TF_DBG(ERR, "parent entry not found = %x\n", fid);
- return -EINVAL;
+ /* free the child bitset*/
+ flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
+ if (flow_db)
+ memset(pc_entry->child_fid_bitset, 0,
+ flow_db->parent_child_db.child_bitset_size);
+
+ /* free the contents */
+ tmp_bitset = pc_entry->child_fid_bitset;
+ memset(pc_entry, 0, sizeof(struct ulp_fdb_parent_info));
+ pc_entry->child_fid_bitset = tmp_bitset;
}
/*
- * Set or reset the child flow in the parent-child database
+ * Set or reset the parent flow in the parent-child database
*
* ulp_ctxt [in] Ptr to ulp_context
+ * pc_idx [in] The index to parent child db
* parent_fid [in] The flow id of the parent flow entry
- * child_fid [in] The flow id of the child flow entry
* set_flag [in] Use 1 for setting child, 0 to reset
*
* returns zero on success and negative on failure.
*/
int32_t
-ulp_flow_db_parent_child_flow_set(struct bnxt_ulp_context *ulp_ctxt,
+ulp_flow_db_pc_db_parent_flow_set(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t pc_idx,
uint32_t parent_fid,
- uint32_t child_fid,
uint32_t set_flag)
{
+ struct ulp_fdb_parent_info *pc_entry;
struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
- uint32_t idx, a_idx;
- uint64_t *t;
- /* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
+ flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
if (!flow_db) {
BNXT_TF_DBG(ERR, "parent child db validation failed\n");
return -EINVAL;
}
/* check for fid validity */
- if (child_fid >= flow_db->flow_tbl.num_flows || !child_fid) {
- BNXT_TF_DBG(ERR, "Invalid child flow index %x\n", child_fid);
+ if (parent_fid >= flow_db->flow_tbl.num_flows || !parent_fid) {
+ BNXT_TF_DBG(ERR, "Invalid parent flow index %x\n", parent_fid);
return -EINVAL;
}
- p_pdb = &flow_db->parent_child_db;
- a_idx = child_fid / ULP_INDEX_BITMAP_SIZE;
- for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
- t = p_pdb->parent_flow_tbl[idx].child_fid_bitset;
- if (set_flag)
- ULP_INDEX_BITMAP_SET(t[a_idx], child_fid);
- else
- ULP_INDEX_BITMAP_RESET(t[a_idx], child_fid);
- return 0;
- }
+ /* validate the arguments and parent child entry */
+ pc_entry = ulp_flow_db_pc_db_entry_get(ulp_ctxt, pc_idx);
+ if (!pc_entry) {
+ BNXT_TF_DBG(ERR, "failed to get the parent child entry\n");
+ return -EINVAL;
}
- BNXT_TF_DBG(ERR, "Unable to set the parent-child flow %x:%x\n",
- parent_fid, child_fid);
- return -1;
+
+ if (set_flag) {
+ pc_entry->parent_fid = parent_fid;
+ } else {
+ if (pc_entry->parent_fid != parent_fid)
+ BNXT_TF_DBG(ERR, "Panic: invalid parent id\n");
+ pc_entry->parent_fid = 0;
+
+ /* Free the parent child db entry if no user present */
+ if (!pc_entry->f2_cnt)
+ ulp_flow_db_pc_db_entry_free(ulp_ctxt, pc_entry);
+ }
+ return 0;
}
/*
- * Get the parent index from the parent-child database
+ * Set or reset the child flow in the parent-child database
*
* ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
- * parent_idx [out] The parent index of parent flow entry
+ * pc_idx [in] The index to parent child db
+ * child_fid [in] The flow id of the child flow entry
+ * set_flag [in] Use 1 for setting child, 0 to reset
*
* returns zero on success and negative on failure.
*/
int32_t
-ulp_flow_db_parent_flow_idx_get(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid,
- uint32_t *parent_idx)
+ulp_flow_db_pc_db_child_flow_set(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t pc_idx,
+ uint32_t child_fid,
+ uint32_t set_flag)
{
+ struct ulp_fdb_parent_info *pc_entry;
struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
- uint32_t idx;
+ uint32_t a_idx;
+ uint64_t *t;
- /* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
+ flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
if (!flow_db) {
BNXT_TF_DBG(ERR, "parent child db validation failed\n");
return -EINVAL;
}
- p_pdb = &flow_db->parent_child_db;
- for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
- *parent_idx = idx;
- return 0;
- }
+ /* check for fid validity */
+ if (child_fid >= flow_db->flow_tbl.num_flows || !child_fid) {
+ BNXT_TF_DBG(ERR, "Invalid child flow index %x\n", child_fid);
+ return -EINVAL;
}
- BNXT_TF_DBG(ERR, "Unable to get the parent flow %x\n", parent_fid);
- return -1;
+
+ /* validate the arguments and parent child entry */
+ pc_entry = ulp_flow_db_pc_db_entry_get(ulp_ctxt, pc_idx);
+ if (!pc_entry) {
+ BNXT_TF_DBG(ERR, "failed to get the parent child entry\n");
+ return -EINVAL;
+ }
+
+ a_idx = child_fid / ULP_INDEX_BITMAP_SIZE;
+ t = pc_entry->child_fid_bitset;
+ if (set_flag) {
+ ULP_INDEX_BITMAP_SET(t[a_idx], child_fid);
+ pc_entry->f2_cnt++;
+ } else {
+ ULP_INDEX_BITMAP_RESET(t[a_idx], child_fid);
+ if (pc_entry->f2_cnt)
+ pc_entry->f2_cnt--;
+ if (!pc_entry->f2_cnt && !pc_entry->parent_fid)
+ ulp_flow_db_pc_db_entry_free(ulp_ctxt, pc_entry);
+ }
+ return 0;
}
/*
@@ -1541,13 +1500,13 @@ ulp_flow_db_parent_child_flow_next_entry_get(struct bnxt_ulp_flow_db *flow_db,
* Set the counter accumulation in the parent flow
*
* ulp_ctxt [in] Ptr to ulp_context
- * parent_idx [in] The parent index of the parent flow entry
+ * pc_idx [in] The parent child index of the parent flow entry
*
* returns index on success and negative on failure.
*/
static int32_t
ulp_flow_db_parent_flow_count_accum_set(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_idx)
+ uint32_t pc_idx)
{
struct bnxt_ulp_flow_db *flow_db;
struct ulp_fdb_parent_child_db *p_pdb;
@@ -1560,50 +1519,16 @@ ulp_flow_db_parent_flow_count_accum_set(struct bnxt_ulp_context *ulp_ctxt,
/* check for parent idx validity */
p_pdb = &flow_db->parent_child_db;
- if (parent_idx >= p_pdb->entries_count ||
- !p_pdb->parent_flow_tbl[parent_idx].parent_fid) {
- BNXT_TF_DBG(ERR, "Invalid parent flow index %x\n", parent_idx);
+ if (pc_idx >= p_pdb->entries_count ||
+ !p_pdb->parent_flow_tbl[pc_idx].parent_fid) {
+ BNXT_TF_DBG(ERR, "Invalid parent child index %x\n", pc_idx);
return -EINVAL;
}
- p_pdb->parent_flow_tbl[parent_idx].counter_acc = 1;
+ p_pdb->parent_flow_tbl[pc_idx].counter_acc = 1;
return 0;
}
-/*
- * Get the counter accumulation in the parent flow
- *
- * ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
- *
- * returns 0 if counter accum is set else -1.
- */
-static int32_t
-ulp_flow_db_parent_flow_count_accum_get(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid)
-{
- struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
- uint32_t idx;
-
- /* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
- if (!flow_db) {
- BNXT_TF_DBG(ERR, "parent child db validation failed\n");
- return -EINVAL;
- }
-
- p_pdb = &flow_db->parent_child_db;
- for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
- if (p_pdb->parent_flow_tbl[idx].counter_acc)
- return 0;
- break;
- }
- }
- return -1;
-}
-
/*
* Orphan the child flow entry
* This is called only for child flows that have
@@ -1677,22 +1602,30 @@ int32_t
ulp_flow_db_parent_flow_create(struct bnxt_ulp_mapper_parms *parms)
{
struct ulp_flow_db_res_params fid_parms;
- uint32_t sub_typ = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC;
+ uint32_t sub_typ = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT;
struct ulp_flow_db_res_params res_params;
- int32_t fid_idx, rc;
+ int32_t pc_idx;
- /* create the child flow entry in parent flow table */
- fid_idx = ulp_flow_db_parent_flow_alloc(parms->ulp_ctx, parms->fid);
- if (fid_idx < 0) {
- BNXT_TF_DBG(ERR, "Error in creating parent flow fid %x\n",
- parms->fid);
- return -1;
+ /* create or get the parent child database */
+ pc_idx = ulp_flow_db_pc_db_idx_alloc(parms->ulp_ctx, parms->tun_idx);
+ if (pc_idx < 0) {
+ BNXT_TF_DBG(ERR, "Error in getting parent child db %x\n",
+ parms->tun_idx);
+ return -EINVAL;
+ }
+
+ /* Update the parent fid */
+ if (ulp_flow_db_pc_db_parent_flow_set(parms->ulp_ctx, pc_idx,
+ parms->fid, 1)) {
+ BNXT_TF_DBG(ERR, "Error in setting parent fid %x\n",
+ parms->tun_idx);
+ return -EINVAL;
}
/* Add the parent details in the resource list of the flow */
memset(&fid_parms, 0, sizeof(fid_parms));
fid_parms.resource_func = BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW;
- fid_parms.resource_hndl = fid_idx;
+ fid_parms.resource_hndl = pc_idx;
fid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO;
if (ulp_flow_db_resource_add(parms->ulp_ctx, BNXT_ULP_FDB_TYPE_REGULAR,
parms->fid, &fid_parms)) {
@@ -1710,20 +1643,13 @@ ulp_flow_db_parent_flow_create(struct bnxt_ulp_mapper_parms *parms)
&res_params)) {
/* Enable the counter accumulation in parent entry */
if (ulp_flow_db_parent_flow_count_accum_set(parms->ulp_ctx,
- fid_idx)) {
+ pc_idx)) {
BNXT_TF_DBG(ERR, "Error in setting counter acc %x\n",
parms->fid);
return -1;
}
}
- rc = ulp_flow_db_parent_tun_idx_set(parms->ulp_ctx, fid_idx,
- parms->tun_idx);
- if (rc) {
- BNXT_TF_DBG(ERR, "Error setting tun_idx in the parent flow\n");
- return rc;
- }
-
return 0;
}
@@ -1741,13 +1667,19 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
uint32_t sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT;
enum bnxt_ulp_resource_func res_fun;
struct ulp_flow_db_res_params res_p;
- uint32_t parent_fid = parms->parent_fid;
- int32_t rc;
+ int32_t rc, pc_idx;
+
+ /* create or get the parent child database */
+ pc_idx = ulp_flow_db_pc_db_idx_alloc(parms->ulp_ctx, parms->tun_idx);
+ if (pc_idx < 0) {
+ BNXT_TF_DBG(ERR, "Error in getting parent child db %x\n",
+ parms->tun_idx);
+ return -1;
+ }
/* create the parent flow entry in parent flow table */
- rc = ulp_flow_db_parent_child_flow_set(parms->ulp_ctx,
- parms->parent_fid,
- parms->fid, 1);
+ rc = ulp_flow_db_pc_db_child_flow_set(parms->ulp_ctx, pc_idx,
+ parms->fid, 1);
if (rc) {
BNXT_TF_DBG(ERR, "Error in setting child fid %x\n", parms->fid);
return rc;
@@ -1756,7 +1688,7 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
/* Add the parent details in the resource list of the flow */
memset(&fid_parms, 0, sizeof(fid_parms));
fid_parms.resource_func = BNXT_ULP_RESOURCE_FUNC_CHILD_FLOW;
- fid_parms.resource_hndl = parms->parent_fid;
+ fid_parms.resource_hndl = pc_idx;
fid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO;
rc = ulp_flow_db_resource_add(parms->ulp_ctx,
BNXT_ULP_FDB_TYPE_REGULAR,
@@ -1767,30 +1699,26 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
return rc;
}
- /* check if accumulation count is set for parent flow */
- rc = ulp_flow_db_parent_flow_count_accum_get(parms->ulp_ctx,
- parms->parent_fid);
+ /* check if internal count action included for this flow.*/
+ res_fun = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE;
+ rc = ulp_flow_db_resource_params_get(parms->ulp_ctx,
+ BNXT_ULP_FDB_TYPE_REGULAR,
+ parms->fid,
+ res_fun,
+ sub_type,
+ &res_p);
if (!rc) {
- /* check if internal count action included for this flow.*/
- res_fun = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE;
- rc = ulp_flow_db_resource_params_get(parms->ulp_ctx,
- BNXT_ULP_FDB_TYPE_REGULAR,
- parms->fid,
- res_fun,
- sub_type,
- &res_p);
- if (!rc) {
- /* update the counter manager to include parent fid */
- if (ulp_fc_mgr_cntr_parent_flow_set(parms->ulp_ctx,
- res_p.direction,
- res_p.resource_hndl,
- parent_fid)) {
- BNXT_TF_DBG(ERR, "Error in setting child %x\n",
- parms->fid);
- return -1;
- }
+ /* update the counter manager to include parent fid */
+ if (ulp_fc_mgr_cntr_parent_flow_set(parms->ulp_ctx,
+ res_p.direction,
+ res_p.resource_hndl,
+ pc_idx)) {
+ BNXT_TF_DBG(ERR, "Error in setting child %x\n",
+ parms->fid);
+ return -1;
}
}
+
/* return success */
return 0;
}
@@ -1799,7 +1727,7 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
* Update the parent counters
*
* ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
+ * pc_idx [in] The parent flow entry idx
* packet_count [in] - packet count
* byte_count [in] - byte count
*
@@ -1807,41 +1735,31 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
*/
int32_t
ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid,
+ uint32_t pc_idx,
uint64_t packet_count,
uint64_t byte_count)
{
- struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
- uint32_t idx;
+ struct ulp_fdb_parent_info *pc_entry;
- /* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
- if (!flow_db) {
- BNXT_TF_DBG(ERR, "parent child db validation failed\n");
+ /* validate the arguments and get parent child entry */
+ pc_entry = ulp_flow_db_pc_db_entry_get(ulp_ctxt, pc_idx);
+ if (!pc_entry) {
+ BNXT_TF_DBG(ERR, "failed to get the parent child entry\n");
return -EINVAL;
}
- p_pdb = &flow_db->parent_child_db;
- for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
- if (p_pdb->parent_flow_tbl[idx].counter_acc) {
- p_pdb->parent_flow_tbl[idx].pkt_count +=
- packet_count;
- p_pdb->parent_flow_tbl[idx].byte_count +=
- byte_count;
- }
- return 0;
- }
+ if (pc_entry->counter_acc) {
+ pc_entry->pkt_count += packet_count;
+ pc_entry->byte_count += byte_count;
}
- return -ENOENT;
+ return 0;
}
/*
* Get the parent accumulation counters
*
* ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
+ * pc_idx [in] The parent flow entry idx
* packet_count [out] - packet count
* byte_count [out] - byte count
*
@@ -1849,37 +1767,27 @@ ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt,
*/
int32_t
ulp_flow_db_parent_flow_count_get(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid, uint64_t *packet_count,
+ uint32_t pc_idx, uint64_t *packet_count,
uint64_t *byte_count, uint8_t count_reset)
{
- struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
- uint32_t idx;
+ struct ulp_fdb_parent_info *pc_entry;
- /* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
- if (!flow_db) {
- BNXT_TF_DBG(ERR, "parent child db validation failed\n");
+ /* validate the arguments and get parent child entry */
+ pc_entry = ulp_flow_db_pc_db_entry_get(ulp_ctxt, pc_idx);
+ if (!pc_entry) {
+ BNXT_TF_DBG(ERR, "failed to get the parent child entry\n");
return -EINVAL;
}
- p_pdb = &flow_db->parent_child_db;
- for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
- if (p_pdb->parent_flow_tbl[idx].counter_acc) {
- *packet_count =
- p_pdb->parent_flow_tbl[idx].pkt_count;
- *byte_count =
- p_pdb->parent_flow_tbl[idx].byte_count;
- if (count_reset) {
- p_pdb->parent_flow_tbl[idx].pkt_count = 0;
- p_pdb->parent_flow_tbl[idx].byte_count = 0;
- }
- }
- return 0;
+ if (pc_entry->counter_acc) {
+ *packet_count = pc_entry->pkt_count;
+ *byte_count = pc_entry->byte_count;
+ if (count_reset) {
+ pc_entry->pkt_count = 0;
+ pc_entry->byte_count = 0;
}
}
- return -ENOENT;
+ return 0;
}
/*
@@ -1897,7 +1805,7 @@ ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt)
uint32_t idx;
/* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, 1);
+ flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
if (!flow_db) {
BNXT_TF_DBG(ERR, "parent child db validation failed\n");
return;
@@ -1905,7 +1813,7 @@ ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt)
p_pdb = &flow_db->parent_child_db;
for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid &&
+ if (p_pdb->parent_flow_tbl[idx].valid &&
p_pdb->parent_flow_tbl[idx].counter_acc) {
p_pdb->parent_flow_tbl[idx].pkt_count = 0;
p_pdb->parent_flow_tbl[idx].byte_count = 0;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
index 0ddfa6f66d..8680ee8f65 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
@@ -58,6 +58,7 @@ struct bnxt_ulp_flow_tbl {
/* Structure to maintain parent-child flow relationships */
struct ulp_fdb_parent_info {
+ uint32_t valid;
uint32_t parent_fid;
uint32_t counter_acc;
uint64_t pkt_count;
@@ -259,45 +260,38 @@ int32_t
ulp_default_flow_db_cfa_action_get(struct bnxt_ulp_context *ulp_ctx,
uint32_t flow_id,
uint16_t *cfa_action);
-/*
- * Allocate the entry in the parent-child database
- *
- * ulp_ctxt [in] Ptr to ulp_context
- * fid [in] The flow id to the flow entry
- *
- * returns index on success and negative on failure.
- */
-int32_t
-ulp_flow_db_parent_flow_alloc(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t fid);
/*
- * Free the entry in the parent-child database
+ * Set or reset the parent flow in the parent-child database
*
* ulp_ctxt [in] Ptr to ulp_context
- * fid [in] The flow id to the flow entry
+ * pc_idx [in] The index to parent child db
+ * parent_fid [in] The flow id of the parent flow entry
+ * set_flag [in] Use 1 for setting child, 0 to reset
*
- * returns 0 on success and negative on failure.
+ * returns zero on success and negative on failure.
*/
int32_t
-ulp_flow_db_parent_flow_free(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t fid);
+ulp_flow_db_pc_db_parent_flow_set(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t pc_idx,
+ uint32_t parent_fid,
+ uint32_t set_flag);
/*
* Set or reset the child flow in the parent-child database
*
* ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
+ * pc_idx [in] The index to parent child db
* child_fid [in] The flow id of the child flow entry
* set_flag [in] Use 1 for setting child, 0 to reset
*
* returns zero on success and negative on failure.
*/
int32_t
-ulp_flow_db_parent_child_flow_set(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid,
- uint32_t child_fid,
- uint32_t set_flag);
+ulp_flow_db_pc_db_child_flow_set(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t pc_idx,
+ uint32_t child_fid,
+ uint32_t set_flag);
/*
* Get the parent index from the parent-child database
@@ -368,7 +362,7 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms);
* Update the parent counters
*
* ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
+ * pc_idx [in] The parent flow entry idx
* packet_count [in] - packet count
* byte_count [in] - byte count
*
@@ -376,14 +370,14 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms);
*/
int32_t
ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid,
+ uint32_t pc_idx,
uint64_t packet_count,
uint64_t byte_count);
/*
* Get the parent accumulation counters
*
* ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
+ * pc_idx [in] The parent flow entry idx
* packet_count [out] - packet count
* byte_count [out] - byte count
*
@@ -391,7 +385,7 @@ ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt,
*/
int32_t
ulp_flow_db_parent_flow_count_get(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid,
+ uint32_t pc_idx,
uint64_t *packet_count,
uint64_t *byte_count,
uint8_t count_reset);
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 7fc3767b33..6d804c7ef9 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -544,34 +544,14 @@ ulp_mapper_parent_flow_free(struct bnxt_ulp_context *ulp,
uint32_t parent_fid,
struct ulp_flow_db_res_params *res)
{
- uint32_t idx, child_fid = 0, parent_idx;
- struct bnxt_ulp_flow_db *flow_db;
+ uint32_t pc_idx;
- parent_idx = (uint32_t)res->resource_hndl;
+ pc_idx = (uint32_t)res->resource_hndl;
- /* check the validity of the parent fid */
- if (ulp_flow_db_parent_flow_idx_get(ulp, parent_fid, &idx) ||
- idx != parent_idx) {
- BNXT_TF_DBG(ERR, "invalid parent flow id %x\n", parent_fid);
- return -EINVAL;
- }
-
- /* Clear all the child flows parent index */
- flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp);
- while (!ulp_flow_db_parent_child_flow_next_entry_get(flow_db, idx,
- &child_fid)) {
- /* update the child flows resource handle */
- if (ulp_flow_db_child_flow_reset(ulp, BNXT_ULP_FDB_TYPE_REGULAR,
- child_fid)) {
- BNXT_TF_DBG(ERR, "failed to reset child flow %x\n",
- child_fid);
- return -EINVAL;
- }
- }
-
- /* free the parent entry in the parent table flow */
- if (ulp_flow_db_parent_flow_free(ulp, parent_fid)) {
- BNXT_TF_DBG(ERR, "failed to free parent flow %x\n", parent_fid);
+ /* reset the child flow bitset*/
+ if (ulp_flow_db_pc_db_parent_flow_set(ulp, pc_idx, parent_fid, 0)) {
+ BNXT_TF_DBG(ERR, "error in reset parent flow bitset %x:%x\n",
+ pc_idx, parent_fid);
return -EINVAL;
}
return 0;
@@ -582,16 +562,14 @@ ulp_mapper_child_flow_free(struct bnxt_ulp_context *ulp,
uint32_t child_fid,
struct ulp_flow_db_res_params *res)
{
- uint32_t parent_fid;
+ uint32_t pc_idx;
- parent_fid = (uint32_t)res->resource_hndl;
- if (!parent_fid)
- return 0; /* Already freed - orphan child*/
+ pc_idx = (uint32_t)res->resource_hndl;
/* reset the child flow bitset*/
- if (ulp_flow_db_parent_child_flow_set(ulp, parent_fid, child_fid, 0)) {
+ if (ulp_flow_db_pc_db_child_flow_set(ulp, pc_idx, child_fid, 0)) {
BNXT_TF_DBG(ERR, "error in resetting child flow bitset %x:%x\n",
- parent_fid, child_fid);
+ pc_idx, child_fid);
return -EINVAL;
}
return 0;
@@ -1944,6 +1922,12 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
+ /* If only allocation of identifier then perform and exit */
+ if (tbl->tbl_opcode == BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT) {
+ rc = ulp_mapper_tcam_tbl_scan_ident_alloc(parms, tbl);
+ return rc;
+ }
+
kflds = ulp_mapper_key_fields_get(parms, tbl, &num_kflds);
if (!kflds || !num_kflds) {
BNXT_TF_DBG(ERR, "Failed to get key fields\n");
@@ -3889,7 +3873,7 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
parms.class_tid = cparms->class_tid;
parms.flow_type = cparms->flow_type;
parms.parent_flow = cparms->parent_flow;
- parms.parent_fid = cparms->parent_fid;
+ parms.child_flow = cparms->child_flow;
parms.fid = cparms->flow_id;
parms.tun_idx = cparms->tun_idx;
parms.app_priority = cparms->app_priority;
@@ -3954,7 +3938,7 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
rc = ulp_flow_db_parent_flow_create(&parms);
if (rc)
goto flow_error;
- } else if (parms.parent_fid) {
+ } else if (parms.child_flow) {
/* create a child flow details */
rc = ulp_flow_db_child_flow_create(&parms);
if (rc)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
index 004e89ac2b..d4d6969bb5 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
@@ -53,7 +53,7 @@ struct bnxt_ulp_mapper_parms {
enum bnxt_ulp_fdb_type flow_type;
struct bnxt_ulp_mapper_data *mapper_data;
struct bnxt_ulp_device_params *device_params;
- uint32_t parent_fid;
+ uint32_t child_flow;
uint32_t parent_flow;
uint8_t tun_idx;
uint32_t app_priority;
@@ -79,8 +79,8 @@ struct bnxt_ulp_mapper_create_parms {
enum bnxt_ulp_fdb_type flow_type;
uint32_t flow_id;
- /* if set then create it as a child flow with parent as parent_fid */
- uint32_t parent_fid;
+ /* if set then create it as a child flow */
+ uint32_t child_flow;
/* if set then create a parent flow */
uint32_t parent_flow;
uint8_t tun_idx;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
index 35e9858727..9b165c12b5 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
@@ -215,6 +215,21 @@ struct bnxt_ulp_rte_act_info ulp_act_info[] = {
}
};
+struct bnxt_ulp_rte_act_info ulp_vendor_act_info[] = {
+ [BNXT_RTE_FLOW_ACTION_TYPE_END - BNXT_RTE_FLOW_ACTION_TYPE_END] = {
+ .act_type = BNXT_ULP_ACT_TYPE_END,
+ .proto_act_func = NULL
+ },
+ [BNXT_RTE_FLOW_ACTION_TYPE_VXLAN_DECAP - BNXT_RTE_FLOW_ACTION_TYPE_END] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_vendor_vxlan_decap_act_handler
+ },
+ [BNXT_RTE_FLOW_ACTION_TYPE_LAST - BNXT_RTE_FLOW_ACTION_TYPE_END] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ }
+};
+
/*
* This table has to be indexed based on the rte_flow_item_type that is part of
* DPDK. The below array is list of parsing functions for each of the flow items
@@ -414,3 +429,19 @@ struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = {
.proto_hdr_func = NULL
}
};
+
+struct bnxt_ulp_rte_hdr_info ulp_vendor_hdr_info[] = {
+ [BNXT_RTE_FLOW_ITEM_TYPE_END - BNXT_RTE_FLOW_ITEM_TYPE_END] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_END,
+ .proto_hdr_func = NULL
+ },
+ [BNXT_RTE_FLOW_ITEM_TYPE_VXLAN_DECAP - BNXT_RTE_FLOW_ITEM_TYPE_END] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_vendor_vxlan_decap_hdr_handler
+ },
+ [BNXT_RTE_FLOW_ITEM_TYPE_LAST - BNXT_RTE_FLOW_ITEM_TYPE_END] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+
+};
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index 79b9957781..fadcd3873c 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -125,13 +125,21 @@ bnxt_ulp_rte_parser_hdr_parse(const struct rte_flow_item pattern[],
/* Parse all the items in the pattern */
while (item && item->type != RTE_FLOW_ITEM_TYPE_END) {
- /* get the header information from the flow_hdr_info table */
- hdr_info = &ulp_hdr_info[item->type];
+ if (item->type >= (uint32_t)
+ BNXT_RTE_FLOW_ITEM_TYPE_END) {
+ if (item->type >=
+ (uint32_t)BNXT_RTE_FLOW_ITEM_TYPE_LAST)
+ goto hdr_parser_error;
+ /* get the header information */
+ hdr_info = &ulp_vendor_hdr_info[item->type -
+ BNXT_RTE_FLOW_ITEM_TYPE_END];
+ } else {
+ if (item->type > RTE_FLOW_ITEM_TYPE_HIGIG2)
+ goto hdr_parser_error;
+ hdr_info = &ulp_hdr_info[item->type];
+ }
if (hdr_info->hdr_type == BNXT_ULP_HDR_TYPE_NOT_SUPPORTED) {
- BNXT_TF_DBG(ERR,
- "Truflow parser does not support type %d\n",
- item->type);
- return BNXT_TF_RC_PARSE_ERR;
+ goto hdr_parser_error;
} else if (hdr_info->hdr_type == BNXT_ULP_HDR_TYPE_SUPPORTED) {
/* call the registered callback handler */
if (hdr_info->proto_hdr_func) {
@@ -145,6 +153,11 @@ bnxt_ulp_rte_parser_hdr_parse(const struct rte_flow_item pattern[],
}
/* update the implied SVIF */
return ulp_rte_parser_implicit_match_port_process(params);
+
+hdr_parser_error:
+ BNXT_TF_DBG(ERR, "Truflow parser does not support type %d\n",
+ item->type);
+ return BNXT_TF_RC_PARSE_ERR;
}
/*
@@ -160,16 +173,23 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[],
/* Parse all the items in the pattern */
while (action_item && action_item->type != RTE_FLOW_ACTION_TYPE_END) {
- /* get the header information from the flow_hdr_info table */
- hdr_info = &ulp_act_info[action_item->type];
- if (hdr_info->act_type ==
- BNXT_ULP_ACT_TYPE_NOT_SUPPORTED) {
- BNXT_TF_DBG(ERR,
- "Truflow parser does not support act %u\n",
- action_item->type);
- return BNXT_TF_RC_ERROR;
- } else if (hdr_info->act_type ==
- BNXT_ULP_ACT_TYPE_SUPPORTED) {
+ if (action_item->type >=
+ (uint32_t)BNXT_RTE_FLOW_ACTION_TYPE_END) {
+ if (action_item->type >=
+ (uint32_t)BNXT_RTE_FLOW_ACTION_TYPE_LAST)
+ goto act_parser_error;
+ /* get the header information from bnxt actinfo table */
+ hdr_info = &ulp_vendor_act_info[action_item->type -
+ BNXT_RTE_FLOW_ACTION_TYPE_END];
+ } else {
+ if (action_item->type > RTE_FLOW_ACTION_TYPE_SHARED)
+ goto act_parser_error;
+ /* get the header information from the act info table */
+ hdr_info = &ulp_act_info[action_item->type];
+ }
+ if (hdr_info->act_type == BNXT_ULP_ACT_TYPE_NOT_SUPPORTED) {
+ goto act_parser_error;
+ } else if (hdr_info->act_type == BNXT_ULP_ACT_TYPE_SUPPORTED) {
/* call the registered callback handler */
if (hdr_info->proto_act_func) {
if (hdr_info->proto_act_func(action_item,
@@ -184,6 +204,11 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[],
/* update the implied port details */
ulp_rte_parser_implicit_act_port_process(params);
return BNXT_TF_RC_SUCCESS;
+
+act_parser_error:
+ BNXT_TF_DBG(ERR, "Truflow parser does not support act %u\n",
+ action_item->type);
+ return BNXT_TF_RC_ERROR;
}
/*
@@ -325,11 +350,10 @@ ulp_post_process_normal_flow(struct ulp_rte_parser_params *params)
/*
* Function to handle the post processing of the parsing details
*/
-int32_t
+void
bnxt_ulp_rte_parser_post_process(struct ulp_rte_parser_params *params)
{
ulp_post_process_normal_flow(params);
- return ulp_post_process_tun_flow(params);
}
/*
@@ -660,7 +684,7 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item,
{
const struct rte_flow_item_eth *eth_spec = item->spec;
const struct rte_flow_item_eth *eth_mask = item->mask;
- uint32_t idx = 0;
+ uint32_t idx = 0, dmac_idx = 0;
uint32_t size;
uint16_t eth_type = 0;
uint32_t inner_flag = 0;
@@ -686,6 +710,7 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item,
* Copy the rte_flow_item for eth into hdr_field using ethernet
* header fields
*/
+ dmac_idx = idx;
size = sizeof(((struct rte_flow_item_eth *)NULL)->dst.addr_bytes);
ulp_rte_prsr_fld_mask(params, &idx, size,
ulp_deference_struct(eth_spec, dst.addr_bytes),
@@ -719,6 +744,8 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item,
inner_flag = 1;
} else {
ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_ETH);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID,
+ dmac_idx);
}
/* Update the field protocol hdr bitmap */
ulp_rte_l2_proto_type_update(params, eth_type, inner_flag);
@@ -926,7 +953,7 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
const struct rte_flow_item_ipv4 *ipv4_spec = item->spec;
const struct rte_flow_item_ipv4 *ipv4_mask = item->mask;
struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap;
- uint32_t idx = 0;
+ uint32_t idx = 0, dip_idx = 0;
uint32_t size;
uint8_t proto = 0;
uint32_t inner_flag = 0;
@@ -939,22 +966,6 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
return BNXT_TF_RC_ERROR;
}
- if (!ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
- BNXT_ULP_HDR_BIT_O_ETH) &&
- !ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
- BNXT_ULP_HDR_BIT_I_ETH)) {
- /* Since F2 flow does not include eth item, when parser detects
- * IPv4/IPv6 item list and it belongs to the outer header; i.e.,
- * o_ipv4/o_ipv6, check if O_ETH and I_ETH is set. If not set,
- * then add offset sizeof(o_eth/oo_vlan/oi_vlan) to the index.
- * This will allow the parser post processor to update the
- * t_dmac in hdr_field[o_eth.dmac]
- */
- idx += (BNXT_ULP_PROTO_HDR_ETH_NUM +
- BNXT_ULP_PROTO_HDR_VLAN_NUM);
- params->field_idx = idx;
- }
-
if (ulp_rte_prsr_fld_size_validate(params, &idx,
BNXT_ULP_PROTO_HDR_IPV4_NUM)) {
BNXT_TF_DBG(ERR, "Error parsing protocol header\n");
@@ -1033,6 +1044,7 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
ulp_deference_struct(ipv4_mask, hdr.src_addr),
ULP_PRSR_ACT_DEFAULT);
+ dip_idx = idx;
size = sizeof(((struct rte_flow_item_ipv4 *)NULL)->hdr.dst_addr);
ulp_rte_prsr_fld_mask(params, &idx, size,
ulp_deference_struct(ipv4_spec, hdr.dst_addr),
@@ -1048,6 +1060,9 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
} else {
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3, 1);
+ /* Update the tunnel offload dest ip offset */
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID,
+ dip_idx);
}
/* Some of the PMD applications may set the protocol field
@@ -1071,7 +1086,7 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
const struct rte_flow_item_ipv6 *ipv6_spec = item->spec;
const struct rte_flow_item_ipv6 *ipv6_mask = item->mask;
struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap;
- uint32_t idx = 0;
+ uint32_t idx = 0, dip_idx = 0;
uint32_t size;
uint32_t ver_spec = 0, ver_mask = 0;
uint32_t tc_spec = 0, tc_mask = 0;
@@ -1087,22 +1102,6 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
return BNXT_TF_RC_ERROR;
}
- if (!ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
- BNXT_ULP_HDR_BIT_O_ETH) &&
- !ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
- BNXT_ULP_HDR_BIT_I_ETH)) {
- /* Since F2 flow does not include eth item, when parser detects
- * IPv4/IPv6 item list and it belongs to the outer header; i.e.,
- * o_ipv4/o_ipv6, check if O_ETH and I_ETH is set. If not set,
- * then add offset sizeof(o_eth/oo_vlan/oi_vlan) to the index.
- * This will allow the parser post processor to update the
- * t_dmac in hdr_field[o_eth.dmac]
- */
- idx += (BNXT_ULP_PROTO_HDR_ETH_NUM +
- BNXT_ULP_PROTO_HDR_VLAN_NUM);
- params->field_idx = idx;
- }
-
if (ulp_rte_prsr_fld_size_validate(params, &idx,
BNXT_ULP_PROTO_HDR_IPV6_NUM)) {
BNXT_TF_DBG(ERR, "Error parsing protocol header\n");
@@ -1171,6 +1170,7 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
ulp_deference_struct(ipv6_mask, hdr.src_addr),
ULP_PRSR_ACT_DEFAULT);
+ dip_idx = idx;
size = sizeof(((struct rte_flow_item_ipv6 *)NULL)->hdr.dst_addr);
ulp_rte_prsr_fld_mask(params, &idx, size,
ulp_deference_struct(ipv6_spec, hdr.dst_addr),
@@ -1186,6 +1186,9 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
} else {
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3, 1);
+ /* Update the tunnel offload dest ip offset */
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID,
+ dip_idx);
}
/* Update the field protocol hdr bitmap */
@@ -1200,9 +1203,11 @@ static void
ulp_rte_l4_proto_type_update(struct ulp_rte_parser_params *param,
uint16_t dst_port)
{
- if (dst_port == tfp_cpu_to_be_16(ULP_UDP_PORT_VXLAN))
+ if (dst_port == tfp_cpu_to_be_16(ULP_UDP_PORT_VXLAN)) {
ULP_BITMAP_SET(param->hdr_fp_bit.bits,
BNXT_ULP_HDR_BIT_T_VXLAN);
+ ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_L3_TUN, 1);
+ }
if (ULP_BITMAP_ISSET(param->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_T_VXLAN) ||
@@ -2484,3 +2489,24 @@ ulp_rte_sample_act_handler(const struct rte_flow_action *action_item,
return ret;
}
+
+/* Function to handle the parsing of bnxt vendor Flow action vxlan Header. */
+int32_t
+ulp_vendor_vxlan_decap_act_handler(const struct rte_flow_action *action_item,
+ struct ulp_rte_parser_params *params)
+{
+ /* Set the F1 flow header bit */
+ ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F1);
+ return ulp_rte_vxlan_decap_act_handler(action_item, params);
+}
+
+/* Function to handle the parsing of bnxt vendor Flow item vxlan Header. */
+int32_t
+ulp_rte_vendor_vxlan_decap_hdr_handler(const struct rte_flow_item *item,
+ struct ulp_rte_parser_params *params)
+{
+ RTE_SET_USED(item);
+ /* Set the F2 flow header bit */
+ ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F2);
+ return ulp_rte_vxlan_decap_act_handler(NULL, params);
+}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
index 4431f1bbd0..673172c811 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
@@ -75,7 +75,7 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[],
/*
* Function to handle the post processing of the parsing details
*/
-int32_t
+void
bnxt_ulp_rte_parser_post_process(struct ulp_rte_parser_params *params);
/* Function to handle the parsing of RTE Flow item PF Header. */
@@ -270,4 +270,12 @@ int32_t
ulp_rte_shared_act_handler(const struct rte_flow_action *action_item,
struct ulp_rte_parser_params *params);
+int32_t
+ulp_vendor_vxlan_decap_act_handler(const struct rte_flow_action *action_item,
+ struct ulp_rte_parser_params *params);
+
+int32_t
+ulp_rte_vendor_vxlan_decap_hdr_handler(const struct rte_flow_item *item,
+ struct ulp_rte_parser_params *params);
+
#endif /* _ULP_RTE_PARSER_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index 0cbac66237..2685e63432 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -78,17 +78,19 @@ struct ulp_rte_parser_params {
uint32_t priority;
uint32_t fid;
uint32_t parent_flow;
- uint32_t parent_fid;
+ uint32_t child_flow;
uint16_t func_id;
uint16_t port_id;
uint32_t class_id;
uint32_t act_tmpl;
struct bnxt_ulp_context *ulp_ctx;
uint32_t hdr_sig_id;
- uint32_t flow_sig_id;
+ uint64_t flow_sig_id;
uint32_t flow_pattern_id;
uint32_t act_pattern_id;
uint8_t app_id;
+ uint8_t tun_idx;
+
};
/* Flow Parser Header Information Structure */
@@ -101,6 +103,7 @@ struct bnxt_ulp_rte_hdr_info {
/* Flow Parser Header Information Structure Array defined in template source*/
extern struct bnxt_ulp_rte_hdr_info ulp_hdr_info[];
+extern struct bnxt_ulp_rte_hdr_info ulp_vendor_hdr_info[];
/* Flow Parser Action Information Structure */
struct bnxt_ulp_rte_act_info {
@@ -113,6 +116,7 @@ struct bnxt_ulp_rte_act_info {
/* Flow Parser Action Information Structure Array defined in template source*/
extern struct bnxt_ulp_rte_act_info ulp_act_info[];
+extern struct bnxt_ulp_rte_act_info ulp_vendor_act_info[];
/* Flow Matcher structures */
struct bnxt_ulp_header_match_info {
@@ -136,7 +140,7 @@ struct bnxt_ulp_class_match_info {
uint8_t wc_pri;
uint8_t app_sig;
uint32_t hdr_sig_id;
- uint32_t flow_sig_id;
+ uint64_t flow_sig_id;
uint32_t flow_pattern_id;
};
diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.c b/drivers/net/bnxt/tf_ulp/ulp_tun.c
index a1dd5b902c..7ce6740633 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_tun.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_tun.c
@@ -3,225 +3,111 @@
* All rights reserved.
*/
-#include <sys/queue.h>
-
-#include <rte_malloc.h>
-
+#include "bnxt.h"
+#include "bnxt_ulp.h"
#include "ulp_tun.h"
-#include "ulp_rte_parser.h"
-#include "ulp_template_db_enum.h"
-#include "ulp_template_struct.h"
-#include "ulp_matcher.h"
-#include "ulp_mapper.h"
-#include "ulp_flow_db.h"
+#include "ulp_utils.h"
-/* This function programs the outer tunnel flow in the hardware. */
-static int32_t
-ulp_install_outer_tun_flow(struct ulp_rte_parser_params *params,
- struct bnxt_tun_cache_entry *tun_entry,
- uint16_t tun_idx)
+/* returns negative on error, 1 if new entry is allocated or zero if old */
+int32_t
+ulp_app_tun_search_entry(struct bnxt_ulp_context *ulp_ctx,
+ struct rte_flow_tunnel *app_tunnel,
+ struct bnxt_flow_app_tun_ent **tun_entry)
{
- struct bnxt_ulp_mapper_create_parms mparms = { 0 };
- int ret;
-
- /* Reset the JUMP action bit in the action bitmap as we don't
- * offload this action.
- */
- ULP_BITMAP_RESET(params->act_bitmap.bits, BNXT_ULP_ACT_BIT_JUMP);
-
- ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F1);
-
-#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
-#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER
- /* Dump the rte flow pattern */
- ulp_parser_hdr_info_dump(params);
- /* Dump the rte flow action */
- ulp_parser_act_info_dump(params);
-#endif
-#endif
-
- ret = ulp_matcher_pattern_match(params, ¶ms->class_id);
- if (ret != BNXT_TF_RC_SUCCESS)
- goto err;
+ struct bnxt_flow_app_tun_ent *tun_ent_list;
+ int32_t i, rc = 0, free_entry = -1;
- ret = ulp_matcher_action_match(params, ¶ms->act_tmpl);
- if (ret != BNXT_TF_RC_SUCCESS)
- goto err;
-
- params->parent_flow = true;
- bnxt_ulp_init_mapper_params(&mparms, params,
- BNXT_ULP_FDB_TYPE_REGULAR);
- mparms.tun_idx = tun_idx;
-
- /* Call the ulp mapper to create the flow in the hardware. */
- ret = ulp_mapper_flow_create(params->ulp_ctx, &mparms);
- if (ret)
- goto err;
-
- /* Store the tunnel dmac in the tunnel cache table and use it while
- * programming tunnel inner flow.
- */
- memcpy(tun_entry->t_dmac,
- ¶ms->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX].spec,
- RTE_ETHER_ADDR_LEN);
-
- tun_entry->tun_flow_info[params->port_id].state =
- BNXT_ULP_FLOW_STATE_TUN_O_OFFLD;
- tun_entry->outer_tun_flow_id = params->fid;
-
- /* Tunnel outer flow and it's related inner flows are correlated
- * based on Tunnel Destination IP Address.
- */
- if (tun_entry->t_dst_ip_valid)
- goto done;
- if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV4))
- memcpy(&tun_entry->t_dst_ip,
- ¶ms->hdr_field[ULP_TUN_O_IPV4_DIP_INDEX].spec,
- sizeof(rte_be32_t));
- else
- memcpy(tun_entry->t_dst_ip6,
- ¶ms->hdr_field[ULP_TUN_O_IPV6_DIP_INDEX].spec,
- sizeof(tun_entry->t_dst_ip6));
- tun_entry->t_dst_ip_valid = true;
+ tun_ent_list = bnxt_ulp_cntxt_ptr2_app_tun_list_get(ulp_ctx);
+ if (!tun_ent_list) {
+ BNXT_TF_DBG(ERR, "unable to get the app tunnel list\n");
+ return -EINVAL;
+ }
-done:
- return BNXT_TF_RC_FID;
+ for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {
+ if (!tun_ent_list[i].ref_cnt) {
+ if (free_entry < 0)
+ free_entry = i;
+ } else {
+ if (!memcmp(&tun_ent_list[i].app_tunnel,
+ app_tunnel,
+ sizeof(struct rte_flow_tunnel))) {
+ *tun_entry = &tun_ent_list[i];
+ tun_ent_list[free_entry].ref_cnt++;
+ return rc;
+ }
+ }
+ }
+ if (free_entry >= 0) {
+ *tun_entry = &tun_ent_list[free_entry];
+ memcpy(&tun_ent_list[free_entry].app_tunnel, app_tunnel,
+ sizeof(struct rte_flow_tunnel));
+ tun_ent_list[free_entry].ref_cnt = 1;
+ rc = 1;
+ } else {
+ BNXT_TF_DBG(ERR, "ulp app tunnel list is full\n");
+ return -ENOMEM;
+ }
-err:
- memset(tun_entry, 0, sizeof(struct bnxt_tun_cache_entry));
- return BNXT_TF_RC_ERROR;
+ return rc;
}
-/* This function programs the inner tunnel flow in the hardware. */
-static void
-ulp_install_inner_tun_flow(struct bnxt_tun_cache_entry *tun_entry,
- struct ulp_rte_parser_params *tun_o_params)
+void
+ulp_app_tun_entry_delete(struct bnxt_flow_app_tun_ent *tun_entry)
{
- struct bnxt_ulp_mapper_create_parms mparms = { 0 };
- struct ulp_per_port_flow_info *flow_info;
- struct ulp_rte_parser_params *inner_params;
- int ret;
-
- /* Tunnel inner flow doesn't have tunnel dmac, use the tunnel
- * dmac that was stored during F1 programming.
- */
- flow_info = &tun_entry->tun_flow_info[tun_o_params->port_id];
- STAILQ_FOREACH(inner_params, &flow_info->tun_i_prms_list, next) {
- memcpy(&inner_params->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX],
- tun_entry->t_dmac, RTE_ETHER_ADDR_LEN);
- inner_params->parent_fid = tun_entry->outer_tun_flow_id;
-
- bnxt_ulp_init_mapper_params(&mparms, inner_params,
- BNXT_ULP_FDB_TYPE_REGULAR);
-
- ret = ulp_mapper_flow_create(inner_params->ulp_ctx, &mparms);
- if (ret)
- PMD_DRV_LOG(ERR,
- "Failed to create inner tun flow, FID:%u.",
- inner_params->fid);
+ if (tun_entry) {
+ if (tun_entry->ref_cnt) {
+ tun_entry->ref_cnt--;
+ if (!tun_entry->ref_cnt)
+ memset(tun_entry, 0,
+ sizeof(struct bnxt_flow_app_tun_ent));
+ }
}
}
-/* This function either install outer tunnel flow & inner tunnel flow
- * or just the outer tunnel flow based on the flow state.
- */
-static int32_t
-ulp_post_process_outer_tun_flow(struct ulp_rte_parser_params *params,
- struct bnxt_tun_cache_entry *tun_entry,
- uint16_t tun_idx)
+int32_t
+ulp_app_tun_entry_set_decap_action(struct bnxt_flow_app_tun_ent *tun_entry)
{
- int ret;
-
- ret = ulp_install_outer_tun_flow(params, tun_entry, tun_idx);
- if (ret == BNXT_TF_RC_ERROR) {
- PMD_DRV_LOG(ERR, "Failed to create outer tunnel flow.");
- return ret;
- }
+ if (!tun_entry)
+ return -EINVAL;
- /* Install any cached tunnel inner flows that came before tunnel
- * outer flow.
- */
- ulp_install_inner_tun_flow(tun_entry, params);
-
- return BNXT_TF_RC_FID;
+ tun_entry->action.type = (typeof(tun_entry->action.type))
+ BNXT_RTE_FLOW_ACTION_TYPE_VXLAN_DECAP;
+ tun_entry->action.conf = tun_entry;
+ return 0;
}
-/* This function will be called if inner tunnel flow request comes before
- * outer tunnel flow request.
- */
-static int32_t
-ulp_post_process_cache_inner_tun_flow(struct ulp_rte_parser_params *params,
- struct bnxt_tun_cache_entry *tun_entry)
+int32_t
+ulp_app_tun_entry_set_decap_item(struct bnxt_flow_app_tun_ent *tun_entry)
{
- struct ulp_rte_parser_params *inner_tun_params;
- struct ulp_per_port_flow_info *flow_info;
- int ret;
-
-#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
-#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER
- /* Dump the rte flow pattern */
- ulp_parser_hdr_info_dump(params);
- /* Dump the rte flow action */
- ulp_parser_act_info_dump(params);
-#endif
-#endif
-
- ret = ulp_matcher_pattern_match(params, ¶ms->class_id);
- if (ret != BNXT_TF_RC_SUCCESS)
- return BNXT_TF_RC_ERROR;
-
- ret = ulp_matcher_action_match(params, ¶ms->act_tmpl);
- if (ret != BNXT_TF_RC_SUCCESS)
- return BNXT_TF_RC_ERROR;
-
- /* If Tunnel inner flow comes first then we can't install it in the
- * hardware, because, Tunnel inner flow will not have L2 context
- * information. So, just cache the Tunnel inner flow information
- * and program it in the context of F1 flow installation.
- */
- flow_info = &tun_entry->tun_flow_info[params->port_id];
- inner_tun_params = rte_zmalloc("ulp_inner_tun_params",
- sizeof(struct ulp_rte_parser_params), 0);
- if (!inner_tun_params)
- return BNXT_TF_RC_ERROR;
- memcpy(inner_tun_params, params, sizeof(struct ulp_rte_parser_params));
- STAILQ_INSERT_TAIL(&flow_info->tun_i_prms_list, inner_tun_params,
- next);
- flow_info->tun_i_cnt++;
-
- /* F1 and it's related Tunnel inner flows are correlated based on
- * Tunnel Destination IP Address. It could be already set, if
- * the inner flow got offloaded first.
- */
- if (tun_entry->t_dst_ip_valid)
- goto done;
- if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV4))
- memcpy(&tun_entry->t_dst_ip,
- ¶ms->hdr_field[ULP_TUN_O_IPV4_DIP_INDEX].spec,
- sizeof(rte_be32_t));
- else
- memcpy(tun_entry->t_dst_ip6,
- ¶ms->hdr_field[ULP_TUN_O_IPV6_DIP_INDEX].spec,
- sizeof(tun_entry->t_dst_ip6));
- tun_entry->t_dst_ip_valid = true;
-
-done:
- return BNXT_TF_RC_FID;
+ if (!tun_entry)
+ return -EINVAL;
+
+ tun_entry->item.type = (typeof(tun_entry->item.type))
+ BNXT_RTE_FLOW_ITEM_TYPE_VXLAN_DECAP;
+ tun_entry->item.spec = tun_entry;
+ tun_entry->item.last = NULL;
+ tun_entry->item.mask = NULL;
+ return 0;
}
-/* This function will be called if inner tunnel flow request comes after
- * the outer tunnel flow request.
- */
-static int32_t
-ulp_post_process_inner_tun_flow(struct ulp_rte_parser_params *params,
- struct bnxt_tun_cache_entry *tun_entry)
+struct bnxt_flow_app_tun_ent *
+ulp_app_tun_match_entry(struct bnxt_ulp_context *ulp_ctx,
+ const void *ctx)
{
- memcpy(¶ms->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX],
- tun_entry->t_dmac, RTE_ETHER_ADDR_LEN);
+ struct bnxt_flow_app_tun_ent *tun_ent_list;
+ int32_t i;
- params->parent_fid = tun_entry->outer_tun_flow_id;
+ tun_ent_list = bnxt_ulp_cntxt_ptr2_app_tun_list_get(ulp_ctx);
+ if (!tun_ent_list) {
+ BNXT_TF_DBG(ERR, "unable to get the app tunnel list\n");
+ return NULL;
+ }
- return BNXT_TF_RC_NORMAL;
+ for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {
+ if (&tun_ent_list[i] == ctx)
+ return &tun_ent_list[i];
+ }
+ return NULL;
}
static int32_t
@@ -229,203 +115,116 @@ ulp_get_tun_entry(struct ulp_rte_parser_params *params,
struct bnxt_tun_cache_entry **tun_entry,
uint16_t *tun_idx)
{
- int i, first_free_entry = BNXT_ULP_TUN_ENTRY_INVALID;
+ int32_t i, first_free_entry = BNXT_ULP_TUN_ENTRY_INVALID;
struct bnxt_tun_cache_entry *tun_tbl;
- bool tun_entry_found = false, free_entry_found = false;
+ uint32_t dip_idx, dmac_idx, use_ipv4 = 0;
tun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(params->ulp_ctx);
- if (!tun_tbl)
+ if (!tun_tbl) {
+ BNXT_TF_DBG(ERR, "Error: could not get Tunnel table\n");
return BNXT_TF_RC_ERROR;
+ }
+
+ /* get the outer destination ip field index */
+ dip_idx = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID);
+ dmac_idx = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID);
+ if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV4))
+ use_ipv4 = 1;
for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {
- if (!memcmp(&tun_tbl[i].t_dst_ip,
- ¶ms->hdr_field[ULP_TUN_O_IPV4_DIP_INDEX].spec,
- sizeof(rte_be32_t)) ||
- !memcmp(&tun_tbl[i].t_dst_ip6,
- ¶ms->hdr_field[ULP_TUN_O_IPV6_DIP_INDEX].spec,
- 16)) {
- tun_entry_found = true;
- break;
+ if (!tun_tbl[i].t_dst_ip_valid) {
+ if (first_free_entry == BNXT_ULP_TUN_ENTRY_INVALID)
+ first_free_entry = i;
+ continue;
}
-
- if (!tun_tbl[i].t_dst_ip_valid && !free_entry_found) {
- first_free_entry = i;
- free_entry_found = true;
+ /* match on the destination ip of the tunnel */
+ if ((use_ipv4 && !memcmp(&tun_tbl[i].t_dst_ip,
+ params->hdr_field[dip_idx].spec,
+ sizeof(rte_be32_t))) ||
+ (!use_ipv4 &&
+ !memcmp(tun_tbl[i].t_dst_ip6,
+ params->hdr_field[dip_idx].spec,
+ sizeof(((struct bnxt_tun_cache_entry *)
+ NULL)->t_dst_ip6)))) {
+ *tun_entry = &tun_tbl[i];
+ *tun_idx = i;
+ return 0;
}
}
-
- if (tun_entry_found) {
- *tun_entry = &tun_tbl[i];
- *tun_idx = i;
- } else {
- if (first_free_entry == BNXT_ULP_TUN_ENTRY_INVALID)
- return BNXT_TF_RC_ERROR;
- *tun_entry = &tun_tbl[first_free_entry];
- *tun_idx = first_free_entry;
- }
-
- return 0;
-}
-
-int32_t
-ulp_post_process_tun_flow(struct ulp_rte_parser_params *params)
-{
- bool inner_tun_sig, cache_inner_tun_flow;
- bool outer_tun_reject, outer_tun_flow, inner_tun_flow;
- enum bnxt_ulp_tun_flow_state flow_state;
- struct bnxt_tun_cache_entry *tun_entry;
- uint32_t l3_tun, l3_tun_decap;
- uint16_t tun_idx;
- int rc;
-
- /* Computational fields that indicate it's a TUNNEL DECAP flow */
- l3_tun = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_TUN);
- l3_tun_decap = ULP_COMP_FLD_IDX_RD(params,
- BNXT_ULP_CF_IDX_L3_TUN_DECAP);
- if (!l3_tun)
- return BNXT_TF_RC_NORMAL;
-
- rc = ulp_get_tun_entry(params, &tun_entry, &tun_idx);
- if (rc == BNXT_TF_RC_ERROR)
- return rc;
-
- if (params->port_id >= RTE_MAX_ETHPORTS)
+ if (first_free_entry == BNXT_ULP_TUN_ENTRY_INVALID) {
+ BNXT_TF_DBG(ERR, "Error: No entry available in tunnel table\n");
return BNXT_TF_RC_ERROR;
- flow_state = tun_entry->tun_flow_info[params->port_id].state;
- /* Outer tunnel flow validation */
- outer_tun_flow = BNXT_OUTER_TUN_FLOW(l3_tun, params);
- outer_tun_reject = BNXT_REJECT_OUTER_TUN_FLOW(flow_state,
- outer_tun_flow);
-
- /* Inner tunnel flow validation */
- inner_tun_sig = BNXT_INNER_TUN_SIGNATURE(l3_tun, l3_tun_decap, params);
- cache_inner_tun_flow = BNXT_CACHE_INNER_TUN_FLOW(flow_state,
- inner_tun_sig);
- inner_tun_flow = BNXT_INNER_TUN_FLOW(flow_state, inner_tun_sig);
-
- if (outer_tun_reject) {
- tun_entry->outer_tun_rej_cnt++;
- BNXT_TF_DBG(ERR,
- "Tunnel F1 flow rejected, COUNT: %d\n",
- tun_entry->outer_tun_rej_cnt);
}
- if (outer_tun_reject)
- return BNXT_TF_RC_ERROR;
- else if (cache_inner_tun_flow)
- return ulp_post_process_cache_inner_tun_flow(params, tun_entry);
- else if (outer_tun_flow)
- return ulp_post_process_outer_tun_flow(params, tun_entry,
- tun_idx);
- else if (inner_tun_flow)
- return ulp_post_process_inner_tun_flow(params, tun_entry);
- else
- return BNXT_TF_RC_NORMAL;
-}
+ *tun_idx = first_free_entry;
+ *tun_entry = &tun_tbl[first_free_entry];
+ tun_tbl[first_free_entry].t_dst_ip_valid = true;
-void
-ulp_tun_tbl_init(struct bnxt_tun_cache_entry *tun_tbl)
-{
- struct ulp_per_port_flow_info *flow_info;
- int i, j;
+ /* Update the destination ip and mac */
+ if (use_ipv4)
+ memcpy(&tun_tbl[first_free_entry].t_dst_ip,
+ params->hdr_field[dip_idx].spec, sizeof(rte_be32_t));
+ else
+ memcpy(tun_tbl[first_free_entry].t_dst_ip6,
+ params->hdr_field[dip_idx].spec,
+ sizeof(((struct bnxt_tun_cache_entry *)
+ NULL)->t_dst_ip6));
+ memcpy(tun_tbl[first_free_entry].t_dmac,
+ params->hdr_field[dmac_idx].spec, RTE_ETHER_ADDR_LEN);
- for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {
- for (j = 0; j < RTE_MAX_ETHPORTS; j++) {
- flow_info = &tun_tbl[i].tun_flow_info[j];
- STAILQ_INIT(&flow_info->tun_i_prms_list);
- }
- }
+ return 0;
}
+/* Tunnel API to delete the tunnel entry */
void
-ulp_clear_tun_entry(struct bnxt_tun_cache_entry *tun_tbl, uint8_t tun_idx)
+ulp_tunnel_offload_entry_clear(struct bnxt_tun_cache_entry *tun_tbl,
+ uint8_t tun_idx)
{
- struct ulp_rte_parser_params *inner_params;
- struct ulp_per_port_flow_info *flow_info;
- int j;
-
- for (j = 0; j < RTE_MAX_ETHPORTS; j++) {
- flow_info = &tun_tbl[tun_idx].tun_flow_info[j];
- STAILQ_FOREACH(inner_params,
- &flow_info->tun_i_prms_list,
- next) {
- STAILQ_REMOVE(&flow_info->tun_i_prms_list,
- inner_params,
- ulp_rte_parser_params, next);
- rte_free(inner_params);
- }
- }
-
- memset(&tun_tbl[tun_idx], 0,
- sizeof(struct bnxt_tun_cache_entry));
-
- for (j = 0; j < RTE_MAX_ETHPORTS; j++) {
- flow_info = &tun_tbl[tun_idx].tun_flow_info[j];
- STAILQ_INIT(&flow_info->tun_i_prms_list);
- }
+ memset(&tun_tbl[tun_idx], 0, sizeof(struct bnxt_tun_cache_entry));
}
-static bool
-ulp_chk_and_rem_tun_i_flow(struct bnxt_tun_cache_entry *tun_entry,
- struct ulp_per_port_flow_info *flow_info,
- uint32_t fid)
+/* Tunnel API to perform tunnel offload process when there is F1/F2 flows */
+int32_t
+ulp_tunnel_offload_process(struct ulp_rte_parser_params *params)
{
- struct ulp_rte_parser_params *inner_params;
- int j;
-
- STAILQ_FOREACH(inner_params,
- &flow_info->tun_i_prms_list,
- next) {
- if (inner_params->fid == fid) {
- STAILQ_REMOVE(&flow_info->tun_i_prms_list,
- inner_params,
- ulp_rte_parser_params,
- next);
- rte_free(inner_params);
- flow_info->tun_i_cnt--;
- /* When a dpdk application offloads a duplicate
- * tunnel inner flow on a port that it is not
- * destined to, there won't be a tunnel outer flow
- * associated with these duplicate tunnel inner flows.
- * So, when the last tunnel inner flow ages out, the
- * driver has to clear the tunnel entry, otherwise
- * the tunnel entry cannot be reused.
- */
- if (!flow_info->tun_i_cnt &&
- flow_info->state != BNXT_ULP_FLOW_STATE_TUN_O_OFFLD) {
- memset(tun_entry, 0,
- sizeof(struct bnxt_tun_cache_entry));
- for (j = 0; j < RTE_MAX_ETHPORTS; j++)
- STAILQ_INIT(&flow_info->tun_i_prms_list);
- }
- return true;
- }
- }
+ struct bnxt_tun_cache_entry *tun_entry;
+ uint16_t tun_idx;
+ int32_t rc = BNXT_TF_RC_SUCCESS;
- return false;
-}
+ /* Perform the tunnel offload only for F1 and F2 flows */
+ if (!ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
+ BNXT_ULP_HDR_BIT_F1) &&
+ !ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
+ BNXT_ULP_HDR_BIT_F2))
+ return rc;
-/* When a dpdk application offloads the same tunnel inner flow
- * on all the uplink ports, a tunnel inner flow entry is cached
- * even if it is not for the right uplink port. Such tunnel
- * inner flows will eventually get aged out as there won't be
- * any traffic on these ports. When such a flow destroy is
- * called, cleanup the tunnel inner flow entry.
- */
-void
-ulp_clear_tun_inner_entry(struct bnxt_tun_cache_entry *tun_tbl, uint32_t fid)
-{
- struct ulp_per_port_flow_info *flow_info;
- int i, j;
+ /* search for the tunnel entry if not found create one */
+ rc = ulp_get_tun_entry(params, &tun_entry, &tun_idx);
+ if (rc == BNXT_TF_RC_ERROR)
+ return rc;
- for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {
- if (!tun_tbl[i].t_dst_ip_valid)
- continue;
- for (j = 0; j < RTE_MAX_ETHPORTS; j++) {
- flow_info = &tun_tbl[i].tun_flow_info[j];
- if (ulp_chk_and_rem_tun_i_flow(&tun_tbl[i],
- flow_info, fid) == true)
- return;
- }
+ /* Tunnel offload for the outer Tunnel flow */
+ if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
+ BNXT_ULP_HDR_BIT_F1)) {
+ /* Reset the JUMP action bit in the action bitmap as we don't
+ * offload this action.
+ */
+ ULP_BITMAP_RESET(params->act_bitmap.bits,
+ BNXT_ULP_ACT_BIT_JUMP);
+ params->parent_flow = true;
+ params->tun_idx = tun_idx;
+ tun_entry->outer_tun_flow_id = params->fid;
+ } else if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
+ BNXT_ULP_HDR_BIT_F2)) {
+ ULP_BITMAP_RESET(params->hdr_bitmap.bits,
+ BNXT_ULP_HDR_BIT_F2);
+ /* add the vxlan decap action for F2 flows */
+ ULP_BITMAP_SET(params->act_bitmap.bits,
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP);
+ params->child_flow = true;
+ params->tun_idx = tun_idx;
+ params->parent_flow = false;
}
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_TUNNEL_ID, tun_idx);
+ return rc;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.h b/drivers/net/bnxt/tf_ulp/ulp_tun.h
index 898071bfe7..0fc2ac39d1 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_tun.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_tun.h
@@ -8,7 +8,6 @@
#include <inttypes.h>
#include <stdbool.h>
-#include <sys/queue.h>
#include "rte_version.h"
#include "rte_ethdev.h"
@@ -16,60 +15,6 @@
#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
-#define BNXT_OUTER_TUN_FLOW(l3_tun, params) \
- ((l3_tun) && \
- ULP_BITMAP_ISSET((params)->act_bitmap.bits, \
- BNXT_ULP_ACT_BIT_JUMP))
-#define BNXT_INNER_TUN_SIGNATURE(l3_tun, l3_tun_decap, params) \
- ((l3_tun) && (l3_tun_decap) && \
- !ULP_BITMAP_ISSET((params)->hdr_bitmap.bits, \
- BNXT_ULP_HDR_BIT_O_ETH))
-
-#define BNXT_CACHE_INNER_TUN_FLOW(state, inner_tun_sig) \
- ((state) == BNXT_ULP_FLOW_STATE_NORMAL && (inner_tun_sig))
-#define BNXT_INNER_TUN_FLOW(state, inner_tun_sig) \
- ((state) == BNXT_ULP_FLOW_STATE_TUN_O_OFFLD && (inner_tun_sig))
-
-/* It is invalid to get another outer flow offload request
- * for the same tunnel, while the outer flow is already offloaded.
- */
-#define BNXT_REJECT_OUTER_TUN_FLOW(state, outer_tun_sig) \
- ((state) == BNXT_ULP_FLOW_STATE_TUN_O_OFFLD && (outer_tun_sig))
-
-#define ULP_TUN_O_DMAC_HDR_FIELD_INDEX 1
-#define ULP_TUN_O_IPV4_DIP_INDEX 19
-#define ULP_TUN_O_IPV6_DIP_INDEX 17
-
-/* When a flow offload request comes the following state transitions
- * happen based on the order in which the outer & inner flow offload
- * requests arrive.
- *
- * If inner tunnel flow offload request arrives first then the flow
- * state will remain in BNXT_ULP_FLOW_STATE_NORMAL state.
- * The following outer tunnel flow offload request will change the
- * state of the flow to BNXT_ULP_FLOW_STATE_TUN_O_OFFLD from
- * BNXT_ULP_FLOW_STATE_NORMAL.
- *
- * If outer tunnel flow offload request arrives first then the flow state
- * will change from BNXT_ULP_FLOW_STATE_NORMAL to
- * BNXT_ULP_FLOW_STATE_TUN_O_OFFLD.
- *
- * Once the flow state is in BNXT_ULP_FLOW_STATE_TUN_O_OFFLD, any inner
- * tunnel flow offload requests after that point will be treated as a
- * normal flow and the tunnel flow state remains in
- * BNXT_ULP_FLOW_STATE_TUN_O_OFFLD
- */
-enum bnxt_ulp_tun_flow_state {
- BNXT_ULP_FLOW_STATE_NORMAL = 0,
- BNXT_ULP_FLOW_STATE_TUN_O_OFFLD,
-};
-
-struct ulp_per_port_flow_info {
- enum bnxt_ulp_tun_flow_state state;
- uint32_t tun_i_cnt;
- STAILQ_HEAD(, ulp_rte_parser_params) tun_i_prms_list;
-};
-
struct bnxt_tun_cache_entry {
bool t_dst_ip_valid;
uint8_t t_dmac[RTE_ETHER_ADDR_LEN];
@@ -78,17 +23,39 @@ struct bnxt_tun_cache_entry {
uint8_t t_dst_ip6[16];
};
uint32_t outer_tun_flow_id;
- uint16_t outer_tun_rej_cnt;
- struct ulp_per_port_flow_info tun_flow_info[RTE_MAX_ETHPORTS];
};
-void
-ulp_tun_tbl_init(struct bnxt_tun_cache_entry *tun_tbl);
+struct bnxt_flow_app_tun_ent {
+ struct rte_flow_tunnel app_tunnel;
+ uint32_t tun_id;
+ uint32_t ref_cnt;
+ struct rte_flow_action action;
+ struct rte_flow_item item;
+};
+
+int32_t
+ulp_app_tun_search_entry(struct bnxt_ulp_context *ulp_ctx,
+ struct rte_flow_tunnel *app_tunnel,
+ struct bnxt_flow_app_tun_ent **tun_entry);
void
-ulp_clear_tun_entry(struct bnxt_tun_cache_entry *tun_tbl, uint8_t tun_idx);
+ulp_app_tun_entry_delete(struct bnxt_flow_app_tun_ent *tun_entry);
+int32_t
+ulp_app_tun_entry_set_decap_action(struct bnxt_flow_app_tun_ent *tun_entry);
+
+int32_t
+ulp_app_tun_entry_set_decap_item(struct bnxt_flow_app_tun_ent *tun_entry);
+
+struct bnxt_flow_app_tun_ent *
+ulp_app_tun_match_entry(struct bnxt_ulp_context *ulp_ctx, const void *ctx);
+
+/* Tunnel API to delete the tunnel entry */
void
-ulp_clear_tun_inner_entry(struct bnxt_tun_cache_entry *tun_tbl, uint32_t fid);
+ulp_tunnel_offload_entry_clear(struct bnxt_tun_cache_entry *tun_tbl,
+ uint8_t tun_idx);
+
+int32_t
+ulp_tunnel_offload_process(struct ulp_rte_parser_params *params);
#endif
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v2 07/13] net/bnxt: add support for dynamic encap action
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 00/13] enhancements to host based flow table management Venkat Duvvuru
` (5 preceding siblings ...)
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 06/13] net/bnxt: add support for tunnel offloads Venkat Duvvuru
@ 2021-09-08 5:06 ` Venkat Duvvuru
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 08/13] net/bnxt: add wild card TCAM byte order for Thor Venkat Duvvuru
` (7 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-08 5:06 UTC (permalink / raw)
To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
The encapsulation record processing is enhanced to handle data
dynamically. Different combinations of VXLAN encapsulation using
no VLAN or single or double VLAN can be supported and also supports
both IPv4 and IPv6 versions.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
---
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 25 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 2 +
.../generic_templates/ulp_template_db_enum.h | 44 +-
.../generic_templates/ulp_template_db_tbl.c | 8 +-
.../ulp_template_db_thor_act.c | 4 +-
.../ulp_template_db_thor_class.c | 46 +-
.../ulp_template_db_wh_plus_act.c | 1700 ++++++++++++-----
.../ulp_template_db_wh_plus_class.c | 222 +--
drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 6 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 2 +-
drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 152 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.h | 4 +
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 337 ++--
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 2 +
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 10 +-
drivers/net/bnxt/tf_ulp/ulp_utils.c | 73 +-
drivers/net/bnxt/tf_ulp/ulp_utils.h | 27 +-
18 files changed, 1717 insertions(+), 949 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index dfafd9ff5b..3b86410fb1 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -830,13 +830,12 @@ ulp_ctx_init(struct bnxt *bp,
goto error_deinit;
}
- /* TODO: For now we are overriding to APP:1 on this branch*/
- bp->app_id = 1;
rc = bnxt_ulp_cntxt_app_id_set(bp->ulp_ctx, bp->app_id);
if (rc) {
BNXT_TF_DBG(ERR, "Unable to set app_id for ULP init.\n");
goto error_deinit;
}
+ BNXT_TF_DBG(DEBUG, "Ulp initialized with app id %d\n", bp->app_id);
rc = bnxt_ulp_cntxt_app_caps_init(bp->ulp_ctx, bp->app_id, devid);
if (rc) {
@@ -1393,13 +1392,17 @@ bnxt_ulp_port_init(struct bnxt *bp)
uint32_t ulp_flags;
int32_t rc = 0;
- if (!bp || !BNXT_TRUFLOW_EN(bp))
- return rc;
-
if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
BNXT_TF_DBG(ERR,
"Skip ulp init for port: %d, not a TVF or PF\n",
- bp->eth_dev->data->port_id);
+ bp->eth_dev->data->port_id);
+ return rc;
+ }
+
+ if (!BNXT_TRUFLOW_EN(bp)) {
+ BNXT_TF_DBG(ERR,
+ "Skip ulp init for port: %d, truflow is not enabled\n",
+ bp->eth_dev->data->port_id);
return rc;
}
@@ -1520,9 +1523,6 @@ bnxt_ulp_port_deinit(struct bnxt *bp)
struct rte_pci_device *pci_dev;
struct rte_pci_addr *pci_addr;
- if (!BNXT_TRUFLOW_EN(bp))
- return;
-
if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
BNXT_TF_DBG(ERR,
"Skip ULP deinit port:%d, not a TVF or PF\n",
@@ -1530,6 +1530,13 @@ bnxt_ulp_port_deinit(struct bnxt *bp)
return;
}
+ if (!BNXT_TRUFLOW_EN(bp)) {
+ BNXT_TF_DBG(ERR,
+ "Skip ULP deinit for port:%d, truflow is not enabled\n",
+ bp->eth_dev->data->port_id);
+ return;
+ }
+
if (!bp->ulp_ctx) {
BNXT_TF_DBG(DEBUG, "ulp ctx already de-allocated\n");
return;
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
index 3daf5942e8..413e4c3b26 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
@@ -96,7 +96,9 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms,
mapper_cparms->act_tid = params->act_tmpl;
mapper_cparms->func_id = params->func_id;
mapper_cparms->hdr_bitmap = ¶ms->hdr_bitmap;
+ mapper_cparms->enc_hdr_bitmap = ¶ms->enc_hdr_bitmap;
mapper_cparms->hdr_field = params->hdr_field;
+ mapper_cparms->enc_field = params->enc_field;
mapper_cparms->comp_fld = params->comp_fld;
mapper_cparms->act = ¶ms->act_bitmap;
mapper_cparms->act_prop = ¶ms->act_prop;
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
index e55d0923a5..9010d9a749 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 20 11:56:39 2021 */
+/* date: Thu May 27 17:35:19 2021 */
#ifndef ULP_TEMPLATE_DB_H_
#define ULP_TEMPLATE_DB_H_
@@ -41,7 +41,7 @@
#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 89
#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 600
#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 26
-#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 619
+#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 618
#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 49
#define ULP_THOR_CLASS_TMPL_LIST_SIZE 6
#define ULP_THOR_CLASS_TBL_LIST_SIZE 33
@@ -53,7 +53,7 @@
#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 35
#define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2
#define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 1
-#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 512
+#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 527
#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 39
#define ULP_THOR_ACT_TMPL_LIST_SIZE 7
#define ULP_THOR_ACT_TBL_LIST_SIZE 2
@@ -229,7 +229,9 @@ enum bnxt_ulp_cond_opc {
BNXT_ULP_COND_OPC_ACT_PAT_MATCH = 11,
BNXT_ULP_COND_OPC_EXT_MEM_IS_SET = 12,
BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET = 13,
- BNXT_ULP_COND_OPC_LAST = 14
+ BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET = 14,
+ BNXT_ULP_COND_OPC_ENC_HDR_BIT_NOT_SET = 15,
+ BNXT_ULP_COND_OPC_LAST = 16
};
enum bnxt_ulp_critical_resource {
@@ -257,6 +259,36 @@ enum bnxt_ulp_direction {
BNXT_ULP_DIRECTION_LAST = 2
};
+enum bnxt_ulp_enc_field {
+ BNXT_ULP_ENC_FIELD_ETH_DMAC = 0,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC = 1,
+ BNXT_ULP_ENC_FIELD_ETH_TYPE = 2,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TCI = 3,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TYPE = 4,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TCI = 5,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TYPE = 6,
+ BNXT_ULP_ENC_FIELD_IPV4_IHL = 7,
+ BNXT_ULP_ENC_FIELD_IPV4_TOS = 8,
+ BNXT_ULP_ENC_FIELD_IPV4_PKT_ID = 9,
+ BNXT_ULP_ENC_FIELD_IPV4_FRAG = 10,
+ BNXT_ULP_ENC_FIELD_IPV4_TTL = 11,
+ BNXT_ULP_ENC_FIELD_IPV4_PROTO = 12,
+ BNXT_ULP_ENC_FIELD_IPV4_SADDR = 13,
+ BNXT_ULP_ENC_FIELD_IPV4_DADDR = 14,
+ BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW = 15,
+ BNXT_ULP_ENC_FIELD_IPV6_PROTO = 16,
+ BNXT_ULP_ENC_FIELD_IPV6_TTL = 17,
+ BNXT_ULP_ENC_FIELD_IPV6_SADDR = 18,
+ BNXT_ULP_ENC_FIELD_IPV6_DADDR = 19,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT = 20,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT = 21,
+ BNXT_ULP_ENC_FIELD_VXLAN_FLAGS = 22,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 = 23,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI = 24,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 = 25,
+ BNXT_ULP_ENC_FIELD_LAST = 26
+};
+
enum bnxt_ulp_fdb_opc {
BNXT_ULP_FDB_OPC_PUSH_FID = 0,
BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE = 1,
@@ -304,7 +336,9 @@ enum bnxt_ulp_field_src {
BNXT_ULP_FIELD_SRC_SKIP = 13,
BNXT_ULP_FIELD_SRC_REJECT = 14,
BNXT_ULP_FIELD_SRC_PORT_TABLE = 15,
- BNXT_ULP_FIELD_SRC_LAST = 16
+ BNXT_ULP_FIELD_SRC_ENC_HDR_BIT = 16,
+ BNXT_ULP_FIELD_SRC_ENC_FIELD = 17,
+ BNXT_ULP_FIELD_SRC_LAST = 18
};
enum bnxt_ulp_func_opc {
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
index 58b4dba63c..b5bce6f4c7 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
@@ -198,7 +198,9 @@ const struct bnxt_ulp_template_device_tbls ulp_template_thor_tbls[] = {
struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
[BNXT_ULP_DEVICE_ID_WH_PLUS] = {
.description = "Whitney_Plus",
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .encap_byte_order = BNXT_ULP_BYTE_ORDER_BE,
.encap_byte_swap = 1,
.int_flow_db_num_entries = 16384,
.ext_flow_db_num_entries = 32768,
@@ -218,7 +220,9 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
},
[BNXT_ULP_DEVICE_ID_THOR] = {
.description = "Thor",
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .encap_byte_order = BNXT_ULP_BYTE_ORDER_BE,
.encap_byte_swap = 1,
.int_flow_db_num_entries = 16384,
.ext_flow_db_num_entries = 32768,
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
index ce5a70b0c5..9faf25aaf0 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 13 18:15:56 2021 */
+/* date: Wed May 26 15:11:34 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -41,7 +41,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 0,
.result_bit_size = 64,
.result_num_fields = 1
@@ -62,7 +61,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 1,
.result_bit_size = 128,
.result_num_fields = 17
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
index d20c4197fa..ea9b9773a5 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 20 11:56:39 2021 */
+/* date: Wed May 26 15:11:34 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -59,7 +59,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 0,
.blob_key_bit_size = 10,
.key_bit_size = 10,
@@ -82,7 +81,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 1,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -104,7 +102,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 2,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -122,8 +119,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_start_idx = 5,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 1, , table: l2_cntxt_tcam.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -141,7 +137,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 7,
.blob_key_bit_size = 213,
.key_bit_size = 213,
@@ -166,7 +161,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 28,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -189,7 +183,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 33,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -207,8 +200,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_start_idx = 6,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 1, , table: fkb_select.l3_l4_wm */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -223,7 +215,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 10,
.result_bit_size = 106,
.result_num_fields = 106
@@ -246,7 +237,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 36,
.blob_key_bit_size = 94,
.key_bit_size = 94,
@@ -271,7 +261,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 79,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -297,7 +286,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_BE,
.key_start_idx = 82,
.blob_key_bit_size = 0,
.key_bit_size = 0,
@@ -322,7 +310,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 136,
.result_bit_size = 128,
.result_num_fields = 17
@@ -341,7 +328,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 196,
.blob_key_bit_size = 10,
.key_bit_size = 10,
@@ -364,7 +350,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 197,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -382,8 +367,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_start_idx = 9,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -403,7 +387,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 198,
.blob_key_bit_size = 213,
.key_bit_size = 213,
@@ -428,7 +411,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 219,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -450,7 +432,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 168,
.result_bit_size = 32,
.result_num_fields = 1
@@ -468,7 +449,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 169,
.result_bit_size = 32,
.result_num_fields = 1
@@ -482,8 +462,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 10,
.cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
{ /* class_tid: 4, , table: int_full_act_record.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -501,7 +480,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 170,
.result_bit_size = 128,
.result_num_fields = 17,
@@ -521,7 +499,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 220,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -539,8 +516,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_start_idx = 11,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -558,7 +534,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 221,
.blob_key_bit_size = 213,
.key_bit_size = 213,
@@ -582,7 +557,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 193,
.result_bit_size = 32,
.result_num_fields = 1
@@ -600,7 +574,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 194,
.result_bit_size = 32,
.result_num_fields = 1
@@ -621,7 +594,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 195,
.result_bit_size = 128,
.result_num_fields = 17,
@@ -640,7 +612,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 212,
.result_bit_size = 32,
.result_num_fields = 1
@@ -658,7 +629,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 213,
.result_bit_size = 32,
.result_num_fields = 1
@@ -679,7 +649,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 214,
.result_bit_size = 128,
.result_num_fields = 17,
@@ -701,7 +670,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .record_size = 16,
.result_start_idx = 231,
.result_bit_size = 0,
.result_num_fields = 0,
@@ -723,7 +692,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 242,
.result_bit_size = 128,
.result_num_fields = 17
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
index de924fe81a..578ede8bba 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Mon May 17 15:54:03 2021 */
+/* date: Tue Jun 1 16:05:30 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -90,7 +90,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 0,
.blob_key_bit_size = 1,
.key_bit_size = 1,
@@ -114,14 +113,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 0,
.result_bit_size = 64,
.result_num_fields = 1
},
{ /* act_tid: 1, , table: int_vtag_encap_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
.direction = TF_DIR_RX,
@@ -135,11 +133,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .record_size = 8,
.result_start_idx = 1,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 1, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -157,8 +155,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 13,
+ .result_start_idx = 12,
.result_bit_size = 128,
.result_num_fields = 26,
.encap_num_fields = 0
@@ -179,11 +176,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 39,
+ .result_start_idx = 38,
.result_bit_size = 128,
.result_num_fields = 26,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 2, , table: control.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
@@ -195,8 +191,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_start_idx = 14,
.cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* act_tid: 2, , table: mirror_tbl.alloc */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -215,8 +210,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 77,
+ .result_start_idx = 75,
.result_bit_size = 32,
.result_num_fields = 6
},
@@ -237,8 +231,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 83,
+ .result_start_idx = 81,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -259,8 +252,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 84,
+ .result_start_idx = 82,
.result_bit_size = 128,
.result_num_fields = 26,
.encap_num_fields = 0
@@ -282,11 +274,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 110,
+ .result_start_idx = 108,
.result_bit_size = 128,
.result_num_fields = 26,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 2, , table: mirror_tbl.wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -304,8 +295,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 148,
+ .result_start_idx = 145,
.result_bit_size = 32,
.result_num_fields = 6
},
@@ -324,12 +314,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 1,
.blob_key_bit_size = 1,
.key_bit_size = 1,
.key_num_fields = 1,
- .result_start_idx = 154,
+ .result_start_idx = 151,
.result_bit_size = 34,
.result_num_fields = 2
},
@@ -348,8 +337,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 156,
+ .result_start_idx = 153,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -368,8 +356,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 157,
+ .result_start_idx = 154,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -388,8 +375,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 158,
+ .result_start_idx = 155,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -408,11 +394,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 159,
+ .record_size = 16,
+ .result_start_idx = 156,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 3, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -429,8 +415,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 171,
+ .result_start_idx = 167,
.result_bit_size = 128,
.result_num_fields = 26
},
@@ -449,11 +434,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 197,
+ .result_start_idx = 193,
.result_bit_size = 128,
.result_num_fields = 26,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 4, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -470,8 +454,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 235,
+ .result_start_idx = 230,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -490,11 +473,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 236,
+ .record_size = 8,
+ .result_start_idx = 231,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 4, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -511,8 +494,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 248,
+ .result_start_idx = 242,
.result_bit_size = 128,
.result_num_fields = 26
},
@@ -531,11 +513,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 274,
+ .result_start_idx = 268,
.result_bit_size = 128,
.result_num_fields = 26,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 4, , table: ext_full_act_record.one_tag */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -552,11 +533,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 312,
+ .result_start_idx = 305,
.result_bit_size = 128,
.result_num_fields = 26,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 5, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -573,8 +553,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 350,
+ .result_start_idx = 342,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -593,8 +572,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 351,
+ .result_start_idx = 343,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -613,8 +591,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 352,
+ .result_start_idx = 344,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -633,11 +610,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 353,
+ .record_size = 16,
+ .result_start_idx = 345,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 5, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -654,8 +631,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 365,
+ .result_start_idx = 356,
.result_bit_size = 128,
.result_num_fields = 26
},
@@ -674,11 +650,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 391,
+ .result_start_idx = 382,
.result_bit_size = 128,
.result_num_fields = 26,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 6, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -695,8 +670,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 429,
+ .result_start_idx = 419,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -715,11 +689,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 430,
+ .record_size = 16,
+ .result_start_idx = 420,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 3
+ .encap_num_fields = 2
},
{ /* act_tid: 6, , table: sp_smac_ipv6.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -736,11 +710,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 433,
+ .record_size = 24,
+ .result_start_idx = 422,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 3
+ .encap_num_fields = 2
},
{ /* act_tid: 6, , table: int_tun_encap_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -757,11 +731,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 436,
+ .record_size = 64,
+ .result_start_idx = 424,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 12
+ .encap_num_fields = 30
},
{ /* act_tid: 6, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -778,8 +752,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 448,
+ .result_start_idx = 454,
.result_bit_size = 128,
.result_num_fields = 26
},
@@ -798,11 +771,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 474,
+ .result_start_idx = 480,
.result_bit_size = 128,
.result_num_fields = 26,
- .encap_num_fields = 12
+ .encap_num_fields = 30
}
};
@@ -1033,22 +1005,26 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
},
/* act_tid: 1, , table: int_vtag_encap_record.0 */
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
},
{
.description = "ecv_l2_en",
@@ -1057,26 +1033,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "vtag_tpid",
@@ -1088,13 +1060,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
},
{
.description = "vtag_de",
@@ -1103,19 +1075,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
- },
- {
- .description = "spare",
- .field_bit_size = 80,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
},
/* act_tid: 1, , table: int_full_act_record.0 */
{
@@ -1628,20 +1594,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -1649,25 +1617,23 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.description = "ecv_l2_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_L2_EN_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -1678,8 +1644,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -1690,14 +1656,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 0,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2105,20 +2065,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2126,25 +2088,23 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.description = "ecv_l2_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_L2_EN_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2155,8 +2115,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2167,14 +2127,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 0,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2268,20 +2222,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
},
/* act_tid: 3, , table: int_encap_mac_record.0 */
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2294,24 +2250,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
ULP_WP_SYM_ECV_L2_EN_YES}
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "vtag_tpid",
@@ -2320,8 +2274,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2332,14 +2286,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 80,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2806,20 +2754,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2827,25 +2777,23 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.description = "ecv_l2_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_L2_EN_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2856,8 +2804,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2868,14 +2816,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 0,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2888,23 +2830,27 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
},
/* act_tid: 4, , table: int_vtag_encap_record.0 */
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
+ },
{
.description = "ecv_l2_en",
.field_bit_size = 1,
@@ -2912,26 +2858,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "vtag_tpid",
@@ -2943,13 +2885,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
},
{
.description = "vtag_de",
@@ -2958,19 +2900,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
- },
- {
- .description = "spare",
- .field_bit_size = 80,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
},
/* act_tid: 4, , table: int_full_act_record.0 */
{
@@ -3350,20 +3286,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -3371,25 +3309,23 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.description = "ecv_l2_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_L2_EN_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -3400,8 +3336,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -3412,14 +3348,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 0,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -3620,22 +3550,26 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
},
{
.description = "ecv_l2_en",
@@ -3644,26 +3578,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "vtag_tpid",
@@ -3675,13 +3605,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
},
{
.description = "vtag_de",
@@ -3690,19 +3620,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
- },
- {
- .description = "spare",
- .field_bit_size = 0,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
},
/* act_tid: 5, , table: int_flow_counter_tbl.0 */
{
@@ -3733,20 +3657,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
},
/* act_tid: 5, , table: int_encap_mac_record.dummy */
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -3759,24 +3685,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
ULP_WP_SYM_ECV_L2_EN_YES}
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "vtag_tpid",
@@ -3785,8 +3709,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -3797,14 +3721,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 80,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -4271,20 +4189,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -4292,25 +4212,23 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.description = "ecv_l2_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_L2_EN_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -4321,8 +4239,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -4333,14 +4251,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 0,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -4356,76 +4268,62 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.description = "smac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC & 0xff}
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
},
{
.description = "ipv4_src_addr",
.field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC & 0xff}
- },
- {
- .description = "reserved",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}
},
/* act_tid: 6, , table: sp_smac_ipv6.0 */
{
.description = "smac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC & 0xff}
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
},
{
.description = "ipv6_src_addr",
.field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC & 0xff}
- },
- {
- .description = "reserved",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ENC_FIELD_IPV6_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_SADDR & 0xff}
},
/* act_tid: 6, , table: int_tun_encap_record.0 */
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ULP_WP_SYM_ECV_TUN_TYPE_VXLAN}
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
},
{
.description = "ecv_l2_en",
@@ -4433,81 +4331,478 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ ULP_WP_SYM_ECV_L2_EN_YES}
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM}
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ ULP_WP_SYM_ECV_TUN_TYPE_VXLAN}
},
{
- .description = "encap_l2_dmac",
+ .description = "enc_eth_dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC & 0xff}
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
},
{
- .description = "encap_vtag",
- .field_bit_size = 0,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ,
+ .description = "enc_o_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_o_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_ihl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_tos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_pkt_id",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_frag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_daddr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_vtc",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_zero",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG & 0xff,
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ZERO,
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
- .description = "encap_ip",
- .field_bit_size = 0,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ,
+ .description = "enc_ipv6_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_daddr",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_vxlan_flags",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_IP & 0xff,
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
- .description = "encap_udp",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .description = "enc_vxlan_rsvd0",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
- .description = "encap_tun",
- .field_bit_size = 0,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ,
+ .description = "enc_vxlan_vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN & 0xff,
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_vxlan_rsvd1",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
/* act_tid: 6, , table: int_full_act_record.0 */
{
@@ -4857,29 +5152,27 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ULP_WP_SYM_ECV_TUN_TYPE_VXLAN}
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
},
{
.description = "ecv_l2_en",
@@ -4887,79 +5180,478 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ ULP_WP_SYM_ECV_L2_EN_YES}
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM}
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ ULP_WP_SYM_ECV_TUN_TYPE_VXLAN}
},
{
- .description = "encap_l2_dmac",
+ .description = "enc_eth_dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC & 0xff}
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
},
{
- .description = "encap_vtag",
- .field_bit_size = 0,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ,
+ .description = "enc_o_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_o_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_ihl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_tos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_pkt_id",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_frag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_daddr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_vtc",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_zero",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG & 0xff,
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ZERO,
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
- .description = "encap_ip",
- .field_bit_size = 0,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ,
+ .description = "enc_ipv6_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_daddr",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_vxlan_flags",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_vxlan_rsvd0",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_IP & 0xff,
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
- .description = "encap_udp",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .description = "enc_vxlan_vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
- .description = "encap_tun",
- .field_bit_size = 80,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .description = "enc_vxlan_rsvd1",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
index 7b6ee03a4b..7203dcf1fb 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Mon May 17 15:54:03 2021 */
+/* date: Fri May 28 16:46:46 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -80,7 +80,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 0,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -102,7 +101,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 1,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -120,8 +118,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 2,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 1, , table: l2_cntxt_tcam.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -139,7 +136,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 6,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -164,7 +160,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 19,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -188,7 +183,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 24,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -206,8 +200,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 3,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 1, , table: control.2 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
@@ -225,8 +218,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
.func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
.func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
- .func_dst_opr = BNXT_ULP_RF_IDX_CC },
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
},
{ /* class_tid: 1, , table: profile_tcam.ipv4 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -244,7 +236,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 27,
.blob_key_bit_size = 81,
.key_bit_size = 81,
@@ -271,7 +262,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 70,
.blob_key_bit_size = 81,
.key_bit_size = 81,
@@ -298,7 +288,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 113,
.blob_key_bit_size = 81,
.key_bit_size = 81,
@@ -324,7 +313,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 156,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -346,7 +334,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 159,
.blob_key_bit_size = 176,
.key_bit_size = 176,
@@ -368,7 +355,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 169,
.blob_key_bit_size = 448,
.key_bit_size = 448,
@@ -390,7 +376,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 179,
.blob_key_bit_size = 416,
.key_bit_size = 416,
@@ -412,7 +397,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 190,
.blob_key_bit_size = 448,
.key_bit_size = 448,
@@ -434,7 +418,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 201,
.blob_key_bit_size = 200,
.key_bit_size = 200,
@@ -456,7 +439,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 212,
.blob_key_bit_size = 448,
.key_bit_size = 448,
@@ -479,7 +461,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 223,
.blob_key_bit_size = 16,
.key_bit_size = 16,
@@ -497,8 +478,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 25,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -516,7 +496,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 225,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -541,7 +520,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 238,
.blob_key_bit_size = 16,
.key_bit_size = 16,
@@ -559,8 +537,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 26,
.cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
{ /* class_tid: 2, , table: mac_addr_cache.rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
@@ -576,7 +553,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 240,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -594,8 +570,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 27,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 2, , table: l2_cntxt_tcam.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -613,7 +588,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 245,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -638,7 +612,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 258,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -662,7 +635,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 263,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -680,8 +652,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 28,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 2, , table: profile_tcam.f2 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -701,7 +672,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_operand = 1,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 266,
.blob_key_bit_size = 81,
.key_bit_size = 81,
@@ -725,7 +695,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 309,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -747,7 +716,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 312,
.blob_key_bit_size = 112,
.key_bit_size = 112,
@@ -769,7 +737,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 320,
.blob_key_bit_size = 448,
.key_bit_size = 448,
@@ -792,7 +759,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 328,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -814,7 +780,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 329,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -832,8 +797,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 32,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 3, , table: l2_cntxt_tcam.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -851,7 +815,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 334,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -876,7 +839,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 347,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -899,7 +861,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 352,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -917,8 +878,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 33,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 3, , table: control.conflict_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
@@ -936,8 +896,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
.func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
.func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
- .func_dst_opr = BNXT_ULP_RF_IDX_CC },
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
},
{ /* class_tid: 3, , table: profile_tcam.ipv4 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -955,7 +914,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 355,
.blob_key_bit_size = 81,
.key_bit_size = 81,
@@ -982,7 +940,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 398,
.blob_key_bit_size = 81,
.key_bit_size = 81,
@@ -1007,7 +964,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 441,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -1029,7 +985,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 444,
.blob_key_bit_size = 176,
.key_bit_size = 176,
@@ -1051,7 +1006,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 454,
.blob_key_bit_size = 448,
.key_bit_size = 448,
@@ -1073,7 +1027,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 464,
.blob_key_bit_size = 416,
.key_bit_size = 416,
@@ -1095,7 +1048,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 475,
.blob_key_bit_size = 448,
.key_bit_size = 448,
@@ -1120,7 +1072,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 292,
.result_bit_size = 128,
.result_num_fields = 26
@@ -1139,7 +1090,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 486,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1157,8 +1107,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 41,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1178,7 +1127,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 487,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -1203,7 +1151,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 500,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1225,7 +1172,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 335,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1243,7 +1189,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 336,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1261,7 +1206,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 337,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1275,8 +1219,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 42,
.cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
{ /* class_tid: 4, , table: int_full_act_record.egr_vfr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1294,7 +1237,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 338,
.result_bit_size = 128,
.result_num_fields = 26,
@@ -1314,7 +1256,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 501,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1332,8 +1273,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 43,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 4, , table: l2_cntxt_tcam_bypass.egr_vfr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1351,7 +1291,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 502,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -1376,7 +1315,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 515,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1399,7 +1337,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 516,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1417,8 +1354,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 44,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1436,7 +1372,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 517,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -1461,7 +1396,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 530,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1486,7 +1420,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 398,
.result_bit_size = 128,
.result_num_fields = 26,
@@ -1505,7 +1438,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 424,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1523,7 +1455,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 425,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1541,7 +1472,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 426,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1562,7 +1492,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 427,
.result_bit_size = 128,
.result_num_fields = 26,
@@ -1582,7 +1511,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 531,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1600,8 +1528,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 47,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1619,7 +1546,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 532,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -1644,7 +1570,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 545,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1666,7 +1591,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 470,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1684,7 +1608,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 471,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1702,7 +1625,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 472,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1723,7 +1645,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 473,
.result_bit_size = 128,
.result_num_fields = 26,
@@ -1746,7 +1667,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 546,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -1771,7 +1691,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 559,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1789,8 +1708,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 48,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_egr0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1808,7 +1726,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 560,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -1833,7 +1750,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 573,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1858,11 +1774,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .record_size = 8,
.result_start_idx = 529,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1880,8 +1796,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 541,
+ .result_start_idx = 540,
.result_bit_size = 128,
.result_num_fields = 26
},
@@ -1901,8 +1816,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 567,
+ .result_start_idx = 566,
.result_bit_size = 128,
.result_num_fields = 26
},
@@ -1923,12 +1837,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 574,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 593,
+ .result_start_idx = 592,
.result_bit_size = 64,
.result_num_fields = 13,
.ident_start_idx = 26,
@@ -1951,12 +1864,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 587,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 606,
+ .result_start_idx = 605,
.result_bit_size = 64,
.result_num_fields = 13,
.ident_start_idx = 26,
@@ -2522,17 +2434,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -6207,17 +6115,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -8046,17 +7950,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -16093,22 +15993,26 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
},
/* class_tid: 5, , table: int_vtag_encap_record.vfr_egr0 */
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
},
{
.description = "ecv_l2_en",
@@ -16117,26 +16021,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "vtag_tpid",
@@ -16148,13 +16048,10 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
0x00}
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "vtag_de",
@@ -16163,16 +16060,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 80,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
},
/* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
{
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
index 039c9c2a6b..1cb52e9bfa 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
@@ -116,7 +116,7 @@ ulp_flow_db_resource_func_get(struct ulp_fdb_resource_info *res_info)
func = (((res_info->nxt_resource_idx & ULP_FLOW_DB_RES_FUNC_MASK) >>
ULP_FLOW_DB_RES_FUNC_BITS) << ULP_FLOW_DB_RES_FUNC_UPPER);
- /* The reource func is split into upper and lower */
+ /* The resource func is split into upper and lower */
if (func & ULP_FLOW_DB_RES_FUNC_NEED_LOWER)
return (func | res_info->resource_func_lower);
return func;
@@ -622,7 +622,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt,
if (params->critical_resource && fid_resource->resource_em_handle) {
BNXT_TF_DBG(DEBUG, "Ignore multiple critical resources\n");
- /* Ignore the multiple criticial resources */
+ /* Ignore the multiple critical resources */
params->critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO;
}
@@ -674,7 +674,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt,
* flow_type [in] Specify it is regular or default flow
* fid [in] The index to the flow entry
* params [in/out] The contents to be copied into params.
- * Onlythe critical_resource needs to be set by the caller.
+ * Only the critical_resource needs to be set by the caller.
*
* Returns 0 on success and negative on failure.
*/
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
index 8680ee8f65..6dbec92745 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
@@ -18,7 +18,7 @@
/*
* Structure for the flow database resource information
- * The below structure is based on the below paritions
+ * The below structure is based on the below partitions
* nxt_resource_idx = dir[31],resource_func_upper[30:28],nxt_resource_idx[27:0]
* If resource_func is EM_TBL then use resource_em_handle.
* Else the other part of the union is used and
diff --git a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
index bc5627ec5b..5f5b5d639e 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
@@ -185,7 +185,7 @@ ulp_ha_mgr_timer_cb(void *arg __rte_unused)
rc = ulp_ha_mgr_state_get(ulp_ctx, &curr_state);
if (rc) {
/*
- * This shouldn't happen, if it does, resetart the timer
+ * This shouldn't happen, if it does, reset the timer
* and try again next time.
*/
BNXT_TF_DBG(ERR, "Failed(%d) to get state.\n",
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 6d804c7ef9..2687a545f3 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -1010,7 +1010,7 @@ ulp_mapper_field_src_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
idx = tfp_be_to_cpu_16(idx);
- if (idx >= BNXT_ULP_CF_IDX_LAST || bytelen > sizeof(uint32_t)) {
+ if (idx >= BNXT_ULP_CF_IDX_LAST || bytelen > sizeof(uint64_t)) {
BNXT_TF_DBG(ERR, "comp field [%d] read oob %d\n", idx,
bytelen);
return -EINVAL;
@@ -1215,8 +1215,47 @@ ulp_mapper_field_src_process(struct bnxt_ulp_mapper_parms *parms,
BNXT_TF_DBG(ERR, "field port table failed\n");
return -EINVAL;
}
+ break;
+ case BNXT_ULP_FIELD_SRC_ENC_HDR_BIT:
+ if (!ulp_operand_read(field_opr,
+ (uint8_t *)&lregval, sizeof(uint64_t))) {
+ BNXT_TF_DBG(ERR, "Header bit read failed\n");
+ return -EINVAL;
+ }
+ lregval = tfp_be_to_cpu_64(lregval);
+ if (ULP_BITMAP_ISSET(parms->enc_hdr_bitmap->bits, lregval)) {
+ *val = mapper_fld_one;
+ *value = 1;
+ } else {
+ *val = mapper_fld_zeros;
+ }
+ break;
+ case BNXT_ULP_FIELD_SRC_ENC_FIELD:
+ if (!ulp_operand_read(field_opr,
+ (uint8_t *)&idx, sizeof(uint16_t))) {
+ BNXT_TF_DBG(ERR, "Header field read failed\n");
+ return -EINVAL;
+ }
+ idx = tfp_be_to_cpu_16(idx);
+ /* get the index from the global field list */
+ if (idx >= BNXT_ULP_ENC_FIELD_LAST) {
+ BNXT_TF_DBG(ERR, "invalid encap field tbl idx %d\n",
+ idx);
+ return -EINVAL;
+ }
+ buffer = parms->enc_field[idx].spec;
+ field_size = parms->enc_field[idx].size;
+ if (bytelen > field_size) {
+ BNXT_TF_DBG(ERR, "Encap field[%d] size small %u\n",
+ idx, field_size);
+ return -EINVAL;
+ }
+ *val = &buffer[field_size - bytelen];
+ break;
case BNXT_ULP_FIELD_SRC_SKIP:
/* do nothing */
+ *val = mapper_fld_zeros;
+ *val_len = 0;
break;
case BNXT_ULP_FIELD_SRC_REJECT:
return -EINVAL;
@@ -1270,6 +1309,8 @@ static int32_t ulp_mapper_field_blob_write(enum bnxt_ulp_field_src fld_src,
BNXT_TF_DBG(ERR, "encap blob push failed\n");
return -EINVAL;
}
+ } else if (fld_src == BNXT_ULP_FIELD_SRC_SKIP) {
+ /* do nothing */
} else {
if (!ulp_blob_push(blob, val, val_len)) {
BNXT_TF_DBG(ERR, "push of val1 failed\n");
@@ -1465,7 +1506,7 @@ ulp_mapper_field_opc_process(struct bnxt_ulp_mapper_parms *parms,
if (!rc) {
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
- if (fld->field_src1 != BNXT_ULP_FIELD_SRC_ZERO)
+ if (fld->field_src1 != BNXT_ULP_FIELD_SRC_ZERO && val_len)
ulp_mapper_field_dump(name, fld, blob, write_idx, val,
val_len);
#endif
@@ -1489,7 +1530,8 @@ ulp_mapper_tbl_result_build(struct bnxt_ulp_mapper_parms *parms,
const char *name)
{
struct bnxt_ulp_mapper_field_info *dflds;
- uint32_t i, num_flds = 0, encap_flds = 0;
+ uint32_t i = 0, num_flds = 0, encap_flds = 0;
+ struct ulp_blob encap_blob;
int32_t rc = 0;
/* Get the result field list */
@@ -1506,33 +1548,60 @@ ulp_mapper_tbl_result_build(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
- /* process the result fields, loop through them */
- for (i = 0; i < (num_flds + encap_flds); i++) {
- /* set the swap index if encap swap bit is enabled */
- if (parms->device_params->encap_byte_swap && encap_flds &&
- i == num_flds)
- ulp_blob_encap_swap_idx_set(data);
-
- /* Process the result fields */
+ /* process the result fields */
+ for (i = 0; i < num_flds; i++) {
rc = ulp_mapper_field_opc_process(parms, tbl->direction,
&dflds[i], data, 0, name);
if (rc) {
- BNXT_TF_DBG(ERR, "data field failed\n");
+ BNXT_TF_DBG(ERR, "result field processing failed\n");
return rc;
}
}
- /* if encap bit swap is enabled perform the bit swap */
- if (parms->device_params->encap_byte_swap && encap_flds) {
- ulp_blob_perform_encap_swap(data);
+ /* process encap fields if any */
+ if (encap_flds) {
+ uint32_t pad = 0;
+ /* Initialize the encap blob */
+ if (!tbl->record_size) {
+ BNXT_TF_DBG(ERR, "Encap tbl record size incorrect\n");
+ return -EINVAL;
+ }
+ if (!ulp_blob_init(&encap_blob,
+ ULP_BYTE_2_BITS(tbl->record_size),
+ parms->device_params->encap_byte_order)) {
+ BNXT_TF_DBG(ERR, "blob inits failed.\n");
+ return -EINVAL;
+ }
+ for (; i < encap_flds; i++) {
+ rc = ulp_mapper_field_opc_process(parms, tbl->direction,
+ &dflds[i],
+ &encap_blob, 0, name);
+ if (rc) {
+ BNXT_TF_DBG(ERR,
+ "encap field processing failed\n");
+ return rc;
+ }
+ }
+ /* add the dynamic pad push */
+ pad = ULP_BYTE_2_BITS(tbl->record_size) -
+ ulp_blob_data_len_get(&encap_blob);
+ ulp_blob_pad_push(&encap_blob, pad);
+
+ /* perform the 64 bit byte swap */
+ ulp_blob_perform_64B_byte_swap(&encap_blob);
+ /* Append encap blob to the result blob */
+ rc = ulp_blob_buffer_copy(data, &encap_blob);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "encap buffer copy failed\n");
+ return rc;
+ }
+ }
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
- BNXT_TF_DBG(INFO, "Dump after encap swap\n");
- ulp_mapper_blob_dump(data);
+ BNXT_TF_DBG(DEBUG, "Result dump\n");
+ ulp_mapper_blob_dump(data);
#endif
#endif
- }
-
return rc;
}
@@ -1934,11 +2003,14 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
- if (!ulp_blob_init(key, tbl->blob_key_bit_size, tbl->byte_order) ||
- !ulp_blob_init(mask, tbl->blob_key_bit_size, tbl->byte_order) ||
- !ulp_blob_init(&data, tbl->result_bit_size, dparms->byte_order) ||
+ if (!ulp_blob_init(key, tbl->blob_key_bit_size,
+ dparms->key_byte_order) ||
+ !ulp_blob_init(mask, tbl->blob_key_bit_size,
+ dparms->key_byte_order) ||
+ !ulp_blob_init(&data, tbl->result_bit_size,
+ dparms->result_byte_order) ||
!ulp_blob_init(&update_data, tbl->result_bit_size,
- dparms->byte_order)) {
+ dparms->result_byte_order)) {
BNXT_TF_DBG(ERR, "blob inits failed.\n");
return -EINVAL;
}
@@ -2145,9 +2217,9 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
/* Initialize the key/result blobs */
if (!ulp_blob_init(&key, tbl->blob_key_bit_size,
- tbl->byte_order) ||
+ dparms->key_byte_order) ||
!ulp_blob_init(&data, tbl->result_bit_size,
- tbl->byte_order)) {
+ dparms->result_byte_order)) {
BNXT_TF_DBG(ERR, "blob inits failed.\n");
return -EINVAL;
}
@@ -2336,7 +2408,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
/* Initialize the blob data */
if (!ulp_blob_init(&data, bit_size,
- parms->device_params->byte_order)) {
+ parms->device_params->result_byte_order)) {
BNXT_TF_DBG(ERR, "Failed to initialize index table blob\n");
return -EINVAL;
}
@@ -2627,7 +2699,7 @@ ulp_mapper_if_tbl_process(struct bnxt_ulp_mapper_parms *parms,
tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session);
/* Initialize the blob data */
if (!ulp_blob_init(&data, tbl->result_bit_size,
- parms->device_params->byte_order)) {
+ parms->device_params->result_byte_order)) {
BNXT_TF_DBG(ERR, "Failed initial index table blob\n");
return -EINVAL;
}
@@ -2658,7 +2730,7 @@ ulp_mapper_if_tbl_process(struct bnxt_ulp_mapper_parms *parms,
case BNXT_ULP_IF_TBL_OPC_RD_COMP_FIELD:
/* Initialize the result blob */
if (!ulp_blob_init(&res_blob, tbl->result_bit_size,
- parms->device_params->byte_order)) {
+ parms->device_params->result_byte_order)) {
BNXT_TF_DBG(ERR, "Failed initial result blob\n");
return -EINVAL;
}
@@ -2747,7 +2819,7 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms,
}
if (!ulp_blob_init(&key, tbl->key_bit_size,
- parms->device_params->byte_order)) {
+ parms->device_params->key_byte_order)) {
BNXT_TF_DBG(ERR, "Failed to alloc blob\n");
return -EINVAL;
}
@@ -3252,6 +3324,26 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms,
}
*res = (mtype == BNXT_ULP_FLOW_MEM_TYPE_INT) ? 1 : 0;
break;
+ case BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET:
+ if (operand < BNXT_ULP_HDR_BIT_LAST) {
+ *res = ULP_BITMAP_ISSET(parms->enc_hdr_bitmap->bits,
+ operand);
+ } else {
+ BNXT_TF_DBG(ERR, "header bit out of bounds %d\n",
+ operand);
+ rc = -EINVAL;
+ }
+ break;
+ case BNXT_ULP_COND_OPC_ENC_HDR_BIT_NOT_SET:
+ if (operand < BNXT_ULP_HDR_BIT_LAST) {
+ *res = !ULP_BITMAP_ISSET(parms->enc_hdr_bitmap->bits,
+ operand);
+ } else {
+ BNXT_TF_DBG(ERR, "header bit out of bounds %d\n",
+ operand);
+ rc = -EINVAL;
+ }
+ break;
default:
BNXT_TF_DBG(ERR, "Invalid conditional opcode %d\n", opc);
rc = -EINVAL;
@@ -3864,8 +3956,10 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
parms.act_prop = cparms->act_prop;
parms.act_bitmap = cparms->act;
parms.hdr_bitmap = cparms->hdr_bitmap;
+ parms.enc_hdr_bitmap = cparms->enc_hdr_bitmap;
parms.regfile = ®file;
parms.hdr_field = cparms->hdr_field;
+ parms.enc_field = cparms->enc_field;
parms.fld_bitmap = cparms->fld_bitmap;
parms.comp_fld = cparms->comp_fld;
parms.ulp_ctx = ulp_ctx;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
index d4d6969bb5..4d6ba0f73a 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
@@ -44,7 +44,9 @@ struct bnxt_ulp_mapper_parms {
struct ulp_rte_act_prop *act_prop;
struct ulp_rte_act_bitmap *act_bitmap;
struct ulp_rte_hdr_bitmap *hdr_bitmap;
+ struct ulp_rte_hdr_bitmap *enc_hdr_bitmap;
struct ulp_rte_hdr_field *hdr_field;
+ struct ulp_rte_hdr_field *enc_field;
struct ulp_rte_field_bitmap *fld_bitmap;
uint64_t *comp_fld;
struct ulp_regfile *regfile;
@@ -67,7 +69,9 @@ struct bnxt_ulp_mapper_parms {
struct bnxt_ulp_mapper_create_parms {
uint32_t app_priority;
struct ulp_rte_hdr_bitmap *hdr_bitmap;
+ struct ulp_rte_hdr_bitmap *enc_hdr_bitmap;
struct ulp_rte_hdr_field *hdr_field;
+ struct ulp_rte_hdr_field *enc_field;
uint64_t *comp_fld;
struct ulp_rte_act_bitmap *act;
struct ulp_rte_act_prop *act_prop;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index fadcd3873c..4e9968e5fa 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -40,6 +40,18 @@ ulp_rte_item_skip_void(const struct rte_flow_item **item, uint32_t increment)
return 0;
}
+/* Utility function to copy field spec items */
+static struct ulp_rte_hdr_field *
+ulp_rte_parser_fld_copy(struct ulp_rte_hdr_field *field,
+ const void *buffer,
+ uint32_t size)
+{
+ field->size = size;
+ memcpy(field->spec, buffer, field->size);
+ field++;
+ return field;
+}
+
/* Utility function to update the field_bitmap */
static void
ulp_rte_parser_field_bitmap_update(struct ulp_rte_parser_params *params,
@@ -883,7 +895,7 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
BNXT_ULP_HDR_BIT_II_VLAN);
inner_flag = 1;
} else {
- BNXT_TF_DBG(ERR, "Error Parsing:Vlan hdr found withtout eth\n");
+ BNXT_TF_DBG(ERR, "Error Parsing:Vlan hdr found without eth\n");
return BNXT_TF_RC_ERROR;
}
/* Update the field protocol hdr bitmap */
@@ -1726,6 +1738,184 @@ ulp_rte_rss_act_handler(const struct rte_flow_action *action_item,
return BNXT_TF_RC_SUCCESS;
}
+/* Function to handle the parsing of RTE Flow item eth Header. */
+static void
+ulp_rte_enc_eth_hdr_handler(struct ulp_rte_parser_params *params,
+ const struct rte_flow_item_eth *eth_spec)
+{
+ struct ulp_rte_hdr_field *field;
+ uint32_t size;
+
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_ETH_DMAC];
+ size = sizeof(eth_spec->dst.addr_bytes);
+ field = ulp_rte_parser_fld_copy(field, eth_spec->dst.addr_bytes, size);
+
+ size = sizeof(eth_spec->src.addr_bytes);
+ field = ulp_rte_parser_fld_copy(field, eth_spec->src.addr_bytes, size);
+
+ size = sizeof(eth_spec->type);
+ field = ulp_rte_parser_fld_copy(field, ð_spec->type, size);
+
+ ULP_BITMAP_SET(params->enc_hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_ETH);
+}
+
+/* Function to handle the parsing of RTE Flow item vlan Header. */
+static void
+ulp_rte_enc_vlan_hdr_handler(struct ulp_rte_parser_params *params,
+ const struct rte_flow_item_vlan *vlan_spec,
+ uint32_t inner)
+{
+ struct ulp_rte_hdr_field *field;
+ uint32_t size;
+
+ if (!inner) {
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_O_VLAN_TCI];
+ ULP_BITMAP_SET(params->enc_hdr_bitmap.bits,
+ BNXT_ULP_HDR_BIT_OO_VLAN);
+ } else {
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_I_VLAN_TCI];
+ ULP_BITMAP_SET(params->enc_hdr_bitmap.bits,
+ BNXT_ULP_HDR_BIT_OI_VLAN);
+ }
+
+ size = sizeof(vlan_spec->tci);
+ field = ulp_rte_parser_fld_copy(field, &vlan_spec->tci, size);
+
+ size = sizeof(vlan_spec->inner_type);
+ field = ulp_rte_parser_fld_copy(field, &vlan_spec->inner_type, size);
+}
+
+/* Function to handle the parsing of RTE Flow item ipv4 Header. */
+static void
+ulp_rte_enc_ipv4_hdr_handler(struct ulp_rte_parser_params *params,
+ const struct rte_flow_item_ipv4 *ip)
+{
+ struct ulp_rte_hdr_field *field;
+ uint32_t size;
+ uint8_t val8;
+
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_IPV4_IHL];
+ size = sizeof(ip->hdr.version_ihl);
+ if (!ip->hdr.version_ihl)
+ val8 = RTE_IPV4_VHL_DEF;
+ else
+ val8 = ip->hdr.version_ihl;
+ field = ulp_rte_parser_fld_copy(field, &val8, size);
+
+ size = sizeof(ip->hdr.type_of_service);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.type_of_service, size);
+
+ size = sizeof(ip->hdr.packet_id);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.packet_id, size);
+
+ size = sizeof(ip->hdr.fragment_offset);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.fragment_offset, size);
+
+ size = sizeof(ip->hdr.time_to_live);
+ if (!ip->hdr.time_to_live)
+ val8 = BNXT_ULP_DEFAULT_TTL;
+ else
+ val8 = ip->hdr.time_to_live;
+ field = ulp_rte_parser_fld_copy(field, &val8, size);
+
+ size = sizeof(ip->hdr.next_proto_id);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.next_proto_id, size);
+
+ size = sizeof(ip->hdr.src_addr);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.src_addr, size);
+
+ size = sizeof(ip->hdr.dst_addr);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.dst_addr, size);
+
+ ULP_BITMAP_SET(params->enc_hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV4);
+}
+
+/* Function to handle the parsing of RTE Flow item ipv6 Header. */
+static void
+ulp_rte_enc_ipv6_hdr_handler(struct ulp_rte_parser_params *params,
+ const struct rte_flow_item_ipv6 *ip)
+{
+ struct ulp_rte_hdr_field *field;
+ uint32_t size;
+ uint32_t val32;
+ uint8_t val8;
+
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW];
+ size = sizeof(ip->hdr.vtc_flow);
+ if (!ip->hdr.vtc_flow)
+ val32 = rte_cpu_to_be_32(BNXT_ULP_IPV6_DFLT_VER);
+ else
+ val32 = ip->hdr.vtc_flow;
+ field = ulp_rte_parser_fld_copy(field, &val32, size);
+
+ size = sizeof(ip->hdr.proto);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.proto, size);
+
+ size = sizeof(ip->hdr.hop_limits);
+ if (!ip->hdr.hop_limits)
+ val8 = BNXT_ULP_DEFAULT_TTL;
+ else
+ val8 = ip->hdr.hop_limits;
+ field = ulp_rte_parser_fld_copy(field, &val8, size);
+
+ size = sizeof(ip->hdr.src_addr);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.src_addr, size);
+
+ size = sizeof(ip->hdr.dst_addr);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.dst_addr, size);
+
+ ULP_BITMAP_SET(params->enc_hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV6);
+}
+
+/* Function to handle the parsing of RTE Flow item UDP Header. */
+static void
+ulp_rte_enc_udp_hdr_handler(struct ulp_rte_parser_params *params,
+ const struct rte_flow_item_udp *udp_spec)
+{
+ struct ulp_rte_hdr_field *field;
+ uint32_t size;
+ uint8_t type = IPPROTO_UDP;
+
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_UDP_SPORT];
+ size = sizeof(udp_spec->hdr.src_port);
+ field = ulp_rte_parser_fld_copy(field, &udp_spec->hdr.src_port, size);
+
+ size = sizeof(udp_spec->hdr.dst_port);
+ field = ulp_rte_parser_fld_copy(field, &udp_spec->hdr.dst_port, size);
+
+ ULP_BITMAP_SET(params->enc_hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_UDP);
+
+ /* Update thhe ip header protocol */
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_IPV4_PROTO];
+ ulp_rte_parser_fld_copy(field, &type, sizeof(type));
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_IPV6_PROTO];
+ ulp_rte_parser_fld_copy(field, &type, sizeof(type));
+}
+
+/* Function to handle the parsing of RTE Flow item vxlan Header. */
+static void
+ulp_rte_enc_vxlan_hdr_handler(struct ulp_rte_parser_params *params,
+ struct rte_flow_item_vxlan *vxlan_spec)
+{
+ struct ulp_rte_hdr_field *field;
+ uint32_t size;
+
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_VXLAN_FLAGS];
+ size = sizeof(vxlan_spec->flags);
+ field = ulp_rte_parser_fld_copy(field, &vxlan_spec->flags, size);
+
+ size = sizeof(vxlan_spec->rsvd0);
+ field = ulp_rte_parser_fld_copy(field, &vxlan_spec->rsvd0, size);
+
+ size = sizeof(vxlan_spec->vni);
+ field = ulp_rte_parser_fld_copy(field, &vxlan_spec->vni, size);
+
+ size = sizeof(vxlan_spec->rsvd1);
+ field = ulp_rte_parser_fld_copy(field, &vxlan_spec->rsvd1, size);
+
+ ULP_BITMAP_SET(params->enc_hdr_bitmap.bits, BNXT_ULP_HDR_BIT_T_VXLAN);
+}
+
/* Function to handle the parsing of RTE Flow action vxlan_encap Header. */
int32_t
ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
@@ -1733,23 +1923,14 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
{
const struct rte_flow_action_vxlan_encap *vxlan_encap;
const struct rte_flow_item *item;
- const struct rte_flow_item_eth *eth_spec;
const struct rte_flow_item_ipv4 *ipv4_spec;
const struct rte_flow_item_ipv6 *ipv6_spec;
struct rte_flow_item_vxlan vxlan_spec;
uint32_t vlan_num = 0, vlan_size = 0;
uint32_t ip_size = 0, ip_type = 0;
uint32_t vxlan_size = 0;
- uint8_t *buff;
- /* IP header per byte - ver/hlen, TOS, ID, ID, FRAG, FRAG, TTL, PROTO */
- const uint8_t def_ipv4_hdr[] = {0x45, 0x00, 0x00, 0x01, 0x00,
- 0x00, 0x40, 0x11};
- /* IPv6 header per byte - vtc-flow,flow,zero,nexthdr-ttl */
- const uint8_t def_ipv6_hdr[] = {0x60, 0x00, 0x00, 0x01, 0x00,
- 0x00, 0x11, 0xf6};
struct ulp_rte_act_bitmap *act = ¶ms->act_bitmap;
struct ulp_rte_act_prop *ap = ¶ms->act_prop;
- const uint8_t *tmp_buff;
vxlan_encap = action_item->conf;
if (!vxlan_encap) {
@@ -1771,18 +1952,10 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
BNXT_TF_DBG(ERR, "Parse Error:vxlan encap does not have eth\n");
return BNXT_TF_RC_ERROR;
}
- eth_spec = item->spec;
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC];
- ulp_encap_buffer_copy(buff,
- eth_spec->dst.addr_bytes,
- BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_DMAC,
- ULP_BUFFER_ALIGN_8_BYTE);
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC];
- ulp_encap_buffer_copy(buff,
- eth_spec->src.addr_bytes,
- BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_SMAC,
- ULP_BUFFER_ALIGN_8_BYTE);
+ /* Parse the ethernet header */
+ if (item->spec)
+ ulp_rte_enc_eth_hdr_handler(params, item->spec);
/* Goto the next item */
if (!ulp_rte_item_skip_void(&item, 1))
@@ -1791,11 +1964,8 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
/* May have vlan header */
if (item->type == RTE_FLOW_ITEM_TYPE_VLAN) {
vlan_num++;
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG];
- ulp_encap_buffer_copy(buff,
- item->spec,
- sizeof(struct rte_flow_item_vlan),
- ULP_BUFFER_ALIGN_8_BYTE);
+ if (item->spec)
+ ulp_rte_enc_vlan_hdr_handler(params, item->spec, 0);
if (!ulp_rte_item_skip_void(&item, 1))
return BNXT_TF_RC_ERROR;
@@ -1804,13 +1974,13 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
/* may have two vlan headers */
if (item->type == RTE_FLOW_ITEM_TYPE_VLAN) {
vlan_num++;
- memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG +
- sizeof(struct rte_flow_item_vlan)],
- item->spec,
- sizeof(struct rte_flow_item_vlan));
+ if (item->spec)
+ ulp_rte_enc_vlan_hdr_handler(params, item->spec, 1);
+
if (!ulp_rte_item_skip_void(&item, 1))
return BNXT_TF_RC_ERROR;
}
+
/* Update the vlan count and size of more than one */
if (vlan_num) {
vlan_size = vlan_num * sizeof(struct rte_flow_item_vlan);
@@ -1829,49 +1999,6 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
ipv4_spec = item->spec;
ip_size = BNXT_ULP_ENCAP_IPV4_SIZE;
- /* copy the ipv4 details */
- if (ulp_buffer_is_empty(&ipv4_spec->hdr.version_ihl,
- BNXT_ULP_ENCAP_IPV4_VER_HLEN_TOS)) {
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP];
- ulp_encap_buffer_copy(buff,
- def_ipv4_hdr,
- BNXT_ULP_ENCAP_IPV4_VER_HLEN_TOS +
- BNXT_ULP_ENCAP_IPV4_ID_PROTO,
- ULP_BUFFER_ALIGN_8_BYTE);
- } else {
- /* Total length being ignored in the ip hdr. */
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP];
- tmp_buff = (const uint8_t *)&ipv4_spec->hdr.packet_id;
- ulp_encap_buffer_copy(buff,
- tmp_buff,
- BNXT_ULP_ENCAP_IPV4_ID_PROTO,
- ULP_BUFFER_ALIGN_8_BYTE);
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP +
- BNXT_ULP_ENCAP_IPV4_ID_PROTO];
- ulp_encap_buffer_copy(buff,
- &ipv4_spec->hdr.version_ihl,
- BNXT_ULP_ENCAP_IPV4_VER_HLEN_TOS,
- ULP_BUFFER_ALIGN_8_BYTE);
- }
-
- /* Update the dst ip address in ip encap buffer */
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP +
- BNXT_ULP_ENCAP_IPV4_VER_HLEN_TOS +
- BNXT_ULP_ENCAP_IPV4_ID_PROTO];
- ulp_encap_buffer_copy(buff,
- (const uint8_t *)&ipv4_spec->hdr.dst_addr,
- sizeof(ipv4_spec->hdr.dst_addr),
- ULP_BUFFER_ALIGN_8_BYTE);
-
- /* Update the src ip address */
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC +
- BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SRC -
- sizeof(ipv4_spec->hdr.src_addr)];
- ulp_encap_buffer_copy(buff,
- (const uint8_t *)&ipv4_spec->hdr.src_addr,
- sizeof(ipv4_spec->hdr.src_addr),
- ULP_BUFFER_ALIGN_8_BYTE);
-
/* Update the ip size details */
ip_size = tfp_cpu_to_be_32(ip_size);
memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ],
@@ -1885,6 +2012,8 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
/* update the computed field to notify it is ipv4 header */
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG,
1);
+ if (ipv4_spec)
+ ulp_rte_enc_ipv4_hdr_handler(params, ipv4_spec);
if (!ulp_rte_item_skip_void(&item, 1))
return BNXT_TF_RC_ERROR;
@@ -1892,47 +2021,6 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
ipv6_spec = item->spec;
ip_size = BNXT_ULP_ENCAP_IPV6_SIZE;
- /* copy the ipv6 details */
- tmp_buff = (const uint8_t *)&ipv6_spec->hdr.vtc_flow;
- if (ulp_buffer_is_empty(tmp_buff,
- BNXT_ULP_ENCAP_IPV6_VTC_FLOW)) {
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP];
- ulp_encap_buffer_copy(buff,
- def_ipv6_hdr,
- sizeof(def_ipv6_hdr),
- ULP_BUFFER_ALIGN_8_BYTE);
- } else {
- /* The payload length being ignored in the ip hdr. */
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP];
- tmp_buff = (const uint8_t *)&ipv6_spec->hdr.proto;
- ulp_encap_buffer_copy(buff,
- tmp_buff,
- BNXT_ULP_ENCAP_IPV6_PROTO_TTL,
- ULP_BUFFER_ALIGN_8_BYTE);
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP +
- BNXT_ULP_ENCAP_IPV6_PROTO_TTL +
- BNXT_ULP_ENCAP_IPV6_DO];
- tmp_buff = (const uint8_t *)&ipv6_spec->hdr.vtc_flow;
- ulp_encap_buffer_copy(buff,
- tmp_buff,
- BNXT_ULP_ENCAP_IPV6_VTC_FLOW,
- ULP_BUFFER_ALIGN_8_BYTE);
- }
- /* Update the dst ip address in ip encap buffer */
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP +
- sizeof(def_ipv6_hdr)];
- ulp_encap_buffer_copy(buff,
- (const uint8_t *)ipv6_spec->hdr.dst_addr,
- sizeof(ipv6_spec->hdr.dst_addr),
- ULP_BUFFER_ALIGN_8_BYTE);
-
- /* Update the src ip address */
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC];
- ulp_encap_buffer_copy(buff,
- (const uint8_t *)ipv6_spec->hdr.src_addr,
- sizeof(ipv6_spec->hdr.src_addr),
- ULP_BUFFER_ALIGN_16_BYTE);
-
/* Update the ip size details */
ip_size = tfp_cpu_to_be_32(ip_size);
memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ],
@@ -1946,6 +2034,8 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
/* update the computed field to notify it is ipv6 header */
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG,
1);
+ if (ipv6_spec)
+ ulp_rte_enc_ipv6_hdr_handler(params, ipv6_spec);
if (!ulp_rte_item_skip_void(&item, 1))
return BNXT_TF_RC_ERROR;
@@ -1959,10 +2049,8 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
BNXT_TF_DBG(ERR, "vxlan encap does not have udp\n");
return BNXT_TF_RC_ERROR;
}
- /* copy the udp details */
- ulp_encap_buffer_copy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP],
- item->spec, BNXT_ULP_ENCAP_UDP_SIZE,
- ULP_BUFFER_ALIGN_8_BYTE);
+ if (item->spec)
+ ulp_rte_enc_udp_hdr_handler(params, item->spec);
if (!ulp_rte_item_skip_void(&item, 1))
return BNXT_TF_RC_ERROR;
@@ -1976,21 +2064,12 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
/* copy the vxlan details */
memcpy(&vxlan_spec, item->spec, vxlan_size);
vxlan_spec.flags = 0x08;
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN];
- if (ip_type == rte_cpu_to_be_32(BNXT_ULP_ETH_IPV4)) {
- ulp_encap_buffer_copy(buff, (const uint8_t *)&vxlan_spec,
- vxlan_size, ULP_BUFFER_ALIGN_8_BYTE);
- } else {
- ulp_encap_buffer_copy(buff, (const uint8_t *)&vxlan_spec,
- vxlan_size / 2, ULP_BUFFER_ALIGN_8_BYTE);
- ulp_encap_buffer_copy(buff + (vxlan_size / 2),
- (const uint8_t *)&vxlan_spec.vni,
- vxlan_size / 2, ULP_BUFFER_ALIGN_8_BYTE);
- }
vxlan_size = tfp_cpu_to_be_32(vxlan_size);
memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ],
&vxlan_size, sizeof(uint32_t));
+ ulp_rte_enc_vxlan_hdr_handler(params, &vxlan_spec);
+
/* update the hdr_bitmap with vxlan */
ULP_BITMAP_SET(act->bits, BNXT_ULP_ACT_BIT_VXLAN_ENCAP);
return BNXT_TF_RC_SUCCESS;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
index 673172c811..e14f86278a 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
@@ -33,8 +33,10 @@
#define BNXT_ULP_GET_IPV6_FLOWLABEL(vtcf) \
((vtcf) & BNXT_ULP_PARSER_IPV6_FLOW_LABEL)
#define BNXT_ULP_PARSER_IPV6_VER_MASK 0xf0000000
+#define BNXT_ULP_IPV6_DFLT_VER 0x60000000
#define BNXT_ULP_PARSER_IPV6_TC 0x0ff00000
#define BNXT_ULP_PARSER_IPV6_FLOW_LABEL 0x000fffff
+#define BNXT_ULP_DEFAULT_TTL 64
enum bnxt_ulp_prsr_action {
ULP_PRSR_ACT_DEFAULT = 0,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index 2685e63432..904763f27d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -30,6 +30,7 @@
#define BNXT_ULP_PROTO_HDR_GRE_NUM 6
#define BNXT_ULP_PROTO_HDR_ICMP_NUM 5
#define BNXT_ULP_PROTO_HDR_MAX 128
+#define BNXT_ULP_PROTO_HDR_ENCAP_MAX 64
#define BNXT_ULP_PROTO_HDR_FIELD_SVIF_IDX 1
/* Direction attributes */
@@ -64,12 +65,13 @@ struct ulp_rte_act_prop {
/* Structure to be used for passing all the parser functions */
struct ulp_rte_parser_params {
- STAILQ_ENTRY(ulp_rte_parser_params) next;
struct ulp_rte_hdr_bitmap hdr_bitmap;
+ struct ulp_rte_hdr_bitmap enc_hdr_bitmap;
struct ulp_rte_hdr_bitmap hdr_fp_bit;
struct ulp_rte_field_bitmap fld_bitmap;
struct ulp_rte_field_bitmap fld_s_bitmap;
struct ulp_rte_hdr_field hdr_field[BNXT_ULP_PROTO_HDR_MAX];
+ struct ulp_rte_hdr_field enc_field[BNXT_ULP_PROTO_HDR_ENCAP_MAX];
uint64_t comp_fld[BNXT_ULP_CF_IDX_LAST];
uint32_t field_idx;
struct ulp_rte_act_bitmap act_bitmap;
@@ -207,7 +209,9 @@ struct bnxt_ulp_template_device_tbls {
/* Device specific parameters */
struct bnxt_ulp_device_params {
uint8_t description[16];
- enum bnxt_ulp_byte_order byte_order;
+ enum bnxt_ulp_byte_order key_byte_order;
+ enum bnxt_ulp_byte_order result_byte_order;
+ enum bnxt_ulp_byte_order encap_byte_order;
uint8_t encap_byte_swap;
uint8_t num_phy_ports;
uint32_t mark_db_lfid_entries;
@@ -254,7 +258,6 @@ struct bnxt_ulp_mapper_tbl_info {
uint8_t direction;
enum bnxt_ulp_pri_opc pri_opcode;
uint32_t pri_operand;
- enum bnxt_ulp_byte_order byte_order;
/* conflict resolution opcode */
enum bnxt_ulp_accept_opc accept_opcode;
@@ -267,6 +270,7 @@ struct bnxt_ulp_mapper_tbl_info {
uint16_t key_num_fields;
/* Size of the blob that holds the key */
uint16_t blob_key_bit_size;
+ uint16_t record_size;
/* Information for accessing the ulp_class_result_field_list */
uint32_t result_start_idx;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c
index 1649e157f2..fc4f435c97 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c
@@ -62,7 +62,7 @@ ulp_regfile_read(struct ulp_regfile *regfile,
* data [in] The value is written into this variable. It is going to be in the
* same byte order as it was written.
*
- * size [in] The size in bytes of the value beingritten into this
+ * size [in] The size in bytes of the value being written into this
* variable.
*
* returns 0 on success
@@ -295,7 +295,7 @@ ulp_blob_push(struct ulp_blob *blob,
datalen,
data);
if (!rc) {
- BNXT_TF_DBG(ERR, "Failed ro write blob\n");
+ BNXT_TF_DBG(ERR, "Failed to write blob\n");
return 0;
}
blob->write_idx += datalen;
@@ -355,7 +355,7 @@ ulp_blob_insert(struct ulp_blob *blob, uint32_t offset,
datalen,
data);
if (!rc) {
- BNXT_TF_DBG(ERR, "Failed ro write blob\n");
+ BNXT_TF_DBG(ERR, "Failed to write blob\n");
return 0;
}
/* copy the previously stored data */
@@ -409,7 +409,7 @@ ulp_blob_push_64(struct ulp_blob *blob,
*
* data [in] 32-bit value to be added to the blob.
*
- * datalen [in] The number of bits to be added ot the blob.
+ * datalen [in] The number of bits to be added to the blob.
*
* The offset of the data is updated after each push of data.
* NULL returned on error, pointer pushed value otherwise.
@@ -987,6 +987,33 @@ ulp_blob_append(struct ulp_blob *dst, struct ulp_blob *src,
return 0;
}
+/*
+ * Perform the blob buffer copy.
+ * This api makes the src blob merged to the dst blob.
+ *
+ * dst [in] The destination blob, the blob to be merged.
+ * src [in] The src blob.
+ *
+ * returns 0 on success.
+ */
+int32_t
+ulp_blob_buffer_copy(struct ulp_blob *dst, struct ulp_blob *src)
+{
+ if ((dst->write_idx + src->write_idx) > dst->bitlen) {
+ BNXT_TF_DBG(ERR, "source buffer too large\n");
+ return -EINVAL;
+ }
+ if (ULP_BITS_IS_BYTE_NOT_ALIGNED(dst->write_idx) ||
+ ULP_BITS_IS_BYTE_NOT_ALIGNED(src->write_idx)) {
+ BNXT_TF_DBG(ERR, "source buffer is not aligned\n");
+ return -EINVAL;
+ }
+ memcpy(&dst->data[ULP_BITS_2_BYTE_NR(dst->write_idx)],
+ src->data, ULP_BITS_2_BYTE_NR(src->write_idx));
+ dst->write_idx += src->write_idx;
+ return 0;
+}
+
/*
* Read data from the operand
*
@@ -1012,44 +1039,6 @@ ulp_operand_read(uint8_t *operand,
return bytes;
}
-/*
- * copy the buffer in the encap format which is 2 bytes.
- * The MSB of the src is placed at the LSB of dst.
- *
- * dst [out] The destination buffer
- * src [in] The source buffer dst
- * size[in] size of the buffer.
- * align[in] The alignment is either 8 or 16.
- */
-void
-ulp_encap_buffer_copy(uint8_t *dst,
- const uint8_t *src,
- uint16_t size,
- uint16_t align)
-{
- uint16_t idx, tmp_size = 0;
-
- do {
- dst += tmp_size;
- src += tmp_size;
- idx = 0;
- if (size > align) {
- tmp_size = align;
- size -= align;
- } else {
- tmp_size = size;
- size = 0;
- }
- /* copy 2 bytes at a time. Write MSB to LSB */
- while ((idx + sizeof(uint16_t)) <= tmp_size) {
- memcpy(&dst[idx],
- &src[tmp_size - idx - sizeof(uint16_t)],
- sizeof(uint16_t));
- idx += sizeof(uint16_t);
- }
- } while (size);
-}
-
/*
* Check the buffer is empty
*
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.h b/drivers/net/bnxt/tf_ulp/ulp_utils.h
index e1b0e773f3..68a537fa0a 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.h
@@ -475,6 +475,18 @@ int32_t
ulp_blob_append(struct ulp_blob *dst, struct ulp_blob *src,
uint16_t src_offset, uint16_t src_len);
+/*
+ * Perform the blob buffer copy.
+ * This api makes the src blob merged to the dst blob.
+ *
+ * dst [in] The destination blob, the blob to be merged.
+ * src [in] The src blob.
+ *
+ * returns 0 on success.
+ */
+int32_t
+ulp_blob_buffer_copy(struct ulp_blob *dst, struct ulp_blob *src);
+
/*
* Read data from the operand
*
@@ -491,21 +503,6 @@ ulp_operand_read(uint8_t *operand,
uint8_t *val,
uint16_t bitlen);
-/*
- * copy the buffer in the encap format which is 2 bytes.
- * The MSB of the src is placed at the LSB of dst.
- *
- * dst [out] The destination buffer
- * src [in] The source buffer dst
- * size[in] size of the buffer.
- * align[in] The alignment is either 8 or 16.
- */
-void
-ulp_encap_buffer_copy(uint8_t *dst,
- const uint8_t *src,
- uint16_t size,
- uint16_t align);
-
/*
* Check the buffer is empty
*
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v2 08/13] net/bnxt: add wild card TCAM byte order for Thor
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 00/13] enhancements to host based flow table management Venkat Duvvuru
` (6 preceding siblings ...)
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 07/13] net/bnxt: add support for dynamic encap action Venkat Duvvuru
@ 2021-09-08 5:06 ` Venkat Duvvuru
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 09/13] net/bnxt: add flow templates " Venkat Duvvuru
` (6 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-08 5:06 UTC (permalink / raw)
To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
The wild card tcam for Thor platform is different from the profile tcam
byte order.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Shuanglin Wang <shuanglin.wang@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
.../generic_templates/ulp_template_db_tbl.c | 2 ++
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 25 +++++++++++++------
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 1 +
3 files changed, 21 insertions(+), 7 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
index b5bce6f4c7..68f1b5fd00 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
@@ -201,6 +201,7 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
.key_byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE,
.encap_byte_order = BNXT_ULP_BYTE_ORDER_BE,
+ .wc_key_byte_order = BNXT_ULP_BYTE_ORDER_BE,
.encap_byte_swap = 1,
.int_flow_db_num_entries = 16384,
.ext_flow_db_num_entries = 32768,
@@ -223,6 +224,7 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
.key_byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE,
.encap_byte_order = BNXT_ULP_BYTE_ORDER_BE,
+ .wc_key_byte_order = BNXT_ULP_BYTE_ORDER_BE,
.encap_byte_swap = 1,
.int_flow_db_num_entries = 16384,
.ext_flow_db_num_entries = 32768,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 2687a545f3..bcc089b3e1 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -1953,6 +1953,15 @@ static void ulp_mapper_wc_tcam_tbl_post_process(struct ulp_blob *blob)
#endif
}
+static int32_t ulp_mapper_tcam_is_wc_tcam(struct bnxt_ulp_mapper_tbl_info *tbl)
+{
+ if (tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM ||
+ tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM_HIGH ||
+ tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM_LOW)
+ return 1;
+ return 0;
+}
+
static int32_t
ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
struct bnxt_ulp_mapper_tbl_info *tbl)
@@ -1972,6 +1981,7 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
uint32_t hit = 0;
uint16_t tmplen = 0;
uint16_t idx;
+ enum bnxt_ulp_byte_order key_byte_order;
/* Set the key and mask to the original key and mask. */
key = &okey;
@@ -2003,10 +2013,13 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
- if (!ulp_blob_init(key, tbl->blob_key_bit_size,
- dparms->key_byte_order) ||
- !ulp_blob_init(mask, tbl->blob_key_bit_size,
- dparms->key_byte_order) ||
+ if (ulp_mapper_tcam_is_wc_tcam(tbl))
+ key_byte_order = dparms->wc_key_byte_order;
+ else
+ key_byte_order = dparms->key_byte_order;
+
+ if (!ulp_blob_init(key, tbl->blob_key_bit_size, key_byte_order) ||
+ !ulp_blob_init(mask, tbl->blob_key_bit_size, key_byte_order) ||
!ulp_blob_init(&data, tbl->result_bit_size,
dparms->result_byte_order) ||
!ulp_blob_init(&update_data, tbl->result_bit_size,
@@ -2043,9 +2056,7 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
}
/* For wild card tcam perform the post process to swap the blob */
- if (tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM ||
- tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM_HIGH ||
- tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM_LOW) {
+ if (ulp_mapper_tcam_is_wc_tcam(tbl)) {
if (dparms->dynamic_pad_en) {
/* Sets up the slices for writing to the WC TCAM */
rc = ulp_mapper_wc_tcam_tbl_dyn_post_process(dparms,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index 904763f27d..e2a4b81cec 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -212,6 +212,7 @@ struct bnxt_ulp_device_params {
enum bnxt_ulp_byte_order key_byte_order;
enum bnxt_ulp_byte_order result_byte_order;
enum bnxt_ulp_byte_order encap_byte_order;
+ enum bnxt_ulp_byte_order wc_key_byte_order;
uint8_t encap_byte_swap;
uint8_t num_phy_ports;
uint32_t mark_db_lfid_entries;
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v2 09/13] net/bnxt: add flow templates for Thor
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 00/13] enhancements to host based flow table management Venkat Duvvuru
` (7 preceding siblings ...)
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 08/13] net/bnxt: add wild card TCAM byte order for Thor Venkat Duvvuru
@ 2021-09-08 5:06 ` Venkat Duvvuru
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 10/13] net/bnxt: tf core SRAM Manager Venkat Duvvuru
` (5 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-08 5:06 UTC (permalink / raw)
To: dev; +Cc: Kishore Padmanabha, Mike Baucom, Venkat Duvvuru
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
1. Add support for egress flows with port and count action for
Thor platform.
2. Added templates to support VXLAN encapsulation feature for Thor.
3. Added support for VXLAN decap and VLAN pop actions along with
the ingress flow.
4. Added templates to enable VXLAN decap support for f1 and f2 flows.
5. Added templates Thor VF Rep support
6. Added Thor ingress mod table actions for NAT, NAPT, and TTL.
7. Added mirror/sample table support
8. Added supported for IPv6 flows for Thor.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Mike Baucom <michael.baucom@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
Reviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com>
---
drivers/net/bnxt/tf_core/tf_tcam.c | 6 +-
.../generic_templates/ulp_template_db_enum.h | 123 +-
.../generic_templates/ulp_template_db_tbl.c | 182 +-
.../ulp_template_db_thor_act.c | 4329 +-
.../ulp_template_db_thor_class.c | 44219 ++++++++++++++--
.../ulp_template_db_wh_plus_class.c | 4 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 10 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 18 +-
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 1 +
drivers/net/bnxt/tf_ulp/ulp_utils.c | 3 +
10 files changed, 44734 insertions(+), 4161 deletions(-)
diff --git a/drivers/net/bnxt/tf_core/tf_tcam.c b/drivers/net/bnxt/tf_core/tf_tcam.c
index 806af3070a..273f20858b 100644
--- a/drivers/net/bnxt/tf_core/tf_tcam.c
+++ b/drivers/net/bnxt/tf_core/tf_tcam.c
@@ -323,8 +323,12 @@ tf_tcam_alloc(struct tf *tfp,
}
/* return the start index of each row */
- if (i == 0)
+ if (parms->priority == 0) {
+ if (i == 0)
+ parms->idx = index;
+ } else {
parms->idx = index;
+ }
}
return 0;
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
index 9010d9a749..84e3d92f41 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
@@ -3,12 +3,12 @@
* All rights reserved.
*/
-/* date: Thu May 27 17:35:19 2021 */
+/* date: Tue Jul 13 12:36:40 2021 */
#ifndef ULP_TEMPLATE_DB_H_
#define ULP_TEMPLATE_DB_H_
-#define BNXT_ULP_REGFILE_MAX_SZ 40
+#define BNXT_ULP_REGFILE_MAX_SZ 42
#define BNXT_ULP_MAX_NUM_DEVICES 4
#define BNXT_ULP_LOG2_MAX_NUM_DEV 2
#define BNXT_ULP_GEN_TBL_MAX_SZ 12
@@ -27,9 +27,9 @@
#define BNXT_ULP_ACT_HID_SHFTL 26
#define BNXT_ULP_ACT_HID_MASK 2047
#define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 8
-#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 43
+#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 62
#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 50
-#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 204
+#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 206
#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 6
#define BNXT_ULP_COND_GOTO_REJECT 1023
#define BNXT_ULP_COND_GOTO_RF 0x10000
@@ -44,23 +44,23 @@
#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 618
#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 49
#define ULP_THOR_CLASS_TMPL_LIST_SIZE 6
-#define ULP_THOR_CLASS_TBL_LIST_SIZE 33
-#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 242
-#define ULP_THOR_CLASS_IDENT_LIST_SIZE 8
-#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 259
-#define ULP_THOR_CLASS_COND_LIST_SIZE 13
+#define ULP_THOR_CLASS_TBL_LIST_SIZE 114
+#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 2305
+#define ULP_THOR_CLASS_IDENT_LIST_SIZE 39
+#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1192
+#define ULP_THOR_CLASS_COND_LIST_SIZE 55
#define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7
#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 35
#define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2
#define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 1
-#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 527
+#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 536
#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 39
#define ULP_THOR_ACT_TMPL_LIST_SIZE 7
-#define ULP_THOR_ACT_TBL_LIST_SIZE 2
-#define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 0
-#define ULP_THOR_ACT_IDENT_LIST_SIZE 0
-#define ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE 18
-#define ULP_THOR_ACT_COND_LIST_SIZE 5
+#define ULP_THOR_ACT_TBL_LIST_SIZE 28
+#define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 2
+#define ULP_THOR_ACT_IDENT_LIST_SIZE 1
+#define ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE 479
+#define ULP_THOR_ACT_COND_LIST_SIZE 20
enum bnxt_ulp_act_bit {
BNXT_ULP_ACT_BIT_MARK = 0x0000000000000001,
@@ -203,7 +203,11 @@ enum bnxt_ulp_cf_idx {
BNXT_ULP_CF_IDX_TUNNEL_ID = 63,
BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID = 64,
BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID = 65,
- BNXT_ULP_CF_IDX_LAST = 66
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID = 66,
+ BNXT_ULP_CF_IDX_OI_VLAN_FB_VID = 67,
+ BNXT_ULP_CF_IDX_IO_VLAN_FB_VID = 68,
+ BNXT_ULP_CF_IDX_II_VLAN_FB_VID = 69,
+ BNXT_ULP_CF_IDX_LAST = 70
};
enum bnxt_ulp_cond_list_opc {
@@ -386,29 +390,42 @@ enum bnxt_ulp_glb_rf_idx {
BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR = 5,
BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 = 6,
BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 = 7,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0 = 8,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1 = 9,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 = 10,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 = 11,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0 = 12,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1 = 13,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 14,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 = 15,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2 = 16,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 17,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 18,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 19,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 20,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 21,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 22,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 23,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 24,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 25,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 26,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 27,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 28,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 29,
- BNXT_ULP_GLB_RF_IDX_LAST = 30
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 = 8,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 = 9,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 = 10,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 = 11,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0 = 12,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1 = 13,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 = 14,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 = 15,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 = 16,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3 = 17,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4 = 18,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0 = 19,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1 = 20,
+ BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0 = 21,
+ BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_1 = 22,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 = 23,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 = 24,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 = 25,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 26,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 = 27,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2 = 28,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 29,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 30,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 31,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 32,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 33,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 34,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 35,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 36,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 37,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 38,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 39,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 40,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 41,
+ BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID = 42,
+ BNXT_ULP_GLB_RF_IDX_LAST = 43
};
enum bnxt_ulp_hdr_type {
@@ -520,7 +537,9 @@ enum bnxt_ulp_rf_idx {
BNXT_ULP_RF_IDX_CC = 37,
BNXT_ULP_RF_IDX_CF_FLOW_SIG_ID = 38,
BNXT_ULP_RF_IDX_PHY_PORT = 39,
- BNXT_ULP_RF_IDX_LAST = 40
+ BNXT_ULP_RF_IDX_METADATA_PROF = 40,
+ BNXT_ULP_RF_IDX_MODIFY_PTR = 41,
+ BNXT_ULP_RF_IDX_LAST = 42
};
enum bnxt_ulp_shared_session {
@@ -693,6 +712,13 @@ enum bnxt_ulp_act_prop_idx {
};
enum ulp_wp_sym {
+ ULP_WP_SYM_METADATA_OP_NORMAL = 0,
+ ULP_WP_SYM_METADATA_OP_L2_HASH = 0,
+ ULP_WP_SYM_METADATA_OP_L4_HASH = 0,
+ ULP_WP_SYM_FWD_OP_BYPASS_CFA = 0,
+ ULP_WP_SYM_FWD_OP_BYPASS_CFA_ROCE = 0,
+ ULP_WP_SYM_FWD_OP_BYPASS_LKUP = 0,
+ ULP_WP_SYM_FWD_OP_NORMAL_FLOW = 0,
ULP_WP_SYM_CTXT_OPCODE_BYPASS_CFA = 0,
ULP_WP_SYM_CTXT_OPCODE_BYPASS_LKUP = 0,
ULP_WP_SYM_CTXT_OPCODE_META_UPDATE = 0,
@@ -843,6 +869,10 @@ enum ulp_wp_sym {
ULP_WP_SYM_L4_HDR_IS_UDP_TCP_YES = 1,
ULP_WP_SYM_POP_VLAN_NO = 0,
ULP_WP_SYM_POP_VLAN_YES = 1,
+ ULP_WP_SYM_VLAN_DEL_RPT_DISABLED = 0,
+ ULP_WP_SYM_VLAN_DEL_RPT_STRIP_OUTER = 0,
+ ULP_WP_SYM_VLAN_DEL_RPT_STRIP_BOTH = 0,
+ ULP_WP_SYM_VLAN_DEL_RPT_DYN_STRIP = 0,
ULP_WP_SYM_DECAP_FUNC_NONE = 0,
ULP_WP_SYM_DECAP_FUNC_THRU_TL2 = 3,
ULP_WP_SYM_DECAP_FUNC_THRU_TL3 = 8,
@@ -916,6 +946,13 @@ enum ulp_wp_sym {
};
enum ulp_thor_sym {
+ ULP_THOR_SYM_METADATA_OP_NORMAL = 0,
+ ULP_THOR_SYM_METADATA_OP_L2_HASH = 1,
+ ULP_THOR_SYM_METADATA_OP_L4_HASH = 2,
+ ULP_THOR_SYM_FWD_OP_BYPASS_CFA = 0,
+ ULP_THOR_SYM_FWD_OP_BYPASS_CFA_ROCE = 1,
+ ULP_THOR_SYM_FWD_OP_BYPASS_LKUP = 2,
+ ULP_THOR_SYM_FWD_OP_NORMAL_FLOW = 3,
ULP_THOR_SYM_CTXT_OPCODE_BYPASS_CFA = 0,
ULP_THOR_SYM_CTXT_OPCODE_BYPASS_LKUP = 1,
ULP_THOR_SYM_CTXT_OPCODE_META_UPDATE = 2,
@@ -1066,6 +1103,10 @@ enum ulp_thor_sym {
ULP_THOR_SYM_L4_HDR_IS_UDP_TCP_YES = 1,
ULP_THOR_SYM_POP_VLAN_NO = 0,
ULP_THOR_SYM_POP_VLAN_YES = 1,
+ ULP_THOR_SYM_VLAN_DEL_RPT_DISABLED = 0,
+ ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER = 1,
+ ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_BOTH = 2,
+ ULP_THOR_SYM_VLAN_DEL_RPT_DYN_STRIP = 3,
ULP_THOR_SYM_DECAP_FUNC_NONE = 0,
ULP_THOR_SYM_DECAP_FUNC_THRU_TL2 = 3,
ULP_THOR_SYM_DECAP_FUNC_THRU_TL3 = 8,
@@ -1122,7 +1163,7 @@ enum ulp_thor_sym {
ULP_THOR_SYM_ACT_REC_POP_VLAN_NO = 0,
ULP_THOR_SYM_ACT_REC_METER_EN_YES = 1,
ULP_THOR_SYM_ACT_REC_METER_EN_NO = 0,
- ULP_THOR_SYM_LOOPBACK_PORT = 3,
+ ULP_THOR_SYM_LOOPBACK_PORT = 16,
ULP_THOR_SYM_LOOPBACK_PARIF = 15,
ULP_THOR_SYM_EXT_EM_MAX_KEY_SIZE = 0,
ULP_THOR_SYM_MATCH_TYPE_EM = 0,
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
index 68f1b5fd00..3d1e95d18c 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 20 11:56:39 2021 */
+/* date: Thu Jul 8 08:44:00 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -187,6 +187,10 @@ const struct bnxt_ulp_template_device_tbls ulp_template_thor_tbls[] = {
.tmpl_list_size = ULP_THOR_ACT_TMPL_LIST_SIZE,
.tbl_list = ulp_thor_act_tbl_list,
.tbl_list_size = ULP_THOR_ACT_TBL_LIST_SIZE,
+ .key_info_list = ulp_thor_act_key_info_list,
+ .key_info_list_size = ULP_THOR_ACT_KEY_INFO_LIST_SIZE,
+ .ident_list = ulp_thor_act_ident_list,
+ .ident_list_size = ULP_THOR_ACT_IDENT_LIST_SIZE,
.cond_list = ulp_thor_act_cond_list,
.cond_list_size = ULP_THOR_ACT_COND_LIST_SIZE,
.result_field_list = ulp_thor_act_result_field_list,
@@ -202,6 +206,7 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE,
.encap_byte_order = BNXT_ULP_BYTE_ORDER_BE,
.wc_key_byte_order = BNXT_ULP_BYTE_ORDER_BE,
+ .em_byte_order = BNXT_ULP_BYTE_ORDER_LE,
.encap_byte_swap = 1,
.int_flow_db_num_entries = 16384,
.ext_flow_db_num_entries = 32768,
@@ -225,11 +230,12 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE,
.encap_byte_order = BNXT_ULP_BYTE_ORDER_BE,
.wc_key_byte_order = BNXT_ULP_BYTE_ORDER_BE,
+ .em_byte_order = BNXT_ULP_BYTE_ORDER_BE,
.encap_byte_swap = 1,
.int_flow_db_num_entries = 16384,
.ext_flow_db_num_entries = 32768,
- .mark_db_lfid_entries = 0,
- .mark_db_gfid_entries = 0,
+ .mark_db_lfid_entries = 65536,
+ .mark_db_gfid_entries = 65536,
.flow_count_db_entries = 16384,
.fdb_parent_flow_entries = 2,
.num_resources_per_flow = 8,
@@ -909,6 +915,14 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = {
{
.app_id = 0,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
@@ -941,12 +955,156 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = {
{
.app_id = 0,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
.direction = TF_DIR_RX
},
{
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
.app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1204,7 +1362,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 63
+ .count = 15
},
{
.app_id = 0,
@@ -1666,6 +1824,14 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.app_id = 0,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
.count = 200
@@ -1703,6 +1869,14 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 15232
},
{
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .count = 1
+ },
+ {
.app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
index 9faf25aaf0..223ecbf843 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Wed May 26 15:11:34 2021 */
+/* date: Thu Jul 8 08:44:00 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -15,16 +15,88 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {
/* act_tid: 1, ingress */
[1] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 2,
+ .num_tbls = 4,
.start_tbl_idx = 0,
.reject_info = {
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
.cond_start_idx = 0,
- .cond_nums = 4 }
+ .cond_nums = 0 }
+ },
+ /* act_tid: 2, ingress */
+ [2] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 6,
+ .start_tbl_idx = 4,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 3,
+ .cond_nums = 0 }
+ },
+ /* act_tid: 3, ingress */
+ [3] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 4,
+ .start_tbl_idx = 10,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 4,
+ .cond_nums = 0 }
+ },
+ /* act_tid: 4, egress */
+ [4] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 4,
+ .start_tbl_idx = 14,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 7,
+ .cond_nums = 0 }
+ },
+ /* act_tid: 5, egress */
+ [5] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 4,
+ .start_tbl_idx = 18,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 10,
+ .cond_nums = 0 }
+ },
+ /* act_tid: 6, egress */
+ [6] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 6,
+ .start_tbl_idx = 22,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 13,
+ .cond_nums = 0 }
}
};
struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
+ { /* act_tid: 1, , table: shared_mirror_record.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 0,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .key_start_idx = 0,
+ .blob_key_bit_size = 1,
+ .key_bit_size = 1,
+ .key_num_fields = 1,
+ .ident_start_idx = 0,
+ .ident_nums = 1
+ },
{ /* act_tid: 1, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
@@ -35,7 +107,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 4,
+ .cond_start_idx = 1,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
@@ -45,73 +117,4205 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.result_bit_size = 64,
.result_num_fields = 1
},
- { /* act_tid: 1, , table: int_full_act_record.0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 0,
- .cond_false_goto = 0,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 5,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 1,
- .result_bit_size = 128,
- .result_num_fields = 17
- }
-};
-
-struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = {
- /* cond_reject: thor, act_tid: 1 */
+ { /* act_tid: 1, , table: mod_record.ing_ttl */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 2,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 1,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 1, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 3,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 48,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* act_tid: 2, , table: control.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 3,
+ .cond_nums = 0 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* act_tid: 2, , table: mirror_tbl.alloc */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 3,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 65,
+ .result_bit_size = 32,
+ .result_num_fields = 5
+ },
+ { /* act_tid: 2, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 3,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 70,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 2, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 4,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 71,
+ .result_bit_size = 128,
+ .result_num_fields = 17,
+ .encap_num_fields = 0
+ },
+ { /* act_tid: 2, , table: mirror_tbl.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 4,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 88,
+ .result_bit_size = 32,
+ .result_num_fields = 5
+ },
+ { /* act_tid: 2, , table: shared_mirror_record.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 4,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .key_start_idx = 1,
+ .blob_key_bit_size = 1,
+ .key_bit_size = 1,
+ .key_num_fields = 1,
+ .result_start_idx = 93,
+ .result_bit_size = 36,
+ .result_num_fields = 2
+ },
+ { /* act_tid: 3, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 4,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 95,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 3, , table: mod_record.ing_ttl */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 5,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 96,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 3, , table: mod_record.ing_no_ttl */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 6,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 143,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 3, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 7,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 190,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* act_tid: 4, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 7,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 207,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 4, , table: int_vtag_encap_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 8,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 8,
+ .result_start_idx = 208,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 11
+ },
+ { /* act_tid: 4, , table: mod_record.dec_ttl_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 9,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 219,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 4, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 10,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 266,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* act_tid: 5, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 10,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 283,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 5, , table: mod_record.ing_ttl */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 11,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 284,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 5, , table: mod_record.ing_no_ttl */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 12,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 331,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 5, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 13,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 378,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* act_tid: 6, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 13,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 395,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 6, , table: sp_smac_ipv4.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 14,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 16,
+ .result_start_idx = 396,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 3
+ },
+ { /* act_tid: 6, , table: sp_smac_ipv6.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 15,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 32,
+ .result_start_idx = 399,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 3
+ },
+ { /* act_tid: 6, , table: int_tun_encap_record.ipv4_vxlan */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 16,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 402,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 30
+ },
+ { /* act_tid: 6, , table: int_tun_encap_record.ipv6_vxlan */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 18,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 432,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 30
+ },
+ { /* act_tid: 6, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 20,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 462,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ }
+};
+
+struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = {
+ /* cond_execute: act_tid: 1, shared_mirror_record.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+ },
+ /* cond_execute: act_tid: 1, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 1, mod_record.ing_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 2, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 3, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 3, mod_record.ing_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 3, mod_record.ing_no_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 4, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 4, int_vtag_encap_record.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
+ },
+ /* cond_execute: act_tid: 4, mod_record.dec_ttl_egr */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 5, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 5, mod_record.ing_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 5, mod_record.ing_no_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 6, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 6, sp_smac_ipv4.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG
+ },
+ /* cond_execute: act_tid: 6, sp_smac_ipv6.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG
+ },
+ /* cond_execute: act_tid: 6, int_tun_encap_record.ipv4_vxlan */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: act_tid: 6, int_tun_encap_record.ipv6_vxlan */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ }
+};
+
+struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = {
+ /* act_tid: 1, , table: shared_mirror_record.rd */
+ {
+ .field_info_mask = {
+ .description = "shared_index",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "shared_index",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff}
+ }
+ },
+ /* act_tid: 2, , table: shared_mirror_record.wr */
+ {
+ .field_info_mask = {
+ .description = "shared_index",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "shared_index",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
+ }
+ }
+};
+
+struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
+ /* act_tid: 1, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 1, , table: mod_record.ing_ttl */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ /* act_tid: 1, , table: int_full_act_record.0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr2 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_DECAP_FUNC_THRU_TUN},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_DECAP_FUNC_NONE}
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr2 = {
+ (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 2, , table: mirror_tbl.alloc */
+ {
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 13,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ignore_drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "copy_ing_or_egr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "enable",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 2, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 2, , table: int_full_act_record.0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 2, , table: mirror_tbl.wr */
+ {
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 13,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ignore_drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "copy_ing_or_egr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "enable",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 2, , table: shared_mirror_record.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "mirror_id",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
+ },
+ /* act_tid: 3, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 3, , table: mod_record.ing_ttl */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ /* act_tid: 3, , table: mod_record.ing_no_ttl */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ /* act_tid: 3, , table: int_full_act_record.0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 4, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 4, , table: int_vtag_encap_record.0 */
+ {
+ .description = "ecv_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
+ },
+ {
+ .description = "ecv_l2_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vtag_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}
+ },
+ {
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
+ },
+ {
+ .description = "vtag_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vtag_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
+ },
+ /* act_tid: 4, , table: mod_record.dec_ttl_egr */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ /* act_tid: 4, , table: int_full_act_record.0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
+ },
+ {
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 5, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 5, , table: mod_record.ing_ttl */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ /* act_tid: 5, , table: mod_record.ing_no_ttl */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ /* act_tid: 5, , table: int_full_act_record.0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 6, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 6, , table: sp_smac_ipv4.0 */
+ {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
+ },
+ {
+ .description = "ipv4_src_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 6, , table: sp_smac_ipv6.0 */
+ {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
+ },
+ {
+ .description = "ipv6_src_addr",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_SADDR & 0xff}
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 6, , table: int_tun_encap_record.ipv4_vxlan */
+ {
+ .description = "ecv_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_VALID_YES}
+ },
+ {
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
+ },
+ {
+ .description = "ecv_l2_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_L2_EN_YES}
+ },
+ {
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
+ },
+ {
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_L4_TYPE_UDP_CSUM}
+ },
+ {
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_TUN_TYPE_VXLAN}
+ },
+ {
+ .description = "enc_eth_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
+ },
+ {
+ .description = "enc_o_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_o_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_ihl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff}
+ },
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_POP_VLAN
+ .description = "enc_ipv4_tos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff}
},
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ .description = "enc_ipv4_pkt_id",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff}
},
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_VXLAN_DECAP
+ .description = "enc_ipv4_frag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff}
},
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+ .description = "enc_ipv4_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff}
},
- /* cond_execute: act_tid: 1, int_flow_counter_tbl.0 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_COUNT
- }
-};
-
-struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
- /* act_tid: 1, , table: int_flow_counter_tbl.0 */
+ .description = "enc_ipv4_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff}
+ },
{
- .description = "count",
- .field_bit_size = 64,
+ .description = "enc_ipv4_daddr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}
+ },
+ {
+ .description = "enc_ipv6_vtc",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv6_zero",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv6_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv6_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv6_daddr",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
+ },
+ {
+ .description = "enc_udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
+ },
+ {
+ .description = "enc_vxlan_flags",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}
+ },
+ {
+ .description = "enc_vxlan_rsvd0",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}
+ },
+ {
+ .description = "enc_vxlan_vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
+ },
+ {
+ .description = "enc_vxlan_rsvd1",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}
+ },
+ /* act_tid: 6, , table: int_tun_encap_record.ipv6_vxlan */
+ {
+ .description = "ecv_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_VALID_YES}
+ },
+ {
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 1, , table: int_full_act_record.0 */
{
- .description = "sp_rec_ptr",
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
+ },
+ {
+ .description = "ecv_l2_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_L2_EN_YES}
+ },
+ {
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
+ },
+ {
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_L4_TYPE_UDP_CSUM}
+ },
+ {
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_TUN_TYPE_VXLAN}
+ },
+ {
+ .description = "enc_eth_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
+ },
+ {
+ .description = "enc_o_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_o_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_ihl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv4_tos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv4_pkt_id",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv4_frag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv4_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv4_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv4_daddr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv6_vtc",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff}
+ },
+ {
+ .description = "enc_ipv6_zero",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
+ .description = "enc_ipv6_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff}
+ },
+ {
+ .description = "enc_ipv6_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff}
+ },
+ {
+ .description = "enc_ipv6_daddr",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff}
+ },
+ {
+ .description = "enc_udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
+ },
+ {
+ .description = "enc_udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
+ },
+ {
+ .description = "enc_vxlan_flags",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}
+ },
+ {
+ .description = "enc_vxlan_rsvd0",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}
+ },
+ {
+ .description = "enc_vxlan_vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
+ },
+ {
+ .description = "enc_vxlan_rsvd1",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}
+ },
+ /* act_tid: 6, , table: int_full_act_record.0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_SP_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_SP_PTR & 0xff}
+ },
+ {
.description = "encap_ptr",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
},
{
.description = "mod_rec_ptr",
@@ -164,8 +4368,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
},
{
.description = "use_default",
@@ -195,16 +4399,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "drop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "hit",
@@ -221,3 +4416,13 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
1}
}
};
+
+struct bnxt_ulp_mapper_ident_info ulp_thor_act_ident_list[] = {
+ /* act_tid: 1, , table: shared_mirror_record.rd */
+ {
+ .description = "mirror_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_MIRROR_ID_0,
+ .ident_bit_size = 4,
+ .ident_bit_pos = 32
+ }
+};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
index ea9b9773a5..bcb204ae13 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Wed May 26 15:11:34 2021 */
+/* date: Fri Jul 30 09:57:44 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -15,32 +15,52 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {
/* class_tid: 1, ingress */
[1] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 12,
+ .num_tbls = 28,
.start_tbl_idx = 0,
.reject_info = {
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 0,
- .cond_nums = 4 }
+ .cond_nums = 1 }
+ },
+ /* class_tid: 2, ingress */
+ [2] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 17,
+ .start_tbl_idx = 28,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 29,
+ .cond_nums = 0 }
+ },
+ /* class_tid: 3, egress */
+ [3] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 24,
+ .start_tbl_idx = 45,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 36,
+ .cond_nums = 0 }
},
/* class_tid: 4, ingress */
[4] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 15,
- .start_tbl_idx = 12,
+ .num_tbls = 21,
+ .start_tbl_idx = 69,
.reject_info = {
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 8,
- .cond_nums = 1 }
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 }
},
/* class_tid: 5, egress */
[5] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 6,
- .start_tbl_idx = 27,
+ .num_tbls = 24,
+ .start_tbl_idx = 90,
.reject_info = {
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 12,
- .cond_nums = 1 }
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 }
}
};
@@ -54,7 +74,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 4,
+ .cond_start_idx = 1,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
@@ -76,7 +96,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 5,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 4,
+ .cond_start_idx = 1,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
@@ -97,7 +117,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 5,
+ .cond_start_idx = 2,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
@@ -116,7 +136,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 3,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 5,
+ .cond_start_idx = 2,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
@@ -129,7 +149,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 6,
+ .cond_start_idx = 3,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
@@ -156,7 +176,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 6,
+ .cond_start_idx = 3,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
@@ -169,17 +189,28 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 1, , table: profile_tcam_cache.l3_l4_rd */
+ { /* class_tid: 1, , table: control.ipv6_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 8,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 3,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* class_tid: 1, , table: profile_tcam_cache.ipv6_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 6,
- .cond_nums = 0 },
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 4,
+ .cond_nums = 1 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
@@ -188,23 +219,41 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.key_bit_size = 14,
.key_num_fields = 3,
.ident_start_idx = 6,
- .ident_nums = 0
+ .ident_nums = 4
},
- { /* class_tid: 1, , table: control.l3_l4 */
+ { /* class_tid: 1, , table: control.ipv6_prof_cache_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 4,
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 6,
+ .cond_start_idx = 5,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 1, , table: fkb_select.l3_l4_wm */
+ { /* class_tid: 1, , table: control.v6_conflict_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 4,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 6,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .func_info = {
+ .func_opc = BNXT_ULP_FUNC_OPC_EQ,
+ .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
+ .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
+ .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
+ },
+ { /* class_tid: 1, , table: fkb_select.l2_l3_l4_v6_em */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
@@ -212,23 +261,24 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 7,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
- .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
.result_start_idx = 10,
.result_bit_size = 106,
.result_num_fields = 106
},
- { /* class_tid: 1, , table: profile_tcam.l3_l4 */
+ { /* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 7,
- .cond_nums = 0 },
+ .cond_nums = 1 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
@@ -244,11 +294,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_start_idx = 116,
.result_bit_size = 33,
.result_num_fields = 8,
- .ident_start_idx = 6,
- .ident_nums = 0
+ .ident_start_idx = 10,
+ .ident_nums = 1
},
- { /* class_tid: 1, , table: profile_tcam_cache.l3_l4_wr */
+ { /* class_tid: 1, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_RX,
@@ -256,7 +307,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 7,
+ .cond_start_idx = 8,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
@@ -269,4026 +320,39779 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 138,
.result_num_fields = 7
},
- { /* class_tid: 1, , table: wm.l3_l4 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ { /* class_tid: 1, , table: em.l2_l3_l4_v6.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_INTERNAL,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 0,
- .cond_false_goto = 0,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 7,
- .cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 8,
+ .cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
- .pri_operand = 0,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.key_start_idx = 82,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
.result_start_idx = 131,
- .result_bit_size = 38,
- .result_num_fields = 5
+ .result_bit_size = 0,
+ .result_num_fields = 6
},
- { /* class_tid: 4, , table: int_full_act_record.0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ { /* class_tid: 1, , table: profile_tcam_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 9,
+ .cond_start_idx = 8,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 136,
- .result_bit_size = 128,
- .result_num_fields = 17
+ .key_start_idx = 196,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .ident_start_idx = 11,
+ .ident_nums = 2
},
- { /* class_tid: 4, , table: port_table.wr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
+ { /* class_tid: 1, , table: control.gen_tbl_miss */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 9,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 196,
- .blob_key_bit_size = 10,
- .key_bit_size = 10,
- .key_num_fields = 1,
- .result_start_idx = 153,
- .result_bit_size = 152,
- .result_num_fields = 5
+ .cond_false_goto = 6,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 8,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ { /* class_tid: 1, , table: fkb_select.l3_l4_wm */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 9,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 197,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .ident_start_idx = 6,
- .ident_nums = 0
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 137,
+ .result_bit_size = 106,
+ .result_num_fields = 106
},
- { /* class_tid: 4, , table: control.ing_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ { /* class_tid: 1, , table: fkb_select.l3_l4_wm_vxlan */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 3,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 9,
+ .cond_start_idx = 10,
.cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 243,
+ .result_bit_size = 106,
+ .result_num_fields = 106
},
- { /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
+ { /* class_tid: 1, , table: profile_tcam.l3_l4.ip */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 11,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 199,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 349,
+ .result_bit_size = 33,
+ .result_num_fields = 8,
+ .ident_start_idx = 13,
+ .ident_nums = 0
+ },
+ { /* class_tid: 1, , table: profile_tcam.l3_l4.vxlan */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 10,
- .cond_nums = 0 },
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 13,
+ .cond_nums = 1 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 198,
- .blob_key_bit_size = 213,
- .key_bit_size = 213,
- .key_num_fields = 21,
- .result_start_idx = 158,
- .result_bit_size = 43,
- .result_num_fields = 6,
- .ident_start_idx = 6,
- .ident_nums = 1
+ .key_start_idx = 242,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 357,
+ .result_bit_size = 33,
+ .result_num_fields = 8,
+ .ident_start_idx = 13,
+ .ident_nums = 0
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
+ { /* class_tid: 1, , table: profile_tcam_cache.wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 10,
+ .cond_start_idx = 14,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 219,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .result_start_idx = 164,
- .result_bit_size = 62,
- .result_num_fields = 4
+ .key_start_idx = 285,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .result_start_idx = 365,
+ .result_bit_size = 138,
+ .result_num_fields = 7
},
- { /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+ { /* class_tid: 1, , table: wm.l3_l4.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 10,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 168,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 14,
+ .cond_nums = 3 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 288,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 372,
+ .result_bit_size = 38,
+ .result_num_fields = 5
},
- { /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
- .direction = TF_DIR_RX,
+ { /* class_tid: 1, , table: wm.l3_l4.ipv6 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 10,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 169,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 17,
+ .cond_nums = 3 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 402,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 377,
+ .result_bit_size = 38,
+ .result_num_fields = 5
},
- { /* class_tid: 4, , table: control.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ { /* class_tid: 1, , table: wm.l3.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 0,
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 10,
+ .cond_start_idx = 20,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 516,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 382,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 1, , table: wm.l3.ipv6 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 22,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 630,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 387,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 1, , table: wm.l2 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 24,
.cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 744,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 392,
+ .result_bit_size = 38,
+ .result_num_fields = 5
},
- { /* class_tid: 4, , table: int_full_act_record.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ { /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 25,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 858,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 397,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv6 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 27,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 972,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 402,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 2, , table: port_table.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 11,
+ .cond_start_idx = 29,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 170,
- .result_bit_size = 128,
- .result_num_fields = 17,
- .encap_num_fields = 0
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .key_start_idx = 1086,
+ .blob_key_bit_size = 10,
+ .key_bit_size = 10,
+ .key_num_fields = 1,
+ .ident_start_idx = 13,
+ .ident_nums = 3
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */
+ { /* class_tid: 2, , table: tunnel_cache.rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 11,
+ .cond_start_idx = 29,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 220,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .ident_start_idx = 7,
- .ident_nums = 0
+ .key_start_idx = 1087,
+ .blob_key_bit_size = 16,
+ .key_bit_size = 16,
+ .key_num_fields = 2,
+ .ident_start_idx = 16,
+ .ident_nums = 1
},
- { /* class_tid: 4, , table: control.egr_1 */
+ { /* class_tid: 2, , table: control.tunnel_cache_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 2,
+ .cond_false_goto = 3,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 11,
+ .cond_start_idx = 29,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
+ { /* class_tid: 2, , table: l2_cntxt_tcam.1 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .direction = TF_DIR_TX,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 12,
+ .cond_start_idx = 30,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT,
.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 221,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .key_start_idx = 1089,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
- .result_start_idx = 187,
+ .result_start_idx = 407,
.result_bit_size = 43,
.result_num_fields = 6,
- .ident_start_idx = 7,
+ .ident_start_idx = 17,
.ident_nums = 1
},
- { /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
- .direction = TF_DIR_TX,
+ { /* class_tid: 2, , table: tunnel_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 12,
+ .cond_start_idx = 30,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 193,
- .result_bit_size = 32,
- .result_num_fields = 1
- },
- { /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
- .direction = TF_DIR_TX,
+ .key_start_idx = 1110,
+ .blob_key_bit_size = 16,
+ .key_bit_size = 16,
+ .key_num_fields = 2,
+ .result_start_idx = 413,
+ .result_bit_size = 52,
+ .result_num_fields = 3
+ },
+ { /* class_tid: 2, , table: control.flow_type_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 0,
- .cond_false_goto = 0,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 12,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 194,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .cond_true_goto = 1,
+ .cond_false_goto = 5,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 30,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
- { /* class_tid: 5, , table: int_full_act_record.loopback */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ { /* class_tid: 2, , table: mac_addr_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 13,
+ .cond_start_idx = 31,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE,
- .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 195,
- .result_bit_size = 128,
- .result_num_fields = 17,
- .encap_num_fields = 0
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1112,
+ .blob_key_bit_size = 73,
+ .key_bit_size = 73,
+ .key_num_fields = 5,
+ .ident_start_idx = 18,
+ .ident_nums = 1
},
- { /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
- .direction = TF_DIR_TX,
+ { /* class_tid: 2, , table: control.mac_addr_cache_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 31,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 2, , table: l2_cntxt_tcam.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 13,
+ .cond_start_idx = 32,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
- .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 212,
- .result_bit_size = 32,
- .result_num_fields = 1
- },
- { /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
- .direction = TF_DIR_TX,
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .key_start_idx = 1117,
+ .blob_key_bit_size = 213,
+ .key_bit_size = 213,
+ .key_num_fields = 21,
+ .result_start_idx = 416,
+ .result_bit_size = 43,
+ .result_num_fields = 6,
+ .ident_start_idx = 19,
+ .ident_nums = 0
+ },
+ { /* class_tid: 2, , table: mac_addr_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 13,
+ .cond_start_idx = 32,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
- .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 213,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .key_start_idx = 1138,
+ .blob_key_bit_size = 73,
+ .key_bit_size = 73,
+ .key_num_fields = 5,
+ .result_start_idx = 422,
+ .result_bit_size = 62,
+ .result_num_fields = 4
},
- { /* class_tid: 5, , table: int_full_act_record.vf_ing */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 13,
+ .cond_start_idx = 32,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
- .result_start_idx = 214,
- .result_bit_size = 128,
- .result_num_fields = 17,
- .encap_num_fields = 0
+ .key_start_idx = 1143,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .ident_start_idx = 19,
+ .ident_nums = 3
+ },
+ { /* class_tid: 2, , table: control.profile_tcam_cache.f2_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 4,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 32,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 5, , table: vtag_encap_record.vfr_egr0 */
+ { /* class_tid: 2, , table: fkb_select.f2_wm */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 33,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 426,
+ .result_bit_size = 106,
+ .result_num_fields = 106
+ },
+ { /* class_tid: 2, , table: profile_tcam.f2 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 34,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 1,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 1146,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 532,
+ .result_bit_size = 33,
+ .result_num_fields = 8
+ },
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 13,
+ .cond_start_idx = 34,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1189,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .result_start_idx = 540,
+ .result_bit_size = 138,
+ .result_num_fields = 7
+ },
+ { /* class_tid: 2, , table: wm.l3_l4.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 34,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .record_size = 16,
- .result_start_idx = 231,
- .result_bit_size = 0,
- .result_num_fields = 0,
- .encap_num_fields = 11
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 1192,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 547,
+ .result_bit_size = 38,
+ .result_num_fields = 5
},
- { /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
+ { /* class_tid: 2, , table: wm.l3_l4.ipv6 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 0,
.cond_false_goto = 0,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 13,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 35,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 242,
- .result_bit_size = 128,
- .result_num_fields = 17
- }
-};
-
-struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {
- /* cond_reject: thor, class_tid: 1 */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
- .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 1306,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 552,
+ .result_bit_size = 38,
+ .result_num_fields = 5
},
- {
- .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET,
- .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC
+ { /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 6,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 36,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1420,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 22,
+ .ident_nums = 1
},
- {
- .cond_opcode = BNXT_ULP_COND_OPC_FLOW_PAT_MATCH,
- .cond_operand = 2
+ { /* class_tid: 3, , table: mac_addr_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 37,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1421,
+ .blob_key_bit_size = 73,
+ .key_bit_size = 73,
+ .key_num_fields = 5,
+ .ident_start_idx = 23,
+ .ident_nums = 1
},
- {
- .cond_opcode = BNXT_ULP_COND_OPC_FLOW_PAT_MATCH,
- .cond_operand = 3
+ { /* class_tid: 3, , table: control.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 4,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 37,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
- /* cond_execute: class_tid: 1, l2_cntxt_tcam_cache.rd */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET,
- .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC
+ { /* class_tid: 3, , table: port_table.egr.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 38,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .key_start_idx = 1426,
+ .blob_key_bit_size = 10,
+ .key_bit_size = 10,
+ .key_num_fields = 1,
+ .ident_start_idx = 24,
+ .ident_nums = 3
},
- /* cond_execute: class_tid: 1, control.0 */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
- .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ { /* class_tid: 3, , table: l2_cntxt_tcam.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 38,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .key_start_idx = 1427,
+ .blob_key_bit_size = 213,
+ .key_bit_size = 213,
+ .key_num_fields = 21,
+ .result_start_idx = 557,
+ .result_bit_size = 43,
+ .result_num_fields = 6,
+ .ident_start_idx = 27,
+ .ident_nums = 1
},
- /* cond_execute: class_tid: 1, control.l3_l4 */
- {
+ { /* class_tid: 3, , table: mac_addr_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 38,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1448,
+ .blob_key_bit_size = 73,
+ .key_bit_size = 73,
+ .key_num_fields = 5,
+ .result_start_idx = 563,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 3, , table: control.ipv6_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 8,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 38,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* class_tid: 3, , table: profile_tcam_cache.ipv6_rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 39,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1453,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .ident_start_idx = 28,
+ .ident_nums = 4
+ },
+ { /* class_tid: 3, , table: control.ipv6_prof_cache_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 40,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 3, , table: control.v6_conflict_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 4,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 41,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .func_info = {
+ .func_opc = BNXT_ULP_FUNC_OPC_EQ,
+ .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
+ .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
+ .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
+ },
+ { /* class_tid: 3, , table: fkb_select.l2_l3_l4_v6_em */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 42,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .result_start_idx = 567,
+ .result_bit_size = 106,
+ .result_num_fields = 106
+ },
+ { /* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 42,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 1456,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 673,
+ .result_bit_size = 33,
+ .result_num_fields = 8,
+ .ident_start_idx = 32,
+ .ident_nums = 1
+ },
+ { /* class_tid: 3, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 42,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1499,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .result_start_idx = 681,
+ .result_bit_size = 138,
+ .result_num_fields = 7
+ },
+ { /* class_tid: 3, , table: em.l2_l3_l4_v6.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_INTERNAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 42,
+ .cond_nums = 0 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 1502,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 688,
+ .result_bit_size = 0,
+ .result_num_fields = 6
+ },
+ { /* class_tid: 3, , table: profile_tcam_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 42,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1616,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .ident_start_idx = 33,
+ .ident_nums = 2
+ },
+ { /* class_tid: 3, , table: control.gen_tbl_miss */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 42,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 3, , table: control.conflict_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 5,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 43,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .func_info = {
+ .func_opc = BNXT_ULP_FUNC_OPC_EQ,
+ .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
+ .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
+ .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
+ },
+ { /* class_tid: 3, , table: fkb_select.l3_l4_wc */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 44,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 694,
+ .result_bit_size = 106,
+ .result_num_fields = 106
+ },
+ { /* class_tid: 3, , table: profile_tcam.l3_l4.ip */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 44,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 1619,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 800,
+ .result_bit_size = 33,
+ .result_num_fields = 8,
+ .ident_start_idx = 35,
+ .ident_nums = 0
+ },
+ { /* class_tid: 3, , table: profile_tcam.l3_l4.nonip */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 45,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 1662,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 808,
+ .result_bit_size = 33,
+ .result_num_fields = 8,
+ .ident_start_idx = 35,
+ .ident_nums = 0
+ },
+ { /* class_tid: 3, , table: profile_tcam_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 45,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1705,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .result_start_idx = 816,
+ .result_bit_size = 138,
+ .result_num_fields = 7
+ },
+ { /* class_tid: 3, , table: wm.l3_l4.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 45,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 1708,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 823,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 3, , table: wm.l3.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 47,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 1822,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 828,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 3, , table: wm.l2 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 1936,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 833,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 4, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 838,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* class_tid: 4, , table: port_table.ing_wr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2050,
+ .blob_key_bit_size = 10,
+ .key_bit_size = 10,
+ .key_num_fields = 1,
+ .result_start_idx = 855,
+ .result_bit_size = 152,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2051,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 35,
+ .ident_nums = 0
+ },
+ { /* class_tid: 4, , table: control.ing_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 48,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 2052,
+ .blob_key_bit_size = 213,
+ .key_bit_size = 213,
+ .key_num_fields = 21,
+ .result_start_idx = 860,
+ .result_bit_size = 43,
+ .result_num_fields = 6,
+ .ident_start_idx = 35,
+ .ident_nums = 1
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2073,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 866,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 870,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 871,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 4, , table: int_full_act_record.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 872,
+ .result_bit_size = 128,
+ .result_num_fields = 17,
+ .encap_num_fields = 0
+ },
+ { /* class_tid: 4, , table: port_table.egr_wr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2074,
+ .blob_key_bit_size = 10,
+ .key_bit_size = 10,
+ .key_num_fields = 1,
+ .result_start_idx = 889,
+ .result_bit_size = 152,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 4, , table: control.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 5,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 49,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd_vfr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 50,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2075,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 36,
+ .ident_nums = 0
+ },
+ { /* class_tid: 4, , table: control.egr_1 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 50,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 4, , table: ilt_tbl.egr_vfr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_ILT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 51,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .result_start_idx = 894,
+ .result_bit_size = 64,
+ .result_num_fields = 8
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 51,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2076,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 902,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 51,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2077,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 36,
+ .ident_nums = 0
+ },
+ { /* class_tid: 4, , table: control.egr_2 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 51,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 2078,
+ .blob_key_bit_size = 213,
+ .key_bit_size = 213,
+ .key_num_fields = 21,
+ .result_start_idx = 906,
+ .result_bit_size = 43,
+ .result_num_fields = 6,
+ .ident_start_idx = 36,
+ .ident_nums = 1
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2099,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 912,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 916,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 917,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 5, , table: int_full_act_record.loopback */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 918,
+ .result_bit_size = 128,
+ .result_num_fields = 17,
+ .encap_num_fields = 0
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2100,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 37,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: control.vf_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 52,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 53,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .key_start_idx = 2101,
+ .blob_key_bit_size = 213,
+ .key_bit_size = 213,
+ .key_num_fields = 21,
+ .result_start_idx = 935,
+ .result_bit_size = 43,
+ .result_num_fields = 6,
+ .ident_start_idx = 37,
+ .ident_nums = 1
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 53,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2122,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 941,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 53,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
+ .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 945,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 53,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
+ .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 946,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 5, , table: int_full_act_record.vf_ing */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 53,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
+ .result_start_idx = 947,
+ .result_bit_size = 128,
+ .result_num_fields = 17,
+ .encap_num_fields = 0
+ },
+ { /* class_tid: 5, , table: ilt_tbl.vf_ing */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_ILT,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 53,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_SVIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 964,
+ .result_bit_size = 64,
+ .result_num_fields = 8
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.rd_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 53,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2123,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 38,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: control.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 53,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 5, , table: ilt_tbl.vfr_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_ILT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .result_start_idx = 972,
+ .result_bit_size = 64,
+ .result_num_fields = 8
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2124,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 980,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 5, , table: metadata_record.vfr_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 984,
+ .result_bit_size = 16,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 5, , table: mod_record.vfr_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 985,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* class_tid: 5, , table: int_full_act_record.vfr_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 1032,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_rd_vfr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2125,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 38,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: control.ing_rd_vfr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 5,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 54,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam.vfr_ing0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 2126,
+ .blob_key_bit_size = 213,
+ .key_bit_size = 213,
+ .key_num_fields = 21,
+ .result_start_idx = 1049,
+ .result_bit_size = 43,
+ .result_num_fields = 6,
+ .ident_start_idx = 38,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: fkb_select.vfr_em */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 1055,
+ .result_bit_size = 106,
+ .result_num_fields = 106
+ },
+ { /* class_tid: 5, , table: profile_tcam.vfr_ing0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 2147,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 1161,
+ .result_bit_size = 33,
+ .result_num_fields = 8
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_wr_vfr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2190,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 38,
+ .ident_nums = 1
+ },
+ { /* class_tid: 5, , table: int_full_act_record.vfr_ing0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 1169,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* class_tid: 5, , table: em.vfr.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_INTERNAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 2191,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 1186,
+ .result_bit_size = 0,
+ .result_num_fields = 6
+ }
+};
+
+struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {
+ /* cond_reject: thor, class_tid: 1 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH
+ },
+ /* cond_execute: class_tid: 1, l2_cntxt_tcam_cache.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC
+ },
+ /* cond_execute: class_tid: 1, control.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 1, control.ipv6_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ },
+ /* cond_execute: class_tid: 1, profile_tcam_cache.ipv6_rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH
+ },
+ /* cond_execute: class_tid: 1, control.ipv6_prof_cache_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 1, control.v6_conflict_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_CC
+ },
+ /* cond_execute: class_tid: 1, profile_tcam.l2_l3_l4_v6_em */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, control.gen_tbl_miss */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 1, fkb_select.l3_l4_wm */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, fkb_select.l3_l4_wm_vxlan */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, profile_tcam.l3_l4.ip */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_O_L3
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, profile_tcam.l3_l4.vxlan */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, wm.l3_l4.ipv4 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_O_L4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, wm.l3_l4.ipv6 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_O_L4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, wm.l3.ipv4 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, wm.l3.ipv6 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, wm.l2 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, wm.l3_l4.vxlan.ipv4 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ /* cond_execute: class_tid: 1, wm.l3_l4.vxlan.ipv6 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ },
+ /* cond_execute: class_tid: 2, control.tunnel_cache_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 2, control.flow_type_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_F1
+ },
+ /* cond_execute: class_tid: 2, control.mac_addr_cache_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 2, control.profile_tcam_cache.f2_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 2, fkb_select.f2_wm */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 2, wm.l3_l4.ipv4 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ /* cond_execute: class_tid: 2, wm.l3_l4.ipv6 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ },
+ /* cond_execute: class_tid: 3, l2_cntxt_tcam_cache.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC
+ },
+ /* cond_execute: class_tid: 3, control.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 3, control.ipv6_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ },
+ /* cond_execute: class_tid: 3, profile_tcam_cache.ipv6_rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH
+ },
+ /* cond_execute: class_tid: 3, control.ipv6_prof_cache_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 3, control.v6_conflict_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_CC
+ },
+ /* cond_execute: class_tid: 3, control.gen_tbl_miss */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 3, control.conflict_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_CC
+ },
+ /* cond_execute: class_tid: 3, profile_tcam.l3_l4.ip */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_O_L3
+ },
+ /* cond_execute: class_tid: 3, wm.l3_l4.ipv4 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_O_L4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ /* cond_execute: class_tid: 3, wm.l3.ipv4 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ /* cond_execute: class_tid: 4, control.ing_0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 4, control.egr_0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
+ },
+ /* cond_execute: class_tid: 4, control.egr_1 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 4, control.egr_2 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 5, control.vf_0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 5, control.0 */
+ {
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 1, wm.l3_l4 */
+ /* cond_execute: class_tid: 5, control.ing_rd_vfr */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ }
+};
+
+struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
+ /* class_tid: 1, , table: port_table.rd */
+ {
+ .field_info_mask = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: l2_cntxt_tcam_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: mac_addr_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: l2_cntxt_tcam.0 */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 2}
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 1, , table: mac_addr_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.ipv6_rd */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_UDP}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_YES},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_NO}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: em.l2_l3_l4_v6.0 */
+ {
+ .field_info_mask = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: profile_tcam.l3_l4.ip */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_UDP}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L4_HDR_VALID_YES},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L4_HDR_VALID_IGNORE}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV4},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_YES},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_NO}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 1, , table: profile_tcam.l3_l4.vxlan */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL4_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV4},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_TL2_VTAG_PRESENT_YES},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_TL2_VTAG_PRESENT_NO}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: wm.l3_l4.ipv4 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 1, , table: wm.l3_l4.ipv6 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 1, , table: wm.l3.ipv4 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 1, , table: wm.l3.ipv6 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 1, , table: wm.l2 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv4 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv6 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 2, , table: port_table.rd */
+ {
+ .field_info_mask = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: tunnel_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_TUNNEL_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_TUNNEL_ID & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 2, , table: tunnel_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_TUNNEL_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_TUNNEL_ID & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: mac_addr_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: l2_cntxt_tcam.0 */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 2}
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 2, , table: mac_addr_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: profile_tcam.f2 */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL4_HDR_TYPE_UDP}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL4_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: wm.l3_l4.ipv4 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 2, , table: wm.l3_l4.ipv6 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: mac_addr_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: port_table.egr.rd */
+ {
+ .field_info_mask = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam.0 */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 3, , table: mac_addr_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam_cache.ipv6_rd */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_UDP}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_YES},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_NO}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: em.l2_l3_l4_v6.0 */
+ {
+ .field_info_mask = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam.l3_l4.ip */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_UDP}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV4},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_YES},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_NO}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam.l3_l4.nonip */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_YES},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_NO}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: wm.l3_l4.ipv4 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 3, , table: wm.l3.ipv4 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 3, , table: wm.l2 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 4, , table: port_table.ing_wr_0 */
+ {
+ .field_info_mask = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: port_table.egr_wr_0 */
+ {
+ .field_info_mask = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd_vfr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.rd_egr0 */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_rd_vfr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam.vfr_ing0 */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: profile_tcam.vfr_ing0 */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_wr_vfr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: em.vfr.0 */
+ {
+ .field_info_mask = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ }
+};
+
+struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
+ /* class_tid: 1, , table: l2_cntxt_tcam.0 */
+ {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ },
+ {
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ },
+ {
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ },
+ /* class_tid: 1, , table: mac_addr_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: fkb_select.l2_l3_l4_v6_em */
+ {
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "parif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "spif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "lcos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "loopback.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tuntype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tflags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tqos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "terr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ },
+ {
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ },
+ {
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ },
+ {
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}
+ },
+ {
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}
+ },
+ {
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_win.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ },
+ /* class_tid: 1, , table: em.l2_l3_l4_v6.0 */
+ {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: fkb_select.l3_l4_wm */
+ {
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "parif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "spif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "lcos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "loopback.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tuntype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tflags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tqos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "terr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_win.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: fkb_select.l3_l4_wm_vxlan */
+ {
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "parif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "spif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "lcos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "loopback.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tuntype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tflags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tqos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "terr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_win.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.l3_l4.ip */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.l3_l4.vxlan */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 & 0xff}
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ },
+ /* class_tid: 1, , table: wm.l3_l4.ipv4 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 1, , table: wm.l3_l4.ipv6 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 1, , table: wm.l3.ipv4 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 1, , table: wm.l3.ipv6 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 1, , table: wm.l2 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv4 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv6 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
+ {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 2, , table: tunnel_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ /* class_tid: 2, , table: l2_cntxt_tcam.0 */
+ {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
+ },
+ {
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ },
+ {
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ },
+ /* class_tid: 2, , table: mac_addr_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 2, , table: fkb_select.f2_wm */
+ {
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "parif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "spif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "lcos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "loopback.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tuntype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tflags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tqos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "terr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_win.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 2, , table: profile_tcam.f2 */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 & 0xff}
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ },
+ /* class_tid: 2, , table: wm.l3_l4.ipv4 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 2, , table: wm.l3_l4.ipv6 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam.0 */
+ {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}
+ },
+ {
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ },
+ {
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ },
+ /* class_tid: 3, , table: mac_addr_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 3, , table: fkb_select.l2_l3_l4_v6_em */
+ {
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "parif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "spif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "lcos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "loopback.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
{
- .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
- .cond_operand = BNXT_ULP_CF_IDX_O_L4
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_reject: thor, class_tid: 4 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
- .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: class_tid: 4, control.ing_0 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
- .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: class_tid: 4, control.egr_0 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
- .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: class_tid: 4, control.egr_1 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
- .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tuntype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tflags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tqos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "terr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ {
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ },
+ {
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ },
+ {
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_reject: thor, class_tid: 5 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
- .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
- }
-};
-
-struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
- /* class_tid: 1, , table: port_table.rd */
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
{
- .field_info_mask = {
- .description = "dev.port_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "dev.port_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
- }
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: l2_cntxt_tcam_cache.rd */
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- }
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: mac_addr_cache.rd */
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- }
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
- },
- .field_info_spec = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
- }
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
- },
- .field_info_spec = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
- }
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: l2_cntxt_tcam.0 */
{
- .field_info_mask = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}
},
{
- .field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}
},
{
- .field_info_mask = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_win.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
- },
- .field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
- }
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
- },
- .field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
- }
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- }
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 2}
- },
- .field_info_spec = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- .field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- }
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: mac_addr_cache.wr */
+ /* class_tid: 3, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- }
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .field_info_mask = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
- },
- .field_info_spec = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
- }
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "em_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
- },
- .field_info_spec = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
- }
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam_cache.l3_l4_rd */
{
- .field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "wc_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
- }
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
+ /* class_tid: 3, , table: em.l2_l3_l4_v6.0 */
{
- .field_info_mask = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
- }
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
- /* class_tid: 1, , table: profile_tcam.l3_l4 */
{
- .field_info_mask = {
- .description = "l4_hdr_is_udp_tcp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l4_hdr_is_udp_tcp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
},
{
- .field_info_mask = {
- .description = "l4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_THOR_SYM_L4_HDR_TYPE_TCP},
- .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr3 = {
- ULP_THOR_SYM_L4_HDR_TYPE_UDP}
- }
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
- },
- .field_info_spec = {
- .description = "l4_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
- },
- .field_info_spec = {
- .description = "l4_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
- }
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 3, , table: fkb_select.l3_l4_wc */
{
- .field_info_mask = {
- .description = "ieh",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "ieh",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "l3_ipv6_cmp_dst",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l3_ipv6_cmp_dst",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "parif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "spif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "l3_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "lcos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "l3_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "meta.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "l3_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_L3_HDR_VALID_YES}
- }
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "loopback.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_uc_mc_bc",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "l2_uc_mc_bc",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_hdr_type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "l2_hdr_type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "l2_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "l2_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_L2_HDR_VALID_YES}
- }
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tun_hdr_flags",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tun_hdr_flags",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tun_hdr_err",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tun_hdr_err",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tun_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "tun_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4_hdr_is_udp_tcp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl4_hdr_is_udp_tcp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl4_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "tl4_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3_ipv6_cmp_dst",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl3_ipv6_cmp_dst",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3_ipv6_cmp_src",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl3_ipv6_cmp_src",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3_hdr_isIP",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl3_hdr_isIP",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl3_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl3_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "tl3_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl2_two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl2_vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_uc_mc_bc",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl2_uc_mc_bc",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_hdr_type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl2_hdr_type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "tl2_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "hrec_next",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "hrec_next",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
- }
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "agg_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "agg_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "pkt_type_0",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "pkt_type_0",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "pkt_type_1",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "pkt_type_1",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- .field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- }
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam_cache.l3_l4_wr */
{
- .field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
- }
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
- }
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l3_l4 */
{
- .field_info_mask = {
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
- }
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
- }
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "lcos",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "lcos",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "meta",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "meta",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "rcyc_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "rcyc_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tuntype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tflags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_l2type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_l2type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tctxts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_dt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_dt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tctxt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_sa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_sa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tqos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_nvt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_nvt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "terr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "tl2_ovp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ovp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_ovd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ovd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_ovv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ovv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_ovt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ovt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_ivp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ivp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_ivd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ivd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_ivv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ivv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_ivt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ivt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.l3type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.l3type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.sip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.sip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "tl3.sip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.sip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.sip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.sip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.dip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.dip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.dip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.dip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "tl3.dip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.dip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.fid.ipv4",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.fid.ipv4",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.fid.ipv6",
- .field_bit_size = 20,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.fid.ipv6",
- .field_bit_size = 20,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.qos",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.qos",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_nonext",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_nonext",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_esp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_esp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_auth",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_auth",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.l3err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.l3err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "tl4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "tl4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_win.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tuntype",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tuntype",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tflags",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tflags",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tids",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tids",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tid",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tid",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 3, , table: profile_tcam.l3_l4.ip */
{
- .field_info_mask = {
- .description = "tctxts",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tctxts",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 & 0xff}
},
{
- .field_info_mask = {
- .description = "tctxt",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tctxt",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
},
{
- .field_info_mask = {
- .description = "tqos",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tqos",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "terr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "terr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_l2type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_l2type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_dt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_dt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 3, , table: profile_tcam.l3_l4.nonip */
{
- .field_info_mask = {
- .description = "l2_sa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_sa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 & 0xff}
},
{
- .field_info_mask = {
- .description = "l2_nvt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_nvt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
},
{
- .field_info_mask = {
- .description = "l2_ovp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ovp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "l2_ovd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ovd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ovv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ovv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ovt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ovt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ivp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ivp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ivd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ivd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 3, , table: profile_tcam_cache.wr */
{
- .field_info_mask = {
- .description = "l2_ivv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ivv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .field_info_mask = {
- .description = "l2_ivt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ivt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "l2_etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.l3type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.l3type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.sip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
- },
- .field_info_spec = {
- .description = "l3.sip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
- }
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.sip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.sip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.sip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.sip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
+ /* class_tid: 3, , table: wm.l3_l4.ipv4 */
{
- .field_info_mask = {
- .description = "l3.dip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
- },
- .field_info_spec = {
- .description = "l3.dip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
- }
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.dip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.dip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.dip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.dip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .field_info_mask = {
- .description = "l3.ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 3, , table: wm.l3.ipv4 */
{
- .field_info_mask = {
- .description = "l3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}
- }
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.fid.ipv4",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.fid.ipv4",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.fid.ipv6",
- .field_bit_size = 20,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.fid.ipv6",
- .field_bit_size = 20,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.qos",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.qos",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .field_info_mask = {
- .description = "l3.ieh_nonext",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_nonext",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 3, , table: wm.l2 */
{
- .field_info_mask = {
- .description = "l3.ieh_esp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_esp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_auth",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_auth",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .field_info_mask = {
- .description = "l3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 4, , table: int_full_act_record.0 */
{
- .field_info_mask = {
- .description = "l3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.l3err.ipv4",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.l3err.ipv4",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.l3err.ipv6",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.l3err.ipv6",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
- },
- .field_info_spec = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
- }
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
- },
- .field_info_spec = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
- }
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}
},
{
- .field_info_mask = {
- .description = "l4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.ack",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.ack",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.win",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.win",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.tsval",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.tsval",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
- {
- .field_info_mask = {
- .description = "l4.txecr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.txecr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ /* class_tid: 4, , table: port_table.ing_wr_0 */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "drv_func.mac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: port_table.wr_0 */
{
- .field_info_mask = {
- .description = "dev.port_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "dev.port_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
- }
+ .description = "drv_func.parent.mac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
- }
+ .description = "phy_port",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "default_arec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
/* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
- .field_info_mask = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
},
{
- .field_info_mask = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
{
- .field_info_mask = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
},
{
- .field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
},
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
{
- .field_info_mask = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
{
- .field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
+ /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
{
- .field_info_mask = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
+ /* class_tid: 4, , table: int_full_act_record.egr_0 */
{
- .field_info_mask = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
- }
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- .field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- }
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
- }
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
- }
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
- .field_info_mask = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 4, , table: port_table.egr_wr_0 */
{
- .field_info_mask = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "drv_func.mac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "drv_func.parent.mac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "phy_port",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "default_arec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
+ /* class_tid: 4, , table: ilt_tbl.egr_vfr */
{
- .field_info_mask = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "ilt_destination",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "fwd_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_FWD_OP_BYPASS_LKUP}
},
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
- }
+ .description = "en_ilt_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "en_bd_action",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "en_bd_meta",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "reserved",
+ .field_bit_size = 23,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
{
- .field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .field_info_mask = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- .field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- }
- }
-};
-
-struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
- /* class_tid: 1, , table: l2_cntxt_tcam.0 */
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
.description = "prof_func_id",
.field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
},
@@ -4304,8 +40108,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
.description = "ctxt_opcode",
@@ -4330,10 +40134,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
},
- /* class_tid: 1, , table: mac_addr_cache.wr */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -4347,7 +40151,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_cntxt_tcam_index",
.field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
},
{
.description = "l2_cntxt_id",
@@ -4364,461 +40171,494 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: fkb_select.l3_l4_wm */
+ /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
{
- .description = "l2_cntxt_id.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- 1}
- },
- {
- .description = "parif.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spif.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "svif.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "lcos.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "meta.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "rcyc_cnt.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
+ /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
{
- .description = "loopback.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
+ /* class_tid: 5, , table: int_full_act_record.loopback */
{
- .description = "tl2_l2type.en",
- .field_bit_size = 1,
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_dmac.en",
- .field_bit_size = 1,
+ .description = "encap_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_smac.en",
- .field_bit_size = 1,
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_dt.en",
- .field_bit_size = 1,
+ .description = "rsvd1",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_sa.en",
- .field_bit_size = 1,
+ .description = "rsvd0",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_nvt.en",
- .field_bit_size = 1,
+ .description = "decap_func",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovp.en",
- .field_bit_size = 1,
+ .description = "meter",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovd.en",
+ .description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovv.en",
- .field_bit_size = 1,
+ .description = "stats_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovt.en",
- .field_bit_size = 1,
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff,
+ ULP_THOR_SYM_LOOPBACK_PORT & 0xff}
},
{
- .description = "tl2_ivp.en",
+ .description = "use_default",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivd.en",
- .field_bit_size = 1,
+ .description = "mirror",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivv.en",
+ .description = "cond_copy",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivt.en",
- .field_bit_size = 1,
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_etype.en",
+ .description = "drop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_l3type.en",
+ .description = "hit",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_sip.en",
- .field_bit_size = 1,
+ .description = "type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
{
- .description = "tl3_sip_selcmp.en",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
},
{
- .description = "tl3_dip.en",
- .field_bit_size = 1,
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_dip_selcmp.en",
- .field_bit_size = 1,
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
{
- .description = "tl3_ttl.en",
- .field_bit_size = 1,
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
},
{
- .description = "tl3_prot.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .description = "tl3_fid.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_LOOPBACK_PARIF}
},
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
{
- .description = "tl3_qos.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "tl3_ieh_nonext.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
},
{
- .description = "tl3_ieh_esp.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .description = "tl3_ieh_auth.en",
- .field_bit_size = 1,
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
{
- .description = "tl3_ieh_dest.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
+ /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
{
- .description = "tl3_ieh_frag.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
+ /* class_tid: 5, , table: int_full_act_record.vf_ing */
{
- .description = "tl3_ieh_rthdr.en",
- .field_bit_size = 1,
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_hop.en",
- .field_bit_size = 1,
+ .description = "encap_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_1frag.en",
- .field_bit_size = 1,
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_df.en",
- .field_bit_size = 1,
+ .description = "rsvd1",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_l3err.en",
- .field_bit_size = 1,
+ .description = "rsvd0",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_l4type.en",
- .field_bit_size = 1,
+ .description = "decap_func",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_src.en",
- .field_bit_size = 1,
+ .description = "meter",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_dst.en",
+ .description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_flags.en",
- .field_bit_size = 1,
+ .description = "stats_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_seq.en",
- .field_bit_size = 1,
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}
},
{
- .description = "tl4_pa.en",
+ .description = "use_default",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_opt.en",
- .field_bit_size = 1,
+ .description = "mirror",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_tcpts.en",
+ .description = "cond_copy",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_err.en",
- .field_bit_size = 1,
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tuntype.en",
+ .description = "drop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tflags.en",
+ .description = "hit",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tids.en",
- .field_bit_size = 1,
+ .description = "type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 5, , table: ilt_tbl.vf_ing */
{
- .description = "tid.en",
- .field_bit_size = 1,
+ .description = "ilt_destination",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tctxts.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tctxt.en",
- .field_bit_size = 1,
+ .description = "fwd_op",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_FWD_OP_BYPASS_LKUP}
},
{
- .description = "tqos.en",
+ .description = "en_ilt_dest",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "terr.en",
+ .description = "en_bd_action",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_l2type.en",
+ .description = "en_bd_meta",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_dmac.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_smac.en",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 23,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: ilt_tbl.vfr_egr */
{
- .description = "l2_dt.en",
- .field_bit_size = 1,
+ .description = "ilt_destination",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_sa.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_nvt.en",
- .field_bit_size = 1,
+ .description = "fwd_op",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_FWD_OP_BYPASS_LKUP}
},
{
- .description = "l2_ovp.en",
+ .description = "en_ilt_dest",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovd.en",
+ .description = "en_bd_action",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "l2_ovv.en",
+ .description = "en_bd_meta",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovt.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivp.en",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 23,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
{
- .description = "l2_ivd.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "l2_ivv.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivt.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_etype.en",
- .field_bit_size = 1,
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: metadata_record.vfr_egr */
{
- .description = "l3_l3type.en",
- .field_bit_size = 1,
+ .description = "prof_meta_mask",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
+ /* class_tid: 5, , table: mod_record.vfr_egr */
{
- .description = "l3_sip.en",
+ .description = "metadata_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -4826,1078 +40666,1113 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
1}
},
{
- .description = "l3_sip_selcmp.en",
+ .description = "rem_ovlan",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- {
- .description = "l3_dip_selcmp.en",
+ .description = "rem_ivlan",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ttl.en",
+ .description = "rep_add_ivlan",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_prot.en",
+ .description = "rep_add_ovlan",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_fid.en",
+ .description = "ttl_update",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_qos.en",
+ .description = "tun_md_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_nonext.en",
+ .description = "reserved_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_esp.en",
+ .description = "l2_dmac_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_auth.en",
+ .description = "l2_smac_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_dest.en",
+ .description = "l3_sip_ipv6_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_frag.en",
+ .description = "l3_dip_ipv6_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_rthdr.en",
+ .description = "l3_sip_ipv4_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_hop.en",
+ .description = "l3_dip_ipv4_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_1frag.en",
+ .description = "l4_sport_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_df.en",
+ .description = "l4_dport_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_l3err.en",
- .field_bit_size = 1,
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_l4type.en",
- .field_bit_size = 1,
+ .description = "metadata_op",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_src.en",
- .field_bit_size = 1,
+ .description = "metadata_prof",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0 & 0xff}
},
{
- .description = "l4_dst.en",
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_flags.en",
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_seq.en",
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_dec",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_ack.en",
+ .description = "ttl_il3_dec",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_win.en",
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_rdir",
.field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ /* class_tid: 5, , table: int_full_act_record.vfr_egr */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_pa.en",
- .field_bit_size = 1,
+ .description = "encap_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_opt.en",
- .field_bit_size = 1,
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_tcpts.en",
- .field_bit_size = 1,
+ .description = "rsvd0",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_tsval.en",
- .field_bit_size = 1,
+ .description = "decap_func",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_txecr.en",
- .field_bit_size = 1,
+ .description = "meter",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_err.en",
+ .description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam.l3_l4 */
{
- .description = "wc_key_id",
- .field_bit_size = 6,
+ .description = "stats_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff,
+ ULP_THOR_SYM_LOOPBACK_PORT & 0xff}
},
{
- .description = "wc_search_en",
+ .description = "use_default",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_type",
- .field_bit_size = 2,
+ .description = "mirror",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 6,
+ .description = "cond_copy",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_search_en",
+ .description = "drop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "pl_byp_lkup_en",
+ .description = "hit",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam_cache.l3_l4_wr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ 1}
},
+ /* class_tid: 5, , table: l2_cntxt_tcam.vfr_ing0 */
{
- .description = "profile_tcam_index",
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 & 0xff}
+ },
+ {
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ },
+ {
+ .description = "l2_cntxt_id",
.field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
+ },
+ /* class_tid: 5, , table: fkb_select.vfr_em */
+ {
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 8,
+ .description = "parif.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "spif.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_key_id",
- .field_bit_size = 8,
+ .description = "svif.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "flow_sig_id",
- .field_bit_size = 64,
+ .description = "lcos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l3_l4 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "meta.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "loopback.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: int_full_act_record.0 */
{
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "encap_ptr",
- .field_bit_size = 16,
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd1",
- .field_bit_size = 16,
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd0",
- .field_bit_size = 8,
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "decap_func",
- .field_bit_size = 5,
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meter",
- .field_bit_size = 10,
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_op",
+ .description = "tl2_ovt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_ptr",
- .field_bit_size = 16,
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 11,
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "use_default",
+ .description = "tl2_ivv.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mirror",
- .field_bit_size = 4,
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "cond_copy",
+ .description = "tl2_etype.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drop",
+ .description = "tl3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "hit",
+ .description = "tl3_sip_selcmp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "type",
- .field_bit_size = 3,
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: port_table.wr_0 */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drv_func.mac",
- .field_bit_size = 48,
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drv_func.parent.mac",
- .field_bit_size = 48,
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "phy_port",
- .field_bit_size = 8,
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "default_arec_ptr",
- .field_bit_size = 16,
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_tcam_index",
- .field_bit_size = 10,
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: int_full_act_record.egr_0 */
{
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "encap_ptr",
- .field_bit_size = 16,
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd1",
- .field_bit_size = 16,
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd0",
- .field_bit_size = 8,
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "decap_func",
- .field_bit_size = 5,
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meter",
- .field_bit_size = 10,
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_op",
+ .description = "tuntype.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_ptr",
- .field_bit_size = 16,
+ .description = "tflags.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 11,
+ .description = "tids.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "use_default",
+ .description = "tid.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mirror",
- .field_bit_size = 4,
+ .description = "tctxts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "cond_copy",
+ .description = "tctxt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
+ .description = "tqos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drop",
+ .description = "terr.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "hit",
+ .description = "l2_l2type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "type",
- .field_bit_size = 3,
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: int_full_act_record.loopback */
{
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "encap_ptr",
- .field_bit_size = 16,
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd1",
- .field_bit_size = 16,
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd0",
- .field_bit_size = 8,
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "decap_func",
- .field_bit_size = 5,
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meter",
- .field_bit_size = 10,
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_op",
+ .description = "l3_sip_selcmp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_ptr",
- .field_bit_size = 16,
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 11,
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff,
- ULP_THOR_SYM_LOOPBACK_PORT & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "use_default",
+ .description = "l3_ttl.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mirror",
- .field_bit_size = 4,
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "cond_copy",
+ .description = "l3_fid.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drop",
+ .description = "l3_ieh_nonext.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "hit",
+ .description = "l3_ieh_esp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "type",
- .field_bit_size = 3,
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: int_full_act_record.vf_ing */
{
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "encap_ptr",
- .field_bit_size = 16,
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd1",
- .field_bit_size = 16,
+ .description = "l3_df.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd0",
- .field_bit_size = 8,
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "decap_func",
- .field_bit_size = 5,
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meter",
- .field_bit_size = 10,
+ .description = "l4_src.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_op",
+ .description = "l4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_ptr",
- .field_bit_size = 16,
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 11,
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "use_default",
+ .description = "l4_ack.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mirror",
- .field_bit_size = 4,
+ .description = "l4_win.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "cond_copy",
+ .description = "l4_pa.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drop",
+ .description = "l4_tcpts.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "hit",
+ .description = "l4_tsval.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "type",
- .field_bit_size = 3,
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: vtag_encap_record.vfr_egr0 */
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "l4_err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: profile_tcam.vfr_ing0 */
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "wc_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l2_en",
+ .description = "wc_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
- },
- {
- .description = "rsrvd",
- .field_bit_size = 1,
+ .description = "em_key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "em_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 & 0xff}
},
{
- .description = "vtag_tpid",
- .field_bit_size = 16,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- 0x81,
- 0x00}
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 & 0xff}
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "em_search_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ 1}
},
{
- .description = "vtag_de",
+ .description = "pl_byp_lkup_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- {
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
- },
- /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
+ /* class_tid: 5, , table: int_full_act_record.vfr_ing0 */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -5908,10 +41783,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "encap_ptr",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "mod_rec_ptr",
@@ -5959,10 +41831,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "vnic_or_vport",
.field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff,
- ULP_THOR_SYM_LOOPBACK_PORT & 0xff}
+ (BNXT_ULP_CF_IDX_VF_FUNC_VNIC >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_VNIC & 0xff}
},
{
.description = "use_default",
@@ -6007,6 +41879,50 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
+ },
+ /* class_tid: 5, , table: em.vfr.0 */
+ {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
};
@@ -6053,6 +41969,203 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 29
},
+ /* class_tid: 1, , table: profile_tcam_cache.ipv6_rd */
+ {
+ .description = "em_key_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_KEY_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 50
+ },
+ {
+ .description = "em_profile_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 42
+ },
+ {
+ .description = "flow_sig_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .ident_bit_size = 64,
+ .ident_bit_pos = 74
+ },
+ {
+ .description = "profile_tcam_index",
+ .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
+ },
+ /* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */
+ {
+ .description = "em_profile_id",
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_EM_PROF,
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 23
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.rd */
+ {
+ .description = "flow_sig_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .ident_bit_size = 64,
+ .ident_bit_pos = 74
+ },
+ {
+ .description = "profile_tcam_index",
+ .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
+ },
+ /* class_tid: 2, , table: port_table.rd */
+ {
+ .description = "default_arec_ptr",
+ .regfile_idx = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
+ .ident_bit_size = 16,
+ .ident_bit_pos = 136
+ },
+ {
+ .description = "drv_func.parent.mac",
+ .regfile_idx = BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC,
+ .ident_bit_size = 48,
+ .ident_bit_pos = 80
+ },
+ {
+ .description = "phy_port",
+ .regfile_idx = BNXT_ULP_RF_IDX_PHY_PORT,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 128
+ },
+ /* class_tid: 2, , table: tunnel_cache.rd */
+ {
+ .description = "l2_cntxt_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 42
+ },
+ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
+ {
+ .description = "l2_cntxt_id",
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 29
+ },
+ /* class_tid: 2, , table: mac_addr_cache.rd */
+ {
+ .description = "l2_cntxt_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 42
+ },
+ /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
+ {
+ .description = "em_profile_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 42
+ },
+ {
+ .description = "flow_sig_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .ident_bit_size = 64,
+ .ident_bit_pos = 74
+ },
+ {
+ .description = "profile_tcam_index",
+ .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ {
+ .description = "l2_cntxt_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 42
+ },
+ /* class_tid: 3, , table: mac_addr_cache.rd */
+ {
+ .description = "l2_cntxt_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 42
+ },
+ /* class_tid: 3, , table: port_table.egr.rd */
+ {
+ .description = "default_arec_ptr",
+ .regfile_idx = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
+ .ident_bit_size = 16,
+ .ident_bit_pos = 136
+ },
+ {
+ .description = "drv_func.parent.mac",
+ .regfile_idx = BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC,
+ .ident_bit_size = 48,
+ .ident_bit_pos = 80
+ },
+ {
+ .description = "phy_port",
+ .regfile_idx = BNXT_ULP_RF_IDX_PHY_PORT,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 128
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam.0 */
+ {
+ .description = "l2_cntxt_id",
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 29
+ },
+ /* class_tid: 3, , table: profile_tcam_cache.ipv6_rd */
+ {
+ .description = "em_key_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_KEY_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 50
+ },
+ {
+ .description = "em_profile_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 42
+ },
+ {
+ .description = "flow_sig_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .ident_bit_size = 64,
+ .ident_bit_pos = 74
+ },
+ {
+ .description = "profile_tcam_index",
+ .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
+ },
+ /* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */
+ {
+ .description = "em_profile_id",
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_EM_PROF,
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 23
+ },
+ /* class_tid: 3, , table: profile_tcam_cache.rd */
+ {
+ .description = "flow_sig_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .ident_bit_size = 64,
+ .ident_bit_pos = 74
+ },
+ {
+ .description = "profile_tcam_index",
+ .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
+ },
/* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
.description = "l2_cntxt_id",
@@ -6070,5 +42183,21 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 29
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
+ {
+ .description = "l2_cntxt_id",
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 29
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_wr_vfr */
+ {
+ .description = "rid",
+ .regfile_idx = BNXT_ULP_RF_IDX_RID,
+ .ident_bit_size = 32,
+ .ident_bit_pos = 0
}
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
index 7203dcf1fb..2870a0615a 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Fri May 28 16:46:46 2021 */
+/* date: Wed Jun 30 14:36:16 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -1488,7 +1488,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 47,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE,
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index bcc089b3e1..234f7ea2fa 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -2212,6 +2212,7 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
int32_t trc;
int32_t rc = 0;
int32_t pad = 0;
+ enum bnxt_ulp_byte_order key_order, res_order;
tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session);
rc = bnxt_ulp_cntxt_mem_type_get(parms->ulp_ctx, &mtype);
@@ -2226,11 +2227,12 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
+ key_order = dparms->em_byte_order;
+ res_order = dparms->em_byte_order;
+
/* Initialize the key/result blobs */
- if (!ulp_blob_init(&key, tbl->blob_key_bit_size,
- dparms->key_byte_order) ||
- !ulp_blob_init(&data, tbl->result_bit_size,
- dparms->result_byte_order)) {
+ if (!ulp_blob_init(&key, tbl->blob_key_bit_size, key_order) ||
+ !ulp_blob_init(&data, tbl->result_bit_size, res_order)) {
BNXT_TF_DBG(ERR, "blob inits failed.\n");
return -EINVAL;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index 4e9968e5fa..dce95de05c 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -826,12 +826,12 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
*/
ulp_rte_prsr_fld_mask(params, &idx, size,
&priority,
- &priority_mask,
+ (vlan_mask) ? &priority_mask : NULL,
ULP_PRSR_ACT_MASK_IGNORE);
ulp_rte_prsr_fld_mask(params, &idx, size,
&vlan_tag,
- &vlan_tag_mask,
+ (vlan_mask) ? &vlan_tag_mask : NULL,
ULP_PRSR_ACT_DEFAULT);
size = sizeof(((struct rte_flow_item_vlan *)NULL)->inner_type);
@@ -859,6 +859,10 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_ONE_VTAG, 1);
ULP_BITMAP_SET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_OO_VLAN);
+ if (vlan_mask && vlan_tag_mask)
+ ULP_COMP_FLD_IDX_WR(params,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID, 1);
+
} else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) &&
!ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_I_ETH) &&
outer_vtag_num == 1) {
@@ -870,6 +874,10 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_ONE_VTAG, 0);
ULP_BITMAP_SET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_OI_VLAN);
+ if (vlan_mask && vlan_tag_mask)
+ ULP_COMP_FLD_IDX_WR(params,
+ BNXT_ULP_CF_IDX_OI_VLAN_FB_VID, 1);
+
} else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) &&
ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_I_ETH) &&
!inner_vtag_num) {
@@ -881,6 +889,9 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_ONE_VTAG, 1);
ULP_BITMAP_SET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_IO_VLAN);
+ if (vlan_mask && vlan_tag_mask)
+ ULP_COMP_FLD_IDX_WR(params,
+ BNXT_ULP_CF_IDX_IO_VLAN_FB_VID, 1);
inner_flag = 1;
} else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) &&
ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_I_ETH) &&
@@ -893,6 +904,9 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_ONE_VTAG, 0);
ULP_BITMAP_SET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_II_VLAN);
+ if (vlan_mask && vlan_tag_mask)
+ ULP_COMP_FLD_IDX_WR(params,
+ BNXT_ULP_CF_IDX_II_VLAN_FB_VID, 1);
inner_flag = 1;
} else {
BNXT_TF_DBG(ERR, "Error Parsing:Vlan hdr found without eth\n");
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index e2a4b81cec..1683cd7ec4 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -213,6 +213,7 @@ struct bnxt_ulp_device_params {
enum bnxt_ulp_byte_order result_byte_order;
enum bnxt_ulp_byte_order encap_byte_order;
enum bnxt_ulp_byte_order wc_key_byte_order;
+ enum bnxt_ulp_byte_order em_byte_order;
uint8_t encap_byte_swap;
uint8_t num_phy_ports;
uint32_t mark_db_lfid_entries;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c
index fc4f435c97..686b80e456 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c
@@ -964,8 +964,11 @@ ulp_blob_append(struct ulp_blob *dst, struct ulp_blob *src,
ulp_bs_put_msb(dst->data, dst->write_idx,
ULP_BLOB_BYTE, bluff);
dst->write_idx += remaining;
+ src_offset += remaining;
}
+ src_buf += ULP_BITS_2_BYTE_NR(src_offset);
+
/* Push the byte aligned pieces */
for (k = 0; k < ULP_BITS_2_BYTE_NR(src_len); k++) {
ulp_bs_put_msb(dst->data, dst->write_idx, ULP_BLOB_BYTE,
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v2 10/13] net/bnxt: tf core SRAM Manager
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 00/13] enhancements to host based flow table management Venkat Duvvuru
` (8 preceding siblings ...)
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 09/13] net/bnxt: add flow templates " Venkat Duvvuru
@ 2021-09-08 5:06 ` Venkat Duvvuru
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 11/13] net/bnxt: dynamically allocate space for EM defrag function Venkat Duvvuru
` (4 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-08 5:06 UTC (permalink / raw)
To: dev; +Cc: Farah Smith
From: Farah Smith <farah.smith@broadcom.com>
Adjust info message to debug level to prevent excessive
logging.
Signed-off-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
---
drivers/net/bnxt/tf_core/tf_tbl_sram.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.c b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
index ea10afecb6..d7727f7a11 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl_sram.c
+++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
@@ -130,7 +130,7 @@ static int tf_tbl_sram_get_info(struct tf_tbl_sram_get_info_parms *parms)
if (slices)
parms->slice_size = tf_tbl_sram_slices_2_size[slices];
- TFP_DRV_LOG(INFO,
+ TFP_DRV_LOG(DEBUG,
"(%s) bank(%s) slice_size(%s)\n",
tf_tbl_type_2_str(parms->tbl_type),
tf_sram_bank_2_str(parms->bank_id),
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v2 11/13] net/bnxt: dynamically allocate space for EM defrag function
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 00/13] enhancements to host based flow table management Venkat Duvvuru
` (9 preceding siblings ...)
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 10/13] net/bnxt: tf core SRAM Manager Venkat Duvvuru
@ 2021-09-08 5:06 ` Venkat Duvvuru
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 12/13] net/bnxt: sram manager shared session Venkat Duvvuru
` (3 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-08 5:06 UTC (permalink / raw)
To: dev; +Cc: Randy Schacher
From: Randy Schacher <stuart.schacher@broadcom.com>
Alter defrag function to dynamically allocate and delete
free_list and adj_list buffers.
Signed-off-by: Randy Schacher <stuart.schacher@broadcom.com>
Reviewed-by: Peter Spreadborough <peter.spreadborough@broadcom.com>
---
drivers/net/bnxt/tf_core/dpool.c | 38 +++++++++++++++++++++-----------
1 file changed, 25 insertions(+), 13 deletions(-)
diff --git a/drivers/net/bnxt/tf_core/dpool.c b/drivers/net/bnxt/tf_core/dpool.c
index 145efa486f..5c03f775a5 100644
--- a/drivers/net/bnxt/tf_core/dpool.c
+++ b/drivers/net/bnxt/tf_core/dpool.c
@@ -7,9 +7,6 @@
#include <stdbool.h>
#include <stdint.h>
#include <errno.h>
-
-#include <rte_malloc.h>
-
#include "tfp.h"
#include "dpool.h"
@@ -84,13 +81,13 @@ static int dpool_move(struct dpool *dpool,
return 0;
}
-
int dpool_defrag(struct dpool *dpool,
uint32_t entry_size,
uint8_t defrag)
{
struct dpool_free_list *free_list;
struct dpool_adj_list *adj_list;
+ struct tfp_calloc_parms parms;
uint32_t count;
uint32_t index;
uint32_t used;
@@ -103,15 +100,31 @@ int dpool_defrag(struct dpool *dpool,
uint32_t max_size = 0;
int rc;
- free_list = rte_zmalloc("dpool_free_list",
- sizeof(struct dpool_free_list), 0);
+ parms.nitems = 1;
+ parms.size = sizeof(struct dpool_free_list);
+ parms.alignment = 0;
+
+ rc = tfp_calloc(&parms);
+
+ if (rc)
+ return rc;
+
+ free_list = (struct dpool_free_list *)parms.mem_va;
if (free_list == NULL) {
TFP_DRV_LOG(ERR, "dpool free list allocation failed\n");
return -ENOMEM;
}
- adj_list = rte_zmalloc("dpool_adjacent_list",
- sizeof(struct dpool_adj_list), 0);
+ parms.nitems = 1;
+ parms.size = sizeof(struct dpool_adj_list);
+ parms.alignment = 0;
+
+ rc = tfp_calloc(&parms);
+
+ if (rc)
+ return rc;
+
+ adj_list = (struct dpool_adj_list *)parms.mem_va;
if (adj_list == NULL) {
TFP_DRV_LOG(ERR, "dpool adjacent list allocation failed\n");
return -ENOMEM;
@@ -239,8 +252,8 @@ int dpool_defrag(struct dpool *dpool,
free_list->entry[largest_free_index].index,
max_index);
if (rc) {
- rte_free(free_list);
- rte_free(adj_list);
+ tfp_free(free_list);
+ tfp_free(adj_list);
return rc;
}
} else {
@@ -249,12 +262,11 @@ int dpool_defrag(struct dpool *dpool,
}
done:
- rte_free(free_list);
- rte_free(adj_list);
+ tfp_free(free_list);
+ tfp_free(adj_list);
return largest_free_size;
}
-
uint32_t dpool_alloc(struct dpool *dpool,
uint32_t size,
uint8_t defrag)
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v2 12/13] net/bnxt: sram manager shared session
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 00/13] enhancements to host based flow table management Venkat Duvvuru
` (10 preceding siblings ...)
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 11/13] net/bnxt: dynamically allocate space for EM defrag function Venkat Duvvuru
@ 2021-09-08 5:06 ` Venkat Duvvuru
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 13/13] net/bnxt: add enhancements to TF ULP Venkat Duvvuru
` (2 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-08 5:06 UTC (permalink / raw)
To: dev; +Cc: Farah Smith
From: Farah Smith <farah.smith@broadcom.com>
Fix shared session support issues due to SRAM manager
additions. Shared session does not support slices within
RM blocks. Calculate resources required without slices
and determine base addresses using old methods for the
shared session.
Signed-off-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com>
---
drivers/net/bnxt/tf_core/tf_em_internal.c | 5 +-
drivers/net/bnxt/tf_core/tf_rm.c | 134 +++++++++++++++++++---
drivers/net/bnxt/tf_core/tf_tbl_sram.c | 73 +++++++++---
3 files changed, 176 insertions(+), 36 deletions(-)
diff --git a/drivers/net/bnxt/tf_core/tf_em_internal.c b/drivers/net/bnxt/tf_core/tf_em_internal.c
index 2d57595f17..67ba011eae 100644
--- a/drivers/net/bnxt/tf_core/tf_em_internal.c
+++ b/drivers/net/bnxt/tf_core/tf_em_internal.c
@@ -326,8 +326,11 @@ tf_em_int_unbind(struct tf *tfp)
return rc;
if (!tf_session_is_shared_session(tfs)) {
- for (i = 0; i < TF_DIR_MAX; i++)
+ for (i = 0; i < TF_DIR_MAX; i++) {
+ if (tfs->em_pool[i] == NULL)
+ continue;
dpool_free_all(tfs->em_pool[i]);
+ }
}
rc = tf_session_get_db(tfp, TF_MODULE_TYPE_EM, &em_db_ptr);
diff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c
index 03c958a7d6..dd537aaece 100644
--- a/drivers/net/bnxt/tf_core/tf_rm.c
+++ b/drivers/net/bnxt/tf_core/tf_rm.c
@@ -18,6 +18,9 @@
#include "tfp.h"
#include "tf_msg.h"
+/* Logging defines */
+#define TF_RM_DEBUG 0
+
/**
* Generic RM Element data type that an RM DB is build upon.
*/
@@ -207,6 +210,45 @@ tf_rm_adjust_index(struct tf_rm_element *db,
return rc;
}
+/**
+ * Logs an array of found residual entries to the console.
+ *
+ * [in] dir
+ * Receive or transmit direction
+ *
+ * [in] module
+ * Type of Device Module
+ *
+ * [in] count
+ * Number of entries in the residual array
+ *
+ * [in] residuals
+ * Pointer to an array of residual entries. Array is index same as
+ * the DB in which this function is used. Each entry holds residual
+ * value for that entry.
+ */
+#if (TF_RM_DEBUG == 1)
+static void
+tf_rm_log_residuals(enum tf_dir dir,
+ enum tf_module_type module,
+ uint16_t count,
+ uint16_t *residuals)
+{
+ int i;
+
+ /* Walk the residual array and log the types that wasn't
+ * cleaned up to the console.
+ */
+ for (i = 0; i < count; i++) {
+ if (residuals[i] != 0)
+ TFP_DRV_LOG(INFO,
+ "%s, %s was not cleaned up, %d outstanding\n",
+ tf_dir_2_str(dir),
+ tf_module_subtype_2_str(module, i),
+ residuals[i]);
+ }
+}
+#endif /* TF_RM_DEBUG == 1 */
/**
* Performs a check of the passed in DB for any lingering elements. If
* a resource type was found to not have been cleaned up by the caller
@@ -322,6 +364,12 @@ tf_rm_check_residuals(struct tf_rm_new_db *rm_db,
*resv_size = found;
}
+#if (TF_RM_DEBUG == 1)
+ tf_rm_log_residuals(rm_db->dir,
+ rm_db->module,
+ rm_db->num_entries,
+ residuals);
+#endif
tfp_free((void *)residuals);
*resv = local_resv;
@@ -367,7 +415,8 @@ tf_rm_update_parent_reservations(struct tf *tfp,
struct tf_rm_element_cfg *cfg,
uint16_t *alloc_cnt,
uint16_t num_elements,
- uint16_t *req_cnt)
+ uint16_t *req_cnt,
+ bool shared_session)
{
int parent, child;
const char *type_str;
@@ -378,18 +427,28 @@ tf_rm_update_parent_reservations(struct tf *tfp,
/* If I am a parent */
if (cfg[parent].cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_PARENT) {
- /* start with my own count */
- RTE_ASSERT(cfg[parent].slices);
- combined_cnt =
- alloc_cnt[parent] / cfg[parent].slices;
+ uint8_t p_slices = 1;
+
+ /* Shared session doesn't support slices */
+ if (!shared_session)
+ p_slices = cfg[parent].slices;
+
+ RTE_ASSERT(p_slices);
- if (alloc_cnt[parent] % cfg[parent].slices)
+ combined_cnt = alloc_cnt[parent] / p_slices;
+
+ if (alloc_cnt[parent] % p_slices)
combined_cnt++;
if (alloc_cnt[parent]) {
dev->ops->tf_dev_get_resource_str(tfp,
cfg[parent].hcapi_type,
&type_str);
+#if (TF_RM_DEBUG == 1)
+ printf("%s:%s cnt(%d) slices(%d)\n",
+ type_str, tf_tbl_type_2_str(parent),
+ alloc_cnt[parent], p_slices);
+#endif /* (TF_RM_DEBUG == 1) */
}
/* Search again through all the elements */
@@ -399,20 +458,31 @@ tf_rm_update_parent_reservations(struct tf *tfp,
TF_RM_ELEM_CFG_HCAPI_BA_CHILD &&
cfg[child].parent_subtype == parent &&
alloc_cnt[child]) {
+ uint8_t c_slices = 1;
uint16_t cnt = 0;
- RTE_ASSERT(cfg[child].slices);
+
+ if (!shared_session)
+ c_slices = cfg[child].slices;
+
+ RTE_ASSERT(c_slices);
dev->ops->tf_dev_get_resource_str(tfp,
cfg[child].hcapi_type,
&type_str);
+#if (TF_RM_DEBUG == 1)
+ printf("%s:%s cnt(%d) slices(%d)\n",
+ type_str,
+ tf_tbl_type_2_str(child),
+ alloc_cnt[child],
+ c_slices);
+#endif /* (TF_RM_DEBUG == 1) */
/* Increment the parents combined count
* with each child's count adjusted for
- * number of slices per RM allocated item.
+ * number of slices per RM alloc item.
*/
- cnt =
- alloc_cnt[child] / cfg[child].slices;
+ cnt = alloc_cnt[child] / c_slices;
- if (alloc_cnt[child] % cfg[child].slices)
+ if (alloc_cnt[child] % c_slices)
cnt++;
combined_cnt += cnt;
@@ -422,6 +492,10 @@ tf_rm_update_parent_reservations(struct tf *tfp,
}
/* Save the parent count to be requested */
req_cnt[parent] = combined_cnt;
+#if (TF_RM_DEBUG == 1)
+ printf("%s calculated total:%d\n\n",
+ type_str, req_cnt[parent]);
+#endif /* (TF_RM_DEBUG == 1) */
}
}
return 0;
@@ -444,6 +518,7 @@ tf_rm_create_db(struct tf *tfp,
struct tf_rm_new_db *rm_db;
struct tf_rm_element *db;
uint32_t pool_size;
+ bool shared_session = 0;
TF_CHECK_PARMS2(tfp, parms);
@@ -460,7 +535,6 @@ tf_rm_create_db(struct tf *tfp,
/* Need device max number of elements for the RM QCAPS */
rc = dev->ops->tf_dev_get_max_types(tfp, &max_types);
-
/* Allocate memory for RM QCAPS request */
cparms.nitems = max_types;
cparms.size = sizeof(struct tf_rm_resc_req_entry);
@@ -496,12 +570,15 @@ tf_rm_create_db(struct tf *tfp,
tfp_memcpy(req_cnt, parms->alloc_cnt,
parms->num_elements * sizeof(uint16_t));
+ shared_session = tf_session_is_shared_session(tfs);
+
/* Update the req_cnt based upon the element configuration
*/
tf_rm_update_parent_reservations(tfp, dev, parms->cfg,
parms->alloc_cnt,
parms->num_elements,
- req_cnt);
+ req_cnt,
+ shared_session);
/* Process capabilities against DB requirements. However, as a
* DB can hold elements that are not HCAPI we can reduce the
@@ -517,6 +594,12 @@ tf_rm_create_db(struct tf *tfp,
&hcapi_items);
if (hcapi_items == 0) {
+#if (TF_RM_DEBUG == 1)
+ TFP_DRV_LOG(INFO,
+ "%s: module: %s Empty RM DB create request\n",
+ tf_dir_2_str(parms->dir),
+ tf_module_2_str(parms->module));
+#endif
parms->rm_db = NULL;
return -ENOMEM;
}
@@ -565,11 +648,11 @@ tf_rm_create_db(struct tf *tfp,
hcapi_type,
&type_str);
TFP_DRV_LOG(ERR,
- "Failure, %s:%d:%s req:%d avail:%d\n",
- tf_dir_2_str(parms->dir),
- hcapi_type, type_str,
- req_cnt[i],
- query[hcapi_type].max);
+ "Failure, %s:%d:%s req:%d avail:%d\n",
+ tf_dir_2_str(parms->dir),
+ hcapi_type, type_str,
+ req_cnt[i],
+ query[hcapi_type].max);
return -EINVAL;
}
}
@@ -689,6 +772,13 @@ tf_rm_create_db(struct tf *tfp,
rm_db->module = parms->module;
*parms->rm_db = (void *)rm_db;
+#if (TF_RM_DEBUG == 1)
+
+ printf("%s: module:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_module_2_str(parms->module));
+#endif /* (TF_RM_DEBUG == 1) */
+
tfp_free((void *)req);
tfp_free((void *)resv);
tfp_free((void *)req_cnt);
@@ -922,6 +1012,13 @@ tf_rm_create_db_no_reservation(struct tf *tfp,
rm_db->module = parms->module;
*parms->rm_db = (void *)rm_db;
+#if (TF_RM_DEBUG == 1)
+
+ printf("%s: module:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_module_2_str(parms->module));
+#endif /* (TF_RM_DEBUG == 1) */
+
tfp_free((void *)req);
tfp_free((void *)resv);
tfp_free((void *)req_cnt);
@@ -1185,7 +1282,6 @@ tf_rm_is_allocated(struct tf_rm_is_allocated_parms *parms)
cfg_type = rm_db->db[parms->subtype].cfg_type;
-
/* Bail out if not controlled by RM */
if (cfg_type != TF_RM_ELEM_CFG_HCAPI_BA &&
cfg_type != TF_RM_ELEM_CFG_HCAPI_BA_PARENT &&
diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.c b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
index d7727f7a11..167078a8c6 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl_sram.c
+++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
@@ -21,6 +21,10 @@
#define DBG_SRAM 0
+#define TF_TBL_PTR_TO_RM(new_idx, idx, base, shift) { \
+ *(new_idx) = (((idx) >> (shift)) - (base)); \
+}
+
/**
* tf_sram_tbl_get_info_parms parameter definition
*/
@@ -394,6 +398,7 @@ tf_tbl_sram_set(struct tf *tfp,
{
int rc;
bool allocated = 0;
+ int rallocated = 0;
uint16_t hcapi_type;
struct tf_rm_get_hcapi_parms hparms = { 0 };
struct tf_session *tfs;
@@ -402,7 +407,9 @@ tf_tbl_sram_set(struct tf *tfp,
void *tbl_db_ptr = NULL;
struct tf_tbl_sram_get_info_parms iparms = { 0 };
struct tf_sram_mgr_is_allocated_parms aparms = { 0 };
+ struct tf_rm_is_allocated_parms raparms = { 0 };
void *sram_handle = NULL;
+ uint16_t base = 0, shift = 0;
TF_CHECK_PARMS3(tfp, parms, parms->data);
@@ -442,23 +449,57 @@ tf_tbl_sram_set(struct tf *tfp,
return rc;
}
- aparms.sram_offset = parms->idx;
- aparms.slice_size = iparms.slice_size;
- aparms.bank_id = iparms.bank_id;
- aparms.dir = parms->dir;
- aparms.is_allocated = &allocated;
- rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
- if (rc || !allocated) {
- TFP_DRV_LOG(ERR,
- "%s: Entry not allocated:%s idx(%d):(%s)\n",
- tf_dir_2_str(parms->dir),
- tf_tbl_type_2_str(parms->type),
- parms->idx,
- strerror(-rc));
- rc = -ENOMEM;
- return rc;
+ if (tf_session_is_shared_session(tfs)) {
+ /* Only get table info if required for the device */
+ if (dev->ops->tf_dev_get_tbl_info) {
+ rc = dev->ops->tf_dev_get_tbl_info(tfp,
+ tbl_db->tbl_db[parms->dir],
+ parms->type,
+ &base,
+ &shift);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get table info:%d\n",
+ tf_dir_2_str(parms->dir),
+ parms->type);
+ return rc;
+ }
+ }
+ TF_TBL_PTR_TO_RM(&raparms.index, parms->idx, base, shift);
+
+ raparms.rm_db = tbl_db->tbl_db[parms->dir];
+ raparms.subtype = parms->type;
+ raparms.allocated = &rallocated;
+ rc = tf_rm_is_allocated(&raparms);
+ if (rc)
+ return rc;
+
+ if (rallocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
+ TFP_DRV_LOG(ERR,
+ "%s, Invalid or not allocated index, type:%s, idx:%d\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->idx);
+ return -EINVAL;
+ }
+ } else {
+ aparms.sram_offset = parms->idx;
+ aparms.slice_size = iparms.slice_size;
+ aparms.bank_id = iparms.bank_id;
+ aparms.dir = parms->dir;
+ aparms.is_allocated = &allocated;
+ rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
+ if (rc || !allocated) {
+ TFP_DRV_LOG(ERR,
+ "%s: Entry not allocated:%s idx(%d):(%s)\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->idx,
+ strerror(-rc));
+ rc = -ENOMEM;
+ return rc;
+ }
}
-
/* Set the entry */
hparms.rm_db = tbl_db->tbl_db[parms->dir];
hparms.subtype = parms->type;
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v2 13/13] net/bnxt: add enhancements to TF ULP
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 00/13] enhancements to host based flow table management Venkat Duvvuru
` (11 preceding siblings ...)
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 12/13] net/bnxt: sram manager shared session Venkat Duvvuru
@ 2021-09-08 5:06 ` Venkat Duvvuru
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 00/13] enhancements to host based flow table management Venkat Duvvuru
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 " Venkat Duvvuru
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-08 5:06 UTC (permalink / raw)
To: dev; +Cc: Kishore Padmanabha, Mike Baucom, Venkat Duvvuru
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
1. Added support to specify l4 port masks in the template. Also enabled
source mac in the wild card key for ingress flows.
2. Added support to enable offload for ipv6 traffic within the vxlan
tunnel connection.
3. The flow counters is reduced from 7168 to 6912 for Whitney.
The stats operation is updated to reflect counts for packets
at egress from CFA instead of ingress to CFA
4. The miss path for the l2 context table is updated with correct
parif and default action handler to handle the miss path for
egress flows.
5. This support enables allocation of encapsulation, modification and
action records dynamically based on a given flow actions.
6. Reduce the l2context resource requests during open_session. Move the
SMAC from the L2Context to the EM/WM
7. Remap the parif in the bd action in order to eliminate incorrect
replication of broadcast packets. The layer 4 source port mask
was incorrectly updated in the outer layer 4 source port mask
instead of inner layer 4. Add the l3 proto to egress rules, switch
to using computed fields for l4 ports, add internal smac to f1/f2
flows, add l3 proto to ingress ipv6 flows
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Mike Baucom <michael.baucom@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
---
drivers/net/bnxt/tf_core/tf_tbl_sram.c | 7 -
.../generic_templates/ulp_template_db_class.c | 8102 ++++++++++++-----
.../generic_templates/ulp_template_db_enum.h | 675 +-
.../generic_templates/ulp_template_db_field.h | 195 +-
.../generic_templates/ulp_template_db_tbl.c | 2136 ++++-
.../ulp_template_db_thor_act.c | 996 +-
.../ulp_template_db_thor_class.c | 7495 ++++++++-------
.../ulp_template_db_wh_plus_class.c | 14 +-
drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c | 4 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 135 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 175 +-
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 10 +
drivers/net/bnxt/tf_ulp/ulp_utils.c | 3 +-
13 files changed, 13538 insertions(+), 6409 deletions(-)
diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.c b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
index 167078a8c6..636811bc2d 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl_sram.c
+++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
@@ -134,11 +134,6 @@ static int tf_tbl_sram_get_info(struct tf_tbl_sram_get_info_parms *parms)
if (slices)
parms->slice_size = tf_tbl_sram_slices_2_size[slices];
- TFP_DRV_LOG(DEBUG,
- "(%s) bank(%s) slice_size(%s)\n",
- tf_tbl_type_2_str(parms->tbl_type),
- tf_sram_bank_2_str(parms->bank_id),
- tf_sram_slice_2_str(parms->slice_size));
return rc;
}
@@ -373,7 +368,6 @@ tf_tbl_sram_free(struct tf *tfp __rte_unused,
return rc;
}
-
#if (DBG_SRAM == 1)
{
struct tf_sram_mgr_dump_parms dparms;
@@ -411,7 +405,6 @@ tf_tbl_sram_set(struct tf *tfp,
void *sram_handle = NULL;
uint16_t base = 0, shift = 0;
-
TF_CHECK_PARMS3(tfp, parms, parms->data);
/* Retrieve the session information */
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
index f74687acfa..ad3866243d 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 20 11:56:39 2021 */
+/* date: Fri Aug 6 11:15:47 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -362,508 +362,652 @@ uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {
[BNXT_ULP_CLASS_HID_315d] = 344,
[BNXT_ULP_CLASS_HID_3612] = 345,
[BNXT_ULP_CLASS_HID_66da] = 346,
- [BNXT_ULP_CLASS_HID_6165] = 347,
- [BNXT_ULP_CLASS_HID_2aa1] = 348,
- [BNXT_ULP_CLASS_HID_09cd] = 349,
- [BNXT_ULP_CLASS_HID_3845] = 350,
- [BNXT_ULP_CLASS_HID_11e9] = 351,
- [BNXT_ULP_CLASS_HID_4361] = 352,
- [BNXT_ULP_CLASS_HID_218d] = 353,
- [BNXT_ULP_CLASS_HID_5105] = 354,
- [BNXT_ULP_CLASS_HID_0c89] = 355,
- [BNXT_ULP_CLASS_HID_3e81] = 356,
- [BNXT_ULP_CLASS_HID_1dad] = 357,
- [BNXT_ULP_CLASS_HID_4ca5] = 358,
- [BNXT_ULP_CLASS_HID_25c9] = 359,
- [BNXT_ULP_CLASS_HID_57c1] = 360,
- [BNXT_ULP_CLASS_HID_33ed] = 361,
- [BNXT_ULP_CLASS_HID_65e5] = 362,
- [BNXT_ULP_CLASS_HID_6dd9] = 363,
- [BNXT_ULP_CLASS_HID_261d] = 364,
- [BNXT_ULP_CLASS_HID_0571] = 365,
- [BNXT_ULP_CLASS_HID_34f9] = 366,
- [BNXT_ULP_CLASS_HID_1d55] = 367,
- [BNXT_ULP_CLASS_HID_4fdd] = 368,
- [BNXT_ULP_CLASS_HID_2d31] = 369,
- [BNXT_ULP_CLASS_HID_5db9] = 370,
- [BNXT_ULP_CLASS_HID_0035] = 371,
- [BNXT_ULP_CLASS_HID_323d] = 372,
- [BNXT_ULP_CLASS_HID_1111] = 373,
- [BNXT_ULP_CLASS_HID_4019] = 374,
- [BNXT_ULP_CLASS_HID_2975] = 375,
- [BNXT_ULP_CLASS_HID_5b7d] = 376,
- [BNXT_ULP_CLASS_HID_3f51] = 377,
- [BNXT_ULP_CLASS_HID_6959] = 378,
- [BNXT_ULP_CLASS_HID_0e85] = 379,
- [BNXT_ULP_CLASS_HID_380d] = 380,
- [BNXT_ULP_CLASS_HID_1f21] = 381,
- [BNXT_ULP_CLASS_HID_4ea9] = 382,
- [BNXT_ULP_CLASS_HID_1705] = 383,
- [BNXT_ULP_CLASS_HID_418d] = 384,
- [BNXT_ULP_CLASS_HID_2721] = 385,
- [BNXT_ULP_CLASS_HID_57a9] = 386,
- [BNXT_ULP_CLASS_HID_1a25] = 387,
- [BNXT_ULP_CLASS_HID_342d] = 388,
- [BNXT_ULP_CLASS_HID_2b01] = 389,
- [BNXT_ULP_CLASS_HID_5a09] = 390,
- [BNXT_ULP_CLASS_HID_2325] = 391,
- [BNXT_ULP_CLASS_HID_5d2d] = 392,
- [BNXT_ULP_CLASS_HID_3101] = 393,
- [BNXT_ULP_CLASS_HID_6309] = 394,
- [BNXT_ULP_CLASS_HID_0bad] = 395,
- [BNXT_ULP_CLASS_HID_2535] = 396,
- [BNXT_ULP_CLASS_HID_1869] = 397,
- [BNXT_ULP_CLASS_HID_4bf1] = 398,
- [BNXT_ULP_CLASS_HID_136d] = 399,
- [BNXT_ULP_CLASS_HID_43f5] = 400,
- [BNXT_ULP_CLASS_HID_2129] = 401,
- [BNXT_ULP_CLASS_HID_53b1] = 402,
- [BNXT_ULP_CLASS_HID_072d] = 403,
- [BNXT_ULP_CLASS_HID_3135] = 404,
- [BNXT_ULP_CLASS_HID_1429] = 405,
- [BNXT_ULP_CLASS_HID_4731] = 406,
- [BNXT_ULP_CLASS_HID_2f6d] = 407,
- [BNXT_ULP_CLASS_HID_5f75] = 408,
- [BNXT_ULP_CLASS_HID_3d69] = 409,
- [BNXT_ULP_CLASS_HID_6f71] = 410,
- [BNXT_ULP_CLASS_HID_0dbd] = 411,
- [BNXT_ULP_CLASS_HID_3f25] = 412,
- [BNXT_ULP_CLASS_HID_1239] = 413,
- [BNXT_ULP_CLASS_HID_4da1] = 414,
- [BNXT_ULP_CLASS_HID_153d] = 415,
- [BNXT_ULP_CLASS_HID_45a5] = 416,
- [BNXT_ULP_CLASS_HID_3bb9] = 417,
- [BNXT_ULP_CLASS_HID_55a1] = 418,
- [BNXT_ULP_CLASS_HID_193d] = 419,
- [BNXT_ULP_CLASS_HID_4b25] = 420,
- [BNXT_ULP_CLASS_HID_2e39] = 421,
- [BNXT_ULP_CLASS_HID_5921] = 422,
- [BNXT_ULP_CLASS_HID_213d] = 423,
- [BNXT_ULP_CLASS_HID_5125] = 424,
- [BNXT_ULP_CLASS_HID_3739] = 425,
- [BNXT_ULP_CLASS_HID_093d] = 426,
- [BNXT_ULP_CLASS_HID_684d] = 427,
- [BNXT_ULP_CLASS_HID_2389] = 428,
- [BNXT_ULP_CLASS_HID_00e5] = 429,
- [BNXT_ULP_CLASS_HID_316d] = 430,
- [BNXT_ULP_CLASS_HID_18c1] = 431,
- [BNXT_ULP_CLASS_HID_4a49] = 432,
- [BNXT_ULP_CLASS_HID_28a5] = 433,
- [BNXT_ULP_CLASS_HID_582d] = 434,
- [BNXT_ULP_CLASS_HID_05a1] = 435,
- [BNXT_ULP_CLASS_HID_37a9] = 436,
- [BNXT_ULP_CLASS_HID_1485] = 437,
- [BNXT_ULP_CLASS_HID_458d] = 438,
- [BNXT_ULP_CLASS_HID_2ce1] = 439,
- [BNXT_ULP_CLASS_HID_5ee9] = 440,
- [BNXT_ULP_CLASS_HID_3ac5] = 441,
- [BNXT_ULP_CLASS_HID_6ccd] = 442,
- [BNXT_ULP_CLASS_HID_0b11] = 443,
- [BNXT_ULP_CLASS_HID_3d99] = 444,
- [BNXT_ULP_CLASS_HID_1ab5] = 445,
- [BNXT_ULP_CLASS_HID_4b3d] = 446,
- [BNXT_ULP_CLASS_HID_1291] = 447,
- [BNXT_ULP_CLASS_HID_4419] = 448,
- [BNXT_ULP_CLASS_HID_22b5] = 449,
- [BNXT_ULP_CLASS_HID_523d] = 450,
- [BNXT_ULP_CLASS_HID_1fb1] = 451,
- [BNXT_ULP_CLASS_HID_31b9] = 452,
- [BNXT_ULP_CLASS_HID_2e95] = 453,
- [BNXT_ULP_CLASS_HID_5f9d] = 454,
- [BNXT_ULP_CLASS_HID_26b1] = 455,
- [BNXT_ULP_CLASS_HID_58b9] = 456,
- [BNXT_ULP_CLASS_HID_3495] = 457,
- [BNXT_ULP_CLASS_HID_669d] = 458,
- [BNXT_ULP_CLASS_HID_0e39] = 459,
- [BNXT_ULP_CLASS_HID_20a1] = 460,
- [BNXT_ULP_CLASS_HID_1dfd] = 461,
- [BNXT_ULP_CLASS_HID_4e65] = 462,
- [BNXT_ULP_CLASS_HID_16f9] = 463,
- [BNXT_ULP_CLASS_HID_4661] = 464,
- [BNXT_ULP_CLASS_HID_24bd] = 465,
- [BNXT_ULP_CLASS_HID_5625] = 466,
- [BNXT_ULP_CLASS_HID_02b9] = 467,
- [BNXT_ULP_CLASS_HID_34a1] = 468,
- [BNXT_ULP_CLASS_HID_11bd] = 469,
- [BNXT_ULP_CLASS_HID_42a5] = 470,
- [BNXT_ULP_CLASS_HID_2af9] = 471,
- [BNXT_ULP_CLASS_HID_5ae1] = 472,
- [BNXT_ULP_CLASS_HID_38fd] = 473,
- [BNXT_ULP_CLASS_HID_6ae5] = 474,
- [BNXT_ULP_CLASS_HID_0829] = 475,
- [BNXT_ULP_CLASS_HID_3ab1] = 476,
- [BNXT_ULP_CLASS_HID_17ad] = 477,
- [BNXT_ULP_CLASS_HID_4835] = 478,
- [BNXT_ULP_CLASS_HID_10a9] = 479,
- [BNXT_ULP_CLASS_HID_4031] = 480,
- [BNXT_ULP_CLASS_HID_3e2d] = 481,
- [BNXT_ULP_CLASS_HID_5035] = 482,
- [BNXT_ULP_CLASS_HID_1ca9] = 483,
- [BNXT_ULP_CLASS_HID_4eb1] = 484,
- [BNXT_ULP_CLASS_HID_2bad] = 485,
- [BNXT_ULP_CLASS_HID_5cb5] = 486,
- [BNXT_ULP_CLASS_HID_24a9] = 487,
- [BNXT_ULP_CLASS_HID_54b1] = 488,
- [BNXT_ULP_CLASS_HID_32ad] = 489,
- [BNXT_ULP_CLASS_HID_0ca9] = 490,
- [BNXT_ULP_CLASS_HID_7f35] = 491,
- [BNXT_ULP_CLASS_HID_34f1] = 492,
- [BNXT_ULP_CLASS_HID_179d] = 493,
- [BNXT_ULP_CLASS_HID_2615] = 494,
- [BNXT_ULP_CLASS_HID_0fb9] = 495,
- [BNXT_ULP_CLASS_HID_5d31] = 496,
- [BNXT_ULP_CLASS_HID_3fdd] = 497,
- [BNXT_ULP_CLASS_HID_4f55] = 498,
- [BNXT_ULP_CLASS_HID_12d9] = 499,
- [BNXT_ULP_CLASS_HID_20d1] = 500,
- [BNXT_ULP_CLASS_HID_03fd] = 501,
- [BNXT_ULP_CLASS_HID_52f5] = 502,
- [BNXT_ULP_CLASS_HID_3b99] = 503,
- [BNXT_ULP_CLASS_HID_4991] = 504,
- [BNXT_ULP_CLASS_HID_2dbd] = 505,
- [BNXT_ULP_CLASS_HID_7bb5] = 506,
- [BNXT_ULP_CLASS_HID_34c6] = 507,
- [BNXT_ULP_CLASS_HID_0c22] = 508,
- [BNXT_ULP_CLASS_HID_1cbe] = 509,
- [BNXT_ULP_CLASS_HID_179a] = 510,
- [BNXT_ULP_CLASS_HID_59be] = 511,
- [BNXT_ULP_CLASS_HID_515a] = 512,
- [BNXT_ULP_CLASS_HID_1c72] = 513,
- [BNXT_ULP_CLASS_HID_171e] = 514,
- [BNXT_ULP_CLASS_HID_19c8] = 515,
- [BNXT_ULP_CLASS_HID_112c] = 516,
- [BNXT_ULP_CLASS_HID_4d68] = 517,
- [BNXT_ULP_CLASS_HID_444c] = 518,
- [BNXT_ULP_CLASS_HID_0e8c] = 519,
- [BNXT_ULP_CLASS_HID_09e0] = 520,
- [BNXT_ULP_CLASS_HID_1af0] = 521,
- [BNXT_ULP_CLASS_HID_15d4] = 522,
- [BNXT_ULP_CLASS_HID_1dd0] = 523,
- [BNXT_ULP_CLASS_HID_14f4] = 524,
- [BNXT_ULP_CLASS_HID_70b0] = 525,
- [BNXT_ULP_CLASS_HID_4854] = 526,
- [BNXT_ULP_CLASS_HID_3dd4] = 527,
- [BNXT_ULP_CLASS_HID_34f8] = 528,
- [BNXT_ULP_CLASS_HID_09e8] = 529,
- [BNXT_ULP_CLASS_HID_008c] = 530,
- [BNXT_ULP_CLASS_HID_34e6] = 531,
- [BNXT_ULP_CLASS_HID_0c02] = 532,
- [BNXT_ULP_CLASS_HID_1c9e] = 533,
- [BNXT_ULP_CLASS_HID_17ba] = 534,
- [BNXT_ULP_CLASS_HID_429e] = 535,
- [BNXT_ULP_CLASS_HID_5dba] = 536,
- [BNXT_ULP_CLASS_HID_2a16] = 537,
- [BNXT_ULP_CLASS_HID_2532] = 538,
- [BNXT_ULP_CLASS_HID_2da2] = 539,
- [BNXT_ULP_CLASS_HID_24fe] = 540,
- [BNXT_ULP_CLASS_HID_355a] = 541,
- [BNXT_ULP_CLASS_HID_0c76] = 542,
- [BNXT_ULP_CLASS_HID_13e6] = 543,
- [BNXT_ULP_CLASS_HID_7276] = 544,
- [BNXT_ULP_CLASS_HID_42d2] = 545,
- [BNXT_ULP_CLASS_HID_5dee] = 546,
- [BNXT_ULP_CLASS_HID_59de] = 547,
- [BNXT_ULP_CLASS_HID_513a] = 548,
- [BNXT_ULP_CLASS_HID_1c12] = 549,
- [BNXT_ULP_CLASS_HID_177e] = 550,
- [BNXT_ULP_CLASS_HID_0e92] = 551,
- [BNXT_ULP_CLASS_HID_09fe] = 552,
- [BNXT_ULP_CLASS_HID_5c1a] = 553,
- [BNXT_ULP_CLASS_HID_5746] = 554,
- [BNXT_ULP_CLASS_HID_79da] = 555,
- [BNXT_ULP_CLASS_HID_7106] = 556,
- [BNXT_ULP_CLASS_HID_3c1e] = 557,
- [BNXT_ULP_CLASS_HID_377a] = 558,
- [BNXT_ULP_CLASS_HID_2e9e] = 559,
- [BNXT_ULP_CLASS_HID_29fa] = 560,
- [BNXT_ULP_CLASS_HID_14d2] = 561,
- [BNXT_ULP_CLASS_HID_7742] = 562,
- [BNXT_ULP_CLASS_HID_3706] = 563,
- [BNXT_ULP_CLASS_HID_0fe2] = 564,
- [BNXT_ULP_CLASS_HID_1f7e] = 565,
- [BNXT_ULP_CLASS_HID_145a] = 566,
- [BNXT_ULP_CLASS_HID_417e] = 567,
- [BNXT_ULP_CLASS_HID_5e5a] = 568,
- [BNXT_ULP_CLASS_HID_29f6] = 569,
- [BNXT_ULP_CLASS_HID_26d2] = 570,
- [BNXT_ULP_CLASS_HID_2e42] = 571,
- [BNXT_ULP_CLASS_HID_271e] = 572,
- [BNXT_ULP_CLASS_HID_36ba] = 573,
- [BNXT_ULP_CLASS_HID_0f96] = 574,
- [BNXT_ULP_CLASS_HID_1006] = 575,
- [BNXT_ULP_CLASS_HID_7196] = 576,
- [BNXT_ULP_CLASS_HID_4132] = 577,
- [BNXT_ULP_CLASS_HID_5e0e] = 578,
- [BNXT_ULP_CLASS_HID_59fe] = 579,
- [BNXT_ULP_CLASS_HID_511a] = 580,
- [BNXT_ULP_CLASS_HID_1c32] = 581,
- [BNXT_ULP_CLASS_HID_175e] = 582,
- [BNXT_ULP_CLASS_HID_0eb2] = 583,
- [BNXT_ULP_CLASS_HID_09de] = 584,
- [BNXT_ULP_CLASS_HID_5c3a] = 585,
- [BNXT_ULP_CLASS_HID_5766] = 586,
- [BNXT_ULP_CLASS_HID_79fa] = 587,
- [BNXT_ULP_CLASS_HID_7126] = 588,
- [BNXT_ULP_CLASS_HID_3c3e] = 589,
- [BNXT_ULP_CLASS_HID_375a] = 590,
- [BNXT_ULP_CLASS_HID_2ebe] = 591,
- [BNXT_ULP_CLASS_HID_29da] = 592,
- [BNXT_ULP_CLASS_HID_14f2] = 593,
- [BNXT_ULP_CLASS_HID_7762] = 594,
- [BNXT_ULP_CLASS_HID_19e8] = 595,
- [BNXT_ULP_CLASS_HID_110c] = 596,
- [BNXT_ULP_CLASS_HID_4d48] = 597,
- [BNXT_ULP_CLASS_HID_446c] = 598,
- [BNXT_ULP_CLASS_HID_0eac] = 599,
- [BNXT_ULP_CLASS_HID_09c0] = 600,
- [BNXT_ULP_CLASS_HID_1ad0] = 601,
- [BNXT_ULP_CLASS_HID_15f4] = 602,
- [BNXT_ULP_CLASS_HID_39ec] = 603,
- [BNXT_ULP_CLASS_HID_3100] = 604,
- [BNXT_ULP_CLASS_HID_0210] = 605,
- [BNXT_ULP_CLASS_HID_1d34] = 606,
- [BNXT_ULP_CLASS_HID_2ea0] = 607,
- [BNXT_ULP_CLASS_HID_29c4] = 608,
- [BNXT_ULP_CLASS_HID_3ad4] = 609,
- [BNXT_ULP_CLASS_HID_35e8] = 610,
- [BNXT_ULP_CLASS_HID_5d80] = 611,
- [BNXT_ULP_CLASS_HID_54a4] = 612,
- [BNXT_ULP_CLASS_HID_29b4] = 613,
- [BNXT_ULP_CLASS_HID_20c8] = 614,
- [BNXT_ULP_CLASS_HID_7244] = 615,
- [BNXT_ULP_CLASS_HID_4d98] = 616,
- [BNXT_ULP_CLASS_HID_5e68] = 617,
- [BNXT_ULP_CLASS_HID_598c] = 618,
- [BNXT_ULP_CLASS_HID_1248] = 619,
- [BNXT_ULP_CLASS_HID_74d8] = 620,
- [BNXT_ULP_CLASS_HID_49a8] = 621,
- [BNXT_ULP_CLASS_HID_40cc] = 622,
- [BNXT_ULP_CLASS_HID_0b0c] = 623,
- [BNXT_ULP_CLASS_HID_0220] = 624,
- [BNXT_ULP_CLASS_HID_1730] = 625,
- [BNXT_ULP_CLASS_HID_7980] = 626,
- [BNXT_ULP_CLASS_HID_1db0] = 627,
- [BNXT_ULP_CLASS_HID_1494] = 628,
- [BNXT_ULP_CLASS_HID_70d0] = 629,
- [BNXT_ULP_CLASS_HID_4834] = 630,
- [BNXT_ULP_CLASS_HID_3db4] = 631,
- [BNXT_ULP_CLASS_HID_3498] = 632,
- [BNXT_ULP_CLASS_HID_0988] = 633,
- [BNXT_ULP_CLASS_HID_00ec] = 634,
- [BNXT_ULP_CLASS_HID_3f44] = 635,
- [BNXT_ULP_CLASS_HID_36a8] = 636,
- [BNXT_ULP_CLASS_HID_0b58] = 637,
- [BNXT_ULP_CLASS_HID_02bc] = 638,
- [BNXT_ULP_CLASS_HID_5f48] = 639,
- [BNXT_ULP_CLASS_HID_56ac] = 640,
- [BNXT_ULP_CLASS_HID_2b5c] = 641,
- [BNXT_ULP_CLASS_HID_2280] = 642,
- [BNXT_ULP_CLASS_HID_4000] = 643,
- [BNXT_ULP_CLASS_HID_5b64] = 644,
- [BNXT_ULP_CLASS_HID_2c14] = 645,
- [BNXT_ULP_CLASS_HID_2778] = 646,
- [BNXT_ULP_CLASS_HID_18f8] = 647,
- [BNXT_ULP_CLASS_HID_13dc] = 648,
- [BNXT_ULP_CLASS_HID_4c18] = 649,
- [BNXT_ULP_CLASS_HID_477c] = 650,
- [BNXT_ULP_CLASS_HID_1a88] = 651,
- [BNXT_ULP_CLASS_HID_15ec] = 652,
- [BNXT_ULP_CLASS_HID_4e28] = 653,
- [BNXT_ULP_CLASS_HID_490c] = 654,
- [BNXT_ULP_CLASS_HID_3a8c] = 655,
- [BNXT_ULP_CLASS_HID_35f0] = 656,
- [BNXT_ULP_CLASS_HID_06e0] = 657,
- [BNXT_ULP_CLASS_HID_01c4] = 658,
- [BNXT_ULP_CLASS_HID_1a08] = 659,
- [BNXT_ULP_CLASS_HID_12ec] = 660,
- [BNXT_ULP_CLASS_HID_4ea8] = 661,
- [BNXT_ULP_CLASS_HID_478c] = 662,
- [BNXT_ULP_CLASS_HID_0d4c] = 663,
- [BNXT_ULP_CLASS_HID_0a20] = 664,
- [BNXT_ULP_CLASS_HID_1930] = 665,
- [BNXT_ULP_CLASS_HID_1614] = 666,
- [BNXT_ULP_CLASS_HID_3a0c] = 667,
- [BNXT_ULP_CLASS_HID_32e0] = 668,
- [BNXT_ULP_CLASS_HID_01f0] = 669,
- [BNXT_ULP_CLASS_HID_1ed4] = 670,
- [BNXT_ULP_CLASS_HID_2d40] = 671,
- [BNXT_ULP_CLASS_HID_2a24] = 672,
- [BNXT_ULP_CLASS_HID_3934] = 673,
- [BNXT_ULP_CLASS_HID_3608] = 674,
- [BNXT_ULP_CLASS_HID_5e60] = 675,
- [BNXT_ULP_CLASS_HID_5744] = 676,
- [BNXT_ULP_CLASS_HID_2a54] = 677,
- [BNXT_ULP_CLASS_HID_2328] = 678,
- [BNXT_ULP_CLASS_HID_71a4] = 679,
- [BNXT_ULP_CLASS_HID_4e78] = 680,
- [BNXT_ULP_CLASS_HID_5d88] = 681,
- [BNXT_ULP_CLASS_HID_5a6c] = 682,
- [BNXT_ULP_CLASS_HID_11a8] = 683,
- [BNXT_ULP_CLASS_HID_7738] = 684,
- [BNXT_ULP_CLASS_HID_4a48] = 685,
- [BNXT_ULP_CLASS_HID_432c] = 686,
- [BNXT_ULP_CLASS_HID_08ec] = 687,
- [BNXT_ULP_CLASS_HID_01c0] = 688,
- [BNXT_ULP_CLASS_HID_14d0] = 689,
- [BNXT_ULP_CLASS_HID_7a60] = 690,
- [BNXT_ULP_CLASS_HID_1d90] = 691,
- [BNXT_ULP_CLASS_HID_14b4] = 692,
- [BNXT_ULP_CLASS_HID_70f0] = 693,
- [BNXT_ULP_CLASS_HID_4814] = 694,
- [BNXT_ULP_CLASS_HID_3d94] = 695,
- [BNXT_ULP_CLASS_HID_34b8] = 696,
- [BNXT_ULP_CLASS_HID_09a8] = 697,
- [BNXT_ULP_CLASS_HID_00cc] = 698,
- [BNXT_ULP_CLASS_HID_3f64] = 699,
- [BNXT_ULP_CLASS_HID_3688] = 700,
- [BNXT_ULP_CLASS_HID_0b78] = 701,
- [BNXT_ULP_CLASS_HID_029c] = 702,
- [BNXT_ULP_CLASS_HID_5f68] = 703,
- [BNXT_ULP_CLASS_HID_568c] = 704,
- [BNXT_ULP_CLASS_HID_2b7c] = 705,
- [BNXT_ULP_CLASS_HID_22a0] = 706,
- [BNXT_ULP_CLASS_HID_4020] = 707,
- [BNXT_ULP_CLASS_HID_5b44] = 708,
- [BNXT_ULP_CLASS_HID_2c34] = 709,
- [BNXT_ULP_CLASS_HID_2758] = 710,
- [BNXT_ULP_CLASS_HID_18d8] = 711,
- [BNXT_ULP_CLASS_HID_13fc] = 712,
- [BNXT_ULP_CLASS_HID_4c38] = 713,
- [BNXT_ULP_CLASS_HID_475c] = 714,
- [BNXT_ULP_CLASS_HID_1aa8] = 715,
- [BNXT_ULP_CLASS_HID_15cc] = 716,
- [BNXT_ULP_CLASS_HID_4e08] = 717,
- [BNXT_ULP_CLASS_HID_492c] = 718,
- [BNXT_ULP_CLASS_HID_3aac] = 719,
- [BNXT_ULP_CLASS_HID_35d0] = 720,
- [BNXT_ULP_CLASS_HID_06c0] = 721,
- [BNXT_ULP_CLASS_HID_01e4] = 722,
- [BNXT_ULP_CLASS_HID_4d32] = 723,
- [BNXT_ULP_CLASS_HID_54aa] = 724,
- [BNXT_ULP_CLASS_HID_0686] = 725,
- [BNXT_ULP_CLASS_HID_540e] = 726,
- [BNXT_ULP_CLASS_HID_2e3c] = 727,
- [BNXT_ULP_CLASS_HID_3a20] = 728,
- [BNXT_ULP_CLASS_HID_46f0] = 729,
- [BNXT_ULP_CLASS_HID_52e4] = 730,
- [BNXT_ULP_CLASS_HID_55e4] = 731,
- [BNXT_ULP_CLASS_HID_21f8] = 732,
- [BNXT_ULP_CLASS_HID_75e8] = 733,
- [BNXT_ULP_CLASS_HID_41fc] = 734,
- [BNXT_ULP_CLASS_HID_4d12] = 735,
- [BNXT_ULP_CLASS_HID_548a] = 736,
- [BNXT_ULP_CLASS_HID_3356] = 737,
- [BNXT_ULP_CLASS_HID_1ace] = 738,
- [BNXT_ULP_CLASS_HID_1a9a] = 739,
- [BNXT_ULP_CLASS_HID_4d46] = 740,
- [BNXT_ULP_CLASS_HID_2812] = 741,
- [BNXT_ULP_CLASS_HID_338a] = 742,
- [BNXT_ULP_CLASS_HID_06e6] = 743,
- [BNXT_ULP_CLASS_HID_546e] = 744,
- [BNXT_ULP_CLASS_HID_46ee] = 745,
- [BNXT_ULP_CLASS_HID_0d22] = 746,
- [BNXT_ULP_CLASS_HID_26e2] = 747,
- [BNXT_ULP_CLASS_HID_746a] = 748,
- [BNXT_ULP_CLASS_HID_1fa6] = 749,
- [BNXT_ULP_CLASS_HID_2d2e] = 750,
- [BNXT_ULP_CLASS_HID_4ef2] = 751,
- [BNXT_ULP_CLASS_HID_576a] = 752,
- [BNXT_ULP_CLASS_HID_30b6] = 753,
- [BNXT_ULP_CLASS_HID_192e] = 754,
- [BNXT_ULP_CLASS_HID_197a] = 755,
- [BNXT_ULP_CLASS_HID_4ea6] = 756,
- [BNXT_ULP_CLASS_HID_2bf2] = 757,
- [BNXT_ULP_CLASS_HID_306a] = 758,
- [BNXT_ULP_CLASS_HID_06c6] = 759,
- [BNXT_ULP_CLASS_HID_544e] = 760,
- [BNXT_ULP_CLASS_HID_46ce] = 761,
- [BNXT_ULP_CLASS_HID_0d02] = 762,
- [BNXT_ULP_CLASS_HID_26c2] = 763,
- [BNXT_ULP_CLASS_HID_744a] = 764,
- [BNXT_ULP_CLASS_HID_1f86] = 765,
- [BNXT_ULP_CLASS_HID_2d0e] = 766,
- [BNXT_ULP_CLASS_HID_2e1c] = 767,
- [BNXT_ULP_CLASS_HID_3a00] = 768,
- [BNXT_ULP_CLASS_HID_46d0] = 769,
- [BNXT_ULP_CLASS_HID_52c4] = 770,
- [BNXT_ULP_CLASS_HID_4e10] = 771,
- [BNXT_ULP_CLASS_HID_5a04] = 772,
- [BNXT_ULP_CLASS_HID_1f98] = 773,
- [BNXT_ULP_CLASS_HID_72f8] = 774,
- [BNXT_ULP_CLASS_HID_0a78] = 775,
- [BNXT_ULP_CLASS_HID_166c] = 776,
- [BNXT_ULP_CLASS_HID_233c] = 777,
- [BNXT_ULP_CLASS_HID_0f20] = 778,
- [BNXT_ULP_CLASS_HID_2a7c] = 779,
- [BNXT_ULP_CLASS_HID_3660] = 780,
- [BNXT_ULP_CLASS_HID_4330] = 781,
- [BNXT_ULP_CLASS_HID_2f24] = 782,
- [BNXT_ULP_CLASS_HID_5584] = 783,
- [BNXT_ULP_CLASS_HID_2198] = 784,
- [BNXT_ULP_CLASS_HID_7588] = 785,
- [BNXT_ULP_CLASS_HID_419c] = 786,
- [BNXT_ULP_CLASS_HID_7758] = 787,
- [BNXT_ULP_CLASS_HID_43ac] = 788,
- [BNXT_ULP_CLASS_HID_0c10] = 789,
- [BNXT_ULP_CLASS_HID_1864] = 790,
- [BNXT_ULP_CLASS_HID_30c8] = 791,
- [BNXT_ULP_CLASS_HID_1cdc] = 792,
- [BNXT_ULP_CLASS_HID_50cc] = 793,
- [BNXT_ULP_CLASS_HID_3d20] = 794,
- [BNXT_ULP_CLASS_HID_529c] = 795,
- [BNXT_ULP_CLASS_HID_3ef0] = 796,
- [BNXT_ULP_CLASS_HID_72e0] = 797,
- [BNXT_ULP_CLASS_HID_5ef4] = 798,
- [BNXT_ULP_CLASS_HID_2dfc] = 799,
- [BNXT_ULP_CLASS_HID_39e0] = 800,
- [BNXT_ULP_CLASS_HID_4530] = 801,
- [BNXT_ULP_CLASS_HID_5124] = 802,
- [BNXT_ULP_CLASS_HID_4df0] = 803,
- [BNXT_ULP_CLASS_HID_59e4] = 804,
- [BNXT_ULP_CLASS_HID_1c78] = 805,
- [BNXT_ULP_CLASS_HID_7118] = 806,
- [BNXT_ULP_CLASS_HID_0998] = 807,
- [BNXT_ULP_CLASS_HID_158c] = 808,
- [BNXT_ULP_CLASS_HID_20dc] = 809,
- [BNXT_ULP_CLASS_HID_0cc0] = 810,
- [BNXT_ULP_CLASS_HID_299c] = 811,
- [BNXT_ULP_CLASS_HID_3580] = 812,
- [BNXT_ULP_CLASS_HID_40d0] = 813,
- [BNXT_ULP_CLASS_HID_2cc4] = 814,
- [BNXT_ULP_CLASS_HID_55a4] = 815,
- [BNXT_ULP_CLASS_HID_21b8] = 816,
- [BNXT_ULP_CLASS_HID_75a8] = 817,
- [BNXT_ULP_CLASS_HID_41bc] = 818,
- [BNXT_ULP_CLASS_HID_7778] = 819,
- [BNXT_ULP_CLASS_HID_438c] = 820,
- [BNXT_ULP_CLASS_HID_0c30] = 821,
- [BNXT_ULP_CLASS_HID_1844] = 822,
- [BNXT_ULP_CLASS_HID_30e8] = 823,
- [BNXT_ULP_CLASS_HID_1cfc] = 824,
- [BNXT_ULP_CLASS_HID_50ec] = 825,
- [BNXT_ULP_CLASS_HID_3d00] = 826,
- [BNXT_ULP_CLASS_HID_52bc] = 827,
- [BNXT_ULP_CLASS_HID_3ed0] = 828,
- [BNXT_ULP_CLASS_HID_72c0] = 829,
- [BNXT_ULP_CLASS_HID_5ed4] = 830,
- [BNXT_ULP_CLASS_HID_3866] = 831,
- [BNXT_ULP_CLASS_HID_381e] = 832,
- [BNXT_ULP_CLASS_HID_3860] = 833,
- [BNXT_ULP_CLASS_HID_0454] = 834,
- [BNXT_ULP_CLASS_HID_3818] = 835,
- [BNXT_ULP_CLASS_HID_042c] = 836,
- [BNXT_ULP_CLASS_HID_3846] = 837,
- [BNXT_ULP_CLASS_HID_387e] = 838,
- [BNXT_ULP_CLASS_HID_3ba6] = 839,
- [BNXT_ULP_CLASS_HID_385e] = 840,
- [BNXT_ULP_CLASS_HID_3840] = 841,
- [BNXT_ULP_CLASS_HID_0474] = 842,
- [BNXT_ULP_CLASS_HID_3878] = 843,
- [BNXT_ULP_CLASS_HID_044c] = 844,
- [BNXT_ULP_CLASS_HID_3ba0] = 845,
- [BNXT_ULP_CLASS_HID_0794] = 846,
- [BNXT_ULP_CLASS_HID_3858] = 847,
- [BNXT_ULP_CLASS_HID_046c] = 848
+ [BNXT_ULP_CLASS_HID_e082] = 347,
+ [BNXT_ULP_CLASS_HID_ab46] = 348,
+ [BNXT_ULP_CLASS_HID_c82a] = 349,
+ [BNXT_ULP_CLASS_HID_f9a2] = 350,
+ [BNXT_ULP_CLASS_HID_d8ce] = 351,
+ [BNXT_ULP_CLASS_HID_a2d2] = 352,
+ [BNXT_ULP_CLASS_HID_c076] = 353,
+ [BNXT_ULP_CLASS_HID_f1ee] = 354,
+ [BNXT_ULP_CLASS_HID_a96e] = 355,
+ [BNXT_ULP_CLASS_HID_dae6] = 356,
+ [BNXT_ULP_CLASS_HID_c7aa] = 357,
+ [BNXT_ULP_CLASS_HID_c26e] = 358,
+ [BNXT_ULP_CLASS_HID_a0fa] = 359,
+ [BNXT_ULP_CLASS_HID_d272] = 360,
+ [BNXT_ULP_CLASS_HID_fff6] = 361,
+ [BNXT_ULP_CLASS_HID_e16e] = 362,
+ [BNXT_ULP_CLASS_HID_e165] = 363,
+ [BNXT_ULP_CLASS_HID_aaa1] = 364,
+ [BNXT_ULP_CLASS_HID_c9cd] = 365,
+ [BNXT_ULP_CLASS_HID_f845] = 366,
+ [BNXT_ULP_CLASS_HID_90f9] = 367,
+ [BNXT_ULP_CLASS_HID_c371] = 368,
+ [BNXT_ULP_CLASS_HID_e19d] = 369,
+ [BNXT_ULP_CLASS_HID_d015] = 370,
+ [BNXT_ULP_CLASS_HID_8c09] = 371,
+ [BNXT_ULP_CLASS_HID_be89] = 372,
+ [BNXT_ULP_CLASS_HID_ddad] = 373,
+ [BNXT_ULP_CLASS_HID_cc2d] = 374,
+ [BNXT_ULP_CLASS_HID_a4d9] = 375,
+ [BNXT_ULP_CLASS_HID_d759] = 376,
+ [BNXT_ULP_CLASS_HID_f27d] = 377,
+ [BNXT_ULP_CLASS_HID_e4fd] = 378,
+ [BNXT_ULP_CLASS_HID_ecf6] = 379,
+ [BNXT_ULP_CLASS_HID_a732] = 380,
+ [BNXT_ULP_CLASS_HID_c45e] = 381,
+ [BNXT_ULP_CLASS_HID_f5d6] = 382,
+ [BNXT_ULP_CLASS_HID_d4ba] = 383,
+ [BNXT_ULP_CLASS_HID_aea6] = 384,
+ [BNXT_ULP_CLASS_HID_cc02] = 385,
+ [BNXT_ULP_CLASS_HID_fd9a] = 386,
+ [BNXT_ULP_CLASS_HID_a51a] = 387,
+ [BNXT_ULP_CLASS_HID_d692] = 388,
+ [BNXT_ULP_CLASS_HID_cbde] = 389,
+ [BNXT_ULP_CLASS_HID_ce1a] = 390,
+ [BNXT_ULP_CLASS_HID_ac8e] = 391,
+ [BNXT_ULP_CLASS_HID_de06] = 392,
+ [BNXT_ULP_CLASS_HID_f382] = 393,
+ [BNXT_ULP_CLASS_HID_ed1a] = 394,
+ [BNXT_ULP_CLASS_HID_9d6a] = 395,
+ [BNXT_ULP_CLASS_HID_cee2] = 396,
+ [BNXT_ULP_CLASS_HID_ec0e] = 397,
+ [BNXT_ULP_CLASS_HID_dd86] = 398,
+ [BNXT_ULP_CLASS_HID_852e] = 399,
+ [BNXT_ULP_CLASS_HID_b6a6] = 400,
+ [BNXT_ULP_CLASS_HID_eb82] = 401,
+ [BNXT_ULP_CLASS_HID_c50a] = 402,
+ [BNXT_ULP_CLASS_HID_ccca] = 403,
+ [BNXT_ULP_CLASS_HID_8706] = 404,
+ [BNXT_ULP_CLASS_HID_d38e] = 405,
+ [BNXT_ULP_CLASS_HID_d5ca] = 406,
+ [BNXT_ULP_CLASS_HID_b48e] = 407,
+ [BNXT_ULP_CLASS_HID_8e8a] = 408,
+ [BNXT_ULP_CLASS_HID_db02] = 409,
+ [BNXT_ULP_CLASS_HID_dd8e] = 410,
+ [BNXT_ULP_CLASS_HID_819a] = 411,
+ [BNXT_ULP_CLASS_HID_b31a] = 412,
+ [BNXT_ULP_CLASS_HID_d03e] = 413,
+ [BNXT_ULP_CLASS_HID_c1be] = 414,
+ [BNXT_ULP_CLASS_HID_890e] = 415,
+ [BNXT_ULP_CLASS_HID_ba8e] = 416,
+ [BNXT_ULP_CLASS_HID_dfaa] = 417,
+ [BNXT_ULP_CLASS_HID_c93a] = 418,
+ [BNXT_ULP_CLASS_HID_b11a] = 419,
+ [BNXT_ULP_CLASS_HID_8b4e] = 420,
+ [BNXT_ULP_CLASS_HID_c79e] = 421,
+ [BNXT_ULP_CLASS_HID_d9da] = 422,
+ [BNXT_ULP_CLASS_HID_b88e] = 423,
+ [BNXT_ULP_CLASS_HID_ea0e] = 424,
+ [BNXT_ULP_CLASS_HID_cf0a] = 425,
+ [BNXT_ULP_CLASS_HID_c18e] = 426,
+ [BNXT_ULP_CLASS_HID_a94a] = 427,
+ [BNXT_ULP_CLASS_HID_daca] = 428,
+ [BNXT_ULP_CLASS_HID_ffee] = 429,
+ [BNXT_ULP_CLASS_HID_e96e] = 430,
+ [BNXT_ULP_CLASS_HID_910e] = 431,
+ [BNXT_ULP_CLASS_HID_c28e] = 432,
+ [BNXT_ULP_CLASS_HID_e7aa] = 433,
+ [BNXT_ULP_CLASS_HID_d12a] = 434,
+ [BNXT_ULP_CLASS_HID_d8ca] = 435,
+ [BNXT_ULP_CLASS_HID_930e] = 436,
+ [BNXT_ULP_CLASS_HID_ef4e] = 437,
+ [BNXT_ULP_CLASS_HID_e18a] = 438,
+ [BNXT_ULP_CLASS_HID_c08e] = 439,
+ [BNXT_ULP_CLASS_HID_9a8a] = 440,
+ [BNXT_ULP_CLASS_HID_d70a] = 441,
+ [BNXT_ULP_CLASS_HID_e90e] = 442,
+ [BNXT_ULP_CLASS_HID_edd9] = 443,
+ [BNXT_ULP_CLASS_HID_a61d] = 444,
+ [BNXT_ULP_CLASS_HID_c571] = 445,
+ [BNXT_ULP_CLASS_HID_f4f9] = 446,
+ [BNXT_ULP_CLASS_HID_9c45] = 447,
+ [BNXT_ULP_CLASS_HID_cfcd] = 448,
+ [BNXT_ULP_CLASS_HID_ed21] = 449,
+ [BNXT_ULP_CLASS_HID_dca9] = 450,
+ [BNXT_ULP_CLASS_HID_80b5] = 451,
+ [BNXT_ULP_CLASS_HID_b235] = 452,
+ [BNXT_ULP_CLASS_HID_d111] = 453,
+ [BNXT_ULP_CLASS_HID_c091] = 454,
+ [BNXT_ULP_CLASS_HID_a865] = 455,
+ [BNXT_ULP_CLASS_HID_dbe5] = 456,
+ [BNXT_ULP_CLASS_HID_fec1] = 457,
+ [BNXT_ULP_CLASS_HID_e841] = 458,
+ [BNXT_ULP_CLASS_HID_8e85] = 459,
+ [BNXT_ULP_CLASS_HID_b80d] = 460,
+ [BNXT_ULP_CLASS_HID_df65] = 461,
+ [BNXT_ULP_CLASS_HID_ceed] = 462,
+ [BNXT_ULP_CLASS_HID_9645] = 463,
+ [BNXT_ULP_CLASS_HID_c1cd] = 464,
+ [BNXT_ULP_CLASS_HID_e725] = 465,
+ [BNXT_ULP_CLASS_HID_d6ad] = 466,
+ [BNXT_ULP_CLASS_HID_9aa5] = 467,
+ [BNXT_ULP_CLASS_HID_b425] = 468,
+ [BNXT_ULP_CLASS_HID_eb05] = 469,
+ [BNXT_ULP_CLASS_HID_da85] = 470,
+ [BNXT_ULP_CLASS_HID_a265] = 471,
+ [BNXT_ULP_CLASS_HID_dde5] = 472,
+ [BNXT_ULP_CLASS_HID_f0c5] = 473,
+ [BNXT_ULP_CLASS_HID_e245] = 474,
+ [BNXT_ULP_CLASS_HID_8b8f] = 475,
+ [BNXT_ULP_CLASS_HID_a517] = 476,
+ [BNXT_ULP_CLASS_HID_d86b] = 477,
+ [BNXT_ULP_CLASS_HID_cbf3] = 478,
+ [BNXT_ULP_CLASS_HID_934f] = 479,
+ [BNXT_ULP_CLASS_HID_c2c7] = 480,
+ [BNXT_ULP_CLASS_HID_e02b] = 481,
+ [BNXT_ULP_CLASS_HID_d3a3] = 482,
+ [BNXT_ULP_CLASS_HID_87a7] = 483,
+ [BNXT_ULP_CLASS_HID_b137] = 484,
+ [BNXT_ULP_CLASS_HID_d403] = 485,
+ [BNXT_ULP_CLASS_HID_c793] = 486,
+ [BNXT_ULP_CLASS_HID_af67] = 487,
+ [BNXT_ULP_CLASS_HID_dee7] = 488,
+ [BNXT_ULP_CLASS_HID_fdc3] = 489,
+ [BNXT_ULP_CLASS_HID_ef43] = 490,
+ [BNXT_ULP_CLASS_HID_8dbf] = 491,
+ [BNXT_ULP_CLASS_HID_bf07] = 492,
+ [BNXT_ULP_CLASS_HID_d21f] = 493,
+ [BNXT_ULP_CLASS_HID_cde7] = 494,
+ [BNXT_ULP_CLASS_HID_956f] = 495,
+ [BNXT_ULP_CLASS_HID_c4c7] = 496,
+ [BNXT_ULP_CLASS_HID_fbcf] = 497,
+ [BNXT_ULP_CLASS_HID_d5a7] = 498,
+ [BNXT_ULP_CLASS_HID_9957] = 499,
+ [BNXT_ULP_CLASS_HID_cb27] = 500,
+ [BNXT_ULP_CLASS_HID_ee37] = 501,
+ [BNXT_ULP_CLASS_HID_d987] = 502,
+ [BNXT_ULP_CLASS_HID_a107] = 503,
+ [BNXT_ULP_CLASS_HID_d0e7] = 504,
+ [BNXT_ULP_CLASS_HID_f7e7] = 505,
+ [BNXT_ULP_CLASS_HID_c827] = 506,
+ [BNXT_ULP_CLASS_HID_f76a] = 507,
+ [BNXT_ULP_CLASS_HID_bcae] = 508,
+ [BNXT_ULP_CLASS_HID_dfc2] = 509,
+ [BNXT_ULP_CLASS_HID_ee4a] = 510,
+ [BNXT_ULP_CLASS_HID_cf26] = 511,
+ [BNXT_ULP_CLASS_HID_b53a] = 512,
+ [BNXT_ULP_CLASS_HID_d79e] = 513,
+ [BNXT_ULP_CLASS_HID_e606] = 514,
+ [BNXT_ULP_CLASS_HID_be86] = 515,
+ [BNXT_ULP_CLASS_HID_cd0e] = 516,
+ [BNXT_ULP_CLASS_HID_d042] = 517,
+ [BNXT_ULP_CLASS_HID_d586] = 518,
+ [BNXT_ULP_CLASS_HID_b712] = 519,
+ [BNXT_ULP_CLASS_HID_c59a] = 520,
+ [BNXT_ULP_CLASS_HID_e81e] = 521,
+ [BNXT_ULP_CLASS_HID_f686] = 522,
+ [BNXT_ULP_CLASS_HID_86f6] = 523,
+ [BNXT_ULP_CLASS_HID_d57e] = 524,
+ [BNXT_ULP_CLASS_HID_f792] = 525,
+ [BNXT_ULP_CLASS_HID_c61a] = 526,
+ [BNXT_ULP_CLASS_HID_9eb2] = 527,
+ [BNXT_ULP_CLASS_HID_ad3a] = 528,
+ [BNXT_ULP_CLASS_HID_f01e] = 529,
+ [BNXT_ULP_CLASS_HID_de96] = 530,
+ [BNXT_ULP_CLASS_HID_d756] = 531,
+ [BNXT_ULP_CLASS_HID_9c9a] = 532,
+ [BNXT_ULP_CLASS_HID_c812] = 533,
+ [BNXT_ULP_CLASS_HID_ce56] = 534,
+ [BNXT_ULP_CLASS_HID_af12] = 535,
+ [BNXT_ULP_CLASS_HID_9516] = 536,
+ [BNXT_ULP_CLASS_HID_c09e] = 537,
+ [BNXT_ULP_CLASS_HID_c612] = 538,
+ [BNXT_ULP_CLASS_HID_9a06] = 539,
+ [BNXT_ULP_CLASS_HID_a886] = 540,
+ [BNXT_ULP_CLASS_HID_cba2] = 541,
+ [BNXT_ULP_CLASS_HID_da22] = 542,
+ [BNXT_ULP_CLASS_HID_9292] = 543,
+ [BNXT_ULP_CLASS_HID_a112] = 544,
+ [BNXT_ULP_CLASS_HID_c436] = 545,
+ [BNXT_ULP_CLASS_HID_d2a6] = 546,
+ [BNXT_ULP_CLASS_HID_aa86] = 547,
+ [BNXT_ULP_CLASS_HID_90d2] = 548,
+ [BNXT_ULP_CLASS_HID_dc02] = 549,
+ [BNXT_ULP_CLASS_HID_c246] = 550,
+ [BNXT_ULP_CLASS_HID_a312] = 551,
+ [BNXT_ULP_CLASS_HID_f192] = 552,
+ [BNXT_ULP_CLASS_HID_d496] = 553,
+ [BNXT_ULP_CLASS_HID_da12] = 554,
+ [BNXT_ULP_CLASS_HID_b2d6] = 555,
+ [BNXT_ULP_CLASS_HID_c156] = 556,
+ [BNXT_ULP_CLASS_HID_e472] = 557,
+ [BNXT_ULP_CLASS_HID_f2f2] = 558,
+ [BNXT_ULP_CLASS_HID_8a92] = 559,
+ [BNXT_ULP_CLASS_HID_d912] = 560,
+ [BNXT_ULP_CLASS_HID_fc36] = 561,
+ [BNXT_ULP_CLASS_HID_cab6] = 562,
+ [BNXT_ULP_CLASS_HID_c356] = 563,
+ [BNXT_ULP_CLASS_HID_8892] = 564,
+ [BNXT_ULP_CLASS_HID_f4d2] = 565,
+ [BNXT_ULP_CLASS_HID_fa16] = 566,
+ [BNXT_ULP_CLASS_HID_db12] = 567,
+ [BNXT_ULP_CLASS_HID_8116] = 568,
+ [BNXT_ULP_CLASS_HID_cc96] = 569,
+ [BNXT_ULP_CLASS_HID_f292] = 570,
+ [BNXT_ULP_CLASS_HID_e84d] = 571,
+ [BNXT_ULP_CLASS_HID_a389] = 572,
+ [BNXT_ULP_CLASS_HID_c0e5] = 573,
+ [BNXT_ULP_CLASS_HID_f16d] = 574,
+ [BNXT_ULP_CLASS_HID_99d1] = 575,
+ [BNXT_ULP_CLASS_HID_ca59] = 576,
+ [BNXT_ULP_CLASS_HID_e8b5] = 577,
+ [BNXT_ULP_CLASS_HID_d93d] = 578,
+ [BNXT_ULP_CLASS_HID_8521] = 579,
+ [BNXT_ULP_CLASS_HID_b7a1] = 580,
+ [BNXT_ULP_CLASS_HID_d485] = 581,
+ [BNXT_ULP_CLASS_HID_c505] = 582,
+ [BNXT_ULP_CLASS_HID_adf1] = 583,
+ [BNXT_ULP_CLASS_HID_de71] = 584,
+ [BNXT_ULP_CLASS_HID_fb55] = 585,
+ [BNXT_ULP_CLASS_HID_edd5] = 586,
+ [BNXT_ULP_CLASS_HID_8b11] = 587,
+ [BNXT_ULP_CLASS_HID_bd99] = 588,
+ [BNXT_ULP_CLASS_HID_daf1] = 589,
+ [BNXT_ULP_CLASS_HID_cb79] = 590,
+ [BNXT_ULP_CLASS_HID_93d1] = 591,
+ [BNXT_ULP_CLASS_HID_c459] = 592,
+ [BNXT_ULP_CLASS_HID_e2b1] = 593,
+ [BNXT_ULP_CLASS_HID_d339] = 594,
+ [BNXT_ULP_CLASS_HID_9f31] = 595,
+ [BNXT_ULP_CLASS_HID_b1b1] = 596,
+ [BNXT_ULP_CLASS_HID_ee91] = 597,
+ [BNXT_ULP_CLASS_HID_df11] = 598,
+ [BNXT_ULP_CLASS_HID_a7f1] = 599,
+ [BNXT_ULP_CLASS_HID_d871] = 600,
+ [BNXT_ULP_CLASS_HID_f551] = 601,
+ [BNXT_ULP_CLASS_HID_e7d1] = 602,
+ [BNXT_ULP_CLASS_HID_8e1b] = 603,
+ [BNXT_ULP_CLASS_HID_a083] = 604,
+ [BNXT_ULP_CLASS_HID_ddff] = 605,
+ [BNXT_ULP_CLASS_HID_ce67] = 606,
+ [BNXT_ULP_CLASS_HID_96db] = 607,
+ [BNXT_ULP_CLASS_HID_c753] = 608,
+ [BNXT_ULP_CLASS_HID_e5bf] = 609,
+ [BNXT_ULP_CLASS_HID_d637] = 610,
+ [BNXT_ULP_CLASS_HID_8233] = 611,
+ [BNXT_ULP_CLASS_HID_b4a3] = 612,
+ [BNXT_ULP_CLASS_HID_d197] = 613,
+ [BNXT_ULP_CLASS_HID_c207] = 614,
+ [BNXT_ULP_CLASS_HID_aaf3] = 615,
+ [BNXT_ULP_CLASS_HID_db73] = 616,
+ [BNXT_ULP_CLASS_HID_f857] = 617,
+ [BNXT_ULP_CLASS_HID_ead7] = 618,
+ [BNXT_ULP_CLASS_HID_882b] = 619,
+ [BNXT_ULP_CLASS_HID_ba93] = 620,
+ [BNXT_ULP_CLASS_HID_d78b] = 621,
+ [BNXT_ULP_CLASS_HID_c873] = 622,
+ [BNXT_ULP_CLASS_HID_90fb] = 623,
+ [BNXT_ULP_CLASS_HID_c153] = 624,
+ [BNXT_ULP_CLASS_HID_fe5b] = 625,
+ [BNXT_ULP_CLASS_HID_d033] = 626,
+ [BNXT_ULP_CLASS_HID_9cc3] = 627,
+ [BNXT_ULP_CLASS_HID_ceb3] = 628,
+ [BNXT_ULP_CLASS_HID_eba3] = 629,
+ [BNXT_ULP_CLASS_HID_dc13] = 630,
+ [BNXT_ULP_CLASS_HID_a493] = 631,
+ [BNXT_ULP_CLASS_HID_d573] = 632,
+ [BNXT_ULP_CLASS_HID_f273] = 633,
+ [BNXT_ULP_CLASS_HID_cdb3] = 634,
+ [BNXT_ULP_CLASS_HID_ff35] = 635,
+ [BNXT_ULP_CLASS_HID_b4f1] = 636,
+ [BNXT_ULP_CLASS_HID_d79d] = 637,
+ [BNXT_ULP_CLASS_HID_e615] = 638,
+ [BNXT_ULP_CLASS_HID_8ea9] = 639,
+ [BNXT_ULP_CLASS_HID_dd21] = 640,
+ [BNXT_ULP_CLASS_HID_ffcd] = 641,
+ [BNXT_ULP_CLASS_HID_ce45] = 642,
+ [BNXT_ULP_CLASS_HID_9259] = 643,
+ [BNXT_ULP_CLASS_HID_a0d9] = 644,
+ [BNXT_ULP_CLASS_HID_c3fd] = 645,
+ [BNXT_ULP_CLASS_HID_d27d] = 646,
+ [BNXT_ULP_CLASS_HID_ba89] = 647,
+ [BNXT_ULP_CLASS_HID_c909] = 648,
+ [BNXT_ULP_CLASS_HID_ec2d] = 649,
+ [BNXT_ULP_CLASS_HID_faad] = 650,
+ [BNXT_ULP_CLASS_HID_34c6] = 651,
+ [BNXT_ULP_CLASS_HID_0c22] = 652,
+ [BNXT_ULP_CLASS_HID_1cbe] = 653,
+ [BNXT_ULP_CLASS_HID_179a] = 654,
+ [BNXT_ULP_CLASS_HID_59be] = 655,
+ [BNXT_ULP_CLASS_HID_515a] = 656,
+ [BNXT_ULP_CLASS_HID_1c72] = 657,
+ [BNXT_ULP_CLASS_HID_171e] = 658,
+ [BNXT_ULP_CLASS_HID_19c8] = 659,
+ [BNXT_ULP_CLASS_HID_112c] = 660,
+ [BNXT_ULP_CLASS_HID_4d68] = 661,
+ [BNXT_ULP_CLASS_HID_444c] = 662,
+ [BNXT_ULP_CLASS_HID_0e8c] = 663,
+ [BNXT_ULP_CLASS_HID_09e0] = 664,
+ [BNXT_ULP_CLASS_HID_1af0] = 665,
+ [BNXT_ULP_CLASS_HID_15d4] = 666,
+ [BNXT_ULP_CLASS_HID_1dd0] = 667,
+ [BNXT_ULP_CLASS_HID_14f4] = 668,
+ [BNXT_ULP_CLASS_HID_70b0] = 669,
+ [BNXT_ULP_CLASS_HID_4854] = 670,
+ [BNXT_ULP_CLASS_HID_3dd4] = 671,
+ [BNXT_ULP_CLASS_HID_34f8] = 672,
+ [BNXT_ULP_CLASS_HID_09e8] = 673,
+ [BNXT_ULP_CLASS_HID_008c] = 674,
+ [BNXT_ULP_CLASS_HID_34e6] = 675,
+ [BNXT_ULP_CLASS_HID_0c02] = 676,
+ [BNXT_ULP_CLASS_HID_1c9e] = 677,
+ [BNXT_ULP_CLASS_HID_17ba] = 678,
+ [BNXT_ULP_CLASS_HID_429e] = 679,
+ [BNXT_ULP_CLASS_HID_5dba] = 680,
+ [BNXT_ULP_CLASS_HID_2a16] = 681,
+ [BNXT_ULP_CLASS_HID_2532] = 682,
+ [BNXT_ULP_CLASS_HID_2da2] = 683,
+ [BNXT_ULP_CLASS_HID_24fe] = 684,
+ [BNXT_ULP_CLASS_HID_355a] = 685,
+ [BNXT_ULP_CLASS_HID_0c76] = 686,
+ [BNXT_ULP_CLASS_HID_13e6] = 687,
+ [BNXT_ULP_CLASS_HID_7276] = 688,
+ [BNXT_ULP_CLASS_HID_42d2] = 689,
+ [BNXT_ULP_CLASS_HID_5dee] = 690,
+ [BNXT_ULP_CLASS_HID_59de] = 691,
+ [BNXT_ULP_CLASS_HID_513a] = 692,
+ [BNXT_ULP_CLASS_HID_1c12] = 693,
+ [BNXT_ULP_CLASS_HID_177e] = 694,
+ [BNXT_ULP_CLASS_HID_0e92] = 695,
+ [BNXT_ULP_CLASS_HID_09fe] = 696,
+ [BNXT_ULP_CLASS_HID_5c1a] = 697,
+ [BNXT_ULP_CLASS_HID_5746] = 698,
+ [BNXT_ULP_CLASS_HID_79da] = 699,
+ [BNXT_ULP_CLASS_HID_7106] = 700,
+ [BNXT_ULP_CLASS_HID_3c1e] = 701,
+ [BNXT_ULP_CLASS_HID_377a] = 702,
+ [BNXT_ULP_CLASS_HID_2e9e] = 703,
+ [BNXT_ULP_CLASS_HID_29fa] = 704,
+ [BNXT_ULP_CLASS_HID_14d2] = 705,
+ [BNXT_ULP_CLASS_HID_7742] = 706,
+ [BNXT_ULP_CLASS_HID_3706] = 707,
+ [BNXT_ULP_CLASS_HID_0fe2] = 708,
+ [BNXT_ULP_CLASS_HID_1f7e] = 709,
+ [BNXT_ULP_CLASS_HID_145a] = 710,
+ [BNXT_ULP_CLASS_HID_417e] = 711,
+ [BNXT_ULP_CLASS_HID_5e5a] = 712,
+ [BNXT_ULP_CLASS_HID_29f6] = 713,
+ [BNXT_ULP_CLASS_HID_26d2] = 714,
+ [BNXT_ULP_CLASS_HID_2e42] = 715,
+ [BNXT_ULP_CLASS_HID_271e] = 716,
+ [BNXT_ULP_CLASS_HID_36ba] = 717,
+ [BNXT_ULP_CLASS_HID_0f96] = 718,
+ [BNXT_ULP_CLASS_HID_1006] = 719,
+ [BNXT_ULP_CLASS_HID_7196] = 720,
+ [BNXT_ULP_CLASS_HID_4132] = 721,
+ [BNXT_ULP_CLASS_HID_5e0e] = 722,
+ [BNXT_ULP_CLASS_HID_59fe] = 723,
+ [BNXT_ULP_CLASS_HID_511a] = 724,
+ [BNXT_ULP_CLASS_HID_1c32] = 725,
+ [BNXT_ULP_CLASS_HID_175e] = 726,
+ [BNXT_ULP_CLASS_HID_0eb2] = 727,
+ [BNXT_ULP_CLASS_HID_09de] = 728,
+ [BNXT_ULP_CLASS_HID_5c3a] = 729,
+ [BNXT_ULP_CLASS_HID_5766] = 730,
+ [BNXT_ULP_CLASS_HID_79fa] = 731,
+ [BNXT_ULP_CLASS_HID_7126] = 732,
+ [BNXT_ULP_CLASS_HID_3c3e] = 733,
+ [BNXT_ULP_CLASS_HID_375a] = 734,
+ [BNXT_ULP_CLASS_HID_2ebe] = 735,
+ [BNXT_ULP_CLASS_HID_29da] = 736,
+ [BNXT_ULP_CLASS_HID_14f2] = 737,
+ [BNXT_ULP_CLASS_HID_7762] = 738,
+ [BNXT_ULP_CLASS_HID_19e8] = 739,
+ [BNXT_ULP_CLASS_HID_110c] = 740,
+ [BNXT_ULP_CLASS_HID_4d48] = 741,
+ [BNXT_ULP_CLASS_HID_446c] = 742,
+ [BNXT_ULP_CLASS_HID_0eac] = 743,
+ [BNXT_ULP_CLASS_HID_09c0] = 744,
+ [BNXT_ULP_CLASS_HID_1ad0] = 745,
+ [BNXT_ULP_CLASS_HID_15f4] = 746,
+ [BNXT_ULP_CLASS_HID_39ec] = 747,
+ [BNXT_ULP_CLASS_HID_3100] = 748,
+ [BNXT_ULP_CLASS_HID_0210] = 749,
+ [BNXT_ULP_CLASS_HID_1d34] = 750,
+ [BNXT_ULP_CLASS_HID_2ea0] = 751,
+ [BNXT_ULP_CLASS_HID_29c4] = 752,
+ [BNXT_ULP_CLASS_HID_3ad4] = 753,
+ [BNXT_ULP_CLASS_HID_35e8] = 754,
+ [BNXT_ULP_CLASS_HID_5d80] = 755,
+ [BNXT_ULP_CLASS_HID_54a4] = 756,
+ [BNXT_ULP_CLASS_HID_29b4] = 757,
+ [BNXT_ULP_CLASS_HID_20c8] = 758,
+ [BNXT_ULP_CLASS_HID_7244] = 759,
+ [BNXT_ULP_CLASS_HID_4d98] = 760,
+ [BNXT_ULP_CLASS_HID_5e68] = 761,
+ [BNXT_ULP_CLASS_HID_598c] = 762,
+ [BNXT_ULP_CLASS_HID_1248] = 763,
+ [BNXT_ULP_CLASS_HID_74d8] = 764,
+ [BNXT_ULP_CLASS_HID_49a8] = 765,
+ [BNXT_ULP_CLASS_HID_40cc] = 766,
+ [BNXT_ULP_CLASS_HID_0b0c] = 767,
+ [BNXT_ULP_CLASS_HID_0220] = 768,
+ [BNXT_ULP_CLASS_HID_1730] = 769,
+ [BNXT_ULP_CLASS_HID_7980] = 770,
+ [BNXT_ULP_CLASS_HID_1db0] = 771,
+ [BNXT_ULP_CLASS_HID_1494] = 772,
+ [BNXT_ULP_CLASS_HID_70d0] = 773,
+ [BNXT_ULP_CLASS_HID_4834] = 774,
+ [BNXT_ULP_CLASS_HID_3db4] = 775,
+ [BNXT_ULP_CLASS_HID_3498] = 776,
+ [BNXT_ULP_CLASS_HID_0988] = 777,
+ [BNXT_ULP_CLASS_HID_00ec] = 778,
+ [BNXT_ULP_CLASS_HID_3f44] = 779,
+ [BNXT_ULP_CLASS_HID_36a8] = 780,
+ [BNXT_ULP_CLASS_HID_0b58] = 781,
+ [BNXT_ULP_CLASS_HID_02bc] = 782,
+ [BNXT_ULP_CLASS_HID_5f48] = 783,
+ [BNXT_ULP_CLASS_HID_56ac] = 784,
+ [BNXT_ULP_CLASS_HID_2b5c] = 785,
+ [BNXT_ULP_CLASS_HID_2280] = 786,
+ [BNXT_ULP_CLASS_HID_4000] = 787,
+ [BNXT_ULP_CLASS_HID_5b64] = 788,
+ [BNXT_ULP_CLASS_HID_2c14] = 789,
+ [BNXT_ULP_CLASS_HID_2778] = 790,
+ [BNXT_ULP_CLASS_HID_18f8] = 791,
+ [BNXT_ULP_CLASS_HID_13dc] = 792,
+ [BNXT_ULP_CLASS_HID_4c18] = 793,
+ [BNXT_ULP_CLASS_HID_477c] = 794,
+ [BNXT_ULP_CLASS_HID_1a88] = 795,
+ [BNXT_ULP_CLASS_HID_15ec] = 796,
+ [BNXT_ULP_CLASS_HID_4e28] = 797,
+ [BNXT_ULP_CLASS_HID_490c] = 798,
+ [BNXT_ULP_CLASS_HID_3a8c] = 799,
+ [BNXT_ULP_CLASS_HID_35f0] = 800,
+ [BNXT_ULP_CLASS_HID_06e0] = 801,
+ [BNXT_ULP_CLASS_HID_01c4] = 802,
+ [BNXT_ULP_CLASS_HID_1a08] = 803,
+ [BNXT_ULP_CLASS_HID_12ec] = 804,
+ [BNXT_ULP_CLASS_HID_4ea8] = 805,
+ [BNXT_ULP_CLASS_HID_478c] = 806,
+ [BNXT_ULP_CLASS_HID_0d4c] = 807,
+ [BNXT_ULP_CLASS_HID_0a20] = 808,
+ [BNXT_ULP_CLASS_HID_1930] = 809,
+ [BNXT_ULP_CLASS_HID_1614] = 810,
+ [BNXT_ULP_CLASS_HID_3a0c] = 811,
+ [BNXT_ULP_CLASS_HID_32e0] = 812,
+ [BNXT_ULP_CLASS_HID_01f0] = 813,
+ [BNXT_ULP_CLASS_HID_1ed4] = 814,
+ [BNXT_ULP_CLASS_HID_2d40] = 815,
+ [BNXT_ULP_CLASS_HID_2a24] = 816,
+ [BNXT_ULP_CLASS_HID_3934] = 817,
+ [BNXT_ULP_CLASS_HID_3608] = 818,
+ [BNXT_ULP_CLASS_HID_5e60] = 819,
+ [BNXT_ULP_CLASS_HID_5744] = 820,
+ [BNXT_ULP_CLASS_HID_2a54] = 821,
+ [BNXT_ULP_CLASS_HID_2328] = 822,
+ [BNXT_ULP_CLASS_HID_71a4] = 823,
+ [BNXT_ULP_CLASS_HID_4e78] = 824,
+ [BNXT_ULP_CLASS_HID_5d88] = 825,
+ [BNXT_ULP_CLASS_HID_5a6c] = 826,
+ [BNXT_ULP_CLASS_HID_11a8] = 827,
+ [BNXT_ULP_CLASS_HID_7738] = 828,
+ [BNXT_ULP_CLASS_HID_4a48] = 829,
+ [BNXT_ULP_CLASS_HID_432c] = 830,
+ [BNXT_ULP_CLASS_HID_08ec] = 831,
+ [BNXT_ULP_CLASS_HID_01c0] = 832,
+ [BNXT_ULP_CLASS_HID_14d0] = 833,
+ [BNXT_ULP_CLASS_HID_7a60] = 834,
+ [BNXT_ULP_CLASS_HID_1d90] = 835,
+ [BNXT_ULP_CLASS_HID_14b4] = 836,
+ [BNXT_ULP_CLASS_HID_70f0] = 837,
+ [BNXT_ULP_CLASS_HID_4814] = 838,
+ [BNXT_ULP_CLASS_HID_3d94] = 839,
+ [BNXT_ULP_CLASS_HID_34b8] = 840,
+ [BNXT_ULP_CLASS_HID_09a8] = 841,
+ [BNXT_ULP_CLASS_HID_00cc] = 842,
+ [BNXT_ULP_CLASS_HID_3f64] = 843,
+ [BNXT_ULP_CLASS_HID_3688] = 844,
+ [BNXT_ULP_CLASS_HID_0b78] = 845,
+ [BNXT_ULP_CLASS_HID_029c] = 846,
+ [BNXT_ULP_CLASS_HID_5f68] = 847,
+ [BNXT_ULP_CLASS_HID_568c] = 848,
+ [BNXT_ULP_CLASS_HID_2b7c] = 849,
+ [BNXT_ULP_CLASS_HID_22a0] = 850,
+ [BNXT_ULP_CLASS_HID_4020] = 851,
+ [BNXT_ULP_CLASS_HID_5b44] = 852,
+ [BNXT_ULP_CLASS_HID_2c34] = 853,
+ [BNXT_ULP_CLASS_HID_2758] = 854,
+ [BNXT_ULP_CLASS_HID_18d8] = 855,
+ [BNXT_ULP_CLASS_HID_13fc] = 856,
+ [BNXT_ULP_CLASS_HID_4c38] = 857,
+ [BNXT_ULP_CLASS_HID_475c] = 858,
+ [BNXT_ULP_CLASS_HID_1aa8] = 859,
+ [BNXT_ULP_CLASS_HID_15cc] = 860,
+ [BNXT_ULP_CLASS_HID_4e08] = 861,
+ [BNXT_ULP_CLASS_HID_492c] = 862,
+ [BNXT_ULP_CLASS_HID_3aac] = 863,
+ [BNXT_ULP_CLASS_HID_35d0] = 864,
+ [BNXT_ULP_CLASS_HID_06c0] = 865,
+ [BNXT_ULP_CLASS_HID_01e4] = 866,
+ [BNXT_ULP_CLASS_HID_4d32] = 867,
+ [BNXT_ULP_CLASS_HID_54aa] = 868,
+ [BNXT_ULP_CLASS_HID_0686] = 869,
+ [BNXT_ULP_CLASS_HID_540e] = 870,
+ [BNXT_ULP_CLASS_HID_2e3c] = 871,
+ [BNXT_ULP_CLASS_HID_3a20] = 872,
+ [BNXT_ULP_CLASS_HID_46f0] = 873,
+ [BNXT_ULP_CLASS_HID_52e4] = 874,
+ [BNXT_ULP_CLASS_HID_55e4] = 875,
+ [BNXT_ULP_CLASS_HID_21f8] = 876,
+ [BNXT_ULP_CLASS_HID_75e8] = 877,
+ [BNXT_ULP_CLASS_HID_41fc] = 878,
+ [BNXT_ULP_CLASS_HID_4d12] = 879,
+ [BNXT_ULP_CLASS_HID_548a] = 880,
+ [BNXT_ULP_CLASS_HID_3356] = 881,
+ [BNXT_ULP_CLASS_HID_1ace] = 882,
+ [BNXT_ULP_CLASS_HID_1a9a] = 883,
+ [BNXT_ULP_CLASS_HID_4d46] = 884,
+ [BNXT_ULP_CLASS_HID_2812] = 885,
+ [BNXT_ULP_CLASS_HID_338a] = 886,
+ [BNXT_ULP_CLASS_HID_06e6] = 887,
+ [BNXT_ULP_CLASS_HID_546e] = 888,
+ [BNXT_ULP_CLASS_HID_46ee] = 889,
+ [BNXT_ULP_CLASS_HID_0d22] = 890,
+ [BNXT_ULP_CLASS_HID_26e2] = 891,
+ [BNXT_ULP_CLASS_HID_746a] = 892,
+ [BNXT_ULP_CLASS_HID_1fa6] = 893,
+ [BNXT_ULP_CLASS_HID_2d2e] = 894,
+ [BNXT_ULP_CLASS_HID_4ef2] = 895,
+ [BNXT_ULP_CLASS_HID_576a] = 896,
+ [BNXT_ULP_CLASS_HID_30b6] = 897,
+ [BNXT_ULP_CLASS_HID_192e] = 898,
+ [BNXT_ULP_CLASS_HID_197a] = 899,
+ [BNXT_ULP_CLASS_HID_4ea6] = 900,
+ [BNXT_ULP_CLASS_HID_2bf2] = 901,
+ [BNXT_ULP_CLASS_HID_306a] = 902,
+ [BNXT_ULP_CLASS_HID_06c6] = 903,
+ [BNXT_ULP_CLASS_HID_544e] = 904,
+ [BNXT_ULP_CLASS_HID_46ce] = 905,
+ [BNXT_ULP_CLASS_HID_0d02] = 906,
+ [BNXT_ULP_CLASS_HID_26c2] = 907,
+ [BNXT_ULP_CLASS_HID_744a] = 908,
+ [BNXT_ULP_CLASS_HID_1f86] = 909,
+ [BNXT_ULP_CLASS_HID_2d0e] = 910,
+ [BNXT_ULP_CLASS_HID_2e1c] = 911,
+ [BNXT_ULP_CLASS_HID_3a00] = 912,
+ [BNXT_ULP_CLASS_HID_46d0] = 913,
+ [BNXT_ULP_CLASS_HID_52c4] = 914,
+ [BNXT_ULP_CLASS_HID_4e10] = 915,
+ [BNXT_ULP_CLASS_HID_5a04] = 916,
+ [BNXT_ULP_CLASS_HID_1f98] = 917,
+ [BNXT_ULP_CLASS_HID_72f8] = 918,
+ [BNXT_ULP_CLASS_HID_0a78] = 919,
+ [BNXT_ULP_CLASS_HID_166c] = 920,
+ [BNXT_ULP_CLASS_HID_233c] = 921,
+ [BNXT_ULP_CLASS_HID_0f20] = 922,
+ [BNXT_ULP_CLASS_HID_2a7c] = 923,
+ [BNXT_ULP_CLASS_HID_3660] = 924,
+ [BNXT_ULP_CLASS_HID_4330] = 925,
+ [BNXT_ULP_CLASS_HID_2f24] = 926,
+ [BNXT_ULP_CLASS_HID_5584] = 927,
+ [BNXT_ULP_CLASS_HID_2198] = 928,
+ [BNXT_ULP_CLASS_HID_7588] = 929,
+ [BNXT_ULP_CLASS_HID_419c] = 930,
+ [BNXT_ULP_CLASS_HID_7758] = 931,
+ [BNXT_ULP_CLASS_HID_43ac] = 932,
+ [BNXT_ULP_CLASS_HID_0c10] = 933,
+ [BNXT_ULP_CLASS_HID_1864] = 934,
+ [BNXT_ULP_CLASS_HID_30c8] = 935,
+ [BNXT_ULP_CLASS_HID_1cdc] = 936,
+ [BNXT_ULP_CLASS_HID_50cc] = 937,
+ [BNXT_ULP_CLASS_HID_3d20] = 938,
+ [BNXT_ULP_CLASS_HID_529c] = 939,
+ [BNXT_ULP_CLASS_HID_3ef0] = 940,
+ [BNXT_ULP_CLASS_HID_72e0] = 941,
+ [BNXT_ULP_CLASS_HID_5ef4] = 942,
+ [BNXT_ULP_CLASS_HID_2dfc] = 943,
+ [BNXT_ULP_CLASS_HID_39e0] = 944,
+ [BNXT_ULP_CLASS_HID_4530] = 945,
+ [BNXT_ULP_CLASS_HID_5124] = 946,
+ [BNXT_ULP_CLASS_HID_4df0] = 947,
+ [BNXT_ULP_CLASS_HID_59e4] = 948,
+ [BNXT_ULP_CLASS_HID_1c78] = 949,
+ [BNXT_ULP_CLASS_HID_7118] = 950,
+ [BNXT_ULP_CLASS_HID_0998] = 951,
+ [BNXT_ULP_CLASS_HID_158c] = 952,
+ [BNXT_ULP_CLASS_HID_20dc] = 953,
+ [BNXT_ULP_CLASS_HID_0cc0] = 954,
+ [BNXT_ULP_CLASS_HID_299c] = 955,
+ [BNXT_ULP_CLASS_HID_3580] = 956,
+ [BNXT_ULP_CLASS_HID_40d0] = 957,
+ [BNXT_ULP_CLASS_HID_2cc4] = 958,
+ [BNXT_ULP_CLASS_HID_55a4] = 959,
+ [BNXT_ULP_CLASS_HID_21b8] = 960,
+ [BNXT_ULP_CLASS_HID_75a8] = 961,
+ [BNXT_ULP_CLASS_HID_41bc] = 962,
+ [BNXT_ULP_CLASS_HID_7778] = 963,
+ [BNXT_ULP_CLASS_HID_438c] = 964,
+ [BNXT_ULP_CLASS_HID_0c30] = 965,
+ [BNXT_ULP_CLASS_HID_1844] = 966,
+ [BNXT_ULP_CLASS_HID_30e8] = 967,
+ [BNXT_ULP_CLASS_HID_1cfc] = 968,
+ [BNXT_ULP_CLASS_HID_50ec] = 969,
+ [BNXT_ULP_CLASS_HID_3d00] = 970,
+ [BNXT_ULP_CLASS_HID_52bc] = 971,
+ [BNXT_ULP_CLASS_HID_3ed0] = 972,
+ [BNXT_ULP_CLASS_HID_72c0] = 973,
+ [BNXT_ULP_CLASS_HID_5ed4] = 974,
+ [BNXT_ULP_CLASS_HID_3866] = 975,
+ [BNXT_ULP_CLASS_HID_381e] = 976,
+ [BNXT_ULP_CLASS_HID_3860] = 977,
+ [BNXT_ULP_CLASS_HID_0454] = 978,
+ [BNXT_ULP_CLASS_HID_3818] = 979,
+ [BNXT_ULP_CLASS_HID_042c] = 980,
+ [BNXT_ULP_CLASS_HID_3846] = 981,
+ [BNXT_ULP_CLASS_HID_387e] = 982,
+ [BNXT_ULP_CLASS_HID_3ba6] = 983,
+ [BNXT_ULP_CLASS_HID_385e] = 984,
+ [BNXT_ULP_CLASS_HID_3840] = 985,
+ [BNXT_ULP_CLASS_HID_0474] = 986,
+ [BNXT_ULP_CLASS_HID_3878] = 987,
+ [BNXT_ULP_CLASS_HID_044c] = 988,
+ [BNXT_ULP_CLASS_HID_3ba0] = 989,
+ [BNXT_ULP_CLASS_HID_0794] = 990,
+ [BNXT_ULP_CLASS_HID_3858] = 991,
+ [BNXT_ULP_CLASS_HID_046c] = 992
};
/* Array for the proto matcher list */
@@ -7165,7 +7309,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT }
},
[347] = {
- .class_hid = BNXT_ULP_CLASS_HID_6165,
+ .class_hid = BNXT_ULP_CLASS_HID_e082,
.class_tid = 2,
.hdr_sig_id = 1,
.flow_sig_id = 1313792,
@@ -7176,7 +7320,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7185,7 +7329,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC }
},
[348] = {
- .class_hid = BNXT_ULP_CLASS_HID_2aa1,
+ .class_hid = BNXT_ULP_CLASS_HID_ab46,
.class_tid = 2,
.hdr_sig_id = 1,
.flow_sig_id = 1321984,
@@ -7196,7 +7340,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7206,7 +7350,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC }
},
[349] = {
- .class_hid = BNXT_ULP_CLASS_HID_09cd,
+ .class_hid = BNXT_ULP_CLASS_HID_c82a,
.class_tid = 2,
.hdr_sig_id = 1,
.flow_sig_id = 3410944,
@@ -7217,7 +7361,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7227,7 +7371,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }
},
[350] = {
- .class_hid = BNXT_ULP_CLASS_HID_3845,
+ .class_hid = BNXT_ULP_CLASS_HID_f9a2,
.class_tid = 2,
.hdr_sig_id = 1,
.flow_sig_id = 3419136,
@@ -7238,7 +7382,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7249,10 +7393,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }
},
[351] = {
- .class_hid = BNXT_ULP_CLASS_HID_11e9,
+ .class_hid = BNXT_ULP_CLASS_HID_d8ce,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 2148797440,
+ .flow_sig_id = 538184704,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7260,20 +7404,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
},
[352] = {
- .class_hid = BNXT_ULP_CLASS_HID_4361,
+ .class_hid = BNXT_ULP_CLASS_HID_a2d2,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 2148805632,
+ .flow_sig_id = 538192896,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7281,7 +7425,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7289,13 +7433,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
},
[353] = {
- .class_hid = BNXT_ULP_CLASS_HID_218d,
+ .class_hid = BNXT_ULP_CLASS_HID_c076,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 2150894592,
+ .flow_sig_id = 540281856,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7303,7 +7447,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7311,13 +7455,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
},
[354] = {
- .class_hid = BNXT_ULP_CLASS_HID_5105,
+ .class_hid = BNXT_ULP_CLASS_HID_f1ee,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 2150902784,
+ .flow_sig_id = 540290048,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7325,7 +7469,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7334,13 +7478,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
},
[355] = {
- .class_hid = BNXT_ULP_CLASS_HID_0c89,
+ .class_hid = BNXT_ULP_CLASS_HID_a96e,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 4296281088,
+ .flow_sig_id = 1075055616,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7348,20 +7492,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[356] = {
- .class_hid = BNXT_ULP_CLASS_HID_3e81,
+ .class_hid = BNXT_ULP_CLASS_HID_dae6,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 4296289280,
+ .flow_sig_id = 1075063808,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7369,7 +7513,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7377,13 +7521,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[357] = {
- .class_hid = BNXT_ULP_CLASS_HID_1dad,
+ .class_hid = BNXT_ULP_CLASS_HID_c7aa,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 4298378240,
+ .flow_sig_id = 1077152768,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7391,7 +7535,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7399,13 +7543,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[358] = {
- .class_hid = BNXT_ULP_CLASS_HID_4ca5,
+ .class_hid = BNXT_ULP_CLASS_HID_c26e,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 4298386432,
+ .flow_sig_id = 1077160960,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7413,7 +7557,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7422,13 +7566,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[359] = {
- .class_hid = BNXT_ULP_CLASS_HID_25c9,
+ .class_hid = BNXT_ULP_CLASS_HID_a0fa,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 6443764736,
+ .flow_sig_id = 1611926528,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7436,21 +7580,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[360] = {
- .class_hid = BNXT_ULP_CLASS_HID_57c1,
+ .class_hid = BNXT_ULP_CLASS_HID_d272,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 6443772928,
+ .flow_sig_id = 1611934720,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7458,7 +7602,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7466,14 +7610,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[361] = {
- .class_hid = BNXT_ULP_CLASS_HID_33ed,
+ .class_hid = BNXT_ULP_CLASS_HID_fff6,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 6445861888,
+ .flow_sig_id = 1614023680,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7481,7 +7625,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7489,14 +7633,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[362] = {
- .class_hid = BNXT_ULP_CLASS_HID_65e5,
+ .class_hid = BNXT_ULP_CLASS_HID_e16e,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 6445870080,
+ .flow_sig_id = 1614031872,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7504,7 +7648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7513,11 +7657,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[363] = {
- .class_hid = BNXT_ULP_CLASS_HID_6dd9,
+ .class_hid = BNXT_ULP_CLASS_HID_e165,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 1313792,
@@ -7529,7 +7673,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7538,7 +7681,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }
},
[364] = {
- .class_hid = BNXT_ULP_CLASS_HID_261d,
+ .class_hid = BNXT_ULP_CLASS_HID_aaa1,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 1321984,
@@ -7550,7 +7693,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7560,7 +7702,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }
},
[365] = {
- .class_hid = BNXT_ULP_CLASS_HID_0571,
+ .class_hid = BNXT_ULP_CLASS_HID_c9cd,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 3410944,
@@ -7572,7 +7714,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7582,7 +7723,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
},
[366] = {
- .class_hid = BNXT_ULP_CLASS_HID_34f9,
+ .class_hid = BNXT_ULP_CLASS_HID_f845,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 3419136,
@@ -7594,7 +7735,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7605,7 +7745,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
},
[367] = {
- .class_hid = BNXT_ULP_CLASS_HID_1d55,
+ .class_hid = BNXT_ULP_CLASS_HID_90f9,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 2148797440,
@@ -7617,7 +7757,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7627,7 +7766,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
},
[368] = {
- .class_hid = BNXT_ULP_CLASS_HID_4fdd,
+ .class_hid = BNXT_ULP_CLASS_HID_c371,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 2148805632,
@@ -7639,7 +7778,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7650,7 +7788,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
},
[369] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d31,
+ .class_hid = BNXT_ULP_CLASS_HID_e19d,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 2150894592,
@@ -7662,7 +7800,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7673,7 +7810,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
},
[370] = {
- .class_hid = BNXT_ULP_CLASS_HID_5db9,
+ .class_hid = BNXT_ULP_CLASS_HID_d015,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 2150902784,
@@ -7685,7 +7822,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7697,7 +7833,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
},
[371] = {
- .class_hid = BNXT_ULP_CLASS_HID_0035,
+ .class_hid = BNXT_ULP_CLASS_HID_8c09,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 4296281088,
@@ -7709,7 +7845,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7719,7 +7854,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[372] = {
- .class_hid = BNXT_ULP_CLASS_HID_323d,
+ .class_hid = BNXT_ULP_CLASS_HID_be89,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 4296289280,
@@ -7731,7 +7866,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7742,7 +7876,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[373] = {
- .class_hid = BNXT_ULP_CLASS_HID_1111,
+ .class_hid = BNXT_ULP_CLASS_HID_ddad,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 4298378240,
@@ -7754,7 +7888,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7765,7 +7898,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[374] = {
- .class_hid = BNXT_ULP_CLASS_HID_4019,
+ .class_hid = BNXT_ULP_CLASS_HID_cc2d,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 4298386432,
@@ -7777,7 +7910,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7789,7 +7921,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[375] = {
- .class_hid = BNXT_ULP_CLASS_HID_2975,
+ .class_hid = BNXT_ULP_CLASS_HID_a4d9,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 6443764736,
@@ -7801,7 +7933,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7812,7 +7943,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[376] = {
- .class_hid = BNXT_ULP_CLASS_HID_5b7d,
+ .class_hid = BNXT_ULP_CLASS_HID_d759,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 6443772928,
@@ -7824,7 +7955,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7836,7 +7966,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[377] = {
- .class_hid = BNXT_ULP_CLASS_HID_3f51,
+ .class_hid = BNXT_ULP_CLASS_HID_f27d,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 6445861888,
@@ -7848,7 +7978,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7860,7 +7989,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[378] = {
- .class_hid = BNXT_ULP_CLASS_HID_6959,
+ .class_hid = BNXT_ULP_CLASS_HID_e4fd,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 6445870080,
@@ -7872,7 +8001,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7885,10 +8013,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[379] = {
- .class_hid = BNXT_ULP_CLASS_HID_0e85,
+ .class_hid = BNXT_ULP_CLASS_HID_ecf6,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 8591248384,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1313792,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7896,21 +8024,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
},
[380] = {
- .class_hid = BNXT_ULP_CLASS_HID_380d,
+ .class_hid = BNXT_ULP_CLASS_HID_a732,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 8591256576,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1321984,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7918,22 +8045,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
},
[381] = {
- .class_hid = BNXT_ULP_CLASS_HID_1f21,
+ .class_hid = BNXT_ULP_CLASS_HID_c45e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 8593345536,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3410944,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7941,22 +8067,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
},
[382] = {
- .class_hid = BNXT_ULP_CLASS_HID_4ea9,
+ .class_hid = BNXT_ULP_CLASS_HID_f5d6,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 8593353728,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3419136,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7964,23 +8089,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
},
[383] = {
- .class_hid = BNXT_ULP_CLASS_HID_1705,
+ .class_hid = BNXT_ULP_CLASS_HID_d4ba,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 10738732032,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 538184704,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7988,22 +8112,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[384] = {
- .class_hid = BNXT_ULP_CLASS_HID_418d,
+ .class_hid = BNXT_ULP_CLASS_HID_aea6,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 10738740224,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 538192896,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8011,23 +8134,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[385] = {
- .class_hid = BNXT_ULP_CLASS_HID_2721,
+ .class_hid = BNXT_ULP_CLASS_HID_cc02,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 10740829184,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 540281856,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8035,23 +8157,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[386] = {
- .class_hid = BNXT_ULP_CLASS_HID_57a9,
+ .class_hid = BNXT_ULP_CLASS_HID_fd9a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 10740837376,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 540290048,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8059,24 +8180,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[387] = {
- .class_hid = BNXT_ULP_CLASS_HID_1a25,
+ .class_hid = BNXT_ULP_CLASS_HID_a51a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 12886215680,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1075055616,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8084,22 +8204,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[388] = {
- .class_hid = BNXT_ULP_CLASS_HID_342d,
+ .class_hid = BNXT_ULP_CLASS_HID_d692,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 12886223872,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1075063808,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8107,23 +8226,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[389] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b01,
+ .class_hid = BNXT_ULP_CLASS_HID_cbde,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 12888312832,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1077152768,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8131,23 +8249,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[390] = {
- .class_hid = BNXT_ULP_CLASS_HID_5a09,
+ .class_hid = BNXT_ULP_CLASS_HID_ce1a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 12888321024,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1077160960,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8155,24 +8272,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[391] = {
- .class_hid = BNXT_ULP_CLASS_HID_2325,
+ .class_hid = BNXT_ULP_CLASS_HID_ac8e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 15033699328,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1611926528,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8180,23 +8296,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[392] = {
- .class_hid = BNXT_ULP_CLASS_HID_5d2d,
+ .class_hid = BNXT_ULP_CLASS_HID_de06,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 15033707520,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1611934720,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8204,24 +8319,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[393] = {
- .class_hid = BNXT_ULP_CLASS_HID_3101,
+ .class_hid = BNXT_ULP_CLASS_HID_f382,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 15035796480,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1614023680,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8229,24 +8343,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[394] = {
- .class_hid = BNXT_ULP_CLASS_HID_6309,
+ .class_hid = BNXT_ULP_CLASS_HID_ed1a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 15035804672,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1614031872,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8254,25 +8367,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[395] = {
- .class_hid = BNXT_ULP_CLASS_HID_0bad,
+ .class_hid = BNXT_ULP_CLASS_HID_9d6a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 17181182976,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2148797440,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8280,21 +8392,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[396] = {
- .class_hid = BNXT_ULP_CLASS_HID_2535,
+ .class_hid = BNXT_ULP_CLASS_HID_cee2,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 17181191168,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2148805632,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8302,22 +8414,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[397] = {
- .class_hid = BNXT_ULP_CLASS_HID_1869,
+ .class_hid = BNXT_ULP_CLASS_HID_ec0e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 17183280128,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2150894592,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8325,22 +8437,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[398] = {
- .class_hid = BNXT_ULP_CLASS_HID_4bf1,
+ .class_hid = BNXT_ULP_CLASS_HID_dd86,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 17183288320,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2150902784,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8348,23 +8460,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[399] = {
- .class_hid = BNXT_ULP_CLASS_HID_136d,
+ .class_hid = BNXT_ULP_CLASS_HID_852e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 19328666624,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2685668352,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8372,22 +8484,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[400] = {
- .class_hid = BNXT_ULP_CLASS_HID_43f5,
+ .class_hid = BNXT_ULP_CLASS_HID_b6a6,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 19328674816,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2685676544,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8395,23 +8507,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[401] = {
- .class_hid = BNXT_ULP_CLASS_HID_2129,
+ .class_hid = BNXT_ULP_CLASS_HID_eb82,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 19330763776,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2687765504,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8419,23 +8531,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[402] = {
- .class_hid = BNXT_ULP_CLASS_HID_53b1,
+ .class_hid = BNXT_ULP_CLASS_HID_c50a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 19330771968,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2687773696,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8443,24 +8555,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[403] = {
- .class_hid = BNXT_ULP_CLASS_HID_072d,
+ .class_hid = BNXT_ULP_CLASS_HID_ccca,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 21476150272,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3222539264,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8468,22 +8580,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[404] = {
- .class_hid = BNXT_ULP_CLASS_HID_3135,
+ .class_hid = BNXT_ULP_CLASS_HID_8706,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 21476158464,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3222547456,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8491,23 +8603,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[405] = {
- .class_hid = BNXT_ULP_CLASS_HID_1429,
+ .class_hid = BNXT_ULP_CLASS_HID_d38e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 21478247424,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3224636416,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8515,23 +8627,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[406] = {
- .class_hid = BNXT_ULP_CLASS_HID_4731,
+ .class_hid = BNXT_ULP_CLASS_HID_d5ca,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 21478255616,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3224644608,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8539,24 +8651,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[407] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f6d,
+ .class_hid = BNXT_ULP_CLASS_HID_b48e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 23623633920,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3759410176,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8564,23 +8676,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[408] = {
- .class_hid = BNXT_ULP_CLASS_HID_5f75,
+ .class_hid = BNXT_ULP_CLASS_HID_8e8a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 23623642112,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3759418368,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8588,24 +8700,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[409] = {
- .class_hid = BNXT_ULP_CLASS_HID_3d69,
+ .class_hid = BNXT_ULP_CLASS_HID_db02,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 23625731072,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3761507328,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8613,24 +8725,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[410] = {
- .class_hid = BNXT_ULP_CLASS_HID_6f71,
+ .class_hid = BNXT_ULP_CLASS_HID_dd8e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 23625739264,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3761515520,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8638,25 +8750,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
- },
- [411] = {
- .class_hid = BNXT_ULP_CLASS_HID_0dbd,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ },
+ [411] = {
+ .class_hid = BNXT_ULP_CLASS_HID_819a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 25771117568,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4296281088,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8664,22 +8776,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[412] = {
- .class_hid = BNXT_ULP_CLASS_HID_3f25,
+ .class_hid = BNXT_ULP_CLASS_HID_b31a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 25771125760,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4296289280,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8687,23 +8798,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[413] = {
- .class_hid = BNXT_ULP_CLASS_HID_1239,
+ .class_hid = BNXT_ULP_CLASS_HID_d03e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 25773214720,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4298378240,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8711,23 +8821,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[414] = {
- .class_hid = BNXT_ULP_CLASS_HID_4da1,
+ .class_hid = BNXT_ULP_CLASS_HID_c1be,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 25773222912,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4298386432,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8735,24 +8844,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[415] = {
- .class_hid = BNXT_ULP_CLASS_HID_153d,
+ .class_hid = BNXT_ULP_CLASS_HID_890e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 27918601216,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4833152000,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8760,23 +8868,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[416] = {
- .class_hid = BNXT_ULP_CLASS_HID_45a5,
+ .class_hid = BNXT_ULP_CLASS_HID_ba8e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 27918609408,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4833160192,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8784,24 +8891,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[417] = {
- .class_hid = BNXT_ULP_CLASS_HID_3bb9,
+ .class_hid = BNXT_ULP_CLASS_HID_dfaa,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 27920698368,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4835249152,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8809,24 +8915,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[418] = {
- .class_hid = BNXT_ULP_CLASS_HID_55a1,
+ .class_hid = BNXT_ULP_CLASS_HID_c93a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 27920706560,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4835257344,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8834,25 +8939,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[419] = {
- .class_hid = BNXT_ULP_CLASS_HID_193d,
+ .class_hid = BNXT_ULP_CLASS_HID_b11a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 30066084864,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5370022912,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8860,23 +8964,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[420] = {
- .class_hid = BNXT_ULP_CLASS_HID_4b25,
+ .class_hid = BNXT_ULP_CLASS_HID_8b4e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 30066093056,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5370031104,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8884,24 +8987,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[421] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e39,
+ .class_hid = BNXT_ULP_CLASS_HID_c79e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 30068182016,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5372120064,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8909,24 +9011,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[422] = {
- .class_hid = BNXT_ULP_CLASS_HID_5921,
+ .class_hid = BNXT_ULP_CLASS_HID_d9da,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 30068190208,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5372128256,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8934,25 +9035,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[423] = {
- .class_hid = BNXT_ULP_CLASS_HID_213d,
+ .class_hid = BNXT_ULP_CLASS_HID_b88e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 32213568512,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5906893824,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8960,24 +9060,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[424] = {
- .class_hid = BNXT_ULP_CLASS_HID_5125,
+ .class_hid = BNXT_ULP_CLASS_HID_ea0e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 32213576704,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5906902016,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8985,25 +9084,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[425] = {
- .class_hid = BNXT_ULP_CLASS_HID_3739,
+ .class_hid = BNXT_ULP_CLASS_HID_cf0a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 32215665664,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5908990976,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -9011,25 +9109,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[426] = {
- .class_hid = BNXT_ULP_CLASS_HID_093d,
+ .class_hid = BNXT_ULP_CLASS_HID_c18e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 32215673856,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5908999168,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -9037,25 +9134,3496 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [427] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a94a,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6443764736,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [428] = {
+ .class_hid = BNXT_ULP_CLASS_HID_daca,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6443772928,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [429] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ffee,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6445861888,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [430] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e96e,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6445870080,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [431] = {
+ .class_hid = BNXT_ULP_CLASS_HID_910e,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6980635648,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [432] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c28e,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6980643840,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [433] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e7aa,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6982732800,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [434] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d12a,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6982740992,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [435] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d8ca,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 7517506560,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [436] = {
+ .class_hid = BNXT_ULP_CLASS_HID_930e,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 7517514752,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [437] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ef4e,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 7519603712,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [438] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e18a,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 7519611904,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [439] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c08e,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8054377472,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [440] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9a8a,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8054385664,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [441] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d70a,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8056474624,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [442] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e90e,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8056482816,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [443] = {
+ .class_hid = BNXT_ULP_CLASS_HID_edd9,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1313792,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ },
+ [444] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a61d,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1321984,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ },
+ [445] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c571,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 3410944,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ },
+ [446] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f4f9,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 3419136,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ },
+ [447] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9c45,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2148797440,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [448] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cfcd,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2148805632,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [449] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ed21,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2150894592,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [450] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dca9,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2150902784,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [451] = {
+ .class_hid = BNXT_ULP_CLASS_HID_80b5,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4296281088,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [452] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b235,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4296289280,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [453] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d111,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4298378240,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [454] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c091,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4298386432,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [455] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a865,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6443764736,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [456] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dbe5,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6443772928,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [457] = {
+ .class_hid = BNXT_ULP_CLASS_HID_fec1,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6445861888,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [458] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e841,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6445870080,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [459] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8e85,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 8591248384,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [460] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b80d,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 8591256576,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [461] = {
+ .class_hid = BNXT_ULP_CLASS_HID_df65,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 8593345536,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [462] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ceed,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 8593353728,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [463] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9645,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 10738732032,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [464] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1cd,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 10738740224,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [465] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e725,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 10740829184,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [466] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d6ad,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 10740837376,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [467] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9aa5,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 12886215680,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [468] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b425,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 12886223872,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [469] = {
+ .class_hid = BNXT_ULP_CLASS_HID_eb05,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 12888312832,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [470] = {
+ .class_hid = BNXT_ULP_CLASS_HID_da85,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 12888321024,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [471] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a265,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 15033699328,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [472] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dde5,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 15033707520,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [473] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f0c5,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 15035796480,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [474] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e245,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 15035804672,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [475] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8b8f,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 17181182976,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [476] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a517,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 17181191168,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [477] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d86b,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 17183280128,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [478] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cbf3,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 17183288320,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [479] = {
+ .class_hid = BNXT_ULP_CLASS_HID_934f,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 19328666624,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [480] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c2c7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 19328674816,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [481] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e02b,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 19330763776,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [482] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d3a3,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 19330771968,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [483] = {
+ .class_hid = BNXT_ULP_CLASS_HID_87a7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 21476150272,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [484] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b137,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 21476158464,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [485] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d403,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 21478247424,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [486] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c793,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 21478255616,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [487] = {
+ .class_hid = BNXT_ULP_CLASS_HID_af67,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 23623633920,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [488] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dee7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 23623642112,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [489] = {
+ .class_hid = BNXT_ULP_CLASS_HID_fdc3,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 23625731072,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [490] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ef43,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 23625739264,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [491] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8dbf,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 25771117568,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [492] = {
+ .class_hid = BNXT_ULP_CLASS_HID_bf07,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 25771125760,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [493] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d21f,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 25773214720,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [494] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cde7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 25773222912,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [495] = {
+ .class_hid = BNXT_ULP_CLASS_HID_956f,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 27918601216,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [496] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c4c7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 27918609408,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [497] = {
+ .class_hid = BNXT_ULP_CLASS_HID_fbcf,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 27920698368,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [498] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d5a7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 27920706560,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [499] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9957,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 30066084864,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [500] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cb27,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 30066093056,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [501] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ee37,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 30068182016,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [502] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d987,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 30068190208,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [503] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a107,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 32213568512,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [504] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d0e7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 32213576704,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [505] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f7e7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 32215665664,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [506] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c827,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 32215673856,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [507] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f76a,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1313792,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC }
+ },
+ [508] = {
+ .class_hid = BNXT_ULP_CLASS_HID_bcae,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1321984,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC }
+ },
+ [509] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dfc2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3410944,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC }
+ },
+ [510] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ee4a,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3419136,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC }
+ },
+ [511] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cf26,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 538184704,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [512] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b53a,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 538192896,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [513] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d79e,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 540281856,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [514] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e606,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 540290048,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [515] = {
+ .class_hid = BNXT_ULP_CLASS_HID_be86,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1075055616,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [516] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cd0e,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1075063808,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [517] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d042,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1077152768,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [518] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d586,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1077160960,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [519] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b712,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1611926528,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [520] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c59a,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1611934720,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [521] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e81e,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1614023680,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [522] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f686,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1614031872,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [523] = {
+ .class_hid = BNXT_ULP_CLASS_HID_86f6,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2148797440,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [524] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d57e,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2148805632,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [525] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f792,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2150894592,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [526] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c61a,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2150902784,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [527] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9eb2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2685668352,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [528] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ad3a,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2685676544,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [529] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f01e,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2687765504,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [530] = {
+ .class_hid = BNXT_ULP_CLASS_HID_de96,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2687773696,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [531] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d756,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3222539264,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [532] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9c9a,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3222547456,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [533] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c812,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3224636416,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [534] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ce56,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3224644608,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [535] = {
+ .class_hid = BNXT_ULP_CLASS_HID_af12,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3759410176,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [536] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9516,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3759418368,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [537] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c09e,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3761507328,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [538] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c612,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3761515520,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [539] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9a06,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4296281088,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [540] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a886,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4296289280,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [541] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cba2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4298378240,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [542] = {
+ .class_hid = BNXT_ULP_CLASS_HID_da22,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4298386432,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [543] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9292,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4833152000,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [544] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a112,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4833160192,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [545] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c436,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4835249152,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [546] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d2a6,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4835257344,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [547] = {
+ .class_hid = BNXT_ULP_CLASS_HID_aa86,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5370022912,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [548] = {
+ .class_hid = BNXT_ULP_CLASS_HID_90d2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5370031104,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [549] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dc02,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5372120064,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [550] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c246,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5372128256,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [551] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a312,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5906893824,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [552] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f192,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5906902016,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [553] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d496,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5908990976,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [554] = {
+ .class_hid = BNXT_ULP_CLASS_HID_da12,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5908999168,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [555] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b2d6,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6443764736,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [556] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c156,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6443772928,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [557] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e472,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6445861888,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [558] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f2f2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6445870080,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [559] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8a92,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6980635648,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [560] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d912,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6980643840,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [561] = {
+ .class_hid = BNXT_ULP_CLASS_HID_fc36,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6982732800,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [562] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cab6,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6982740992,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [563] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c356,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 7517506560,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [564] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8892,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 7517514752,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [565] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f4d2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 7519603712,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [566] = {
+ .class_hid = BNXT_ULP_CLASS_HID_fa16,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 7519611904,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [567] = {
+ .class_hid = BNXT_ULP_CLASS_HID_db12,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 8054377472,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [568] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8116,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 8054385664,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [569] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cc96,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 8056474624,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [570] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f292,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 8056482816,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
},
- [427] = {
- .class_hid = BNXT_ULP_CLASS_HID_684d,
+ [571] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e84d,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 1313792,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9068,15 +12636,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC }
},
- [428] = {
- .class_hid = BNXT_ULP_CLASS_HID_2389,
+ [572] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a389,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 1321984,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9089,16 +12657,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC }
},
- [429] = {
- .class_hid = BNXT_ULP_CLASS_HID_00e5,
+ [573] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c0e5,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 3410944,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9111,16 +12679,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC }
},
- [430] = {
- .class_hid = BNXT_ULP_CLASS_HID_316d,
+ [574] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f16d,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 3419136,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9133,17 +12701,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC }
},
- [431] = {
- .class_hid = BNXT_ULP_CLASS_HID_18c1,
+ [575] = {
+ .class_hid = BNXT_ULP_CLASS_HID_99d1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 2148797440,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9156,16 +12724,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
},
- [432] = {
- .class_hid = BNXT_ULP_CLASS_HID_4a49,
+ [576] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ca59,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 2148805632,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9178,17 +12746,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
},
- [433] = {
- .class_hid = BNXT_ULP_CLASS_HID_28a5,
+ [577] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e8b5,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 2150894592,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9201,17 +12769,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
},
- [434] = {
- .class_hid = BNXT_ULP_CLASS_HID_582d,
+ [578] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d93d,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 2150902784,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9224,18 +12792,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
},
- [435] = {
- .class_hid = BNXT_ULP_CLASS_HID_05a1,
+ [579] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8521,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 4296281088,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9248,16 +12816,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [436] = {
- .class_hid = BNXT_ULP_CLASS_HID_37a9,
+ [580] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b7a1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 4296289280,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9270,17 +12838,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [437] = {
- .class_hid = BNXT_ULP_CLASS_HID_1485,
+ [581] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d485,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 4298378240,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9293,17 +12861,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [438] = {
- .class_hid = BNXT_ULP_CLASS_HID_458d,
+ [582] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c505,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 4298386432,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9316,18 +12884,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [439] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ce1,
+ [583] = {
+ .class_hid = BNXT_ULP_CLASS_HID_adf1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 6443764736,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9340,17 +12908,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [440] = {
- .class_hid = BNXT_ULP_CLASS_HID_5ee9,
+ [584] = {
+ .class_hid = BNXT_ULP_CLASS_HID_de71,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 6443772928,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9363,18 +12931,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [441] = {
- .class_hid = BNXT_ULP_CLASS_HID_3ac5,
+ [585] = {
+ .class_hid = BNXT_ULP_CLASS_HID_fb55,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 6445861888,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9387,18 +12955,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [442] = {
- .class_hid = BNXT_ULP_CLASS_HID_6ccd,
+ [586] = {
+ .class_hid = BNXT_ULP_CLASS_HID_edd5,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 6445870080,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9411,19 +12979,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [443] = {
- .class_hid = BNXT_ULP_CLASS_HID_0b11,
+ [587] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8b11,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 8591248384,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9436,16 +13004,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [444] = {
- .class_hid = BNXT_ULP_CLASS_HID_3d99,
+ [588] = {
+ .class_hid = BNXT_ULP_CLASS_HID_bd99,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 8591256576,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9458,17 +13026,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [445] = {
- .class_hid = BNXT_ULP_CLASS_HID_1ab5,
+ [589] = {
+ .class_hid = BNXT_ULP_CLASS_HID_daf1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 8593345536,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9481,17 +13049,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [446] = {
- .class_hid = BNXT_ULP_CLASS_HID_4b3d,
+ [590] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cb79,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 8593353728,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9504,18 +13072,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [447] = {
- .class_hid = BNXT_ULP_CLASS_HID_1291,
+ [591] = {
+ .class_hid = BNXT_ULP_CLASS_HID_93d1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 10738732032,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9528,17 +13096,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [448] = {
- .class_hid = BNXT_ULP_CLASS_HID_4419,
+ [592] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c459,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 10738740224,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9551,18 +13119,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [449] = {
- .class_hid = BNXT_ULP_CLASS_HID_22b5,
+ [593] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e2b1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 10740829184,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9575,18 +13143,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [450] = {
- .class_hid = BNXT_ULP_CLASS_HID_523d,
+ [594] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d339,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 10740837376,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9599,19 +13167,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [451] = {
- .class_hid = BNXT_ULP_CLASS_HID_1fb1,
+ [595] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9f31,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 12886215680,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9624,17 +13192,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [452] = {
- .class_hid = BNXT_ULP_CLASS_HID_31b9,
+ [596] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b1b1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 12886223872,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9647,18 +13215,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [453] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e95,
+ [597] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ee91,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 12888312832,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9671,18 +13239,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [454] = {
- .class_hid = BNXT_ULP_CLASS_HID_5f9d,
+ [598] = {
+ .class_hid = BNXT_ULP_CLASS_HID_df11,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 12888321024,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9695,19 +13263,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [455] = {
- .class_hid = BNXT_ULP_CLASS_HID_26b1,
+ [599] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a7f1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 15033699328,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9720,18 +13288,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [456] = {
- .class_hid = BNXT_ULP_CLASS_HID_58b9,
+ [600] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d871,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 15033707520,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9744,19 +13312,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [457] = {
- .class_hid = BNXT_ULP_CLASS_HID_3495,
+ [601] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f551,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 15035796480,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9769,19 +13337,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [458] = {
- .class_hid = BNXT_ULP_CLASS_HID_669d,
+ [602] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e7d1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 15035804672,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9794,20 +13362,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [459] = {
- .class_hid = BNXT_ULP_CLASS_HID_0e39,
+ [603] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8e1b,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 17181182976,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9820,16 +13388,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [460] = {
- .class_hid = BNXT_ULP_CLASS_HID_20a1,
+ [604] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a083,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 17181191168,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9842,17 +13410,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [461] = {
- .class_hid = BNXT_ULP_CLASS_HID_1dfd,
+ [605] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ddff,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 17183280128,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9865,17 +13433,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [462] = {
- .class_hid = BNXT_ULP_CLASS_HID_4e65,
+ [606] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ce67,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 17183288320,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9888,18 +13456,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [463] = {
- .class_hid = BNXT_ULP_CLASS_HID_16f9,
+ [607] = {
+ .class_hid = BNXT_ULP_CLASS_HID_96db,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 19328666624,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9912,17 +13480,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [464] = {
- .class_hid = BNXT_ULP_CLASS_HID_4661,
+ [608] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c753,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 19328674816,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9935,18 +13503,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [465] = {
- .class_hid = BNXT_ULP_CLASS_HID_24bd,
+ [609] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e5bf,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 19330763776,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9959,18 +13527,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [466] = {
- .class_hid = BNXT_ULP_CLASS_HID_5625,
+ [610] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d637,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 19330771968,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9983,19 +13551,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [467] = {
- .class_hid = BNXT_ULP_CLASS_HID_02b9,
+ [611] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8233,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 21476150272,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10008,17 +13576,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [468] = {
- .class_hid = BNXT_ULP_CLASS_HID_34a1,
+ [612] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b4a3,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 21476158464,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10031,18 +13599,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [469] = {
- .class_hid = BNXT_ULP_CLASS_HID_11bd,
+ [613] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d197,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 21478247424,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10055,18 +13623,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [470] = {
- .class_hid = BNXT_ULP_CLASS_HID_42a5,
+ [614] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c207,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 21478255616,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10079,19 +13647,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [471] = {
- .class_hid = BNXT_ULP_CLASS_HID_2af9,
+ [615] = {
+ .class_hid = BNXT_ULP_CLASS_HID_aaf3,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 23623633920,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10104,18 +13672,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [472] = {
- .class_hid = BNXT_ULP_CLASS_HID_5ae1,
+ [616] = {
+ .class_hid = BNXT_ULP_CLASS_HID_db73,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 23623642112,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10128,19 +13696,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [473] = {
- .class_hid = BNXT_ULP_CLASS_HID_38fd,
+ [617] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f857,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 23625731072,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10153,19 +13721,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [474] = {
- .class_hid = BNXT_ULP_CLASS_HID_6ae5,
+ [618] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ead7,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 23625739264,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10178,20 +13746,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [475] = {
- .class_hid = BNXT_ULP_CLASS_HID_0829,
+ [619] = {
+ .class_hid = BNXT_ULP_CLASS_HID_882b,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 25771117568,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10204,17 +13772,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [476] = {
- .class_hid = BNXT_ULP_CLASS_HID_3ab1,
+ [620] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ba93,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 25771125760,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10227,18 +13795,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [477] = {
- .class_hid = BNXT_ULP_CLASS_HID_17ad,
+ [621] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d78b,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 25773214720,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10251,18 +13819,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [478] = {
- .class_hid = BNXT_ULP_CLASS_HID_4835,
+ [622] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c873,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 25773222912,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10275,19 +13843,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [479] = {
- .class_hid = BNXT_ULP_CLASS_HID_10a9,
+ [623] = {
+ .class_hid = BNXT_ULP_CLASS_HID_90fb,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 27918601216,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10300,18 +13868,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [480] = {
- .class_hid = BNXT_ULP_CLASS_HID_4031,
+ [624] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c153,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 27918609408,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10324,19 +13892,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [481] = {
- .class_hid = BNXT_ULP_CLASS_HID_3e2d,
+ [625] = {
+ .class_hid = BNXT_ULP_CLASS_HID_fe5b,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 27920698368,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10349,19 +13917,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [482] = {
- .class_hid = BNXT_ULP_CLASS_HID_5035,
+ [626] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d033,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 27920706560,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10374,20 +13942,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [483] = {
- .class_hid = BNXT_ULP_CLASS_HID_1ca9,
+ [627] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9cc3,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 30066084864,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10400,18 +13968,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [484] = {
- .class_hid = BNXT_ULP_CLASS_HID_4eb1,
+ [628] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ceb3,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 30066093056,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10424,19 +13992,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [485] = {
- .class_hid = BNXT_ULP_CLASS_HID_2bad,
+ [629] = {
+ .class_hid = BNXT_ULP_CLASS_HID_eba3,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 30068182016,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10449,19 +14017,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [486] = {
- .class_hid = BNXT_ULP_CLASS_HID_5cb5,
+ [630] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dc13,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 30068190208,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10474,20 +14042,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [487] = {
- .class_hid = BNXT_ULP_CLASS_HID_24a9,
+ [631] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a493,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 32213568512,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10500,19 +14068,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [488] = {
- .class_hid = BNXT_ULP_CLASS_HID_54b1,
+ [632] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d573,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 32213576704,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10525,20 +14093,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [489] = {
- .class_hid = BNXT_ULP_CLASS_HID_32ad,
+ [633] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f273,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 32215665664,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10551,20 +14119,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [490] = {
- .class_hid = BNXT_ULP_CLASS_HID_0ca9,
+ [634] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cdb3,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 32215673856,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10577,21 +14145,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [491] = {
- .class_hid = BNXT_ULP_CLASS_HID_7f35,
+ [635] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ff35,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 1313792,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10604,15 +14172,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC }
},
- [492] = {
- .class_hid = BNXT_ULP_CLASS_HID_34f1,
+ [636] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b4f1,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 1321984,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10625,16 +14193,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC }
},
- [493] = {
- .class_hid = BNXT_ULP_CLASS_HID_179d,
+ [637] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d79d,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 3410944,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10647,16 +14215,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC }
},
- [494] = {
- .class_hid = BNXT_ULP_CLASS_HID_2615,
+ [638] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e615,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 3419136,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10669,17 +14237,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC }
},
- [495] = {
- .class_hid = BNXT_ULP_CLASS_HID_0fb9,
+ [639] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8ea9,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 2148797440,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10692,16 +14260,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
},
- [496] = {
- .class_hid = BNXT_ULP_CLASS_HID_5d31,
+ [640] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dd21,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 2148805632,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10714,17 +14282,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
},
- [497] = {
- .class_hid = BNXT_ULP_CLASS_HID_3fdd,
+ [641] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ffcd,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 2150894592,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10737,17 +14305,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
},
- [498] = {
- .class_hid = BNXT_ULP_CLASS_HID_4f55,
+ [642] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ce45,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 2150902784,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10760,18 +14328,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
},
- [499] = {
- .class_hid = BNXT_ULP_CLASS_HID_12d9,
+ [643] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9259,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 4296281088,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10784,16 +14352,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [500] = {
- .class_hid = BNXT_ULP_CLASS_HID_20d1,
+ [644] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a0d9,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 4296289280,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10806,17 +14374,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [501] = {
- .class_hid = BNXT_ULP_CLASS_HID_03fd,
+ [645] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c3fd,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 4298378240,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10829,17 +14397,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [502] = {
- .class_hid = BNXT_ULP_CLASS_HID_52f5,
+ [646] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d27d,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 4298386432,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10852,18 +14420,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [503] = {
- .class_hid = BNXT_ULP_CLASS_HID_3b99,
+ [647] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ba89,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 6443764736,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10876,17 +14444,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [504] = {
- .class_hid = BNXT_ULP_CLASS_HID_4991,
+ [648] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c909,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 6443772928,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10899,18 +14467,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [505] = {
- .class_hid = BNXT_ULP_CLASS_HID_2dbd,
+ [649] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ec2d,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 6445861888,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10923,18 +14491,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [506] = {
- .class_hid = BNXT_ULP_CLASS_HID_7bb5,
+ [650] = {
+ .class_hid = BNXT_ULP_CLASS_HID_faad,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 6445870080,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10947,16 +14515,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [507] = {
+ [651] = {
.class_hid = BNXT_ULP_CLASS_HID_34c6,
.class_tid = 3,
.hdr_sig_id = 0,
@@ -10971,7 +14539,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [508] = {
+ [652] = {
.class_hid = BNXT_ULP_CLASS_HID_0c22,
.class_tid = 3,
.hdr_sig_id = 0,
@@ -10987,7 +14555,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [509] = {
+ [653] = {
.class_hid = BNXT_ULP_CLASS_HID_1cbe,
.class_tid = 3,
.hdr_sig_id = 0,
@@ -11003,7 +14571,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [510] = {
+ [654] = {
.class_hid = BNXT_ULP_CLASS_HID_179a,
.class_tid = 3,
.hdr_sig_id = 0,
@@ -11020,7 +14588,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [511] = {
+ [655] = {
.class_hid = BNXT_ULP_CLASS_HID_59be,
.class_tid = 3,
.hdr_sig_id = 1,
@@ -11035,7 +14603,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [512] = {
+ [656] = {
.class_hid = BNXT_ULP_CLASS_HID_515a,
.class_tid = 3,
.hdr_sig_id = 1,
@@ -11051,7 +14619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [513] = {
+ [657] = {
.class_hid = BNXT_ULP_CLASS_HID_1c72,
.class_tid = 3,
.hdr_sig_id = 1,
@@ -11067,7 +14635,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [514] = {
+ [658] = {
.class_hid = BNXT_ULP_CLASS_HID_171e,
.class_tid = 3,
.hdr_sig_id = 1,
@@ -11084,7 +14652,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [515] = {
+ [659] = {
.class_hid = BNXT_ULP_CLASS_HID_19c8,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11100,7 +14668,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [516] = {
+ [660] = {
.class_hid = BNXT_ULP_CLASS_HID_112c,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11117,7 +14685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [517] = {
+ [661] = {
.class_hid = BNXT_ULP_CLASS_HID_4d68,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11134,7 +14702,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [518] = {
+ [662] = {
.class_hid = BNXT_ULP_CLASS_HID_444c,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11152,7 +14720,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [519] = {
+ [663] = {
.class_hid = BNXT_ULP_CLASS_HID_0e8c,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11169,7 +14737,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [520] = {
+ [664] = {
.class_hid = BNXT_ULP_CLASS_HID_09e0,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11187,7 +14755,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [521] = {
+ [665] = {
.class_hid = BNXT_ULP_CLASS_HID_1af0,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11205,7 +14773,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [522] = {
+ [666] = {
.class_hid = BNXT_ULP_CLASS_HID_15d4,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11224,7 +14792,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [523] = {
+ [667] = {
.class_hid = BNXT_ULP_CLASS_HID_1dd0,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11240,7 +14808,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [524] = {
+ [668] = {
.class_hid = BNXT_ULP_CLASS_HID_14f4,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11257,7 +14825,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [525] = {
+ [669] = {
.class_hid = BNXT_ULP_CLASS_HID_70b0,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11274,7 +14842,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [526] = {
+ [670] = {
.class_hid = BNXT_ULP_CLASS_HID_4854,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11292,7 +14860,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [527] = {
+ [671] = {
.class_hid = BNXT_ULP_CLASS_HID_3dd4,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11309,7 +14877,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [528] = {
+ [672] = {
.class_hid = BNXT_ULP_CLASS_HID_34f8,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11327,7 +14895,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [529] = {
+ [673] = {
.class_hid = BNXT_ULP_CLASS_HID_09e8,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11345,7 +14913,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [530] = {
+ [674] = {
.class_hid = BNXT_ULP_CLASS_HID_008c,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11364,7 +14932,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [531] = {
+ [675] = {
.class_hid = BNXT_ULP_CLASS_HID_34e6,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11380,7 +14948,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [532] = {
+ [676] = {
.class_hid = BNXT_ULP_CLASS_HID_0c02,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11397,7 +14965,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [533] = {
+ [677] = {
.class_hid = BNXT_ULP_CLASS_HID_1c9e,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11414,7 +14982,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [534] = {
+ [678] = {
.class_hid = BNXT_ULP_CLASS_HID_17ba,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11432,7 +15000,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [535] = {
+ [679] = {
.class_hid = BNXT_ULP_CLASS_HID_429e,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11449,7 +15017,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [536] = {
+ [680] = {
.class_hid = BNXT_ULP_CLASS_HID_5dba,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11467,7 +15035,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [537] = {
+ [681] = {
.class_hid = BNXT_ULP_CLASS_HID_2a16,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11485,7 +15053,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [538] = {
+ [682] = {
.class_hid = BNXT_ULP_CLASS_HID_2532,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11504,7 +15072,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [539] = {
+ [683] = {
.class_hid = BNXT_ULP_CLASS_HID_2da2,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11521,7 +15089,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [540] = {
+ [684] = {
.class_hid = BNXT_ULP_CLASS_HID_24fe,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11539,7 +15107,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [541] = {
+ [685] = {
.class_hid = BNXT_ULP_CLASS_HID_355a,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11557,7 +15125,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [542] = {
+ [686] = {
.class_hid = BNXT_ULP_CLASS_HID_0c76,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11576,7 +15144,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [543] = {
+ [687] = {
.class_hid = BNXT_ULP_CLASS_HID_13e6,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11594,7 +15162,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [544] = {
+ [688] = {
.class_hid = BNXT_ULP_CLASS_HID_7276,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11613,7 +15181,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [545] = {
+ [689] = {
.class_hid = BNXT_ULP_CLASS_HID_42d2,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11632,7 +15200,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [546] = {
+ [690] = {
.class_hid = BNXT_ULP_CLASS_HID_5dee,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11652,7 +15220,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [547] = {
+ [691] = {
.class_hid = BNXT_ULP_CLASS_HID_59de,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11668,7 +15236,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [548] = {
+ [692] = {
.class_hid = BNXT_ULP_CLASS_HID_513a,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11685,7 +15253,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [549] = {
+ [693] = {
.class_hid = BNXT_ULP_CLASS_HID_1c12,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11702,7 +15270,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [550] = {
+ [694] = {
.class_hid = BNXT_ULP_CLASS_HID_177e,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11720,7 +15288,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [551] = {
+ [695] = {
.class_hid = BNXT_ULP_CLASS_HID_0e92,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11737,7 +15305,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [552] = {
+ [696] = {
.class_hid = BNXT_ULP_CLASS_HID_09fe,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11755,7 +15323,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [553] = {
+ [697] = {
.class_hid = BNXT_ULP_CLASS_HID_5c1a,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11773,7 +15341,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [554] = {
+ [698] = {
.class_hid = BNXT_ULP_CLASS_HID_5746,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11792,7 +15360,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [555] = {
+ [699] = {
.class_hid = BNXT_ULP_CLASS_HID_79da,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11809,7 +15377,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [556] = {
+ [700] = {
.class_hid = BNXT_ULP_CLASS_HID_7106,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11827,7 +15395,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [557] = {
+ [701] = {
.class_hid = BNXT_ULP_CLASS_HID_3c1e,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11845,7 +15413,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [558] = {
+ [702] = {
.class_hid = BNXT_ULP_CLASS_HID_377a,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11864,7 +15432,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [559] = {
+ [703] = {
.class_hid = BNXT_ULP_CLASS_HID_2e9e,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11882,7 +15450,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [560] = {
+ [704] = {
.class_hid = BNXT_ULP_CLASS_HID_29fa,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11901,7 +15469,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [561] = {
+ [705] = {
.class_hid = BNXT_ULP_CLASS_HID_14d2,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11920,7 +15488,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [562] = {
+ [706] = {
.class_hid = BNXT_ULP_CLASS_HID_7742,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11940,7 +15508,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [563] = {
+ [707] = {
.class_hid = BNXT_ULP_CLASS_HID_3706,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -11956,7 +15524,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [564] = {
+ [708] = {
.class_hid = BNXT_ULP_CLASS_HID_0fe2,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -11973,7 +15541,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [565] = {
+ [709] = {
.class_hid = BNXT_ULP_CLASS_HID_1f7e,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -11990,7 +15558,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [566] = {
+ [710] = {
.class_hid = BNXT_ULP_CLASS_HID_145a,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12008,7 +15576,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [567] = {
+ [711] = {
.class_hid = BNXT_ULP_CLASS_HID_417e,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12025,7 +15593,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [568] = {
+ [712] = {
.class_hid = BNXT_ULP_CLASS_HID_5e5a,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12043,7 +15611,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [569] = {
+ [713] = {
.class_hid = BNXT_ULP_CLASS_HID_29f6,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12061,7 +15629,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [570] = {
+ [714] = {
.class_hid = BNXT_ULP_CLASS_HID_26d2,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12080,7 +15648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [571] = {
+ [715] = {
.class_hid = BNXT_ULP_CLASS_HID_2e42,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12097,7 +15665,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [572] = {
+ [716] = {
.class_hid = BNXT_ULP_CLASS_HID_271e,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12115,7 +15683,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [573] = {
+ [717] = {
.class_hid = BNXT_ULP_CLASS_HID_36ba,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12133,7 +15701,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [574] = {
+ [718] = {
.class_hid = BNXT_ULP_CLASS_HID_0f96,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12152,7 +15720,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [575] = {
+ [719] = {
.class_hid = BNXT_ULP_CLASS_HID_1006,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12170,7 +15738,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [576] = {
+ [720] = {
.class_hid = BNXT_ULP_CLASS_HID_7196,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12189,7 +15757,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [577] = {
+ [721] = {
.class_hid = BNXT_ULP_CLASS_HID_4132,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12208,7 +15776,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [578] = {
+ [722] = {
.class_hid = BNXT_ULP_CLASS_HID_5e0e,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12228,7 +15796,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [579] = {
+ [723] = {
.class_hid = BNXT_ULP_CLASS_HID_59fe,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12244,7 +15812,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [580] = {
+ [724] = {
.class_hid = BNXT_ULP_CLASS_HID_511a,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12261,7 +15829,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [581] = {
+ [725] = {
.class_hid = BNXT_ULP_CLASS_HID_1c32,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12278,7 +15846,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [582] = {
+ [726] = {
.class_hid = BNXT_ULP_CLASS_HID_175e,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12296,7 +15864,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [583] = {
+ [727] = {
.class_hid = BNXT_ULP_CLASS_HID_0eb2,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12313,7 +15881,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [584] = {
+ [728] = {
.class_hid = BNXT_ULP_CLASS_HID_09de,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12331,7 +15899,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [585] = {
+ [729] = {
.class_hid = BNXT_ULP_CLASS_HID_5c3a,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12349,7 +15917,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [586] = {
+ [730] = {
.class_hid = BNXT_ULP_CLASS_HID_5766,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12368,7 +15936,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [587] = {
+ [731] = {
.class_hid = BNXT_ULP_CLASS_HID_79fa,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12385,7 +15953,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [588] = {
+ [732] = {
.class_hid = BNXT_ULP_CLASS_HID_7126,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12403,7 +15971,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [589] = {
+ [733] = {
.class_hid = BNXT_ULP_CLASS_HID_3c3e,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12421,7 +15989,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [590] = {
+ [734] = {
.class_hid = BNXT_ULP_CLASS_HID_375a,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12440,7 +16008,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [591] = {
+ [735] = {
.class_hid = BNXT_ULP_CLASS_HID_2ebe,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12458,7 +16026,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [592] = {
+ [736] = {
.class_hid = BNXT_ULP_CLASS_HID_29da,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12477,7 +16045,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [593] = {
+ [737] = {
.class_hid = BNXT_ULP_CLASS_HID_14f2,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12496,7 +16064,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [594] = {
+ [738] = {
.class_hid = BNXT_ULP_CLASS_HID_7762,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12516,7 +16084,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [595] = {
+ [739] = {
.class_hid = BNXT_ULP_CLASS_HID_19e8,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12533,7 +16101,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [596] = {
+ [740] = {
.class_hid = BNXT_ULP_CLASS_HID_110c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12551,7 +16119,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [597] = {
+ [741] = {
.class_hid = BNXT_ULP_CLASS_HID_4d48,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12569,7 +16137,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [598] = {
+ [742] = {
.class_hid = BNXT_ULP_CLASS_HID_446c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12588,7 +16156,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [599] = {
+ [743] = {
.class_hid = BNXT_ULP_CLASS_HID_0eac,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12606,7 +16174,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [600] = {
+ [744] = {
.class_hid = BNXT_ULP_CLASS_HID_09c0,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12625,7 +16193,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [601] = {
+ [745] = {
.class_hid = BNXT_ULP_CLASS_HID_1ad0,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12644,7 +16212,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [602] = {
+ [746] = {
.class_hid = BNXT_ULP_CLASS_HID_15f4,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12664,7 +16232,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [603] = {
+ [747] = {
.class_hid = BNXT_ULP_CLASS_HID_39ec,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12682,7 +16250,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [604] = {
+ [748] = {
.class_hid = BNXT_ULP_CLASS_HID_3100,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12701,7 +16269,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [605] = {
+ [749] = {
.class_hid = BNXT_ULP_CLASS_HID_0210,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12720,7 +16288,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [606] = {
+ [750] = {
.class_hid = BNXT_ULP_CLASS_HID_1d34,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12740,7 +16308,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [607] = {
+ [751] = {
.class_hid = BNXT_ULP_CLASS_HID_2ea0,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12759,7 +16327,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [608] = {
+ [752] = {
.class_hid = BNXT_ULP_CLASS_HID_29c4,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12779,7 +16347,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [609] = {
+ [753] = {
.class_hid = BNXT_ULP_CLASS_HID_3ad4,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12799,7 +16367,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [610] = {
+ [754] = {
.class_hid = BNXT_ULP_CLASS_HID_35e8,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12820,7 +16388,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [611] = {
+ [755] = {
.class_hid = BNXT_ULP_CLASS_HID_5d80,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12838,7 +16406,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [612] = {
+ [756] = {
.class_hid = BNXT_ULP_CLASS_HID_54a4,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12857,7 +16425,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [613] = {
+ [757] = {
.class_hid = BNXT_ULP_CLASS_HID_29b4,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12876,7 +16444,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [614] = {
+ [758] = {
.class_hid = BNXT_ULP_CLASS_HID_20c8,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12896,7 +16464,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [615] = {
+ [759] = {
.class_hid = BNXT_ULP_CLASS_HID_7244,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12915,7 +16483,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [616] = {
+ [760] = {
.class_hid = BNXT_ULP_CLASS_HID_4d98,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12935,7 +16503,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [617] = {
+ [761] = {
.class_hid = BNXT_ULP_CLASS_HID_5e68,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12955,7 +16523,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [618] = {
+ [762] = {
.class_hid = BNXT_ULP_CLASS_HID_598c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12976,7 +16544,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [619] = {
+ [763] = {
.class_hid = BNXT_ULP_CLASS_HID_1248,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12995,7 +16563,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [620] = {
+ [764] = {
.class_hid = BNXT_ULP_CLASS_HID_74d8,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -13015,7 +16583,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [621] = {
+ [765] = {
.class_hid = BNXT_ULP_CLASS_HID_49a8,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -13035,7 +16603,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [622] = {
+ [766] = {
.class_hid = BNXT_ULP_CLASS_HID_40cc,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -13056,7 +16624,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [623] = {
+ [767] = {
.class_hid = BNXT_ULP_CLASS_HID_0b0c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -13076,7 +16644,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [624] = {
+ [768] = {
.class_hid = BNXT_ULP_CLASS_HID_0220,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -13097,7 +16665,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [625] = {
+ [769] = {
.class_hid = BNXT_ULP_CLASS_HID_1730,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -13118,7 +16686,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [626] = {
+ [770] = {
.class_hid = BNXT_ULP_CLASS_HID_7980,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -13140,7 +16708,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [627] = {
+ [771] = {
.class_hid = BNXT_ULP_CLASS_HID_1db0,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13157,7 +16725,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [628] = {
+ [772] = {
.class_hid = BNXT_ULP_CLASS_HID_1494,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13175,7 +16743,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [629] = {
+ [773] = {
.class_hid = BNXT_ULP_CLASS_HID_70d0,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13193,7 +16761,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [630] = {
+ [774] = {
.class_hid = BNXT_ULP_CLASS_HID_4834,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13212,7 +16780,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [631] = {
+ [775] = {
.class_hid = BNXT_ULP_CLASS_HID_3db4,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13230,7 +16798,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [632] = {
+ [776] = {
.class_hid = BNXT_ULP_CLASS_HID_3498,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13249,7 +16817,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [633] = {
+ [777] = {
.class_hid = BNXT_ULP_CLASS_HID_0988,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13268,7 +16836,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [634] = {
+ [778] = {
.class_hid = BNXT_ULP_CLASS_HID_00ec,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13288,7 +16856,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [635] = {
+ [779] = {
.class_hid = BNXT_ULP_CLASS_HID_3f44,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13306,7 +16874,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [636] = {
+ [780] = {
.class_hid = BNXT_ULP_CLASS_HID_36a8,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13325,7 +16893,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [637] = {
+ [781] = {
.class_hid = BNXT_ULP_CLASS_HID_0b58,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13344,7 +16912,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [638] = {
+ [782] = {
.class_hid = BNXT_ULP_CLASS_HID_02bc,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13364,7 +16932,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [639] = {
+ [783] = {
.class_hid = BNXT_ULP_CLASS_HID_5f48,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13383,7 +16951,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [640] = {
+ [784] = {
.class_hid = BNXT_ULP_CLASS_HID_56ac,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13403,7 +16971,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [641] = {
+ [785] = {
.class_hid = BNXT_ULP_CLASS_HID_2b5c,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13423,7 +16991,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [642] = {
+ [786] = {
.class_hid = BNXT_ULP_CLASS_HID_2280,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13444,7 +17012,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [643] = {
+ [787] = {
.class_hid = BNXT_ULP_CLASS_HID_4000,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13462,7 +17030,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [644] = {
+ [788] = {
.class_hid = BNXT_ULP_CLASS_HID_5b64,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13481,7 +17049,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [645] = {
+ [789] = {
.class_hid = BNXT_ULP_CLASS_HID_2c14,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13500,7 +17068,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [646] = {
+ [790] = {
.class_hid = BNXT_ULP_CLASS_HID_2778,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13520,7 +17088,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [647] = {
+ [791] = {
.class_hid = BNXT_ULP_CLASS_HID_18f8,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13539,7 +17107,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [648] = {
+ [792] = {
.class_hid = BNXT_ULP_CLASS_HID_13dc,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13559,7 +17127,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [649] = {
+ [793] = {
.class_hid = BNXT_ULP_CLASS_HID_4c18,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13579,7 +17147,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [650] = {
+ [794] = {
.class_hid = BNXT_ULP_CLASS_HID_477c,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13600,7 +17168,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [651] = {
+ [795] = {
.class_hid = BNXT_ULP_CLASS_HID_1a88,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13619,7 +17187,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [652] = {
+ [796] = {
.class_hid = BNXT_ULP_CLASS_HID_15ec,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13639,7 +17207,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [653] = {
+ [797] = {
.class_hid = BNXT_ULP_CLASS_HID_4e28,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13659,7 +17227,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [654] = {
+ [798] = {
.class_hid = BNXT_ULP_CLASS_HID_490c,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13680,7 +17248,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [655] = {
+ [799] = {
.class_hid = BNXT_ULP_CLASS_HID_3a8c,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13700,7 +17268,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [656] = {
+ [800] = {
.class_hid = BNXT_ULP_CLASS_HID_35f0,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13721,7 +17289,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [657] = {
+ [801] = {
.class_hid = BNXT_ULP_CLASS_HID_06e0,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13742,7 +17310,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [658] = {
+ [802] = {
.class_hid = BNXT_ULP_CLASS_HID_01c4,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13764,7 +17332,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [659] = {
+ [803] = {
.class_hid = BNXT_ULP_CLASS_HID_1a08,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13781,7 +17349,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [660] = {
+ [804] = {
.class_hid = BNXT_ULP_CLASS_HID_12ec,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13799,7 +17367,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [661] = {
+ [805] = {
.class_hid = BNXT_ULP_CLASS_HID_4ea8,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13817,7 +17385,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [662] = {
+ [806] = {
.class_hid = BNXT_ULP_CLASS_HID_478c,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13836,7 +17404,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [663] = {
+ [807] = {
.class_hid = BNXT_ULP_CLASS_HID_0d4c,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13854,7 +17422,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [664] = {
+ [808] = {
.class_hid = BNXT_ULP_CLASS_HID_0a20,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13873,7 +17441,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [665] = {
+ [809] = {
.class_hid = BNXT_ULP_CLASS_HID_1930,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13892,7 +17460,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [666] = {
+ [810] = {
.class_hid = BNXT_ULP_CLASS_HID_1614,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13912,7 +17480,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [667] = {
+ [811] = {
.class_hid = BNXT_ULP_CLASS_HID_3a0c,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13930,7 +17498,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [668] = {
+ [812] = {
.class_hid = BNXT_ULP_CLASS_HID_32e0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13949,7 +17517,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [669] = {
+ [813] = {
.class_hid = BNXT_ULP_CLASS_HID_01f0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13968,7 +17536,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [670] = {
+ [814] = {
.class_hid = BNXT_ULP_CLASS_HID_1ed4,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13988,7 +17556,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [671] = {
+ [815] = {
.class_hid = BNXT_ULP_CLASS_HID_2d40,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14007,7 +17575,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [672] = {
+ [816] = {
.class_hid = BNXT_ULP_CLASS_HID_2a24,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14027,7 +17595,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [673] = {
+ [817] = {
.class_hid = BNXT_ULP_CLASS_HID_3934,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14047,7 +17615,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [674] = {
+ [818] = {
.class_hid = BNXT_ULP_CLASS_HID_3608,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14068,7 +17636,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [675] = {
+ [819] = {
.class_hid = BNXT_ULP_CLASS_HID_5e60,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14086,7 +17654,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [676] = {
+ [820] = {
.class_hid = BNXT_ULP_CLASS_HID_5744,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14105,7 +17673,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [677] = {
+ [821] = {
.class_hid = BNXT_ULP_CLASS_HID_2a54,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14124,7 +17692,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [678] = {
+ [822] = {
.class_hid = BNXT_ULP_CLASS_HID_2328,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14144,7 +17712,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [679] = {
+ [823] = {
.class_hid = BNXT_ULP_CLASS_HID_71a4,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14163,7 +17731,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [680] = {
+ [824] = {
.class_hid = BNXT_ULP_CLASS_HID_4e78,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14183,7 +17751,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [681] = {
+ [825] = {
.class_hid = BNXT_ULP_CLASS_HID_5d88,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14203,7 +17771,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [682] = {
+ [826] = {
.class_hid = BNXT_ULP_CLASS_HID_5a6c,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14224,7 +17792,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [683] = {
+ [827] = {
.class_hid = BNXT_ULP_CLASS_HID_11a8,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14243,7 +17811,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [684] = {
+ [828] = {
.class_hid = BNXT_ULP_CLASS_HID_7738,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14263,7 +17831,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [685] = {
+ [829] = {
.class_hid = BNXT_ULP_CLASS_HID_4a48,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14283,7 +17851,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [686] = {
+ [830] = {
.class_hid = BNXT_ULP_CLASS_HID_432c,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14304,7 +17872,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [687] = {
+ [831] = {
.class_hid = BNXT_ULP_CLASS_HID_08ec,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14324,7 +17892,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [688] = {
+ [832] = {
.class_hid = BNXT_ULP_CLASS_HID_01c0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14345,7 +17913,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [689] = {
+ [833] = {
.class_hid = BNXT_ULP_CLASS_HID_14d0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14366,7 +17934,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [690] = {
+ [834] = {
.class_hid = BNXT_ULP_CLASS_HID_7a60,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14388,7 +17956,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [691] = {
+ [835] = {
.class_hid = BNXT_ULP_CLASS_HID_1d90,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14405,7 +17973,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [692] = {
+ [836] = {
.class_hid = BNXT_ULP_CLASS_HID_14b4,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14423,7 +17991,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [693] = {
+ [837] = {
.class_hid = BNXT_ULP_CLASS_HID_70f0,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14441,7 +18009,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [694] = {
+ [838] = {
.class_hid = BNXT_ULP_CLASS_HID_4814,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14460,7 +18028,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [695] = {
+ [839] = {
.class_hid = BNXT_ULP_CLASS_HID_3d94,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14478,7 +18046,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [696] = {
+ [840] = {
.class_hid = BNXT_ULP_CLASS_HID_34b8,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14497,7 +18065,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [697] = {
+ [841] = {
.class_hid = BNXT_ULP_CLASS_HID_09a8,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14516,7 +18084,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [698] = {
+ [842] = {
.class_hid = BNXT_ULP_CLASS_HID_00cc,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14536,7 +18104,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [699] = {
+ [843] = {
.class_hid = BNXT_ULP_CLASS_HID_3f64,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14554,7 +18122,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [700] = {
+ [844] = {
.class_hid = BNXT_ULP_CLASS_HID_3688,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14573,7 +18141,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [701] = {
+ [845] = {
.class_hid = BNXT_ULP_CLASS_HID_0b78,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14592,7 +18160,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [702] = {
+ [846] = {
.class_hid = BNXT_ULP_CLASS_HID_029c,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14612,7 +18180,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [703] = {
+ [847] = {
.class_hid = BNXT_ULP_CLASS_HID_5f68,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14631,7 +18199,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [704] = {
+ [848] = {
.class_hid = BNXT_ULP_CLASS_HID_568c,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14651,7 +18219,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [705] = {
+ [849] = {
.class_hid = BNXT_ULP_CLASS_HID_2b7c,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14671,7 +18239,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [706] = {
+ [850] = {
.class_hid = BNXT_ULP_CLASS_HID_22a0,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14692,7 +18260,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [707] = {
+ [851] = {
.class_hid = BNXT_ULP_CLASS_HID_4020,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14710,7 +18278,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [708] = {
+ [852] = {
.class_hid = BNXT_ULP_CLASS_HID_5b44,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14729,7 +18297,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [709] = {
+ [853] = {
.class_hid = BNXT_ULP_CLASS_HID_2c34,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14748,7 +18316,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [710] = {
+ [854] = {
.class_hid = BNXT_ULP_CLASS_HID_2758,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14768,7 +18336,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [711] = {
+ [855] = {
.class_hid = BNXT_ULP_CLASS_HID_18d8,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14787,7 +18355,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [712] = {
+ [856] = {
.class_hid = BNXT_ULP_CLASS_HID_13fc,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14807,7 +18375,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [713] = {
+ [857] = {
.class_hid = BNXT_ULP_CLASS_HID_4c38,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14827,7 +18395,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [714] = {
+ [858] = {
.class_hid = BNXT_ULP_CLASS_HID_475c,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14848,7 +18416,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [715] = {
+ [859] = {
.class_hid = BNXT_ULP_CLASS_HID_1aa8,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14867,7 +18435,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [716] = {
+ [860] = {
.class_hid = BNXT_ULP_CLASS_HID_15cc,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14887,7 +18455,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [717] = {
+ [861] = {
.class_hid = BNXT_ULP_CLASS_HID_4e08,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14907,7 +18475,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [718] = {
+ [862] = {
.class_hid = BNXT_ULP_CLASS_HID_492c,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14928,7 +18496,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [719] = {
+ [863] = {
.class_hid = BNXT_ULP_CLASS_HID_3aac,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14948,7 +18516,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [720] = {
+ [864] = {
.class_hid = BNXT_ULP_CLASS_HID_35d0,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14969,7 +18537,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [721] = {
+ [865] = {
.class_hid = BNXT_ULP_CLASS_HID_06c0,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14990,7 +18558,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [722] = {
+ [866] = {
.class_hid = BNXT_ULP_CLASS_HID_01e4,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -15012,7 +18580,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [723] = {
+ [867] = {
.class_hid = BNXT_ULP_CLASS_HID_4d32,
.class_tid = 3,
.hdr_sig_id = 0,
@@ -15026,7 +18594,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [724] = {
+ [868] = {
.class_hid = BNXT_ULP_CLASS_HID_54aa,
.class_tid = 3,
.hdr_sig_id = 0,
@@ -15041,7 +18609,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [725] = {
+ [869] = {
.class_hid = BNXT_ULP_CLASS_HID_0686,
.class_tid = 3,
.hdr_sig_id = 1,
@@ -15055,7 +18623,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [726] = {
+ [870] = {
.class_hid = BNXT_ULP_CLASS_HID_540e,
.class_tid = 3,
.hdr_sig_id = 1,
@@ -15070,7 +18638,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [727] = {
+ [871] = {
.class_hid = BNXT_ULP_CLASS_HID_2e3c,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -15085,7 +18653,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [728] = {
+ [872] = {
.class_hid = BNXT_ULP_CLASS_HID_3a20,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -15101,7 +18669,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [729] = {
+ [873] = {
.class_hid = BNXT_ULP_CLASS_HID_46f0,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -15117,7 +18685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [730] = {
+ [874] = {
.class_hid = BNXT_ULP_CLASS_HID_52e4,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -15134,7 +18702,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [731] = {
+ [875] = {
.class_hid = BNXT_ULP_CLASS_HID_55e4,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -15149,7 +18717,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [732] = {
+ [876] = {
.class_hid = BNXT_ULP_CLASS_HID_21f8,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -15165,7 +18733,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [733] = {
+ [877] = {
.class_hid = BNXT_ULP_CLASS_HID_75e8,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -15181,7 +18749,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [734] = {
+ [878] = {
.class_hid = BNXT_ULP_CLASS_HID_41fc,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -15198,7 +18766,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [735] = {
+ [879] = {
.class_hid = BNXT_ULP_CLASS_HID_4d12,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15213,7 +18781,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [736] = {
+ [880] = {
.class_hid = BNXT_ULP_CLASS_HID_548a,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15229,7 +18797,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [737] = {
+ [881] = {
.class_hid = BNXT_ULP_CLASS_HID_3356,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15245,7 +18813,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [738] = {
+ [882] = {
.class_hid = BNXT_ULP_CLASS_HID_1ace,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15262,7 +18830,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [739] = {
+ [883] = {
.class_hid = BNXT_ULP_CLASS_HID_1a9a,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15278,7 +18846,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [740] = {
+ [884] = {
.class_hid = BNXT_ULP_CLASS_HID_4d46,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15295,7 +18863,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [741] = {
+ [885] = {
.class_hid = BNXT_ULP_CLASS_HID_2812,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15312,7 +18880,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [742] = {
+ [886] = {
.class_hid = BNXT_ULP_CLASS_HID_338a,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15330,7 +18898,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [743] = {
+ [887] = {
.class_hid = BNXT_ULP_CLASS_HID_06e6,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15345,7 +18913,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [744] = {
+ [888] = {
.class_hid = BNXT_ULP_CLASS_HID_546e,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15361,7 +18929,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [745] = {
+ [889] = {
.class_hid = BNXT_ULP_CLASS_HID_46ee,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15377,7 +18945,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [746] = {
+ [890] = {
.class_hid = BNXT_ULP_CLASS_HID_0d22,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15394,7 +18962,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [747] = {
+ [891] = {
.class_hid = BNXT_ULP_CLASS_HID_26e2,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15410,7 +18978,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [748] = {
+ [892] = {
.class_hid = BNXT_ULP_CLASS_HID_746a,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15427,7 +18995,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [749] = {
+ [893] = {
.class_hid = BNXT_ULP_CLASS_HID_1fa6,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15444,7 +19012,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [750] = {
+ [894] = {
.class_hid = BNXT_ULP_CLASS_HID_2d2e,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15462,7 +19030,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [751] = {
+ [895] = {
.class_hid = BNXT_ULP_CLASS_HID_4ef2,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15477,7 +19045,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [752] = {
+ [896] = {
.class_hid = BNXT_ULP_CLASS_HID_576a,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15493,7 +19061,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [753] = {
+ [897] = {
.class_hid = BNXT_ULP_CLASS_HID_30b6,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15509,7 +19077,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [754] = {
+ [898] = {
.class_hid = BNXT_ULP_CLASS_HID_192e,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15526,7 +19094,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [755] = {
+ [899] = {
.class_hid = BNXT_ULP_CLASS_HID_197a,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15542,7 +19110,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [756] = {
+ [900] = {
.class_hid = BNXT_ULP_CLASS_HID_4ea6,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15559,7 +19127,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [757] = {
+ [901] = {
.class_hid = BNXT_ULP_CLASS_HID_2bf2,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15576,7 +19144,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [758] = {
+ [902] = {
.class_hid = BNXT_ULP_CLASS_HID_306a,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15594,7 +19162,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [759] = {
+ [903] = {
.class_hid = BNXT_ULP_CLASS_HID_06c6,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15609,7 +19177,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [760] = {
+ [904] = {
.class_hid = BNXT_ULP_CLASS_HID_544e,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15625,7 +19193,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [761] = {
+ [905] = {
.class_hid = BNXT_ULP_CLASS_HID_46ce,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15641,7 +19209,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [762] = {
+ [906] = {
.class_hid = BNXT_ULP_CLASS_HID_0d02,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15658,7 +19226,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [763] = {
+ [907] = {
.class_hid = BNXT_ULP_CLASS_HID_26c2,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15674,7 +19242,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [764] = {
+ [908] = {
.class_hid = BNXT_ULP_CLASS_HID_744a,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15691,7 +19259,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [765] = {
+ [909] = {
.class_hid = BNXT_ULP_CLASS_HID_1f86,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15708,7 +19276,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [766] = {
+ [910] = {
.class_hid = BNXT_ULP_CLASS_HID_2d0e,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15726,7 +19294,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [767] = {
+ [911] = {
.class_hid = BNXT_ULP_CLASS_HID_2e1c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15742,7 +19310,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [768] = {
+ [912] = {
.class_hid = BNXT_ULP_CLASS_HID_3a00,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15759,7 +19327,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [769] = {
+ [913] = {
.class_hid = BNXT_ULP_CLASS_HID_46d0,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15776,7 +19344,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [770] = {
+ [914] = {
.class_hid = BNXT_ULP_CLASS_HID_52c4,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15794,7 +19362,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [771] = {
+ [915] = {
.class_hid = BNXT_ULP_CLASS_HID_4e10,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15811,7 +19379,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [772] = {
+ [916] = {
.class_hid = BNXT_ULP_CLASS_HID_5a04,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15829,7 +19397,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [773] = {
+ [917] = {
.class_hid = BNXT_ULP_CLASS_HID_1f98,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15847,7 +19415,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [774] = {
+ [918] = {
.class_hid = BNXT_ULP_CLASS_HID_72f8,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15866,7 +19434,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [775] = {
+ [919] = {
.class_hid = BNXT_ULP_CLASS_HID_0a78,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15883,7 +19451,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [776] = {
+ [920] = {
.class_hid = BNXT_ULP_CLASS_HID_166c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15901,7 +19469,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [777] = {
+ [921] = {
.class_hid = BNXT_ULP_CLASS_HID_233c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15919,7 +19487,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [778] = {
+ [922] = {
.class_hid = BNXT_ULP_CLASS_HID_0f20,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15938,7 +19506,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [779] = {
+ [923] = {
.class_hid = BNXT_ULP_CLASS_HID_2a7c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15956,7 +19524,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [780] = {
+ [924] = {
.class_hid = BNXT_ULP_CLASS_HID_3660,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15975,7 +19543,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [781] = {
+ [925] = {
.class_hid = BNXT_ULP_CLASS_HID_4330,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15994,7 +19562,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [782] = {
+ [926] = {
.class_hid = BNXT_ULP_CLASS_HID_2f24,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -16014,7 +19582,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [783] = {
+ [927] = {
.class_hid = BNXT_ULP_CLASS_HID_5584,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16030,7 +19598,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [784] = {
+ [928] = {
.class_hid = BNXT_ULP_CLASS_HID_2198,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16047,7 +19615,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [785] = {
+ [929] = {
.class_hid = BNXT_ULP_CLASS_HID_7588,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16064,7 +19632,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [786] = {
+ [930] = {
.class_hid = BNXT_ULP_CLASS_HID_419c,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16082,7 +19650,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [787] = {
+ [931] = {
.class_hid = BNXT_ULP_CLASS_HID_7758,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16099,7 +19667,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [788] = {
+ [932] = {
.class_hid = BNXT_ULP_CLASS_HID_43ac,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16117,7 +19685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [789] = {
+ [933] = {
.class_hid = BNXT_ULP_CLASS_HID_0c10,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16135,7 +19703,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [790] = {
+ [934] = {
.class_hid = BNXT_ULP_CLASS_HID_1864,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16154,7 +19722,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [791] = {
+ [935] = {
.class_hid = BNXT_ULP_CLASS_HID_30c8,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16171,7 +19739,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [792] = {
+ [936] = {
.class_hid = BNXT_ULP_CLASS_HID_1cdc,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16189,7 +19757,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [793] = {
+ [937] = {
.class_hid = BNXT_ULP_CLASS_HID_50cc,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16207,7 +19775,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [794] = {
+ [938] = {
.class_hid = BNXT_ULP_CLASS_HID_3d20,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16226,7 +19794,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [795] = {
+ [939] = {
.class_hid = BNXT_ULP_CLASS_HID_529c,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16244,7 +19812,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [796] = {
+ [940] = {
.class_hid = BNXT_ULP_CLASS_HID_3ef0,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16263,7 +19831,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [797] = {
+ [941] = {
.class_hid = BNXT_ULP_CLASS_HID_72e0,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16282,7 +19850,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [798] = {
+ [942] = {
.class_hid = BNXT_ULP_CLASS_HID_5ef4,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16302,7 +19870,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [799] = {
+ [943] = {
.class_hid = BNXT_ULP_CLASS_HID_2dfc,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16318,7 +19886,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [800] = {
+ [944] = {
.class_hid = BNXT_ULP_CLASS_HID_39e0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16335,7 +19903,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [801] = {
+ [945] = {
.class_hid = BNXT_ULP_CLASS_HID_4530,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16352,7 +19920,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [802] = {
+ [946] = {
.class_hid = BNXT_ULP_CLASS_HID_5124,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16370,7 +19938,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [803] = {
+ [947] = {
.class_hid = BNXT_ULP_CLASS_HID_4df0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16387,7 +19955,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [804] = {
+ [948] = {
.class_hid = BNXT_ULP_CLASS_HID_59e4,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16405,7 +19973,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [805] = {
+ [949] = {
.class_hid = BNXT_ULP_CLASS_HID_1c78,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16423,7 +19991,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [806] = {
+ [950] = {
.class_hid = BNXT_ULP_CLASS_HID_7118,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16442,7 +20010,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [807] = {
+ [951] = {
.class_hid = BNXT_ULP_CLASS_HID_0998,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16459,7 +20027,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [808] = {
+ [952] = {
.class_hid = BNXT_ULP_CLASS_HID_158c,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16477,7 +20045,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [809] = {
+ [953] = {
.class_hid = BNXT_ULP_CLASS_HID_20dc,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16495,7 +20063,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [810] = {
+ [954] = {
.class_hid = BNXT_ULP_CLASS_HID_0cc0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16514,7 +20082,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [811] = {
+ [955] = {
.class_hid = BNXT_ULP_CLASS_HID_299c,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16532,7 +20100,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [812] = {
+ [956] = {
.class_hid = BNXT_ULP_CLASS_HID_3580,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16551,7 +20119,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [813] = {
+ [957] = {
.class_hid = BNXT_ULP_CLASS_HID_40d0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16570,7 +20138,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [814] = {
+ [958] = {
.class_hid = BNXT_ULP_CLASS_HID_2cc4,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16590,7 +20158,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [815] = {
+ [959] = {
.class_hid = BNXT_ULP_CLASS_HID_55a4,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16606,7 +20174,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [816] = {
+ [960] = {
.class_hid = BNXT_ULP_CLASS_HID_21b8,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16623,7 +20191,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [817] = {
+ [961] = {
.class_hid = BNXT_ULP_CLASS_HID_75a8,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16640,7 +20208,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [818] = {
+ [962] = {
.class_hid = BNXT_ULP_CLASS_HID_41bc,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16658,7 +20226,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [819] = {
+ [963] = {
.class_hid = BNXT_ULP_CLASS_HID_7778,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16675,7 +20243,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [820] = {
+ [964] = {
.class_hid = BNXT_ULP_CLASS_HID_438c,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16693,7 +20261,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [821] = {
+ [965] = {
.class_hid = BNXT_ULP_CLASS_HID_0c30,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16711,7 +20279,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [822] = {
+ [966] = {
.class_hid = BNXT_ULP_CLASS_HID_1844,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16730,7 +20298,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [823] = {
+ [967] = {
.class_hid = BNXT_ULP_CLASS_HID_30e8,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16747,7 +20315,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [824] = {
+ [968] = {
.class_hid = BNXT_ULP_CLASS_HID_1cfc,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16765,7 +20333,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [825] = {
+ [969] = {
.class_hid = BNXT_ULP_CLASS_HID_50ec,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16783,7 +20351,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [826] = {
+ [970] = {
.class_hid = BNXT_ULP_CLASS_HID_3d00,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16802,7 +20370,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [827] = {
+ [971] = {
.class_hid = BNXT_ULP_CLASS_HID_52bc,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16820,7 +20388,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [828] = {
+ [972] = {
.class_hid = BNXT_ULP_CLASS_HID_3ed0,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16839,7 +20407,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [829] = {
+ [973] = {
.class_hid = BNXT_ULP_CLASS_HID_72c0,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16858,7 +20426,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [830] = {
+ [974] = {
.class_hid = BNXT_ULP_CLASS_HID_5ed4,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16878,7 +20446,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [831] = {
+ [975] = {
.class_hid = BNXT_ULP_CLASS_HID_3866,
.class_tid = 3,
.hdr_sig_id = 0,
@@ -16893,7 +20461,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC }
},
- [832] = {
+ [976] = {
.class_hid = BNXT_ULP_CLASS_HID_381e,
.class_tid = 3,
.hdr_sig_id = 1,
@@ -16908,7 +20476,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC }
},
- [833] = {
+ [977] = {
.class_hid = BNXT_ULP_CLASS_HID_3860,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -16924,7 +20492,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC }
},
- [834] = {
+ [978] = {
.class_hid = BNXT_ULP_CLASS_HID_0454,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -16941,7 +20509,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID }
},
- [835] = {
+ [979] = {
.class_hid = BNXT_ULP_CLASS_HID_3818,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -16957,7 +20525,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC }
},
- [836] = {
+ [980] = {
.class_hid = BNXT_ULP_CLASS_HID_042c,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -16974,7 +20542,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID }
},
- [837] = {
+ [981] = {
.class_hid = BNXT_ULP_CLASS_HID_3846,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -16990,7 +20558,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC }
},
- [838] = {
+ [982] = {
.class_hid = BNXT_ULP_CLASS_HID_387e,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -17006,7 +20574,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC }
},
- [839] = {
+ [983] = {
.class_hid = BNXT_ULP_CLASS_HID_3ba6,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -17022,7 +20590,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC }
},
- [840] = {
+ [984] = {
.class_hid = BNXT_ULP_CLASS_HID_385e,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -17038,7 +20606,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC }
},
- [841] = {
+ [985] = {
.class_hid = BNXT_ULP_CLASS_HID_3840,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -17055,7 +20623,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC }
},
- [842] = {
+ [986] = {
.class_hid = BNXT_ULP_CLASS_HID_0474,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -17073,7 +20641,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID }
},
- [843] = {
+ [987] = {
.class_hid = BNXT_ULP_CLASS_HID_3878,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -17090,7 +20658,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC }
},
- [844] = {
+ [988] = {
.class_hid = BNXT_ULP_CLASS_HID_044c,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -17108,7 +20676,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID }
},
- [845] = {
+ [989] = {
.class_hid = BNXT_ULP_CLASS_HID_3ba0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -17125,7 +20693,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC }
},
- [846] = {
+ [990] = {
.class_hid = BNXT_ULP_CLASS_HID_0794,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -17143,7 +20711,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID }
},
- [847] = {
+ [991] = {
.class_hid = BNXT_ULP_CLASS_HID_3858,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -17160,7 +20728,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC }
},
- [848] = {
+ [992] = {
.class_hid = BNXT_ULP_CLASS_HID_046c,
.class_tid = 3,
.hdr_sig_id = 11,
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
index 84e3d92f41..c016e1940a 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Tue Jul 13 12:36:40 2021 */
+/* date: Fri Aug 20 17:59:14 2021 */
#ifndef ULP_TEMPLATE_DB_H_
#define ULP_TEMPLATE_DB_H_
@@ -11,14 +11,14 @@
#define BNXT_ULP_REGFILE_MAX_SZ 42
#define BNXT_ULP_MAX_NUM_DEVICES 4
#define BNXT_ULP_LOG2_MAX_NUM_DEV 2
-#define BNXT_ULP_GEN_TBL_MAX_SZ 12
-#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 32768
-#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 849
+#define BNXT_ULP_GEN_TBL_MAX_SZ 16
+#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 65536
+#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 993
#define BNXT_ULP_CLASS_HID_LOW_PRIME 6701
#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907
-#define BNXT_ULP_CLASS_HID_SHFTR 24
-#define BNXT_ULP_CLASS_HID_SHFTL 24
-#define BNXT_ULP_CLASS_HID_MASK 32767
+#define BNXT_ULP_CLASS_HID_SHFTR 28
+#define BNXT_ULP_CLASS_HID_SHFTL 28
+#define BNXT_ULP_CLASS_HID_MASK 65535
#define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048
#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 86
#define BNXT_ULP_ACT_HID_LOW_PRIME 7919
@@ -27,10 +27,10 @@
#define BNXT_ULP_ACT_HID_SHFTL 26
#define BNXT_ULP_ACT_HID_MASK 2047
#define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 8
-#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 62
+#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 110
#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 50
-#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 206
-#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 6
+#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 278
+#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 8
#define BNXT_ULP_COND_GOTO_REJECT 1023
#define BNXT_ULP_COND_GOTO_RF 0x10000
#define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7
@@ -44,10 +44,10 @@
#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 618
#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 49
#define ULP_THOR_CLASS_TMPL_LIST_SIZE 6
-#define ULP_THOR_CLASS_TBL_LIST_SIZE 114
-#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 2305
-#define ULP_THOR_CLASS_IDENT_LIST_SIZE 39
-#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1192
+#define ULP_THOR_CLASS_TBL_LIST_SIZE 116
+#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 2323
+#define ULP_THOR_CLASS_IDENT_LIST_SIZE 38
+#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1313
#define ULP_THOR_CLASS_COND_LIST_SIZE 55
#define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7
#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 35
@@ -56,11 +56,11 @@
#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 536
#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 39
#define ULP_THOR_ACT_TMPL_LIST_SIZE 7
-#define ULP_THOR_ACT_TBL_LIST_SIZE 28
-#define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 2
-#define ULP_THOR_ACT_IDENT_LIST_SIZE 1
-#define ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE 479
-#define ULP_THOR_ACT_COND_LIST_SIZE 20
+#define ULP_THOR_ACT_TBL_LIST_SIZE 36
+#define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 16
+#define ULP_THOR_ACT_IDENT_LIST_SIZE 3
+#define ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE 505
+#define ULP_THOR_ACT_COND_LIST_SIZE 27
enum bnxt_ulp_act_bit {
BNXT_ULP_ACT_BIT_MARK = 0x0000000000000001,
@@ -158,56 +158,60 @@ enum bnxt_ulp_cf_idx {
BNXT_ULP_CF_IDX_O_L4_DST_PORT = 18,
BNXT_ULP_CF_IDX_I_L4_SRC_PORT = 19,
BNXT_ULP_CF_IDX_I_L4_DST_PORT = 20,
- BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT = 21,
- BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT = 22,
- BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT = 23,
- BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT = 24,
- BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID = 25,
- BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID = 26,
- BNXT_ULP_CF_IDX_O_L3_PROTO_ID = 27,
- BNXT_ULP_CF_IDX_I_L3_PROTO_ID = 28,
- BNXT_ULP_CF_IDX_DEV_PORT_ID = 29,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 30,
- BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 31,
- BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 32,
- BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 33,
- BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 34,
- BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 35,
- BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 36,
- BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 37,
- BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 38,
- BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 39,
- BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 40,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 41,
- BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 42,
- BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG = 43,
- BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG = 44,
- BNXT_ULP_CF_IDX_ACT_DEC_TTL = 45,
- BNXT_ULP_CF_IDX_ACT_T_DEC_TTL = 46,
- BNXT_ULP_CF_IDX_ACT_PORT_IS_SET = 47,
- BNXT_ULP_CF_IDX_ACT_PORT_TYPE = 48,
- BNXT_ULP_CF_IDX_MATCH_PORT_TYPE = 49,
- BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP = 50,
- BNXT_ULP_CF_IDX_MATCH_PORT_IS_PF = 51,
- BNXT_ULP_CF_IDX_VF_TO_VF = 52,
- BNXT_ULP_CF_IDX_L3_HDR_CNT = 53,
- BNXT_ULP_CF_IDX_L4_HDR_CNT = 54,
- BNXT_ULP_CF_IDX_VFR_MODE = 55,
- BNXT_ULP_CF_IDX_L3_TUN = 56,
- BNXT_ULP_CF_IDX_L3_TUN_DECAP = 57,
- BNXT_ULP_CF_IDX_FID = 58,
- BNXT_ULP_CF_IDX_HDR_SIG_ID = 59,
- BNXT_ULP_CF_IDX_FLOW_SIG_ID = 60,
- BNXT_ULP_CF_IDX_WC_MATCH = 61,
- BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG = 62,
- BNXT_ULP_CF_IDX_TUNNEL_ID = 63,
- BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID = 64,
- BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID = 65,
- BNXT_ULP_CF_IDX_OO_VLAN_FB_VID = 66,
- BNXT_ULP_CF_IDX_OI_VLAN_FB_VID = 67,
- BNXT_ULP_CF_IDX_IO_VLAN_FB_VID = 68,
- BNXT_ULP_CF_IDX_II_VLAN_FB_VID = 69,
- BNXT_ULP_CF_IDX_LAST = 70
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK = 21,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK = 22,
+ BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK = 23,
+ BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK = 24,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT = 25,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT = 26,
+ BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT = 27,
+ BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT = 28,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID = 29,
+ BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID = 30,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID = 31,
+ BNXT_ULP_CF_IDX_I_L3_PROTO_ID = 32,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID = 33,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 34,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 35,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 36,
+ BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 37,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 38,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 39,
+ BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 40,
+ BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 41,
+ BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 42,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 43,
+ BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 44,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 45,
+ BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 46,
+ BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG = 47,
+ BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG = 48,
+ BNXT_ULP_CF_IDX_ACT_DEC_TTL = 49,
+ BNXT_ULP_CF_IDX_ACT_T_DEC_TTL = 50,
+ BNXT_ULP_CF_IDX_ACT_PORT_IS_SET = 51,
+ BNXT_ULP_CF_IDX_ACT_PORT_TYPE = 52,
+ BNXT_ULP_CF_IDX_MATCH_PORT_TYPE = 53,
+ BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP = 54,
+ BNXT_ULP_CF_IDX_MATCH_PORT_IS_PF = 55,
+ BNXT_ULP_CF_IDX_VF_TO_VF = 56,
+ BNXT_ULP_CF_IDX_L3_HDR_CNT = 57,
+ BNXT_ULP_CF_IDX_L4_HDR_CNT = 58,
+ BNXT_ULP_CF_IDX_VFR_MODE = 59,
+ BNXT_ULP_CF_IDX_L3_TUN = 60,
+ BNXT_ULP_CF_IDX_L3_TUN_DECAP = 61,
+ BNXT_ULP_CF_IDX_FID = 62,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID = 63,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID = 64,
+ BNXT_ULP_CF_IDX_WC_MATCH = 65,
+ BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG = 66,
+ BNXT_ULP_CF_IDX_TUNNEL_ID = 67,
+ BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID = 68,
+ BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID = 69,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID = 70,
+ BNXT_ULP_CF_IDX_OI_VLAN_FB_VID = 71,
+ BNXT_ULP_CF_IDX_IO_VLAN_FB_VID = 72,
+ BNXT_ULP_CF_IDX_II_VLAN_FB_VID = 73,
+ BNXT_ULP_CF_IDX_LAST = 74
};
enum bnxt_ulp_cond_list_opc {
@@ -394,38 +398,49 @@ enum bnxt_ulp_glb_rf_idx {
BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 = 9,
BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 = 10,
BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 = 11,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0 = 12,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1 = 13,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_6 = 12,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_7 = 13,
BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 = 14,
BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 = 15,
BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 = 16,
BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3 = 17,
BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4 = 18,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0 = 19,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1 = 20,
- BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0 = 21,
- BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_1 = 22,
- BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 = 23,
- BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 = 24,
- BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 = 25,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 26,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 = 27,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2 = 28,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 29,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 30,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 31,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 32,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 33,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 34,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 35,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 36,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 37,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 38,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 39,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 40,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 41,
- BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID = 42,
- BNXT_ULP_GLB_RF_IDX_LAST = 43
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0 = 19,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1 = 20,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2 = 21,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3 = 22,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_4 = 23,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_5 = 24,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_6 = 25,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_7 = 26,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0 = 27,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1 = 28,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2 = 29,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3 = 30,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_4 = 31,
+ BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0 = 32,
+ BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_1 = 33,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 = 34,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 = 35,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 = 36,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 37,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 = 38,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2 = 39,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 40,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 41,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 42,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 43,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 44,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 45,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 46,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 47,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 48,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 49,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 50,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 51,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 52,
+ BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID = 53,
+ BNXT_ULP_GLB_RF_IDX_LAST = 54
};
enum bnxt_ulp_hdr_type {
@@ -608,7 +623,9 @@ enum bnxt_ulp_resource_sub_type {
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR = 2,
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE = 3,
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE = 4,
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE = 5
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE = 5,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE = 6,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE = 7
};
enum bnxt_ulp_act_prop_sz {
@@ -1526,166 +1543,310 @@ enum bnxt_ulp_class_hid {
BNXT_ULP_CLASS_HID_315d = 0x315d,
BNXT_ULP_CLASS_HID_3612 = 0x3612,
BNXT_ULP_CLASS_HID_66da = 0x66da,
- BNXT_ULP_CLASS_HID_6165 = 0x6165,
- BNXT_ULP_CLASS_HID_2aa1 = 0x2aa1,
- BNXT_ULP_CLASS_HID_09cd = 0x09cd,
- BNXT_ULP_CLASS_HID_3845 = 0x3845,
- BNXT_ULP_CLASS_HID_11e9 = 0x11e9,
- BNXT_ULP_CLASS_HID_4361 = 0x4361,
- BNXT_ULP_CLASS_HID_218d = 0x218d,
- BNXT_ULP_CLASS_HID_5105 = 0x5105,
- BNXT_ULP_CLASS_HID_0c89 = 0x0c89,
- BNXT_ULP_CLASS_HID_3e81 = 0x3e81,
- BNXT_ULP_CLASS_HID_1dad = 0x1dad,
- BNXT_ULP_CLASS_HID_4ca5 = 0x4ca5,
- BNXT_ULP_CLASS_HID_25c9 = 0x25c9,
- BNXT_ULP_CLASS_HID_57c1 = 0x57c1,
- BNXT_ULP_CLASS_HID_33ed = 0x33ed,
- BNXT_ULP_CLASS_HID_65e5 = 0x65e5,
- BNXT_ULP_CLASS_HID_6dd9 = 0x6dd9,
- BNXT_ULP_CLASS_HID_261d = 0x261d,
- BNXT_ULP_CLASS_HID_0571 = 0x0571,
- BNXT_ULP_CLASS_HID_34f9 = 0x34f9,
- BNXT_ULP_CLASS_HID_1d55 = 0x1d55,
- BNXT_ULP_CLASS_HID_4fdd = 0x4fdd,
- BNXT_ULP_CLASS_HID_2d31 = 0x2d31,
- BNXT_ULP_CLASS_HID_5db9 = 0x5db9,
- BNXT_ULP_CLASS_HID_0035 = 0x0035,
- BNXT_ULP_CLASS_HID_323d = 0x323d,
- BNXT_ULP_CLASS_HID_1111 = 0x1111,
- BNXT_ULP_CLASS_HID_4019 = 0x4019,
- BNXT_ULP_CLASS_HID_2975 = 0x2975,
- BNXT_ULP_CLASS_HID_5b7d = 0x5b7d,
- BNXT_ULP_CLASS_HID_3f51 = 0x3f51,
- BNXT_ULP_CLASS_HID_6959 = 0x6959,
- BNXT_ULP_CLASS_HID_0e85 = 0x0e85,
- BNXT_ULP_CLASS_HID_380d = 0x380d,
- BNXT_ULP_CLASS_HID_1f21 = 0x1f21,
- BNXT_ULP_CLASS_HID_4ea9 = 0x4ea9,
- BNXT_ULP_CLASS_HID_1705 = 0x1705,
- BNXT_ULP_CLASS_HID_418d = 0x418d,
- BNXT_ULP_CLASS_HID_2721 = 0x2721,
- BNXT_ULP_CLASS_HID_57a9 = 0x57a9,
- BNXT_ULP_CLASS_HID_1a25 = 0x1a25,
- BNXT_ULP_CLASS_HID_342d = 0x342d,
- BNXT_ULP_CLASS_HID_2b01 = 0x2b01,
- BNXT_ULP_CLASS_HID_5a09 = 0x5a09,
- BNXT_ULP_CLASS_HID_2325 = 0x2325,
- BNXT_ULP_CLASS_HID_5d2d = 0x5d2d,
- BNXT_ULP_CLASS_HID_3101 = 0x3101,
- BNXT_ULP_CLASS_HID_6309 = 0x6309,
- BNXT_ULP_CLASS_HID_0bad = 0x0bad,
- BNXT_ULP_CLASS_HID_2535 = 0x2535,
- BNXT_ULP_CLASS_HID_1869 = 0x1869,
- BNXT_ULP_CLASS_HID_4bf1 = 0x4bf1,
- BNXT_ULP_CLASS_HID_136d = 0x136d,
- BNXT_ULP_CLASS_HID_43f5 = 0x43f5,
- BNXT_ULP_CLASS_HID_2129 = 0x2129,
- BNXT_ULP_CLASS_HID_53b1 = 0x53b1,
- BNXT_ULP_CLASS_HID_072d = 0x072d,
- BNXT_ULP_CLASS_HID_3135 = 0x3135,
- BNXT_ULP_CLASS_HID_1429 = 0x1429,
- BNXT_ULP_CLASS_HID_4731 = 0x4731,
- BNXT_ULP_CLASS_HID_2f6d = 0x2f6d,
- BNXT_ULP_CLASS_HID_5f75 = 0x5f75,
- BNXT_ULP_CLASS_HID_3d69 = 0x3d69,
- BNXT_ULP_CLASS_HID_6f71 = 0x6f71,
- BNXT_ULP_CLASS_HID_0dbd = 0x0dbd,
- BNXT_ULP_CLASS_HID_3f25 = 0x3f25,
- BNXT_ULP_CLASS_HID_1239 = 0x1239,
- BNXT_ULP_CLASS_HID_4da1 = 0x4da1,
- BNXT_ULP_CLASS_HID_153d = 0x153d,
- BNXT_ULP_CLASS_HID_45a5 = 0x45a5,
- BNXT_ULP_CLASS_HID_3bb9 = 0x3bb9,
- BNXT_ULP_CLASS_HID_55a1 = 0x55a1,
- BNXT_ULP_CLASS_HID_193d = 0x193d,
- BNXT_ULP_CLASS_HID_4b25 = 0x4b25,
- BNXT_ULP_CLASS_HID_2e39 = 0x2e39,
- BNXT_ULP_CLASS_HID_5921 = 0x5921,
- BNXT_ULP_CLASS_HID_213d = 0x213d,
- BNXT_ULP_CLASS_HID_5125 = 0x5125,
- BNXT_ULP_CLASS_HID_3739 = 0x3739,
- BNXT_ULP_CLASS_HID_093d = 0x093d,
- BNXT_ULP_CLASS_HID_684d = 0x684d,
- BNXT_ULP_CLASS_HID_2389 = 0x2389,
- BNXT_ULP_CLASS_HID_00e5 = 0x00e5,
- BNXT_ULP_CLASS_HID_316d = 0x316d,
- BNXT_ULP_CLASS_HID_18c1 = 0x18c1,
- BNXT_ULP_CLASS_HID_4a49 = 0x4a49,
- BNXT_ULP_CLASS_HID_28a5 = 0x28a5,
- BNXT_ULP_CLASS_HID_582d = 0x582d,
- BNXT_ULP_CLASS_HID_05a1 = 0x05a1,
- BNXT_ULP_CLASS_HID_37a9 = 0x37a9,
- BNXT_ULP_CLASS_HID_1485 = 0x1485,
- BNXT_ULP_CLASS_HID_458d = 0x458d,
- BNXT_ULP_CLASS_HID_2ce1 = 0x2ce1,
- BNXT_ULP_CLASS_HID_5ee9 = 0x5ee9,
- BNXT_ULP_CLASS_HID_3ac5 = 0x3ac5,
- BNXT_ULP_CLASS_HID_6ccd = 0x6ccd,
- BNXT_ULP_CLASS_HID_0b11 = 0x0b11,
- BNXT_ULP_CLASS_HID_3d99 = 0x3d99,
- BNXT_ULP_CLASS_HID_1ab5 = 0x1ab5,
- BNXT_ULP_CLASS_HID_4b3d = 0x4b3d,
- BNXT_ULP_CLASS_HID_1291 = 0x1291,
- BNXT_ULP_CLASS_HID_4419 = 0x4419,
- BNXT_ULP_CLASS_HID_22b5 = 0x22b5,
- BNXT_ULP_CLASS_HID_523d = 0x523d,
- BNXT_ULP_CLASS_HID_1fb1 = 0x1fb1,
- BNXT_ULP_CLASS_HID_31b9 = 0x31b9,
- BNXT_ULP_CLASS_HID_2e95 = 0x2e95,
- BNXT_ULP_CLASS_HID_5f9d = 0x5f9d,
- BNXT_ULP_CLASS_HID_26b1 = 0x26b1,
- BNXT_ULP_CLASS_HID_58b9 = 0x58b9,
- BNXT_ULP_CLASS_HID_3495 = 0x3495,
- BNXT_ULP_CLASS_HID_669d = 0x669d,
- BNXT_ULP_CLASS_HID_0e39 = 0x0e39,
- BNXT_ULP_CLASS_HID_20a1 = 0x20a1,
- BNXT_ULP_CLASS_HID_1dfd = 0x1dfd,
- BNXT_ULP_CLASS_HID_4e65 = 0x4e65,
- BNXT_ULP_CLASS_HID_16f9 = 0x16f9,
- BNXT_ULP_CLASS_HID_4661 = 0x4661,
- BNXT_ULP_CLASS_HID_24bd = 0x24bd,
- BNXT_ULP_CLASS_HID_5625 = 0x5625,
- BNXT_ULP_CLASS_HID_02b9 = 0x02b9,
- BNXT_ULP_CLASS_HID_34a1 = 0x34a1,
- BNXT_ULP_CLASS_HID_11bd = 0x11bd,
- BNXT_ULP_CLASS_HID_42a5 = 0x42a5,
- BNXT_ULP_CLASS_HID_2af9 = 0x2af9,
- BNXT_ULP_CLASS_HID_5ae1 = 0x5ae1,
- BNXT_ULP_CLASS_HID_38fd = 0x38fd,
- BNXT_ULP_CLASS_HID_6ae5 = 0x6ae5,
- BNXT_ULP_CLASS_HID_0829 = 0x0829,
- BNXT_ULP_CLASS_HID_3ab1 = 0x3ab1,
- BNXT_ULP_CLASS_HID_17ad = 0x17ad,
- BNXT_ULP_CLASS_HID_4835 = 0x4835,
- BNXT_ULP_CLASS_HID_10a9 = 0x10a9,
- BNXT_ULP_CLASS_HID_4031 = 0x4031,
- BNXT_ULP_CLASS_HID_3e2d = 0x3e2d,
- BNXT_ULP_CLASS_HID_5035 = 0x5035,
- BNXT_ULP_CLASS_HID_1ca9 = 0x1ca9,
- BNXT_ULP_CLASS_HID_4eb1 = 0x4eb1,
- BNXT_ULP_CLASS_HID_2bad = 0x2bad,
- BNXT_ULP_CLASS_HID_5cb5 = 0x5cb5,
- BNXT_ULP_CLASS_HID_24a9 = 0x24a9,
- BNXT_ULP_CLASS_HID_54b1 = 0x54b1,
- BNXT_ULP_CLASS_HID_32ad = 0x32ad,
- BNXT_ULP_CLASS_HID_0ca9 = 0x0ca9,
- BNXT_ULP_CLASS_HID_7f35 = 0x7f35,
- BNXT_ULP_CLASS_HID_34f1 = 0x34f1,
- BNXT_ULP_CLASS_HID_179d = 0x179d,
- BNXT_ULP_CLASS_HID_2615 = 0x2615,
- BNXT_ULP_CLASS_HID_0fb9 = 0x0fb9,
- BNXT_ULP_CLASS_HID_5d31 = 0x5d31,
- BNXT_ULP_CLASS_HID_3fdd = 0x3fdd,
- BNXT_ULP_CLASS_HID_4f55 = 0x4f55,
- BNXT_ULP_CLASS_HID_12d9 = 0x12d9,
- BNXT_ULP_CLASS_HID_20d1 = 0x20d1,
- BNXT_ULP_CLASS_HID_03fd = 0x03fd,
- BNXT_ULP_CLASS_HID_52f5 = 0x52f5,
- BNXT_ULP_CLASS_HID_3b99 = 0x3b99,
- BNXT_ULP_CLASS_HID_4991 = 0x4991,
- BNXT_ULP_CLASS_HID_2dbd = 0x2dbd,
- BNXT_ULP_CLASS_HID_7bb5 = 0x7bb5,
+ BNXT_ULP_CLASS_HID_e082 = 0xe082,
+ BNXT_ULP_CLASS_HID_ab46 = 0xab46,
+ BNXT_ULP_CLASS_HID_c82a = 0xc82a,
+ BNXT_ULP_CLASS_HID_f9a2 = 0xf9a2,
+ BNXT_ULP_CLASS_HID_d8ce = 0xd8ce,
+ BNXT_ULP_CLASS_HID_a2d2 = 0xa2d2,
+ BNXT_ULP_CLASS_HID_c076 = 0xc076,
+ BNXT_ULP_CLASS_HID_f1ee = 0xf1ee,
+ BNXT_ULP_CLASS_HID_a96e = 0xa96e,
+ BNXT_ULP_CLASS_HID_dae6 = 0xdae6,
+ BNXT_ULP_CLASS_HID_c7aa = 0xc7aa,
+ BNXT_ULP_CLASS_HID_c26e = 0xc26e,
+ BNXT_ULP_CLASS_HID_a0fa = 0xa0fa,
+ BNXT_ULP_CLASS_HID_d272 = 0xd272,
+ BNXT_ULP_CLASS_HID_fff6 = 0xfff6,
+ BNXT_ULP_CLASS_HID_e16e = 0xe16e,
+ BNXT_ULP_CLASS_HID_e165 = 0xe165,
+ BNXT_ULP_CLASS_HID_aaa1 = 0xaaa1,
+ BNXT_ULP_CLASS_HID_c9cd = 0xc9cd,
+ BNXT_ULP_CLASS_HID_f845 = 0xf845,
+ BNXT_ULP_CLASS_HID_90f9 = 0x90f9,
+ BNXT_ULP_CLASS_HID_c371 = 0xc371,
+ BNXT_ULP_CLASS_HID_e19d = 0xe19d,
+ BNXT_ULP_CLASS_HID_d015 = 0xd015,
+ BNXT_ULP_CLASS_HID_8c09 = 0x8c09,
+ BNXT_ULP_CLASS_HID_be89 = 0xbe89,
+ BNXT_ULP_CLASS_HID_ddad = 0xddad,
+ BNXT_ULP_CLASS_HID_cc2d = 0xcc2d,
+ BNXT_ULP_CLASS_HID_a4d9 = 0xa4d9,
+ BNXT_ULP_CLASS_HID_d759 = 0xd759,
+ BNXT_ULP_CLASS_HID_f27d = 0xf27d,
+ BNXT_ULP_CLASS_HID_e4fd = 0xe4fd,
+ BNXT_ULP_CLASS_HID_ecf6 = 0xecf6,
+ BNXT_ULP_CLASS_HID_a732 = 0xa732,
+ BNXT_ULP_CLASS_HID_c45e = 0xc45e,
+ BNXT_ULP_CLASS_HID_f5d6 = 0xf5d6,
+ BNXT_ULP_CLASS_HID_d4ba = 0xd4ba,
+ BNXT_ULP_CLASS_HID_aea6 = 0xaea6,
+ BNXT_ULP_CLASS_HID_cc02 = 0xcc02,
+ BNXT_ULP_CLASS_HID_fd9a = 0xfd9a,
+ BNXT_ULP_CLASS_HID_a51a = 0xa51a,
+ BNXT_ULP_CLASS_HID_d692 = 0xd692,
+ BNXT_ULP_CLASS_HID_cbde = 0xcbde,
+ BNXT_ULP_CLASS_HID_ce1a = 0xce1a,
+ BNXT_ULP_CLASS_HID_ac8e = 0xac8e,
+ BNXT_ULP_CLASS_HID_de06 = 0xde06,
+ BNXT_ULP_CLASS_HID_f382 = 0xf382,
+ BNXT_ULP_CLASS_HID_ed1a = 0xed1a,
+ BNXT_ULP_CLASS_HID_9d6a = 0x9d6a,
+ BNXT_ULP_CLASS_HID_cee2 = 0xcee2,
+ BNXT_ULP_CLASS_HID_ec0e = 0xec0e,
+ BNXT_ULP_CLASS_HID_dd86 = 0xdd86,
+ BNXT_ULP_CLASS_HID_852e = 0x852e,
+ BNXT_ULP_CLASS_HID_b6a6 = 0xb6a6,
+ BNXT_ULP_CLASS_HID_eb82 = 0xeb82,
+ BNXT_ULP_CLASS_HID_c50a = 0xc50a,
+ BNXT_ULP_CLASS_HID_ccca = 0xccca,
+ BNXT_ULP_CLASS_HID_8706 = 0x8706,
+ BNXT_ULP_CLASS_HID_d38e = 0xd38e,
+ BNXT_ULP_CLASS_HID_d5ca = 0xd5ca,
+ BNXT_ULP_CLASS_HID_b48e = 0xb48e,
+ BNXT_ULP_CLASS_HID_8e8a = 0x8e8a,
+ BNXT_ULP_CLASS_HID_db02 = 0xdb02,
+ BNXT_ULP_CLASS_HID_dd8e = 0xdd8e,
+ BNXT_ULP_CLASS_HID_819a = 0x819a,
+ BNXT_ULP_CLASS_HID_b31a = 0xb31a,
+ BNXT_ULP_CLASS_HID_d03e = 0xd03e,
+ BNXT_ULP_CLASS_HID_c1be = 0xc1be,
+ BNXT_ULP_CLASS_HID_890e = 0x890e,
+ BNXT_ULP_CLASS_HID_ba8e = 0xba8e,
+ BNXT_ULP_CLASS_HID_dfaa = 0xdfaa,
+ BNXT_ULP_CLASS_HID_c93a = 0xc93a,
+ BNXT_ULP_CLASS_HID_b11a = 0xb11a,
+ BNXT_ULP_CLASS_HID_8b4e = 0x8b4e,
+ BNXT_ULP_CLASS_HID_c79e = 0xc79e,
+ BNXT_ULP_CLASS_HID_d9da = 0xd9da,
+ BNXT_ULP_CLASS_HID_b88e = 0xb88e,
+ BNXT_ULP_CLASS_HID_ea0e = 0xea0e,
+ BNXT_ULP_CLASS_HID_cf0a = 0xcf0a,
+ BNXT_ULP_CLASS_HID_c18e = 0xc18e,
+ BNXT_ULP_CLASS_HID_a94a = 0xa94a,
+ BNXT_ULP_CLASS_HID_daca = 0xdaca,
+ BNXT_ULP_CLASS_HID_ffee = 0xffee,
+ BNXT_ULP_CLASS_HID_e96e = 0xe96e,
+ BNXT_ULP_CLASS_HID_910e = 0x910e,
+ BNXT_ULP_CLASS_HID_c28e = 0xc28e,
+ BNXT_ULP_CLASS_HID_e7aa = 0xe7aa,
+ BNXT_ULP_CLASS_HID_d12a = 0xd12a,
+ BNXT_ULP_CLASS_HID_d8ca = 0xd8ca,
+ BNXT_ULP_CLASS_HID_930e = 0x930e,
+ BNXT_ULP_CLASS_HID_ef4e = 0xef4e,
+ BNXT_ULP_CLASS_HID_e18a = 0xe18a,
+ BNXT_ULP_CLASS_HID_c08e = 0xc08e,
+ BNXT_ULP_CLASS_HID_9a8a = 0x9a8a,
+ BNXT_ULP_CLASS_HID_d70a = 0xd70a,
+ BNXT_ULP_CLASS_HID_e90e = 0xe90e,
+ BNXT_ULP_CLASS_HID_edd9 = 0xedd9,
+ BNXT_ULP_CLASS_HID_a61d = 0xa61d,
+ BNXT_ULP_CLASS_HID_c571 = 0xc571,
+ BNXT_ULP_CLASS_HID_f4f9 = 0xf4f9,
+ BNXT_ULP_CLASS_HID_9c45 = 0x9c45,
+ BNXT_ULP_CLASS_HID_cfcd = 0xcfcd,
+ BNXT_ULP_CLASS_HID_ed21 = 0xed21,
+ BNXT_ULP_CLASS_HID_dca9 = 0xdca9,
+ BNXT_ULP_CLASS_HID_80b5 = 0x80b5,
+ BNXT_ULP_CLASS_HID_b235 = 0xb235,
+ BNXT_ULP_CLASS_HID_d111 = 0xd111,
+ BNXT_ULP_CLASS_HID_c091 = 0xc091,
+ BNXT_ULP_CLASS_HID_a865 = 0xa865,
+ BNXT_ULP_CLASS_HID_dbe5 = 0xdbe5,
+ BNXT_ULP_CLASS_HID_fec1 = 0xfec1,
+ BNXT_ULP_CLASS_HID_e841 = 0xe841,
+ BNXT_ULP_CLASS_HID_8e85 = 0x8e85,
+ BNXT_ULP_CLASS_HID_b80d = 0xb80d,
+ BNXT_ULP_CLASS_HID_df65 = 0xdf65,
+ BNXT_ULP_CLASS_HID_ceed = 0xceed,
+ BNXT_ULP_CLASS_HID_9645 = 0x9645,
+ BNXT_ULP_CLASS_HID_c1cd = 0xc1cd,
+ BNXT_ULP_CLASS_HID_e725 = 0xe725,
+ BNXT_ULP_CLASS_HID_d6ad = 0xd6ad,
+ BNXT_ULP_CLASS_HID_9aa5 = 0x9aa5,
+ BNXT_ULP_CLASS_HID_b425 = 0xb425,
+ BNXT_ULP_CLASS_HID_eb05 = 0xeb05,
+ BNXT_ULP_CLASS_HID_da85 = 0xda85,
+ BNXT_ULP_CLASS_HID_a265 = 0xa265,
+ BNXT_ULP_CLASS_HID_dde5 = 0xdde5,
+ BNXT_ULP_CLASS_HID_f0c5 = 0xf0c5,
+ BNXT_ULP_CLASS_HID_e245 = 0xe245,
+ BNXT_ULP_CLASS_HID_8b8f = 0x8b8f,
+ BNXT_ULP_CLASS_HID_a517 = 0xa517,
+ BNXT_ULP_CLASS_HID_d86b = 0xd86b,
+ BNXT_ULP_CLASS_HID_cbf3 = 0xcbf3,
+ BNXT_ULP_CLASS_HID_934f = 0x934f,
+ BNXT_ULP_CLASS_HID_c2c7 = 0xc2c7,
+ BNXT_ULP_CLASS_HID_e02b = 0xe02b,
+ BNXT_ULP_CLASS_HID_d3a3 = 0xd3a3,
+ BNXT_ULP_CLASS_HID_87a7 = 0x87a7,
+ BNXT_ULP_CLASS_HID_b137 = 0xb137,
+ BNXT_ULP_CLASS_HID_d403 = 0xd403,
+ BNXT_ULP_CLASS_HID_c793 = 0xc793,
+ BNXT_ULP_CLASS_HID_af67 = 0xaf67,
+ BNXT_ULP_CLASS_HID_dee7 = 0xdee7,
+ BNXT_ULP_CLASS_HID_fdc3 = 0xfdc3,
+ BNXT_ULP_CLASS_HID_ef43 = 0xef43,
+ BNXT_ULP_CLASS_HID_8dbf = 0x8dbf,
+ BNXT_ULP_CLASS_HID_bf07 = 0xbf07,
+ BNXT_ULP_CLASS_HID_d21f = 0xd21f,
+ BNXT_ULP_CLASS_HID_cde7 = 0xcde7,
+ BNXT_ULP_CLASS_HID_956f = 0x956f,
+ BNXT_ULP_CLASS_HID_c4c7 = 0xc4c7,
+ BNXT_ULP_CLASS_HID_fbcf = 0xfbcf,
+ BNXT_ULP_CLASS_HID_d5a7 = 0xd5a7,
+ BNXT_ULP_CLASS_HID_9957 = 0x9957,
+ BNXT_ULP_CLASS_HID_cb27 = 0xcb27,
+ BNXT_ULP_CLASS_HID_ee37 = 0xee37,
+ BNXT_ULP_CLASS_HID_d987 = 0xd987,
+ BNXT_ULP_CLASS_HID_a107 = 0xa107,
+ BNXT_ULP_CLASS_HID_d0e7 = 0xd0e7,
+ BNXT_ULP_CLASS_HID_f7e7 = 0xf7e7,
+ BNXT_ULP_CLASS_HID_c827 = 0xc827,
+ BNXT_ULP_CLASS_HID_f76a = 0xf76a,
+ BNXT_ULP_CLASS_HID_bcae = 0xbcae,
+ BNXT_ULP_CLASS_HID_dfc2 = 0xdfc2,
+ BNXT_ULP_CLASS_HID_ee4a = 0xee4a,
+ BNXT_ULP_CLASS_HID_cf26 = 0xcf26,
+ BNXT_ULP_CLASS_HID_b53a = 0xb53a,
+ BNXT_ULP_CLASS_HID_d79e = 0xd79e,
+ BNXT_ULP_CLASS_HID_e606 = 0xe606,
+ BNXT_ULP_CLASS_HID_be86 = 0xbe86,
+ BNXT_ULP_CLASS_HID_cd0e = 0xcd0e,
+ BNXT_ULP_CLASS_HID_d042 = 0xd042,
+ BNXT_ULP_CLASS_HID_d586 = 0xd586,
+ BNXT_ULP_CLASS_HID_b712 = 0xb712,
+ BNXT_ULP_CLASS_HID_c59a = 0xc59a,
+ BNXT_ULP_CLASS_HID_e81e = 0xe81e,
+ BNXT_ULP_CLASS_HID_f686 = 0xf686,
+ BNXT_ULP_CLASS_HID_86f6 = 0x86f6,
+ BNXT_ULP_CLASS_HID_d57e = 0xd57e,
+ BNXT_ULP_CLASS_HID_f792 = 0xf792,
+ BNXT_ULP_CLASS_HID_c61a = 0xc61a,
+ BNXT_ULP_CLASS_HID_9eb2 = 0x9eb2,
+ BNXT_ULP_CLASS_HID_ad3a = 0xad3a,
+ BNXT_ULP_CLASS_HID_f01e = 0xf01e,
+ BNXT_ULP_CLASS_HID_de96 = 0xde96,
+ BNXT_ULP_CLASS_HID_d756 = 0xd756,
+ BNXT_ULP_CLASS_HID_9c9a = 0x9c9a,
+ BNXT_ULP_CLASS_HID_c812 = 0xc812,
+ BNXT_ULP_CLASS_HID_ce56 = 0xce56,
+ BNXT_ULP_CLASS_HID_af12 = 0xaf12,
+ BNXT_ULP_CLASS_HID_9516 = 0x9516,
+ BNXT_ULP_CLASS_HID_c09e = 0xc09e,
+ BNXT_ULP_CLASS_HID_c612 = 0xc612,
+ BNXT_ULP_CLASS_HID_9a06 = 0x9a06,
+ BNXT_ULP_CLASS_HID_a886 = 0xa886,
+ BNXT_ULP_CLASS_HID_cba2 = 0xcba2,
+ BNXT_ULP_CLASS_HID_da22 = 0xda22,
+ BNXT_ULP_CLASS_HID_9292 = 0x9292,
+ BNXT_ULP_CLASS_HID_a112 = 0xa112,
+ BNXT_ULP_CLASS_HID_c436 = 0xc436,
+ BNXT_ULP_CLASS_HID_d2a6 = 0xd2a6,
+ BNXT_ULP_CLASS_HID_aa86 = 0xaa86,
+ BNXT_ULP_CLASS_HID_90d2 = 0x90d2,
+ BNXT_ULP_CLASS_HID_dc02 = 0xdc02,
+ BNXT_ULP_CLASS_HID_c246 = 0xc246,
+ BNXT_ULP_CLASS_HID_a312 = 0xa312,
+ BNXT_ULP_CLASS_HID_f192 = 0xf192,
+ BNXT_ULP_CLASS_HID_d496 = 0xd496,
+ BNXT_ULP_CLASS_HID_da12 = 0xda12,
+ BNXT_ULP_CLASS_HID_b2d6 = 0xb2d6,
+ BNXT_ULP_CLASS_HID_c156 = 0xc156,
+ BNXT_ULP_CLASS_HID_e472 = 0xe472,
+ BNXT_ULP_CLASS_HID_f2f2 = 0xf2f2,
+ BNXT_ULP_CLASS_HID_8a92 = 0x8a92,
+ BNXT_ULP_CLASS_HID_d912 = 0xd912,
+ BNXT_ULP_CLASS_HID_fc36 = 0xfc36,
+ BNXT_ULP_CLASS_HID_cab6 = 0xcab6,
+ BNXT_ULP_CLASS_HID_c356 = 0xc356,
+ BNXT_ULP_CLASS_HID_8892 = 0x8892,
+ BNXT_ULP_CLASS_HID_f4d2 = 0xf4d2,
+ BNXT_ULP_CLASS_HID_fa16 = 0xfa16,
+ BNXT_ULP_CLASS_HID_db12 = 0xdb12,
+ BNXT_ULP_CLASS_HID_8116 = 0x8116,
+ BNXT_ULP_CLASS_HID_cc96 = 0xcc96,
+ BNXT_ULP_CLASS_HID_f292 = 0xf292,
+ BNXT_ULP_CLASS_HID_e84d = 0xe84d,
+ BNXT_ULP_CLASS_HID_a389 = 0xa389,
+ BNXT_ULP_CLASS_HID_c0e5 = 0xc0e5,
+ BNXT_ULP_CLASS_HID_f16d = 0xf16d,
+ BNXT_ULP_CLASS_HID_99d1 = 0x99d1,
+ BNXT_ULP_CLASS_HID_ca59 = 0xca59,
+ BNXT_ULP_CLASS_HID_e8b5 = 0xe8b5,
+ BNXT_ULP_CLASS_HID_d93d = 0xd93d,
+ BNXT_ULP_CLASS_HID_8521 = 0x8521,
+ BNXT_ULP_CLASS_HID_b7a1 = 0xb7a1,
+ BNXT_ULP_CLASS_HID_d485 = 0xd485,
+ BNXT_ULP_CLASS_HID_c505 = 0xc505,
+ BNXT_ULP_CLASS_HID_adf1 = 0xadf1,
+ BNXT_ULP_CLASS_HID_de71 = 0xde71,
+ BNXT_ULP_CLASS_HID_fb55 = 0xfb55,
+ BNXT_ULP_CLASS_HID_edd5 = 0xedd5,
+ BNXT_ULP_CLASS_HID_8b11 = 0x8b11,
+ BNXT_ULP_CLASS_HID_bd99 = 0xbd99,
+ BNXT_ULP_CLASS_HID_daf1 = 0xdaf1,
+ BNXT_ULP_CLASS_HID_cb79 = 0xcb79,
+ BNXT_ULP_CLASS_HID_93d1 = 0x93d1,
+ BNXT_ULP_CLASS_HID_c459 = 0xc459,
+ BNXT_ULP_CLASS_HID_e2b1 = 0xe2b1,
+ BNXT_ULP_CLASS_HID_d339 = 0xd339,
+ BNXT_ULP_CLASS_HID_9f31 = 0x9f31,
+ BNXT_ULP_CLASS_HID_b1b1 = 0xb1b1,
+ BNXT_ULP_CLASS_HID_ee91 = 0xee91,
+ BNXT_ULP_CLASS_HID_df11 = 0xdf11,
+ BNXT_ULP_CLASS_HID_a7f1 = 0xa7f1,
+ BNXT_ULP_CLASS_HID_d871 = 0xd871,
+ BNXT_ULP_CLASS_HID_f551 = 0xf551,
+ BNXT_ULP_CLASS_HID_e7d1 = 0xe7d1,
+ BNXT_ULP_CLASS_HID_8e1b = 0x8e1b,
+ BNXT_ULP_CLASS_HID_a083 = 0xa083,
+ BNXT_ULP_CLASS_HID_ddff = 0xddff,
+ BNXT_ULP_CLASS_HID_ce67 = 0xce67,
+ BNXT_ULP_CLASS_HID_96db = 0x96db,
+ BNXT_ULP_CLASS_HID_c753 = 0xc753,
+ BNXT_ULP_CLASS_HID_e5bf = 0xe5bf,
+ BNXT_ULP_CLASS_HID_d637 = 0xd637,
+ BNXT_ULP_CLASS_HID_8233 = 0x8233,
+ BNXT_ULP_CLASS_HID_b4a3 = 0xb4a3,
+ BNXT_ULP_CLASS_HID_d197 = 0xd197,
+ BNXT_ULP_CLASS_HID_c207 = 0xc207,
+ BNXT_ULP_CLASS_HID_aaf3 = 0xaaf3,
+ BNXT_ULP_CLASS_HID_db73 = 0xdb73,
+ BNXT_ULP_CLASS_HID_f857 = 0xf857,
+ BNXT_ULP_CLASS_HID_ead7 = 0xead7,
+ BNXT_ULP_CLASS_HID_882b = 0x882b,
+ BNXT_ULP_CLASS_HID_ba93 = 0xba93,
+ BNXT_ULP_CLASS_HID_d78b = 0xd78b,
+ BNXT_ULP_CLASS_HID_c873 = 0xc873,
+ BNXT_ULP_CLASS_HID_90fb = 0x90fb,
+ BNXT_ULP_CLASS_HID_c153 = 0xc153,
+ BNXT_ULP_CLASS_HID_fe5b = 0xfe5b,
+ BNXT_ULP_CLASS_HID_d033 = 0xd033,
+ BNXT_ULP_CLASS_HID_9cc3 = 0x9cc3,
+ BNXT_ULP_CLASS_HID_ceb3 = 0xceb3,
+ BNXT_ULP_CLASS_HID_eba3 = 0xeba3,
+ BNXT_ULP_CLASS_HID_dc13 = 0xdc13,
+ BNXT_ULP_CLASS_HID_a493 = 0xa493,
+ BNXT_ULP_CLASS_HID_d573 = 0xd573,
+ BNXT_ULP_CLASS_HID_f273 = 0xf273,
+ BNXT_ULP_CLASS_HID_cdb3 = 0xcdb3,
+ BNXT_ULP_CLASS_HID_ff35 = 0xff35,
+ BNXT_ULP_CLASS_HID_b4f1 = 0xb4f1,
+ BNXT_ULP_CLASS_HID_d79d = 0xd79d,
+ BNXT_ULP_CLASS_HID_e615 = 0xe615,
+ BNXT_ULP_CLASS_HID_8ea9 = 0x8ea9,
+ BNXT_ULP_CLASS_HID_dd21 = 0xdd21,
+ BNXT_ULP_CLASS_HID_ffcd = 0xffcd,
+ BNXT_ULP_CLASS_HID_ce45 = 0xce45,
+ BNXT_ULP_CLASS_HID_9259 = 0x9259,
+ BNXT_ULP_CLASS_HID_a0d9 = 0xa0d9,
+ BNXT_ULP_CLASS_HID_c3fd = 0xc3fd,
+ BNXT_ULP_CLASS_HID_d27d = 0xd27d,
+ BNXT_ULP_CLASS_HID_ba89 = 0xba89,
+ BNXT_ULP_CLASS_HID_c909 = 0xc909,
+ BNXT_ULP_CLASS_HID_ec2d = 0xec2d,
+ BNXT_ULP_CLASS_HID_faad = 0xfaad,
BNXT_ULP_CLASS_HID_34c6 = 0x34c6,
BNXT_ULP_CLASS_HID_0c22 = 0x0c22,
BNXT_ULP_CLASS_HID_1cbe = 0x1cbe,
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h
index 1d7bbfe2cc..0a5c7e3d6e 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 20 11:56:39 2021 */
+/* date: Fri Aug 6 11:15:47 2021 */
#ifndef ULP_HDR_FIELD_ENUMS_H_
#define ULP_HDR_FIELD_ENUMS_H_
@@ -459,16 +459,14 @@ enum bnxt_ulp_hf_0_2_1_bitmask {
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC = 0x0000080000000000,
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC = 0x0000040000000000,
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_TYPE = 0x0000020000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_VER = 0x0000010000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_TOS = 0x0000008000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_LEN = 0x0000004000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_TTL = 0x0000000800000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_TC = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_FLOW_LABEL = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_PROTO_ID = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR = 0x0000000200000000
};
enum bnxt_ulp_hf_0_2_2_bitmask {
@@ -504,16 +502,7 @@ enum bnxt_ulp_hf_0_2_2_bitmask {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT = 0x0000000040000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT = 0x0000000020000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SENT_SEQ = 0x0000000010000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_RECV_ACK = 0x0000000008000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DATA_OFF = 0x0000000004000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_TCP_FLAGS = 0x0000000002000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_RX_WIN = 0x0000000001000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_CSUM = 0x0000000000800000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_URP = 0x0000000000400000
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000
};
enum bnxt_ulp_hf_0_2_3_bitmask {
@@ -540,20 +529,23 @@ enum bnxt_ulp_hf_0_2_3_bitmask {
BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC = 0x0000080000000000,
BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC = 0x0000040000000000,
BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_TYPE = 0x0000020000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_VER = 0x0000010000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_TOS = 0x0000008000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_LEN = 0x0000004000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_TTL = 0x0000000800000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT = 0x0000000040000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT = 0x0000000020000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_LENGTH = 0x0000000010000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_CSUM = 0x0000000008000000
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_TC = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_FLOW_LABEL = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_PROTO_ID = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SENT_SEQ = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_RECV_ACK = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DATA_OFF = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_TCP_FLAGS = 0x0000000008000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_RX_WIN = 0x0000000004000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_CSUM = 0x0000000002000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_URP = 0x0000000001000000
};
enum bnxt_ulp_hf_0_2_4_bitmask {
@@ -590,11 +582,134 @@ enum bnxt_ulp_hf_0_2_4_bitmask {
BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_TYPE = 0x0000000040000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_CODE = 0x0000000020000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_CSUM = 0x0000000010000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_IDENT = 0x0000000008000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_SEQ_NUM = 0x0000000004000000
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SENT_SEQ = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_RECV_ACK = 0x0000000008000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DATA_OFF = 0x0000000004000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_TCP_FLAGS = 0x0000000002000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_RX_WIN = 0x0000000001000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_CSUM = 0x0000000000800000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_URP = 0x0000000000400000
+};
+
+enum bnxt_ulp_hf_0_2_5_bitmask {
+ BNXT_ULP_HF_0_2_5_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_TC = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_FLOW_LABEL = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_PROTO_ID = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_LENGTH = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_CSUM = 0x0000000020000000
+};
+
+enum bnxt_ulp_hf_0_2_6_bitmask {
+ BNXT_ULP_HF_0_2_6_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_LENGTH = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_CSUM = 0x0000000008000000
+};
+
+enum bnxt_ulp_hf_0_2_7_bitmask {
+ BNXT_ULP_HF_0_2_7_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_TYPE = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_CODE = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_CSUM = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_IDENT = 0x0000000008000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_SEQ_NUM = 0x0000000004000000
};
enum bnxt_ulp_hf_0_3_0_bitmask {
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
index 3d1e95d18c..684fa66f48 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu Jul 8 08:44:00 2021 */
+/* date: Tue Aug 17 12:16:42 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -131,6 +131,46 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = {
.num_buckets = 8,
.hash_tbl_entries = 1024,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE << 1 |
+ BNXT_ULP_DIRECTION_INGRESS] = {
+ .name = "INGRESS GEN_TABLE_SOURCE_PROPERTY_CACHE",
+ .result_num_entries = 0,
+ .result_num_bytes = 6,
+ .key_num_bytes = 10,
+ .num_buckets = 4,
+ .hash_tbl_entries = 0,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE << 1 |
+ BNXT_ULP_DIRECTION_EGRESS] = {
+ .name = "INGRESS GEN_TABLE_SOURCE_PROPERTY_CACHE",
+ .result_num_entries = 128,
+ .result_num_bytes = 6,
+ .key_num_bytes = 10,
+ .num_buckets = 4,
+ .hash_tbl_entries = 512,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE << 1 |
+ BNXT_ULP_DIRECTION_INGRESS] = {
+ .name = "INGRESS GEN_TABLE_VXLAN_ENCAP_REC_CACHE",
+ .result_num_entries = 0,
+ .result_num_bytes = 6,
+ .key_num_bytes = 17,
+ .num_buckets = 8,
+ .hash_tbl_entries = 0,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE << 1 |
+ BNXT_ULP_DIRECTION_EGRESS] = {
+ .name = "INGRESS GEN_TABLE_VXLAN_ENCAP_REC_CACHE",
+ .result_num_entries = 256,
+ .result_num_bytes = 6,
+ .key_num_bytes = 17,
+ .num_buckets = 8,
+ .hash_tbl_entries = 1024,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
}
};
@@ -222,6 +262,7 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
.byte_count_shift = 0,
.packet_count_shift = 36,
.dynamic_pad_en = 0,
+ .dynamic_sram_en = 0,
.dev_tbls = ulp_template_wh_plus_tbls
},
[BNXT_ULP_DEVICE_ID_THOR] = {
@@ -246,12 +287,24 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
.byte_count_shift = 0,
.packet_count_shift = 35,
.dynamic_pad_en = 1,
+ .dynamic_sram_en = 1,
+ .dyn_encap_list_size = 4,
+ .dyn_encap_sizes = {{64, TF_TBL_TYPE_ACT_ENCAP_8B},
+ {128, TF_TBL_TYPE_ACT_ENCAP_16B},
+ {256, TF_TBL_TYPE_ACT_ENCAP_32B},
+ {512, TF_TBL_TYPE_ACT_ENCAP_64B}},
+ .dyn_modify_list_size = 4,
+ .dyn_modify_sizes = {{64, TF_TBL_TYPE_ACT_MODIFY_8B},
+ {128, TF_TBL_TYPE_ACT_MODIFY_16B},
+ {256, TF_TBL_TYPE_ACT_MODIFY_32B},
+ {512, TF_TBL_TYPE_ACT_MODIFY_64B}},
.em_blk_size_bits = 100,
.em_blk_align_bits = 128,
.em_key_align_bytes = 80,
.wc_slice_width = 160,
.wc_max_slices = 4,
- .wc_mode_list = {0x0000000c, 0x0000000e, 0x0000000f, 0x0000000f},
+ .wc_mode_list = {0x0000000c, 0x0000000e,
+ 0x0000000f, 0x0000000f},
.wc_mod_list_max_size = 4,
.wc_ctl_size_bits = 32,
.dev_tbls = ulp_template_thor_tbls
@@ -307,6 +360,16 @@ struct bnxt_ulp_app_capabilities_info ulp_app_cap_info_list[] = {
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.flags = BNXT_ULP_APP_CAP_SHARED_EN |
BNXT_ULP_APP_CAP_UNICAST_ONLY
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY
}
};
@@ -1279,333 +1342,1261 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = {
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
.direction = TF_DIR_TX
- }
-};
-
-/* List of tf resources required to be reserved per app/device */
-struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
+ },
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 422
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 6
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 191
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 63
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 192
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 8192
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 6912
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 1023
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 511
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 15
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
- .count = 255
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
- .count = 1
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 422
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 6
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 960
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 88
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
- .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 13168
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
- .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
- .count = 1
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 292
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 148
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 191
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 63
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 192
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 8192
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_6,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_7,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_6,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_7,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3,
+ .direction = TF_DIR_RX
+ }
+};
+
+/* List of tf resources required to be reserved per app/device */
+struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 422
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 191
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 6912
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 511
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 15
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
+ .count = 255
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 422
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 960
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 88
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 13168
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 292
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 148
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 191
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 6912
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 511
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 223
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 255
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 488
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
+ .count = 511
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 292
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 144
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 960
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 928
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 15232
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 272
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 31
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 64
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 64
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 272
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 128
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4096
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 16384
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 272
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 64
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 100
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 272
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 128
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4096
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 16384
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .count = 1
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 32
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 2
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 128
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 128
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 32
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 2
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 32
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 1024
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 32
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 2
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 128
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 6912
+ .count = 128
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 1023
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 511
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 223
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 255
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 488
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
- .count = 511
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
- .count = 1
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 292
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 144
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 960
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 928
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 15232
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
- .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
- .count = 1
+ .count = 1024
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 422
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 6
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1613,15 +2604,15 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 32
+ .count = 16
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1629,255 +2620,223 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 2048
- },
- {
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 512
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 528
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
- .count = 5
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 256
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 32
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 31
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 64
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 64
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 300
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 6
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 128
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 2048
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 13200
+ .count = 1024
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 26
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 26
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 32
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 63
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 32
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 1023
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_STATS_64,
.count = 512
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
- .count = 5
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 256
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 32
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 32
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 64
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 100
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
- .count = 32
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 200
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 110
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 128
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 2048
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 15232
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_METADATA,
- .count = 1
+ .count = 1024
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1885,7 +2844,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1893,7 +2852,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1901,7 +2860,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1909,7 +2868,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1917,7 +2876,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1925,7 +2884,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 128
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1933,7 +2892,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 128
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1941,7 +2900,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1949,7 +2908,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1957,7 +2916,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1965,7 +2924,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1973,7 +2932,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1981,7 +2940,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1989,15 +2948,15 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 64
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
@@ -2005,7 +2964,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 1024
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2013,7 +2972,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2021,7 +2980,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2029,7 +2988,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2037,7 +2996,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2045,7 +3004,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2053,7 +3012,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 128
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2061,7 +3020,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 128
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2069,7 +3028,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2077,7 +3036,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2085,7 +3044,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2093,7 +3052,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2101,7 +3060,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2109,7 +3068,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2117,7 +3076,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2125,7 +3084,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2133,7 +3092,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2141,7 +3100,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
@@ -2149,7 +3108,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 1024
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2157,7 +3116,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2165,7 +3124,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2173,7 +3132,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2181,7 +3140,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 16
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2189,7 +3148,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2197,7 +3156,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 528
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2205,7 +3164,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 256
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2213,7 +3172,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2221,7 +3180,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2229,7 +3188,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2237,7 +3196,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2245,7 +3204,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2253,7 +3212,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2261,15 +3220,15 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 512
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
@@ -2277,7 +3236,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 1024
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2285,7 +3244,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2293,7 +3252,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2301,7 +3260,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2309,7 +3268,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2317,7 +3276,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2325,7 +3284,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 512
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2333,7 +3292,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 256
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2341,7 +3300,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2349,7 +3308,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2357,7 +3316,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2365,7 +3324,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2373,7 +3332,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2381,7 +3340,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2389,7 +3348,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2397,7 +3356,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
@@ -2405,532 +3364,596 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 1024
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 422
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 191
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 63
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 192
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 128
+ .count = 8192
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 128
+ .count = 7168
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 4
+ .count = 1023
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 4
+ .count = 511
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 4
+ .count = 15
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
- .count = 4
+ .count = 255
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 422
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 960
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 64
+ .count = 88
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 13168
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 292
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 148
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 191
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 63
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 192
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 128
+ .count = 8192
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 128
+ .count = 7168
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 4
+ .count = 1023
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .count = 511
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 4
+ .count = 223
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 4
+ .count = 255
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .count = 488
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
- .count = 4
+ .count = 511
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 292
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 144
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 960
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 928
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 15232
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 16
+ .count = 63
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 528
+ .count = 4096
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 256
+ .count = 1024
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 4
+ .count = 32
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 4
+ .count = 32
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .count = 1024
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .count = 1024
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 1024
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 512
+ .count = 2048
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 6144
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 63
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 512
+ .count = 4096
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 256
+ .count = 1024
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 4
+ .count = 32
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 4
+ .count = 32
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .count = 1024
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .count = 1024
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 1024
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 2048
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 6144
}
};
@@ -3322,25 +4345,23 @@ uint8_t ulp_glb_field_tbl[] = {
[4229] = 21,
[4231] = 22,
[4244] = 2,
- [4245] = 23,
[4246] = 3,
- [4247] = 24,
[4248] = 4,
- [4249] = 25,
[4250] = 5,
- [4251] = 26,
[4252] = 6,
- [4253] = 27,
[4254] = 7,
- [4255] = 28,
[4256] = 8,
- [4257] = 29,
[4258] = 9,
- [4259] = 30,
[4260] = 10,
- [4261] = 31,
[4262] = 11,
- [4263] = 32,
+ [4265] = 23,
+ [4267] = 24,
+ [4269] = 25,
+ [4271] = 26,
+ [4273] = 27,
+ [4275] = 28,
+ [4277] = 29,
+ [4279] = 30,
[4298] = 12,
[4300] = 13,
[4302] = 14,
@@ -3374,15 +4395,6 @@ uint8_t ulp_glb_field_tbl[] = {
[4389] = 31,
[4390] = 11,
[4391] = 32,
- [4409] = 33,
- [4411] = 34,
- [4413] = 35,
- [4415] = 36,
- [4417] = 37,
- [4419] = 38,
- [4421] = 39,
- [4423] = 40,
- [4425] = 41,
[4426] = 12,
[4428] = 13,
[4430] = 14,
@@ -3397,33 +4409,36 @@ uint8_t ulp_glb_field_tbl[] = {
[4485] = 21,
[4487] = 22,
[4500] = 2,
- [4501] = 23,
[4502] = 3,
- [4503] = 24,
[4504] = 4,
- [4505] = 25,
[4506] = 5,
- [4507] = 26,
[4508] = 6,
- [4509] = 27,
[4510] = 7,
- [4511] = 28,
[4512] = 8,
- [4513] = 29,
[4514] = 9,
- [4515] = 30,
[4516] = 10,
- [4517] = 31,
[4518] = 11,
- [4519] = 32,
+ [4521] = 23,
+ [4523] = 24,
+ [4525] = 25,
+ [4527] = 26,
+ [4529] = 27,
+ [4531] = 28,
+ [4533] = 29,
+ [4535] = 30,
+ [4537] = 31,
+ [4539] = 32,
+ [4541] = 33,
+ [4543] = 34,
+ [4545] = 35,
+ [4547] = 36,
+ [4549] = 37,
+ [4551] = 38,
+ [4553] = 39,
[4554] = 12,
- [4555] = 33,
[4556] = 13,
- [4557] = 34,
[4558] = 14,
- [4559] = 35,
[4560] = 15,
- [4561] = 36,
[4574] = 16,
[4575] = 17,
[4576] = 18,
@@ -3433,11 +4448,6 @@ uint8_t ulp_glb_field_tbl[] = {
[4611] = 20,
[4613] = 21,
[4615] = 22,
- [4619] = 33,
- [4621] = 34,
- [4623] = 35,
- [4625] = 36,
- [4627] = 37,
[4628] = 2,
[4629] = 23,
[4630] = 3,
@@ -3458,6 +4468,15 @@ uint8_t ulp_glb_field_tbl[] = {
[4645] = 31,
[4646] = 11,
[4647] = 32,
+ [4665] = 33,
+ [4667] = 34,
+ [4669] = 35,
+ [4671] = 36,
+ [4673] = 37,
+ [4675] = 38,
+ [4677] = 39,
+ [4679] = 40,
+ [4681] = 41,
[4682] = 12,
[4684] = 13,
[4686] = 14,
@@ -3466,6 +4485,116 @@ uint8_t ulp_glb_field_tbl[] = {
[4703] = 17,
[4704] = 18,
[4705] = 19,
+ [4736] = 0,
+ [4737] = 1,
+ [4739] = 20,
+ [4741] = 21,
+ [4743] = 22,
+ [4756] = 2,
+ [4758] = 3,
+ [4760] = 4,
+ [4762] = 5,
+ [4764] = 6,
+ [4766] = 7,
+ [4768] = 8,
+ [4770] = 9,
+ [4772] = 10,
+ [4774] = 11,
+ [4777] = 23,
+ [4779] = 24,
+ [4781] = 25,
+ [4783] = 26,
+ [4785] = 27,
+ [4787] = 28,
+ [4789] = 29,
+ [4791] = 30,
+ [4810] = 12,
+ [4811] = 31,
+ [4812] = 13,
+ [4813] = 32,
+ [4814] = 14,
+ [4815] = 33,
+ [4816] = 15,
+ [4817] = 34,
+ [4830] = 16,
+ [4831] = 17,
+ [4832] = 18,
+ [4833] = 19,
+ [4864] = 0,
+ [4865] = 1,
+ [4867] = 20,
+ [4869] = 21,
+ [4871] = 22,
+ [4884] = 2,
+ [4885] = 23,
+ [4886] = 3,
+ [4887] = 24,
+ [4888] = 4,
+ [4889] = 25,
+ [4890] = 5,
+ [4891] = 26,
+ [4892] = 6,
+ [4893] = 27,
+ [4894] = 7,
+ [4895] = 28,
+ [4896] = 8,
+ [4897] = 29,
+ [4898] = 9,
+ [4899] = 30,
+ [4900] = 10,
+ [4901] = 31,
+ [4902] = 11,
+ [4903] = 32,
+ [4938] = 12,
+ [4939] = 33,
+ [4940] = 13,
+ [4941] = 34,
+ [4942] = 14,
+ [4943] = 35,
+ [4944] = 15,
+ [4945] = 36,
+ [4958] = 16,
+ [4959] = 17,
+ [4960] = 18,
+ [4961] = 19,
+ [4992] = 0,
+ [4993] = 1,
+ [4995] = 20,
+ [4997] = 21,
+ [4999] = 22,
+ [5003] = 33,
+ [5005] = 34,
+ [5007] = 35,
+ [5009] = 36,
+ [5011] = 37,
+ [5012] = 2,
+ [5013] = 23,
+ [5014] = 3,
+ [5015] = 24,
+ [5016] = 4,
+ [5017] = 25,
+ [5018] = 5,
+ [5019] = 26,
+ [5020] = 6,
+ [5021] = 27,
+ [5022] = 7,
+ [5023] = 28,
+ [5024] = 8,
+ [5025] = 29,
+ [5026] = 9,
+ [5027] = 30,
+ [5028] = 10,
+ [5029] = 31,
+ [5030] = 11,
+ [5031] = 32,
+ [5066] = 12,
+ [5068] = 13,
+ [5070] = 14,
+ [5072] = 15,
+ [5086] = 16,
+ [5087] = 17,
+ [5088] = 18,
+ [5089] = 19,
[6144] = 0,
[6145] = 1,
[6146] = 2,
@@ -3705,4 +4834,3 @@ uint8_t ulp_glb_field_tbl[] = {
[7638] = 6,
[7642] = 7
};
-
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
index 223ecbf843..e49c1151d3 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu Jul 8 08:44:00 2021 */
+/* date: Tue Aug 17 12:16:42 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -15,7 +15,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {
/* act_tid: 1, ingress */
[1] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 4,
+ .num_tbls = 5,
.start_tbl_idx = 0,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
@@ -26,7 +26,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {
[2] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
.num_tbls = 6,
- .start_tbl_idx = 4,
+ .start_tbl_idx = 5,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
.cond_start_idx = 3,
@@ -36,7 +36,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {
[3] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
.num_tbls = 4,
- .start_tbl_idx = 10,
+ .start_tbl_idx = 11,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
.cond_start_idx = 4,
@@ -45,8 +45,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {
/* act_tid: 4, egress */
[4] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 4,
- .start_tbl_idx = 14,
+ .num_tbls = 5,
+ .start_tbl_idx = 15,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
.cond_start_idx = 7,
@@ -56,20 +56,20 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {
[5] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
.num_tbls = 4,
- .start_tbl_idx = 18,
+ .start_tbl_idx = 20,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 10,
+ .cond_start_idx = 12,
.cond_nums = 0 }
},
/* act_tid: 6, egress */
[6] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 6,
- .start_tbl_idx = 22,
+ .num_tbls = 12,
+ .start_tbl_idx = 24,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 13,
+ .cond_start_idx = 15,
.cond_nums = 0 }
}
};
@@ -125,14 +125,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
+ .cond_false_goto = 2,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 2,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
.result_start_idx = 1,
.result_bit_size = 0,
.result_num_fields = 0,
@@ -146,7 +145,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 0,
- .cond_false_goto = 0,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 3,
.cond_nums = 0 },
@@ -158,6 +157,26 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.result_bit_size = 128,
.result_num_fields = 17
},
+ { /* act_tid: 1, , table: int_compact_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_COMPACT_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 3,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 65,
+ .result_bit_size = 64,
+ .result_num_fields = 13
+ },
{ /* act_tid: 2, , table: control.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
@@ -187,7 +206,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 65,
+ .result_start_idx = 78,
.result_bit_size = 32,
.result_num_fields = 5
},
@@ -208,13 +227,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 70,
+ .result_start_idx = 83,
.result_bit_size = 64,
.result_num_fields = 1
},
- { /* act_tid: 2, , table: int_full_act_record.0 */
+ { /* act_tid: 2, , table: int_compact_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_type = TF_TBL_TYPE_COMPACT_ACT_RECORD,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
.direction = TF_DIR_RX,
@@ -229,9 +248,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 71,
- .result_bit_size = 128,
- .result_num_fields = 17,
+ .result_start_idx = 84,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
.encap_num_fields = 0
},
{ /* act_tid: 2, , table: mirror_tbl.wr */
@@ -250,7 +269,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 88,
+ .result_start_idx = 97,
.result_bit_size = 32,
.result_num_fields = 5
},
@@ -273,7 +292,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.blob_key_bit_size = 1,
.key_bit_size = 1,
.key_num_fields = 1,
- .result_start_idx = 93,
+ .result_start_idx = 102,
.result_bit_size = 36,
.result_num_fields = 2
},
@@ -292,7 +311,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 95,
+ .result_start_idx = 104,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -311,8 +330,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 96,
+ .result_start_idx = 105,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 47
@@ -332,8 +350,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 143,
+ .result_start_idx = 152,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 47
@@ -353,7 +370,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 190,
+ .result_start_idx = 199,
.result_bit_size = 128,
.result_num_fields = 17
},
@@ -372,7 +389,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 207,
+ .result_start_idx = 216,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -391,8 +408,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 8,
- .result_start_idx = 208,
+ .result_start_idx = 217,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 11
@@ -412,8 +428,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 219,
+ .result_start_idx = 228,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 47
@@ -426,17 +441,36 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 0,
- .cond_false_goto = 0,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
.cond_start_idx = 10,
- .cond_nums = 0 },
+ .cond_nums = 2 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 266,
+ .result_start_idx = 275,
.result_bit_size = 128,
.result_num_fields = 17
},
+ { /* act_tid: 4, , table: int_compact_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_COMPACT_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 12,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 292,
+ .result_bit_size = 64,
+ .result_num_fields = 13
+ },
{ /* act_tid: 5, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
@@ -447,12 +481,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 10,
+ .cond_start_idx = 12,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 283,
+ .result_start_idx = 305,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -466,13 +500,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 2,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 11,
+ .cond_start_idx = 13,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 284,
+ .result_start_idx = 306,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 47
@@ -487,13 +520,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 12,
+ .cond_start_idx = 14,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 331,
+ .result_start_idx = 353,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 47
@@ -508,12 +540,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 13,
+ .cond_start_idx = 15,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 378,
+ .result_start_idx = 400,
.result_bit_size = 128,
.result_num_fields = 17
},
@@ -527,15 +559,48 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 13,
+ .cond_start_idx = 15,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 395,
+ .result_start_idx = 417,
.result_bit_size = 64,
.result_num_fields = 1
},
+ { /* act_tid: 6, , table: source_property_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 16,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2,
+ .blob_key_bit_size = 80,
+ .key_bit_size = 80,
+ .key_num_fields = 2,
+ .ident_start_idx = 1,
+ .ident_nums = 1
+ },
+ { /* act_tid: 6, , table: control.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 17,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
{ /* act_tid: 6, , table: sp_smac_ipv4.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
@@ -546,17 +611,40 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 14,
+ .cond_start_idx = 18,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
.record_size = 16,
- .result_start_idx = 396,
+ .result_start_idx = 418,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 3
},
+ { /* act_tid: 6, , table: source_property_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 19,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 4,
+ .blob_key_bit_size = 80,
+ .key_bit_size = 80,
+ .key_num_fields = 2,
+ .result_start_idx = 421,
+ .result_bit_size = 48,
+ .result_num_fields = 2
+ },
{ /* act_tid: 6, , table: sp_smac_ipv6.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
@@ -567,17 +655,50 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 15,
+ .cond_start_idx = 19,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.record_size = 32,
- .result_start_idx = 399,
+ .result_start_idx = 423,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 3
},
+ { /* act_tid: 6, , table: vxlan_encap_rec_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 20,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 6,
+ .blob_key_bit_size = 136,
+ .key_bit_size = 136,
+ .key_num_fields = 5,
+ .ident_start_idx = 2,
+ .ident_nums = 1
+ },
+ { /* act_tid: 6, , table: control.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 22,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
{ /* act_tid: 6, , table: int_tun_encap_record.ipv4_vxlan */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
@@ -588,17 +709,39 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 16,
+ .cond_start_idx = 23,
.cond_nums = 2 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 402,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .result_start_idx = 426,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 30
},
+ { /* act_tid: 6, , table: vxlan_encap_rec_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 25,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 11,
+ .blob_key_bit_size = 136,
+ .key_bit_size = 136,
+ .key_num_fields = 5,
+ .result_start_idx = 456,
+ .result_bit_size = 48,
+ .result_num_fields = 2
+ },
{ /* act_tid: 6, , table: int_tun_encap_record.ipv6_vxlan */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
@@ -609,13 +752,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 18,
+ .cond_start_idx = 25,
.cond_nums = 2 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 432,
+ .result_start_idx = 458,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 30
@@ -630,13 +772,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 20,
+ .cond_start_idx = 27,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 462,
+ .result_start_idx = 488,
.result_bit_size = 128,
.result_num_fields = 17
}
@@ -693,6 +835,15 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
.cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
},
+ /* cond_execute: act_tid: 4, int_full_act_record.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
+ },
/* cond_execute: act_tid: 5, int_flow_counter_tbl.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
@@ -713,6 +864,16 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
.cond_operand = BNXT_ULP_ACT_BIT_COUNT
},
+ /* cond_execute: act_tid: 6, source_property_cache.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG
+ },
+ /* cond_execute: act_tid: 6, control.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
/* cond_execute: act_tid: 6, sp_smac_ipv4.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
@@ -723,6 +884,20 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
.cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG
},
+ /* cond_execute: act_tid: 6, vxlan_encap_rec_cache.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: act_tid: 6, control.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
/* cond_execute: act_tid: 6, int_tun_encap_record.ipv4_vxlan */
{
.cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
@@ -783,6 +958,316 @@ struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = {
(BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
}
+ },
+ /* act_tid: 6, , table: source_property_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ipv4_src_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "ipv4_src_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}
+ }
+ },
+ /* act_tid: 6, , table: source_property_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ipv4_src_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "ipv4_src_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}
+ }
+ },
+ /* act_tid: 6, , table: vxlan_encap_rec_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ipv4_dst_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "ipv4_dst_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
+ }
+ },
+ /* act_tid: 6, , table: vxlan_encap_rec_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ipv4_dst_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "ipv4_dst_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
+ }
}
};
@@ -1069,38 +1554,178 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "encap_ptr",
- .field_bit_size = 16,
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr2 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_DECAP_FUNC_THRU_TUN},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_DECAP_FUNC_NONE}
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr2 = {
+ (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_RF,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr2 = {
- (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff},
+ ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER},
.field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd1",
- .field_bit_size = 16,
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 1, , table: int_compact_act_record.0 */
+ {
.description = "rsvd0",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
@@ -1137,7 +1762,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -1233,9 +1860,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "type",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
/* act_tid: 2, , table: mirror_tbl.alloc */
{
@@ -1277,31 +1902,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 2, , table: int_full_act_record.0 */
- {
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "encap_ptr",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "rsvd1",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
+ /* act_tid: 2, , table: int_compact_act_record.0 */
{
.description = "rsvd0",
.field_bit_size = 8,
@@ -1324,7 +1925,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -1387,9 +1990,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "type",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
/* act_tid: 2, , table: mirror_tbl.wr */
{
@@ -2250,7 +2851,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -2721,16 +3324,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
+ 1}
},
{
.description = "stats_ptr",
@@ -2803,6 +3399,102 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_opr1 = {
1}
},
+ /* act_tid: 4, , table: int_compact_act_record.0 */
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
/* act_tid: 5, , table: int_flow_counter_tbl.0 */
{
.description = "count",
@@ -3708,6 +4400,25 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* act_tid: 6, , table: source_property_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_SP_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_SP_PTR & 0xff}
+ },
/* act_tid: 6, , table: sp_smac_ipv6.0 */
{
.description = "smac",
@@ -4021,6 +4732,25 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
(BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff,
BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}
},
+ /* act_tid: 6, , table: vxlan_encap_rec_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "enc_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
+ },
/* act_tid: 6, , table: int_tun_encap_record.ipv6_vxlan */
{
.description = "ecv_valid",
@@ -4351,7 +5081,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -4424,5 +5156,19 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_act_ident_list[] = {
.regfile_idx = BNXT_ULP_RF_IDX_MIRROR_ID_0,
.ident_bit_size = 4,
.ident_bit_pos = 32
+ },
+ /* act_tid: 6, , table: source_property_cache.rd */
+ {
+ .description = "sp_rec_ptr",
+ .regfile_idx = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
+ .ident_bit_size = 16,
+ .ident_bit_pos = 32
+ },
+ /* act_tid: 6, , table: vxlan_encap_rec_cache.rd */
+ {
+ .description = "enc_rec_ptr",
+ .regfile_idx = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .ident_bit_size = 16,
+ .ident_bit_pos = 32
}
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
index bcb204ae13..68c1e292b2 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Fri Jul 30 09:57:44 2021 */
+/* date: Fri Aug 20 18:05:25 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -25,7 +25,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {
/* class_tid: 2, ingress */
[2] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 17,
+ .num_tbls = 24,
.start_tbl_idx = 28,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
@@ -35,18 +35,18 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {
/* class_tid: 3, egress */
[3] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 24,
- .start_tbl_idx = 45,
+ .num_tbls = 18,
+ .start_tbl_idx = 52,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 36,
+ .cond_start_idx = 39,
.cond_nums = 0 }
},
/* class_tid: 4, ingress */
[4] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
.num_tbls = 21,
- .start_tbl_idx = 69,
+ .start_tbl_idx = 70,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
.cond_start_idx = 48,
@@ -55,8 +55,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {
/* class_tid: 5, egress */
[5] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 24,
- .start_tbl_idx = 90,
+ .num_tbls = 25,
+ .start_tbl_idx = 91,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
.cond_start_idx = 52,
@@ -855,18 +855,28 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
+ { /* class_tid: 2, , table: control.ipv6_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 8,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 32,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_ipv6_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 32,
- .cond_nums = 0 },
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 33,
+ .cond_nums = 1 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
@@ -875,38 +885,57 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.key_bit_size = 14,
.key_num_fields = 3,
.ident_start_idx = 19,
- .ident_nums = 3
+ .ident_nums = 4
},
- { /* class_tid: 2, , table: control.profile_tcam_cache.f2_check */
+ { /* class_tid: 2, , table: control.f2_ipv6_prof_cache_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 4,
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 32,
+ .cond_start_idx = 34,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 2, , table: fkb_select.f2_wm */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
+ { /* class_tid: 2, , table: control.f2_v6_conflict_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
+ .cond_true_goto = 4,
+ .cond_false_goto = 1023,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 33,
+ .cond_start_idx = 35,
.cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
- .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .func_info = {
+ .func_opc = BNXT_ULP_FUNC_OPC_EQ,
+ .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
+ .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
+ .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
+ },
+ { /* class_tid: 2, , table: fkb_select.f2_l2_l3_l4_v6_em */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 36,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
.result_start_idx = 426,
.result_bit_size = 106,
.result_num_fields = 106
},
- { /* class_tid: 2, , table: profile_tcam.f2 */
+ { /* class_tid: 2, , table: profile_tcam.f2_l2_l3_l4_v6_em */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.direction = TF_DIR_RX,
@@ -914,14 +943,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 34,
+ .cond_start_idx = 36,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
- .pri_operand = 1,
+ .pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.key_start_idx = 1146,
@@ -930,9 +959,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.key_num_fields = 43,
.result_start_idx = 532,
.result_bit_size = 33,
- .result_num_fields = 8
+ .result_num_fields = 8,
+ .ident_start_idx = 23,
+ .ident_nums = 1
},
- { /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_l2_l3_l4_v6_wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
@@ -942,7 +973,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 34,
+ .cond_start_idx = 36,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
@@ -955,135 +986,81 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 138,
.result_num_fields = 7
},
- { /* class_tid: 2, , table: wm.l3_l4.ipv4 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ { /* class_tid: 2, , table: em.f2_l2_l3_l4_v6.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_INTERNAL,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 0,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 34,
- .cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 36,
+ .cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
- .pri_operand = 0,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.key_start_idx = 1192,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
.result_start_idx = 547,
- .result_bit_size = 38,
- .result_num_fields = 5
- },
- { /* class_tid: 2, , table: wm.l3_l4.ipv6 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 0,
- .cond_false_goto = 0,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 35,
- .cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
- .pri_operand = 0,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1306,
- .blob_key_bit_size = 0,
- .key_bit_size = 0,
- .key_num_fields = 114,
- .result_start_idx = 552,
- .result_bit_size = 38,
- .result_num_fields = 5
- },
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 6,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 36,
- .cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1420,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .ident_start_idx = 22,
- .ident_nums = 1
+ .result_bit_size = 0,
+ .result_num_fields = 6
},
- { /* class_tid: 3, , table: mac_addr_cache.rd */
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 37,
+ .cond_start_idx = 36,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1421,
- .blob_key_bit_size = 73,
- .key_bit_size = 73,
- .key_num_fields = 5,
- .ident_start_idx = 23,
- .ident_nums = 1
+ .key_start_idx = 1306,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .ident_start_idx = 24,
+ .ident_nums = 3
},
- { /* class_tid: 3, , table: control.0 */
+ { /* class_tid: 2, , table: control.profile_tcam_cache.f2_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 4,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 37,
+ .cond_start_idx = 36,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 3, , table: port_table.egr.rd */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
- .direction = TF_DIR_TX,
+ { /* class_tid: 2, , table: fkb_select.f2_wm */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 38,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 37,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .key_start_idx = 1426,
- .blob_key_bit_size = 10,
- .key_bit_size = 10,
- .key_num_fields = 1,
- .ident_start_idx = 24,
- .ident_nums = 3
+ .result_start_idx = 553,
+ .result_bit_size = 106,
+ .result_num_fields = 106
},
- { /* class_tid: 3, , table: l2_cntxt_tcam.0 */
+ { /* class_tid: 2, , table: profile_tcam.f2 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .direction = TF_DIR_TX,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
@@ -1091,26 +1068,27 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_start_idx = 38,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
- .pri_operand = 0,
- .key_start_idx = 1427,
- .blob_key_bit_size = 213,
- .key_bit_size = 213,
- .key_num_fields = 21,
- .result_start_idx = 557,
- .result_bit_size = 43,
- .result_num_fields = 6,
- .ident_start_idx = 27,
- .ident_nums = 1
+ .pri_operand = 1,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 1309,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 659,
+ .result_bit_size = 33,
+ .result_num_fields = 8
},
- { /* class_tid: 3, , table: mac_addr_cache.wr */
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
@@ -1118,15 +1096,61 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_start_idx = 38,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1448,
- .blob_key_bit_size = 73,
- .key_bit_size = 73,
- .key_num_fields = 5,
- .result_start_idx = 563,
- .result_bit_size = 62,
- .result_num_fields = 4
+ .key_start_idx = 1352,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .result_start_idx = 667,
+ .result_bit_size = 138,
+ .result_num_fields = 7
+ },
+ { /* class_tid: 2, , table: wm.l3_l4.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 38,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 1355,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 674,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 39,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1469,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 27,
+ .ident_nums = 1
},
{ /* class_tid: 3, , table: control.ipv6_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
@@ -1135,7 +1159,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 8,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 38,
+ .cond_start_idx = 39,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
@@ -1148,12 +1172,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1023,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 39,
+ .cond_start_idx = 40,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1453,
+ .key_start_idx = 1470,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -1167,7 +1191,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 2,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 40,
+ .cond_start_idx = 41,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
@@ -1179,7 +1203,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 4,
.cond_false_goto = 1023,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 41,
+ .cond_start_idx = 42,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.func_info = {
@@ -1198,13 +1222,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .result_start_idx = 567,
+ .result_start_idx = 679,
.result_bit_size = 106,
.result_num_fields = 106
},
@@ -1216,7 +1240,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
@@ -1226,11 +1250,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 1456,
+ .key_start_idx = 1473,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
- .result_start_idx = 673,
+ .result_start_idx = 785,
.result_bit_size = 33,
.result_num_fields = 8,
.ident_start_idx = 32,
@@ -1246,16 +1270,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1499,
+ .key_start_idx = 1516,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
- .result_start_idx = 681,
+ .result_start_idx = 793,
.result_bit_size = 138,
.result_num_fields = 7
},
@@ -1267,15 +1291,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1502,
+ .key_start_idx = 1519,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
- .result_start_idx = 688,
+ .result_start_idx = 800,
.result_bit_size = 0,
.result_num_fields = 6
},
@@ -1288,12 +1312,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1616,
+ .key_start_idx = 1633,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -1304,32 +1328,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 2,
- .cond_false_goto = 1,
+ .cond_true_goto = 1,
+ .cond_false_goto = 5,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 3, , table: control.conflict_check */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 5,
- .cond_false_goto = 1023,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 43,
- .cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .func_info = {
- .func_opc = BNXT_ULP_FUNC_OPC_EQ,
- .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
- .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
- .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
- .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
- .func_dst_opr = BNXT_ULP_RF_IDX_CC }
- },
{ /* class_tid: 3, , table: fkb_select.l3_l4_wc */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
@@ -1343,7 +1349,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 694,
+ .result_start_idx = 806,
.result_bit_size = 106,
.result_num_fields = 106
},
@@ -1365,11 +1371,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 1619,
+ .key_start_idx = 1636,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
- .result_start_idx = 800,
+ .result_start_idx = 912,
.result_bit_size = 33,
.result_num_fields = 8,
.ident_start_idx = 35,
@@ -1393,11 +1399,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 1662,
+ .key_start_idx = 1679,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
- .result_start_idx = 808,
+ .result_start_idx = 920,
.result_bit_size = 33,
.result_num_fields = 8,
.ident_start_idx = 35,
@@ -1418,11 +1424,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1705,
+ .key_start_idx = 1722,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
- .result_start_idx = 816,
+ .result_start_idx = 928,
.result_bit_size = 138,
.result_num_fields = 7
},
@@ -1443,11 +1449,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1708,
+ .key_start_idx = 1725,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
- .result_start_idx = 823,
+ .result_start_idx = 935,
.result_bit_size = 38,
.result_num_fields = 5
},
@@ -1468,11 +1474,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1822,
+ .key_start_idx = 1839,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
- .result_start_idx = 828,
+ .result_start_idx = 940,
.result_bit_size = 38,
.result_num_fields = 5
},
@@ -1493,11 +1499,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1936,
+ .key_start_idx = 1953,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
- .result_start_idx = 833,
+ .result_start_idx = 945,
.result_bit_size = 38,
.result_num_fields = 5
},
@@ -1517,7 +1523,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 838,
+ .result_start_idx = 950,
.result_bit_size = 128,
.result_num_fields = 17
},
@@ -1535,11 +1541,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2050,
+ .key_start_idx = 2067,
.blob_key_bit_size = 10,
.key_bit_size = 10,
.key_num_fields = 1,
- .result_start_idx = 855,
+ .result_start_idx = 967,
.result_bit_size = 152,
.result_num_fields = 5
},
@@ -1557,7 +1563,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2051,
+ .key_start_idx = 2068,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1594,11 +1600,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 2052,
+ .key_start_idx = 2069,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
- .result_start_idx = 860,
+ .result_start_idx = 972,
.result_bit_size = 43,
.result_num_fields = 6,
.ident_start_idx = 35,
@@ -1618,11 +1624,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2073,
+ .key_start_idx = 2090,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .result_start_idx = 866,
+ .result_start_idx = 978,
.result_bit_size = 62,
.result_num_fields = 4
},
@@ -1639,7 +1645,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 870,
+ .result_start_idx = 982,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -1656,7 +1662,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 871,
+ .result_start_idx = 983,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -1676,7 +1682,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 872,
+ .result_start_idx = 984,
.result_bit_size = 128,
.result_num_fields = 17,
.encap_num_fields = 0
@@ -1695,11 +1701,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2074,
+ .key_start_idx = 2091,
.blob_key_bit_size = 10,
.key_bit_size = 10,
.key_num_fields = 1,
- .result_start_idx = 889,
+ .result_start_idx = 1001,
.result_bit_size = 152,
.result_num_fields = 5
},
@@ -1728,7 +1734,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2075,
+ .key_start_idx = 2092,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1761,7 +1767,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .result_start_idx = 894,
+ .result_start_idx = 1006,
.result_bit_size = 64,
.result_num_fields = 8
},
@@ -1779,11 +1785,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2076,
+ .key_start_idx = 2093,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .result_start_idx = 902,
+ .result_start_idx = 1014,
.result_bit_size = 62,
.result_num_fields = 4
},
@@ -1801,7 +1807,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2077,
+ .key_start_idx = 2094,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1836,11 +1842,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 2078,
+ .key_start_idx = 2095,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
- .result_start_idx = 906,
+ .result_start_idx = 1018,
.result_bit_size = 43,
.result_num_fields = 6,
.ident_start_idx = 36,
@@ -1860,11 +1866,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2099,
+ .key_start_idx = 2116,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .result_start_idx = 912,
+ .result_start_idx = 1024,
.result_bit_size = 62,
.result_num_fields = 4
},
@@ -1881,7 +1887,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 916,
+ .result_start_idx = 1028,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -1898,7 +1904,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 917,
+ .result_start_idx = 1029,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -1918,11 +1924,33 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 918,
+ .result_start_idx = 1030,
.result_bit_size = 128,
.result_num_fields = 17,
.encap_num_fields = 0
},
+ { /* class_tid: 5, , table: port_table.egr_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2117,
+ .blob_key_bit_size = 10,
+ .key_bit_size = 10,
+ .key_num_fields = 1,
+ .result_start_idx = 1047,
+ .result_bit_size = 152,
+ .result_num_fields = 5
+ },
{ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
@@ -1937,7 +1965,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2100,
+ .key_start_idx = 2118,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1972,11 +2000,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .key_start_idx = 2101,
+ .key_start_idx = 2119,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
- .result_start_idx = 935,
+ .result_start_idx = 1052,
.result_bit_size = 43,
.result_num_fields = 6,
.ident_start_idx = 37,
@@ -1996,11 +2024,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2122,
+ .key_start_idx = 2140,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .result_start_idx = 941,
+ .result_start_idx = 1058,
.result_bit_size = 62,
.result_num_fields = 4
},
@@ -2017,7 +2045,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 945,
+ .result_start_idx = 1062,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -2034,7 +2062,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 946,
+ .result_start_idx = 1063,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -2054,7 +2082,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
- .result_start_idx = 947,
+ .result_start_idx = 1064,
.result_bit_size = 128,
.result_num_fields = 17,
.encap_num_fields = 0
@@ -2072,7 +2100,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_SVIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 964,
+ .result_start_idx = 1081,
.result_bit_size = 64,
.result_num_fields = 8
},
@@ -2091,7 +2119,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2123,
+ .key_start_idx = 2141,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -2124,7 +2152,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .result_start_idx = 972,
+ .result_start_idx = 1089,
.result_bit_size = 64,
.result_num_fields = 8
},
@@ -2142,11 +2170,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2124,
+ .key_start_idx = 2142,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .result_start_idx = 980,
+ .result_start_idx = 1097,
.result_bit_size = 62,
.result_num_fields = 4
},
@@ -2165,7 +2193,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 984,
+ .result_start_idx = 1101,
.result_bit_size = 16,
.result_num_fields = 1
},
@@ -2184,8 +2212,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 985,
+ .result_start_idx = 1102,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 47
@@ -2206,7 +2233,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 1032,
+ .result_start_idx = 1149,
.result_bit_size = 128,
.result_num_fields = 17
},
@@ -2224,7 +2251,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2125,
+ .key_start_idx = 2143,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -2261,11 +2288,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 2126,
+ .key_start_idx = 2144,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
- .result_start_idx = 1049,
+ .result_start_idx = 1166,
.result_bit_size = 43,
.result_num_fields = 6,
.ident_start_idx = 38,
@@ -2284,7 +2311,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 1055,
+ .result_start_idx = 1172,
.result_bit_size = 106,
.result_num_fields = 106
},
@@ -2306,11 +2333,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 2147,
+ .key_start_idx = 2165,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
- .result_start_idx = 1161,
+ .result_start_idx = 1278,
.result_bit_size = 33,
.result_num_fields = 8
},
@@ -2325,15 +2352,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 55,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2190,
+ .key_start_idx = 2208,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .ident_start_idx = 38,
- .ident_nums = 1
+ .result_start_idx = 1286,
+ .result_bit_size = 62,
+ .result_num_fields = 4
},
{ /* class_tid: 5, , table: int_full_act_record.vfr_ing0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2351,7 +2379,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 1169,
+ .result_start_idx = 1290,
.result_bit_size = 128,
.result_num_fields = 17
},
@@ -2367,11 +2395,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 2191,
+ .key_start_idx = 2209,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
- .result_start_idx = 1186,
+ .result_start_idx = 1307,
.result_bit_size = 0,
.result_num_fields = 6
}
@@ -2529,6 +2557,26 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
+ /* cond_execute: class_tid: 2, control.ipv6_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6
+ },
+ /* cond_execute: class_tid: 2, profile_tcam_cache.f2_ipv6_rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH
+ },
+ /* cond_execute: class_tid: 2, control.f2_ipv6_prof_cache_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 2, control.f2_v6_conflict_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_CC
+ },
/* cond_execute: class_tid: 2, control.profile_tcam_cache.f2_check */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
@@ -2544,21 +2592,6 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
},
- /* cond_execute: class_tid: 2, wm.l3_l4.ipv6 */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
- .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
- },
- /* cond_execute: class_tid: 3, l2_cntxt_tcam_cache.rd */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET,
- .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC
- },
- /* cond_execute: class_tid: 3, control.0 */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
- .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
- },
/* cond_execute: class_tid: 3, control.ipv6_check */
{
.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
@@ -2584,11 +2617,6 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 3, control.conflict_check */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
- .cond_operand = BNXT_ULP_RF_IDX_CC
- },
/* cond_execute: class_tid: 3, profile_tcam.l3_l4.ip */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
@@ -5115,12 +5143,24 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -8346,7 +8386,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr1 = {
(BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
@@ -8373,7 +8416,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr1 = {
(BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
@@ -15050,7 +15096,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr1 = {
(BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
@@ -15077,7 +15126,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr1 = {
(BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
@@ -16551,7 +16603,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr1 = {
(BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
@@ -16578,7 +16633,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr1 = {
(BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
@@ -18283,7 +18341,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
- /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_ipv6_rd */
{
.field_info_mask = {
.description = "recycle_cnt",
@@ -18338,7 +18396,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
}
},
- /* class_tid: 2, , table: profile_tcam.f2 */
+ /* class_tid: 2, , table: profile_tcam.f2_l2_l3_l4_v6_em */
{
.field_info_mask = {
.description = "l4_hdr_is_udp_tcp",
@@ -18357,14 +18415,34 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l4_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l4_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_I_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_UDP}
}
},
{
@@ -18372,7 +18450,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l4_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4 & 0xff}
},
.field_info_spec = {
.description = "l4_hdr_error",
@@ -18386,13 +18467,19 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l4_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4 & 0xff}
},
.field_info_spec = {
.description = "l4_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4 & 0xff}
}
},
{
@@ -18456,13 +18543,17 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l3_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
.description = "l3_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
}
},
{
@@ -18470,7 +18561,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l3_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
.description = "l3_hdr_error",
@@ -18484,13 +18577,17 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
.description = "l3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
}
},
{
@@ -18526,7 +18623,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l2_uc_mc_bc",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
.description = "l2_uc_mc_bc",
@@ -18990,15 +19089,13 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
1}
}
},
- /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_l2_l3_l4_v6_wr */
{
.field_info_mask = {
.description = "recycle_cnt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "recycle_cnt",
@@ -19045,10 +19142,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
}
},
- /* class_tid: 2, , table: wm.l3_l4.ipv4 */
+ /* class_tid: 2, , table: em.f2_l2_l3_l4_v6.0 */
{
.field_info_mask = {
- .description = "wc_profile_id",
+ .description = "em_profile_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
@@ -19056,13 +19153,13 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "wc_profile_id",
+ .description = "em_profile_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 & 0xff}
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
}
},
{
@@ -19401,20 +19498,12 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "tl3.dip.ipv4",
.field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
.description = "tl3.dip.ipv4",
.field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
@@ -19766,7 +19855,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr2 = {
(BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
.field_info_spec = {
.description = "tids",
@@ -19780,7 +19869,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr2 = {
(BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -19879,12 +19968,30 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
.field_info_spec = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -20059,12 +20166,30 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.sip.ipv6",
.field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
.field_info_spec = {
.description = "l3.sip.ipv6",
.field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -20083,42 +20208,42 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.dip.ipv4",
.field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
.description = "l3.dip.ipv4",
.field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
.description = "l3.dip.ipv6",
.field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
.field_info_spec = {
.description = "l3.dip.ipv6",
.field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -20149,12 +20274,24 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -20341,24 +20478,50 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l4.src",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
.description = "l4.src",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
.field_info_mask = {
.description = "l4.dst",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
.description = "l4.dst",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -20481,2254 +20644,2585 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
- /* class_tid: 2, , table: wm.l3_l4.ipv6 */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
{
.field_info_mask = {
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 & 0xff}
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
}
},
+ /* class_tid: 2, , table: profile_tcam.f2 */
{
.field_info_mask = {
- .description = "parif",
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "parif",
+ .description = "l4_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "lcos",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "lcos",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "meta",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "meta",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "rcyc_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "rcyc_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "loopback",
+ .description = "l3_hdr_isIP",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "loopback",
+ .description = "l3_hdr_isIP",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_l2type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_l2type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl2_dt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_dt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_sa",
+ .description = "l2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_sa",
+ .description = "l2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_nvt",
+ .description = "l2_uc_mc_bc",
.field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_nvt",
+ .description = "l2_uc_mc_bc",
.field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ovp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovd",
+ .description = "l2_hdr_error",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ovd",
+ .description = "l2_hdr_error",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ovv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L2_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl2_ovt",
+ .description = "tun_hdr_flags",
.field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovt",
+ .description = "tun_hdr_flags",
.field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ivp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivd",
+ .description = "tun_hdr_err",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ivd",
+ .description = "tun_hdr_err",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl2_ivv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ivv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ivt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl2_etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.l3type",
+ .description = "tl4_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.l3type",
+ .description = "tl4_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL4_HDR_TYPE_UDP}
}
},
{
.field_info_mask = {
- .description = "tl3.sip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.sip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.sip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.sip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL4_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl3.sip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.sip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.dip.ipv4",
- .field_bit_size = 32,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.dip.ipv4",
- .field_bit_size = 32,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.dip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.dip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.dip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.dip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl3.fid.ipv4",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.fid.ipv4",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl3.fid.ipv6",
- .field_bit_size = 20,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.fid.ipv6",
- .field_bit_size = 20,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl3.qos",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.qos",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl3.ieh_nonext",
+ .description = "tl3_hdr_error",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.ieh_nonext",
+ .description = "tl3_hdr_error",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_esp",
+ .description = "tl3_hdr_valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.ieh_esp",
+ .description = "tl3_hdr_valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL3_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_auth",
+ .description = "tl2_two_vtags",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.ieh_auth",
+ .description = "tl2_two_vtags",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_dest",
+ .description = "tl2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.ieh_dest",
+ .description = "tl2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_hop",
+ .description = "tl2_hdr_valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.ieh_hop",
+ .description = "tl2_hdr_valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL2_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_1frag",
+ .description = "hrec_next",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.ieh_1frag",
+ .description = "hrec_next",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl3.l3err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.l3err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
.field_info_spec = {
- .description = "tl4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
}
},
+ /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
{
.field_info_mask = {
- .description = "tl4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
}
},
+ /* class_tid: 2, , table: wm.l3_l4.ipv4 */
{
.field_info_mask = {
- .description = "tl4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "tl4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
}
},
{
.field_info_mask = {
- .description = "tuntype",
+ .description = "parif",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tuntype",
+ .description = "parif",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tflags",
- .field_bit_size = 3,
+ .description = "spif",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tflags",
- .field_bit_size = 3,
+ .description = "spif",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tids",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tids",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "tid",
- .field_bit_size = 32,
+ .description = "svif",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tid",
- .field_bit_size = 32,
+ .description = "svif",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tctxts",
- .field_bit_size = 24,
+ .description = "lcos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tctxts",
- .field_bit_size = 24,
+ .description = "lcos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tctxt",
- .field_bit_size = 32,
+ .description = "meta",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tctxt",
- .field_bit_size = 32,
+ .description = "meta",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tqos",
- .field_bit_size = 3,
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tqos",
- .field_bit_size = 3,
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "terr",
- .field_bit_size = 4,
+ .description = "loopback",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "terr",
- .field_bit_size = 4,
+ .description = "loopback",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_l2type",
+ .description = "tl2_l2type",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_l2type",
+ .description = "tl2_l2type",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_dmac",
+ .description = "tl2_dmac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_dmac",
+ .description = "tl2_dmac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_smac",
+ .description = "tl2_smac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_smac",
+ .description = "tl2_smac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_dt",
+ .description = "tl2_dt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_dt",
+ .description = "tl2_dt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_sa",
+ .description = "tl2_sa",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_sa",
+ .description = "tl2_sa",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_nvt",
+ .description = "tl2_nvt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_nvt",
+ .description = "tl2_nvt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovp",
+ .description = "tl2_ovp",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovp",
+ .description = "tl2_ovp",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovd",
+ .description = "tl2_ovd",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovd",
+ .description = "tl2_ovd",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovv",
+ .description = "tl2_ovv",
.field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovv",
+ .description = "tl2_ovv",
.field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovt",
+ .description = "tl2_ovt",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovt",
+ .description = "tl2_ovt",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivp",
+ .description = "tl2_ivp",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivp",
+ .description = "tl2_ivp",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivd",
+ .description = "tl2_ivd",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivd",
+ .description = "tl2_ivd",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivv",
+ .description = "tl2_ivv",
.field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivv",
+ .description = "tl2_ivv",
.field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivt",
+ .description = "tl2_ivt",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivt",
+ .description = "tl2_ivt",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_etype",
+ .description = "tl2_etype",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_etype",
+ .description = "tl2_etype",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.l3type",
+ .description = "tl3.l3type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.l3type",
+ .description = "tl3.l3type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.sip.ipv4",
+ .description = "tl3.sip.ipv4",
.field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.sip.ipv4",
+ .description = "tl3.sip.ipv4",
.field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.sip.ipv6",
+ .description = "tl3.sip.ipv6",
.field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.sip.ipv6",
+ .description = "tl3.sip.ipv6",
.field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.sip_selcmp.ipv6",
+ .description = "tl3.sip_selcmp.ipv6",
.field_bit_size = 72,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.sip_selcmp.ipv6",
+ .description = "tl3.sip_selcmp.ipv6",
.field_bit_size = 72,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.dip.ipv4",
+ .description = "tl3.dip.ipv4",
.field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.dip.ipv4",
+ .description = "tl3.dip.ipv4",
.field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.dip.ipv6",
+ .description = "tl3.dip.ipv6",
.field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.dip.ipv6",
+ .description = "tl3.dip.ipv6",
.field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.dip_selcmp.ipv6",
+ .description = "tl3.dip_selcmp.ipv6",
.field_bit_size = 72,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.dip_selcmp.ipv6",
+ .description = "tl3.dip_selcmp.ipv6",
.field_bit_size = 72,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ttl",
+ .description = "tl3.ttl",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ttl",
+ .description = "tl3.ttl",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.prot",
+ .description = "tl3.prot",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.prot",
+ .description = "tl3.prot",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.fid.ipv4",
+ .description = "tl3.fid.ipv4",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.fid.ipv4",
+ .description = "tl3.fid.ipv4",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.fid.ipv6",
+ .description = "tl3.fid.ipv6",
.field_bit_size = 20,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.fid.ipv6",
+ .description = "tl3.fid.ipv6",
.field_bit_size = 20,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.qos",
+ .description = "tl3.qos",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.qos",
+ .description = "tl3.qos",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_nonext",
+ .description = "tl3.ieh_nonext",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_nonext",
+ .description = "tl3.ieh_nonext",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_esp",
+ .description = "tl3.ieh_esp",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_esp",
+ .description = "tl3.ieh_esp",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_auth",
+ .description = "tl3.ieh_auth",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_auth",
+ .description = "tl3.ieh_auth",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_dest",
+ .description = "tl3.ieh_dest",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_dest",
+ .description = "tl3.ieh_dest",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_frag",
+ .description = "tl3.ieh_frag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_frag",
+ .description = "tl3.ieh_frag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_rthdr",
+ .description = "tl3.ieh_rthdr",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_rthdr",
+ .description = "tl3.ieh_rthdr",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_hop",
+ .description = "tl3.ieh_hop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_hop",
+ .description = "tl3.ieh_hop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_1frag",
+ .description = "tl3.ieh_1frag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_1frag",
+ .description = "tl3.ieh_1frag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.df",
+ .description = "tl3.df",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.df",
+ .description = "tl3.df",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.l3err.ipv4",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.l3err.ipv4",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "l3.l3err.ipv6",
+ .description = "tl3.l3err",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.l3err.ipv6",
+ .description = "tl3.l3err",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.l4type",
+ .description = "tl4.l4type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.l4type",
+ .description = "tl4.l4type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.src",
+ .description = "tl4.src",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.src",
+ .description = "tl4.src",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.dst",
+ .description = "tl4.dst",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.dst",
+ .description = "tl4.dst",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.flags",
+ .description = "tl4.flags",
.field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.flags",
+ .description = "tl4.flags",
.field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.seq",
+ .description = "tl4.seq",
.field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.seq",
+ .description = "tl4.seq",
.field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.ack",
- .field_bit_size = 32,
+ .description = "tl4.pa",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.ack",
- .field_bit_size = 32,
+ .description = "tl4.pa",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.win",
- .field_bit_size = 16,
+ .description = "tl4.opt",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.win",
- .field_bit_size = 16,
+ .description = "tl4.opt",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.pa",
+ .description = "tl4.tcpts",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.pa",
+ .description = "tl4.tcpts",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.opt",
- .field_bit_size = 1,
+ .description = "tl4.err",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.opt",
- .field_bit_size = 1,
+ .description = "tl4.err",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.tcpts",
- .field_bit_size = 1,
+ .description = "tuntype",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.tcpts",
- .field_bit_size = 1,
+ .description = "tuntype",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.tsval",
- .field_bit_size = 32,
+ .description = "tflags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.tsval",
- .field_bit_size = 32,
+ .description = "tflags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.txecr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l4.txecr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4.err",
- .field_bit_size = 4,
+ .description = "tid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.err",
- .field_bit_size = 4,
+ .description = "tid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
- /* class_tid: 3, , table: mac_addr_cache.rd */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "mac_addr",
+ .description = "l2_dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "mac_addr",
+ .description = "l2_dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
}
},
- /* class_tid: 3, , table: port_table.egr.rd */
{
.field_info_mask = {
- .description = "dev.port_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- 0xff,
- 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "dev.port_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam.0 */
{
.field_info_mask = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_tpid_sel",
+ .description = "l2_ovp",
.field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovlan_tpid_sel",
+ .description = "l2_ovp",
.field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- }
- },
- {
- .field_info_mask = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
- /* class_tid: 3, , table: mac_addr_cache.wr */
{
.field_info_mask = {
- .description = "svif",
+ .description = "l3.ttl",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "svif",
+ .description = "l3.ttl",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ (BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ (BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
- /* class_tid: 3, , table: profile_tcam_cache.ipv6_rd */
{
.field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
- /* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */
{
.field_info_mask = {
- .description = "l4_hdr_is_udp_tcp",
+ .description = "l3.ieh_dest",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4_hdr_is_udp_tcp",
+ .description = "l3.ieh_dest",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_THOR_SYM_L4_HDR_TYPE_TCP},
- .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr3 = {
- ULP_THOR_SYM_L4_HDR_TYPE_UDP}
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4_hdr_error",
+ .description = "l3.ieh_rthdr",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4_hdr_error",
+ .description = "l3.ieh_rthdr",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4_hdr_valid",
+ .description = "l3.ieh_hop",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4_hdr_valid",
+ .description = "l3.ieh_hop",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "ieh",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "ieh",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3_ipv6_cmp_dst",
+ .description = "l3.df",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3_ipv6_cmp_dst",
+ .description = "l3.df",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3_hdr_type",
+ .description = "l4.l4type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3_hdr_type",
+ .description = "l4.l4type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 0xff}
+ (BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 0xff}
+ (BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ULP_THOR_SYM_L3_HDR_VALID_YES}
+ (BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_vtag_present",
- .field_bit_size = 1,
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam_cache.ipv6_rd */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_UDP}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
.field_opr1 = {
@@ -23114,17 +23608,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_spec = {
.description = "prof_func_id",
.field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
@@ -23230,17 +23716,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_spec = {
.description = "prof_func_id",
.field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
@@ -24082,12 +24560,30 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
.field_info_spec = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -24388,12 +24884,24 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -24773,17 +25281,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_spec = {
.description = "prof_func_id",
.field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
@@ -25425,17 +25925,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_spec = {
.description = "prof_func_id",
.field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
@@ -26095,17 +26587,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_spec = {
.description = "prof_func_id",
.field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
@@ -26211,17 +26695,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_spec = {
.description = "prof_func_id",
.field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
@@ -27063,12 +27539,30 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -27349,12 +27843,27 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -27542,47 +28051,29 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l4.src",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
.field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l4.src",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
.field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -27590,47 +28081,29 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l4.dst",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
.field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l4.dst",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
.field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -28571,12 +29044,30 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -28857,12 +29348,27 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -30011,12 +30517,30 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -30285,12 +30809,14 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -31393,227 +31919,11 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
}
},
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
- {
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
- }
- },
- /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
- {
- .field_info_mask = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
+ /* class_tid: 5, , table: port_table.egr_wr */
{
.field_info_mask = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
+ .description = "dev.port_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
@@ -31621,104 +31931,16 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
+ .description = "dev.port_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
- }
- },
- {
- .field_info_mask = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- .field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
}
},
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
{
.field_info_mask = {
.description = "svif",
@@ -31738,67 +31960,392 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
}
},
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.rd_egr0 */
- {
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
- }
- },
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
- {
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
- }
- },
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_rd_vfr */
- {
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
- }
- },
- /* class_tid: 5, , table: l2_cntxt_tcam.vfr_ing0 */
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.rd_egr0 */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_rd_vfr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam.vfr_ing0 */
{
.field_info_mask = {
.description = "etype",
@@ -33860,332 +34407,1091 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
}
},
{
- .field_info_mask = {
- .description = "l3.ieh_auth",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_auth",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ }
+};
+
+struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
+ /* class_tid: 1, , table: l2_cntxt_tcam.0 */
+ {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ },
+ {
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ },
+ {
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ },
+ /* class_tid: 1, , table: mac_addr_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: fkb_select.l2_l3_l4_v6_em */
+ {
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "parif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "spif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "lcos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "loopback.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tuntype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tflags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tqos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "terr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ },
+ {
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ },
+ {
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ },
+ {
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}
+ },
+ {
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.l3err.ipv4",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.l3err.ipv4",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}
},
{
- .field_info_mask = {
- .description = "l3.l3err.ipv6",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.l3err.ipv6",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}
},
{
- .field_info_mask = {
- .description = "l4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_win.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.ack",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.ack",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.win",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.win",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */
{
- .field_info_mask = {
- .description = "l4.tsval",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.tsval",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.txecr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.txecr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- }
-};
-
-struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
- /* class_tid: 1, , table: l2_cntxt_tcam.0 */
- {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "em_key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "em_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "em_search_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ 1}
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: mac_addr_cache.wr */
+ /* class_tid: 1, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -34196,27 +35502,98 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "l2_cntxt_tcam_index",
+ .description = "profile_tcam_index",
.field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "wc_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ },
+ /* class_tid: 1, , table: em.l2_l3_l4_v6.0 */
+ {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: fkb_select.l2_l3_l4_v6_em */
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: fkb_select.l3_l4_wm */
{
.description = "l2_cntxt_id.en",
.field_bit_size = 1,
@@ -34589,10 +35966,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ 1}
},
{
.description = "l2_dt.en",
@@ -34651,22 +36027,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
{
.description = "l2_ivv.en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ 1}
},
{
.description = "l2_ivt.en",
@@ -34690,10 +36054,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ 1}
},
{
.description = "l3_sip_selcmp.en",
@@ -34705,10 +36068,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ 1}
},
{
.description = "l3_dip_selcmp.en",
@@ -34726,7 +36088,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l3_fid.en",
@@ -34810,19 +36174,17 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}
+ 1}
},
{
.description = "l4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}
+ 1}
},
{
.description = "l4_flags.en",
@@ -34884,166 +36246,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */
- {
- .description = "wc_key_id",
- .field_bit_size = 6,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "wc_search_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "em_key_type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "em_key_id",
- .field_bit_size = 6,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
- },
- {
- .description = "em_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
- },
- {
- .description = "em_search_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- {
- .description = "pl_byp_lkup_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- /* class_tid: 1, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
- {
- .description = "rid",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
- },
- {
- .description = "profile_tcam_index",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
- },
- {
- .description = "em_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
- },
- {
- .description = "em_key_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
- },
- {
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "wc_key_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "flow_sig_id",
- .field_bit_size = 64,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
- },
- /* class_tid: 1, , table: em.l2_l3_l4_v6.0 */
- {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- {
- .description = "strength",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 3}
- },
- {
- .description = "data",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
- },
- {
- .description = "opcode",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "meta_prof",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "ctxt_data",
- .field_bit_size = 14,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- /* class_tid: 1, , table: fkb_select.l3_l4_wm */
+ /* class_tid: 1, , table: fkb_select.l3_l4_wm_vxlan */
{
.description = "l2_cntxt_id.en",
.field_bit_size = 1,
@@ -35170,7 +36373,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl2_ivv.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl2_ivt.en",
@@ -35194,7 +36399,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl3_sip_selcmp.en",
@@ -35206,7 +36413,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl3_dip_selcmp.en",
@@ -35224,7 +36433,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl3_fid.en",
@@ -35308,13 +36519,17 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl4_flags.en",
@@ -35478,9 +36693,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_ivv.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l2_ivt.en",
@@ -35504,9 +36717,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l3_sip_selcmp.en",
@@ -35518,9 +36729,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l3_dip_selcmp.en",
@@ -35538,9 +36747,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l3_fid.en",
@@ -35624,17 +36831,13 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l4_flags.en",
@@ -35696,9 +36899,112 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: fkb_select.l3_l4_wm_vxlan */
+ /* class_tid: 1, , table: profile_tcam.l3_l4.ip */
{
- .description = "l2_cntxt_id.en",
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.l3_l4.vxlan */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 & 0xff}
+ },
+ {
+ .description = "wc_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -35706,1131 +37012,1203 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
1}
},
{
- .description = "parif.en",
- .field_bit_size = 1,
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "spif.en",
- .field_bit_size = 1,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "svif.en",
+ .description = "em_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "lcos.en",
+ .description = "pl_byp_lkup_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 1, , table: profile_tcam_cache.wr */
{
- .description = "meta.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "rcyc_cnt.en",
- .field_bit_size = 1,
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
},
{
- .description = "loopback.en",
- .field_bit_size = 1,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_l2type.en",
- .field_bit_size = 1,
+ .description = "em_key_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_dmac.en",
- .field_bit_size = 1,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_smac.en",
- .field_bit_size = 1,
+ .description = "wc_key_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_dt.en",
- .field_bit_size = 1,
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
+ /* class_tid: 1, , table: wm.l3_l4.ipv4 */
{
- .description = "tl2_sa.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_nvt.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovp.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovd.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl2_ovv.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 1, , table: wm.l3_l4.ipv6 */
{
- .description = "tl2_ovt.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivp.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivd.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivv.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 1, , table: wm.l3.ipv4 */
{
- .description = "tl2_ivt.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_etype.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_l3type.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_sip.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 1, , table: wm.l3.ipv6 */
{
- .description = "tl3_sip_selcmp.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_dip.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_dip_selcmp.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ttl.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl3_prot.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 1, , table: wm.l2 */
{
- .description = "tl3_fid.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_qos.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_nonext.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_esp.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl3_ieh_auth.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv4 */
{
- .description = "tl3_ieh_dest.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_frag.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_rthdr.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_hop.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl3_ieh_1frag.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv6 */
{
- .description = "tl3_df.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_l3err.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_l4type.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_src.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl4_dst.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
{
- .description = "tl4_flags.en",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_seq.en",
- .field_bit_size = 1,
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_pa.en",
- .field_bit_size = 1,
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_opt.en",
- .field_bit_size = 1,
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_tcpts.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_err.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 2, , table: tunnel_cache.wr */
{
- .description = "tuntype.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "tflags.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tids.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
+ /* class_tid: 2, , table: l2_cntxt_tcam.0 */
{
- .description = "tid.en",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
},
{
- .description = "tctxts.en",
- .field_bit_size = 1,
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tctxt.en",
- .field_bit_size = 1,
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
{
- .description = "tqos.en",
- .field_bit_size = 1,
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
},
{
- .description = "terr.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .description = "l2_l2type.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
},
+ /* class_tid: 2, , table: mac_addr_cache.wr */
{
- .description = "l2_dmac.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_smac.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 2, , table: fkb_select.f2_l2_l3_l4_v6_em */
{
- .description = "l2_dt.en",
+ .description = "l2_cntxt_id.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "l2_sa.en",
+ .description = "parif.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_nvt.en",
+ .description = "spif.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovp.en",
+ .description = "svif.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovd.en",
+ .description = "lcos.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovv.en",
+ .description = "meta.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovt.en",
+ .description = "rcyc_cnt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivp.en",
+ .description = "loopback.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivd.en",
+ .description = "tl2_l2type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivv.en",
+ .description = "tl2_dmac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivt.en",
+ .description = "tl2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_etype.en",
+ .description = "tl2_dt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_l3type.en",
+ .description = "tl2_sa.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_sip.en",
+ .description = "tl2_nvt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_sip_selcmp.en",
+ .description = "tl2_ovp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip.en",
+ .description = "tl2_ovd.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip_selcmp.en",
+ .description = "tl2_ovv.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ttl.en",
+ .description = "tl2_ovt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_prot.en",
+ .description = "tl2_ivp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_fid.en",
+ .description = "tl2_ivd.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_qos.en",
+ .description = "tl2_ivv.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_nonext.en",
+ .description = "tl2_ivt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_esp.en",
+ .description = "tl2_etype.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_auth.en",
+ .description = "tl3_l3type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_dest.en",
+ .description = "tl3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_frag.en",
+ .description = "tl3_sip_selcmp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_rthdr.en",
+ .description = "tl3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_hop.en",
+ .description = "tl3_dip_selcmp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_1frag.en",
+ .description = "tl3_ttl.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_df.en",
+ .description = "tl3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_l3err.en",
+ .description = "tl3_fid.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_l4type.en",
+ .description = "tl3_qos.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_src.en",
+ .description = "tl3_ieh_nonext.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_dst.en",
+ .description = "tl3_ieh_esp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_flags.en",
+ .description = "tl3_ieh_auth.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_seq.en",
+ .description = "tl3_ieh_dest.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_ack.en",
+ .description = "tl3_ieh_frag.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_win.en",
+ .description = "tl3_ieh_rthdr.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_pa.en",
+ .description = "tl3_ieh_hop.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_opt.en",
+ .description = "tl3_ieh_1frag.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_tcpts.en",
+ .description = "tl3_df.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_tsval.en",
+ .description = "tl3_l3err.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_txecr.en",
+ .description = "tl4_l4type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_err.en",
+ .description = "tl4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam.l3_l4.ip */
{
- .description = "wc_key_id",
- .field_bit_size = 6,
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_search_en",
+ .description = "tl4_seq.en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_type",
- .field_bit_size = 2,
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 6,
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_search_en",
+ .description = "tl4_err.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "pl_byp_lkup_en",
+ .description = "tuntype.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam.l3_l4.vxlan */
{
- .description = "wc_key_id",
- .field_bit_size = 6,
+ .description = "tflags.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 & 0xff}
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}
},
{
- .description = "wc_search_en",
+ .description = "tid.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_type",
- .field_bit_size = 2,
+ .description = "tctxts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 6,
+ .description = "tctxt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "tqos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_search_en",
+ .description = "terr.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "pl_byp_lkup_en",
+ .description = "l2_l2type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam_cache.wr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ 1}
},
{
- .description = "profile_tcam_index",
- .field_bit_size = 10,
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 8,
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_key_id",
- .field_bit_size = 8,
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "flow_sig_id",
- .field_bit_size = 64,
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l3_l4.ipv4 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l3_l4.ipv6 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}
},
- /* class_tid: 1, , table: wm.l3.ipv4 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff}
+ },
+ {
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l3.ipv6 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l2 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l3_df.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ (BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff}
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff}
},
- /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv4 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l4_win.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv6 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l4_err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: l2_cntxt_tcam.1 */
+ /* class_tid: 2, , table: profile_tcam.f2_l2_l3_l4_v6_em */
{
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "wc_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "wc_search_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "em_key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "em_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: tunnel_cache.wr */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_l2_l3_l4_v6_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -36841,99 +38219,94 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "l2_cntxt_tcam_index",
+ .description = "profile_tcam_index",
.field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
},
- /* class_tid: 2, , table: l2_cntxt_tcam.0 */
{
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "em_key_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "wc_key_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
+ /* class_tid: 2, , table: em.f2_l2_l3_l4_v6.0 */
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ 1}
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ 3}
},
- /* class_tid: 2, , table: mac_addr_cache.wr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "l2_cntxt_tcam_index",
- .field_bit_size = 10,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -37100,9 +38473,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "tl3_dip_selcmp.en",
@@ -37316,7 +38687,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l2_dt.en",
@@ -37400,7 +38773,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l3_sip_selcmp.en",
@@ -37432,7 +38807,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l3_fid.en",
@@ -37516,13 +38893,17 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l4_flags.en",
@@ -37743,127 +39124,6 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 2, , table: wm.l3_l4.ipv6 */
- {
- .description = "ctxt_data",
- .field_bit_size = 14,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "meta_prof",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "opcode",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "data",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
- },
- {
- .description = "strength",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- /* class_tid: 3, , table: l2_cntxt_tcam.0 */
- {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}
- },
- {
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "def_ctxt_data",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
- },
- {
- .description = "ctxt_opcode",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
- },
- {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
- },
- {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
- },
- /* class_tid: 3, , table: mac_addr_cache.wr */
- {
- .description = "rid",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
- },
- {
- .description = "l2_cntxt_tcam_index",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
- },
- {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
- },
- {
- .description = "src_property_ptr",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
/* class_tid: 3, , table: fkb_select.l2_l3_l4_v6_em */
{
.description = "l2_cntxt_id.en",
@@ -38240,7 +39500,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
},
{
.description = "l2_dt.en",
@@ -38374,7 +39637,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}
},
{
.description = "l3_fid.en",
@@ -39066,7 +40332,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l2_dt.en",
@@ -39186,7 +40454,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l3_fid.en",
@@ -39663,7 +40933,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -39910,7 +41182,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -40050,7 +41324,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "parif",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
},
{
.description = "reserved",
@@ -40238,7 +41515,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -40299,6 +41578,43 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
+ /* class_tid: 5, , table: port_table.egr_wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drv_func.mac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drv_func.parent.mac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff}
+ },
+ {
+ .description = "phy_port",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "default_arec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
+ },
/* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
{
.description = "prof_func_id",
@@ -40450,7 +41766,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -40610,7 +41928,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "parif",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
},
{
.description = "reserved",
@@ -40970,7 +42291,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -41772,6 +43095,34 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_wr_vfr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
/* class_tid: 5, , table: int_full_act_record.vfr_ing0 */
{
.description = "sp_rec_ptr",
@@ -41819,7 +43170,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -42058,7 +43411,13 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 42
},
- /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_ipv6_rd */
+ {
+ .description = "em_key_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_KEY_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 50
+ },
{
.description = "em_profile_id",
.regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
@@ -42077,47 +43436,40 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 32
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ /* class_tid: 2, , table: profile_tcam.f2_l2_l3_l4_v6_em */
{
- .description = "l2_cntxt_id",
- .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
- .ident_bit_size = 10,
- .ident_bit_pos = 42
+ .description = "em_profile_id",
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_EM_PROF,
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 23
},
- /* class_tid: 3, , table: mac_addr_cache.rd */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
{
- .description = "l2_cntxt_id",
- .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
- .ident_bit_size = 10,
+ .description = "em_profile_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
.ident_bit_pos = 42
},
- /* class_tid: 3, , table: port_table.egr.rd */
- {
- .description = "default_arec_ptr",
- .regfile_idx = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
- .ident_bit_size = 16,
- .ident_bit_pos = 136
- },
{
- .description = "drv_func.parent.mac",
- .regfile_idx = BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC,
- .ident_bit_size = 48,
- .ident_bit_pos = 80
+ .description = "flow_sig_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .ident_bit_size = 64,
+ .ident_bit_pos = 74
},
{
- .description = "phy_port",
- .regfile_idx = BNXT_ULP_RF_IDX_PHY_PORT,
- .ident_bit_size = 8,
- .ident_bit_pos = 128
+ .description = "profile_tcam_index",
+ .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
},
- /* class_tid: 3, , table: l2_cntxt_tcam.0 */
+ /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
{
.description = "l2_cntxt_id",
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
- .ident_bit_pos = 29
+ .ident_bit_pos = 42
},
/* class_tid: 3, , table: profile_tcam_cache.ipv6_rd */
{
@@ -42168,36 +43520,29 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
},
/* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
- .description = "l2_cntxt_id",
+ .description = "l2_cntxt_id_low",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 29
},
/* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
- .description = "l2_cntxt_id",
+ .description = "l2_cntxt_id_low",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 29
},
/* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
{
- .description = "l2_cntxt_id",
+ .description = "l2_cntxt_id_low",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 29
- },
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_wr_vfr */
- {
- .description = "rid",
- .regfile_idx = BNXT_ULP_RF_IDX_RID,
- .ident_bit_size = 32,
- .ident_bit_pos = 0
}
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
index 2870a0615a..4b9cb7fd5b 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Wed Jun 30 14:36:16 2021 */
+/* date: Wed Aug 11 16:00:16 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -16741,27 +16741,27 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
},
/* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
- .description = "l2_cntxt_id",
+ .description = "l2_cntxt_id_low",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 0
},
/* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
- .description = "l2_cntxt_id",
+ .description = "l2_cntxt_id_low",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 0
},
/* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
{
- .description = "l2_cntxt_id",
+ .description = "l2_cntxt_id_low",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 0
diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
index c6b2b1675d..7b6db7a0f8 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
@@ -75,9 +75,9 @@ ulp_mapper_generic_tbl_list_init(struct bnxt_ulp_mapper_data *mapper_data)
entry->container.byte_data = &entry->mem_data[size];
entry->container.byte_order = tbl->result_byte_order;
} else {
- BNXT_TF_DBG(ERR, "%s:Invalid gen table num of ent %d\n",
+ BNXT_TF_DBG(DEBUG, "%s: Unused Gen tbl entry is %d\n",
tbl->name, idx);
- return -EINVAL;
+ /* return -EINVAL; */
}
if (tbl->hash_tbl_entries) {
cparams.key_size = tbl->key_num_bytes;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 234f7ea2fa..059ee99837 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -438,6 +438,77 @@ ulp_mapper_ident_fields_get(struct bnxt_ulp_mapper_parms *mparms,
return &dev_tbls->ident_list[idx];
}
+static enum tf_tbl_type
+ulp_mapper_dyn_tbl_type_get(struct bnxt_ulp_mapper_parms *mparms,
+ struct bnxt_ulp_mapper_tbl_info *tbl,
+ struct ulp_blob *bdata,
+ uint16_t *out_len)
+{
+ struct bnxt_ulp_device_params *d_params = mparms->device_params;
+ uint16_t blob_len = ulp_blob_data_len_get(bdata);
+ struct bnxt_ulp_dyn_size_map *size_map;
+ uint32_t i;
+
+ if (d_params->dynamic_sram_en) {
+ switch (tbl->resource_type) {
+ case TF_TBL_TYPE_ACT_ENCAP_8B:
+ case TF_TBL_TYPE_ACT_ENCAP_16B:
+ case TF_TBL_TYPE_ACT_ENCAP_32B:
+ case TF_TBL_TYPE_ACT_ENCAP_64B:
+ size_map = d_params->dyn_encap_sizes;
+ for (i = 0; i < d_params->dyn_encap_list_size; i++) {
+ if (blob_len <= size_map[i].slab_size) {
+ *out_len = size_map[i].slab_size;
+ return size_map[i].tbl_type;
+ }
+ }
+ break;
+ case TF_TBL_TYPE_ACT_MODIFY_8B:
+ case TF_TBL_TYPE_ACT_MODIFY_16B:
+ case TF_TBL_TYPE_ACT_MODIFY_32B:
+ case TF_TBL_TYPE_ACT_MODIFY_64B:
+ size_map = d_params->dyn_modify_sizes;
+ for (i = 0; i < d_params->dyn_modify_list_size; i++) {
+ if (blob_len <= size_map[i].slab_size) {
+ *out_len = size_map[i].slab_size;
+ return size_map[i].tbl_type;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ }
+ return tbl->resource_type;
+}
+
+static uint16_t
+ulp_mapper_dyn_blob_size_get(struct bnxt_ulp_mapper_parms *mparms,
+ struct bnxt_ulp_mapper_tbl_info *tbl)
+{
+ struct bnxt_ulp_device_params *d_params = mparms->device_params;
+
+ if (d_params->dynamic_sram_en) {
+ switch (tbl->resource_type) {
+ case TF_TBL_TYPE_ACT_ENCAP_8B:
+ case TF_TBL_TYPE_ACT_ENCAP_16B:
+ case TF_TBL_TYPE_ACT_ENCAP_32B:
+ case TF_TBL_TYPE_ACT_ENCAP_64B:
+ case TF_TBL_TYPE_ACT_MODIFY_8B:
+ case TF_TBL_TYPE_ACT_MODIFY_16B:
+ case TF_TBL_TYPE_ACT_MODIFY_32B:
+ case TF_TBL_TYPE_ACT_MODIFY_64B:
+ /* return max size */
+ return BNXT_ULP_FLMP_BLOB_SIZE_IN_BITS;
+ default:
+ break;
+ }
+ } else if (tbl->encap_num_fields) {
+ return BNXT_ULP_FLMP_BLOB_SIZE_IN_BITS;
+ }
+ return tbl->result_bit_size;
+}
+
static inline int32_t
ulp_mapper_tcam_entry_free(struct bnxt_ulp_context *ulp,
struct tf *tfp,
@@ -1562,7 +1633,8 @@ ulp_mapper_tbl_result_build(struct bnxt_ulp_mapper_parms *parms,
if (encap_flds) {
uint32_t pad = 0;
/* Initialize the encap blob */
- if (!tbl->record_size) {
+ if (!tbl->record_size &&
+ !parms->device_params->dynamic_sram_en) {
BNXT_TF_DBG(ERR, "Encap tbl record size incorrect\n");
return -EINVAL;
}
@@ -1583,9 +1655,21 @@ ulp_mapper_tbl_result_build(struct bnxt_ulp_mapper_parms *parms,
}
}
/* add the dynamic pad push */
- pad = ULP_BYTE_2_BITS(tbl->record_size) -
- ulp_blob_data_len_get(&encap_blob);
- ulp_blob_pad_push(&encap_blob, pad);
+ if (parms->device_params->dynamic_sram_en) {
+ uint16_t rec_s = ULP_BYTE_2_BITS(tbl->record_size);
+
+ (void)ulp_mapper_dyn_tbl_type_get(parms, tbl,
+ &encap_blob, &rec_s);
+ pad = rec_s - ulp_blob_data_len_get(&encap_blob);
+ } else {
+ pad = ULP_BYTE_2_BITS(tbl->record_size) -
+ ulp_blob_data_len_get(&encap_blob);
+ }
+ if (ulp_blob_pad_push(&encap_blob, pad) < 0) {
+ BNXT_TF_DBG(ERR, "encap buffer padding failed\n");
+ return -EINVAL;
+ }
+
/* perform the 64 bit byte swap */
ulp_blob_perform_64B_byte_swap(&encap_blob);
@@ -2411,13 +2495,11 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
bool global = false;
uint64_t act_rec_size;
bool shared = false;
+ enum tf_tbl_type tbl_type = tbl->resource_type;
tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session);
- /* use the max size if encap is enabled */
- if (tbl->encap_num_fields)
- bit_size = BNXT_ULP_FLMP_BLOB_SIZE_IN_BITS;
- else
- bit_size = tbl->result_bit_size;
+ /* compute the blob size */
+ bit_size = ulp_mapper_dyn_blob_size_get(parms, tbl);
/* Initialize the blob data */
if (!ulp_blob_init(&data, bit_size,
@@ -2526,7 +2608,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
gparms.dir = tbl->direction;
gparms.type = tbl->resource_type;
gparms.data = ulp_blob_data_get(&data, &tmplen);
- gparms.data_sz_in_bytes = ULP_BITS_2_BYTE(tbl->result_bit_size);
+ gparms.data_sz_in_bytes = ULP_BITS_2_BYTE(tmplen);
gparms.idx = index;
rc = tf_get_tbl_entry(tfp, &gparms);
if (rc) {
@@ -2568,14 +2650,16 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
if (alloc) {
aparms.dir = tbl->direction;
- aparms.type = tbl->resource_type;
+ tbl_type = ulp_mapper_dyn_tbl_type_get(parms, tbl,
+ &data, &tmplen);
+ aparms.type = tbl_type;
aparms.tbl_scope_id = tbl_scope_id;
/* All failures after the alloc succeeds require a free */
rc = tf_alloc_tbl_entry(tfp, &aparms);
if (rc) {
BNXT_TF_DBG(ERR, "Alloc table[%s][%s] failed rc=%d\n",
- tf_tbl_type_2_str(tbl->resource_type),
+ tf_tbl_type_2_str(aparms.type),
tf_dir_2_str(tbl->direction), rc);
return rc;
}
@@ -2619,8 +2703,10 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
if (write) {
sparms.dir = tbl->direction;
- sparms.type = tbl->resource_type;
sparms.data = ulp_blob_data_get(&data, &tmplen);
+ tbl_type = ulp_mapper_dyn_tbl_type_get(parms, tbl, &data,
+ &tmplen);
+ sparms.type = tbl_type;
sparms.data_sz_in_bytes = ULP_BITS_2_BYTE(tmplen);
sparms.idx = index;
sparms.tbl_scope_id = tbl_scope_id;
@@ -2655,7 +2741,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
memset(&fid_parms, 0, sizeof(fid_parms));
fid_parms.direction = tbl->direction;
fid_parms.resource_func = tbl->resource_func;
- fid_parms.resource_type = tbl->resource_type;
+ fid_parms.resource_type = tbl_type;
fid_parms.resource_sub_type = tbl->resource_sub_type;
fid_parms.resource_hndl = index;
fid_parms.critical_resource = tbl->critical_resource;
@@ -2684,7 +2770,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
* write to the entry or link the flow
*/
free_parms.dir = tbl->direction;
- free_parms.type = tbl->resource_type;
+ free_parms.type = tbl_type;
free_parms.idx = index;
free_parms.tbl_scope_id = tbl_scope_id;
@@ -2862,8 +2948,7 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms,
cache_key = ulp_blob_data_get(&key, &tmplen);
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
- BNXT_TF_DBG(DEBUG, "The gen_tbl[%u] key\n", tbl_idx);
- ulp_mapper_blob_dump(&key);
+ ulp_mapper_gen_tbl_dump(tbl->resource_sub_type, tbl->direction, &key);
#endif
#endif
/* get the generic table */
@@ -3310,18 +3395,10 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms,
*res = regval == 0;
break;
case BNXT_ULP_COND_OPC_FLOW_PAT_MATCH:
- if (parms->flow_pattern_id == operand) {
- BNXT_TF_DBG(ERR, "field pattern match failed %x\n",
- parms->flow_pattern_id);
- return -EINVAL;
- }
+ *res = parms->flow_pattern_id == operand;
break;
case BNXT_ULP_COND_OPC_ACT_PAT_MATCH:
- if (parms->act_pattern_id == operand) {
- BNXT_TF_DBG(ERR, "act pattern match failed %x\n",
- parms->act_pattern_id);
- return -EINVAL;
- }
+ *res = parms->act_pattern_id == operand;
break;
case BNXT_ULP_COND_OPC_EXT_MEM_IS_SET:
if (bnxt_ulp_cntxt_mem_type_get(parms->ulp_ctx, &mtype)) {
@@ -3507,7 +3584,6 @@ ulp_mapper_func_info_process(struct bnxt_ulp_mapper_parms *parms,
return rc;
}
-
/*
* Processes a list of conditions and returns both a status and result of the
* list. The status must be checked prior to verifying the result.
@@ -3863,8 +3939,7 @@ ulp_mapper_resources_free(struct bnxt_ulp_context *ulp_ctx,
* Set the critical resource on the first resource del, then iterate
* while status is good
*/
- if (flow_type != BNXT_ULP_FDB_TYPE_RID)
- res_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES;
+ res_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES;
rc = ulp_flow_db_resource_del(ulp_ctx, flow_type, fid, &res_parms);
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index dce95de05c..3a9c9bba27 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -1226,20 +1226,66 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
/* Function to handle the update of proto header based on field values */
static void
-ulp_rte_l4_proto_type_update(struct ulp_rte_parser_params *param,
- uint16_t dst_port)
-{
- if (dst_port == tfp_cpu_to_be_16(ULP_UDP_PORT_VXLAN)) {
- ULP_BITMAP_SET(param->hdr_fp_bit.bits,
- BNXT_ULP_HDR_BIT_T_VXLAN);
- ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_L3_TUN, 1);
+ulp_rte_l4_proto_type_update(struct ulp_rte_parser_params *params,
+ uint16_t src_port, uint16_t src_mask,
+ uint16_t dst_port, uint16_t dst_mask,
+ enum bnxt_ulp_hdr_bit hdr_bit)
+{
+ switch (hdr_bit) {
+ case BNXT_ULP_HDR_BIT_I_UDP:
+ case BNXT_ULP_HDR_BIT_I_TCP:
+ ULP_BITMAP_SET(params->hdr_bitmap.bits, hdr_bit);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4, 1);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_SRC_PORT,
+ (uint64_t)rte_be_to_cpu_16(src_port));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_DST_PORT,
+ (uint64_t)rte_be_to_cpu_16(dst_port));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK,
+ (uint64_t)rte_be_to_cpu_16(src_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK,
+ (uint64_t)rte_be_to_cpu_16(dst_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID,
+ 1);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT,
+ !!(src_port & src_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT,
+ !!(dst_port & dst_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_PROTO_ID,
+ (hdr_bit == BNXT_ULP_HDR_BIT_I_UDP) ?
+ IPPROTO_UDP : IPPROTO_TCP);
+ break;
+ case BNXT_ULP_HDR_BIT_O_UDP:
+ case BNXT_ULP_HDR_BIT_O_TCP:
+ ULP_BITMAP_SET(params->hdr_bitmap.bits, hdr_bit);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4, 1);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_SRC_PORT,
+ (uint64_t)rte_be_to_cpu_16(src_port));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DST_PORT,
+ (uint64_t)rte_be_to_cpu_16(dst_port));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK,
+ (uint64_t)rte_be_to_cpu_16(src_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK,
+ (uint64_t)rte_be_to_cpu_16(dst_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID,
+ 1);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT,
+ !!(src_port & src_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT,
+ !!(dst_port & dst_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_PROTO_ID,
+ (hdr_bit == BNXT_ULP_HDR_BIT_O_UDP) ?
+ IPPROTO_UDP : IPPROTO_TCP);
+ break;
+ default:
+ break;
}
- if (ULP_BITMAP_ISSET(param->hdr_bitmap.bits,
- BNXT_ULP_HDR_BIT_T_VXLAN) ||
- ULP_BITMAP_ISSET(param->hdr_bitmap.bits,
- BNXT_ULP_HDR_BIT_T_GRE))
- ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_L3_TUN, 1);
+ if (hdr_bit == BNXT_ULP_HDR_BIT_O_UDP && dst_port ==
+ tfp_cpu_to_be_16(ULP_UDP_PORT_VXLAN)) {
+ ULP_BITMAP_SET(params->hdr_fp_bit.bits,
+ BNXT_ULP_HDR_BIT_T_VXLAN);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN, 1);
+ }
}
/* Function to handle the parsing of RTE Flow item UDP Header. */
@@ -1253,7 +1299,9 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item,
uint32_t idx = 0;
uint32_t size;
uint16_t dport = 0, sport = 0;
+ uint16_t dport_mask = 0, sport_mask = 0;
uint32_t cnt;
+ enum bnxt_ulp_hdr_bit out_l4 = BNXT_ULP_HDR_BIT_O_UDP;
cnt = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L4_HDR_CNT);
if (cnt == 2) {
@@ -1265,6 +1313,10 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item,
sport = udp_spec->hdr.src_port;
dport = udp_spec->hdr.dst_port;
}
+ if (udp_mask) {
+ sport_mask = udp_mask->hdr.src_port;
+ dport_mask = udp_mask->hdr.dst_port;
+ }
if (ulp_rte_prsr_fld_size_validate(params, &idx,
BNXT_ULP_PROTO_HDR_UDP_NUM)) {
@@ -1302,48 +1354,11 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item,
/* Set the udp header bitmap and computed l4 header bitmaps */
if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP) ||
- ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP)) {
- ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_UDP);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4, 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_SRC_PORT,
- (uint32_t)rte_be_to_cpu_16(sport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_DST_PORT,
- (uint32_t)rte_be_to_cpu_16(dport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID,
- 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_PROTO_ID,
- IPPROTO_UDP);
- if (udp_mask && udp_mask->hdr.src_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT,
- 1);
- if (udp_mask && udp_mask->hdr.dst_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT,
- 1);
- } else {
- ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4, 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_SRC_PORT,
- (uint32_t)rte_be_to_cpu_16(sport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DST_PORT,
- (uint32_t)rte_be_to_cpu_16(dport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID,
- 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_PROTO_ID,
- IPPROTO_UDP);
- if (udp_mask && udp_mask->hdr.src_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT,
- 1);
- if (udp_mask && udp_mask->hdr.dst_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT,
- 1);
+ ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP))
+ out_l4 = BNXT_ULP_HDR_BIT_I_UDP;
- /* Update the field protocol hdr bitmap */
- ulp_rte_l4_proto_type_update(params, dport);
- }
+ ulp_rte_l4_proto_type_update(params, sport, sport_mask, dport,
+ dport_mask, out_l4);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L4_HDR_CNT, ++cnt);
return BNXT_TF_RC_SUCCESS;
}
@@ -1358,8 +1373,10 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item,
struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap;
uint32_t idx = 0;
uint16_t dport = 0, sport = 0;
+ uint16_t dport_mask = 0, sport_mask = 0;
uint32_t size;
uint32_t cnt;
+ enum bnxt_ulp_hdr_bit out_l4 = BNXT_ULP_HDR_BIT_O_TCP;
cnt = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L4_HDR_CNT);
if (cnt == 2) {
@@ -1371,6 +1388,10 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item,
sport = tcp_spec->hdr.src_port;
dport = tcp_spec->hdr.dst_port;
}
+ if (tcp_mask) {
+ sport_mask = tcp_mask->hdr.src_port;
+ dport_mask = tcp_mask->hdr.dst_port;
+ }
if (ulp_rte_prsr_fld_size_validate(params, &idx,
BNXT_ULP_PROTO_HDR_TCP_NUM)) {
@@ -1438,45 +1459,11 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item,
/* Set the udp header bitmap and computed l4 header bitmaps */
if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP) ||
- ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP)) {
- ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_TCP);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4, 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_SRC_PORT,
- (uint32_t)rte_be_to_cpu_16(sport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_DST_PORT,
- (uint32_t)rte_be_to_cpu_16(dport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID,
- 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_PROTO_ID,
- IPPROTO_TCP);
- if (tcp_mask && tcp_mask->hdr.src_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT,
- 1);
- if (tcp_mask && tcp_mask->hdr.dst_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT,
- 1);
- } else {
- ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4, 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_SRC_PORT,
- (uint32_t)rte_be_to_cpu_16(sport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DST_PORT,
- (uint32_t)rte_be_to_cpu_16(dport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID,
- 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_PROTO_ID,
- IPPROTO_TCP);
- if (tcp_mask && tcp_mask->hdr.src_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT,
- 1);
- if (tcp_mask && tcp_mask->hdr.dst_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT,
- 1);
- }
+ ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP))
+ out_l4 = BNXT_ULP_HDR_BIT_I_TCP;
+
+ ulp_rte_l4_proto_type_update(params, sport, sport_mask, dport,
+ dport_mask, out_l4);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L4_HDR_CNT, ++cnt);
return BNXT_TF_RC_SUCCESS;
}
@@ -1528,7 +1515,7 @@ ulp_rte_vxlan_hdr_handler(const struct rte_flow_item *item,
/* Update the hdr_bitmap with vxlan */
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_T_VXLAN);
- ulp_rte_l4_proto_type_update(params, 0);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN, 1);
return BNXT_TF_RC_SUCCESS;
}
@@ -1563,7 +1550,7 @@ ulp_rte_gre_hdr_handler(const struct rte_flow_item *item,
/* Update the hdr_bitmap with GRE */
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_T_GRE);
- ulp_rte_l4_proto_type_update(params, 0);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN, 1);
return BNXT_TF_RC_SUCCESS;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index 1683cd7ec4..d3bfb8c12d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -206,6 +206,11 @@ struct bnxt_ulp_template_device_tbls {
uint32_t cond_list_size;
};
+struct bnxt_ulp_dyn_size_map {
+ uint32_t slab_size;
+ enum tf_tbl_type tbl_type;
+};
+
/* Device specific parameters */
struct bnxt_ulp_device_params {
uint8_t description[16];
@@ -229,6 +234,11 @@ struct bnxt_ulp_device_params {
uint32_t byte_count_shift;
uint32_t packet_count_shift;
uint32_t dynamic_pad_en;
+ uint32_t dynamic_sram_en;
+ uint32_t dyn_encap_list_size;
+ struct bnxt_ulp_dyn_size_map dyn_encap_sizes[4];
+ uint32_t dyn_modify_list_size;
+ struct bnxt_ulp_dyn_size_map dyn_modify_sizes[4];
uint16_t em_blk_size_bits;
uint16_t em_blk_align_bits;
uint16_t em_key_align_bytes;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c
index 686b80e456..df3afaa6fd 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c
@@ -882,7 +882,8 @@ ulp_blob_msb_block_merge(struct ulp_blob *dst, struct ulp_blob *src,
for (i = 0; i < num;) {
if (((dst->write_idx % block_size) + (num - i)) > block_size)
- write_bytes = block_size - dst->write_idx;
+ write_bytes = block_size -
+ (dst->write_idx % block_size);
else
write_bytes = num - i;
for (k = 0; k < ULP_BITS_2_BYTE_NR(write_bytes); k++) {
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v3 00/13] enhancements to host based flow table management
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 00/13] enhancements to host based flow table management Venkat Duvvuru
` (12 preceding siblings ...)
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 13/13] net/bnxt: add enhancements to TF ULP Venkat Duvvuru
@ 2021-09-11 15:30 ` Venkat Duvvuru
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 01/13] net/bnxt: tf core index table updates Venkat Duvvuru
` (14 more replies)
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 " Venkat Duvvuru
14 siblings, 15 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-11 15:30 UTC (permalink / raw)
To: dev; +Cc: Venkat Duvvuru
This patch set adds support for new offload features/enhancments for
Thor adapters like VF representor support, new flow matches/actions
& dynamic SRAM manager support.
v2 ==> v3
=========
* Fixed compilation issue.
Farah Smith (4):
net/bnxt: tf core index table updates
net/bnxt: add Thor SRAM mgr model
net/bnxt: tf core SRAM Manager
net/bnxt: sram manager shared session
Jay Ding (1):
net/bnxt: add flow meter drop counter support
Kishore Padmanabha (6):
net/bnxt: add flow templates support for Thor
net/bnxt: add support for tunnel offloads
net/bnxt: add support for dynamic encap action
net/bnxt: add wild card TCAM byte order for Thor
net/bnxt: add flow templates for Thor
net/bnxt: add enhancements to TF ULP
Peter Spreadborough (1):
net/bnxt: enable dpool allocator
Randy Schacher (1):
net/bnxt: dynamically allocate space for EM defrag function
drivers/net/bnxt/tf_core/cfa_resource_types.h | 5 +-
drivers/net/bnxt/tf_core/dpool.c | 38 +-
drivers/net/bnxt/tf_core/ll.c | 3 +
drivers/net/bnxt/tf_core/ll.h | 50 +-
drivers/net/bnxt/tf_core/meson.build | 2 +
drivers/net/bnxt/tf_core/tf_core.c | 169 +-
drivers/net/bnxt/tf_core/tf_core.h | 159 +-
drivers/net/bnxt/tf_core/tf_device.c | 40 +-
drivers/net/bnxt/tf_core/tf_device.h | 137 +-
drivers/net/bnxt/tf_core/tf_device_p4.c | 77 +-
drivers/net/bnxt/tf_core/tf_device_p4.h | 50 +-
drivers/net/bnxt/tf_core/tf_device_p58.c | 112 +-
drivers/net/bnxt/tf_core/tf_device_p58.h | 70 +-
drivers/net/bnxt/tf_core/tf_em.h | 10 -
drivers/net/bnxt/tf_core/tf_em_common.c | 4 +
.../net/bnxt/tf_core/tf_em_hash_internal.c | 34 -
drivers/net/bnxt/tf_core/tf_em_internal.c | 185 +-
drivers/net/bnxt/tf_core/tf_msg.c | 2 +-
drivers/net/bnxt/tf_core/tf_rm.c | 180 +-
drivers/net/bnxt/tf_core/tf_rm.h | 62 +-
drivers/net/bnxt/tf_core/tf_session.c | 56 +
drivers/net/bnxt/tf_core/tf_session.h | 58 +-
drivers/net/bnxt/tf_core/tf_sram_mgr.c | 971 +
drivers/net/bnxt/tf_core/tf_sram_mgr.h | 317 +
drivers/net/bnxt/tf_core/tf_tbl.c | 259 +-
drivers/net/bnxt/tf_core/tf_tbl.h | 87 +-
drivers/net/bnxt/tf_core/tf_tbl_sram.c | 747 +
drivers/net/bnxt/tf_core/tf_tbl_sram.h | 154 +
drivers/net/bnxt/tf_core/tf_tcam.c | 16 +-
drivers/net/bnxt/tf_core/tf_tcam.h | 7 +
drivers/net/bnxt/tf_core/tf_tcam_shared.c | 28 +-
drivers/net/bnxt/tf_core/tf_util.c | 12 +
drivers/net/bnxt/tf_ulp/bnxt_tf_common.h | 10 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 52 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 20 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 226 +-
.../bnxt/tf_ulp/generic_templates/meson.build | 17 +-
.../generic_templates/ulp_template_db_act.c | 2 +-
.../generic_templates/ulp_template_db_class.c | 12109 +++-
.../generic_templates/ulp_template_db_enum.h | 618 +-
.../generic_templates/ulp_template_db_field.h | 767 +-
.../generic_templates/ulp_template_db_tbl.c | 2757 +-
.../ulp_template_db_thor_act.c | 5079 +-
.../ulp_template_db_thor_class.c | 45573 ++++++++++++++--
.../ulp_template_db_wh_plus_act.c | 1700 +-
.../ulp_template_db_wh_plus_class.c | 8329 ++-
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 48 +-
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h | 8 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 678 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 68 +-
drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c | 9 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 448 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.h | 10 +-
drivers/net/bnxt/tf_ulp/ulp_matcher.c | 13 +
drivers/net/bnxt/tf_ulp/ulp_port_db.c | 15 +-
drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c | 31 +
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 663 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 12 +-
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 32 +-
drivers/net/bnxt/tf_ulp/ulp_tun.c | 521 +-
drivers/net/bnxt/tf_ulp/ulp_tun.h | 89 +-
drivers/net/bnxt/tf_ulp/ulp_utils.c | 71 +-
drivers/net/bnxt/tf_ulp/ulp_utils.h | 27 +-
meson_options.txt | 2 +
64 files changed, 71149 insertions(+), 12956 deletions(-)
create mode 100644 drivers/net/bnxt/tf_core/tf_sram_mgr.c
create mode 100644 drivers/net/bnxt/tf_core/tf_sram_mgr.h
create mode 100644 drivers/net/bnxt/tf_core/tf_tbl_sram.c
create mode 100644 drivers/net/bnxt/tf_core/tf_tbl_sram.h
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v3 01/13] net/bnxt: tf core index table updates
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 00/13] enhancements to host based flow table management Venkat Duvvuru
@ 2021-09-11 15:30 ` Venkat Duvvuru
2021-09-16 13:47 ` Ferruh Yigit
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 02/13] net/bnxt: enable dpool allocator Venkat Duvvuru
` (13 subsequent siblings)
14 siblings, 1 reply; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-11 15:30 UTC (permalink / raw)
To: dev; +Cc: Farah Smith
From: Farah Smith <farah.smith@broadcom.com>
Remove unused shadow table functionality.
Signed-off-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Peter Spreadborough <peter.spreadborough@broadcom.com>
---
drivers/net/bnxt/tf_core/tf_core.c | 65 --------------
drivers/net/bnxt/tf_core/tf_core.h | 103 +----------------------
drivers/net/bnxt/tf_core/tf_device.h | 22 -----
drivers/net/bnxt/tf_core/tf_device_p4.c | 2 -
drivers/net/bnxt/tf_core/tf_device_p58.c | 2 -
drivers/net/bnxt/tf_core/tf_em_common.c | 4 +
drivers/net/bnxt/tf_core/tf_tbl.c | 21 -----
drivers/net/bnxt/tf_core/tf_tbl.h | 72 ----------------
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 3 +-
9 files changed, 7 insertions(+), 287 deletions(-)
diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c
index 97e6165e92..5458f76e2d 100644
--- a/drivers/net/bnxt/tf_core/tf_core.c
+++ b/drivers/net/bnxt/tf_core/tf_core.c
@@ -1105,71 +1105,6 @@ tf_alloc_tbl_entry(struct tf *tfp,
return 0;
}
-int
-tf_search_tbl_entry(struct tf *tfp,
- struct tf_search_tbl_entry_parms *parms)
-{
- int rc;
- struct tf_session *tfs;
- struct tf_dev_info *dev;
- struct tf_tbl_alloc_search_parms sparms;
-
- TF_CHECK_PARMS2(tfp, parms);
-
- /* Retrieve the session information */
- rc = tf_session_get_session(tfp, &tfs);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed to lookup session, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(-rc));
- return rc;
- }
-
- /* Retrieve the device information */
- rc = tf_session_get_device(tfs, &dev);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed to lookup device, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(-rc));
- return rc;
- }
-
- if (dev->ops->tf_dev_alloc_search_tbl == NULL) {
- rc = -EOPNOTSUPP;
- TFP_DRV_LOG(ERR,
- "%s: Operation not supported, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(-rc));
- return rc;
- }
-
- memset(&sparms, 0, sizeof(struct tf_tbl_alloc_search_parms));
- sparms.dir = parms->dir;
- sparms.type = parms->type;
- sparms.result = parms->result;
- sparms.result_sz_in_bytes = parms->result_sz_in_bytes;
- sparms.alloc = parms->alloc;
- sparms.tbl_scope_id = parms->tbl_scope_id;
- rc = dev->ops->tf_dev_alloc_search_tbl(tfp, &sparms);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: TBL allocation failed, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(-rc));
- return rc;
- }
-
- /* Return the outputs from the search */
- parms->hit = sparms.hit;
- parms->search_status = sparms.search_status;
- parms->ref_cnt = sparms.ref_cnt;
- parms->idx = sparms.idx;
-
- return 0;
-}
-
int
tf_free_tbl_entry(struct tf *tfp,
struct tf_free_tbl_entry_parms *parms)
diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h
index 84b234f0e3..7e0cdf7e0d 100644
--- a/drivers/net/bnxt/tf_core/tf_core.h
+++ b/drivers/net/bnxt/tf_core/tf_core.h
@@ -1622,79 +1622,6 @@ int tf_clear_tcam_shared_entries(struct tf *tfp,
* @ref tf_get_shared_tbl_increment
*/
-/**
- * tf_alloc_tbl_entry parameter definition
- */
-struct tf_search_tbl_entry_parms {
- /**
- * [in] Receive or transmit direction
- */
- enum tf_dir dir;
- /**
- * [in] Type of the allocation
- */
- enum tf_tbl_type type;
- /**
- * [in] Table scope identifier (ignored unless TF_TBL_TYPE_EXT)
- */
- uint32_t tbl_scope_id;
- /**
- * [in] Result data to search for
- */
- uint8_t *result;
- /**
- * [in] Result data size in bytes
- */
- uint16_t result_sz_in_bytes;
- /**
- * [in] Allocate on miss.
- */
- uint8_t alloc;
- /**
- * [out] Set if matching entry found
- */
- uint8_t hit;
- /**
- * [out] Search result status (hit, miss, reject)
- */
- enum tf_search_status search_status;
- /**
- * [out] Current ref count after allocation
- */
- uint16_t ref_cnt;
- /**
- * [out] Idx of allocated entry or found entry
- */
- uint32_t idx;
-};
-
-/**
- * search Table Entry (experimental)
- *
- * This function searches the shadow copy of an index table for a matching
- * entry. The result data must match for hit to be set. Only TruFlow core
- * data is accessed. If shadow_copy is not enabled, an error is returned.
- *
- * Implementation:
- *
- * A hash is performed on the result data and mapped to a shadow copy entry
- * where the result is populated. If the result matches the entry, hit is set,
- * ref_cnt is incremented (if alloc), and the search status indicates what
- * action the caller can take regarding setting the entry.
- *
- * search status should be used as follows:
- * - On MISS, the caller should set the result into the returned index.
- *
- * - On REJECT, the caller should reject the flow since there are no resources.
- *
- * - On Hit, the matching index is returned to the caller. Additionally, the
- * ref_cnt is updated.
- *
- * Also returns success or failure code.
- */
-int tf_search_tbl_entry(struct tf *tfp,
- struct tf_search_tbl_entry_parms *parms);
-
/**
* tf_alloc_tbl_entry parameter definition
*/
@@ -1711,30 +1638,9 @@ struct tf_alloc_tbl_entry_parms {
* [in] Table scope identifier (ignored unless TF_TBL_TYPE_EXT)
*/
uint32_t tbl_scope_id;
+
/**
- * [in] Enable search for matching entry. If the table type is
- * internal the shadow copy will be searched before
- * alloc. Session must be configured with shadow copy enabled.
- */
- uint8_t search_enable;
- /**
- * [in] Result data to search for (if search_enable)
- */
- uint8_t *result;
- /**
- * [in] Result data size in bytes (if search_enable)
- */
- uint16_t result_sz_in_bytes;
- /**
- * [out] If search_enable, set if matching entry found
- */
- uint8_t hit;
- /**
- * [out] Current ref count after allocation (if search_enable)
- */
- uint16_t ref_cnt;
- /**
- * [out] Idx of allocated entry or found entry (if search_enable)
+ * [out] Idx of allocated entry
*/
uint32_t idx;
};
@@ -1790,11 +1696,6 @@ struct tf_free_tbl_entry_parms {
* [in] Index to free
*/
uint32_t idx;
- /**
- * [out] Reference count after free, only valid if session has been
- * created with shadow_copy.
- */
- uint16_t ref_cnt;
};
/**
diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h
index da3f541685..b43cfc6925 100644
--- a/drivers/net/bnxt/tf_core/tf_device.h
+++ b/drivers/net/bnxt/tf_core/tf_device.h
@@ -347,28 +347,6 @@ struct tf_dev_ops {
int (*tf_dev_free_ext_tbl)(struct tf *tfp,
struct tf_tbl_free_parms *parms);
- /**
- * Searches for the specified table type element in a shadow DB.
- *
- * This API searches for the specified table type element in a
- * device specific shadow DB. If the element is found the
- * reference count for the element is updated. If the element
- * is not found a new element is allocated from the table type
- * DB and then inserted into the shadow DB.
- *
- * [in] tfp
- * Pointer to TF handle
- *
- * [in] parms
- * Pointer to table allocation and search parameters
- *
- * Returns
- * - (0) if successful.
- * - (-EINVAL) on failure.
- */
- int (*tf_dev_alloc_search_tbl)(struct tf *tfp,
- struct tf_tbl_alloc_search_parms *parms);
-
/**
* Sets the specified table type element.
*
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c
index 971fab7bda..2e7ccec123 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.c
@@ -236,7 +236,6 @@ const struct tf_dev_ops tf_dev_ops_p4_init = {
.tf_dev_alloc_tbl = NULL,
.tf_dev_free_ext_tbl = NULL,
.tf_dev_free_tbl = NULL,
- .tf_dev_alloc_search_tbl = NULL,
.tf_dev_set_tbl = NULL,
.tf_dev_set_ext_tbl = NULL,
.tf_dev_get_tbl = NULL,
@@ -282,7 +281,6 @@ const struct tf_dev_ops tf_dev_ops_p4 = {
.tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc,
.tf_dev_free_tbl = tf_tbl_free,
.tf_dev_free_ext_tbl = tf_tbl_ext_free,
- .tf_dev_alloc_search_tbl = tf_tbl_alloc_search,
.tf_dev_set_tbl = tf_tbl_set,
.tf_dev_set_ext_tbl = tf_tbl_ext_common_set,
.tf_dev_get_tbl = tf_tbl_get,
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c
index 6bbc5e21e9..ce4d8c661f 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.c
@@ -280,7 +280,6 @@ const struct tf_dev_ops tf_dev_ops_p58_init = {
.tf_dev_alloc_tbl = NULL,
.tf_dev_free_ext_tbl = NULL,
.tf_dev_free_tbl = NULL,
- .tf_dev_alloc_search_tbl = NULL,
.tf_dev_set_tbl = NULL,
.tf_dev_set_ext_tbl = NULL,
.tf_dev_get_tbl = NULL,
@@ -326,7 +325,6 @@ const struct tf_dev_ops tf_dev_ops_p58 = {
.tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc,
.tf_dev_free_tbl = tf_tbl_free,
.tf_dev_free_ext_tbl = tf_tbl_ext_free,
- .tf_dev_alloc_search_tbl = tf_tbl_alloc_search,
.tf_dev_set_tbl = tf_tbl_set,
.tf_dev_set_ext_tbl = tf_tbl_ext_common_set,
.tf_dev_get_tbl = tf_tbl_get,
diff --git a/drivers/net/bnxt/tf_core/tf_em_common.c b/drivers/net/bnxt/tf_core/tf_em_common.c
index 812ccb0d29..3bdfc14e05 100644
--- a/drivers/net/bnxt/tf_core/tf_em_common.c
+++ b/drivers/net/bnxt/tf_core/tf_em_common.c
@@ -23,6 +23,10 @@
#include "bnxt.h"
+
+/** Invalid table scope id */
+#define TF_TBL_SCOPE_INVALID 0xffffffff
+
/* Number of pointers per page_size */
#define MAX_PAGE_PTRS(page_size) ((page_size) / sizeof(void *))
diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c
index ced59130b2..e77399c6bd 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl.c
+++ b/drivers/net/bnxt/tf_core/tf_tbl.c
@@ -26,11 +26,6 @@
struct tf;
-/**
- * Table Shadow DBs
- */
-static void *shadow_tbl_db[TF_DIR_MAX];
-
/**
* Shadow init flag, set on bind and cleared on unbind
*/
@@ -327,22 +322,6 @@ tf_tbl_free(struct tf *tfp __rte_unused,
return 0;
}
-int
-tf_tbl_alloc_search(struct tf *tfp,
- struct tf_tbl_alloc_search_parms *parms)
-{
- int rc = 0;
- TF_CHECK_PARMS2(tfp, parms);
-
- if (!shadow_init || !shadow_tbl_db[parms->dir]) {
- TFP_DRV_LOG(ERR, "%s: Shadow TBL not initialized.\n",
- tf_dir_2_str(parms->dir));
- return -EINVAL;
- }
-
- return rc;
-}
-
int
tf_tbl_set(struct tf *tfp,
struct tf_tbl_set_parms *parms)
diff --git a/drivers/net/bnxt/tf_core/tf_tbl.h b/drivers/net/bnxt/tf_core/tf_tbl.h
index aba46fd161..7e1107ffe7 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl.h
+++ b/drivers/net/bnxt/tf_core/tf_tbl.h
@@ -15,8 +15,6 @@ struct tf;
* The Table module provides processing of Internal TF table types.
*/
-/** Invalid table scope id */
-#define TF_TBL_SCOPE_INVALID 0xffffffff
/**
* Table configuration parameters
@@ -86,57 +84,6 @@ struct tf_tbl_free_parms {
* [in] Index to free
*/
uint32_t idx;
- /**
- * [out] Reference count after free, only valid if session has been
- * created with shadow_copy.
- */
- uint16_t ref_cnt;
-};
-
-/**
- * Table allocate search parameters
- */
-struct tf_tbl_alloc_search_parms {
- /**
- * [in] Receive or transmit direction
- */
- enum tf_dir dir;
- /**
- * [in] Type of the allocation
- */
- enum tf_tbl_type type;
- /**
- * [in] Table scope identifier (ignored unless TF_TBL_TYPE_EXT)
- */
- uint32_t tbl_scope_id;
- /**
- * [in] Result data to search for
- */
- uint8_t *result;
- /**
- * [in] Result data size in bytes
- */
- uint16_t result_sz_in_bytes;
- /**
- * [in] Whether or not to allocate on MISS, 1 is allocate.
- */
- uint8_t alloc;
- /**
- * [out] If search_enable, set if matching entry found
- */
- uint8_t hit;
- /**
- * [out] The status of the search (REJECT, MISS, HIT)
- */
- enum tf_search_status search_status;
- /**
- * [out] Current ref count after allocation
- */
- uint16_t ref_cnt;
- /**
- * [out] Idx of allocated entry or found entry
- */
- uint32_t idx;
};
/**
@@ -326,25 +273,6 @@ int tf_tbl_alloc(struct tf *tfp,
int tf_tbl_free(struct tf *tfp,
struct tf_tbl_free_parms *parms);
-/**
- * Supported if Shadow DB is configured. Searches the Shadow DB for
- * any matching element. If found the refcount in the shadow DB is
- * updated accordingly. If not found a new element is allocated and
- * installed into the shadow DB.
- *
- * [in] tfp
- * Pointer to TF handle, used for HCAPI communication
- *
- * [in] parms
- * Pointer to parameters
- *
- * Returns
- * - (0) if successful.
- * - (-EINVAL) on failure.
- */
-int tf_tbl_alloc_search(struct tf *tfp,
- struct tf_tbl_alloc_search_parms *parms);
-
/**
* Configures the requested element by sending a firmware request which
* then installs it into the device internal structures.
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 871dbad0fe..f3a60cc880 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -189,13 +189,12 @@ ulp_mapper_resource_index_tbl_alloc(struct bnxt_ulp_context *ulp_ctx,
aparms.type = glb_res->resource_type;
aparms.dir = glb_res->direction;
- aparms.search_enable = 0;
aparms.tbl_scope_id = tbl_scope_id;
/* Allocate the index tbl using tf api */
rc = tf_alloc_tbl_entry(tfp, &aparms);
if (rc) {
- BNXT_TF_DBG(ERR, "Failed to alloc identifier [%s][%d]\n",
+ BNXT_TF_DBG(ERR, "Failed to alloc index table [%s][%d]\n",
tf_dir_2_str(aparms.dir), aparms.type);
return rc;
}
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* Re: [dpdk-dev] [PATCH v3 01/13] net/bnxt: tf core index table updates
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 01/13] net/bnxt: tf core index table updates Venkat Duvvuru
@ 2021-09-16 13:47 ` Ferruh Yigit
2021-09-16 15:51 ` Ajit Khaparde
0 siblings, 1 reply; 83+ messages in thread
From: Ferruh Yigit @ 2021-09-16 13:47 UTC (permalink / raw)
To: Ajit Khaparde; +Cc: Farah Smith, Venkat Duvvuru, dev
On 9/11/2021 4:30 PM, Venkat Duvvuru wrote:
> From: Farah Smith <farah.smith@broadcom.com>
>
> Remove unused shadow table functionality.
>
Can you please update 'tf' (or 'TF') in the patch titles with 'TruFlow', to make
it more clear and consistent with the previous commits?
Ajit,
Also can you add 'TruFlow' to the 'devtools/words-case.txt', to have automated
checks on it, if you believe it can be useful?
Thanks,
ferruh
> Signed-off-by: Farah Smith <farah.smith@broadcom.com>
> Reviewed-by: Peter Spreadborough <peter.spreadborough@broadcom.com>
> ---
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [dpdk-dev] [PATCH v3 01/13] net/bnxt: tf core index table updates
2021-09-16 13:47 ` Ferruh Yigit
@ 2021-09-16 15:51 ` Ajit Khaparde
0 siblings, 0 replies; 83+ messages in thread
From: Ajit Khaparde @ 2021-09-16 15:51 UTC (permalink / raw)
To: Ferruh Yigit; +Cc: Farah Smith, Venkat Duvvuru, dpdk-dev
[-- Attachment #1: Type: text/plain, Size: 751 bytes --]
On Thu, Sep 16, 2021 at 6:47 AM Ferruh Yigit <ferruh.yigit@intel.com> wrote:
>
> On 9/11/2021 4:30 PM, Venkat Duvvuru wrote:
> > From: Farah Smith <farah.smith@broadcom.com>
> >
> > Remove unused shadow table functionality.
> >
>
> Can you please update 'tf' (or 'TF') in the patch titles with 'TruFlow', to make
> it more clear and consistent with the previous commits?
>
>
> Ajit,
>
> Also can you add 'TruFlow' to the 'devtools/words-case.txt', to have automated
> checks on it, if you believe it can be useful?
Yes. Let me add that. That way it won't be flagged as a spelling error.
>
> Thanks,
> ferruh
>
> > Signed-off-by: Farah Smith <farah.smith@broadcom.com>
> > Reviewed-by: Peter Spreadborough <peter.spreadborough@broadcom.com>
> > ---
>
^ permalink raw reply [flat|nested] 83+ messages in thread
* [dpdk-dev] [PATCH v3 02/13] net/bnxt: enable dpool allocator
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 00/13] enhancements to host based flow table management Venkat Duvvuru
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 01/13] net/bnxt: tf core index table updates Venkat Duvvuru
@ 2021-09-11 15:30 ` Venkat Duvvuru
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 03/13] net/bnxt: add flow meter drop counter support Venkat Duvvuru
` (12 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-11 15:30 UTC (permalink / raw)
To: dev; +Cc: Peter Spreadborough
From: Peter Spreadborough <peter.spreadborough@broadcom.com>
Enable dynamic entry allocator for EM SRAM entries.
Deprecate static entry allocator code.
Signed-off-by: Peter Spreadborough <peter.spreadborough@broadcom.com>
Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
---
drivers/net/bnxt/tf_core/tf_device_p58.c | 4 -
drivers/net/bnxt/tf_core/tf_em.h | 10 -
.../net/bnxt/tf_core/tf_em_hash_internal.c | 34 ----
drivers/net/bnxt/tf_core/tf_em_internal.c | 180 +-----------------
4 files changed, 1 insertion(+), 227 deletions(-)
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c
index ce4d8c661f..808dcb1f77 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.c
@@ -348,11 +348,7 @@ const struct tf_dev_ops tf_dev_ops_p58 = {
.tf_dev_get_tcam_resc_info = tf_tcam_get_resc_info,
.tf_dev_insert_int_em_entry = tf_em_hash_insert_int_entry,
.tf_dev_delete_int_em_entry = tf_em_hash_delete_int_entry,
-#if (TF_EM_ALLOC == 1)
.tf_dev_move_int_em_entry = tf_em_move_int_entry,
-#else
- .tf_dev_move_int_em_entry = NULL,
-#endif
.tf_dev_insert_ext_em_entry = NULL,
.tf_dev_delete_ext_em_entry = NULL,
.tf_dev_get_em_resc_info = tf_em_get_resc_info,
diff --git a/drivers/net/bnxt/tf_core/tf_em.h b/drivers/net/bnxt/tf_core/tf_em.h
index 568071ad8c..074c128651 100644
--- a/drivers/net/bnxt/tf_core/tf_em.h
+++ b/drivers/net/bnxt/tf_core/tf_em.h
@@ -13,16 +13,6 @@
#include "hcapi_cfa_defs.h"
-/**
- * TF_EM_ALLOC
- *
- * 0: Use stack allocator with fixed sized entries
- * (default).
- * 1: Use dpool allocator with variable size
- * entries.
- */
-#define TF_EM_ALLOC 0
-
#define TF_EM_MIN_ENTRIES (1 << 15) /* 32K */
#define TF_EM_MAX_ENTRIES (1 << 27) /* 128M */
diff --git a/drivers/net/bnxt/tf_core/tf_em_hash_internal.c b/drivers/net/bnxt/tf_core/tf_em_hash_internal.c
index 098e8af07e..60273a798c 100644
--- a/drivers/net/bnxt/tf_core/tf_em_hash_internal.c
+++ b/drivers/net/bnxt/tf_core/tf_em_hash_internal.c
@@ -22,9 +22,7 @@
/**
* EM Pool
*/
-#if (TF_EM_ALLOC == 1)
#include "dpool.h"
-#endif
/**
* Insert EM internal entry API
@@ -41,11 +39,7 @@ tf_em_hash_insert_int_entry(struct tf *tfp,
uint16_t rptr_index = 0;
uint8_t rptr_entry = 0;
uint8_t num_of_entries = 0;
-#if (TF_EM_ALLOC == 1)
struct dpool *pool;
-#else
- struct stack *pool;
-#endif
uint32_t index;
uint32_t key0_hash;
uint32_t key1_hash;
@@ -62,7 +56,6 @@ tf_em_hash_insert_int_entry(struct tf *tfp,
rc = tf_session_get_device(tfs, &dev);
if (rc)
return rc;
-#if (TF_EM_ALLOC == 1)
pool = (struct dpool *)tfs->em_pool[parms->dir];
index = dpool_alloc(pool,
parms->em_record_sz_in_bits / 128,
@@ -74,16 +67,6 @@ tf_em_hash_insert_int_entry(struct tf *tfp,
tf_dir_2_str(parms->dir));
return -1;
}
-#else
- pool = (struct stack *)tfs->em_pool[parms->dir];
- rc = stack_pop(pool, &index);
- if (rc) {
- PMD_DRV_LOG(ERR,
- "%s, EM entry index allocation failed\n",
- tf_dir_2_str(parms->dir));
- return rc;
- }
-#endif
if (dev->ops->tf_dev_cfa_key_hash == NULL)
return -EINVAL;
@@ -103,11 +86,7 @@ tf_em_hash_insert_int_entry(struct tf *tfp,
&num_of_entries);
if (rc) {
/* Free the allocated index before returning */
-#if (TF_EM_ALLOC == 1)
dpool_free(pool, index);
-#else
- stack_push(pool, index);
-#endif
return -1;
}
@@ -128,9 +107,7 @@ tf_em_hash_insert_int_entry(struct tf *tfp,
rptr_index,
rptr_entry,
0);
-#if (TF_EM_ALLOC == 1)
dpool_set_entry_data(pool, index, parms->flow_handle);
-#endif
return 0;
}
@@ -146,11 +123,7 @@ tf_em_hash_delete_int_entry(struct tf *tfp,
{
int rc = 0;
struct tf_session *tfs;
-#if (TF_EM_ALLOC == 1)
struct dpool *pool;
-#else
- struct stack *pool;
-#endif
/* Retrieve the session information */
rc = tf_session_get_session(tfp, &tfs);
if (rc) {
@@ -165,19 +138,13 @@ tf_em_hash_delete_int_entry(struct tf *tfp,
/* Return resource to pool */
if (rc == 0) {
-#if (TF_EM_ALLOC == 1)
pool = (struct dpool *)tfs->em_pool[parms->dir];
dpool_free(pool, parms->index);
-#else
- pool = (struct stack *)tfs->em_pool[parms->dir];
- stack_push(pool, parms->index);
-#endif
}
return rc;
}
-#if (TF_EM_ALLOC == 1)
/** Move EM internal entry API
*
* returns:
@@ -212,4 +179,3 @@ tf_em_move_int_entry(struct tf *tfp,
return rc;
}
-#endif
diff --git a/drivers/net/bnxt/tf_core/tf_em_internal.c b/drivers/net/bnxt/tf_core/tf_em_internal.c
index 0720bb905d..2d57595f17 100644
--- a/drivers/net/bnxt/tf_core/tf_em_internal.c
+++ b/drivers/net/bnxt/tf_core/tf_em_internal.c
@@ -22,145 +22,7 @@
/**
* EM Pool
*/
-#if (TF_EM_ALLOC == 1)
#include "dpool.h"
-#else
-
-/**
- * Create EM Tbl pool of memory indexes.
- *
- * [in] dir
- * direction
- * [in] num_entries
- * number of entries to write
- * [in] start
- * starting offset
- *
- * Return:
- * 0 - Success, entry allocated - no search support
- * -ENOMEM -EINVAL -EOPNOTSUPP
- * - Failure, entry not allocated, out of resources
- */
-static int
-tf_create_em_pool(struct tf_session *tfs,
- enum tf_dir dir,
- uint32_t num_entries,
- uint32_t start)
-{
- struct tfp_calloc_parms parms;
- uint32_t i, j;
- int rc = 0;
- struct stack *pool;
-
- /*
- * Allocate stack pool
- */
- parms.nitems = 1;
- parms.size = sizeof(struct stack);
- parms.alignment = 0;
-
- rc = tfp_calloc(&parms);
-
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s, EM stack allocation failure %s\n",
- tf_dir_2_str(dir),
- strerror(-rc));
- return rc;
- }
-
- pool = (struct stack *)parms.mem_va;
- tfs->em_pool[dir] = (void *)pool;
-
- /* Assumes that num_entries has been checked before we get here */
- parms.nitems = num_entries / TF_SESSION_EM_ENTRY_SIZE;
- parms.size = sizeof(uint32_t);
- parms.alignment = 0;
-
- rc = tfp_calloc(&parms);
-
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s, EM pool allocation failure %s\n",
- tf_dir_2_str(dir),
- strerror(-rc));
- return rc;
- }
-
- /* Create empty stack
- */
- rc = stack_init(num_entries / TF_SESSION_EM_ENTRY_SIZE,
- (uint32_t *)parms.mem_va,
- pool);
-
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s, EM pool stack init failure %s\n",
- tf_dir_2_str(dir),
- strerror(-rc));
- goto cleanup;
- }
-
- /* Fill pool with indexes
- */
- j = start + num_entries - TF_SESSION_EM_ENTRY_SIZE;
-
- for (i = 0; i < (num_entries / TF_SESSION_EM_ENTRY_SIZE); i++) {
- rc = stack_push(pool, j);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s, EM pool stack push failure %s\n",
- tf_dir_2_str(dir),
- strerror(-rc));
- goto cleanup;
- }
-
- j -= TF_SESSION_EM_ENTRY_SIZE;
- }
-
- if (!stack_is_full(pool)) {
- rc = -EINVAL;
- TFP_DRV_LOG(ERR,
- "%s, EM pool stack failure %s\n",
- tf_dir_2_str(dir),
- strerror(-rc));
- goto cleanup;
- }
-
- return 0;
-cleanup:
- tfp_free((void *)parms.mem_va);
- tfp_free((void *)tfs->em_pool[dir]);
- tfs->em_pool[dir] = NULL;
- return rc;
-}
-
-/**
- * Create EM Tbl pool of memory indexes.
- *
- * [in] dir
- * direction
- *
- * Return:
- */
-static void
-tf_free_em_pool(struct tf_session *tfs,
- enum tf_dir dir)
-{
- struct stack *pool = (struct stack *)tfs->em_pool[dir];
- uint32_t *ptr;
-
- if (pool != NULL) {
- ptr = stack_items(pool);
-
- if (ptr != NULL)
- tfp_free(ptr);
-
- tfp_free(pool);
- tfs->em_pool[dir] = NULL;
- }
-}
-#endif /* TF_EM_ALLOC != 1 */
/**
* Insert EM internal entry API
@@ -178,11 +40,7 @@ tf_em_insert_int_entry(struct tf *tfp,
uint8_t rptr_entry = 0;
uint8_t num_of_entries = 0;
struct tf_session *tfs;
-#if (TF_EM_ALLOC == 1)
struct dpool *pool;
-#else
- struct stack *pool;
-#endif
uint32_t index;
/* Retrieve the session information */
@@ -195,7 +53,6 @@ tf_em_insert_int_entry(struct tf *tfp,
return rc;
}
-#if (TF_EM_ALLOC == 1)
pool = (struct dpool *)tfs->em_pool[parms->dir];
index = dpool_alloc(pool, TF_SESSION_EM_ENTRY_SIZE, 0);
if (index == DP_INVALID_INDEX) {
@@ -204,16 +61,6 @@ tf_em_insert_int_entry(struct tf *tfp,
tf_dir_2_str(parms->dir));
return -1;
}
-#else
- pool = (struct stack *)tfs->em_pool[parms->dir];
- rc = stack_pop(pool, &index);
- if (rc) {
- PMD_DRV_LOG(ERR,
- "%s, EM entry index allocation failed\n",
- tf_dir_2_str(parms->dir));
- return rc;
- }
-#endif
rptr_index = index;
@@ -224,11 +71,7 @@ tf_em_insert_int_entry(struct tf *tfp,
&num_of_entries);
if (rc) {
/* Free the allocated index before returning */
-#if (TF_EM_ALLOC == 1)
dpool_free(pool, index);
-#else
- stack_push(pool, index);
-#endif
return -1;
}
TF_SET_GFID(gfid,
@@ -264,11 +107,7 @@ tf_em_delete_int_entry(struct tf *tfp,
{
int rc = 0;
struct tf_session *tfs;
-#if (TF_EM_ALLOC == 1)
struct dpool *pool;
-#else
- struct stack *pool;
-#endif
/* Retrieve the session information */
rc = tf_session_get_session(tfp, &tfs);
if (rc) {
@@ -283,19 +122,13 @@ tf_em_delete_int_entry(struct tf *tfp,
/* Return resource to pool */
if (rc == 0) {
-#if (TF_EM_ALLOC == 1)
pool = (struct dpool *)tfs->em_pool[parms->dir];
dpool_free(pool, parms->index);
-#else
- pool = (struct stack *)tfs->em_pool[parms->dir];
- stack_push(pool, parms->index);
-#endif
}
return rc;
}
-#if (TF_EM_ALLOC == 1)
static int
tf_em_move_callback(void *user_data,
uint64_t entry_data,
@@ -342,7 +175,6 @@ tf_em_move_callback(void *user_data,
return rc;
}
-#endif
int
tf_em_int_bind(struct tf *tfp,
@@ -434,7 +266,7 @@ tf_em_int_bind(struct tf *tfp,
tf_dir_2_str(i));
return rc;
}
-#if (TF_EM_ALLOC == 1)
+
/*
* Allocate stack pool
*/
@@ -460,12 +292,6 @@ tf_em_int_bind(struct tf *tfp,
7,
(void *)tfp,
tf_em_move_callback);
-#else
- rc = tf_create_em_pool(tfs,
- i,
- iparms.info->entry.stride,
- iparms.info->entry.start);
-#endif
/* Logging handled in tf_create_em_pool */
if (rc)
return rc;
@@ -501,11 +327,7 @@ tf_em_int_unbind(struct tf *tfp)
if (!tf_session_is_shared_session(tfs)) {
for (i = 0; i < TF_DIR_MAX; i++)
-#if (TF_EM_ALLOC == 1)
dpool_free_all(tfs->em_pool[i]);
-#else
- tf_free_em_pool(tfs, i);
-#endif
}
rc = tf_session_get_db(tfp, TF_MODULE_TYPE_EM, &em_db_ptr);
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v3 03/13] net/bnxt: add flow meter drop counter support
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 00/13] enhancements to host based flow table management Venkat Duvvuru
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 01/13] net/bnxt: tf core index table updates Venkat Duvvuru
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 02/13] net/bnxt: enable dpool allocator Venkat Duvvuru
@ 2021-09-11 15:30 ` Venkat Duvvuru
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 04/13] net/bnxt: add Thor SRAM mgr model Venkat Duvvuru
` (11 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-11 15:30 UTC (permalink / raw)
To: dev; +Cc: Jay Ding
From: Jay Ding <jay.ding@broadcom.com>
- Add flow meter drop counter support for Thor.
Signed-off-by: Jay Ding <jay.ding@broadcom.com>
Reviewed-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/tf_core/cfa_resource_types.h | 5 +-
drivers/net/bnxt/tf_core/tf_core.h | 8 +-
drivers/net/bnxt/tf_core/tf_device_p58.c | 1 +
drivers/net/bnxt/tf_core/tf_device_p58.h | 14 ++++
drivers/net/bnxt/tf_core/tf_tbl.c | 74 +++++++++++--------
drivers/net/bnxt/tf_core/tf_util.c | 2 +
6 files changed, 68 insertions(+), 36 deletions(-)
diff --git a/drivers/net/bnxt/tf_core/cfa_resource_types.h b/drivers/net/bnxt/tf_core/cfa_resource_types.h
index cbab0d0078..36a55d4e17 100644
--- a/drivers/net/bnxt/tf_core/cfa_resource_types.h
+++ b/drivers/net/bnxt/tf_core/cfa_resource_types.h
@@ -104,10 +104,11 @@
#define CFA_RESOURCE_TYPE_P58_WC_FKB 0x12UL
/* VEB TCAM */
#define CFA_RESOURCE_TYPE_P58_VEB_TCAM 0x13UL
+/* Metadata */
+#define CFA_RESOURCE_TYPE_P58_METADATA 0x14UL
/* Meter drop counter */
#define CFA_RESOURCE_TYPE_P58_METER_DROP_CNT 0x15UL
-#define CFA_RESOURCE_TYPE_P58_LAST CFA_RESOURCE_TYPE_P58_METER_DROP_CNT
-
+#define CFA_RESOURCE_TYPE_P58_LAST CFA_RESOURCE_TYPE_P58_METER_DROP_CNT
/* Multicast Group */
#define CFA_RESOURCE_TYPE_P45_MCG 0x0UL
diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h
index 7e0cdf7e0d..af8d13bd7e 100644
--- a/drivers/net/bnxt/tf_core/tf_core.h
+++ b/drivers/net/bnxt/tf_core/tf_core.h
@@ -283,9 +283,9 @@ enum tf_tbl_type {
TF_TBL_TYPE_ACT_MODIFY_32B,
/** TH 64B Modify Record */
TF_TBL_TYPE_ACT_MODIFY_64B,
- /** (Future) Meter Profiles */
+ /** Meter Profiles */
TF_TBL_TYPE_METER_PROF,
- /** (Future) Meter Instance */
+ /** Meter Instance */
TF_TBL_TYPE_METER_INST,
/** Wh+/SR/Th Mirror Config */
TF_TBL_TYPE_MIRROR_CONFIG,
@@ -301,6 +301,8 @@ enum tf_tbl_type {
TF_TBL_TYPE_EM_FKB,
/** TH WC Flexible Key builder */
TF_TBL_TYPE_WC_FKB,
+ /** Meter Drop Counter */
+ TF_TBL_TYPE_METER_DROP_CNT,
/* External */
@@ -2194,6 +2196,8 @@ enum tf_global_config_type {
TF_TUNNEL_ENCAP, /**< Tunnel Encap Config(TECT) */
TF_ACTION_BLOCK, /**< Action Block Config(ABCR) */
TF_COUNTER_CFG, /**< Counter Configuration (CNTRS_CTRL) */
+ TF_METER_CFG, /**< Meter Config(ACTP4_FMTCR) */
+ TF_METER_INTERVAL_CFG, /**< Meter Interval Config(FMTCR_INTERVAL) */
TF_GLOBAL_CFG_TYPE_MAX
};
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c
index 808dcb1f77..a492c62bff 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.c
@@ -43,6 +43,7 @@ const char *tf_resource_str_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = {
[CFA_RESOURCE_TYPE_P58_EM_FKB] = "em_fkb ",
[CFA_RESOURCE_TYPE_P58_WC_FKB] = "wc_fkb ",
[CFA_RESOURCE_TYPE_P58_VEB_TCAM] = "veb ",
+ [CFA_RESOURCE_TYPE_P58_METADATA] = "metadata",
};
/**
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h
index 66b0f4e983..8c2e07aa34 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.h
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.h
@@ -75,10 +75,18 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER,
0, 0, 0
},
+ [TF_TBL_TYPE_METER_DROP_CNT] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT,
+ 0, 0, 0
+ },
[TF_TBL_TYPE_MIRROR_CONFIG] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR,
0, 0, 0
},
+ [TF_TBL_TYPE_METADATA] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA,
+ 0, 0, 0
+ },
/* Policy - ARs in bank 1 */
[TF_TBL_TYPE_FULL_ACT_RECORD] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
@@ -194,5 +202,11 @@ struct tf_global_cfg_cfg tf_global_cfg_p58[TF_GLOBAL_CFG_TYPE_MAX] = {
[TF_COUNTER_CFG] = {
TF_GLOBAL_CFG_CFG_HCAPI, TF_COUNTER_CFG
},
+ [TF_METER_CFG] = {
+ TF_GLOBAL_CFG_CFG_HCAPI, TF_METER_CFG
+ },
+ [TF_METER_INTERVAL_CFG] = {
+ TF_GLOBAL_CFG_CFG_HCAPI, TF_METER_INTERVAL_CFG
+ },
};
#endif /* _TF_DEVICE_P58_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c
index e77399c6bd..7011edcd78 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl.c
+++ b/drivers/net/bnxt/tf_core/tf_tbl.c
@@ -374,23 +374,28 @@ tf_tbl_set(struct tf *tfp,
}
}
- /* Verify that the entry has been previously allocated */
- aparms.rm_db = tbl_db->tbl_db[parms->dir];
- aparms.subtype = parms->type;
- TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift);
-
- aparms.allocated = &allocated;
- rc = tf_rm_is_allocated(&aparms);
- if (rc)
- return rc;
+ /* Do not check meter drop counter because it is not allocated
+ * resources
+ */
+ if (parms->type != TF_TBL_TYPE_METER_DROP_CNT) {
+ /* Verify that the entry has been previously allocated */
+ aparms.rm_db = tbl_db->tbl_db[parms->dir];
+ aparms.subtype = parms->type;
+ TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift);
+
+ aparms.allocated = &allocated;
+ rc = tf_rm_is_allocated(&aparms);
+ if (rc)
+ return rc;
- if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
- TFP_DRV_LOG(ERR,
- "%s, Invalid or not allocated index, type:%d, idx:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type,
- parms->idx);
- return -EINVAL;
+ if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
+ TFP_DRV_LOG(ERR,
+ "%s, Invalid or not allocated index, type:%d, idx:%d\n",
+ tf_dir_2_str(parms->dir),
+ parms->type,
+ parms->idx);
+ return -EINVAL;
+ }
}
/* Set the entry */
@@ -477,23 +482,28 @@ tf_tbl_get(struct tf *tfp,
}
}
- /* Verify that the entry has been previously allocated */
- aparms.rm_db = tbl_db->tbl_db[parms->dir];
- aparms.subtype = parms->type;
- TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift);
-
- aparms.allocated = &allocated;
- rc = tf_rm_is_allocated(&aparms);
- if (rc)
- return rc;
+ /* Do not check meter drop counter because it is not allocated
+ * resources.
+ */
+ if (parms->type != TF_TBL_TYPE_METER_DROP_CNT) {
+ /* Verify that the entry has been previously allocated */
+ aparms.rm_db = tbl_db->tbl_db[parms->dir];
+ aparms.subtype = parms->type;
+ TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift);
+
+ aparms.allocated = &allocated;
+ rc = tf_rm_is_allocated(&aparms);
+ if (rc)
+ return rc;
- if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
- TFP_DRV_LOG(ERR,
- "%s, Invalid or not allocated index, type:%d, idx:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type,
- parms->idx);
- return -EINVAL;
+ if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
+ TFP_DRV_LOG(ERR,
+ "%s, Invalid or not allocated index, type:%d, idx:%d\n",
+ tf_dir_2_str(parms->dir),
+ parms->type,
+ parms->idx);
+ return -EINVAL;
+ }
}
/* Set the entry */
diff --git a/drivers/net/bnxt/tf_core/tf_util.c b/drivers/net/bnxt/tf_core/tf_util.c
index e712816209..d100399d0a 100644
--- a/drivers/net/bnxt/tf_core/tf_util.c
+++ b/drivers/net/bnxt/tf_core/tf_util.c
@@ -112,6 +112,8 @@ tf_tbl_type_2_str(enum tf_tbl_type tbl_type)
return "WC Flexible Key Builder";
case TF_TBL_TYPE_EXT:
return "External";
+ case TF_TBL_TYPE_METER_DROP_CNT:
+ return "Meter drop counter";
default:
return "Invalid tbl type";
}
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v3 04/13] net/bnxt: add Thor SRAM mgr model
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 00/13] enhancements to host based flow table management Venkat Duvvuru
` (2 preceding siblings ...)
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 03/13] net/bnxt: add flow meter drop counter support Venkat Duvvuru
@ 2021-09-11 15:30 ` Venkat Duvvuru
2021-09-16 13:49 ` Ferruh Yigit
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 05/13] net/bnxt: add flow templates support for Thor Venkat Duvvuru
` (10 subsequent siblings)
14 siblings, 1 reply; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-11 15:30 UTC (permalink / raw)
To: dev; +Cc: Farah Smith
From: Farah Smith <farah.smith@broadcom.com>
Add dynamic SRAM manager allocation support.
Signed-off-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com>
Reviewed-by: Peter Spreadborough <peter.spreadborough@broadcom.com>
---
drivers/net/bnxt/tf_core/ll.c | 3 +
drivers/net/bnxt/tf_core/ll.h | 50 +-
drivers/net/bnxt/tf_core/meson.build | 2 +
drivers/net/bnxt/tf_core/tf_core.c | 104 ++-
drivers/net/bnxt/tf_core/tf_core.h | 48 +-
drivers/net/bnxt/tf_core/tf_device.c | 40 +-
drivers/net/bnxt/tf_core/tf_device.h | 133 ++-
drivers/net/bnxt/tf_core/tf_device_p4.c | 75 +-
drivers/net/bnxt/tf_core/tf_device_p4.h | 50 +-
drivers/net/bnxt/tf_core/tf_device_p58.c | 105 ++-
drivers/net/bnxt/tf_core/tf_device_p58.h | 60 +-
drivers/net/bnxt/tf_core/tf_msg.c | 2 +-
drivers/net/bnxt/tf_core/tf_rm.c | 46 +-
drivers/net/bnxt/tf_core/tf_rm.h | 62 +-
drivers/net/bnxt/tf_core/tf_session.c | 56 ++
drivers/net/bnxt/tf_core/tf_session.h | 58 +-
drivers/net/bnxt/tf_core/tf_sram_mgr.c | 971 ++++++++++++++++++++++
drivers/net/bnxt/tf_core/tf_sram_mgr.h | 317 +++++++
drivers/net/bnxt/tf_core/tf_tbl.c | 186 +----
drivers/net/bnxt/tf_core/tf_tbl.h | 15 +-
drivers/net/bnxt/tf_core/tf_tbl_sram.c | 713 ++++++++++++++++
drivers/net/bnxt/tf_core/tf_tbl_sram.h | 154 ++++
drivers/net/bnxt/tf_core/tf_tcam.c | 10 +-
drivers/net/bnxt/tf_core/tf_tcam.h | 7 +
drivers/net/bnxt/tf_core/tf_tcam_shared.c | 28 +-
drivers/net/bnxt/tf_core/tf_util.c | 10 +
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 23 +
meson_options.txt | 2 +
28 files changed, 2978 insertions(+), 352 deletions(-)
create mode 100644 drivers/net/bnxt/tf_core/tf_sram_mgr.c
create mode 100644 drivers/net/bnxt/tf_core/tf_sram_mgr.h
create mode 100644 drivers/net/bnxt/tf_core/tf_tbl_sram.c
create mode 100644 drivers/net/bnxt/tf_core/tf_tbl_sram.h
diff --git a/drivers/net/bnxt/tf_core/ll.c b/drivers/net/bnxt/tf_core/ll.c
index cd168a7970..f2bdff6b9e 100644
--- a/drivers/net/bnxt/tf_core/ll.c
+++ b/drivers/net/bnxt/tf_core/ll.c
@@ -13,6 +13,7 @@ void ll_init(struct ll *ll)
{
ll->head = NULL;
ll->tail = NULL;
+ ll->cnt = 0;
}
/* insert entry in linked list */
@@ -30,6 +31,7 @@ void ll_insert(struct ll *ll,
entry->next->prev = entry;
ll->head = entry->next->prev;
}
+ ll->cnt++;
}
/* delete entry from linked list */
@@ -49,4 +51,5 @@ void ll_delete(struct ll *ll,
entry->prev->next = entry->next;
entry->next->prev = entry->prev;
}
+ ll->cnt--;
}
diff --git a/drivers/net/bnxt/tf_core/ll.h b/drivers/net/bnxt/tf_core/ll.h
index 239478b4f8..9cf8f64ec2 100644
--- a/drivers/net/bnxt/tf_core/ll.h
+++ b/drivers/net/bnxt/tf_core/ll.h
@@ -8,6 +8,8 @@
#ifndef _LL_H_
#define _LL_H_
+#include <stdint.h>
+
/* linked list entry */
struct ll_entry {
struct ll_entry *prev;
@@ -18,6 +20,7 @@ struct ll_entry {
struct ll {
struct ll_entry *head;
struct ll_entry *tail;
+ uint32_t cnt;
};
/**
@@ -28,7 +31,7 @@ struct ll {
void ll_init(struct ll *ll);
/**
- * Linked list insert
+ * Linked list insert head
*
* [in] ll, linked list where element is inserted
* [in] entry, entry to be added
@@ -43,4 +46,49 @@ void ll_insert(struct ll *ll, struct ll_entry *entry);
*/
void ll_delete(struct ll *ll, struct ll_entry *entry);
+/**
+ * Linked list return next entry without deleting it
+ *
+ * Useful in performing search
+ *
+ * [in] Entry in the list
+ */
+static inline struct ll_entry *ll_next(struct ll_entry *entry)
+{
+ return entry->next;
+}
+
+/**
+ * Linked list return the head of the list without removing it
+ *
+ * Useful in performing search
+ *
+ * [in] ll, linked list
+ */
+static inline struct ll_entry *ll_head(struct ll *ll)
+{
+ return ll->head;
+}
+
+/**
+ * Linked list return the tail of the list without removing it
+ *
+ * Useful in performing search
+ *
+ * [in] ll, linked list
+ */
+static inline struct ll_entry *ll_tail(struct ll *ll)
+{
+ return ll->tail;
+}
+
+/**
+ * Linked list return the number of entries in the list
+ *
+ * [in] ll, linked list
+ */
+static inline uint32_t ll_cnt(struct ll *ll)
+{
+ return ll->cnt;
+}
#endif /* _LL_H_ */
diff --git a/drivers/net/bnxt/tf_core/meson.build b/drivers/net/bnxt/tf_core/meson.build
index f28e77ec2e..b7333a431b 100644
--- a/drivers/net/bnxt/tf_core/meson.build
+++ b/drivers/net/bnxt/tf_core/meson.build
@@ -16,6 +16,8 @@ sources += files(
'stack.c',
'tf_rm.c',
'tf_tbl.c',
+ 'tf_tbl_sram.c',
+ 'tf_sram_mgr.c',
'tf_em_common.c',
'tf_em_host.c',
'tf_em_internal.c',
diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c
index 5458f76e2d..936102c804 100644
--- a/drivers/net/bnxt/tf_core/tf_core.c
+++ b/drivers/net/bnxt/tf_core/tf_core.c
@@ -1079,17 +1079,16 @@ tf_alloc_tbl_entry(struct tf *tfp,
strerror(-rc));
return rc;
}
-
- } else {
- if (dev->ops->tf_dev_alloc_tbl == NULL) {
- rc = -EOPNOTSUPP;
+ } else if (dev->ops->tf_dev_is_sram_managed(tfp, parms->type)) {
+ rc = dev->ops->tf_dev_alloc_sram_tbl(tfp, &aparms);
+ if (rc) {
TFP_DRV_LOG(ERR,
- "%s: Operation not supported, rc:%s\n",
+ "%s: SRAM table allocation failed, rc:%s\n",
tf_dir_2_str(parms->dir),
strerror(-rc));
- return -EOPNOTSUPP;
+ return rc;
}
-
+ } else {
rc = dev->ops->tf_dev_alloc_tbl(tfp, &aparms);
if (rc) {
TFP_DRV_LOG(ERR,
@@ -1162,15 +1161,16 @@ tf_free_tbl_entry(struct tf *tfp,
strerror(-rc));
return rc;
}
- } else {
- if (dev->ops->tf_dev_free_tbl == NULL) {
- rc = -EOPNOTSUPP;
+ } else if (dev->ops->tf_dev_is_sram_managed(tfp, parms->type)) {
+ rc = dev->ops->tf_dev_free_sram_tbl(tfp, &fparms);
+ if (rc) {
TFP_DRV_LOG(ERR,
- "%s: Operation not supported, rc:%s\n",
+ "%s: SRAM table free failed, rc:%s\n",
tf_dir_2_str(parms->dir),
strerror(-rc));
- return -EOPNOTSUPP;
+ return rc;
}
+ } else {
rc = dev->ops->tf_dev_free_tbl(tfp, &fparms);
if (rc) {
@@ -1181,7 +1181,6 @@ tf_free_tbl_entry(struct tf *tfp,
return rc;
}
}
-
return 0;
}
@@ -1244,6 +1243,15 @@ tf_set_tbl_entry(struct tf *tfp,
strerror(-rc));
return rc;
}
+ } else if (dev->ops->tf_dev_is_sram_managed(tfp, parms->type)) {
+ rc = dev->ops->tf_dev_set_sram_tbl(tfp, &sparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: SRAM table set failed, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ strerror(-rc));
+ return rc;
+ }
} else {
if (dev->ops->tf_dev_set_tbl == NULL) {
rc = -EOPNOTSUPP;
@@ -1300,28 +1308,39 @@ tf_get_tbl_entry(struct tf *tfp,
strerror(-rc));
return rc;
}
-
- if (dev->ops->tf_dev_get_tbl == NULL) {
- rc = -EOPNOTSUPP;
- TFP_DRV_LOG(ERR,
- "%s: Operation not supported, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(-rc));
- return -EOPNOTSUPP;
- }
-
gparms.dir = parms->dir;
gparms.type = parms->type;
gparms.data = parms->data;
gparms.data_sz_in_bytes = parms->data_sz_in_bytes;
gparms.idx = parms->idx;
- rc = dev->ops->tf_dev_get_tbl(tfp, &gparms);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Table get failed, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(-rc));
- return rc;
+
+ if (dev->ops->tf_dev_is_sram_managed(tfp, parms->type)) {
+ rc = dev->ops->tf_dev_get_sram_tbl(tfp, &gparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: SRAM table get failed, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ strerror(-rc));
+ return rc;
+ }
+ } else {
+ if (dev->ops->tf_dev_get_tbl == NULL) {
+ rc = -EOPNOTSUPP;
+ TFP_DRV_LOG(ERR,
+ "%s: Operation not supported, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ strerror(-rc));
+ return -EOPNOTSUPP;
+ }
+
+ rc = dev->ops->tf_dev_get_tbl(tfp, &gparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Table get failed, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ strerror(-rc));
+ return rc;
+ }
}
return rc;
@@ -1361,6 +1380,13 @@ tf_bulk_get_tbl_entry(struct tf *tfp,
return rc;
}
+ bparms.dir = parms->dir;
+ bparms.type = parms->type;
+ bparms.starting_idx = parms->starting_idx;
+ bparms.num_entries = parms->num_entries;
+ bparms.entry_sz_in_bytes = parms->entry_sz_in_bytes;
+ bparms.physical_mem_addr = parms->physical_mem_addr;
+
if (parms->type == TF_TBL_TYPE_EXT) {
/* Not supported, yet */
rc = -EOPNOTSUPP;
@@ -1370,10 +1396,17 @@ tf_bulk_get_tbl_entry(struct tf *tfp,
strerror(-rc));
return rc;
+ } else if (dev->ops->tf_dev_is_sram_managed(tfp, parms->type)) {
+ rc = dev->ops->tf_dev_get_bulk_sram_tbl(tfp, &bparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: SRAM table bulk get failed, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ strerror(-rc));
+ }
+ return rc;
}
- /* Internal table type processing */
-
if (dev->ops->tf_dev_get_bulk_tbl == NULL) {
rc = -EOPNOTSUPP;
TFP_DRV_LOG(ERR,
@@ -1383,12 +1416,6 @@ tf_bulk_get_tbl_entry(struct tf *tfp,
return -EOPNOTSUPP;
}
- bparms.dir = parms->dir;
- bparms.type = parms->type;
- bparms.starting_idx = parms->starting_idx;
- bparms.num_entries = parms->num_entries;
- bparms.entry_sz_in_bytes = parms->entry_sz_in_bytes;
- bparms.physical_mem_addr = parms->physical_mem_addr;
rc = dev->ops->tf_dev_get_bulk_tbl(tfp, &bparms);
if (rc) {
TFP_DRV_LOG(ERR,
@@ -1397,7 +1424,6 @@ tf_bulk_get_tbl_entry(struct tf *tfp,
strerror(-rc));
return rc;
}
-
return rc;
}
diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h
index af8d13bd7e..fb02c2b161 100644
--- a/drivers/net/bnxt/tf_core/tf_core.h
+++ b/drivers/net/bnxt/tf_core/tf_core.h
@@ -65,6 +65,16 @@ enum tf_ext_mem_chan_type {
TF_EXT_MEM_CHAN_TYPE_MAX
};
+/**
+ * WC TCAM number of slice per row that devices supported
+ */
+enum tf_wc_num_slice {
+ TF_WC_TCAM_1_SLICE_PER_ROW = 1,
+ TF_WC_TCAM_2_SLICE_PER_ROW = 2,
+ TF_WC_TCAM_4_SLICE_PER_ROW = 4,
+ TF_WC_TCAM_8_SLICE_PER_ROW = 8,
+};
+
/**
* EEM record AR helper
*
@@ -670,6 +680,13 @@ struct tf_open_session_parms {
*/
void *bp;
+ /**
+ * [in]
+ *
+ * The number of slices per row for WC TCAM entry.
+ */
+ enum tf_wc_num_slice wc_num_slices;
+
/**
* [out] shared_session_creator
*
@@ -734,8 +751,6 @@ int tf_open_session(struct tf *tfp,
/**
* General internal resource info
*
- * TODO: remove tf_rm_new_entry structure and use this structure
- * internally.
*/
struct tf_resource_info {
uint16_t start;
@@ -1656,12 +1671,7 @@ struct tf_alloc_tbl_entry_parms {
* entry of the indicated type for this TruFlow session.
*
* Allocates an index table record. This function will attempt to
- * allocate an entry or search an index table for a matching entry if
- * search is enabled (only the shadow copy of the table is accessed).
- *
- * If search is not enabled, the first available free entry is
- * returned. If search is enabled and a matching entry to entry_data
- * is found hit is set to TRUE and success is returned.
+ * allocate an index table entry.
*
* External types:
*
@@ -1670,8 +1680,8 @@ struct tf_alloc_tbl_entry_parms {
* Allocates an external index table action record.
*
* NOTE:
- * Implementation of the internals of this function will be a stack with push
- * and pop.
+ * Implementation of the internals of the external function will be a stack with
+ * push and pop.
*
* Returns success or failure code.
*/
@@ -1707,20 +1717,15 @@ struct tf_free_tbl_entry_parms {
*
* Internal types:
*
- * If session has shadow_copy enabled the shadow DB is searched and if
- * found the element ref_cnt is decremented. If ref_cnt goes to
- * zero then the element is returned to the session pool.
- *
- * If the session does not have a shadow DB the element is free'ed and
- * given back to the session pool.
+ * The element is freed and given back to the session pool.
*
* External types:
*
- * Free's an external index table action record.
+ * Frees an external index table action record.
*
* NOTE:
- * Implementation of the internals of this function will be a stack with push
- * and pop.
+ * Implementation of the internals of the external table will be a stack with
+ * push and pop.
*
* Returns success or failure code.
*/
@@ -1764,9 +1769,8 @@ struct tf_set_tbl_entry_parms {
/**
* set index table entry
*
- * Used to insert an application programmed index table entry into a
- * previous allocated table location. A shadow copy of the table
- * is maintained (if enabled) (only for internal objects)
+ * Used to set an application programmed index table entry into a
+ * previous allocated table location.
*
* Returns success or failure code.
*/
diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c
index 498e668b16..25a7166bbb 100644
--- a/drivers/net/bnxt/tf_core/tf_device.c
+++ b/drivers/net/bnxt/tf_core/tf_device.c
@@ -11,10 +11,14 @@
#include "tf_rm.h"
#ifdef TF_TCAM_SHARED
#include "tf_tcam_shared.h"
+#include "tf_tbl_sram.h"
#endif /* TF_TCAM_SHARED */
struct tf;
+/* Number of slices per row for WC TCAM */
+uint16_t g_wc_num_slices_per_row = TF_WC_TCAM_1_SLICE_PER_ROW;
+
/* Forward declarations */
static int tf_dev_unbind_p4(struct tf *tfp);
static int tf_dev_unbind_p58(struct tf *tfp);
@@ -83,7 +87,8 @@ static int
tf_dev_bind_p4(struct tf *tfp,
bool shadow_copy,
struct tf_session_resources *resources,
- struct tf_dev_info *dev_handle)
+ struct tf_dev_info *dev_handle,
+ enum tf_wc_num_slice wc_num_slices)
{
int rc;
int frc;
@@ -131,7 +136,6 @@ tf_dev_bind_p4(struct tf *tfp,
if (rsv_cnt) {
tbl_cfg.num_elements = TF_TBL_TYPE_MAX;
tbl_cfg.cfg = tf_tbl_p4;
- tbl_cfg.shadow_copy = shadow_copy;
tbl_cfg.resources = resources;
rc = tf_tbl_bind(tfp, &tbl_cfg);
if (rc) {
@@ -151,6 +155,7 @@ tf_dev_bind_p4(struct tf *tfp,
tcam_cfg.cfg = tf_tcam_p4;
tcam_cfg.shadow_copy = shadow_copy;
tcam_cfg.resources = resources;
+ tcam_cfg.wc_num_slices = wc_num_slices;
#ifdef TF_TCAM_SHARED
rc = tf_tcam_shared_bind(tfp, &tcam_cfg);
#else /* !TF_TCAM_SHARED */
@@ -369,7 +374,8 @@ static int
tf_dev_bind_p58(struct tf *tfp,
bool shadow_copy,
struct tf_session_resources *resources,
- struct tf_dev_info *dev_handle)
+ struct tf_dev_info *dev_handle,
+ enum tf_wc_num_slice wc_num_slices)
{
int rc;
int frc;
@@ -414,7 +420,6 @@ tf_dev_bind_p58(struct tf *tfp,
if (rsv_cnt) {
tbl_cfg.num_elements = TF_TBL_TYPE_MAX;
tbl_cfg.cfg = tf_tbl_p58;
- tbl_cfg.shadow_copy = shadow_copy;
tbl_cfg.resources = resources;
rc = tf_tbl_bind(tfp, &tbl_cfg);
if (rc) {
@@ -423,6 +428,13 @@ tf_dev_bind_p58(struct tf *tfp,
goto fail;
}
no_rsv_flag = false;
+
+ rc = tf_tbl_sram_bind(tfp);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "SRAM table initialization failure\n");
+ goto fail;
+ }
}
rsv_cnt = tf_dev_reservation_check(TF_TCAM_TBL_TYPE_MAX,
@@ -433,6 +445,7 @@ tf_dev_bind_p58(struct tf *tfp,
tcam_cfg.cfg = tf_tcam_p58;
tcam_cfg.shadow_copy = shadow_copy;
tcam_cfg.resources = resources;
+ tcam_cfg.wc_num_slices = wc_num_slices;
#ifdef TF_TCAM_SHARED
rc = tf_tcam_shared_bind(tfp, &tcam_cfg);
#else /* !TF_TCAM_SHARED */
@@ -565,6 +578,18 @@ tf_dev_unbind_p58(struct tf *tfp)
fail = true;
}
+ /* Unbind the SRAM table prior to table as the table manager
+ * owns and frees the table DB while the SRAM table manager owns
+ * and manages it's internal data structures. SRAM table manager
+ * relies on the table rm_db to exist.
+ */
+ rc = tf_tbl_sram_unbind(tfp);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Device unbind failed, SRAM table\n");
+ fail = true;
+ }
+
rc = tf_tbl_unbind(tfp);
if (rc) {
TFP_DRV_LOG(INFO,
@@ -606,6 +631,7 @@ tf_dev_bind(struct tf *tfp __rte_unused,
enum tf_device_type type,
bool shadow_copy,
struct tf_session_resources *resources,
+ uint16_t wc_num_slices,
struct tf_dev_info *dev_handle)
{
switch (type) {
@@ -615,13 +641,15 @@ tf_dev_bind(struct tf *tfp __rte_unused,
return tf_dev_bind_p4(tfp,
shadow_copy,
resources,
- dev_handle);
+ dev_handle,
+ wc_num_slices);
case TF_DEVICE_TYPE_THOR:
dev_handle->type = type;
return tf_dev_bind_p58(tfp,
shadow_copy,
resources,
- dev_handle);
+ dev_handle,
+ wc_num_slices);
default:
TFP_DRV_LOG(ERR,
"No such device\n");
diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h
index b43cfc6925..9b0c037db0 100644
--- a/drivers/net/bnxt/tf_core/tf_device.h
+++ b/drivers/net/bnxt/tf_core/tf_device.h
@@ -57,6 +57,9 @@ struct tf_dev_info {
* [in] resources
* Pointer to resource allocation information
*
+ * [in] wc_num_slices
+ * Number of slices per row for WC
+ *
* [out] dev_handle
* Device handle
*
@@ -69,6 +72,7 @@ int tf_dev_bind(struct tf *tfp,
enum tf_device_type type,
bool shadow_copy,
struct tf_session_resources *resources,
+ uint16_t wc_num_slices,
struct tf_dev_info *dev_handle);
/**
@@ -139,6 +143,23 @@ struct tf_dev_ops {
uint16_t resource_id,
const char **resource_str);
+ /**
+ * Set the WC TCAM slice information that the device
+ * supports.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] num_slices_per_row
+ * Number of slices per row the device supports
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+ int (*tf_dev_set_tcam_slice_info)(struct tf *tfp,
+ enum tf_wc_num_slice num_slices_per_row);
+
/**
* Retrieves the WC TCAM slice information that the device
* supports.
@@ -241,6 +262,22 @@ struct tf_dev_ops {
int (*tf_dev_get_ident_resc_info)(struct tf *tfp,
struct tf_identifier_resource_info *parms);
+ /**
+ * Indicates whether the index table type is SRAM managed
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] type
+ * Truflow index table type, e.g. TF_TYPE_FULL_ACT_RECORD
+ *
+ * Returns
+ * - (0) if the table is not managed by the SRAM manager
+ * - (1) if the table is managed by the SRAM manager
+ */
+ bool (*tf_dev_is_sram_managed)(struct tf *tfp,
+ enum tf_tbl_type tbl_type);
+
/**
* Get SRAM table information.
*
@@ -289,6 +326,25 @@ struct tf_dev_ops {
int (*tf_dev_alloc_tbl)(struct tf *tfp,
struct tf_tbl_alloc_parms *parms);
+ /**
+ * Allocation of an SRAM index table type element.
+ *
+ * This API allocates the specified table type element from a
+ * device specific table type DB. The allocated element is
+ * returned.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] parms
+ * Pointer to table allocation parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+ int (*tf_dev_alloc_sram_tbl)(struct tf *tfp,
+ struct tf_tbl_alloc_parms *parms);
/**
* Allocation of a external table type element.
*
@@ -327,7 +383,24 @@ struct tf_dev_ops {
*/
int (*tf_dev_free_tbl)(struct tf *tfp,
struct tf_tbl_free_parms *parms);
-
+ /**
+ * Free of an SRAM table type element.
+ *
+ * This API free's a previous allocated table type element from a
+ * device specific table type DB.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] parms
+ * Pointer to table free parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+ int (*tf_dev_free_sram_tbl)(struct tf *tfp,
+ struct tf_tbl_free_parms *parms);
/**
* Free of a external table type element.
*
@@ -385,6 +458,25 @@ struct tf_dev_ops {
int (*tf_dev_set_ext_tbl)(struct tf *tfp,
struct tf_tbl_set_parms *parms);
+ /**
+ * Sets the specified SRAM table type element.
+ *
+ * This API sets the specified element data by invoking the
+ * firmware.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] parms
+ * Pointer to table set parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+ int (*tf_dev_set_sram_tbl)(struct tf *tfp,
+ struct tf_tbl_set_parms *parms);
+
/**
* Retrieves the specified table type element.
*
@@ -404,6 +496,25 @@ struct tf_dev_ops {
int (*tf_dev_get_tbl)(struct tf *tfp,
struct tf_tbl_get_parms *parms);
+ /**
+ * Retrieves the specified SRAM table type element.
+ *
+ * This API retrieves the specified element data by invoking the
+ * firmware.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] parms
+ * Pointer to table get parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+ int (*tf_dev_get_sram_tbl)(struct tf *tfp,
+ struct tf_tbl_get_parms *parms);
+
/**
* Retrieves the specified table type element using 'bulk'
* mechanism.
@@ -424,6 +535,26 @@ struct tf_dev_ops {
int (*tf_dev_get_bulk_tbl)(struct tf *tfp,
struct tf_tbl_get_bulk_parms *parms);
+ /**
+ * Retrieves the specified SRAM table type element using 'bulk'
+ * mechanism.
+ *
+ * This API retrieves the specified element data by invoking the
+ * firmware.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] parms
+ * Pointer to table get bulk parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+ int (*tf_dev_get_bulk_sram_tbl)(struct tf *tfp,
+ struct tf_tbl_get_bulk_parms *parms);
+
/**
* Gets the increment value to add to the shared session resource
* start offset by for each count in the "stride"
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c
index 2e7ccec123..826cd0cdbc 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.c
@@ -118,14 +118,48 @@ tf_dev_p4_get_resource_str(struct tf *tfp __rte_unused,
}
/**
- * Device specific function that retrieves the WC TCAM slices the
+ * Device specific function that set the WC TCAM slices the
* device supports.
*
* [in] tfp
* Pointer to TF handle
*
- * [out] slice_size
- * Pointer to the WC TCAM slice size
+ * [in] num_slices_per_row
+ * The WC TCAM row slice configuration
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+static int
+tf_dev_p4_set_tcam_slice_info(struct tf *tfp __rte_unused,
+ enum tf_wc_num_slice num_slices_per_row)
+{
+ switch (num_slices_per_row) {
+ case TF_WC_TCAM_1_SLICE_PER_ROW:
+ case TF_WC_TCAM_2_SLICE_PER_ROW:
+ case TF_WC_TCAM_4_SLICE_PER_ROW:
+ g_wc_num_slices_per_row = num_slices_per_row;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/**
+ * Device specific function that retrieves the TCAM slices the
+ * device supports.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] type
+ * TF TCAM type
+ *
+ * [in] key_sz
+ * The key size
*
* [out] num_slices_per_row
* Pointer to the WC TCAM row slice configuration
@@ -141,11 +175,10 @@ tf_dev_p4_get_tcam_slice_info(struct tf *tfp __rte_unused,
uint16_t *num_slices_per_row)
{
/* Single slice support */
-#define CFA_P4_WC_TCAM_SLICES_PER_ROW 1
#define CFA_P4_WC_TCAM_SLICE_SIZE 12
if (type == TF_TCAM_TBL_TYPE_WC_TCAM) {
- *num_slices_per_row = CFA_P4_WC_TCAM_SLICES_PER_ROW;
+ *num_slices_per_row = g_wc_num_slices_per_row;
if (key_sz > *num_slices_per_row * CFA_P4_WC_TCAM_SLICE_SIZE)
return -ENOTSUP;
} else { /* for other type of tcam */
@@ -220,26 +253,51 @@ static int tf_dev_p4_word_align(uint16_t size)
return ((((size) + 31) >> 5) * 4);
}
+/**
+ * Indicates whether the index table type is SRAM managed
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] type
+ * Truflow index table type, e.g. TF_TYPE_FULL_ACT_RECORD
+ *
+ * Returns
+ * - (0) if the table is not managed by the SRAM manager
+ * - (1) if the table is managed by the SRAM manager
+ */
+static bool tf_dev_p4_is_sram_managed(struct tf *tfp __rte_unused,
+ enum tf_tbl_type type __rte_unused)
+{
+ return false;
+}
/**
* Truflow P4 device specific functions
*/
const struct tf_dev_ops tf_dev_ops_p4_init = {
.tf_dev_get_max_types = tf_dev_p4_get_max_types,
.tf_dev_get_resource_str = tf_dev_p4_get_resource_str,
+ .tf_dev_set_tcam_slice_info = tf_dev_p4_set_tcam_slice_info,
.tf_dev_get_tcam_slice_info = tf_dev_p4_get_tcam_slice_info,
.tf_dev_alloc_ident = NULL,
.tf_dev_free_ident = NULL,
.tf_dev_search_ident = NULL,
.tf_dev_get_ident_resc_info = NULL,
.tf_dev_get_tbl_info = NULL,
+ .tf_dev_is_sram_managed = tf_dev_p4_is_sram_managed,
.tf_dev_alloc_ext_tbl = NULL,
.tf_dev_alloc_tbl = NULL,
+ .tf_dev_alloc_sram_tbl = NULL,
.tf_dev_free_ext_tbl = NULL,
.tf_dev_free_tbl = NULL,
+ .tf_dev_free_sram_tbl = NULL,
.tf_dev_set_tbl = NULL,
.tf_dev_set_ext_tbl = NULL,
+ .tf_dev_set_sram_tbl = NULL,
.tf_dev_get_tbl = NULL,
+ .tf_dev_get_sram_tbl = NULL,
.tf_dev_get_bulk_tbl = NULL,
+ .tf_dev_get_bulk_sram_tbl = NULL,
.tf_dev_get_shared_tbl_increment = tf_dev_p4_get_shared_tbl_increment,
.tf_dev_get_tbl_resc_info = NULL,
.tf_dev_alloc_tcam = NULL,
@@ -271,20 +329,27 @@ const struct tf_dev_ops tf_dev_ops_p4_init = {
const struct tf_dev_ops tf_dev_ops_p4 = {
.tf_dev_get_max_types = tf_dev_p4_get_max_types,
.tf_dev_get_resource_str = tf_dev_p4_get_resource_str,
+ .tf_dev_set_tcam_slice_info = tf_dev_p4_set_tcam_slice_info,
.tf_dev_get_tcam_slice_info = tf_dev_p4_get_tcam_slice_info,
.tf_dev_alloc_ident = tf_ident_alloc,
.tf_dev_free_ident = tf_ident_free,
.tf_dev_search_ident = tf_ident_search,
.tf_dev_get_ident_resc_info = tf_ident_get_resc_info,
.tf_dev_get_tbl_info = NULL,
+ .tf_dev_is_sram_managed = tf_dev_p4_is_sram_managed,
.tf_dev_alloc_tbl = tf_tbl_alloc,
.tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc,
+ .tf_dev_alloc_sram_tbl = tf_tbl_alloc,
.tf_dev_free_tbl = tf_tbl_free,
.tf_dev_free_ext_tbl = tf_tbl_ext_free,
+ .tf_dev_free_sram_tbl = tf_tbl_free,
.tf_dev_set_tbl = tf_tbl_set,
.tf_dev_set_ext_tbl = tf_tbl_ext_common_set,
+ .tf_dev_set_sram_tbl = NULL,
.tf_dev_get_tbl = tf_tbl_get,
+ .tf_dev_get_sram_tbl = NULL,
.tf_dev_get_bulk_tbl = tf_tbl_bulk_get,
+ .tf_dev_get_bulk_sram_tbl = NULL,
.tf_dev_get_shared_tbl_increment = tf_dev_p4_get_shared_tbl_increment,
.tf_dev_get_tbl_resc_info = tf_tbl_get_resc_info,
#ifdef TF_TCAM_SHARED
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h
index a73ba3cd70..c1357913f1 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.h
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.h
@@ -15,101 +15,101 @@
struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = {
[TF_IDENT_TYPE_L2_CTXT_HIGH] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_L2_CTXT_LOW] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_PROF_FUNC] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_FUNC,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_WC_PROF] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_EM_PROF] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_EM_PROF_ID,
- 0, 0, 0
+ 0, 0
},
};
struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = {
[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_PROF_TCAM] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_TCAM,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_WC_TCAM] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_SP_TCAM] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_TCAM,
- 0, 0, 0
+ 0, 0
},
};
struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = {
[TF_TBL_TYPE_FULL_ACT_RECORD] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_MCAST_GROUPS] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_ENCAP_8B] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_ENCAP_16B] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_ENCAP_64B] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_SP_SMAC] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_STATS_64] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_MODIFY_IPV4] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_METER_PROF] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_METER_INST] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_MIRROR_CONFIG] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR,
- 0, 0, 0
+ 0, 0
},
};
@@ -117,14 +117,14 @@ struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = {
struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = {
[TF_EM_TBL_TYPE_TBL_SCOPE] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_TBL_SCOPE,
- 0, 0, 0
+ 0, 0
},
};
struct tf_rm_element_cfg tf_em_int_p4[TF_EM_TBL_TYPE_MAX] = {
[TF_EM_TBL_TYPE_EM_RECORD] = {
TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_EM_REC,
- 0, 0, 0
+ 0, 0
},
};
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c
index a492c62bff..47d7836a58 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.c
@@ -17,6 +17,7 @@
#include "tf_if_tbl.h"
#include "tfp.h"
#include "tf_msg_common.h"
+#include "tf_tbl_sram.h"
#define TF_DEV_P58_PARIF_MAX 16
#define TF_DEV_P58_PF_MASK 0xfUL
@@ -105,14 +106,48 @@ tf_dev_p58_get_resource_str(struct tf *tfp __rte_unused,
}
/**
- * Device specific function that retrieves the WC TCAM slices the
+ * Device specific function that set the WC TCAM slices the
* device supports.
*
* [in] tfp
* Pointer to TF handle
*
- * [out] slice_size
- * Pointer to the WC TCAM slice size
+ * [in] num_slices_per_row
+ * The WC TCAM row slice configuration
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+static int
+tf_dev_p58_set_tcam_slice_info(struct tf *tfp __rte_unused,
+ enum tf_wc_num_slice num_slices_per_row)
+{
+ switch (num_slices_per_row) {
+ case TF_WC_TCAM_1_SLICE_PER_ROW:
+ case TF_WC_TCAM_2_SLICE_PER_ROW:
+ case TF_WC_TCAM_4_SLICE_PER_ROW:
+ g_wc_num_slices_per_row = num_slices_per_row;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/**
+ * Device specific function that retrieves the TCAM slices the
+ * device supports.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] type
+ * TF TCAM type
+ *
+ * [in] key_sz
+ * The key size
*
* [out] num_slices_per_row
* Pointer to the WC TCAM row slice configuration
@@ -123,16 +158,13 @@ tf_dev_p58_get_resource_str(struct tf *tfp __rte_unused,
*/
static int
tf_dev_p58_get_tcam_slice_info(struct tf *tfp __rte_unused,
- enum tf_tcam_tbl_type type,
- uint16_t key_sz,
- uint16_t *num_slices_per_row)
+ enum tf_tcam_tbl_type type,
+ uint16_t key_sz,
+ uint16_t *num_slices_per_row)
{
-#define CFA_P58_WC_TCAM_SLICES_PER_ROW 1
#define CFA_P58_WC_TCAM_SLICE_SIZE 24
-
if (type == TF_TCAM_TBL_TYPE_WC_TCAM) {
- /* only support single slice key size now */
- *num_slices_per_row = CFA_P58_WC_TCAM_SLICES_PER_ROW;
+ *num_slices_per_row = g_wc_num_slices_per_row;
if (key_sz > *num_slices_per_row * CFA_P58_WC_TCAM_SLICE_SIZE)
return -ENOTSUP;
} else { /* for other type of tcam */
@@ -194,6 +226,44 @@ static int tf_dev_p58_get_shared_tbl_increment(struct tf *tfp __rte_unused,
return 0;
}
+/**
+ * Indicates whether the index table type is SRAM managed
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] type
+ * Truflow index table type, e.g. TF_TYPE_FULL_ACT_RECORD
+ *
+ * Returns
+ * - (0) if the table is not managed by the SRAM manager
+ * - (1) if the table is managed by the SRAM manager
+ */
+static bool tf_dev_p58_is_sram_managed(struct tf *tfp __rte_unused,
+ enum tf_tbl_type type)
+{
+ switch (type) {
+ case TF_TBL_TYPE_FULL_ACT_RECORD:
+ case TF_TBL_TYPE_COMPACT_ACT_RECORD:
+ case TF_TBL_TYPE_ACT_ENCAP_8B:
+ case TF_TBL_TYPE_ACT_ENCAP_16B:
+ case TF_TBL_TYPE_ACT_ENCAP_32B:
+ case TF_TBL_TYPE_ACT_ENCAP_64B:
+ case TF_TBL_TYPE_ACT_SP_SMAC:
+ case TF_TBL_TYPE_ACT_SP_SMAC_IPV4:
+ case TF_TBL_TYPE_ACT_SP_SMAC_IPV6:
+ case TF_TBL_TYPE_ACT_STATS_64:
+ case TF_TBL_TYPE_ACT_MODIFY_IPV4:
+ case TF_TBL_TYPE_ACT_MODIFY_8B:
+ case TF_TBL_TYPE_ACT_MODIFY_16B:
+ case TF_TBL_TYPE_ACT_MODIFY_32B:
+ case TF_TBL_TYPE_ACT_MODIFY_64B:
+ return true;
+ default:
+ return false;
+ }
+}
+
#define TF_DEV_P58_BANK_SZ_64B 2048
/**
* Get SRAM table information.
@@ -265,26 +335,34 @@ static int tf_dev_p58_get_sram_tbl_info(struct tf *tfp __rte_unused,
}
return 0;
}
+
/**
* Truflow P58 device specific functions
*/
const struct tf_dev_ops tf_dev_ops_p58_init = {
.tf_dev_get_max_types = tf_dev_p58_get_max_types,
.tf_dev_get_resource_str = tf_dev_p58_get_resource_str,
+ .tf_dev_set_tcam_slice_info = tf_dev_p58_set_tcam_slice_info,
.tf_dev_get_tcam_slice_info = tf_dev_p58_get_tcam_slice_info,
.tf_dev_alloc_ident = NULL,
.tf_dev_free_ident = NULL,
.tf_dev_search_ident = NULL,
.tf_dev_get_ident_resc_info = NULL,
.tf_dev_get_tbl_info = NULL,
+ .tf_dev_is_sram_managed = tf_dev_p58_is_sram_managed,
.tf_dev_alloc_ext_tbl = NULL,
.tf_dev_alloc_tbl = NULL,
+ .tf_dev_alloc_sram_tbl = NULL,
.tf_dev_free_ext_tbl = NULL,
.tf_dev_free_tbl = NULL,
+ .tf_dev_free_sram_tbl = NULL,
.tf_dev_set_tbl = NULL,
.tf_dev_set_ext_tbl = NULL,
+ .tf_dev_set_sram_tbl = NULL,
.tf_dev_get_tbl = NULL,
+ .tf_dev_get_sram_tbl = NULL,
.tf_dev_get_bulk_tbl = NULL,
+ .tf_dev_get_bulk_sram_tbl = NULL,
.tf_dev_get_shared_tbl_increment = tf_dev_p58_get_shared_tbl_increment,
.tf_dev_get_tbl_resc_info = NULL,
.tf_dev_alloc_tcam = NULL,
@@ -316,20 +394,27 @@ const struct tf_dev_ops tf_dev_ops_p58_init = {
const struct tf_dev_ops tf_dev_ops_p58 = {
.tf_dev_get_max_types = tf_dev_p58_get_max_types,
.tf_dev_get_resource_str = tf_dev_p58_get_resource_str,
+ .tf_dev_set_tcam_slice_info = tf_dev_p58_set_tcam_slice_info,
.tf_dev_get_tcam_slice_info = tf_dev_p58_get_tcam_slice_info,
.tf_dev_alloc_ident = tf_ident_alloc,
.tf_dev_free_ident = tf_ident_free,
.tf_dev_search_ident = tf_ident_search,
.tf_dev_get_ident_resc_info = tf_ident_get_resc_info,
+ .tf_dev_is_sram_managed = tf_dev_p58_is_sram_managed,
.tf_dev_get_tbl_info = tf_dev_p58_get_sram_tbl_info,
.tf_dev_alloc_tbl = tf_tbl_alloc,
+ .tf_dev_alloc_sram_tbl = tf_tbl_sram_alloc,
.tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc,
.tf_dev_free_tbl = tf_tbl_free,
.tf_dev_free_ext_tbl = tf_tbl_ext_free,
+ .tf_dev_free_sram_tbl = tf_tbl_sram_free,
.tf_dev_set_tbl = tf_tbl_set,
.tf_dev_set_ext_tbl = tf_tbl_ext_common_set,
+ .tf_dev_set_sram_tbl = tf_tbl_sram_set,
.tf_dev_get_tbl = tf_tbl_get,
+ .tf_dev_get_sram_tbl = tf_tbl_sram_get,
.tf_dev_get_bulk_tbl = tf_tbl_bulk_get,
+ .tf_dev_get_bulk_sram_tbl = tf_tbl_sram_bulk_get,
.tf_dev_get_shared_tbl_increment = tf_dev_p58_get_shared_tbl_increment,
.tf_dev_get_tbl_resc_info = tf_tbl_get_resc_info,
#ifdef TF_TCAM_SHARED
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h
index 8c2e07aa34..3e8759f2df 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.h
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.h
@@ -15,107 +15,107 @@
struct tf_rm_element_cfg tf_ident_p58[TF_IDENT_TYPE_MAX] = {
[TF_IDENT_TYPE_L2_CTXT_HIGH] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_L2_CTXT_LOW] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_PROF_FUNC] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_PROF_FUNC,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_WC_PROF] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_EM_PROF] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_PROF_ID,
- 0, 0, 0
+ 0, 0
},
};
struct tf_rm_element_cfg tf_tcam_p58[TF_TCAM_TBL_TYPE_MAX] = {
[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_PROF_TCAM] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_PROF_TCAM,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_WC_TCAM] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_TCAM,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_VEB_TCAM] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_VEB_TCAM,
- 0, 0, 0
+ 0, 0
},
};
struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = {
[TF_TBL_TYPE_EM_FKB] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_WC_FKB] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_METER_PROF] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_METER_INST] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_METER_DROP_CNT] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_MIRROR_CONFIG] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_METADATA] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA,
- 0, 0, 0
+ 0, 0
},
/* Policy - ARs in bank 1 */
[TF_TBL_TYPE_FULL_ACT_RECORD] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
- .slices = 1,
+ .slices = 4,
},
[TF_TBL_TYPE_COMPACT_ACT_RECORD] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
- .slices = 1,
+ .slices = 8,
},
/* Policy - Encaps in bank 2 */
[TF_TBL_TYPE_ACT_ENCAP_8B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 1,
+ .slices = 8,
},
[TF_TBL_TYPE_ACT_ENCAP_16B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 1,
+ .slices = 4,
},
[TF_TBL_TYPE_ACT_ENCAP_32B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 1,
+ .slices = 2,
},
[TF_TBL_TYPE_ACT_ENCAP_64B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
@@ -128,19 +128,19 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 1,
+ .slices = 8,
},
[TF_TBL_TYPE_ACT_MODIFY_16B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 1,
+ .slices = 4,
},
[TF_TBL_TYPE_ACT_MODIFY_32B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 1,
+ .slices = 2,
},
[TF_TBL_TYPE_ACT_MODIFY_64B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
@@ -152,32 +152,32 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = {
[TF_TBL_TYPE_ACT_SP_SMAC] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
- .slices = 1,
+ .slices = 8,
},
[TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
- .slices = 1,
+ .slices = 4,
},
[TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
- .slices = 1,
+ .slices = 2,
},
/* Policy - Stats in bank 3 */
[TF_TBL_TYPE_ACT_STATS_64] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3,
- .slices = 1,
+ .slices = 8,
},
};
struct tf_rm_element_cfg tf_em_int_p58[TF_EM_TBL_TYPE_MAX] = {
[TF_EM_TBL_TYPE_EM_RECORD] = {
TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P58_EM_REC,
- 0, 0, 0
+ 0, 0
},
};
diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c
index e07d9168be..0fbb2fe837 100644
--- a/drivers/net/bnxt/tf_core/tf_msg.c
+++ b/drivers/net/bnxt/tf_core/tf_msg.c
@@ -2231,7 +2231,7 @@ tf_msg_get_if_tbl_entry(struct tf *tfp,
if (rc != 0)
return rc;
- tfp_memcpy(params->data, resp.data, req.size);
+ tfp_memcpy(¶ms->data[0], resp.data, req.size);
return 0;
}
diff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c
index 0a46e2a343..03c958a7d6 100644
--- a/drivers/net/bnxt/tf_core/tf_rm.c
+++ b/drivers/net/bnxt/tf_core/tf_rm.c
@@ -34,6 +34,12 @@ struct tf_rm_element {
*/
uint16_t hcapi_type;
+ /**
+ * Resource slices. How many slices will fit in the
+ * resource pool chunk size.
+ */
+ uint8_t slices;
+
/**
* HCAPI RM allocated range information for the element.
*/
@@ -356,12 +362,15 @@ tf_rm_check_residuals(struct tf_rm_new_db *rm_db,
* - - Failure if negative
*/
static int
-tf_rm_update_parent_reservations(struct tf_rm_element_cfg *cfg,
+tf_rm_update_parent_reservations(struct tf *tfp,
+ struct tf_dev_info *dev,
+ struct tf_rm_element_cfg *cfg,
uint16_t *alloc_cnt,
uint16_t num_elements,
uint16_t *req_cnt)
{
int parent, child;
+ const char *type_str;
/* Search through all the elements */
for (parent = 0; parent < num_elements; parent++) {
@@ -377,15 +386,25 @@ tf_rm_update_parent_reservations(struct tf_rm_element_cfg *cfg,
if (alloc_cnt[parent] % cfg[parent].slices)
combined_cnt++;
+ if (alloc_cnt[parent]) {
+ dev->ops->tf_dev_get_resource_str(tfp,
+ cfg[parent].hcapi_type,
+ &type_str);
+ }
+
/* Search again through all the elements */
for (child = 0; child < num_elements; child++) {
/* If this is one of my children */
if (cfg[child].cfg_type ==
TF_RM_ELEM_CFG_HCAPI_BA_CHILD &&
- cfg[child].parent_subtype == parent) {
+ cfg[child].parent_subtype == parent &&
+ alloc_cnt[child]) {
uint16_t cnt = 0;
RTE_ASSERT(cfg[child].slices);
+ dev->ops->tf_dev_get_resource_str(tfp,
+ cfg[child].hcapi_type,
+ &type_str);
/* Increment the parents combined count
* with each child's count adjusted for
* number of slices per RM allocated item.
@@ -479,7 +498,7 @@ tf_rm_create_db(struct tf *tfp,
/* Update the req_cnt based upon the element configuration
*/
- tf_rm_update_parent_reservations(parms->cfg,
+ tf_rm_update_parent_reservations(tfp, dev, parms->cfg,
parms->alloc_cnt,
parms->num_elements,
req_cnt);
@@ -594,6 +613,7 @@ tf_rm_create_db(struct tf *tfp,
db[i].cfg_type = cfg->cfg_type;
db[i].hcapi_type = cfg->hcapi_type;
+ db[i].slices = cfg->slices;
/* Save the parent subtype for later use to find the pool
*/
@@ -1271,6 +1291,26 @@ tf_rm_get_hcapi_type(struct tf_rm_get_hcapi_parms *parms)
return 0;
}
+int
+tf_rm_get_slices(struct tf_rm_get_slices_parms *parms)
+{
+ struct tf_rm_new_db *rm_db;
+ enum tf_rm_elem_cfg_type cfg_type;
+
+ TF_CHECK_PARMS2(parms, parms->rm_db);
+ rm_db = (struct tf_rm_new_db *)parms->rm_db;
+ TF_CHECK_PARMS1(rm_db->db);
+
+ cfg_type = rm_db->db[parms->subtype].cfg_type;
+
+ /* Bail out if not controlled by HCAPI */
+ if (cfg_type == TF_RM_ELEM_CFG_NULL)
+ return -ENOTSUP;
+
+ *parms->slices = rm_db->db[parms->subtype].slices;
+
+ return 0;
+}
int
tf_rm_get_inuse_count(struct tf_rm_get_inuse_count_parms *parms)
diff --git a/drivers/net/bnxt/tf_core/tf_rm.h b/drivers/net/bnxt/tf_core/tf_rm.h
index 8b984112e8..da7d0c7211 100644
--- a/drivers/net/bnxt/tf_core/tf_rm.h
+++ b/drivers/net/bnxt/tf_core/tf_rm.h
@@ -43,16 +43,6 @@ struct tf;
* support module, not called directly.
*/
-/**
- * Resource reservation single entry result. Used when accessing HCAPI
- * RM on the firmware.
- */
-struct tf_rm_new_entry {
- /** Starting index of the allocated resource */
- uint16_t start;
- /** Number of allocated elements */
- uint16_t stride;
-};
/**
* RM Element configuration enumeration. Used by the Device to
@@ -114,10 +104,6 @@ struct tf_rm_element_cfg {
*/
enum tf_rm_elem_cfg_type cfg_type;
- /* If a HCAPI to TF type conversion is required then TF type
- * can be added here.
- */
-
/**
* HCAPI RM Type for the element. Used for TF to HCAPI type
* conversion.
@@ -125,28 +111,19 @@ struct tf_rm_element_cfg {
uint16_t hcapi_type;
/**
- * if cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_CHILD
+ * if cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_CHILD/PARENT
*
* Parent Truflow module subtype associated with this resource type.
*/
uint16_t parent_subtype;
/**
- * if cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_CHILD
+ * if cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_CHILD/PARENT
*
* Resource slices. How many slices will fit in the
* resource pool chunk size.
*/
uint8_t slices;
-
- /**
- * Pool element divider count
- * If 0 or 1, there is 1:1 correspondence between the RM
- * BA pool resource element and the HCAPI RM firmware
- * resource. If > 1, the RM BA pool element has a 1:n
- * correspondence to the HCAPI RM firmware resource.
- */
- uint8_t divider;
};
/**
@@ -160,7 +137,7 @@ struct tf_rm_alloc_info {
* In case of dynamic allocation support this would have
* to be changed to linked list of tf_rm_entry instead.
*/
- struct tf_rm_new_entry entry;
+ struct tf_resource_info entry;
};
/**
@@ -331,6 +308,25 @@ struct tf_rm_get_hcapi_parms {
*/
uint16_t *hcapi_type;
};
+/**
+ * Get Slices parameters for a single element
+ */
+struct tf_rm_get_slices_parms {
+ /**
+ * [in] RM DB Handle
+ */
+ void *rm_db;
+ /**
+ * [in] TF subtype indicates which DB entry to perform the
+ * action on. (e.g. TF_TBL_TYPE_FULL_ACTION subtype of module
+ * TF_MODULE_TYPE_TABLE)
+ */
+ uint16_t subtype;
+ /**
+ * [in/out] Pointer to number of slices for the given type
+ */
+ uint16_t *slices;
+};
/**
* Get InUse count parameters for single element
@@ -394,6 +390,8 @@ struct tf_rm_check_indexes_in_range_parms {
* @ref tf_rm_get_hcapi_type
*
* @ref tf_rm_get_inuse_count
+ *
+ * @ref tf_rm_get_slice_size
*/
/**
@@ -571,5 +569,17 @@ int tf_rm_get_inuse_count(struct tf_rm_get_inuse_count_parms *parms);
int
tf_rm_check_indexes_in_range(struct tf_rm_check_indexes_in_range_parms *parms);
+/**
+ * Get the number of slices per resource bit allocator for the resource type
+ *
+ * [in] parms
+ * Pointer to get inuse parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int
+tf_rm_get_slices(struct tf_rm_get_slices_parms *parms);
#endif /* TF_RM_NEW_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_session.c b/drivers/net/bnxt/tf_core/tf_session.c
index 90b65c59e6..3e6664e9f2 100644
--- a/drivers/net/bnxt/tf_core/tf_session.c
+++ b/drivers/net/bnxt/tf_core/tf_session.c
@@ -202,6 +202,7 @@ tf_session_create(struct tf *tfp,
parms->open_cfg->device_type,
session->shadow_copy,
&parms->open_cfg->resources,
+ parms->open_cfg->wc_num_slices,
&session->dev);
/* Logging handled by dev_bind */
@@ -705,6 +706,22 @@ tf_session_get_session(struct tf *tfp,
return rc;
}
+int tf_session_get(struct tf *tfp,
+ struct tf_session **tfs,
+ struct tf_dev_info **tfd)
+{
+ int rc;
+ rc = tf_session_get_session_internal(tfp, tfs);
+
+ /* Logging done by tf_session_get_session_internal */
+ if (rc)
+ return rc;
+
+ rc = tf_session_get_device(*tfs, tfd);
+
+ return rc;
+}
+
struct tf_session_client *
tf_session_get_session_client(struct tf_session *tfs,
union tf_session_client_id session_client_id)
@@ -1012,4 +1029,43 @@ tf_session_set_tcam_shared_db(struct tf *tfp,
tfs->tcam_shared_db_handle = tcam_shared_db_handle;
return rc;
}
+
+int
+tf_session_get_sram_db(struct tf *tfp,
+ void **sram_handle)
+{
+ struct tf_session *tfs = NULL;
+ int rc = 0;
+
+ *sram_handle = NULL;
+
+ if (tfp == NULL)
+ return (-EINVAL);
+
+ rc = tf_session_get_session_internal(tfp, &tfs);
+ if (rc)
+ return rc;
+
+ *sram_handle = tfs->sram_handle;
+ return rc;
+}
+
+int
+tf_session_set_sram_db(struct tf *tfp,
+ void *sram_handle)
+{
+ struct tf_session *tfs = NULL;
+ int rc = 0;
+
+ if (tfp == NULL)
+ return (-EINVAL);
+
+ rc = tf_session_get_session_internal(tfp, &tfs);
+ if (rc)
+ return rc;
+
+ tfs->sram_handle = sram_handle;
+ return rc;
+}
+
#endif /* TF_TCAM_SHARED */
diff --git a/drivers/net/bnxt/tf_core/tf_session.h b/drivers/net/bnxt/tf_core/tf_session.h
index d68421cd13..c1d7f70060 100644
--- a/drivers/net/bnxt/tf_core/tf_session.h
+++ b/drivers/net/bnxt/tf_core/tf_session.h
@@ -166,6 +166,10 @@ struct tf_session {
*/
void *tcam_shared_db_handle;
#endif /* TF_TCAM_SHARED */
+ /**
+ * SRAM db reference for the session
+ */
+ void *sram_handle;
};
/**
@@ -278,6 +282,10 @@ struct tf_session_close_session_parms {
*
* @ref tf_session_set_tcam_shared_db
* #endif
+ *
+ * @ref tf_session_get_sram_db
+ *
+ * @ref tf_session_set_sram_db
*/
/**
@@ -435,11 +443,11 @@ tf_session_find_session_client_by_fid(struct tf_session *tfs,
/**
* Looks up the device information from the TF Session.
*
- * [in] tfp
- * Pointer to TF handle
+ * [in] tfs
+ * Pointer to session handle
*
* [out] tfd
- * Pointer pointer to the device
+ * Pointer to the device
*
* Returns
* - (0) if successful.
@@ -448,6 +456,26 @@ tf_session_find_session_client_by_fid(struct tf_session *tfs,
int tf_session_get_device(struct tf_session *tfs,
struct tf_dev_info **tfd);
+/**
+ * Returns the session and the device from the tfp.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [out] tfs
+ * Pointer to the session
+ *
+ * [out] tfd
+ * Pointer to the device
+
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_session_get(struct tf *tfp,
+ struct tf_session **tfs,
+ struct tf_dev_info **tfd);
+
/**
* Looks up the FW Session id the requested TF handle.
*
@@ -614,4 +642,28 @@ int
tf_session_get_tcam_shared_db(struct tf *tfp,
void **tcam_shared_db_handle);
+/**
+ * Set the pointer to the SRAM database
+ *
+ * [in] session, pointer to the session
+ *
+ * Returns:
+ * - the pointer to the parent bnxt struct
+ */
+int
+tf_session_set_sram_db(struct tf *tfp,
+ void *sram_handle);
+
+/**
+ * Get the pointer to the SRAM database
+ *
+ * [in] session, pointer to the session
+ *
+ * Returns:
+ * - the pointer to the parent bnxt struct
+ */
+int
+tf_session_get_sram_db(struct tf *tfp,
+ void **sram_handle);
+
#endif /* _TF_SESSION_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_sram_mgr.c b/drivers/net/bnxt/tf_core/tf_sram_mgr.c
new file mode 100644
index 0000000000..f633a78b25
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/tf_sram_mgr.c
@@ -0,0 +1,971 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019-2021 Broadcom
+ * All rights reserved.
+ */
+#include <stdlib.h>
+#include <stdio.h>
+#include "tf_sram_mgr.h"
+#include "tf_core.h"
+#include "tf_rm.h"
+#include "tf_common.h"
+#include "assert.h"
+#include "tf_util.h"
+#include "tfp.h"
+#if (STATS_CLEAR_ON_READ_SUPPORT == 0)
+#include "tf_msg.h"
+#endif
+/***************************
+ * Internal Data Structures
+ ***************************/
+
+/**
+ * TF SRAM block info
+ *
+ * Contains all the information about a particular 64B SRAM
+ * block and the slices within it.
+ */
+struct tf_sram_block {
+ /* Previous block
+ */
+ struct tf_sram_block *prev;
+ /* Next block
+ */
+ struct tf_sram_block *next;
+
+ /** Bitmap indicating which slices are in use
+ * If a bit is set, it indicates the slice
+ * in the row is in use.
+ */
+ uint8_t in_use_mask;
+
+ /** Block id - this is a 64B offset
+ */
+ uint16_t block_id;
+};
+
+/**
+ * TF SRAM block list
+ *
+ * List of 64B SRAM blocks used for fixed size slices (8, 16, 32, 64B)
+ */
+struct tf_sram_slice_list {
+ /** Pointer to head of linked list of blocks.
+ */
+ struct tf_sram_block *head;
+
+ /** Pointer to tail of linked list of blocks.
+ */
+ struct tf_sram_block *tail;
+
+ /** Total count of blocks
+ */
+ uint32_t cnt;
+
+ /** First non-full block in the list
+ */
+ struct tf_sram_block *first_not_full_block;
+
+ /** Entry slice size for this list
+ */
+ enum tf_sram_slice_size size;
+};
+
+
+/**
+ * TF SRAM bank info consists of lists of different slice sizes per bank
+ */
+struct tf_sram_bank_info {
+ struct tf_sram_slice_list slice[TF_SRAM_SLICE_SIZE_MAX];
+};
+
+/**
+ * SRAM banks consist of SRAM bank information
+ */
+struct tf_sram_bank {
+ struct tf_sram_bank_info bank[TF_SRAM_BANK_ID_MAX];
+};
+
+/**
+ * SRAM banks consist of SRAM bank information
+ */
+struct tf_sram {
+ struct tf_sram_bank dir[TF_DIR_MAX];
+};
+
+/**********************
+ * Internal functions
+ **********************/
+
+/**
+ * Get slice size in string format
+ */
+const char
+*tf_sram_slice_2_str(enum tf_sram_slice_size slice_size)
+{
+ switch (slice_size) {
+ case TF_SRAM_SLICE_SIZE_8B:
+ return "8B slice";
+ case TF_SRAM_SLICE_SIZE_16B:
+ return "16B slice";
+ case TF_SRAM_SLICE_SIZE_32B:
+ return "32B slice";
+ case TF_SRAM_SLICE_SIZE_64B:
+ return "64B slice";
+ default:
+ return "Invalid slice size";
+ }
+}
+
+/**
+ * Get bank in string format
+ */
+const char
+*tf_sram_bank_2_str(enum tf_sram_bank_id bank_id)
+{
+ switch (bank_id) {
+ case TF_SRAM_BANK_ID_0:
+ return "bank_0";
+ case TF_SRAM_BANK_ID_1:
+ return "bank_1";
+ case TF_SRAM_BANK_ID_2:
+ return "bank_2";
+ case TF_SRAM_BANK_ID_3:
+ return "bank_3";
+ default:
+ return "Invalid bank_id";
+ }
+}
+
+/**
+ * TF SRAM get slice list
+ */
+static int
+tf_sram_get_slice_list(struct tf_sram *sram,
+ struct tf_sram_slice_list **slice_list,
+ enum tf_sram_slice_size slice_size,
+ enum tf_dir dir,
+ enum tf_sram_bank_id bank_id)
+{
+ int rc = 0;
+
+ TF_CHECK_PARMS2(sram, slice_list);
+
+ *slice_list = &sram->dir[dir].bank[bank_id].slice[slice_size];
+
+ return rc;
+}
+
+uint16_t tf_sram_bank_2_base_offset[TF_SRAM_BANK_ID_MAX] = {
+ 0,
+ 2048,
+ 4096,
+ 6144
+};
+
+/**
+ * Translate a block id and bank_id to an 8B offset
+ */
+static void
+tf_sram_block_id_2_offset(enum tf_sram_bank_id bank_id, uint16_t block_id,
+ uint16_t *offset)
+{
+ *offset = (block_id + tf_sram_bank_2_base_offset[bank_id]) << 3;
+}
+
+/**
+ * Translates an 8B offset and bank_id to a block_id
+ */
+static void
+tf_sram_offset_2_block_id(enum tf_sram_bank_id bank_id, uint16_t offset,
+ uint16_t *block_id, uint16_t *slice_offset)
+{
+ *slice_offset = offset & 0x7;
+ *block_id = ((offset & ~0x7) >> 3) -
+ tf_sram_bank_2_base_offset[bank_id];
+}
+
+/**
+ * Find a matching block_id within the slice list
+ */
+static struct tf_sram_block
+*tf_sram_find_block(uint16_t block_id, struct tf_sram_slice_list *slice_list)
+{
+ uint32_t cnt;
+ struct tf_sram_block *block;
+
+ cnt = slice_list->cnt;
+ block = slice_list->head;
+
+ while (cnt > 0 && block) {
+ if (block->block_id == block_id)
+ return block;
+ block = block->next;
+ cnt--;
+ }
+ return NULL;
+}
+
+/**
+ * Given the current block get the next block within the slice list
+ *
+ * List is not changed.
+ */
+static struct tf_sram_block
+*tf_sram_get_next_block(struct tf_sram_block *block)
+{
+ struct tf_sram_block *nblock;
+
+ if (block != NULL)
+ nblock = block->next;
+ else
+ nblock = NULL;
+ return nblock;
+}
+
+/**
+ * Free an allocated slice from a block and if the block is empty,
+ * return an indication so that the block can be freed.
+ */
+static int
+tf_sram_free_slice(enum tf_sram_slice_size slice_size,
+ uint16_t slice_offset, struct tf_sram_block *block,
+ bool *block_is_empty)
+{
+ int rc = 0;
+ uint8_t shift;
+ uint8_t slice_mask = 0;
+
+ TF_CHECK_PARMS2(block, block_is_empty);
+
+ switch (slice_size) {
+ case TF_SRAM_SLICE_SIZE_8B:
+ shift = slice_offset >> 0;
+ assert(shift < 8);
+ slice_mask = 1 << shift;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_16B:
+ shift = slice_offset >> 1;
+ assert(shift < 4);
+ slice_mask = 1 << shift;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_32B:
+ shift = slice_offset >> 2;
+ assert(shift < 2);
+ slice_mask = 1 << shift;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_64B:
+ default:
+ shift = slice_offset >> 0;
+ assert(shift < 1);
+ slice_mask = 1 << shift;
+ break;
+ }
+
+ if ((block->in_use_mask & slice_mask) == 0) {
+ rc = -EINVAL;
+ TFP_DRV_LOG(ERR, "block_id(0x%x) slice(%d) was not allocated\n",
+ block->block_id, slice_offset);
+ return rc;
+ }
+
+ block->in_use_mask &= ~slice_mask;
+
+ if (block->in_use_mask == 0)
+ *block_is_empty = true;
+ else
+ *block_is_empty = false;
+
+ return rc;
+}
+
+/**
+ * TF SRAM get next slice
+ *
+ * Gets the next slice_offset available in the block
+ * and updates the in_use_mask.
+ */
+static int
+tf_sram_get_next_slice_in_block(struct tf_sram_block *block,
+ enum tf_sram_slice_size slice_size,
+ uint16_t *slice_offset,
+ bool *block_is_full)
+{
+ int rc, free_id = -1;
+ uint8_t shift, max_slices, mask, i, full_mask;
+
+ TF_CHECK_PARMS3(block, slice_offset, block_is_full);
+
+ switch (slice_size) {
+ case TF_SRAM_SLICE_SIZE_8B:
+ shift = 0;
+ max_slices = 8;
+ full_mask = 0xff;
+ break;
+ case TF_SRAM_SLICE_SIZE_16B:
+ shift = 1;
+ max_slices = 4;
+ full_mask = 0xf;
+ break;
+ case TF_SRAM_SLICE_SIZE_32B:
+ shift = 2;
+ max_slices = 2;
+ full_mask = 0x3;
+ break;
+ case TF_SRAM_SLICE_SIZE_64B:
+ default:
+ shift = 0;
+ max_slices = 1;
+ full_mask = 1;
+ break;
+ }
+
+ mask = block->in_use_mask;
+
+ for (i = 0; i < max_slices; i++) {
+ if ((mask & 1) == 0) {
+ free_id = i;
+ block->in_use_mask |= 1 << free_id;
+ break;
+ }
+ mask = mask >> 1;
+ }
+
+ if (block->in_use_mask == full_mask)
+ *block_is_full = true;
+ else
+ *block_is_full = false;
+
+
+ if (free_id >= 0) {
+ *slice_offset = free_id << shift;
+ rc = 0;
+ } else {
+ *slice_offset = 0;
+ rc = -ENOMEM;
+ }
+
+ return rc;
+}
+
+/**
+ * TF SRAM get indication as to whether the slice offset is
+ * allocated in the block.
+ *
+ */
+static int
+tf_sram_is_slice_allocated_in_block(struct tf_sram_block *block,
+ enum tf_sram_slice_size slice_size,
+ uint16_t slice_offset,
+ bool *is_allocated)
+{
+ int rc = 0;
+ uint8_t shift;
+ uint8_t slice_mask = 0;
+
+ TF_CHECK_PARMS2(block, is_allocated);
+
+ *is_allocated = false;
+
+ switch (slice_size) {
+ case TF_SRAM_SLICE_SIZE_8B:
+ shift = slice_offset >> 0;
+ assert(shift < 8);
+ slice_mask = 1 << shift;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_16B:
+ shift = slice_offset >> 1;
+ assert(shift < 4);
+ slice_mask = 1 << shift;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_32B:
+ shift = slice_offset >> 2;
+ assert(shift < 2);
+ slice_mask = 1 << shift;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_64B:
+ default:
+ shift = slice_offset >> 0;
+ assert(shift < 1);
+ slice_mask = 1 << shift;
+ break;
+ }
+
+ if ((block->in_use_mask & slice_mask) == 0) {
+ TFP_DRV_LOG(ERR, "block_id(0x%x) slice(%d) was not allocated\n",
+ block->block_id, slice_offset);
+ *is_allocated = false;
+ } else {
+ *is_allocated = true;
+ }
+
+ return rc;
+}
+
+/**
+ * Initialize slice list
+ */
+static void
+tf_sram_init_slice_list(struct tf_sram_slice_list *slice_list,
+ enum tf_sram_slice_size slice_size)
+{
+ slice_list->head = NULL;
+ slice_list->tail = NULL;
+ slice_list->cnt = 0;
+ slice_list->size = slice_size;
+}
+
+/**
+ * Get the block count
+ */
+static uint32_t
+tf_sram_get_block_cnt(struct tf_sram_slice_list *slice_list)
+{
+ return slice_list->cnt;
+}
+
+
+/**
+ * Free a block data structure - does not free to the RM
+ */
+static void
+tf_sram_free_block(struct tf_sram_slice_list *slice_list,
+ struct tf_sram_block *block)
+{
+ if (slice_list->head == block && slice_list->tail == block) {
+ slice_list->head = NULL;
+ slice_list->tail = NULL;
+ } else if (slice_list->head == block) {
+ slice_list->head = block->next;
+ slice_list->head->prev = NULL;
+ } else if (slice_list->tail == block) {
+ slice_list->tail = block->prev;
+ slice_list->tail->next = NULL;
+ } else {
+ block->prev->next = block->next;
+ block->next->prev = block->prev;
+ }
+ tfp_free(block);
+ slice_list->cnt--;
+}
+/**
+ * Free the entire slice_list
+ */
+static void
+tf_sram_free_slice_list(struct tf_sram_slice_list *slice_list)
+{
+ uint32_t i, block_cnt;
+ struct tf_sram_block *nblock, *block;
+
+ block_cnt = tf_sram_get_block_cnt(slice_list);
+ block = slice_list->head;
+
+ for (i = 0; i < block_cnt; i++) {
+ nblock = block->next;
+ tf_sram_free_block(slice_list, block);
+ block = nblock;
+ }
+}
+
+/**
+ * Allocate a single SRAM block from memory and add it to the slice list
+ */
+static struct tf_sram_block
+*tf_sram_alloc_block(struct tf_sram_slice_list *slice_list,
+ uint16_t block_id)
+{
+ struct tf_sram_block *block;
+ struct tfp_calloc_parms cparms;
+ int rc;
+
+ cparms.nitems = 1;
+ cparms.size = sizeof(struct tf_sram_block);
+ cparms.alignment = 0;
+ rc = tfp_calloc(&cparms);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "Failed to allocate block, rc:%s\n",
+ strerror(-rc));
+ return NULL;
+ }
+ block = (struct tf_sram_block *)cparms.mem_va;
+ block->block_id = block_id;
+
+ if (slice_list->head == NULL) {
+ slice_list->head = block;
+ slice_list->tail = block;
+ block->next = NULL;
+ block->prev = NULL;
+ } else {
+ block->next = slice_list->head;
+ block->prev = NULL;
+ block->next->prev = block;
+ slice_list->head = block->next->prev;
+ }
+ slice_list->cnt++;
+ return block;
+}
+
+/**
+ * Find the first not full block in the slice list
+ */
+static void
+tf_sram_find_first_not_full_block(struct tf_sram_slice_list *slice_list,
+ enum tf_sram_slice_size slice_size,
+ struct tf_sram_block **first_not_full_block)
+{
+ struct tf_sram_block *block = slice_list->head;
+ uint8_t slice_mask, mask;
+
+ switch (slice_size) {
+ case TF_SRAM_SLICE_SIZE_8B:
+ slice_mask = 0xff;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_16B:
+ slice_mask = 0xf;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_32B:
+ slice_mask = 0x3;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_64B:
+ default:
+ slice_mask = 0x1;
+ break;
+ }
+
+ *first_not_full_block = NULL;
+
+ while (block) {
+ mask = block->in_use_mask & slice_mask;
+ if (mask != slice_mask) {
+ *first_not_full_block = block;
+ break;
+ }
+ block = block->next;
+ }
+}
+static void
+tf_sram_dump_block(struct tf_sram_block *block)
+{
+ TFP_DRV_LOG(INFO, "block_id(0x%x) in_use_mask(0x%02x)\n",
+ block->block_id,
+ block->in_use_mask);
+}
+
+/**********************
+ * External functions
+ **********************/
+int
+tf_sram_mgr_bind(void **sram_handle)
+{
+ int rc = 0;
+ enum tf_sram_bank_id bank_id;
+ enum tf_sram_slice_size slice_size;
+ struct tf_sram *sram;
+ struct tf_sram_slice_list *slice_list;
+ enum tf_dir dir;
+ struct tfp_calloc_parms cparms;
+
+ TF_CHECK_PARMS1(sram_handle);
+
+ cparms.nitems = 1;
+ cparms.size = sizeof(struct tf_sram);
+ cparms.alignment = 0;
+ rc = tfp_calloc(&cparms);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "Failed to allocate SRAM mgmt data, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ sram = (struct tf_sram *)cparms.mem_va;
+
+ /* For each direction
+ */
+ for (dir = 0; dir < TF_DIR_MAX; dir++) {
+ /* For each bank
+ */
+ for (bank_id = TF_SRAM_BANK_ID_0;
+ bank_id < TF_SRAM_BANK_ID_MAX;
+ bank_id++) {
+ /* Create each sized slice empty list
+ */
+ for (slice_size = TF_SRAM_SLICE_SIZE_8B;
+ slice_size < TF_SRAM_SLICE_SIZE_MAX;
+ slice_size++) {
+ rc = tf_sram_get_slice_list(sram, &slice_list,
+ slice_size, dir,
+ bank_id);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "No SRAM slice list, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ tf_sram_init_slice_list(slice_list, slice_size);
+ }
+ }
+ }
+
+ *sram_handle = sram;
+
+ return rc;
+}
+
+int
+tf_sram_mgr_unbind(void *sram_handle)
+{
+ int rc = 0;
+ struct tf_sram *sram;
+ enum tf_sram_bank_id bank_id;
+ enum tf_sram_slice_size slice_size;
+ enum tf_dir dir;
+ struct tf_sram_slice_list *slice_list;
+
+ TF_CHECK_PARMS1(sram_handle);
+
+ sram = (struct tf_sram *)sram_handle;
+
+ for (dir = 0; dir < TF_DIR_MAX; dir++) {
+ /* For each bank
+ */
+ for (bank_id = TF_SRAM_BANK_ID_0;
+ bank_id < TF_SRAM_BANK_ID_MAX;
+ bank_id++) {
+ /* For each slice size
+ */
+ for (slice_size = TF_SRAM_SLICE_SIZE_8B;
+ slice_size < TF_SRAM_SLICE_SIZE_MAX;
+ slice_size++) {
+ rc = tf_sram_get_slice_list(sram, &slice_list,
+ slice_size, dir,
+ bank_id);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "No SRAM slice list, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ if (tf_sram_get_block_cnt(slice_list))
+ tf_sram_free_slice_list(slice_list);
+ }
+ }
+ }
+
+ tfp_free(sram);
+ sram_handle = NULL;
+
+ /* Freeing of the RM resources is handled by the table manager */
+ return rc;
+}
+
+int tf_sram_mgr_alloc(void *sram_handle,
+ struct tf_sram_mgr_alloc_parms *parms)
+{
+ int rc = 0;
+ struct tf_sram *sram;
+ struct tf_sram_slice_list *slice_list;
+ uint16_t block_id, slice_offset = 0;
+ uint32_t index;
+ struct tf_sram_block *block;
+ struct tf_rm_allocate_parms aparms = { 0 };
+ bool block_is_full;
+ uint16_t block_offset;
+
+ TF_CHECK_PARMS3(sram_handle, parms, parms->sram_offset);
+
+ sram = (struct tf_sram *)sram_handle;
+
+ /* Check the current slice list
+ */
+ rc = tf_sram_get_slice_list(sram, &slice_list, parms->slice_size,
+ parms->dir, parms->bank_id);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "No SRAM slice list, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ /* If the list is empty or all entries are full allocate a new block
+ */
+ if (!slice_list->first_not_full_block) {
+ /* Allocate and insert a new block
+ */
+ aparms.index = &index;
+ aparms.subtype = parms->tbl_type;
+ aparms.rm_db = parms->rm_db;
+ rc = tf_rm_allocate(&aparms);
+ if (rc)
+ return rc;
+
+ block_id = index;
+ block = tf_sram_alloc_block(slice_list, block_id);
+ } else {
+ /* Block exists
+ */
+ block =
+ (struct tf_sram_block *)(slice_list->first_not_full_block);
+ }
+ rc = tf_sram_get_next_slice_in_block(block,
+ parms->slice_size,
+ &slice_offset,
+ &block_is_full);
+
+ /* Find the new first non-full block in the list
+ */
+ tf_sram_find_first_not_full_block(slice_list,
+ parms->slice_size,
+ &slice_list->first_not_full_block);
+
+ tf_sram_block_id_2_offset(parms->bank_id, block->block_id,
+ &block_offset);
+
+ *parms->sram_offset = block_offset + slice_offset;
+ return rc;
+}
+
+int
+tf_sram_mgr_free(void *sram_handle,
+ struct tf_sram_mgr_free_parms *parms)
+{
+ int rc = 0;
+ struct tf_sram *sram;
+ struct tf_sram_slice_list *slice_list;
+ uint16_t block_id, slice_offset;
+ struct tf_sram_block *block;
+ bool block_is_empty;
+ struct tf_rm_free_parms fparms = { 0 };
+
+ TF_CHECK_PARMS2(sram_handle, parms);
+
+ sram = (struct tf_sram *)sram_handle;
+
+ /* Check the current slice list
+ */
+ rc = tf_sram_get_slice_list(sram, &slice_list, parms->slice_size,
+ parms->dir, parms->bank_id);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "No SRAM slice list, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ /* Determine the block id and slice offset from the SRAM offset
+ */
+ tf_sram_offset_2_block_id(parms->bank_id, parms->sram_offset, &block_id,
+ &slice_offset);
+
+ /* Search the list of blocks for the matching block id
+ */
+ block = tf_sram_find_block(block_id, slice_list);
+ if (block == NULL) {
+ TFP_DRV_LOG(ERR, "block not found 0x%x\n", block_id);
+ return rc;
+ }
+
+ /* If found, search for the matching SRAM slice in use.
+ */
+ rc = tf_sram_free_slice(parms->slice_size, slice_offset,
+ block, &block_is_empty);
+ if (rc) {
+ TFP_DRV_LOG(ERR, "Error freeing slice (%s)\n", strerror(-rc));
+ return rc;
+ }
+#if (STATS_CLEAR_ON_READ_SUPPORT == 0)
+ /* If this is a counter, clear it. In the future we need to switch to
+ * using the special access registers on Thor to automatically clear on
+ * read.
+ */
+ /* If this is counter table, clear the entry on free */
+ if (parms->tbl_type == TF_TBL_TYPE_ACT_STATS_64) {
+ uint8_t data[8] = { 0 };
+ uint16_t hcapi_type = 0;
+ struct tf_rm_get_hcapi_parms hparms = { 0 };
+
+ /* Get the hcapi type */
+ hparms.rm_db = parms->rm_db;
+ hparms.subtype = parms->tbl_type;
+ hparms.hcapi_type = &hcapi_type;
+ rc = tf_rm_get_hcapi_type(&hparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Failed type lookup, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->tbl_type),
+ strerror(-rc));
+ return rc;
+ }
+ /* Clear the counter
+ */
+ rc = tf_msg_set_tbl_entry(parms->tfp,
+ parms->dir,
+ hcapi_type,
+ sizeof(data),
+ data,
+ parms->sram_offset);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Set failed, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->tbl_type),
+ strerror(-rc));
+ return rc;
+ }
+ }
+#endif
+ /* If the block is empty, free the block to the RM
+ */
+ if (block_is_empty) {
+ fparms.rm_db = parms->rm_db;
+ fparms.subtype = parms->tbl_type;
+ fparms.index = block_id;
+ rc = tf_rm_free(&fparms);
+
+ if (rc) {
+ TFP_DRV_LOG(ERR, "Free block_id(%d) failed error(%s)\n",
+ block_id, strerror(-rc));
+ }
+ /* Free local entry regardless
+ */
+ tf_sram_free_block(slice_list, block);
+
+ /* Find the next non-full block in the list
+ */
+ tf_sram_find_first_not_full_block(slice_list,
+ parms->slice_size,
+ &slice_list->first_not_full_block);
+ }
+
+ return rc;
+}
+
+int
+tf_sram_mgr_dump(void *sram_handle,
+ struct tf_sram_mgr_dump_parms *parms)
+{
+ int rc = 0;
+ struct tf_sram *sram;
+ struct tf_sram_slice_list *slice_list;
+ uint32_t block_cnt, i;
+ struct tf_sram_block *block;
+
+ TF_CHECK_PARMS2(sram_handle, parms);
+
+ sram = (struct tf_sram *)sram_handle;
+
+ rc = tf_sram_get_slice_list(sram, &slice_list, parms->slice_size,
+ parms->dir, parms->bank_id);
+ if (rc)
+ return rc;
+
+ if (slice_list->cnt || slice_list->first_not_full_block) {
+ TFP_DRV_LOG(INFO, "\n********** %s: %s: %s ***********\n",
+ tf_sram_bank_2_str(parms->bank_id),
+ tf_dir_2_str(parms->dir),
+ tf_sram_slice_2_str(parms->slice_size));
+
+ block_cnt = tf_sram_get_block_cnt(slice_list);
+ TFP_DRV_LOG(INFO, "block_cnt(%d)\n", block_cnt);
+ if (slice_list->first_not_full_block)
+ TFP_DRV_LOG(INFO, "first_not_full_block(0x%x)\n",
+ slice_list->first_not_full_block->block_id);
+ block = slice_list->head;
+ for (i = 0; i < block_cnt; i++) {
+ tf_sram_dump_block(block);
+ block = tf_sram_get_next_block(block);
+ }
+ TFP_DRV_LOG(INFO, "*********************************\n");
+ }
+ return rc;
+}
+/**
+ * Validate an SRAM Slice is allocated
+ *
+ * Validate whether the SRAM slice is allocated
+ *
+ * [in] sram_handle
+ * Pointer to SRAM handle
+ *
+ * [in] parms
+ * Pointer to the SRAM alloc parameters
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ *
+ */
+int tf_sram_mgr_is_allocated(void *sram_handle,
+ struct tf_sram_mgr_is_allocated_parms *parms)
+{
+ int rc = 0;
+ struct tf_sram *sram;
+ struct tf_sram_slice_list *slice_list;
+ uint16_t block_id, slice_offset;
+ struct tf_sram_block *block;
+
+ TF_CHECK_PARMS3(sram_handle, parms, parms->is_allocated);
+
+ sram = (struct tf_sram *)sram_handle;
+
+ /* Check the current slice list
+ */
+ rc = tf_sram_get_slice_list(sram, &slice_list, parms->slice_size,
+ parms->dir, parms->bank_id);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "No SRAM slice list, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ /* If the list is empty, then it cannot be allocated
+ */
+ if (!slice_list->cnt) {
+ TFP_DRV_LOG(ERR, "List is empty for %s:%s:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_sram_slice_2_str(parms->slice_size),
+ tf_sram_bank_2_str(parms->bank_id));
+
+ parms->is_allocated = false;
+ goto done;
+ }
+
+ /* Determine the block id and slice offset from the SRAM offset
+ */
+ tf_sram_offset_2_block_id(parms->bank_id, parms->sram_offset, &block_id,
+ &slice_offset);
+
+ /* Search the list of blocks for the matching block id
+ */
+ block = tf_sram_find_block(block_id, slice_list);
+ if (block == NULL) {
+ TFP_DRV_LOG(ERR, "block not found in list 0x%x\n",
+ parms->sram_offset);
+ parms->is_allocated = false;
+ goto done;
+ }
+
+ rc = tf_sram_is_slice_allocated_in_block(block,
+ parms->slice_size,
+ slice_offset,
+ parms->is_allocated);
+done:
+ return rc;
+}
diff --git a/drivers/net/bnxt/tf_core/tf_sram_mgr.h b/drivers/net/bnxt/tf_core/tf_sram_mgr.h
new file mode 100644
index 0000000000..4abe3fb468
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/tf_sram_mgr.h
@@ -0,0 +1,317 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019-2021 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef _TF_SRAM_MGR_H_
+#define _TF_SRAM_MGR_H_
+
+#include <string.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <ctype.h>
+#include <limits.h>
+#include <errno.h>
+#include "tf_core.h"
+#include "tf_rm.h"
+
+/* When special access registers are used to access the SRAM, stats can be
+ * automatically cleared on read by the hardware. This requires additional
+ * support to be added in the firmware to use these registers for statistics.
+ * The support entails using the special access registers to read the stats.
+ * These are stored in bank 3 currently but may move depending upon the
+ * policy defined in tf_device_p58.h
+ */
+#define STATS_CLEAR_ON_READ_SUPPORT 0
+
+#define TF_SRAM_MGR_BLOCK_SZ_BYTES 64
+#define TF_SRAM_MGR_MIN_SLICE_BYTES 8
+/**
+ * Bank identifier
+ */
+enum tf_sram_bank_id {
+ TF_SRAM_BANK_ID_0, /**< SRAM Bank 0 id */
+ TF_SRAM_BANK_ID_1, /**< SRAM Bank 1 id */
+ TF_SRAM_BANK_ID_2, /**< SRAM Bank 2 id */
+ TF_SRAM_BANK_ID_3, /**< SRAM Bank 3 id */
+ TF_SRAM_BANK_ID_MAX /**< SRAM Bank index limit */
+};
+
+/**
+ * TF slice size.
+ *
+ * A slice is part of a 64B row
+ *
+ * Each slice is a multiple of 8B
+ */
+enum tf_sram_slice_size {
+ TF_SRAM_SLICE_SIZE_8B, /**< 8 byte SRAM slice */
+ TF_SRAM_SLICE_SIZE_16B, /**< 16 byte SRAM slice */
+ TF_SRAM_SLICE_SIZE_32B, /**< 32 byte SRAM slice */
+ TF_SRAM_SLICE_SIZE_64B, /**< 64 byte SRAM slice */
+ TF_SRAM_SLICE_SIZE_MAX /**< slice limit */
+};
+
+
+/** Initialize the SRAM slice manager
+ *
+ * The SRAM slice manager manages slices within 64B rows. Slices are of size
+ * tf_sram_slice_size. This function provides a handle to the SRAM manager
+ * data.
+ *
+ * SRAM manager data may dynamically allocate data upon initialization if
+ * running on the host.
+ *
+ * [in/out] sram_handle
+ * Pointer to SRAM handle
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ *
+ * Returns the handle for the SRAM slice manager
+ */
+int tf_sram_mgr_bind(void **sram_handle);
+
+/** Uninitialize the SRAM slice manager
+ *
+ * Frees any dynamically allocated data structures for SRAM slice management.
+ *
+ * [in] sram_handle
+ * Pointer to SRAM handle
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ */
+int tf_sram_mgr_unbind(void *sram_handle);
+
+/**
+ * tf_sram_mgr_alloc_parms parameter definition
+ */
+struct tf_sram_mgr_alloc_parms {
+ /**
+ * [in] dir
+ */
+ enum tf_dir dir;
+ /**
+ * [in] bank
+ *
+ * the SRAM bank to allocate from
+ */
+ enum tf_sram_bank_id bank_id;
+ /**
+ * [in] slice_size
+ *
+ * the slice size to allocate
+ */
+ enum tf_sram_slice_size slice_size;
+ /**
+ * [in/out] sram_slice
+ *
+ * A pointer to be filled with an 8B sram slice offset
+ */
+ uint16_t *sram_offset;
+ /**
+ * [in] RM DB Handle required for RM allocation
+ */
+ void *rm_db;
+ /**
+ * [in] tf table type
+ */
+ enum tf_tbl_type tbl_type;
+};
+
+/**
+ * Allocate an SRAM Slice
+ *
+ * Allocate an SRAM slice from the indicated bank. If successful an 8B SRAM
+ * offset will be returned. Slices are variable sized. This may result in
+ * a row being allocated from the RM SRAM bank pool if required.
+ *
+ * [in] sram_handle
+ * Pointer to SRAM handle
+ *
+ * [in] parms
+ * Pointer to the SRAM alloc parameters
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ *
+ */
+int tf_sram_mgr_alloc(void *sram_handle,
+ struct tf_sram_mgr_alloc_parms *parms);
+/**
+ * tf_sram_mgr_free_parms parameter definition
+ */
+struct tf_sram_mgr_free_parms {
+ /**
+ * [in] dir
+ */
+ enum tf_dir dir;
+ /**
+ * [in] bank
+ *
+ * the SRAM bank to free to
+ */
+ enum tf_sram_bank_id bank_id;
+ /**
+ * [in] slice_size
+ *
+ * the slice size to be returned
+ */
+ enum tf_sram_slice_size slice_size;
+ /**
+ * [in] sram_offset
+ *
+ * the SRAM slice offset (8B) to be returned
+ */
+ uint16_t sram_offset;
+ /**
+ * [in] RM DB Handle required for RM free
+ */
+ void *rm_db;
+ /**
+ * [in] tf table type
+ */
+ enum tf_tbl_type tbl_type;
+#if (STATS_CLEAR_ON_READ_SUPPORT == 0)
+ /**
+ * [in] tfp
+ *
+ * A pointer to the tf handle
+ */
+ void *tfp;
+#endif
+};
+
+/**
+ * Free an SRAM Slice
+ *
+ * Free an SRAM slice to the indicated bank. This may result in a 64B row
+ * being returned to the RM SRAM bank pool.
+ *
+ * [in] sram_handle
+ * Pointer to SRAM handle
+ *
+ * [in] parms
+ * Pointer to the SRAM free parameters
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ *
+ */
+int tf_sram_mgr_free(void *sram_handle,
+ struct tf_sram_mgr_free_parms *parms);
+
+/**
+ * tf_sram_mgr_dump_parms parameter definition
+ */
+struct tf_sram_mgr_dump_parms {
+ /**
+ * [in] dir
+ */
+ enum tf_dir dir;
+ /**
+ * [in] bank
+ *
+ * the SRAM bank to dump
+ */
+ enum tf_sram_bank_id bank_id;
+ /**
+ * [in] slice_size
+ *
+ * the slice size list to be dumped
+ */
+ enum tf_sram_slice_size slice_size;
+};
+
+/**
+ * Dump a slice list
+ *
+ * Dump the slice list given the SRAM bank and the slice size
+ *
+ * [in] sram_handle
+ * Pointer to SRAM handle
+ *
+ * [in] parms
+ * Pointer to the SRAM free parameters
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ *
+ */
+int tf_sram_mgr_dump(void *sram_handle,
+ struct tf_sram_mgr_dump_parms *parms);
+
+/**
+ * tf_sram_mgr_is_allocated_parms parameter definition
+ */
+struct tf_sram_mgr_is_allocated_parms {
+ /**
+ * [in] dir
+ */
+ enum tf_dir dir;
+ /**
+ * [in] bank
+ *
+ * the SRAM bank to allocate from
+ */
+ enum tf_sram_bank_id bank_id;
+ /**
+ * [in] slice_size
+ *
+ * the slice size which was allocated
+ */
+ enum tf_sram_slice_size slice_size;
+ /**
+ * [in] sram_offset
+ *
+ * The sram slice offset to validate
+ */
+ uint16_t sram_offset;
+ /**
+ * [in/out] is_allocated
+ *
+ * Pointer passed in to be filled with indication of allocation
+ */
+ bool *is_allocated;
+};
+
+/**
+ * Validate an SRAM Slice is allocated
+ *
+ * Validate whether the SRAM slice is allocated
+ *
+ * [in] sram_handle
+ * Pointer to SRAM handle
+ *
+ * [in] parms
+ * Pointer to the SRAM alloc parameters
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ *
+ */
+int tf_sram_mgr_is_allocated(void *sram_handle,
+ struct tf_sram_mgr_is_allocated_parms *parms);
+
+/**
+ * Given the slice size, return a char string
+ */
+const char
+*tf_sram_slice_2_str(enum tf_sram_slice_size slice_size);
+
+/**
+ * Given the bank_id, return a char string
+ */
+const char
+*tf_sram_bank_2_str(enum tf_sram_bank_id bank_id);
+
+#endif /* _TF_SRAM_MGR_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c
index 7011edcd78..0a8720e7b6 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl.c
+++ b/drivers/net/bnxt/tf_core/tf_tbl.c
@@ -16,20 +16,11 @@
#include "tf_session.h"
#include "tf_device.h"
-#define TF_TBL_RM_TO_PTR(new_idx, idx, base, shift) { \
- *(new_idx) = (((idx) + (base)) << (shift)); \
-}
-
-#define TF_TBL_PTR_TO_RM(new_idx, idx, base, shift) { \
- *(new_idx) = (((idx) >> (shift)) - (base)); \
-}
-
struct tf;
-/**
- * Shadow init flag, set on bind and cleared on unbind
- */
-static uint8_t shadow_init;
+#define TF_TBL_RM_TO_PTR(new_idx, idx, base, shift) { \
+ *(new_idx) = (((idx) + (base)) << (shift)); \
+}
int
tf_tbl_bind(struct tf *tfp,
@@ -121,8 +112,6 @@ tf_tbl_unbind(struct tf *tfp)
tbl_db->tbl_db[i] = NULL;
}
- shadow_init = 0;
-
return 0;
}
@@ -135,7 +124,6 @@ tf_tbl_alloc(struct tf *tfp __rte_unused,
struct tf_rm_allocate_parms aparms = { 0 };
struct tf_session *tfs;
struct tf_dev_info *dev;
- uint16_t base = 0, shift = 0;
struct tbl_rm_db *tbl_db;
void *tbl_db_ptr = NULL;
@@ -154,28 +142,12 @@ tf_tbl_alloc(struct tf *tfp __rte_unused,
rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr);
if (rc) {
TFP_DRV_LOG(ERR,
- "Failed to get em_ext_db from session, rc:%s\n",
+ "Failed to get tbl_db from session, rc:%s\n",
strerror(-rc));
return rc;
}
tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
- /* Only get table info if required for the device */
- if (dev->ops->tf_dev_get_tbl_info) {
- rc = dev->ops->tf_dev_get_tbl_info(tfp,
- tbl_db->tbl_db[parms->dir],
- parms->type,
- &base,
- &shift);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed to get table info:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type);
- return rc;
- }
- }
-
/* Allocate requested element */
aparms.rm_db = tbl_db->tbl_db[parms->dir];
aparms.subtype = parms->type;
@@ -183,13 +155,12 @@ tf_tbl_alloc(struct tf *tfp __rte_unused,
rc = tf_rm_allocate(&aparms);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s: Failed allocate, type:%d\n",
+ "%s: Failed allocate, type:%s\n",
tf_dir_2_str(parms->dir),
- parms->type);
+ tf_tbl_type_2_str(parms->type));
return rc;
}
- TF_TBL_RM_TO_PTR(&idx, idx, base, shift);
*parms->idx = idx;
return 0;
@@ -205,7 +176,6 @@ tf_tbl_free(struct tf *tfp __rte_unused,
int allocated = 0;
struct tf_session *tfs;
struct tf_dev_info *dev;
- uint16_t base = 0, shift = 0;
struct tbl_rm_db *tbl_db;
void *tbl_db_ptr = NULL;
@@ -230,28 +200,10 @@ tf_tbl_free(struct tf *tfp __rte_unused,
}
tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
- /* Only get table info if required for the device */
- if (dev->ops->tf_dev_get_tbl_info) {
- rc = dev->ops->tf_dev_get_tbl_info(tfp,
- tbl_db->tbl_db[parms->dir],
- parms->type,
- &base,
- &shift);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed to get table info:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type);
- return rc;
- }
- }
-
/* Check if element is in use */
aparms.rm_db = tbl_db->tbl_db[parms->dir];
aparms.subtype = parms->type;
-
- TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift);
-
+ aparms.index = parms->idx;
aparms.allocated = &allocated;
rc = tf_rm_is_allocated(&aparms);
if (rc)
@@ -259,9 +211,9 @@ tf_tbl_free(struct tf *tfp __rte_unused,
if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
TFP_DRV_LOG(ERR,
- "%s: Entry already free, type:%d, index:%d\n",
+ "%s: Entry already free, type:%s, index:%d\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
parms->idx);
return -EINVAL;
}
@@ -279,9 +231,9 @@ tf_tbl_free(struct tf *tfp __rte_unused,
rc = tf_rm_get_hcapi_type(&hparms);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Failed type lookup, type:%d, rc:%s\n",
+ "%s, Failed type lookup, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
return rc;
}
@@ -295,9 +247,9 @@ tf_tbl_free(struct tf *tfp __rte_unused,
parms->idx);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Set failed, type:%d, rc:%s\n",
+ "%s, Set failed, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
return rc;
}
@@ -306,15 +258,13 @@ tf_tbl_free(struct tf *tfp __rte_unused,
/* Free requested element */
fparms.rm_db = tbl_db->tbl_db[parms->dir];
fparms.subtype = parms->type;
-
- TF_TBL_PTR_TO_RM(&fparms.index, parms->idx, base, shift);
-
+ fparms.index = parms->idx;
rc = tf_rm_free(&fparms);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s: Free failed, type:%d, index:%d\n",
+ "%s: Free failed, type:%s, index:%d\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
parms->idx);
return rc;
}
@@ -333,7 +283,6 @@ tf_tbl_set(struct tf *tfp,
struct tf_rm_get_hcapi_parms hparms = { 0 };
struct tf_session *tfs;
struct tf_dev_info *dev;
- uint16_t base = 0, shift = 0;
struct tbl_rm_db *tbl_db;
void *tbl_db_ptr = NULL;
@@ -358,21 +307,6 @@ tf_tbl_set(struct tf *tfp,
}
tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
- /* Only get table info if required for the device */
- if (dev->ops->tf_dev_get_tbl_info) {
- rc = dev->ops->tf_dev_get_tbl_info(tfp,
- tbl_db->tbl_db[parms->dir],
- parms->type,
- &base,
- &shift);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed to get table info:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type);
- return rc;
- }
- }
/* Do not check meter drop counter because it is not allocated
* resources
@@ -381,19 +315,18 @@ tf_tbl_set(struct tf *tfp,
/* Verify that the entry has been previously allocated */
aparms.rm_db = tbl_db->tbl_db[parms->dir];
aparms.subtype = parms->type;
- TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift);
-
aparms.allocated = &allocated;
+ aparms.index = parms->idx;
rc = tf_rm_is_allocated(&aparms);
if (rc)
return rc;
if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
TFP_DRV_LOG(ERR,
- "%s, Invalid or not allocated index, type:%d, idx:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type,
- parms->idx);
+ "%s, Invalid or not allocated, type:%s, idx:%d\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->idx);
return -EINVAL;
}
}
@@ -405,9 +338,9 @@ tf_tbl_set(struct tf *tfp,
rc = tf_rm_get_hcapi_type(&hparms);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Failed type lookup, type:%d, rc:%s\n",
+ "%s, Failed type lookup, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
return rc;
}
@@ -420,9 +353,9 @@ tf_tbl_set(struct tf *tfp,
parms->idx);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Set failed, type:%d, rc:%s\n",
+ "%s, Set failed, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
return rc;
}
@@ -441,7 +374,6 @@ tf_tbl_get(struct tf *tfp,
struct tf_rm_get_hcapi_parms hparms = { 0 };
struct tf_session *tfs;
struct tf_dev_info *dev;
- uint16_t base = 0, shift = 0;
struct tbl_rm_db *tbl_db;
void *tbl_db_ptr = NULL;
@@ -466,22 +398,6 @@ tf_tbl_get(struct tf *tfp,
}
tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
- /* Only get table info if required for the device */
- if (dev->ops->tf_dev_get_tbl_info) {
- rc = dev->ops->tf_dev_get_tbl_info(tfp,
- tbl_db->tbl_db[parms->dir],
- parms->type,
- &base,
- &shift);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed to get table info:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type);
- return rc;
- }
- }
-
/* Do not check meter drop counter because it is not allocated
* resources.
*/
@@ -489,8 +405,7 @@ tf_tbl_get(struct tf *tfp,
/* Verify that the entry has been previously allocated */
aparms.rm_db = tbl_db->tbl_db[parms->dir];
aparms.subtype = parms->type;
- TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift);
-
+ aparms.index = parms->idx;
aparms.allocated = &allocated;
rc = tf_rm_is_allocated(&aparms);
if (rc)
@@ -498,9 +413,9 @@ tf_tbl_get(struct tf *tfp,
if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
TFP_DRV_LOG(ERR,
- "%s, Invalid or not allocated index, type:%d, idx:%d\n",
+ "%s, Invalid or not allocated index, type:%s, idx:%d\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
parms->idx);
return -EINVAL;
}
@@ -513,9 +428,9 @@ tf_tbl_get(struct tf *tfp,
rc = tf_rm_get_hcapi_type(&hparms);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Failed type lookup, type:%d, rc:%s\n",
+ "%s, Failed type lookup, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
return rc;
}
@@ -529,9 +444,9 @@ tf_tbl_get(struct tf *tfp,
parms->idx);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Get failed, type:%d, rc:%s\n",
+ "%s, Get failed, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
return rc;
}
@@ -549,7 +464,6 @@ tf_tbl_bulk_get(struct tf *tfp,
struct tf_rm_check_indexes_in_range_parms cparms = { 0 };
struct tf_session *tfs;
struct tf_dev_info *dev;
- uint16_t base = 0, shift = 0;
struct tbl_rm_db *tbl_db;
void *tbl_db_ptr = NULL;
@@ -574,40 +488,21 @@ tf_tbl_bulk_get(struct tf *tfp,
}
tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
- /* Only get table info if required for the device */
- if (dev->ops->tf_dev_get_tbl_info) {
- rc = dev->ops->tf_dev_get_tbl_info(tfp,
- tbl_db->tbl_db[parms->dir],
- parms->type,
- &base,
- &shift);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed to get table info:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type);
- return rc;
- }
- }
-
/* Verify that the entries are in the range of reserved resources. */
cparms.rm_db = tbl_db->tbl_db[parms->dir];
cparms.subtype = parms->type;
-
- TF_TBL_PTR_TO_RM(&cparms.starting_index, parms->starting_idx,
- base, shift);
-
cparms.num_entries = parms->num_entries;
+ cparms.starting_index = parms->starting_idx;
rc = tf_rm_check_indexes_in_range(&cparms);
if (rc) {
TFP_DRV_LOG(ERR,
"%s, Invalid or %d index starting from %d"
- " not in range, type:%d",
+ " not in range, type:%s",
tf_dir_2_str(parms->dir),
parms->starting_idx,
parms->num_entries,
- parms->type);
+ tf_tbl_type_2_str(parms->type));
return rc;
}
@@ -617,9 +512,9 @@ tf_tbl_bulk_get(struct tf *tfp,
rc = tf_rm_get_hcapi_type(&hparms);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Failed type lookup, type:%d, rc:%s\n",
+ "%s, Failed type lookup, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
return rc;
}
@@ -634,9 +529,9 @@ tf_tbl_bulk_get(struct tf *tfp,
parms->physical_mem_addr);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Bulk get failed, type:%d, rc:%s\n",
+ "%s, Bulk get failed, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
}
@@ -653,9 +548,9 @@ tf_tbl_get_resc_info(struct tf *tfp,
struct tf_rm_get_alloc_info_parms ainfo;
void *tbl_db_ptr = NULL;
struct tbl_rm_db *tbl_db;
- uint16_t base = 0, shift = 0;
struct tf_dev_info *dev;
struct tf_session *tfs;
+ uint16_t base = 0, shift = 0;
TF_CHECK_PARMS2(tfp, tbl);
@@ -677,7 +572,6 @@ tf_tbl_get_resc_info(struct tf *tfp,
tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
- /* check if reserved resource for WC is multiple of num_slices */
for (d = 0; d < TF_DIR_MAX; d++) {
ainfo.rm_db = tbl_db->tbl_db[d];
dinfo = tbl[d].info;
diff --git a/drivers/net/bnxt/tf_core/tf_tbl.h b/drivers/net/bnxt/tf_core/tf_tbl.h
index 7e1107ffe7..2483718e5d 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl.h
+++ b/drivers/net/bnxt/tf_core/tf_tbl.h
@@ -28,14 +28,6 @@ struct tf_tbl_cfg_parms {
* Table Type element configuration array
*/
struct tf_rm_element_cfg *cfg;
- /**
- * Shadow table type configuration array
- */
- struct tf_shadow_tbl_cfg *shadow_cfg;
- /**
- * Boolean controlling the request shadow copy.
- */
- bool shadow_copy;
/**
* Session resource allocations
*/
@@ -197,8 +189,6 @@ struct tbl_rm_db {
*
* @ref tf_tbl_free
*
- * @ref tf_tbl_alloc_search
- *
* @ref tf_tbl_set
*
* @ref tf_tbl_get
@@ -255,10 +245,7 @@ int tf_tbl_alloc(struct tf *tfp,
struct tf_tbl_alloc_parms *parms);
/**
- * Free's the requested table type and returns it to the DB. If shadow
- * DB is enabled its searched first and if found the element refcount
- * is decremented. If refcount goes to 0 then its returned to the
- * table type DB.
+ * Frees the requested table type and returns it to the DB.
*
* [in] tfp
* Pointer to TF handle, used for HCAPI communication
diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.c b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
new file mode 100644
index 0000000000..ea10afecb6
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
@@ -0,0 +1,713 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019-2021 Broadcom
+ * All rights reserved.
+ */
+
+/* Truflow Table APIs and supporting code */
+
+#include <rte_common.h>
+
+#include "tf_tbl.h"
+#include "tf_tbl_sram.h"
+#include "tf_sram_mgr.h"
+#include "tf_common.h"
+#include "tf_rm.h"
+#include "tf_util.h"
+#include "tf_msg.h"
+#include "tfp.h"
+#include "tf_session.h"
+#include "tf_device.h"
+#include "cfa_resource_types.h"
+
+#define DBG_SRAM 0
+
+/**
+ * tf_sram_tbl_get_info_parms parameter definition
+ */
+struct tf_tbl_sram_get_info_parms {
+ /**
+ * [in] table RM database
+ */
+ void *rm_db;
+ /**
+ * [in] Receive or transmit direction
+ */
+ enum tf_dir dir;
+ /**
+ * [in] table_type
+ *
+ * the TF index table type
+ */
+ enum tf_tbl_type tbl_type;
+ /**
+ * [out] bank
+ *
+ * The SRAM bank associated with the type
+ */
+ enum tf_sram_bank_id bank_id;
+ /**
+ * [out] slice_size
+ *
+ * the slice size for the indicated table type
+ */
+ enum tf_sram_slice_size slice_size;
+};
+
+/**
+ * Translate HCAPI type to SRAM Manager bank
+ */
+const uint16_t tf_tbl_sram_hcapi_2_bank[CFA_RESOURCE_TYPE_P58_LAST] = {
+ [CFA_RESOURCE_TYPE_P58_SRAM_BANK_0] = TF_SRAM_BANK_ID_0,
+ [CFA_RESOURCE_TYPE_P58_SRAM_BANK_1] = TF_SRAM_BANK_ID_1,
+ [CFA_RESOURCE_TYPE_P58_SRAM_BANK_2] = TF_SRAM_BANK_ID_2,
+ [CFA_RESOURCE_TYPE_P58_SRAM_BANK_3] = TF_SRAM_BANK_ID_3
+};
+
+#define TF_TBL_SRAM_SLICES_MAX \
+ (TF_SRAM_MGR_BLOCK_SZ_BYTES / TF_SRAM_MGR_MIN_SLICE_BYTES)
+/**
+ * Translate HCAPI type to SRAM Manager bank
+ */
+const uint8_t tf_tbl_sram_slices_2_size[TF_TBL_SRAM_SLICES_MAX + 1] = {
+ [0] = TF_SRAM_SLICE_SIZE_64B, /* if 0 slices assume 1 64B block */
+ [1] = TF_SRAM_SLICE_SIZE_64B, /* 1 slice per 64B block */
+ [2] = TF_SRAM_SLICE_SIZE_32B, /* 2 slices per 64B block */
+ [4] = TF_SRAM_SLICE_SIZE_16B, /* 4 slices per 64B block */
+ [8] = TF_SRAM_SLICE_SIZE_8B /* 8 slices per 64B block */
+};
+
+/**
+ * Get SRAM Table Information for a given index table type
+ *
+ *
+ * [in] sram_handle
+ * Pointer to SRAM handle
+ *
+ * [in] parms
+ * Pointer to the SRAM get info parameters
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ *
+ */
+static int tf_tbl_sram_get_info(struct tf_tbl_sram_get_info_parms *parms)
+{
+ int rc = 0;
+ uint16_t hcapi_type;
+ uint16_t slices;
+ struct tf_rm_get_hcapi_parms hparms;
+ struct tf_rm_get_slices_parms sparms;
+
+ hparms.rm_db = parms->rm_db;
+ hparms.subtype = parms->tbl_type;
+ hparms.hcapi_type = &hcapi_type;
+
+ rc = tf_rm_get_hcapi_type(&hparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get hcapi_type %s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->tbl_type),
+ strerror(-rc));
+ return rc;
+ }
+ parms->bank_id = tf_tbl_sram_hcapi_2_bank[hcapi_type];
+
+ sparms.rm_db = parms->rm_db;
+ sparms.subtype = parms->tbl_type;
+ sparms.slices = &slices;
+
+ rc = tf_rm_get_slices(&sparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get slice cnt %s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->tbl_type),
+ strerror(-rc));
+ return rc;
+ }
+ if (slices)
+ parms->slice_size = tf_tbl_sram_slices_2_size[slices];
+
+ TFP_DRV_LOG(INFO,
+ "(%s) bank(%s) slice_size(%s)\n",
+ tf_tbl_type_2_str(parms->tbl_type),
+ tf_sram_bank_2_str(parms->bank_id),
+ tf_sram_slice_2_str(parms->slice_size));
+ return rc;
+}
+
+int
+tf_tbl_sram_bind(struct tf *tfp __rte_unused)
+{
+ int rc = 0;
+ void *sram_handle = NULL;
+
+ TF_CHECK_PARMS1(tfp);
+
+ rc = tf_sram_mgr_bind(&sram_handle);
+
+ tf_session_set_sram_db(tfp, sram_handle);
+
+ TFP_DRV_LOG(INFO,
+ "SRAM Table - initialized\n");
+
+ return rc;
+}
+
+int
+tf_tbl_sram_unbind(struct tf *tfp __rte_unused)
+{
+ int rc = 0;
+ void *sram_handle = NULL;
+
+ TF_CHECK_PARMS1(tfp);
+
+ rc = tf_session_get_sram_db(tfp, &sram_handle);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get sram_handle from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ if (sram_handle)
+ rc = tf_sram_mgr_unbind(sram_handle);
+
+ TFP_DRV_LOG(INFO,
+ "SRAM Table - deinitialized\n");
+ return rc;
+}
+
+int
+tf_tbl_sram_alloc(struct tf *tfp,
+ struct tf_tbl_alloc_parms *parms)
+{
+ int rc;
+ uint16_t idx;
+ struct tf_session *tfs;
+ struct tf_dev_info *dev;
+ struct tf_tbl_sram_get_info_parms iparms = { 0 };
+ struct tf_sram_mgr_alloc_parms aparms = { 0 };
+ struct tbl_rm_db *tbl_db;
+ void *tbl_db_ptr = NULL;
+ void *sram_handle = NULL;
+
+ TF_CHECK_PARMS2(tfp, parms);
+
+ /* Retrieve the session information */
+ rc = tf_session_get(tfp, &tfs, &dev);
+ if (rc)
+ return rc;
+
+ rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get tbl_db from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
+
+ rc = tf_session_get_sram_db(tfp, &sram_handle);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get sram_handle from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ iparms.rm_db = tbl_db->tbl_db[parms->dir];
+ iparms.dir = parms->dir;
+ iparms.tbl_type = parms->type;
+
+ rc = tf_tbl_sram_get_info(&iparms);
+
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get SRAM info %s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type));
+ return rc;
+ }
+
+ aparms.dir = parms->dir;
+ aparms.bank_id = iparms.bank_id;
+ aparms.slice_size = iparms.slice_size;
+ aparms.sram_offset = &idx;
+ aparms.tbl_type = parms->type;
+ aparms.rm_db = tbl_db->tbl_db[parms->dir];
+
+ rc = tf_sram_mgr_alloc(sram_handle, &aparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to allocate SRAM table:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type));
+ return rc;
+ }
+ *parms->idx = idx;
+
+#if (DBG_SRAM == 1)
+ {
+ struct tf_sram_mgr_dump_parms dparms;
+
+ dparms.dir = parms->dir;
+ dparms.bank_id = iparms.bank_id;
+ dparms.slice_size = iparms.slice_size;
+
+ rc = tf_sram_mgr_dump(sram_handle, &dparms);
+ }
+#endif
+
+ return rc;
+}
+
+int
+tf_tbl_sram_free(struct tf *tfp __rte_unused,
+ struct tf_tbl_free_parms *parms)
+{
+ int rc;
+ struct tf_session *tfs;
+ struct tf_dev_info *dev;
+ struct tbl_rm_db *tbl_db;
+ void *tbl_db_ptr = NULL;
+ struct tf_tbl_sram_get_info_parms iparms = { 0 };
+ struct tf_sram_mgr_free_parms fparms = { 0 };
+ struct tf_sram_mgr_is_allocated_parms aparms = { 0 };
+ bool allocated = false;
+ void *sram_handle = NULL;
+
+ TF_CHECK_PARMS2(tfp, parms);
+
+ /* Retrieve the session information */
+ rc = tf_session_get(tfp, &tfs, &dev);
+ if (rc)
+ return rc;
+
+ rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get em_ext_db from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
+
+ rc = tf_session_get_sram_db(tfp, &sram_handle);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get sram_handle from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ iparms.rm_db = tbl_db->tbl_db[parms->dir];
+ iparms.dir = parms->dir;
+ iparms.tbl_type = parms->type;
+
+ rc = tf_tbl_sram_get_info(&iparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get table info:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type));
+ return rc;
+ }
+
+#if (DBG_SRAM == 1)
+ {
+ struct tf_sram_mgr_dump_parms dparms;
+
+ printf("%s: %s: %s\n", tf_dir_2_str(parms->dir),
+ tf_sram_slice_2_str(iparms.slice_size),
+ tf_sram_bank_2_str(iparms.bank_id));
+
+ dparms.dir = parms->dir;
+ dparms.bank_id = iparms.bank_id;
+ dparms.slice_size = iparms.slice_size;
+
+ rc = tf_sram_mgr_dump(sram_handle, &dparms);
+ }
+#endif
+
+ aparms.sram_offset = parms->idx;
+ aparms.slice_size = iparms.slice_size;
+ aparms.bank_id = iparms.bank_id;
+ aparms.dir = parms->dir;
+ aparms.is_allocated = &allocated;
+
+ rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
+ if (rc || !allocated) {
+ TFP_DRV_LOG(ERR,
+ "%s: Free of invalid entry:%s idx(%d):(%s)\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->idx,
+ strerror(-rc));
+ rc = -ENOMEM;
+ return rc;
+ }
+
+ fparms.rm_db = tbl_db->tbl_db[parms->dir];
+ fparms.tbl_type = parms->type;
+ fparms.sram_offset = parms->idx;
+ fparms.slice_size = iparms.slice_size;
+ fparms.bank_id = iparms.bank_id;
+ fparms.dir = parms->dir;
+#if (STATS_CLEAR_ON_READ_SUPPORT == 0)
+ fparms.tfp = tfp;
+#endif
+ rc = tf_sram_mgr_free(sram_handle, &fparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to free entry:%s idx(%d)\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->idx);
+ return rc;
+ }
+
+
+#if (DBG_SRAM == 1)
+ {
+ struct tf_sram_mgr_dump_parms dparms;
+
+ printf("%s: %s: %s\n", tf_dir_2_str(parms->dir),
+ tf_sram_slice_2_str(iparms.slice_size),
+ tf_sram_bank_2_str(iparms.bank_id));
+
+ dparms.dir = parms->dir;
+ dparms.bank_id = iparms.bank_id;
+ dparms.slice_size = iparms.slice_size;
+
+ rc = tf_sram_mgr_dump(sram_handle, &dparms);
+ }
+#endif
+ return rc;
+}
+
+int
+tf_tbl_sram_set(struct tf *tfp,
+ struct tf_tbl_set_parms *parms)
+{
+ int rc;
+ bool allocated = 0;
+ uint16_t hcapi_type;
+ struct tf_rm_get_hcapi_parms hparms = { 0 };
+ struct tf_session *tfs;
+ struct tf_dev_info *dev;
+ struct tbl_rm_db *tbl_db;
+ void *tbl_db_ptr = NULL;
+ struct tf_tbl_sram_get_info_parms iparms = { 0 };
+ struct tf_sram_mgr_is_allocated_parms aparms = { 0 };
+ void *sram_handle = NULL;
+
+
+ TF_CHECK_PARMS3(tfp, parms, parms->data);
+
+ /* Retrieve the session information */
+ rc = tf_session_get(tfp, &tfs, &dev);
+ if (rc)
+ return rc;
+
+ rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get em_ext_db from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
+
+ rc = tf_session_get_sram_db(tfp, &sram_handle);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get sram_handle from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ iparms.rm_db = tbl_db->tbl_db[parms->dir];
+ iparms.dir = parms->dir;
+ iparms.tbl_type = parms->type;
+
+ rc = tf_tbl_sram_get_info(&iparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get table info:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type));
+ return rc;
+ }
+
+ aparms.sram_offset = parms->idx;
+ aparms.slice_size = iparms.slice_size;
+ aparms.bank_id = iparms.bank_id;
+ aparms.dir = parms->dir;
+ aparms.is_allocated = &allocated;
+ rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
+ if (rc || !allocated) {
+ TFP_DRV_LOG(ERR,
+ "%s: Entry not allocated:%s idx(%d):(%s)\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->idx,
+ strerror(-rc));
+ rc = -ENOMEM;
+ return rc;
+ }
+
+ /* Set the entry */
+ hparms.rm_db = tbl_db->tbl_db[parms->dir];
+ hparms.subtype = parms->type;
+ hparms.hcapi_type = &hcapi_type;
+ rc = tf_rm_get_hcapi_type(&hparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Failed type lookup, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ strerror(-rc));
+ return rc;
+ }
+
+ rc = tf_msg_set_tbl_entry(tfp,
+ parms->dir,
+ hcapi_type,
+ parms->data_sz_in_bytes,
+ parms->data,
+ parms->idx);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Set failed, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ strerror(-rc));
+ return rc;
+ }
+ return rc;
+}
+
+int
+tf_tbl_sram_get(struct tf *tfp,
+ struct tf_tbl_get_parms *parms)
+{
+ int rc;
+ uint16_t hcapi_type;
+ bool allocated = 0;
+ struct tf_rm_get_hcapi_parms hparms = { 0 };
+ struct tf_session *tfs;
+ struct tf_dev_info *dev;
+ struct tbl_rm_db *tbl_db;
+ void *tbl_db_ptr = NULL;
+ struct tf_tbl_sram_get_info_parms iparms = { 0 };
+ struct tf_sram_mgr_is_allocated_parms aparms = { 0 };
+ void *sram_handle = NULL;
+
+ TF_CHECK_PARMS3(tfp, parms, parms->data);
+
+ /* Retrieve the session information */
+ rc = tf_session_get(tfp, &tfs, &dev);
+ if (rc)
+ return rc;
+
+ rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get em_ext_db from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
+
+ rc = tf_session_get_sram_db(tfp, &sram_handle);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get sram_handle from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ iparms.rm_db = tbl_db->tbl_db[parms->dir];
+ iparms.dir = parms->dir;
+ iparms.tbl_type = parms->type;
+
+ rc = tf_tbl_sram_get_info(&iparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get table info:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type));
+ return rc;
+ }
+
+ aparms.sram_offset = parms->idx;
+ aparms.slice_size = iparms.slice_size;
+ aparms.bank_id = iparms.bank_id;
+ aparms.dir = parms->dir;
+ aparms.is_allocated = &allocated;
+
+ rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
+ if (rc || !allocated) {
+ TFP_DRV_LOG(ERR,
+ "%s: Entry not allocated:%s idx(%d):(%s)\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->idx,
+ strerror(-rc));
+ rc = -ENOMEM;
+ return rc;
+ }
+
+ /* Get the entry */
+ hparms.rm_db = tbl_db->tbl_db[parms->dir];
+ hparms.subtype = parms->type;
+ hparms.hcapi_type = &hcapi_type;
+ rc = tf_rm_get_hcapi_type(&hparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Failed type lookup, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ strerror(-rc));
+ return rc;
+ }
+
+ /* Get the entry */
+ rc = tf_msg_get_tbl_entry(tfp,
+ parms->dir,
+ hcapi_type,
+ parms->data_sz_in_bytes,
+ parms->data,
+ parms->idx);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Get failed, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ strerror(-rc));
+ return rc;
+ }
+ return rc;
+}
+
+int
+tf_tbl_sram_bulk_get(struct tf *tfp,
+ struct tf_tbl_get_bulk_parms *parms)
+{
+ int rc;
+ uint16_t hcapi_type;
+ struct tf_rm_get_hcapi_parms hparms = { 0 };
+ struct tf_tbl_sram_get_info_parms iparms = { 0 };
+ struct tf_session *tfs;
+ struct tf_dev_info *dev;
+ struct tbl_rm_db *tbl_db;
+ void *tbl_db_ptr = NULL;
+ uint16_t idx;
+ struct tf_sram_mgr_is_allocated_parms aparms = { 0 };
+ bool allocated = false;
+ void *sram_handle = NULL;
+
+ TF_CHECK_PARMS2(tfp, parms);
+
+ /* Retrieve the session information */
+ rc = tf_session_get(tfp, &tfs, &dev);
+ if (rc)
+ return rc;
+
+ rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get em_ext_db from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
+
+ rc = tf_session_get_sram_db(tfp, &sram_handle);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get sram_handle from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ iparms.rm_db = tbl_db->tbl_db[parms->dir];
+ iparms.dir = parms->dir;
+ iparms.tbl_type = parms->type;
+
+ rc = tf_tbl_sram_get_info(&iparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get table info:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type));
+ return rc;
+ }
+
+ /* Validate the start offset and the end offset is allocated
+ * This API is only used for statistics. 8 Byte entry allocation
+ * is used to verify
+ */
+ aparms.sram_offset = parms->starting_idx;
+ aparms.slice_size = iparms.slice_size;
+ aparms.bank_id = iparms.bank_id;
+ aparms.dir = parms->dir;
+ aparms.is_allocated = &allocated;
+ rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
+ if (rc || !allocated) {
+ TFP_DRV_LOG(ERR,
+ "%s: Entry not allocated:%s starting_idx(%d):(%s)\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->starting_idx,
+ strerror(-rc));
+ rc = -ENOMEM;
+ return rc;
+ }
+ idx = parms->starting_idx + parms->num_entries - 1;
+ aparms.sram_offset = idx;
+ rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
+ if (rc || !allocated) {
+ TFP_DRV_LOG(ERR,
+ "%s: Entry not allocated:%s last_idx(%d):(%s)\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ idx,
+ strerror(-rc));
+ rc = -ENOMEM;
+ return rc;
+ }
+
+ hparms.rm_db = tbl_db->tbl_db[parms->dir];
+ hparms.subtype = parms->type;
+ hparms.hcapi_type = &hcapi_type;
+ rc = tf_rm_get_hcapi_type(&hparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Failed type lookup, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ strerror(-rc));
+ return rc;
+ }
+
+ /* Get the entries */
+ rc = tf_msg_bulk_get_tbl_entry(tfp,
+ parms->dir,
+ hcapi_type,
+ parms->starting_idx,
+ parms->num_entries,
+ parms->entry_sz_in_bytes,
+ parms->physical_mem_addr);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Bulk get failed, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ strerror(-rc));
+ }
+ return rc;
+}
diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.h b/drivers/net/bnxt/tf_core/tf_tbl_sram.h
new file mode 100644
index 0000000000..32001e34a9
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.h
@@ -0,0 +1,154 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019-2021 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef TF_TBL_SRAM_H_
+#define TF_TBL_SRAM_H_
+
+#include "tf_core.h"
+#include "stack.h"
+
+
+/**
+ * The SRAM Table module provides processing of managed SRAM types.
+ */
+
+
+/**
+ * @page tblsram SRAM Table
+ *
+ * @ref tf_tbl_sram_bind
+ *
+ * @ref tf_tbl_sram_unbind
+ *
+ * @ref tf_tbl_sram_alloc
+ *
+ * @ref tf_tbl_sram_free
+ *
+ * @ref tf_tbl_sram_set
+ *
+ * @ref tf_tbl_sram_get
+ *
+ * @ref tf_tbl_sram_bulk_get
+ */
+
+/**
+ * Initializes the Table module with the requested DBs. Must be
+ * invoked as the first thing before any of the access functions.
+ *
+ * [in] tfp
+ * Pointer to TF handle, used for HCAPI communication
+ *
+ * [in] parms
+ * Pointer to Table configuration parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_tbl_sram_bind(struct tf *tfp);
+
+/**
+ * Cleans up the private DBs and releases all the data.
+ *
+ * [in] tfp
+ * Pointer to TF handle, used for HCAPI communication
+ *
+ * [in] parms
+ * Pointer to parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_tbl_sram_unbind(struct tf *tfp);
+
+/**
+ * Allocates the requested table type from the internal RM DB.
+ *
+ * [in] tfp
+ * Pointer to TF handle, used for HCAPI communication
+ *
+ * [in] parms
+ * Pointer to Table allocation parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_tbl_sram_alloc(struct tf *tfp,
+ struct tf_tbl_alloc_parms *parms);
+
+/**
+ * Free's the requested table type and returns it to the DB. If shadow
+ * DB is enabled its searched first and if found the element refcount
+ * is decremented. If refcount goes to 0 then its returned to the
+ * table type DB.
+ *
+ * [in] tfp
+ * Pointer to TF handle, used for HCAPI communication
+ *
+ * [in] parms
+ * Pointer to Table free parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_tbl_sram_free(struct tf *tfp,
+ struct tf_tbl_free_parms *parms);
+
+
+/**
+ * Configures the requested element by sending a firmware request which
+ * then installs it into the device internal structures.
+ *
+ * [in] tfp
+ * Pointer to TF handle, used for HCAPI communication
+ *
+ * [in] parms
+ * Pointer to Table set parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_tbl_sram_set(struct tf *tfp,
+ struct tf_tbl_set_parms *parms);
+
+/**
+ * Retrieves the requested element by sending a firmware request to get
+ * the element.
+ *
+ * [in] tfp
+ * Pointer to TF handle, used for HCAPI communication
+ *
+ * [in] parms
+ * Pointer to Table get parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_tbl_sram_get(struct tf *tfp,
+ struct tf_tbl_get_parms *parms);
+
+/**
+ * Retrieves bulk block of elements by sending a firmware request to
+ * get the elements.
+ *
+ * [in] tfp
+ * Pointer to TF handle, used for HCAPI communication
+ *
+ * [in] parms
+ * Pointer to Table get bulk parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_tbl_sram_bulk_get(struct tf *tfp,
+ struct tf_tbl_get_bulk_parms *parms);
+
+#endif /* TF_TBL_SRAM_H */
diff --git a/drivers/net/bnxt/tf_core/tf_tcam.c b/drivers/net/bnxt/tf_core/tf_tcam.c
index 45206c5992..806af3070a 100644
--- a/drivers/net/bnxt/tf_core/tf_tcam.c
+++ b/drivers/net/bnxt/tf_core/tf_tcam.c
@@ -43,7 +43,7 @@ tf_tcam_bind(struct tf *tfp,
struct tf_shadow_tcam_free_db_parms fshadow;
struct tf_shadow_tcam_cfg_parms shadow_cfg;
struct tf_shadow_tcam_create_db_parms shadow_cdb;
- uint16_t num_slices = 1;
+ uint16_t num_slices = parms->wc_num_slices;
struct tf_session *tfs;
struct tf_dev_info *dev;
struct tcam_rm_db *tcam_db;
@@ -61,7 +61,7 @@ tf_tcam_bind(struct tf *tfp,
if (rc)
return rc;
- if (dev->ops->tf_dev_get_tcam_slice_info == NULL) {
+ if (dev->ops->tf_dev_set_tcam_slice_info == NULL) {
rc = -EOPNOTSUPP;
TFP_DRV_LOG(ERR,
"Operation not supported, rc:%s\n",
@@ -69,10 +69,8 @@ tf_tcam_bind(struct tf *tfp,
return rc;
}
- rc = dev->ops->tf_dev_get_tcam_slice_info(tfp,
- TF_TCAM_TBL_TYPE_WC_TCAM,
- 0,
- &num_slices);
+ rc = dev->ops->tf_dev_set_tcam_slice_info(tfp,
+ num_slices);
if (rc)
return rc;
diff --git a/drivers/net/bnxt/tf_core/tf_tcam.h b/drivers/net/bnxt/tf_core/tf_tcam.h
index bed17af6ae..b1e7a92b0b 100644
--- a/drivers/net/bnxt/tf_core/tf_tcam.h
+++ b/drivers/net/bnxt/tf_core/tf_tcam.h
@@ -12,6 +12,9 @@
* The TCAM module provides processing of Internal TCAM types.
*/
+/* Number of slices per row for WC TCAM */
+extern uint16_t g_wc_num_slices_per_row;
+
/**
* TCAM configuration parameters
*/
@@ -36,6 +39,10 @@ struct tf_tcam_cfg_parms {
* Session resource allocations
*/
struct tf_session_resources *resources;
+ /**
+ * WC number of slices per row.
+ */
+ enum tf_wc_num_slice wc_num_slices;
};
/**
diff --git a/drivers/net/bnxt/tf_core/tf_tcam_shared.c b/drivers/net/bnxt/tf_core/tf_tcam_shared.c
index 83b6fbd5fb..c120c6f577 100644
--- a/drivers/net/bnxt/tf_core/tf_tcam_shared.c
+++ b/drivers/net/bnxt/tf_core/tf_tcam_shared.c
@@ -279,18 +279,6 @@ tf_tcam_shared_bind(struct tf *tfp,
if (rc)
return rc;
- rc = tf_tcam_shared_get_slices(tfp,
- dev,
- &num_slices);
- if (rc)
- return rc;
-
- if (num_slices > 1) {
- TFP_DRV_LOG(ERR,
- "Only single slice supported\n");
- return -EOPNOTSUPP;
- }
-
tf_tcam_shared_create_db(&tcam_shared_wc);
@@ -330,6 +318,18 @@ tf_tcam_shared_bind(struct tf *tfp,
tf_session_set_tcam_shared_db(tfp, (void *)tcam_shared_wc);
}
+
+ rc = tf_tcam_shared_get_slices(tfp,
+ dev,
+ &num_slices);
+ if (rc)
+ return rc;
+
+ if (num_slices > 1) {
+ TFP_DRV_LOG(ERR,
+ "Only single slice supported\n");
+ return -EOPNOTSUPP;
+ }
}
done:
return rc;
@@ -972,9 +972,9 @@ tf_tcam_shared_move_entry(struct tf *tfp,
sparms.idx = dphy_idx;
sparms.key = gparms.key;
sparms.mask = gparms.mask;
- sparms.key_size = gparms.key_size;
+ sparms.key_size = key_sz_bytes;
sparms.result = gparms.result;
- sparms.result_size = gparms.result_size;
+ sparms.result_size = remap_sz_bytes;
rc = tf_msg_tcam_entry_set(tfp, dev, &sparms);
if (rc) {
diff --git a/drivers/net/bnxt/tf_core/tf_util.c b/drivers/net/bnxt/tf_core/tf_util.c
index d100399d0a..c1b9be0755 100644
--- a/drivers/net/bnxt/tf_core/tf_util.c
+++ b/drivers/net/bnxt/tf_core/tf_util.c
@@ -76,6 +76,8 @@ tf_tbl_type_2_str(enum tf_tbl_type tbl_type)
switch (tbl_type) {
case TF_TBL_TYPE_FULL_ACT_RECORD:
return "Full Action record";
+ case TF_TBL_TYPE_COMPACT_ACT_RECORD:
+ return "Compact Action record";
case TF_TBL_TYPE_MCAST_GROUPS:
return "Multicast Groups";
case TF_TBL_TYPE_ACT_ENCAP_8B:
@@ -96,6 +98,14 @@ tf_tbl_type_2_str(enum tf_tbl_type tbl_type)
return "Stats 64B";
case TF_TBL_TYPE_ACT_MODIFY_IPV4:
return "Modify IPv4";
+ case TF_TBL_TYPE_ACT_MODIFY_8B:
+ return "Modify 8B";
+ case TF_TBL_TYPE_ACT_MODIFY_16B:
+ return "Modify 16B";
+ case TF_TBL_TYPE_ACT_MODIFY_32B:
+ return "Modify 32B";
+ case TF_TBL_TYPE_ACT_MODIFY_64B:
+ return "Modify 64B";
case TF_TBL_TYPE_METER_PROF:
return "Meter Profile";
case TF_TBL_TYPE_METER_INST:
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index dbf85e4eda..183bae66c5 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -384,6 +384,7 @@ ulp_ctx_shared_session_open(struct bnxt *bp,
size_t copy_nbytes;
uint32_t ulp_dev_id = BNXT_ULP_DEVICE_ID_LAST;
int32_t rc = 0;
+ uint8_t app_id;
/* only perform this if shared session is enabled. */
if (!bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx))
@@ -422,6 +423,12 @@ ulp_ctx_shared_session_open(struct bnxt *bp,
if (rc)
return rc;
+ rc = bnxt_ulp_cntxt_app_id_get(bp->ulp_ctx, &app_id);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Unable to get the app id from ulp.\n");
+ return -EINVAL;
+ }
+
rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &ulp_dev_id);
if (rc) {
BNXT_TF_DBG(ERR, "Unable to get device id from ulp.\n");
@@ -445,6 +452,10 @@ ulp_ctx_shared_session_open(struct bnxt *bp,
parms.shadow_copy = true;
parms.bp = bp;
+ if (app_id == 0 || app_id == 3)
+ parms.wc_num_slices = TF_WC_TCAM_2_SLICE_PER_ROW;
+ else
+ parms.wc_num_slices = TF_WC_TCAM_1_SLICE_PER_ROW;
/*
* Open the session here, but the collect the resources during the
@@ -516,6 +527,7 @@ ulp_ctx_session_open(struct bnxt *bp,
struct tf_open_session_parms params;
struct tf_session_resources *resources;
uint32_t ulp_dev_id = BNXT_ULP_DEVICE_ID_LAST;
+ uint8_t app_id;
memset(¶ms, 0, sizeof(params));
@@ -529,6 +541,12 @@ ulp_ctx_session_open(struct bnxt *bp,
params.shadow_copy = true;
+ rc = bnxt_ulp_cntxt_app_id_get(bp->ulp_ctx, &app_id);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Unable to get the app id from ulp.\n");
+ return -EINVAL;
+ }
+
rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &ulp_dev_id);
if (rc) {
BNXT_TF_DBG(ERR, "Unable to get device id from ulp.\n");
@@ -556,6 +574,11 @@ ulp_ctx_session_open(struct bnxt *bp,
return rc;
params.bp = bp;
+ if (app_id == 0 || app_id == 3)
+ params.wc_num_slices = TF_WC_TCAM_2_SLICE_PER_ROW;
+ else
+ params.wc_num_slices = TF_WC_TCAM_1_SLICE_PER_ROW;
+
rc = tf_open_session(&bp->tfp, ¶ms);
if (rc) {
BNXT_TF_DBG(ERR, "Failed to open TF session - %s, rc = %d\n",
diff --git a/meson_options.txt b/meson_options.txt
index 0e92734c49..f686e6d92a 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -46,3 +46,5 @@ option('tests', type: 'boolean', value: true, description:
'build unit tests')
option('use_hpet', type: 'boolean', value: false, description:
'use HPET timer in EAL')
+option('bnxt_tf_wc_slices', type: 'integer', min: 1, max: 4, value: 2,
+ description: 'Number of slices per WC TCAM entry')
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* Re: [dpdk-dev] [PATCH v3 04/13] net/bnxt: add Thor SRAM mgr model
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 04/13] net/bnxt: add Thor SRAM mgr model Venkat Duvvuru
@ 2021-09-16 13:49 ` Ferruh Yigit
2021-09-16 14:01 ` Bruce Richardson
2021-09-16 16:29 ` Venkat Duvvuru
0 siblings, 2 replies; 83+ messages in thread
From: Ferruh Yigit @ 2021-09-16 13:49 UTC (permalink / raw)
To: Ajit Khaparde, Thomas Monjalon, Bruce Richardson
Cc: Farah Smith, Venkat Duvvuru, dev
On 9/11/2021 4:30 PM, Venkat Duvvuru wrote:
> diff --git a/meson_options.txt b/meson_options.txt
> index 0e92734c49..f686e6d92a 100644
> --- a/meson_options.txt
> +++ b/meson_options.txt
> @@ -46,3 +46,5 @@ option('tests', type: 'boolean', value: true, description:
> 'build unit tests')
> option('use_hpet', type: 'boolean', value: false, description:
> 'use HPET timer in EAL')
> +option('bnxt_tf_wc_slices', type: 'integer', min: 1, max: 4, value: 2,
> + description: 'Number of slices per WC TCAM entry')
> --
Are we sure to add a PMD specific meson option?
I believe if we let to go this way, soon the meson options can be as messy as
Makefile config options. @Thomas, @Bruce, what do you think?
^ permalink raw reply [flat|nested] 83+ messages in thread* Re: [dpdk-dev] [PATCH v3 04/13] net/bnxt: add Thor SRAM mgr model
2021-09-16 13:49 ` Ferruh Yigit
@ 2021-09-16 14:01 ` Bruce Richardson
2021-09-16 14:04 ` Thomas Monjalon
2021-09-16 16:29 ` Venkat Duvvuru
1 sibling, 1 reply; 83+ messages in thread
From: Bruce Richardson @ 2021-09-16 14:01 UTC (permalink / raw)
To: Ferruh Yigit
Cc: Ajit Khaparde, Thomas Monjalon, Farah Smith, Venkat Duvvuru, dev
On Thu, Sep 16, 2021 at 02:49:57PM +0100, Ferruh Yigit wrote:
> On 9/11/2021 4:30 PM, Venkat Duvvuru wrote:
> > diff --git a/meson_options.txt b/meson_options.txt
> > index 0e92734c49..f686e6d92a 100644
> > --- a/meson_options.txt
> > +++ b/meson_options.txt
> > @@ -46,3 +46,5 @@ option('tests', type: 'boolean', value: true, description:
> > 'build unit tests')
> > option('use_hpet', type: 'boolean', value: false, description:
> > 'use HPET timer in EAL')
> > +option('bnxt_tf_wc_slices', type: 'integer', min: 1, max: 4, value: 2,
> > + description: 'Number of slices per WC TCAM entry')
> > --
>
>
> Are we sure to add a PMD specific meson option?
>
> I believe if we let to go this way, soon the meson options can be as messy as
> Makefile config options. @Thomas, @Bruce, what do you think?
Completely agree. Can this be made a runtime option, perhaps passed in as a
devarg if necessary?
^ permalink raw reply [flat|nested] 83+ messages in thread* Re: [dpdk-dev] [PATCH v3 04/13] net/bnxt: add Thor SRAM mgr model
2021-09-16 14:01 ` Bruce Richardson
@ 2021-09-16 14:04 ` Thomas Monjalon
0 siblings, 0 replies; 83+ messages in thread
From: Thomas Monjalon @ 2021-09-16 14:04 UTC (permalink / raw)
To: Ferruh Yigit, Bruce Richardson
Cc: Ajit Khaparde, Farah Smith, Venkat Duvvuru, dev
16/09/2021 16:01, Bruce Richardson:
> On Thu, Sep 16, 2021 at 02:49:57PM +0100, Ferruh Yigit wrote:
> > On 9/11/2021 4:30 PM, Venkat Duvvuru wrote:
> > > diff --git a/meson_options.txt b/meson_options.txt
> > > index 0e92734c49..f686e6d92a 100644
> > > --- a/meson_options.txt
> > > +++ b/meson_options.txt
> > > @@ -46,3 +46,5 @@ option('tests', type: 'boolean', value: true, description:
> > > 'build unit tests')
> > > option('use_hpet', type: 'boolean', value: false, description:
> > > 'use HPET timer in EAL')
> > > +option('bnxt_tf_wc_slices', type: 'integer', min: 1, max: 4, value: 2,
> > > + description: 'Number of slices per WC TCAM entry')
> >
> >
> > Are we sure to add a PMD specific meson option?
> >
> > I believe if we let to go this way, soon the meson options can be as messy as
> > Makefile config options. @Thomas, @Bruce, what do you think?
>
> Completely agree. Can this be made a runtime option, perhaps passed in as a
> devarg if necessary?
+1
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [dpdk-dev] [PATCH v3 04/13] net/bnxt: add Thor SRAM mgr model
2021-09-16 13:49 ` Ferruh Yigit
2021-09-16 14:01 ` Bruce Richardson
@ 2021-09-16 16:29 ` Venkat Duvvuru
2021-09-16 16:30 ` Ferruh Yigit
1 sibling, 1 reply; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-16 16:29 UTC (permalink / raw)
To: Ferruh Yigit
Cc: Ajit Khaparde, Thomas Monjalon, Bruce Richardson, Farah Smith, dev
On Thu, Sep 16, 2021 at 7:20 PM Ferruh Yigit <ferruh.yigit@intel.com> wrote:
>
> On 9/11/2021 4:30 PM, Venkat Duvvuru wrote:
> > diff --git a/meson_options.txt b/meson_options.txt
> > index 0e92734c49..f686e6d92a 100644
> > --- a/meson_options.txt
> > +++ b/meson_options.txt
> > @@ -46,3 +46,5 @@ option('tests', type: 'boolean', value: true, description:
> > 'build unit tests')
> > option('use_hpet', type: 'boolean', value: false, description:
> > 'use HPET timer in EAL')
> > +option('bnxt_tf_wc_slices', type: 'integer', min: 1, max: 4, value: 2,
> > + description: 'Number of slices per WC TCAM entry')
> > --
>
>
> Are we sure to add a PMD specific meson option?
>
> I believe if we let to go this way, soon the meson options can be as messy as
> Makefile config options. @Thomas, @Bruce, what do you think?
Apologies for the confusion.
It is actually taken care of in the code and this meson_options.txt
change is not needed.
Will submit a patch to revert it.
--
This electronic communication and the information and any files transmitted
with it, or attached to it, are confidential and are intended solely for
the use of the individual or entity to whom it is addressed and may contain
information that is confidential, legally privileged, protected by privacy
laws, or otherwise restricted from disclosure to anyone else. If you are
not the intended recipient or the person responsible for delivering the
e-mail to the intended recipient, you are hereby notified that any use,
copying, distributing, dissemination, forwarding, printing, or copying of
this e-mail is strictly prohibited. If you received this e-mail in error,
please return the e-mail to the sender, delete it from your computer, and
destroy any printed copy of it.
^ permalink raw reply [flat|nested] 83+ messages in thread* Re: [dpdk-dev] [PATCH v3 04/13] net/bnxt: add Thor SRAM mgr model
2021-09-16 16:29 ` Venkat Duvvuru
@ 2021-09-16 16:30 ` Ferruh Yigit
0 siblings, 0 replies; 83+ messages in thread
From: Ferruh Yigit @ 2021-09-16 16:30 UTC (permalink / raw)
To: Venkat Duvvuru
Cc: Ajit Khaparde, Thomas Monjalon, Bruce Richardson, Farah Smith, dev
On 9/16/2021 5:29 PM, Venkat Duvvuru wrote:
> On Thu, Sep 16, 2021 at 7:20 PM Ferruh Yigit <ferruh.yigit@intel.com> wrote:
>>
>> On 9/11/2021 4:30 PM, Venkat Duvvuru wrote:
>>> diff --git a/meson_options.txt b/meson_options.txt
>>> index 0e92734c49..f686e6d92a 100644
>>> --- a/meson_options.txt
>>> +++ b/meson_options.txt
>>> @@ -46,3 +46,5 @@ option('tests', type: 'boolean', value: true, description:
>>> 'build unit tests')
>>> option('use_hpet', type: 'boolean', value: false, description:
>>> 'use HPET timer in EAL')
>>> +option('bnxt_tf_wc_slices', type: 'integer', min: 1, max: 4, value: 2,
>>> + description: 'Number of slices per WC TCAM entry')
>>> --
>>
>>
>> Are we sure to add a PMD specific meson option?
>>
>> I believe if we let to go this way, soon the meson options can be as messy as
>> Makefile config options. @Thomas, @Bruce, what do you think?
>
> Apologies for the confusion.
> It is actually taken care of in the code and this meson_options.txt
> change is not needed.
> Will submit a patch to revert it.
>
Great, thanks.
^ permalink raw reply [flat|nested] 83+ messages in thread
* [dpdk-dev] [PATCH v3 05/13] net/bnxt: add flow templates support for Thor
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 00/13] enhancements to host based flow table management Venkat Duvvuru
` (3 preceding siblings ...)
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 04/13] net/bnxt: add Thor SRAM mgr model Venkat Duvvuru
@ 2021-09-11 15:30 ` Venkat Duvvuru
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 06/13] net/bnxt: add support for tunnel offloads Venkat Duvvuru
` (9 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-11 15:30 UTC (permalink / raw)
To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Template adds non-VFR based support for testpmd with:
matches to include
- DMAC, SIP, DIP, Proto, Sport, Dport
- SIP, DIP, Proto, Sport, Dport
actions:
- count, drop
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
---
drivers/net/bnxt/tf_ulp/bnxt_tf_common.h | 6 +
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 36 +++---
drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 12 ++
.../bnxt/tf_ulp/generic_templates/meson.build | 17 ++-
.../ulp_template_db_thor_class.c | 1 -
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 122 +++++++++++++++++-
drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 26 +++-
drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c | 5 +
drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 111 +++++++++++++++-
drivers/net/bnxt/tf_ulp/ulp_matcher.c | 13 ++
drivers/net/bnxt/tf_ulp/ulp_port_db.c | 15 ++-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 9 +-
drivers/net/bnxt/tf_ulp/ulp_tun.c | 20 +++
drivers/net/bnxt/tf_ulp/ulp_utils.c | 8 +-
16 files changed, 356 insertions(+), 49 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
index f59da41e54..e0ebed3fed 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
@@ -13,6 +13,12 @@
#define BNXT_TF_DBG(lvl, fmt, args...) PMD_DRV_LOG(lvl, fmt, ## args)
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#define BNXT_TF_INF(fmt, args...) PMD_DRV_LOG(INFO, fmt, ## args)
+#else
+#define BNXT_TF_INF(fmt, args...)
+#endif
+
#define BNXT_ULP_EM_FLOWS 8192
#define BNXT_ULP_1M_FLOWS 1000000
#define BNXT_EEM_RX_GLOBAL_ID_MASK (BNXT_ULP_1M_FLOWS - 1)
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 183bae66c5..475c7a6cdf 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -698,6 +698,11 @@ ulp_eem_tbl_scope_init(struct bnxt *bp)
rc);
return rc;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+ BNXT_TF_DBG(DEBUG, "TableScope=0x%0x %d\n",
+ params.tbl_scope_id,
+ params.tbl_scope_id);
+#endif
rc = bnxt_ulp_cntxt_tbl_scope_id_set(bp->ulp_ctx, params.tbl_scope_id);
if (rc) {
BNXT_TF_DBG(ERR, "Unable to set table scope id\n");
@@ -825,6 +830,8 @@ ulp_ctx_init(struct bnxt *bp,
goto error_deinit;
}
+ /* TODO: For now we are overriding to APP:1 on this branch*/
+ bp->app_id = 1;
rc = bnxt_ulp_cntxt_app_id_set(bp->ulp_ctx, bp->app_id);
if (rc) {
BNXT_TF_DBG(ERR, "Unable to set app_id for ULP init.\n");
@@ -838,11 +845,6 @@ ulp_ctx_init(struct bnxt *bp,
goto error_deinit;
}
- if (devid == BNXT_ULP_DEVICE_ID_THOR) {
- ulp_data->ulp_flags &= ~BNXT_ULP_VF_REP_ENABLED;
- BNXT_TF_DBG(ERR, "Enabled non-VFR mode\n");
- }
-
/*
* Shared session must be created before first regular session but after
* the ulp_ctx is valid.
@@ -902,7 +904,7 @@ ulp_dparms_init(struct bnxt *bp, struct bnxt_ulp_context *ulp_ctx)
dparms->ext_flow_db_num_entries = bp->max_num_kflows * 1024;
/* GFID = 2 * num_flows */
dparms->mark_db_gfid_entries = dparms->ext_flow_db_num_entries * 2;
- BNXT_TF_DBG(DEBUG, "Set the number of flows = %"PRIu64"\n",
+ BNXT_TF_DBG(DEBUG, "Set the number of flows = %" PRIu64 "\n",
dparms->ext_flow_db_num_entries);
return 0;
@@ -1393,17 +1395,13 @@ bnxt_ulp_port_init(struct bnxt *bp)
uint32_t ulp_flags;
int32_t rc = 0;
+ if (!bp || !BNXT_TRUFLOW_EN(bp))
+ return rc;
+
if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
BNXT_TF_DBG(ERR,
"Skip ulp init for port: %d, not a TVF or PF\n",
- bp->eth_dev->data->port_id);
- return rc;
- }
-
- if (!BNXT_TRUFLOW_EN(bp)) {
- BNXT_TF_DBG(DEBUG,
- "Skip ulp init for port: %d, truflow is not enabled\n",
- bp->eth_dev->data->port_id);
+ bp->eth_dev->data->port_id);
return rc;
}
@@ -1524,6 +1522,9 @@ bnxt_ulp_port_deinit(struct bnxt *bp)
struct rte_pci_device *pci_dev;
struct rte_pci_addr *pci_addr;
+ if (!BNXT_TRUFLOW_EN(bp))
+ return;
+
if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
BNXT_TF_DBG(ERR,
"Skip ULP deinit port:%d, not a TVF or PF\n",
@@ -1531,13 +1532,6 @@ bnxt_ulp_port_deinit(struct bnxt *bp)
return;
}
- if (!BNXT_TRUFLOW_EN(bp)) {
- BNXT_TF_DBG(DEBUG,
- "Skip ULP deinit for port:%d, truflow is not enabled\n",
- bp->eth_dev->data->port_id);
- return;
- }
-
if (!bp->ulp_ctx) {
BNXT_TF_DBG(DEBUG, "ulp ctx already de-allocated\n");
return;
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
index 19e9dba356..238b1d9657 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
@@ -13,6 +13,9 @@
#include "ulp_port_db.h"
#include "ulp_ha_mgr.h"
#include <rte_malloc.h>
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#include "ulp_template_debug_proto.h"
+#endif
static int32_t
bnxt_ulp_flow_validate_args(const struct rte_flow_attr *attr,
@@ -222,6 +225,15 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
else if (ret == BNXT_TF_RC_FID)
goto return_fid;
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER
+ /* Dump the rte flow pattern */
+ ulp_parser_hdr_info_dump(¶ms);
+ /* Dump the rte flow action */
+ ulp_parser_act_info_dump(¶ms);
+#endif
+#endif
+
ret = ulp_matcher_pattern_match(¶ms, ¶ms.class_id);
if (ret != BNXT_TF_RC_SUCCESS)
goto free_fid;
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/meson.build b/drivers/net/bnxt/tf_ulp/generic_templates/meson.build
index b1e7b8cc32..16b27a2e24 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/meson.build
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/meson.build
@@ -2,12 +2,15 @@
# Copyright(c) 2018 Intel Corporation
# Copyright(c) 2020 Broadcom
+#Include the folder for headers
includes += include_directories('.')
+
+#Add the source files
sources += files(
- 'ulp_template_db_class.c',
- 'ulp_template_db_act.c',
- 'ulp_template_db_tbl.c',
- 'ulp_template_db_wh_plus_act.c',
- 'ulp_template_db_wh_plus_class.c',
- 'ulp_template_db_thor_act.c',
- 'ulp_template_db_thor_class.c')
+ 'ulp_template_db_class.c',
+ 'ulp_template_db_act.c',
+ 'ulp_template_db_tbl.c',
+ 'ulp_template_db_wh_plus_act.c',
+ 'ulp_template_db_wh_plus_class.c',
+ 'ulp_template_db_thor_act.c',
+ 'ulp_template_db_thor_class.c')
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
index 83f6152700..e342f340d9 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
@@ -6104,4 +6104,3 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.ident_bit_pos = 29
}
};
-
diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
index 13f71ed83b..22c51976ac 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
@@ -35,7 +35,7 @@ ulp_fc_mgr_shadow_mem_alloc(struct hw_fc_mem_info *parms, int size)
rte_mem_lock_page(parms->mem_va);
parms->mem_pa = (void *)(uintptr_t)rte_mem_virt2phy(parms->mem_va);
- if (parms->mem_pa == (void *)(uintptr_t)RTE_BAD_IOVA) {
+ if (parms->mem_pa == (void *)RTE_BAD_IOVA) {
BNXT_TF_DBG(ERR, "Allocate failed mem_pa\n");
return -ENOMEM;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
index ab6013f0e3..747a360aa0 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
@@ -116,7 +116,7 @@ ulp_flow_db_resource_func_get(struct ulp_fdb_resource_info *res_info)
func = (((res_info->nxt_resource_idx & ULP_FLOW_DB_RES_FUNC_MASK) >>
ULP_FLOW_DB_RES_FUNC_BITS) << ULP_FLOW_DB_RES_FUNC_UPPER);
- /* The resource func is split into upper and lower */
+ /* The reource func is split into upper and lower */
if (func & ULP_FLOW_DB_RES_FUNC_NEED_LOWER)
return (func | res_info->resource_func_lower);
return func;
@@ -654,6 +654,9 @@ ulp_flow_db_fid_alloc(struct bnxt_ulp_context *ulp_ctxt,
if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR)
ulp_flow_db_func_id_set(flow_db, *fid, func_id);
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+ BNXT_TF_DBG(ERR, "flow_id = %u:%u allocated\n", flow_type, *fid);
+#endif
/* return success */
return 0;
}
@@ -714,7 +717,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt,
if (params->critical_resource && fid_resource->resource_em_handle) {
BNXT_TF_DBG(DEBUG, "Ignore multiple critical resources\n");
- /* Ignore the multiple critical resources */
+ /* Ignore the multiple criticial resources */
params->critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO;
}
@@ -766,7 +769,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt,
* flow_type [in] Specify it is regular or default flow
* fid [in] The index to the flow entry
* params [in/out] The contents to be copied into params.
- * Only the critical_resource needs to be set by the caller.
+ * Onlythe critical_resource needs to be set by the caller.
*
* Returns 0 on success and negative on failure.
*/
@@ -937,6 +940,9 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt,
ulp_clear_tun_inner_entry(tun_tbl, fid);
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+ BNXT_TF_DBG(ERR, "flow_id = %u:%u freed\n", flow_type, fid);
+#endif
/* all good, return success */
return 0;
}
@@ -1921,3 +1927,113 @@ void ulp_flow_db_shared_session_set(struct ulp_flow_db_res_params *res,
if (res && (shared & BNXT_ULP_SHARED_SESSION_YES))
res->fdb_flags |= ULP_FDB_FLAG_SHARED_SESSION;
}
+
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+/*
+ * Dump the entry details
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ *
+ * returns none
+ */
+static void ulp_flow_db_res_dump(struct ulp_fdb_resource_info *r,
+ uint32_t *nxt_res)
+{
+ uint8_t res_func = ulp_flow_db_resource_func_get(r);
+
+ BNXT_TF_DBG(DEBUG, "Resource func = %x, nxt_resource_idx = %x\n",
+ res_func, (ULP_FLOW_DB_RES_NXT_MASK & r->nxt_resource_idx));
+ if (res_func == BNXT_ULP_RESOURCE_FUNC_EM_TABLE)
+ BNXT_TF_DBG(DEBUG, "EM Handle = 0x%016" PRIX64 "\n",
+ r->resource_em_handle);
+ else
+ BNXT_TF_DBG(DEBUG, "Handle = 0x%08x\n", r->resource_hndl);
+
+ *nxt_res = 0;
+ ULP_FLOW_DB_RES_NXT_SET(*nxt_res,
+ r->nxt_resource_idx);
+}
+
+/*
+ * Dump the flow entry details
+ *
+ * flow_db [in] Ptr to flow db
+ * fid [in] flow id
+ *
+ * returns none
+ */
+void
+ulp_flow_db_debug_fid_dump(struct bnxt_ulp_flow_db *flow_db, uint32_t fid)
+{
+ struct ulp_fdb_resource_info *r;
+ struct bnxt_ulp_flow_tbl *flow_tbl;
+ uint32_t nxt_res = 0;
+ uint32_t def_flag = 0, reg_flag = 0;
+
+ flow_tbl = &flow_db->flow_tbl;
+ if (ulp_flow_db_active_flows_bit_is_set(flow_db,
+ BNXT_ULP_FDB_TYPE_REGULAR, fid))
+ reg_flag = 1;
+ if (ulp_flow_db_active_flows_bit_is_set(flow_db,
+ BNXT_ULP_FDB_TYPE_DEFAULT, fid))
+ def_flag = 1;
+
+ if (reg_flag && def_flag)
+ BNXT_TF_DBG(DEBUG, "RID = %u\n", fid);
+ else if (reg_flag)
+ BNXT_TF_DBG(DEBUG, "Regular fid = %u and func id = %u\n",
+ fid, flow_db->func_id_tbl[fid]);
+ else if (def_flag)
+ BNXT_TF_DBG(DEBUG, "Default fid = %u\n", fid);
+ else
+ return;
+ /* iterate the resource */
+ nxt_res = fid;
+ do {
+ r = &flow_tbl->flow_resources[nxt_res];
+ ulp_flow_db_res_dump(r, &nxt_res);
+ } while (nxt_res);
+}
+
+/*
+ * Dump the flow database entry details
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ * flow_id [in] if zero then all fids are dumped.
+ *
+ * returns none
+ */
+int32_t ulp_flow_db_debug_dump(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t flow_id)
+{
+ struct bnxt_ulp_flow_db *flow_db;
+ struct bnxt_ulp_flow_tbl *flow_tbl;
+ uint32_t fid;
+
+ if (!ulp_ctxt || !ulp_ctxt->cfg_data) {
+ BNXT_TF_DBG(ERR, "Invalid Arguments\n");
+ return -EINVAL;
+ }
+ flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
+ if (!flow_db) {
+ BNXT_TF_DBG(ERR, "Invalid Arguments\n");
+ return -EINVAL;
+ }
+
+ flow_tbl = &flow_db->flow_tbl;
+ if (flow_id) {
+ ulp_flow_db_debug_fid_dump(flow_db, flow_id);
+ return 0;
+ }
+
+ BNXT_TF_DBG(DEBUG, "Dump flows = %u:%u\n",
+ flow_tbl->num_flows,
+ flow_tbl->num_resources);
+ BNXT_TF_DBG(DEBUG, "Head_index = %u, Tail_index = %u\n",
+ flow_tbl->head_index, flow_tbl->tail_index);
+ for (fid = 1; fid < flow_tbl->num_flows; fid++)
+ ulp_flow_db_debug_fid_dump(flow_db, fid);
+ BNXT_TF_DBG(DEBUG, "Done.\n");
+ return 0;
+}
+#endif
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
index 67afca8872..0ddfa6f66d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
@@ -18,7 +18,7 @@
/*
* Structure for the flow database resource information
- * The below structure is based on the below partitions
+ * The below structure is based on the below paritions
* nxt_resource_idx = dir[31],resource_func_upper[30:28],nxt_resource_idx[27:0]
* If resource_func is EM_TBL then use resource_em_handle.
* Else the other part of the union is used and
@@ -417,4 +417,28 @@ ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt);
void ulp_flow_db_shared_session_set(struct ulp_flow_db_res_params *res,
enum bnxt_ulp_shared_session shared);
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+/*
+ * Dump the flow entry details
+ *
+ * flow_db [in] Ptr to flow db
+ * fid [in] flow id
+ *
+ * returns none
+ */
+void
+ulp_flow_db_debug_fid_dump(struct bnxt_ulp_flow_db *flow_db, uint32_t fid);
+
+/*
+ * Dump the flow database entry details
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ * flow_id [in] if zero then all fids are dumped.
+ *
+ * returns none
+ */
+int32_t ulp_flow_db_debug_dump(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t flow_id);
+#endif
+
#endif /* _ULP_FLOW_DB_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
index 3c1af0b007..c6b2b1675d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
@@ -10,6 +10,11 @@
#include "ulp_mapper.h"
#include "ulp_flow_db.h"
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#include "ulp_template_debug_proto.h"
+#include "ulp_tf_debug.h"
+#endif
+
/* Retrieve the generic table initialization parameters for the tbl_idx */
static struct bnxt_ulp_generic_tbl_params*
ulp_mapper_gen_tbl_params_get(uint32_t tbl_idx)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
index 5f5b5d639e..bc5627ec5b 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
@@ -185,7 +185,7 @@ ulp_ha_mgr_timer_cb(void *arg __rte_unused)
rc = ulp_ha_mgr_state_get(ulp_ctx, &curr_state);
if (rc) {
/*
- * This shouldn't happen, if it does, reset the timer
+ * This shouldn't happen, if it does, resetart the timer
* and try again next time.
*/
BNXT_TF_DBG(ERR, "Failed(%d) to get state.\n",
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index f3a60cc880..7fc3767b33 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -22,6 +22,11 @@
#include "ulp_ha_mgr.h"
#include "bnxt_tf_pmd_shim.h"
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#include "ulp_template_debug_proto.h"
+#include "ulp_tf_debug.h"
+#endif
+
static uint8_t mapper_fld_zeros[16] = { 0 };
static uint8_t mapper_fld_ones[16] = {
@@ -156,6 +161,13 @@ ulp_mapper_resource_ident_allocate(struct bnxt_ulp_context *ulp_ctx,
tf_free_identifier(tfp, &fparms);
return rc;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ BNXT_TF_DBG(DEBUG, "Allocated Glb Res Ident [%s][%d][%d] = 0x%04x\n",
+ tf_dir_2_str(iparms.dir),
+ glb_res->glb_regfile_index, iparms.ident_type, iparms.id);
+#endif
+#endif
return rc;
}
@@ -216,6 +228,13 @@ ulp_mapper_resource_index_tbl_alloc(struct bnxt_ulp_context *ulp_ctx,
tf_free_tbl_entry(tfp, &free_parms);
return rc;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ BNXT_TF_DBG(DEBUG, "Allocated Glb Res Index [%s][%d][%d] = 0x%04x\n",
+ tf_dir_2_str(aparms.dir),
+ glb_res->glb_regfile_index, aparms.type, aparms.idx);
+#endif
+#endif
return rc;
}
@@ -784,6 +803,9 @@ ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms,
tf_ident_2_str(iparms.ident_type));
return rc;
}
+ BNXT_TF_INF("Alloc ident %s:%s.success.\n",
+ tf_dir_2_str(iparms.dir),
+ tf_ident_2_str(iparms.ident_type));
id = (uint64_t)tfp_cpu_to_be_64(iparms.id);
if (ulp_regfile_write(parms->regfile, idx, id)) {
@@ -813,6 +835,11 @@ ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms,
} else {
*val = iparms.id;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_ident_field_dump("Ident", ident, tbl, iparms.id);
+#endif
+#endif
return 0;
error:
@@ -877,6 +904,10 @@ ulp_mapper_ident_extract(struct bnxt_ulp_mapper_parms *parms,
sparms.search_id);
return rc;
}
+ BNXT_TF_INF("Search ident %s:%s:%x.success.\n",
+ tf_dir_2_str(sparms.dir),
+ tf_tbl_type_2_str(sparms.ident_type),
+ sparms.search_id);
/* Write it to the regfile */
id = (uint64_t)tfp_cpu_to_be_64(sparms.search_id);
@@ -904,6 +935,11 @@ ulp_mapper_ident_extract(struct bnxt_ulp_mapper_parms *parms,
goto error;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_ident_field_dump("Ident", ident, tbl, sparms.search_id);
+#endif
+#endif
return 0;
error:
@@ -996,7 +1032,7 @@ ulp_mapper_field_src_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
idx = tfp_be_to_cpu_16(idx);
- if (idx >= BNXT_ULP_CF_IDX_LAST || bytelen > sizeof(uint64_t)) {
+ if (idx >= BNXT_ULP_CF_IDX_LAST || bytelen > sizeof(uint32_t)) {
BNXT_TF_DBG(ERR, "comp field [%d] read oob %d\n", idx,
bytelen);
return -EINVAL;
@@ -1448,7 +1484,16 @@ ulp_mapper_field_opc_process(struct bnxt_ulp_mapper_parms *parms,
break;
}
- return rc;
+ if (!rc) {
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ if (fld->field_src1 != BNXT_ULP_FIELD_SRC_ZERO)
+ ulp_mapper_field_dump(name, fld, blob, write_idx, val,
+ val_len);
+#endif
+#endif
+ return rc;
+ }
error:
BNXT_TF_DBG(ERR, "Error in %s:%s process %u:%u\n", name,
fld->description, (val) ? write_idx : 0, val_len);
@@ -1500,8 +1545,15 @@ ulp_mapper_tbl_result_build(struct bnxt_ulp_mapper_parms *parms,
}
/* if encap bit swap is enabled perform the bit swap */
- if (parms->device_params->encap_byte_swap && encap_flds)
+ if (parms->device_params->encap_byte_swap && encap_flds) {
ulp_blob_perform_encap_swap(data);
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ BNXT_TF_DBG(INFO, "Dump after encap swap\n");
+ ulp_mapper_blob_dump(data);
+#endif
+#endif
+ }
return rc;
}
@@ -1725,6 +1777,9 @@ ulp_mapper_tcam_tbl_entry_write(struct bnxt_ulp_mapper_parms *parms,
tf_dir_2_str(sparms.dir), sparms.idx);
return -EIO;
}
+ BNXT_TF_INF("tcam[%s][%s][%x] write success.\n",
+ tf_tcam_tbl_2_str(sparms.tcam_tbl_type),
+ tf_dir_2_str(sparms.dir), sparms.idx);
/* Mark action */
rc = ulp_mapper_mark_act_ptr_process(parms, tbl);
@@ -1733,6 +1788,11 @@ ulp_mapper_tcam_tbl_entry_write(struct bnxt_ulp_mapper_parms *parms,
return rc;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_tcam_entry_dump("TCAM", idx, tbl, key, mask, data);
+#endif
+#endif
return rc;
}
@@ -1838,6 +1898,12 @@ static void ulp_mapper_wc_tcam_tbl_post_process(struct ulp_blob *blob)
{
ulp_blob_perform_64B_word_swap(blob);
ulp_blob_perform_64B_byte_swap(blob);
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ BNXT_TF_DBG(INFO, "Dump after wc tcam post process\n");
+ ulp_mapper_blob_dump(blob);
+#endif
+#endif
}
static int32_t
@@ -2134,6 +2200,11 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
BNXT_TF_DBG(ERR, "Failed to build the result blob\n");
return rc;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_result_dump("EM Result", tbl, &data);
+#endif
+#endif
if (dparms->dynamic_pad_en) {
uint32_t abits = dparms->em_blk_align_bits;
@@ -2148,6 +2219,11 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
ulp_blob_pad_align(&data, abits);
ulp_blob_perform_byte_reverse(&data, ULP_BITS_2_BYTE(abits));
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_result_dump("EM Merged Result", tbl, &data);
+#endif
+#endif
}
/* do the transpose for the internal EM keys */
@@ -2160,6 +2236,11 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
}
tmplen = ulp_blob_data_len_get(&key);
ulp_blob_perform_byte_reverse(&key, ULP_BITS_2_BYTE(tmplen));
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_result_dump("EM Key Transpose", tbl, &key);
+#endif
+#endif
}
rc = bnxt_ulp_cntxt_tbl_scope_id_get(parms->ulp_ctx,
@@ -2190,6 +2271,12 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return rc;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_em_dump("EM", &key, &data, &iparms);
+ /* tf_dump_tables(tfp, iparms.tbl_scope_id); */
+#endif
+#endif
/* Mark action process */
if (mtype == BNXT_ULP_FLOW_MEM_TYPE_EXT &&
tbl->resource_type == TF_MEM_EXTERNAL)
@@ -2479,6 +2566,9 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
sparms.idx, rc);
goto error;
}
+ BNXT_TF_INF("Index table[%s][%s][%x] write successful.\n",
+ tf_tbl_type_2_str(sparms.type),
+ tf_dir_2_str(sparms.dir), sparms.idx);
/* Calculate action record size */
if (tbl->resource_type == TF_TBL_TYPE_EXT) {
@@ -2635,6 +2725,10 @@ ulp_mapper_if_tbl_process(struct bnxt_ulp_mapper_parms *parms,
iftbl_params.idx, rc);
return rc;
}
+ BNXT_TF_INF("Set table[%s][%s][%x] success.\n",
+ tf_if_tbl_2_str(iftbl_params.type),
+ tf_dir_2_str(iftbl_params.dir),
+ iftbl_params.idx);
/*
* TBD: Need to look at the need to store idx in flow db for restore
@@ -2697,6 +2791,12 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms,
/* The_key is a byte array convert it to a search index */
cache_key = ulp_blob_data_get(&key, &tmplen);
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ BNXT_TF_DBG(DEBUG, "The gen_tbl[%u] key\n", tbl_idx);
+ ulp_mapper_blob_dump(&key);
+#endif
+#endif
/* get the generic table */
gen_tbl_list = &parms->mapper_data->gen_tbl_list[tbl_idx];
@@ -3495,6 +3595,11 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid)
for (tbl_idx = 0; tbl_idx < num_tbls && cond_goto;) {
tbl = &tbls[tbl_idx];
cond_goto = tbl->execute_info.cond_true_goto;
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_table_dump(tbl, tbl_idx);
+#endif
+#endif
/* Process the conditional func code opcodes */
if (ulp_mapper_func_info_process(parms, tbl)) {
BNXT_TF_DBG(ERR, "Failed to process cond update\n");
diff --git a/drivers/net/bnxt/tf_ulp/ulp_matcher.c b/drivers/net/bnxt/tf_ulp/ulp_matcher.c
index 67fa61fc7c..e06d8f6287 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_matcher.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_matcher.c
@@ -6,6 +6,10 @@
#include "ulp_matcher.h"
#include "ulp_utils.h"
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#include "ulp_template_debug_proto.h"
+#endif
+
/* Utility function to calculate the class matcher hash */
static uint32_t
ulp_matcher_class_hash_calculate(uint64_t hi_sig, uint64_t lo_sig)
@@ -95,6 +99,11 @@ ulp_matcher_pattern_match(struct ulp_rte_parser_params *params,
error:
BNXT_TF_DBG(DEBUG, "Did not find any matching template\n");
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+ BNXT_TF_DBG(DEBUG, "class_hid:0x%x, Hdr:%" PRIX64 " Fld:%" PRIX64 "\n",
+ class_hid, params->hdr_bitmap.bits,
+ params->fld_bitmap.bits);
+#endif
*class_id = 0;
return BNXT_TF_RC_ERROR;
}
@@ -142,6 +151,10 @@ ulp_matcher_action_match(struct ulp_rte_parser_params *params,
error:
BNXT_TF_DBG(DEBUG, "Did not find any matching action template\n");
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+ BNXT_TF_DBG(DEBUG, "act_hid:0x%x, Hdr:%" PRIX64 "\n",
+ act_hid, params->act_bitmap.bits);
+#endif
*act_id = 0;
return BNXT_TF_RC_ERROR;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.c b/drivers/net/bnxt/tf_ulp/ulp_port_db.c
index 4045473097..7d9865b3e3 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_port_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.c
@@ -7,9 +7,13 @@
#include "bnxt.h"
#include "bnxt_vnic.h"
#include "bnxt_tf_common.h"
+#include "bnxt_tf_pmd_shim.h"
#include "ulp_port_db.h"
#include "tfp.h"
-#include "bnxt_tf_pmd_shim.h"
+
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#include "ulp_tf_debug.h"
+#endif
static uint32_t
ulp_port_db_allocate_ifindex(struct bnxt_ulp_port_db *port_db)
@@ -151,12 +155,12 @@ int32_t ulp_port_db_dev_port_intf_update(struct bnxt_ulp_context *ulp_ctxt,
intf->type = bnxt_pmd_get_interface_type(port_id);
intf->drv_func_id = bnxt_pmd_get_fw_func_id(port_id,
- BNXT_ULP_INTF_TYPE_INVALID);
+ BNXT_ULP_INTF_TYPE_INVALID);
func = &port_db->ulp_func_id_tbl[intf->drv_func_id];
if (!func->func_valid) {
func->func_svif = bnxt_pmd_get_svif(port_id, true,
- BNXT_ULP_INTF_TYPE_INVALID);
+ BNXT_ULP_INTF_TYPE_INVALID);
func->func_spif = bnxt_pmd_get_phy_port_id(port_id);
func->func_parif =
bnxt_pmd_get_parif(port_id, BNXT_ULP_INTF_TYPE_INVALID);
@@ -202,6 +206,11 @@ int32_t ulp_port_db_dev_port_intf_update(struct bnxt_ulp_context *ulp_ctxt,
port_data->port_vport = bnxt_pmd_get_vport(port_id);
port_data->port_valid = true;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PORT
+ ulp_port_db_dump(port_db, intf, port_id);
+#endif
+#endif
return 0;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index 5fd52b8f36..79b9957781 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -8,6 +8,7 @@
#include "ulp_template_struct.h"
#include "bnxt_ulp.h"
#include "bnxt_tf_common.h"
+#include "bnxt_tf_pmd_shim.h"
#include "ulp_rte_parser.h"
#include "ulp_matcher.h"
#include "ulp_utils.h"
@@ -855,7 +856,7 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
BNXT_ULP_HDR_BIT_II_VLAN);
inner_flag = 1;
} else {
- BNXT_TF_DBG(ERR, "Error Parsing:Vlan hdr found without eth\n");
+ BNXT_TF_DBG(ERR, "Error Parsing:Vlan hdr found withtout eth\n");
return BNXT_TF_RC_ERROR;
}
/* Update the field protocol hdr bitmap */
@@ -1135,8 +1136,8 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
ulp_rte_prsr_fld_mask(params, &idx, size, &ver_spec, &ver_mask,
ULP_PRSR_ACT_DEFAULT);
/*
- * The TC and flow label field are ignored since OVS is setting
- * it for match and it is not supported.
+ * The TC and flow label field are ignored since OVS is
+ * setting it for match and it is not supported.
* This is a work around and
* shall be addressed in the future.
*/
@@ -2138,7 +2139,7 @@ ulp_rte_vf_act_handler(const struct rte_flow_action *action_item,
return BNXT_TF_RC_PARSE_ERR;
}
- bp = bnxt_get_bp(params->port_id);
+ bp = bnxt_pmd_get_bp(params->port_id);
if (bp == NULL) {
BNXT_TF_DBG(ERR, "Invalid bp\n");
return BNXT_TF_RC_ERROR;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.c b/drivers/net/bnxt/tf_ulp/ulp_tun.c
index cb8530d791..a1dd5b902c 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_tun.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_tun.c
@@ -3,6 +3,8 @@
* All rights reserved.
*/
+#include <sys/queue.h>
+
#include <rte_malloc.h>
#include "ulp_tun.h"
@@ -29,6 +31,15 @@ ulp_install_outer_tun_flow(struct ulp_rte_parser_params *params,
ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F1);
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER
+ /* Dump the rte flow pattern */
+ ulp_parser_hdr_info_dump(params);
+ /* Dump the rte flow action */
+ ulp_parser_act_info_dump(params);
+#endif
+#endif
+
ret = ulp_matcher_pattern_match(params, ¶ms->class_id);
if (ret != BNXT_TF_RC_SUCCESS)
goto err;
@@ -146,6 +157,15 @@ ulp_post_process_cache_inner_tun_flow(struct ulp_rte_parser_params *params,
struct ulp_per_port_flow_info *flow_info;
int ret;
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER
+ /* Dump the rte flow pattern */
+ ulp_parser_hdr_info_dump(params);
+ /* Dump the rte flow action */
+ ulp_parser_act_info_dump(params);
+#endif
+#endif
+
ret = ulp_matcher_pattern_match(params, ¶ms->class_id);
if (ret != BNXT_TF_RC_SUCCESS)
return BNXT_TF_RC_ERROR;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c
index bafb539c8d..1649e157f2 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c
@@ -62,7 +62,7 @@ ulp_regfile_read(struct ulp_regfile *regfile,
* data [in] The value is written into this variable. It is going to be in the
* same byte order as it was written.
*
- * size [in] The size in bytes of the value being written into this
+ * size [in] The size in bytes of the value beingritten into this
* variable.
*
* returns 0 on success
@@ -295,7 +295,7 @@ ulp_blob_push(struct ulp_blob *blob,
datalen,
data);
if (!rc) {
- BNXT_TF_DBG(ERR, "Failed to write blob\n");
+ BNXT_TF_DBG(ERR, "Failed ro write blob\n");
return 0;
}
blob->write_idx += datalen;
@@ -355,7 +355,7 @@ ulp_blob_insert(struct ulp_blob *blob, uint32_t offset,
datalen,
data);
if (!rc) {
- BNXT_TF_DBG(ERR, "Failed to write blob\n");
+ BNXT_TF_DBG(ERR, "Failed ro write blob\n");
return 0;
}
/* copy the previously stored data */
@@ -409,7 +409,7 @@ ulp_blob_push_64(struct ulp_blob *blob,
*
* data [in] 32-bit value to be added to the blob.
*
- * datalen [in] The number of bits to be added to the blob.
+ * datalen [in] The number of bits to be added ot the blob.
*
* The offset of the data is updated after each push of data.
* NULL returned on error, pointer pushed value otherwise.
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v3 06/13] net/bnxt: add support for tunnel offloads
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 00/13] enhancements to host based flow table management Venkat Duvvuru
` (4 preceding siblings ...)
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 05/13] net/bnxt: add flow templates support for Thor Venkat Duvvuru
@ 2021-09-11 15:30 ` Venkat Duvvuru
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 07/13] net/bnxt: add support for dynamic encap action Venkat Duvvuru
` (8 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-11 15:30 UTC (permalink / raw)
To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Added support for tunnel offloads, this includes the support for
VXLAN decap action where two flows indicate tunnel offload rule. The
first flow indicate the tunnel properties and second flow indicates the
inner packet structure. The templates are updated to support this
feature.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com>
---
drivers/net/bnxt/tf_ulp/bnxt_tf_common.h | 4 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 12 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 20 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 212 +-
.../generic_templates/ulp_template_db_act.c | 2 +-
.../generic_templates/ulp_template_db_class.c | 8541 +++++++++++-----
.../generic_templates/ulp_template_db_enum.h | 210 +-
.../generic_templates/ulp_template_db_field.h | 654 +-
.../generic_templates/ulp_template_db_tbl.c | 645 +-
.../ulp_template_db_thor_class.c | 110 +-
.../ulp_template_db_wh_plus_act.c | 2 +-
.../ulp_template_db_wh_plus_class.c | 8577 +++++++++++------
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 46 +-
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h | 8 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 562 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 44 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 52 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.h | 6 +-
drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c | 31 +
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 134 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 10 +-
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 10 +-
drivers/net/bnxt/tf_ulp/ulp_tun.c | 541 +-
drivers/net/bnxt/tf_ulp/ulp_tun.h | 89 +-
24 files changed, 13810 insertions(+), 6712 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
index e0ebed3fed..6c4bcd2d90 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
@@ -37,9 +37,7 @@
enum bnxt_tf_rc {
BNXT_TF_RC_PARSE_ERR = -2,
BNXT_TF_RC_ERROR = -1,
- BNXT_TF_RC_SUCCESS = 0,
- BNXT_TF_RC_NORMAL = 1,
- BNXT_TF_RC_FID = 2,
+ BNXT_TF_RC_SUCCESS = 0
};
/* eth IPv4 Type */
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 475c7a6cdf..dfafd9ff5b 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -860,8 +860,6 @@ ulp_ctx_init(struct bnxt *bp,
if (rc)
goto error_deinit;
- ulp_tun_tbl_init(ulp_data->tun_tbl);
-
bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, &bp->tfp);
return rc;
@@ -2064,3 +2062,13 @@ bnxt_ulp_cntxt_entry_release(void)
{
rte_spinlock_unlock(&bnxt_ulp_ctxt_lock);
}
+
+/* Function to get the app tunnel details from the ulp context. */
+struct bnxt_flow_app_tun_ent *
+bnxt_ulp_cntxt_ptr2_app_tun_list_get(struct bnxt_ulp_context *ulp)
+{
+ if (!ulp || !ulp->cfg_data)
+ return NULL;
+
+ return ulp->cfg_data->app_tun;
+}
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
index 082ca501b6..006df9cbc5 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
@@ -47,6 +47,18 @@ enum bnxt_ulp_flow_mem_type {
BNXT_ULP_FLOW_MEM_TYPE_LAST = 3
};
+enum bnxt_rte_flow_item_type {
+ BNXT_RTE_FLOW_ITEM_TYPE_END = (uint32_t)INT_MIN,
+ BNXT_RTE_FLOW_ITEM_TYPE_VXLAN_DECAP,
+ BNXT_RTE_FLOW_ITEM_TYPE_LAST
+};
+
+enum bnxt_rte_flow_action_type {
+ BNXT_RTE_FLOW_ACTION_TYPE_END = (uint32_t)INT_MIN,
+ BNXT_RTE_FLOW_ACTION_TYPE_VXLAN_DECAP,
+ BNXT_RTE_FLOW_ACTION_TYPE_LAST
+};
+
struct bnxt_ulp_df_rule_info {
uint32_t def_port_flow_id;
uint8_t valid;
@@ -79,6 +91,7 @@ struct bnxt_ulp_data {
bool accum_stats;
uint8_t app_id;
uint8_t num_shared_clients;
+ struct bnxt_flow_app_tun_ent app_tun[BNXT_ULP_MAX_TUN_CACHE_ENTRIES];
};
struct bnxt_ulp_context {
@@ -258,9 +271,6 @@ bnxt_ulp_cntxt_acquire_fdb_lock(struct bnxt_ulp_context *ulp_ctx);
void
bnxt_ulp_cntxt_release_fdb_lock(struct bnxt_ulp_context *ulp_ctx);
-int32_t
-ulp_post_process_tun_flow(struct ulp_rte_parser_params *params);
-
struct bnxt_ulp_glb_resource_info *
bnxt_ulp_app_glb_resource_info_list_get(uint32_t *num_entries);
@@ -301,4 +311,8 @@ bnxt_ulp_cntxt_entry_release(void);
uint8_t
bnxt_ulp_cntxt_num_shared_clients_get(struct bnxt_ulp_context *ulp_ctx);
+
+struct bnxt_flow_app_tun_ent *
+bnxt_ulp_cntxt_ptr2_app_tun_list_get(struct bnxt_ulp_context *ulp);
+
#endif /* _BNXT_ULP_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
index 238b1d9657..3daf5942e8 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
@@ -12,6 +12,7 @@
#include "ulp_fc_mgr.h"
#include "ulp_port_db.h"
#include "ulp_ha_mgr.h"
+#include "ulp_tun.h"
#include <rte_malloc.h>
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
#include "ulp_template_debug_proto.h"
@@ -101,12 +102,13 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms,
mapper_cparms->act_prop = ¶ms->act_prop;
mapper_cparms->flow_id = params->fid;
mapper_cparms->parent_flow = params->parent_flow;
- mapper_cparms->parent_fid = params->parent_fid;
+ mapper_cparms->child_flow = params->child_flow;
mapper_cparms->fld_bitmap = ¶ms->fld_bitmap;
mapper_cparms->flow_pattern_id = params->flow_pattern_id;
mapper_cparms->act_pattern_id = params->act_pattern_id;
mapper_cparms->app_id = params->app_id;
mapper_cparms->port_id = params->port_id;
+ mapper_cparms->tun_idx = params->tun_idx;
/* update the signature fields into the computed field list */
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_HDR_SIG_ID,
@@ -218,12 +220,14 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
params.func_id = func_id;
params.priority = attr->priority;
params.port_id = dev->data->port_id;
+
/* Perform the rte flow post process */
- ret = bnxt_ulp_rte_parser_post_process(¶ms);
+ bnxt_ulp_rte_parser_post_process(¶ms);
+
+ /* do the tunnel offload process if any */
+ ret = ulp_tunnel_offload_process(¶ms);
if (ret == BNXT_TF_RC_ERROR)
goto free_fid;
- else if (ret == BNXT_TF_RC_FID)
- goto return_fid;
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER
@@ -249,7 +253,6 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
if (ret)
goto free_fid;
-return_fid:
bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
flow_id = (struct rte_flow *)((uintptr_t)fid);
@@ -314,11 +317,12 @@ bnxt_ulp_flow_validate(struct rte_eth_dev *dev,
goto parse_error;
/* Perform the rte flow post process */
- ret = bnxt_ulp_rte_parser_post_process(¶ms);
+ bnxt_ulp_rte_parser_post_process(¶ms);
+
+ /* do the tunnel offload process if any */
+ ret = ulp_tunnel_offload_process(¶ms);
if (ret == BNXT_TF_RC_ERROR)
goto parse_error;
- else if (ret == BNXT_TF_RC_FID)
- return 0;
ret = ulp_matcher_pattern_match(¶ms, &class_id);
@@ -475,11 +479,201 @@ bnxt_ulp_flow_query(struct rte_eth_dev *eth_dev,
return rc;
}
+/* Tunnel offload Apis */
+#define BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS 1
+
+static int
+bnxt_ulp_tunnel_decap_set(struct rte_eth_dev *eth_dev,
+ struct rte_flow_tunnel *tunnel,
+ struct rte_flow_action **pmd_actions,
+ uint32_t *num_of_actions,
+ struct rte_flow_error *error)
+{
+ struct bnxt_ulp_context *ulp_ctx;
+ struct bnxt_flow_app_tun_ent *tun_entry;
+ int32_t rc = 0;
+
+ ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev);
+ if (ulp_ctx == NULL) {
+ BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
+ "ULP context uninitialized");
+ return -EINVAL;
+ }
+
+ if (tunnel == NULL) {
+ BNXT_TF_DBG(ERR, "No tunnel specified\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "no tunnel specified");
+ return -EINVAL;
+ }
+
+ if (tunnel->type != RTE_FLOW_ITEM_TYPE_VXLAN) {
+ BNXT_TF_DBG(ERR, "Tunnel type unsupported\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "tunnel type unsupported");
+ return -EINVAL;
+ }
+
+ rc = ulp_app_tun_search_entry(ulp_ctx, tunnel, &tun_entry);
+ if (rc < 0) {
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "tunnel decap set failed");
+ return -EINVAL;
+ }
+
+ rc = ulp_app_tun_entry_set_decap_action(tun_entry);
+ if (rc < 0) {
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "tunnel decap set failed");
+ return -EINVAL;
+ }
+
+ *pmd_actions = &tun_entry->action;
+ *num_of_actions = BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS;
+ return 0;
+}
+
+static int
+bnxt_ulp_tunnel_match(struct rte_eth_dev *eth_dev,
+ struct rte_flow_tunnel *tunnel,
+ struct rte_flow_item **pmd_items,
+ uint32_t *num_of_items,
+ struct rte_flow_error *error)
+{
+ struct bnxt_ulp_context *ulp_ctx;
+ struct bnxt_flow_app_tun_ent *tun_entry;
+ int32_t rc = 0;
+
+ ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev);
+ if (ulp_ctx == NULL) {
+ BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
+ "ULP context uninitialized");
+ return -EINVAL;
+ }
+
+ if (tunnel == NULL) {
+ BNXT_TF_DBG(ERR, "No tunnel specified\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
+ "no tunnel specified");
+ return -EINVAL;
+ }
+
+ if (tunnel->type != RTE_FLOW_ITEM_TYPE_VXLAN) {
+ BNXT_TF_DBG(ERR, "Tunnel type unsupported\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
+ "tunnel type unsupported");
+ return -EINVAL;
+ }
+
+ rc = ulp_app_tun_search_entry(ulp_ctx, tunnel, &tun_entry);
+ if (rc < 0) {
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "tunnel match set failed");
+ return -EINVAL;
+ }
+
+ rc = ulp_app_tun_entry_set_decap_item(tun_entry);
+ if (rc < 0) {
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "tunnel match set failed");
+ return -EINVAL;
+ }
+
+ *pmd_items = &tun_entry->item;
+ *num_of_items = BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS;
+ return 0;
+}
+
+static int
+bnxt_ulp_tunnel_decap_release(struct rte_eth_dev *eth_dev,
+ struct rte_flow_action *pmd_actions,
+ uint32_t num_actions,
+ struct rte_flow_error *error)
+{
+ struct bnxt_ulp_context *ulp_ctx;
+ struct bnxt_flow_app_tun_ent *tun_entry;
+ const struct rte_flow_action *action_item = pmd_actions;
+
+ ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev);
+ if (ulp_ctx == NULL) {
+ BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
+ "ULP context uninitialized");
+ return -EINVAL;
+ }
+ if (num_actions != BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS) {
+ BNXT_TF_DBG(ERR, "num actions is invalid\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "num actions is invalid");
+ return -EINVAL;
+ }
+ while (action_item && action_item->type != RTE_FLOW_ACTION_TYPE_END) {
+ if (action_item->type == (typeof(tun_entry->action.type))
+ BNXT_RTE_FLOW_ACTION_TYPE_VXLAN_DECAP) {
+ tun_entry = ulp_app_tun_match_entry(ulp_ctx,
+ action_item->conf);
+ ulp_app_tun_entry_delete(tun_entry);
+ }
+ action_item++;
+ }
+ return 0;
+}
+
+static int
+bnxt_ulp_tunnel_item_release(struct rte_eth_dev *eth_dev,
+ struct rte_flow_item *pmd_items,
+ uint32_t num_items,
+ struct rte_flow_error *error)
+{
+ struct bnxt_ulp_context *ulp_ctx;
+ struct bnxt_flow_app_tun_ent *tun_entry;
+
+ ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev);
+ if (ulp_ctx == NULL) {
+ BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
+ "ULP context uninitialized");
+ return -EINVAL;
+ }
+ if (num_items != BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS) {
+ BNXT_TF_DBG(ERR, "num items is invalid\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "num items is invalid");
+ return -EINVAL;
+ }
+
+ tun_entry = ulp_app_tun_match_entry(ulp_ctx, pmd_items->spec);
+ ulp_app_tun_entry_delete(tun_entry);
+ return 0;
+}
+
const struct rte_flow_ops bnxt_ulp_rte_flow_ops = {
.validate = bnxt_ulp_flow_validate,
.create = bnxt_ulp_flow_create,
.destroy = bnxt_ulp_flow_destroy,
.flush = bnxt_ulp_flow_flush,
.query = bnxt_ulp_flow_query,
- .isolate = NULL
+ .isolate = NULL,
+ /* Tunnel offload callbacks */
+ .tunnel_decap_set = bnxt_ulp_tunnel_decap_set,
+ .tunnel_match = bnxt_ulp_tunnel_match,
+ .tunnel_action_decap_release = bnxt_ulp_tunnel_decap_release,
+ .tunnel_item_release = bnxt_ulp_tunnel_item_release,
+ .get_restore_info = NULL
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c
index e18f314856..0da6070d7d 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Wed Mar 17 11:31:19 2021 */
+/* date: Mon May 17 15:30:41 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
index 9c419f6a15..f74687acfa 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Wed Mar 17 11:31:19 2021 */
+/* date: Thu May 20 11:56:39 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -360,348 +360,510 @@ uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {
[BNXT_ULP_CLASS_HID_15db] = 342,
[BNXT_ULP_CLASS_HID_1151] = 343,
[BNXT_ULP_CLASS_HID_315d] = 344,
- [BNXT_ULP_CLASS_HID_34c6] = 345,
- [BNXT_ULP_CLASS_HID_0c22] = 346,
- [BNXT_ULP_CLASS_HID_1cbe] = 347,
- [BNXT_ULP_CLASS_HID_179a] = 348,
- [BNXT_ULP_CLASS_HID_59be] = 349,
- [BNXT_ULP_CLASS_HID_515a] = 350,
- [BNXT_ULP_CLASS_HID_1c72] = 351,
- [BNXT_ULP_CLASS_HID_171e] = 352,
- [BNXT_ULP_CLASS_HID_19c8] = 353,
- [BNXT_ULP_CLASS_HID_112c] = 354,
- [BNXT_ULP_CLASS_HID_4d68] = 355,
- [BNXT_ULP_CLASS_HID_444c] = 356,
- [BNXT_ULP_CLASS_HID_0e8c] = 357,
- [BNXT_ULP_CLASS_HID_09e0] = 358,
- [BNXT_ULP_CLASS_HID_1af0] = 359,
- [BNXT_ULP_CLASS_HID_15d4] = 360,
- [BNXT_ULP_CLASS_HID_1dd0] = 361,
- [BNXT_ULP_CLASS_HID_14f4] = 362,
- [BNXT_ULP_CLASS_HID_70b0] = 363,
- [BNXT_ULP_CLASS_HID_4854] = 364,
- [BNXT_ULP_CLASS_HID_3dd4] = 365,
- [BNXT_ULP_CLASS_HID_34f8] = 366,
- [BNXT_ULP_CLASS_HID_09e8] = 367,
- [BNXT_ULP_CLASS_HID_008c] = 368,
- [BNXT_ULP_CLASS_HID_34e6] = 369,
- [BNXT_ULP_CLASS_HID_0c02] = 370,
- [BNXT_ULP_CLASS_HID_1c9e] = 371,
- [BNXT_ULP_CLASS_HID_17ba] = 372,
- [BNXT_ULP_CLASS_HID_429e] = 373,
- [BNXT_ULP_CLASS_HID_5dba] = 374,
- [BNXT_ULP_CLASS_HID_2a16] = 375,
- [BNXT_ULP_CLASS_HID_2532] = 376,
- [BNXT_ULP_CLASS_HID_2da2] = 377,
- [BNXT_ULP_CLASS_HID_24fe] = 378,
- [BNXT_ULP_CLASS_HID_355a] = 379,
- [BNXT_ULP_CLASS_HID_0c76] = 380,
- [BNXT_ULP_CLASS_HID_13e6] = 381,
- [BNXT_ULP_CLASS_HID_7276] = 382,
- [BNXT_ULP_CLASS_HID_42d2] = 383,
- [BNXT_ULP_CLASS_HID_5dee] = 384,
- [BNXT_ULP_CLASS_HID_59de] = 385,
- [BNXT_ULP_CLASS_HID_513a] = 386,
- [BNXT_ULP_CLASS_HID_1c12] = 387,
- [BNXT_ULP_CLASS_HID_177e] = 388,
- [BNXT_ULP_CLASS_HID_0e92] = 389,
- [BNXT_ULP_CLASS_HID_09fe] = 390,
- [BNXT_ULP_CLASS_HID_5c1a] = 391,
- [BNXT_ULP_CLASS_HID_5746] = 392,
- [BNXT_ULP_CLASS_HID_79da] = 393,
- [BNXT_ULP_CLASS_HID_7106] = 394,
- [BNXT_ULP_CLASS_HID_3c1e] = 395,
- [BNXT_ULP_CLASS_HID_377a] = 396,
- [BNXT_ULP_CLASS_HID_2e9e] = 397,
- [BNXT_ULP_CLASS_HID_29fa] = 398,
- [BNXT_ULP_CLASS_HID_14d2] = 399,
- [BNXT_ULP_CLASS_HID_7742] = 400,
- [BNXT_ULP_CLASS_HID_3706] = 401,
- [BNXT_ULP_CLASS_HID_0fe2] = 402,
- [BNXT_ULP_CLASS_HID_1f7e] = 403,
- [BNXT_ULP_CLASS_HID_145a] = 404,
- [BNXT_ULP_CLASS_HID_417e] = 405,
- [BNXT_ULP_CLASS_HID_5e5a] = 406,
- [BNXT_ULP_CLASS_HID_29f6] = 407,
- [BNXT_ULP_CLASS_HID_26d2] = 408,
- [BNXT_ULP_CLASS_HID_2e42] = 409,
- [BNXT_ULP_CLASS_HID_271e] = 410,
- [BNXT_ULP_CLASS_HID_36ba] = 411,
- [BNXT_ULP_CLASS_HID_0f96] = 412,
- [BNXT_ULP_CLASS_HID_1006] = 413,
- [BNXT_ULP_CLASS_HID_7196] = 414,
- [BNXT_ULP_CLASS_HID_4132] = 415,
- [BNXT_ULP_CLASS_HID_5e0e] = 416,
- [BNXT_ULP_CLASS_HID_59fe] = 417,
- [BNXT_ULP_CLASS_HID_511a] = 418,
- [BNXT_ULP_CLASS_HID_1c32] = 419,
- [BNXT_ULP_CLASS_HID_175e] = 420,
- [BNXT_ULP_CLASS_HID_0eb2] = 421,
- [BNXT_ULP_CLASS_HID_09de] = 422,
- [BNXT_ULP_CLASS_HID_5c3a] = 423,
- [BNXT_ULP_CLASS_HID_5766] = 424,
- [BNXT_ULP_CLASS_HID_79fa] = 425,
- [BNXT_ULP_CLASS_HID_7126] = 426,
- [BNXT_ULP_CLASS_HID_3c3e] = 427,
- [BNXT_ULP_CLASS_HID_375a] = 428,
- [BNXT_ULP_CLASS_HID_2ebe] = 429,
- [BNXT_ULP_CLASS_HID_29da] = 430,
- [BNXT_ULP_CLASS_HID_14f2] = 431,
- [BNXT_ULP_CLASS_HID_7762] = 432,
- [BNXT_ULP_CLASS_HID_19e8] = 433,
- [BNXT_ULP_CLASS_HID_110c] = 434,
- [BNXT_ULP_CLASS_HID_4d48] = 435,
- [BNXT_ULP_CLASS_HID_446c] = 436,
- [BNXT_ULP_CLASS_HID_0eac] = 437,
- [BNXT_ULP_CLASS_HID_09c0] = 438,
- [BNXT_ULP_CLASS_HID_1ad0] = 439,
- [BNXT_ULP_CLASS_HID_15f4] = 440,
- [BNXT_ULP_CLASS_HID_39ec] = 441,
- [BNXT_ULP_CLASS_HID_3100] = 442,
- [BNXT_ULP_CLASS_HID_0210] = 443,
- [BNXT_ULP_CLASS_HID_1d34] = 444,
- [BNXT_ULP_CLASS_HID_2ea0] = 445,
- [BNXT_ULP_CLASS_HID_29c4] = 446,
- [BNXT_ULP_CLASS_HID_3ad4] = 447,
- [BNXT_ULP_CLASS_HID_35e8] = 448,
- [BNXT_ULP_CLASS_HID_5d80] = 449,
- [BNXT_ULP_CLASS_HID_54a4] = 450,
- [BNXT_ULP_CLASS_HID_29b4] = 451,
- [BNXT_ULP_CLASS_HID_20c8] = 452,
- [BNXT_ULP_CLASS_HID_7244] = 453,
- [BNXT_ULP_CLASS_HID_4d98] = 454,
- [BNXT_ULP_CLASS_HID_5e68] = 455,
- [BNXT_ULP_CLASS_HID_598c] = 456,
- [BNXT_ULP_CLASS_HID_1248] = 457,
- [BNXT_ULP_CLASS_HID_74d8] = 458,
- [BNXT_ULP_CLASS_HID_49a8] = 459,
- [BNXT_ULP_CLASS_HID_40cc] = 460,
- [BNXT_ULP_CLASS_HID_0b0c] = 461,
- [BNXT_ULP_CLASS_HID_0220] = 462,
- [BNXT_ULP_CLASS_HID_1730] = 463,
- [BNXT_ULP_CLASS_HID_7980] = 464,
- [BNXT_ULP_CLASS_HID_1db0] = 465,
- [BNXT_ULP_CLASS_HID_1494] = 466,
- [BNXT_ULP_CLASS_HID_70d0] = 467,
- [BNXT_ULP_CLASS_HID_4834] = 468,
- [BNXT_ULP_CLASS_HID_3db4] = 469,
- [BNXT_ULP_CLASS_HID_3498] = 470,
- [BNXT_ULP_CLASS_HID_0988] = 471,
- [BNXT_ULP_CLASS_HID_00ec] = 472,
- [BNXT_ULP_CLASS_HID_3f44] = 473,
- [BNXT_ULP_CLASS_HID_36a8] = 474,
- [BNXT_ULP_CLASS_HID_0b58] = 475,
- [BNXT_ULP_CLASS_HID_02bc] = 476,
- [BNXT_ULP_CLASS_HID_5f48] = 477,
- [BNXT_ULP_CLASS_HID_56ac] = 478,
- [BNXT_ULP_CLASS_HID_2b5c] = 479,
- [BNXT_ULP_CLASS_HID_2280] = 480,
- [BNXT_ULP_CLASS_HID_4000] = 481,
- [BNXT_ULP_CLASS_HID_5b64] = 482,
- [BNXT_ULP_CLASS_HID_2c14] = 483,
- [BNXT_ULP_CLASS_HID_2778] = 484,
- [BNXT_ULP_CLASS_HID_18f8] = 485,
- [BNXT_ULP_CLASS_HID_13dc] = 486,
- [BNXT_ULP_CLASS_HID_4c18] = 487,
- [BNXT_ULP_CLASS_HID_477c] = 488,
- [BNXT_ULP_CLASS_HID_1a88] = 489,
- [BNXT_ULP_CLASS_HID_15ec] = 490,
- [BNXT_ULP_CLASS_HID_4e28] = 491,
- [BNXT_ULP_CLASS_HID_490c] = 492,
- [BNXT_ULP_CLASS_HID_3a8c] = 493,
- [BNXT_ULP_CLASS_HID_35f0] = 494,
- [BNXT_ULP_CLASS_HID_06e0] = 495,
- [BNXT_ULP_CLASS_HID_01c4] = 496,
- [BNXT_ULP_CLASS_HID_1a08] = 497,
- [BNXT_ULP_CLASS_HID_12ec] = 498,
- [BNXT_ULP_CLASS_HID_4ea8] = 499,
- [BNXT_ULP_CLASS_HID_478c] = 500,
- [BNXT_ULP_CLASS_HID_0d4c] = 501,
- [BNXT_ULP_CLASS_HID_0a20] = 502,
- [BNXT_ULP_CLASS_HID_1930] = 503,
- [BNXT_ULP_CLASS_HID_1614] = 504,
- [BNXT_ULP_CLASS_HID_3a0c] = 505,
- [BNXT_ULP_CLASS_HID_32e0] = 506,
- [BNXT_ULP_CLASS_HID_01f0] = 507,
- [BNXT_ULP_CLASS_HID_1ed4] = 508,
- [BNXT_ULP_CLASS_HID_2d40] = 509,
- [BNXT_ULP_CLASS_HID_2a24] = 510,
- [BNXT_ULP_CLASS_HID_3934] = 511,
- [BNXT_ULP_CLASS_HID_3608] = 512,
- [BNXT_ULP_CLASS_HID_5e60] = 513,
- [BNXT_ULP_CLASS_HID_5744] = 514,
- [BNXT_ULP_CLASS_HID_2a54] = 515,
- [BNXT_ULP_CLASS_HID_2328] = 516,
- [BNXT_ULP_CLASS_HID_71a4] = 517,
- [BNXT_ULP_CLASS_HID_4e78] = 518,
- [BNXT_ULP_CLASS_HID_5d88] = 519,
- [BNXT_ULP_CLASS_HID_5a6c] = 520,
- [BNXT_ULP_CLASS_HID_11a8] = 521,
- [BNXT_ULP_CLASS_HID_7738] = 522,
- [BNXT_ULP_CLASS_HID_4a48] = 523,
- [BNXT_ULP_CLASS_HID_432c] = 524,
- [BNXT_ULP_CLASS_HID_08ec] = 525,
- [BNXT_ULP_CLASS_HID_01c0] = 526,
- [BNXT_ULP_CLASS_HID_14d0] = 527,
- [BNXT_ULP_CLASS_HID_7a60] = 528,
- [BNXT_ULP_CLASS_HID_1d90] = 529,
- [BNXT_ULP_CLASS_HID_14b4] = 530,
- [BNXT_ULP_CLASS_HID_70f0] = 531,
- [BNXT_ULP_CLASS_HID_4814] = 532,
- [BNXT_ULP_CLASS_HID_3d94] = 533,
- [BNXT_ULP_CLASS_HID_34b8] = 534,
- [BNXT_ULP_CLASS_HID_09a8] = 535,
- [BNXT_ULP_CLASS_HID_00cc] = 536,
- [BNXT_ULP_CLASS_HID_3f64] = 537,
- [BNXT_ULP_CLASS_HID_3688] = 538,
- [BNXT_ULP_CLASS_HID_0b78] = 539,
- [BNXT_ULP_CLASS_HID_029c] = 540,
- [BNXT_ULP_CLASS_HID_5f68] = 541,
- [BNXT_ULP_CLASS_HID_568c] = 542,
- [BNXT_ULP_CLASS_HID_2b7c] = 543,
- [BNXT_ULP_CLASS_HID_22a0] = 544,
- [BNXT_ULP_CLASS_HID_4020] = 545,
- [BNXT_ULP_CLASS_HID_5b44] = 546,
- [BNXT_ULP_CLASS_HID_2c34] = 547,
- [BNXT_ULP_CLASS_HID_2758] = 548,
- [BNXT_ULP_CLASS_HID_18d8] = 549,
- [BNXT_ULP_CLASS_HID_13fc] = 550,
- [BNXT_ULP_CLASS_HID_4c38] = 551,
- [BNXT_ULP_CLASS_HID_475c] = 552,
- [BNXT_ULP_CLASS_HID_1aa8] = 553,
- [BNXT_ULP_CLASS_HID_15cc] = 554,
- [BNXT_ULP_CLASS_HID_4e08] = 555,
- [BNXT_ULP_CLASS_HID_492c] = 556,
- [BNXT_ULP_CLASS_HID_3aac] = 557,
- [BNXT_ULP_CLASS_HID_35d0] = 558,
- [BNXT_ULP_CLASS_HID_06c0] = 559,
- [BNXT_ULP_CLASS_HID_01e4] = 560,
- [BNXT_ULP_CLASS_HID_4d32] = 561,
- [BNXT_ULP_CLASS_HID_54aa] = 562,
- [BNXT_ULP_CLASS_HID_0686] = 563,
- [BNXT_ULP_CLASS_HID_540e] = 564,
- [BNXT_ULP_CLASS_HID_2e3c] = 565,
- [BNXT_ULP_CLASS_HID_3a20] = 566,
- [BNXT_ULP_CLASS_HID_46f0] = 567,
- [BNXT_ULP_CLASS_HID_52e4] = 568,
- [BNXT_ULP_CLASS_HID_55e4] = 569,
- [BNXT_ULP_CLASS_HID_21f8] = 570,
- [BNXT_ULP_CLASS_HID_75e8] = 571,
- [BNXT_ULP_CLASS_HID_41fc] = 572,
- [BNXT_ULP_CLASS_HID_4d12] = 573,
- [BNXT_ULP_CLASS_HID_548a] = 574,
- [BNXT_ULP_CLASS_HID_3356] = 575,
- [BNXT_ULP_CLASS_HID_1ace] = 576,
- [BNXT_ULP_CLASS_HID_1a9a] = 577,
- [BNXT_ULP_CLASS_HID_4d46] = 578,
- [BNXT_ULP_CLASS_HID_2812] = 579,
- [BNXT_ULP_CLASS_HID_338a] = 580,
- [BNXT_ULP_CLASS_HID_06e6] = 581,
- [BNXT_ULP_CLASS_HID_546e] = 582,
- [BNXT_ULP_CLASS_HID_46ee] = 583,
- [BNXT_ULP_CLASS_HID_0d22] = 584,
- [BNXT_ULP_CLASS_HID_26e2] = 585,
- [BNXT_ULP_CLASS_HID_746a] = 586,
- [BNXT_ULP_CLASS_HID_1fa6] = 587,
- [BNXT_ULP_CLASS_HID_2d2e] = 588,
- [BNXT_ULP_CLASS_HID_4ef2] = 589,
- [BNXT_ULP_CLASS_HID_576a] = 590,
- [BNXT_ULP_CLASS_HID_30b6] = 591,
- [BNXT_ULP_CLASS_HID_192e] = 592,
- [BNXT_ULP_CLASS_HID_197a] = 593,
- [BNXT_ULP_CLASS_HID_4ea6] = 594,
- [BNXT_ULP_CLASS_HID_2bf2] = 595,
- [BNXT_ULP_CLASS_HID_306a] = 596,
- [BNXT_ULP_CLASS_HID_06c6] = 597,
- [BNXT_ULP_CLASS_HID_544e] = 598,
- [BNXT_ULP_CLASS_HID_46ce] = 599,
- [BNXT_ULP_CLASS_HID_0d02] = 600,
- [BNXT_ULP_CLASS_HID_26c2] = 601,
- [BNXT_ULP_CLASS_HID_744a] = 602,
- [BNXT_ULP_CLASS_HID_1f86] = 603,
- [BNXT_ULP_CLASS_HID_2d0e] = 604,
- [BNXT_ULP_CLASS_HID_2e1c] = 605,
- [BNXT_ULP_CLASS_HID_3a00] = 606,
- [BNXT_ULP_CLASS_HID_46d0] = 607,
- [BNXT_ULP_CLASS_HID_52c4] = 608,
- [BNXT_ULP_CLASS_HID_4e10] = 609,
- [BNXT_ULP_CLASS_HID_5a04] = 610,
- [BNXT_ULP_CLASS_HID_1f98] = 611,
- [BNXT_ULP_CLASS_HID_72f8] = 612,
- [BNXT_ULP_CLASS_HID_0a78] = 613,
- [BNXT_ULP_CLASS_HID_166c] = 614,
- [BNXT_ULP_CLASS_HID_233c] = 615,
- [BNXT_ULP_CLASS_HID_0f20] = 616,
- [BNXT_ULP_CLASS_HID_2a7c] = 617,
- [BNXT_ULP_CLASS_HID_3660] = 618,
- [BNXT_ULP_CLASS_HID_4330] = 619,
- [BNXT_ULP_CLASS_HID_2f24] = 620,
- [BNXT_ULP_CLASS_HID_5584] = 621,
- [BNXT_ULP_CLASS_HID_2198] = 622,
- [BNXT_ULP_CLASS_HID_7588] = 623,
- [BNXT_ULP_CLASS_HID_419c] = 624,
- [BNXT_ULP_CLASS_HID_7758] = 625,
- [BNXT_ULP_CLASS_HID_43ac] = 626,
- [BNXT_ULP_CLASS_HID_0c10] = 627,
- [BNXT_ULP_CLASS_HID_1864] = 628,
- [BNXT_ULP_CLASS_HID_30c8] = 629,
- [BNXT_ULP_CLASS_HID_1cdc] = 630,
- [BNXT_ULP_CLASS_HID_50cc] = 631,
- [BNXT_ULP_CLASS_HID_3d20] = 632,
- [BNXT_ULP_CLASS_HID_529c] = 633,
- [BNXT_ULP_CLASS_HID_3ef0] = 634,
- [BNXT_ULP_CLASS_HID_72e0] = 635,
- [BNXT_ULP_CLASS_HID_5ef4] = 636,
- [BNXT_ULP_CLASS_HID_2dfc] = 637,
- [BNXT_ULP_CLASS_HID_39e0] = 638,
- [BNXT_ULP_CLASS_HID_4530] = 639,
- [BNXT_ULP_CLASS_HID_5124] = 640,
- [BNXT_ULP_CLASS_HID_4df0] = 641,
- [BNXT_ULP_CLASS_HID_59e4] = 642,
- [BNXT_ULP_CLASS_HID_1c78] = 643,
- [BNXT_ULP_CLASS_HID_7118] = 644,
- [BNXT_ULP_CLASS_HID_0998] = 645,
- [BNXT_ULP_CLASS_HID_158c] = 646,
- [BNXT_ULP_CLASS_HID_20dc] = 647,
- [BNXT_ULP_CLASS_HID_0cc0] = 648,
- [BNXT_ULP_CLASS_HID_299c] = 649,
- [BNXT_ULP_CLASS_HID_3580] = 650,
- [BNXT_ULP_CLASS_HID_40d0] = 651,
- [BNXT_ULP_CLASS_HID_2cc4] = 652,
- [BNXT_ULP_CLASS_HID_55a4] = 653,
- [BNXT_ULP_CLASS_HID_21b8] = 654,
- [BNXT_ULP_CLASS_HID_75a8] = 655,
- [BNXT_ULP_CLASS_HID_41bc] = 656,
- [BNXT_ULP_CLASS_HID_7778] = 657,
- [BNXT_ULP_CLASS_HID_438c] = 658,
- [BNXT_ULP_CLASS_HID_0c30] = 659,
- [BNXT_ULP_CLASS_HID_1844] = 660,
- [BNXT_ULP_CLASS_HID_30e8] = 661,
- [BNXT_ULP_CLASS_HID_1cfc] = 662,
- [BNXT_ULP_CLASS_HID_50ec] = 663,
- [BNXT_ULP_CLASS_HID_3d00] = 664,
- [BNXT_ULP_CLASS_HID_52bc] = 665,
- [BNXT_ULP_CLASS_HID_3ed0] = 666,
- [BNXT_ULP_CLASS_HID_72c0] = 667,
- [BNXT_ULP_CLASS_HID_5ed4] = 668,
- [BNXT_ULP_CLASS_HID_3866] = 669,
- [BNXT_ULP_CLASS_HID_381e] = 670,
- [BNXT_ULP_CLASS_HID_3860] = 671,
- [BNXT_ULP_CLASS_HID_0454] = 672,
- [BNXT_ULP_CLASS_HID_3818] = 673,
- [BNXT_ULP_CLASS_HID_042c] = 674,
- [BNXT_ULP_CLASS_HID_3846] = 675,
- [BNXT_ULP_CLASS_HID_387e] = 676,
- [BNXT_ULP_CLASS_HID_3ba6] = 677,
- [BNXT_ULP_CLASS_HID_385e] = 678,
- [BNXT_ULP_CLASS_HID_3840] = 679,
- [BNXT_ULP_CLASS_HID_0474] = 680,
- [BNXT_ULP_CLASS_HID_3878] = 681,
- [BNXT_ULP_CLASS_HID_044c] = 682,
- [BNXT_ULP_CLASS_HID_3ba0] = 683,
- [BNXT_ULP_CLASS_HID_0794] = 684,
- [BNXT_ULP_CLASS_HID_3858] = 685,
- [BNXT_ULP_CLASS_HID_046c] = 686
+ [BNXT_ULP_CLASS_HID_3612] = 345,
+ [BNXT_ULP_CLASS_HID_66da] = 346,
+ [BNXT_ULP_CLASS_HID_6165] = 347,
+ [BNXT_ULP_CLASS_HID_2aa1] = 348,
+ [BNXT_ULP_CLASS_HID_09cd] = 349,
+ [BNXT_ULP_CLASS_HID_3845] = 350,
+ [BNXT_ULP_CLASS_HID_11e9] = 351,
+ [BNXT_ULP_CLASS_HID_4361] = 352,
+ [BNXT_ULP_CLASS_HID_218d] = 353,
+ [BNXT_ULP_CLASS_HID_5105] = 354,
+ [BNXT_ULP_CLASS_HID_0c89] = 355,
+ [BNXT_ULP_CLASS_HID_3e81] = 356,
+ [BNXT_ULP_CLASS_HID_1dad] = 357,
+ [BNXT_ULP_CLASS_HID_4ca5] = 358,
+ [BNXT_ULP_CLASS_HID_25c9] = 359,
+ [BNXT_ULP_CLASS_HID_57c1] = 360,
+ [BNXT_ULP_CLASS_HID_33ed] = 361,
+ [BNXT_ULP_CLASS_HID_65e5] = 362,
+ [BNXT_ULP_CLASS_HID_6dd9] = 363,
+ [BNXT_ULP_CLASS_HID_261d] = 364,
+ [BNXT_ULP_CLASS_HID_0571] = 365,
+ [BNXT_ULP_CLASS_HID_34f9] = 366,
+ [BNXT_ULP_CLASS_HID_1d55] = 367,
+ [BNXT_ULP_CLASS_HID_4fdd] = 368,
+ [BNXT_ULP_CLASS_HID_2d31] = 369,
+ [BNXT_ULP_CLASS_HID_5db9] = 370,
+ [BNXT_ULP_CLASS_HID_0035] = 371,
+ [BNXT_ULP_CLASS_HID_323d] = 372,
+ [BNXT_ULP_CLASS_HID_1111] = 373,
+ [BNXT_ULP_CLASS_HID_4019] = 374,
+ [BNXT_ULP_CLASS_HID_2975] = 375,
+ [BNXT_ULP_CLASS_HID_5b7d] = 376,
+ [BNXT_ULP_CLASS_HID_3f51] = 377,
+ [BNXT_ULP_CLASS_HID_6959] = 378,
+ [BNXT_ULP_CLASS_HID_0e85] = 379,
+ [BNXT_ULP_CLASS_HID_380d] = 380,
+ [BNXT_ULP_CLASS_HID_1f21] = 381,
+ [BNXT_ULP_CLASS_HID_4ea9] = 382,
+ [BNXT_ULP_CLASS_HID_1705] = 383,
+ [BNXT_ULP_CLASS_HID_418d] = 384,
+ [BNXT_ULP_CLASS_HID_2721] = 385,
+ [BNXT_ULP_CLASS_HID_57a9] = 386,
+ [BNXT_ULP_CLASS_HID_1a25] = 387,
+ [BNXT_ULP_CLASS_HID_342d] = 388,
+ [BNXT_ULP_CLASS_HID_2b01] = 389,
+ [BNXT_ULP_CLASS_HID_5a09] = 390,
+ [BNXT_ULP_CLASS_HID_2325] = 391,
+ [BNXT_ULP_CLASS_HID_5d2d] = 392,
+ [BNXT_ULP_CLASS_HID_3101] = 393,
+ [BNXT_ULP_CLASS_HID_6309] = 394,
+ [BNXT_ULP_CLASS_HID_0bad] = 395,
+ [BNXT_ULP_CLASS_HID_2535] = 396,
+ [BNXT_ULP_CLASS_HID_1869] = 397,
+ [BNXT_ULP_CLASS_HID_4bf1] = 398,
+ [BNXT_ULP_CLASS_HID_136d] = 399,
+ [BNXT_ULP_CLASS_HID_43f5] = 400,
+ [BNXT_ULP_CLASS_HID_2129] = 401,
+ [BNXT_ULP_CLASS_HID_53b1] = 402,
+ [BNXT_ULP_CLASS_HID_072d] = 403,
+ [BNXT_ULP_CLASS_HID_3135] = 404,
+ [BNXT_ULP_CLASS_HID_1429] = 405,
+ [BNXT_ULP_CLASS_HID_4731] = 406,
+ [BNXT_ULP_CLASS_HID_2f6d] = 407,
+ [BNXT_ULP_CLASS_HID_5f75] = 408,
+ [BNXT_ULP_CLASS_HID_3d69] = 409,
+ [BNXT_ULP_CLASS_HID_6f71] = 410,
+ [BNXT_ULP_CLASS_HID_0dbd] = 411,
+ [BNXT_ULP_CLASS_HID_3f25] = 412,
+ [BNXT_ULP_CLASS_HID_1239] = 413,
+ [BNXT_ULP_CLASS_HID_4da1] = 414,
+ [BNXT_ULP_CLASS_HID_153d] = 415,
+ [BNXT_ULP_CLASS_HID_45a5] = 416,
+ [BNXT_ULP_CLASS_HID_3bb9] = 417,
+ [BNXT_ULP_CLASS_HID_55a1] = 418,
+ [BNXT_ULP_CLASS_HID_193d] = 419,
+ [BNXT_ULP_CLASS_HID_4b25] = 420,
+ [BNXT_ULP_CLASS_HID_2e39] = 421,
+ [BNXT_ULP_CLASS_HID_5921] = 422,
+ [BNXT_ULP_CLASS_HID_213d] = 423,
+ [BNXT_ULP_CLASS_HID_5125] = 424,
+ [BNXT_ULP_CLASS_HID_3739] = 425,
+ [BNXT_ULP_CLASS_HID_093d] = 426,
+ [BNXT_ULP_CLASS_HID_684d] = 427,
+ [BNXT_ULP_CLASS_HID_2389] = 428,
+ [BNXT_ULP_CLASS_HID_00e5] = 429,
+ [BNXT_ULP_CLASS_HID_316d] = 430,
+ [BNXT_ULP_CLASS_HID_18c1] = 431,
+ [BNXT_ULP_CLASS_HID_4a49] = 432,
+ [BNXT_ULP_CLASS_HID_28a5] = 433,
+ [BNXT_ULP_CLASS_HID_582d] = 434,
+ [BNXT_ULP_CLASS_HID_05a1] = 435,
+ [BNXT_ULP_CLASS_HID_37a9] = 436,
+ [BNXT_ULP_CLASS_HID_1485] = 437,
+ [BNXT_ULP_CLASS_HID_458d] = 438,
+ [BNXT_ULP_CLASS_HID_2ce1] = 439,
+ [BNXT_ULP_CLASS_HID_5ee9] = 440,
+ [BNXT_ULP_CLASS_HID_3ac5] = 441,
+ [BNXT_ULP_CLASS_HID_6ccd] = 442,
+ [BNXT_ULP_CLASS_HID_0b11] = 443,
+ [BNXT_ULP_CLASS_HID_3d99] = 444,
+ [BNXT_ULP_CLASS_HID_1ab5] = 445,
+ [BNXT_ULP_CLASS_HID_4b3d] = 446,
+ [BNXT_ULP_CLASS_HID_1291] = 447,
+ [BNXT_ULP_CLASS_HID_4419] = 448,
+ [BNXT_ULP_CLASS_HID_22b5] = 449,
+ [BNXT_ULP_CLASS_HID_523d] = 450,
+ [BNXT_ULP_CLASS_HID_1fb1] = 451,
+ [BNXT_ULP_CLASS_HID_31b9] = 452,
+ [BNXT_ULP_CLASS_HID_2e95] = 453,
+ [BNXT_ULP_CLASS_HID_5f9d] = 454,
+ [BNXT_ULP_CLASS_HID_26b1] = 455,
+ [BNXT_ULP_CLASS_HID_58b9] = 456,
+ [BNXT_ULP_CLASS_HID_3495] = 457,
+ [BNXT_ULP_CLASS_HID_669d] = 458,
+ [BNXT_ULP_CLASS_HID_0e39] = 459,
+ [BNXT_ULP_CLASS_HID_20a1] = 460,
+ [BNXT_ULP_CLASS_HID_1dfd] = 461,
+ [BNXT_ULP_CLASS_HID_4e65] = 462,
+ [BNXT_ULP_CLASS_HID_16f9] = 463,
+ [BNXT_ULP_CLASS_HID_4661] = 464,
+ [BNXT_ULP_CLASS_HID_24bd] = 465,
+ [BNXT_ULP_CLASS_HID_5625] = 466,
+ [BNXT_ULP_CLASS_HID_02b9] = 467,
+ [BNXT_ULP_CLASS_HID_34a1] = 468,
+ [BNXT_ULP_CLASS_HID_11bd] = 469,
+ [BNXT_ULP_CLASS_HID_42a5] = 470,
+ [BNXT_ULP_CLASS_HID_2af9] = 471,
+ [BNXT_ULP_CLASS_HID_5ae1] = 472,
+ [BNXT_ULP_CLASS_HID_38fd] = 473,
+ [BNXT_ULP_CLASS_HID_6ae5] = 474,
+ [BNXT_ULP_CLASS_HID_0829] = 475,
+ [BNXT_ULP_CLASS_HID_3ab1] = 476,
+ [BNXT_ULP_CLASS_HID_17ad] = 477,
+ [BNXT_ULP_CLASS_HID_4835] = 478,
+ [BNXT_ULP_CLASS_HID_10a9] = 479,
+ [BNXT_ULP_CLASS_HID_4031] = 480,
+ [BNXT_ULP_CLASS_HID_3e2d] = 481,
+ [BNXT_ULP_CLASS_HID_5035] = 482,
+ [BNXT_ULP_CLASS_HID_1ca9] = 483,
+ [BNXT_ULP_CLASS_HID_4eb1] = 484,
+ [BNXT_ULP_CLASS_HID_2bad] = 485,
+ [BNXT_ULP_CLASS_HID_5cb5] = 486,
+ [BNXT_ULP_CLASS_HID_24a9] = 487,
+ [BNXT_ULP_CLASS_HID_54b1] = 488,
+ [BNXT_ULP_CLASS_HID_32ad] = 489,
+ [BNXT_ULP_CLASS_HID_0ca9] = 490,
+ [BNXT_ULP_CLASS_HID_7f35] = 491,
+ [BNXT_ULP_CLASS_HID_34f1] = 492,
+ [BNXT_ULP_CLASS_HID_179d] = 493,
+ [BNXT_ULP_CLASS_HID_2615] = 494,
+ [BNXT_ULP_CLASS_HID_0fb9] = 495,
+ [BNXT_ULP_CLASS_HID_5d31] = 496,
+ [BNXT_ULP_CLASS_HID_3fdd] = 497,
+ [BNXT_ULP_CLASS_HID_4f55] = 498,
+ [BNXT_ULP_CLASS_HID_12d9] = 499,
+ [BNXT_ULP_CLASS_HID_20d1] = 500,
+ [BNXT_ULP_CLASS_HID_03fd] = 501,
+ [BNXT_ULP_CLASS_HID_52f5] = 502,
+ [BNXT_ULP_CLASS_HID_3b99] = 503,
+ [BNXT_ULP_CLASS_HID_4991] = 504,
+ [BNXT_ULP_CLASS_HID_2dbd] = 505,
+ [BNXT_ULP_CLASS_HID_7bb5] = 506,
+ [BNXT_ULP_CLASS_HID_34c6] = 507,
+ [BNXT_ULP_CLASS_HID_0c22] = 508,
+ [BNXT_ULP_CLASS_HID_1cbe] = 509,
+ [BNXT_ULP_CLASS_HID_179a] = 510,
+ [BNXT_ULP_CLASS_HID_59be] = 511,
+ [BNXT_ULP_CLASS_HID_515a] = 512,
+ [BNXT_ULP_CLASS_HID_1c72] = 513,
+ [BNXT_ULP_CLASS_HID_171e] = 514,
+ [BNXT_ULP_CLASS_HID_19c8] = 515,
+ [BNXT_ULP_CLASS_HID_112c] = 516,
+ [BNXT_ULP_CLASS_HID_4d68] = 517,
+ [BNXT_ULP_CLASS_HID_444c] = 518,
+ [BNXT_ULP_CLASS_HID_0e8c] = 519,
+ [BNXT_ULP_CLASS_HID_09e0] = 520,
+ [BNXT_ULP_CLASS_HID_1af0] = 521,
+ [BNXT_ULP_CLASS_HID_15d4] = 522,
+ [BNXT_ULP_CLASS_HID_1dd0] = 523,
+ [BNXT_ULP_CLASS_HID_14f4] = 524,
+ [BNXT_ULP_CLASS_HID_70b0] = 525,
+ [BNXT_ULP_CLASS_HID_4854] = 526,
+ [BNXT_ULP_CLASS_HID_3dd4] = 527,
+ [BNXT_ULP_CLASS_HID_34f8] = 528,
+ [BNXT_ULP_CLASS_HID_09e8] = 529,
+ [BNXT_ULP_CLASS_HID_008c] = 530,
+ [BNXT_ULP_CLASS_HID_34e6] = 531,
+ [BNXT_ULP_CLASS_HID_0c02] = 532,
+ [BNXT_ULP_CLASS_HID_1c9e] = 533,
+ [BNXT_ULP_CLASS_HID_17ba] = 534,
+ [BNXT_ULP_CLASS_HID_429e] = 535,
+ [BNXT_ULP_CLASS_HID_5dba] = 536,
+ [BNXT_ULP_CLASS_HID_2a16] = 537,
+ [BNXT_ULP_CLASS_HID_2532] = 538,
+ [BNXT_ULP_CLASS_HID_2da2] = 539,
+ [BNXT_ULP_CLASS_HID_24fe] = 540,
+ [BNXT_ULP_CLASS_HID_355a] = 541,
+ [BNXT_ULP_CLASS_HID_0c76] = 542,
+ [BNXT_ULP_CLASS_HID_13e6] = 543,
+ [BNXT_ULP_CLASS_HID_7276] = 544,
+ [BNXT_ULP_CLASS_HID_42d2] = 545,
+ [BNXT_ULP_CLASS_HID_5dee] = 546,
+ [BNXT_ULP_CLASS_HID_59de] = 547,
+ [BNXT_ULP_CLASS_HID_513a] = 548,
+ [BNXT_ULP_CLASS_HID_1c12] = 549,
+ [BNXT_ULP_CLASS_HID_177e] = 550,
+ [BNXT_ULP_CLASS_HID_0e92] = 551,
+ [BNXT_ULP_CLASS_HID_09fe] = 552,
+ [BNXT_ULP_CLASS_HID_5c1a] = 553,
+ [BNXT_ULP_CLASS_HID_5746] = 554,
+ [BNXT_ULP_CLASS_HID_79da] = 555,
+ [BNXT_ULP_CLASS_HID_7106] = 556,
+ [BNXT_ULP_CLASS_HID_3c1e] = 557,
+ [BNXT_ULP_CLASS_HID_377a] = 558,
+ [BNXT_ULP_CLASS_HID_2e9e] = 559,
+ [BNXT_ULP_CLASS_HID_29fa] = 560,
+ [BNXT_ULP_CLASS_HID_14d2] = 561,
+ [BNXT_ULP_CLASS_HID_7742] = 562,
+ [BNXT_ULP_CLASS_HID_3706] = 563,
+ [BNXT_ULP_CLASS_HID_0fe2] = 564,
+ [BNXT_ULP_CLASS_HID_1f7e] = 565,
+ [BNXT_ULP_CLASS_HID_145a] = 566,
+ [BNXT_ULP_CLASS_HID_417e] = 567,
+ [BNXT_ULP_CLASS_HID_5e5a] = 568,
+ [BNXT_ULP_CLASS_HID_29f6] = 569,
+ [BNXT_ULP_CLASS_HID_26d2] = 570,
+ [BNXT_ULP_CLASS_HID_2e42] = 571,
+ [BNXT_ULP_CLASS_HID_271e] = 572,
+ [BNXT_ULP_CLASS_HID_36ba] = 573,
+ [BNXT_ULP_CLASS_HID_0f96] = 574,
+ [BNXT_ULP_CLASS_HID_1006] = 575,
+ [BNXT_ULP_CLASS_HID_7196] = 576,
+ [BNXT_ULP_CLASS_HID_4132] = 577,
+ [BNXT_ULP_CLASS_HID_5e0e] = 578,
+ [BNXT_ULP_CLASS_HID_59fe] = 579,
+ [BNXT_ULP_CLASS_HID_511a] = 580,
+ [BNXT_ULP_CLASS_HID_1c32] = 581,
+ [BNXT_ULP_CLASS_HID_175e] = 582,
+ [BNXT_ULP_CLASS_HID_0eb2] = 583,
+ [BNXT_ULP_CLASS_HID_09de] = 584,
+ [BNXT_ULP_CLASS_HID_5c3a] = 585,
+ [BNXT_ULP_CLASS_HID_5766] = 586,
+ [BNXT_ULP_CLASS_HID_79fa] = 587,
+ [BNXT_ULP_CLASS_HID_7126] = 588,
+ [BNXT_ULP_CLASS_HID_3c3e] = 589,
+ [BNXT_ULP_CLASS_HID_375a] = 590,
+ [BNXT_ULP_CLASS_HID_2ebe] = 591,
+ [BNXT_ULP_CLASS_HID_29da] = 592,
+ [BNXT_ULP_CLASS_HID_14f2] = 593,
+ [BNXT_ULP_CLASS_HID_7762] = 594,
+ [BNXT_ULP_CLASS_HID_19e8] = 595,
+ [BNXT_ULP_CLASS_HID_110c] = 596,
+ [BNXT_ULP_CLASS_HID_4d48] = 597,
+ [BNXT_ULP_CLASS_HID_446c] = 598,
+ [BNXT_ULP_CLASS_HID_0eac] = 599,
+ [BNXT_ULP_CLASS_HID_09c0] = 600,
+ [BNXT_ULP_CLASS_HID_1ad0] = 601,
+ [BNXT_ULP_CLASS_HID_15f4] = 602,
+ [BNXT_ULP_CLASS_HID_39ec] = 603,
+ [BNXT_ULP_CLASS_HID_3100] = 604,
+ [BNXT_ULP_CLASS_HID_0210] = 605,
+ [BNXT_ULP_CLASS_HID_1d34] = 606,
+ [BNXT_ULP_CLASS_HID_2ea0] = 607,
+ [BNXT_ULP_CLASS_HID_29c4] = 608,
+ [BNXT_ULP_CLASS_HID_3ad4] = 609,
+ [BNXT_ULP_CLASS_HID_35e8] = 610,
+ [BNXT_ULP_CLASS_HID_5d80] = 611,
+ [BNXT_ULP_CLASS_HID_54a4] = 612,
+ [BNXT_ULP_CLASS_HID_29b4] = 613,
+ [BNXT_ULP_CLASS_HID_20c8] = 614,
+ [BNXT_ULP_CLASS_HID_7244] = 615,
+ [BNXT_ULP_CLASS_HID_4d98] = 616,
+ [BNXT_ULP_CLASS_HID_5e68] = 617,
+ [BNXT_ULP_CLASS_HID_598c] = 618,
+ [BNXT_ULP_CLASS_HID_1248] = 619,
+ [BNXT_ULP_CLASS_HID_74d8] = 620,
+ [BNXT_ULP_CLASS_HID_49a8] = 621,
+ [BNXT_ULP_CLASS_HID_40cc] = 622,
+ [BNXT_ULP_CLASS_HID_0b0c] = 623,
+ [BNXT_ULP_CLASS_HID_0220] = 624,
+ [BNXT_ULP_CLASS_HID_1730] = 625,
+ [BNXT_ULP_CLASS_HID_7980] = 626,
+ [BNXT_ULP_CLASS_HID_1db0] = 627,
+ [BNXT_ULP_CLASS_HID_1494] = 628,
+ [BNXT_ULP_CLASS_HID_70d0] = 629,
+ [BNXT_ULP_CLASS_HID_4834] = 630,
+ [BNXT_ULP_CLASS_HID_3db4] = 631,
+ [BNXT_ULP_CLASS_HID_3498] = 632,
+ [BNXT_ULP_CLASS_HID_0988] = 633,
+ [BNXT_ULP_CLASS_HID_00ec] = 634,
+ [BNXT_ULP_CLASS_HID_3f44] = 635,
+ [BNXT_ULP_CLASS_HID_36a8] = 636,
+ [BNXT_ULP_CLASS_HID_0b58] = 637,
+ [BNXT_ULP_CLASS_HID_02bc] = 638,
+ [BNXT_ULP_CLASS_HID_5f48] = 639,
+ [BNXT_ULP_CLASS_HID_56ac] = 640,
+ [BNXT_ULP_CLASS_HID_2b5c] = 641,
+ [BNXT_ULP_CLASS_HID_2280] = 642,
+ [BNXT_ULP_CLASS_HID_4000] = 643,
+ [BNXT_ULP_CLASS_HID_5b64] = 644,
+ [BNXT_ULP_CLASS_HID_2c14] = 645,
+ [BNXT_ULP_CLASS_HID_2778] = 646,
+ [BNXT_ULP_CLASS_HID_18f8] = 647,
+ [BNXT_ULP_CLASS_HID_13dc] = 648,
+ [BNXT_ULP_CLASS_HID_4c18] = 649,
+ [BNXT_ULP_CLASS_HID_477c] = 650,
+ [BNXT_ULP_CLASS_HID_1a88] = 651,
+ [BNXT_ULP_CLASS_HID_15ec] = 652,
+ [BNXT_ULP_CLASS_HID_4e28] = 653,
+ [BNXT_ULP_CLASS_HID_490c] = 654,
+ [BNXT_ULP_CLASS_HID_3a8c] = 655,
+ [BNXT_ULP_CLASS_HID_35f0] = 656,
+ [BNXT_ULP_CLASS_HID_06e0] = 657,
+ [BNXT_ULP_CLASS_HID_01c4] = 658,
+ [BNXT_ULP_CLASS_HID_1a08] = 659,
+ [BNXT_ULP_CLASS_HID_12ec] = 660,
+ [BNXT_ULP_CLASS_HID_4ea8] = 661,
+ [BNXT_ULP_CLASS_HID_478c] = 662,
+ [BNXT_ULP_CLASS_HID_0d4c] = 663,
+ [BNXT_ULP_CLASS_HID_0a20] = 664,
+ [BNXT_ULP_CLASS_HID_1930] = 665,
+ [BNXT_ULP_CLASS_HID_1614] = 666,
+ [BNXT_ULP_CLASS_HID_3a0c] = 667,
+ [BNXT_ULP_CLASS_HID_32e0] = 668,
+ [BNXT_ULP_CLASS_HID_01f0] = 669,
+ [BNXT_ULP_CLASS_HID_1ed4] = 670,
+ [BNXT_ULP_CLASS_HID_2d40] = 671,
+ [BNXT_ULP_CLASS_HID_2a24] = 672,
+ [BNXT_ULP_CLASS_HID_3934] = 673,
+ [BNXT_ULP_CLASS_HID_3608] = 674,
+ [BNXT_ULP_CLASS_HID_5e60] = 675,
+ [BNXT_ULP_CLASS_HID_5744] = 676,
+ [BNXT_ULP_CLASS_HID_2a54] = 677,
+ [BNXT_ULP_CLASS_HID_2328] = 678,
+ [BNXT_ULP_CLASS_HID_71a4] = 679,
+ [BNXT_ULP_CLASS_HID_4e78] = 680,
+ [BNXT_ULP_CLASS_HID_5d88] = 681,
+ [BNXT_ULP_CLASS_HID_5a6c] = 682,
+ [BNXT_ULP_CLASS_HID_11a8] = 683,
+ [BNXT_ULP_CLASS_HID_7738] = 684,
+ [BNXT_ULP_CLASS_HID_4a48] = 685,
+ [BNXT_ULP_CLASS_HID_432c] = 686,
+ [BNXT_ULP_CLASS_HID_08ec] = 687,
+ [BNXT_ULP_CLASS_HID_01c0] = 688,
+ [BNXT_ULP_CLASS_HID_14d0] = 689,
+ [BNXT_ULP_CLASS_HID_7a60] = 690,
+ [BNXT_ULP_CLASS_HID_1d90] = 691,
+ [BNXT_ULP_CLASS_HID_14b4] = 692,
+ [BNXT_ULP_CLASS_HID_70f0] = 693,
+ [BNXT_ULP_CLASS_HID_4814] = 694,
+ [BNXT_ULP_CLASS_HID_3d94] = 695,
+ [BNXT_ULP_CLASS_HID_34b8] = 696,
+ [BNXT_ULP_CLASS_HID_09a8] = 697,
+ [BNXT_ULP_CLASS_HID_00cc] = 698,
+ [BNXT_ULP_CLASS_HID_3f64] = 699,
+ [BNXT_ULP_CLASS_HID_3688] = 700,
+ [BNXT_ULP_CLASS_HID_0b78] = 701,
+ [BNXT_ULP_CLASS_HID_029c] = 702,
+ [BNXT_ULP_CLASS_HID_5f68] = 703,
+ [BNXT_ULP_CLASS_HID_568c] = 704,
+ [BNXT_ULP_CLASS_HID_2b7c] = 705,
+ [BNXT_ULP_CLASS_HID_22a0] = 706,
+ [BNXT_ULP_CLASS_HID_4020] = 707,
+ [BNXT_ULP_CLASS_HID_5b44] = 708,
+ [BNXT_ULP_CLASS_HID_2c34] = 709,
+ [BNXT_ULP_CLASS_HID_2758] = 710,
+ [BNXT_ULP_CLASS_HID_18d8] = 711,
+ [BNXT_ULP_CLASS_HID_13fc] = 712,
+ [BNXT_ULP_CLASS_HID_4c38] = 713,
+ [BNXT_ULP_CLASS_HID_475c] = 714,
+ [BNXT_ULP_CLASS_HID_1aa8] = 715,
+ [BNXT_ULP_CLASS_HID_15cc] = 716,
+ [BNXT_ULP_CLASS_HID_4e08] = 717,
+ [BNXT_ULP_CLASS_HID_492c] = 718,
+ [BNXT_ULP_CLASS_HID_3aac] = 719,
+ [BNXT_ULP_CLASS_HID_35d0] = 720,
+ [BNXT_ULP_CLASS_HID_06c0] = 721,
+ [BNXT_ULP_CLASS_HID_01e4] = 722,
+ [BNXT_ULP_CLASS_HID_4d32] = 723,
+ [BNXT_ULP_CLASS_HID_54aa] = 724,
+ [BNXT_ULP_CLASS_HID_0686] = 725,
+ [BNXT_ULP_CLASS_HID_540e] = 726,
+ [BNXT_ULP_CLASS_HID_2e3c] = 727,
+ [BNXT_ULP_CLASS_HID_3a20] = 728,
+ [BNXT_ULP_CLASS_HID_46f0] = 729,
+ [BNXT_ULP_CLASS_HID_52e4] = 730,
+ [BNXT_ULP_CLASS_HID_55e4] = 731,
+ [BNXT_ULP_CLASS_HID_21f8] = 732,
+ [BNXT_ULP_CLASS_HID_75e8] = 733,
+ [BNXT_ULP_CLASS_HID_41fc] = 734,
+ [BNXT_ULP_CLASS_HID_4d12] = 735,
+ [BNXT_ULP_CLASS_HID_548a] = 736,
+ [BNXT_ULP_CLASS_HID_3356] = 737,
+ [BNXT_ULP_CLASS_HID_1ace] = 738,
+ [BNXT_ULP_CLASS_HID_1a9a] = 739,
+ [BNXT_ULP_CLASS_HID_4d46] = 740,
+ [BNXT_ULP_CLASS_HID_2812] = 741,
+ [BNXT_ULP_CLASS_HID_338a] = 742,
+ [BNXT_ULP_CLASS_HID_06e6] = 743,
+ [BNXT_ULP_CLASS_HID_546e] = 744,
+ [BNXT_ULP_CLASS_HID_46ee] = 745,
+ [BNXT_ULP_CLASS_HID_0d22] = 746,
+ [BNXT_ULP_CLASS_HID_26e2] = 747,
+ [BNXT_ULP_CLASS_HID_746a] = 748,
+ [BNXT_ULP_CLASS_HID_1fa6] = 749,
+ [BNXT_ULP_CLASS_HID_2d2e] = 750,
+ [BNXT_ULP_CLASS_HID_4ef2] = 751,
+ [BNXT_ULP_CLASS_HID_576a] = 752,
+ [BNXT_ULP_CLASS_HID_30b6] = 753,
+ [BNXT_ULP_CLASS_HID_192e] = 754,
+ [BNXT_ULP_CLASS_HID_197a] = 755,
+ [BNXT_ULP_CLASS_HID_4ea6] = 756,
+ [BNXT_ULP_CLASS_HID_2bf2] = 757,
+ [BNXT_ULP_CLASS_HID_306a] = 758,
+ [BNXT_ULP_CLASS_HID_06c6] = 759,
+ [BNXT_ULP_CLASS_HID_544e] = 760,
+ [BNXT_ULP_CLASS_HID_46ce] = 761,
+ [BNXT_ULP_CLASS_HID_0d02] = 762,
+ [BNXT_ULP_CLASS_HID_26c2] = 763,
+ [BNXT_ULP_CLASS_HID_744a] = 764,
+ [BNXT_ULP_CLASS_HID_1f86] = 765,
+ [BNXT_ULP_CLASS_HID_2d0e] = 766,
+ [BNXT_ULP_CLASS_HID_2e1c] = 767,
+ [BNXT_ULP_CLASS_HID_3a00] = 768,
+ [BNXT_ULP_CLASS_HID_46d0] = 769,
+ [BNXT_ULP_CLASS_HID_52c4] = 770,
+ [BNXT_ULP_CLASS_HID_4e10] = 771,
+ [BNXT_ULP_CLASS_HID_5a04] = 772,
+ [BNXT_ULP_CLASS_HID_1f98] = 773,
+ [BNXT_ULP_CLASS_HID_72f8] = 774,
+ [BNXT_ULP_CLASS_HID_0a78] = 775,
+ [BNXT_ULP_CLASS_HID_166c] = 776,
+ [BNXT_ULP_CLASS_HID_233c] = 777,
+ [BNXT_ULP_CLASS_HID_0f20] = 778,
+ [BNXT_ULP_CLASS_HID_2a7c] = 779,
+ [BNXT_ULP_CLASS_HID_3660] = 780,
+ [BNXT_ULP_CLASS_HID_4330] = 781,
+ [BNXT_ULP_CLASS_HID_2f24] = 782,
+ [BNXT_ULP_CLASS_HID_5584] = 783,
+ [BNXT_ULP_CLASS_HID_2198] = 784,
+ [BNXT_ULP_CLASS_HID_7588] = 785,
+ [BNXT_ULP_CLASS_HID_419c] = 786,
+ [BNXT_ULP_CLASS_HID_7758] = 787,
+ [BNXT_ULP_CLASS_HID_43ac] = 788,
+ [BNXT_ULP_CLASS_HID_0c10] = 789,
+ [BNXT_ULP_CLASS_HID_1864] = 790,
+ [BNXT_ULP_CLASS_HID_30c8] = 791,
+ [BNXT_ULP_CLASS_HID_1cdc] = 792,
+ [BNXT_ULP_CLASS_HID_50cc] = 793,
+ [BNXT_ULP_CLASS_HID_3d20] = 794,
+ [BNXT_ULP_CLASS_HID_529c] = 795,
+ [BNXT_ULP_CLASS_HID_3ef0] = 796,
+ [BNXT_ULP_CLASS_HID_72e0] = 797,
+ [BNXT_ULP_CLASS_HID_5ef4] = 798,
+ [BNXT_ULP_CLASS_HID_2dfc] = 799,
+ [BNXT_ULP_CLASS_HID_39e0] = 800,
+ [BNXT_ULP_CLASS_HID_4530] = 801,
+ [BNXT_ULP_CLASS_HID_5124] = 802,
+ [BNXT_ULP_CLASS_HID_4df0] = 803,
+ [BNXT_ULP_CLASS_HID_59e4] = 804,
+ [BNXT_ULP_CLASS_HID_1c78] = 805,
+ [BNXT_ULP_CLASS_HID_7118] = 806,
+ [BNXT_ULP_CLASS_HID_0998] = 807,
+ [BNXT_ULP_CLASS_HID_158c] = 808,
+ [BNXT_ULP_CLASS_HID_20dc] = 809,
+ [BNXT_ULP_CLASS_HID_0cc0] = 810,
+ [BNXT_ULP_CLASS_HID_299c] = 811,
+ [BNXT_ULP_CLASS_HID_3580] = 812,
+ [BNXT_ULP_CLASS_HID_40d0] = 813,
+ [BNXT_ULP_CLASS_HID_2cc4] = 814,
+ [BNXT_ULP_CLASS_HID_55a4] = 815,
+ [BNXT_ULP_CLASS_HID_21b8] = 816,
+ [BNXT_ULP_CLASS_HID_75a8] = 817,
+ [BNXT_ULP_CLASS_HID_41bc] = 818,
+ [BNXT_ULP_CLASS_HID_7778] = 819,
+ [BNXT_ULP_CLASS_HID_438c] = 820,
+ [BNXT_ULP_CLASS_HID_0c30] = 821,
+ [BNXT_ULP_CLASS_HID_1844] = 822,
+ [BNXT_ULP_CLASS_HID_30e8] = 823,
+ [BNXT_ULP_CLASS_HID_1cfc] = 824,
+ [BNXT_ULP_CLASS_HID_50ec] = 825,
+ [BNXT_ULP_CLASS_HID_3d00] = 826,
+ [BNXT_ULP_CLASS_HID_52bc] = 827,
+ [BNXT_ULP_CLASS_HID_3ed0] = 828,
+ [BNXT_ULP_CLASS_HID_72c0] = 829,
+ [BNXT_ULP_CLASS_HID_5ed4] = 830,
+ [BNXT_ULP_CLASS_HID_3866] = 831,
+ [BNXT_ULP_CLASS_HID_381e] = 832,
+ [BNXT_ULP_CLASS_HID_3860] = 833,
+ [BNXT_ULP_CLASS_HID_0454] = 834,
+ [BNXT_ULP_CLASS_HID_3818] = 835,
+ [BNXT_ULP_CLASS_HID_042c] = 836,
+ [BNXT_ULP_CLASS_HID_3846] = 837,
+ [BNXT_ULP_CLASS_HID_387e] = 838,
+ [BNXT_ULP_CLASS_HID_3ba6] = 839,
+ [BNXT_ULP_CLASS_HID_385e] = 840,
+ [BNXT_ULP_CLASS_HID_3840] = 841,
+ [BNXT_ULP_CLASS_HID_0474] = 842,
+ [BNXT_ULP_CLASS_HID_3878] = 843,
+ [BNXT_ULP_CLASS_HID_044c] = 844,
+ [BNXT_ULP_CLASS_HID_3ba0] = 845,
+ [BNXT_ULP_CLASS_HID_0794] = 846,
+ [BNXT_ULP_CLASS_HID_3858] = 847,
+ [BNXT_ULP_CLASS_HID_046c] = 848
};
/* Array for the proto matcher list */
@@ -6964,8 +7126,3839 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_12_BITMASK_O_UDP_DST_PORT }
},
[345] = {
- .class_hid = BNXT_ULP_CLASS_HID_34c6,
+ .class_hid = BNXT_ULP_CLASS_HID_3612,
+ .class_tid = 2,
+ .hdr_sig_id = 0,
+ .flow_sig_id = 81920,
+ .flow_pattern_id = 0,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_F1 |
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT }
+ },
+ [346] = {
+ .class_hid = BNXT_ULP_CLASS_HID_66da,
+ .class_tid = 2,
+ .hdr_sig_id = 0,
+ .flow_sig_id = 81928,
+ .flow_pattern_id = 0,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_F1 |
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT }
+ },
+ [347] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6165,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 1313792,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC }
+ },
+ [348] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2aa1,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 1321984,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC }
+ },
+ [349] = {
+ .class_hid = BNXT_ULP_CLASS_HID_09cd,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 3410944,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }
+ },
+ [350] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3845,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 3419136,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }
+ },
+ [351] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11e9,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 2148797440,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [352] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4361,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 2148805632,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [353] = {
+ .class_hid = BNXT_ULP_CLASS_HID_218d,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 2150894592,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [354] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5105,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 2150902784,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [355] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0c89,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 4296281088,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [356] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3e81,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 4296289280,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [357] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1dad,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 4298378240,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [358] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4ca5,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 4298386432,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [359] = {
+ .class_hid = BNXT_ULP_CLASS_HID_25c9,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 6443764736,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [360] = {
+ .class_hid = BNXT_ULP_CLASS_HID_57c1,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 6443772928,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [361] = {
+ .class_hid = BNXT_ULP_CLASS_HID_33ed,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 6445861888,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [362] = {
+ .class_hid = BNXT_ULP_CLASS_HID_65e5,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 6445870080,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [363] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6dd9,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 1313792,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }
+ },
+ [364] = {
+ .class_hid = BNXT_ULP_CLASS_HID_261d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 1321984,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }
+ },
+ [365] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0571,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 3410944,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
+ },
+ [366] = {
+ .class_hid = BNXT_ULP_CLASS_HID_34f9,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 3419136,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
+ },
+ [367] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1d55,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 2148797440,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [368] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4fdd,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 2148805632,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [369] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2d31,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 2150894592,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [370] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5db9,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 2150902784,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [371] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0035,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 4296281088,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [372] = {
+ .class_hid = BNXT_ULP_CLASS_HID_323d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 4296289280,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [373] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1111,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 4298378240,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [374] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4019,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 4298386432,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [375] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2975,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 6443764736,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [376] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5b7d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 6443772928,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [377] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3f51,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 6445861888,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [378] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6959,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 6445870080,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [379] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0e85,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 8591248384,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [380] = {
+ .class_hid = BNXT_ULP_CLASS_HID_380d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 8591256576,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [381] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1f21,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 8593345536,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [382] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4ea9,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 8593353728,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [383] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1705,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 10738732032,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [384] = {
+ .class_hid = BNXT_ULP_CLASS_HID_418d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 10738740224,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [385] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2721,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 10740829184,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [386] = {
+ .class_hid = BNXT_ULP_CLASS_HID_57a9,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 10740837376,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [387] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1a25,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 12886215680,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [388] = {
+ .class_hid = BNXT_ULP_CLASS_HID_342d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 12886223872,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [389] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2b01,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 12888312832,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [390] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5a09,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 12888321024,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [391] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2325,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 15033699328,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [392] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5d2d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 15033707520,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [393] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3101,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 15035796480,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [394] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6309,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 15035804672,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [395] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0bad,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 17181182976,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [396] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2535,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 17181191168,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [397] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1869,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 17183280128,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [398] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4bf1,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 17183288320,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [399] = {
+ .class_hid = BNXT_ULP_CLASS_HID_136d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 19328666624,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [400] = {
+ .class_hid = BNXT_ULP_CLASS_HID_43f5,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 19328674816,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [401] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2129,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 19330763776,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [402] = {
+ .class_hid = BNXT_ULP_CLASS_HID_53b1,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 19330771968,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [403] = {
+ .class_hid = BNXT_ULP_CLASS_HID_072d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 21476150272,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [404] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3135,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 21476158464,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [405] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1429,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 21478247424,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [406] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4731,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 21478255616,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [407] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2f6d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 23623633920,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [408] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5f75,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 23623642112,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [409] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3d69,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 23625731072,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [410] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6f71,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 23625739264,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [411] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0dbd,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 25771117568,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [412] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3f25,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 25771125760,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [413] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1239,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 25773214720,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [414] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4da1,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 25773222912,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [415] = {
+ .class_hid = BNXT_ULP_CLASS_HID_153d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 27918601216,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [416] = {
+ .class_hid = BNXT_ULP_CLASS_HID_45a5,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 27918609408,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [417] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3bb9,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 27920698368,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [418] = {
+ .class_hid = BNXT_ULP_CLASS_HID_55a1,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 27920706560,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [419] = {
+ .class_hid = BNXT_ULP_CLASS_HID_193d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 30066084864,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [420] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4b25,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 30066093056,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [421] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2e39,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 30068182016,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [422] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5921,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 30068190208,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [423] = {
+ .class_hid = BNXT_ULP_CLASS_HID_213d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 32213568512,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [424] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5125,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 32213576704,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [425] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3739,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 32215665664,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [426] = {
+ .class_hid = BNXT_ULP_CLASS_HID_093d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 32215673856,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [427] = {
+ .class_hid = BNXT_ULP_CLASS_HID_684d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1313792,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
+ },
+ [428] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2389,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1321984,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
+ },
+ [429] = {
+ .class_hid = BNXT_ULP_CLASS_HID_00e5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3410944,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
+ },
+ [430] = {
+ .class_hid = BNXT_ULP_CLASS_HID_316d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3419136,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
+ },
+ [431] = {
+ .class_hid = BNXT_ULP_CLASS_HID_18c1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2148797440,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [432] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4a49,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2148805632,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [433] = {
+ .class_hid = BNXT_ULP_CLASS_HID_28a5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2150894592,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [434] = {
+ .class_hid = BNXT_ULP_CLASS_HID_582d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2150902784,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [435] = {
+ .class_hid = BNXT_ULP_CLASS_HID_05a1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4296281088,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [436] = {
+ .class_hid = BNXT_ULP_CLASS_HID_37a9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4296289280,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [437] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1485,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4298378240,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [438] = {
+ .class_hid = BNXT_ULP_CLASS_HID_458d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4298386432,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [439] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2ce1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6443764736,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [440] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5ee9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6443772928,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [441] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3ac5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6445861888,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [442] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6ccd,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6445870080,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [443] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0b11,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8591248384,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [444] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3d99,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8591256576,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [445] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1ab5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8593345536,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [446] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4b3d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8593353728,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [447] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1291,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 10738732032,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [448] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4419,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 10738740224,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [449] = {
+ .class_hid = BNXT_ULP_CLASS_HID_22b5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 10740829184,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [450] = {
+ .class_hid = BNXT_ULP_CLASS_HID_523d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 10740837376,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [451] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1fb1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 12886215680,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [452] = {
+ .class_hid = BNXT_ULP_CLASS_HID_31b9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 12886223872,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [453] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2e95,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 12888312832,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [454] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5f9d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 12888321024,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [455] = {
+ .class_hid = BNXT_ULP_CLASS_HID_26b1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 15033699328,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [456] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58b9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 15033707520,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [457] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3495,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 15035796480,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [458] = {
+ .class_hid = BNXT_ULP_CLASS_HID_669d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 15035804672,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [459] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0e39,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 17181182976,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [460] = {
+ .class_hid = BNXT_ULP_CLASS_HID_20a1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 17181191168,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [461] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1dfd,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 17183280128,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [462] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4e65,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 17183288320,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [463] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16f9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 19328666624,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [464] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4661,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 19328674816,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [465] = {
+ .class_hid = BNXT_ULP_CLASS_HID_24bd,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 19330763776,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [466] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5625,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 19330771968,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [467] = {
+ .class_hid = BNXT_ULP_CLASS_HID_02b9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 21476150272,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [468] = {
+ .class_hid = BNXT_ULP_CLASS_HID_34a1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 21476158464,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [469] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11bd,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 21478247424,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [470] = {
+ .class_hid = BNXT_ULP_CLASS_HID_42a5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 21478255616,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [471] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2af9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 23623633920,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [472] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5ae1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 23623642112,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [473] = {
+ .class_hid = BNXT_ULP_CLASS_HID_38fd,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 23625731072,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [474] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6ae5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 23625739264,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [475] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0829,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 25771117568,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [476] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3ab1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 25771125760,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [477] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17ad,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 25773214720,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [478] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4835,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 25773222912,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [479] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10a9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 27918601216,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [480] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4031,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 27918609408,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [481] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3e2d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 27920698368,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [482] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5035,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 27920706560,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [483] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1ca9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 30066084864,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [484] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4eb1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 30066093056,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [485] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2bad,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 30068182016,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [486] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5cb5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 30068190208,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [487] = {
+ .class_hid = BNXT_ULP_CLASS_HID_24a9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 32213568512,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [488] = {
+ .class_hid = BNXT_ULP_CLASS_HID_54b1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 32213576704,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [489] = {
+ .class_hid = BNXT_ULP_CLASS_HID_32ad,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 32215665664,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [490] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0ca9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 32215673856,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [491] = {
+ .class_hid = BNXT_ULP_CLASS_HID_7f35,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1313792,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ },
+ [492] = {
+ .class_hid = BNXT_ULP_CLASS_HID_34f1,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1321984,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ },
+ [493] = {
+ .class_hid = BNXT_ULP_CLASS_HID_179d,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 3410944,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ },
+ [494] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2615,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 3419136,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ },
+ [495] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0fb9,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2148797440,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [496] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5d31,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2148805632,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [497] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3fdd,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2150894592,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [498] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4f55,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2150902784,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [499] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12d9,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4296281088,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [500] = {
+ .class_hid = BNXT_ULP_CLASS_HID_20d1,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4296289280,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [501] = {
+ .class_hid = BNXT_ULP_CLASS_HID_03fd,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4298378240,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [502] = {
+ .class_hid = BNXT_ULP_CLASS_HID_52f5,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4298386432,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [503] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3b99,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6443764736,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [504] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4991,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6443772928,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [505] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2dbd,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6445861888,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [506] = {
+ .class_hid = BNXT_ULP_CLASS_HID_7bb5,
.class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6445870080,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [507] = {
+ .class_hid = BNXT_ULP_CLASS_HID_34c6,
+ .class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 4096,
.flow_pattern_id = 0,
@@ -6975,12 +10968,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [346] = {
+ [508] = {
.class_hid = BNXT_ULP_CLASS_HID_0c22,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 4100,
.flow_pattern_id = 0,
@@ -6990,13 +10983,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [347] = {
+ [509] = {
.class_hid = BNXT_ULP_CLASS_HID_1cbe,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 6144,
.flow_pattern_id = 0,
@@ -7006,13 +10999,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [348] = {
+ [510] = {
.class_hid = BNXT_ULP_CLASS_HID_179a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 6148,
.flow_pattern_id = 0,
@@ -7022,14 +11015,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [349] = {
+ [511] = {
.class_hid = BNXT_ULP_CLASS_HID_59be,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 16384,
.flow_pattern_id = 0,
@@ -7039,12 +11032,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [350] = {
+ [512] = {
.class_hid = BNXT_ULP_CLASS_HID_515a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 16388,
.flow_pattern_id = 0,
@@ -7054,13 +11047,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [351] = {
+ [513] = {
.class_hid = BNXT_ULP_CLASS_HID_1c72,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 24576,
.flow_pattern_id = 0,
@@ -7070,13 +11063,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [352] = {
+ [514] = {
.class_hid = BNXT_ULP_CLASS_HID_171e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 24580,
.flow_pattern_id = 0,
@@ -7086,14 +11079,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [353] = {
+ [515] = {
.class_hid = BNXT_ULP_CLASS_HID_19c8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32768,
.flow_pattern_id = 0,
@@ -7104,12 +11097,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [354] = {
+ [516] = {
.class_hid = BNXT_ULP_CLASS_HID_112c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32772,
.flow_pattern_id = 0,
@@ -7120,13 +11113,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [355] = {
+ [517] = {
.class_hid = BNXT_ULP_CLASS_HID_4d68,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32832,
.flow_pattern_id = 0,
@@ -7137,13 +11130,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [356] = {
+ [518] = {
.class_hid = BNXT_ULP_CLASS_HID_444c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32836,
.flow_pattern_id = 0,
@@ -7154,14 +11147,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [357] = {
+ [519] = {
.class_hid = BNXT_ULP_CLASS_HID_0e8c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49152,
.flow_pattern_id = 0,
@@ -7172,13 +11165,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [358] = {
+ [520] = {
.class_hid = BNXT_ULP_CLASS_HID_09e0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49156,
.flow_pattern_id = 0,
@@ -7189,14 +11182,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [359] = {
+ [521] = {
.class_hid = BNXT_ULP_CLASS_HID_1af0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49216,
.flow_pattern_id = 0,
@@ -7207,14 +11200,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [360] = {
+ [522] = {
.class_hid = BNXT_ULP_CLASS_HID_15d4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49220,
.flow_pattern_id = 0,
@@ -7225,15 +11218,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [361] = {
+ [523] = {
.class_hid = BNXT_ULP_CLASS_HID_1dd0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131072,
.flow_pattern_id = 0,
@@ -7244,12 +11237,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [362] = {
+ [524] = {
.class_hid = BNXT_ULP_CLASS_HID_14f4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131076,
.flow_pattern_id = 0,
@@ -7260,13 +11253,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [363] = {
+ [525] = {
.class_hid = BNXT_ULP_CLASS_HID_70b0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131136,
.flow_pattern_id = 0,
@@ -7277,13 +11270,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [364] = {
+ [526] = {
.class_hid = BNXT_ULP_CLASS_HID_4854,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131140,
.flow_pattern_id = 0,
@@ -7294,14 +11287,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [365] = {
+ [527] = {
.class_hid = BNXT_ULP_CLASS_HID_3dd4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196608,
.flow_pattern_id = 0,
@@ -7312,13 +11305,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [366] = {
+ [528] = {
.class_hid = BNXT_ULP_CLASS_HID_34f8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196612,
.flow_pattern_id = 0,
@@ -7329,14 +11322,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [367] = {
+ [529] = {
.class_hid = BNXT_ULP_CLASS_HID_09e8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196672,
.flow_pattern_id = 0,
@@ -7347,14 +11340,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [368] = {
+ [530] = {
.class_hid = BNXT_ULP_CLASS_HID_008c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196676,
.flow_pattern_id = 0,
@@ -7365,15 +11358,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [369] = {
+ [531] = {
.class_hid = BNXT_ULP_CLASS_HID_34e6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 4096,
.flow_pattern_id = 0,
@@ -7384,12 +11377,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [370] = {
+ [532] = {
.class_hid = BNXT_ULP_CLASS_HID_0c02,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 4100,
.flow_pattern_id = 0,
@@ -7400,13 +11393,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [371] = {
+ [533] = {
.class_hid = BNXT_ULP_CLASS_HID_1c9e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 6144,
.flow_pattern_id = 0,
@@ -7417,13 +11410,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [372] = {
+ [534] = {
.class_hid = BNXT_ULP_CLASS_HID_17ba,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 6148,
.flow_pattern_id = 0,
@@ -7434,14 +11427,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [373] = {
+ [535] = {
.class_hid = BNXT_ULP_CLASS_HID_429e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 12288,
.flow_pattern_id = 0,
@@ -7452,13 +11445,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [374] = {
+ [536] = {
.class_hid = BNXT_ULP_CLASS_HID_5dba,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 12292,
.flow_pattern_id = 0,
@@ -7469,14 +11462,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [375] = {
+ [537] = {
.class_hid = BNXT_ULP_CLASS_HID_2a16,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 14336,
.flow_pattern_id = 0,
@@ -7487,14 +11480,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [376] = {
+ [538] = {
.class_hid = BNXT_ULP_CLASS_HID_2532,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 14340,
.flow_pattern_id = 0,
@@ -7505,15 +11498,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [377] = {
+ [539] = {
.class_hid = BNXT_ULP_CLASS_HID_2da2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 20480,
.flow_pattern_id = 0,
@@ -7524,13 +11517,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [378] = {
+ [540] = {
.class_hid = BNXT_ULP_CLASS_HID_24fe,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 20484,
.flow_pattern_id = 0,
@@ -7541,14 +11534,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [379] = {
+ [541] = {
.class_hid = BNXT_ULP_CLASS_HID_355a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 22528,
.flow_pattern_id = 0,
@@ -7559,14 +11552,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [380] = {
+ [542] = {
.class_hid = BNXT_ULP_CLASS_HID_0c76,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 22532,
.flow_pattern_id = 0,
@@ -7577,15 +11570,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [381] = {
+ [543] = {
.class_hid = BNXT_ULP_CLASS_HID_13e6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 28672,
.flow_pattern_id = 0,
@@ -7596,14 +11589,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [382] = {
+ [544] = {
.class_hid = BNXT_ULP_CLASS_HID_7276,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 28676,
.flow_pattern_id = 0,
@@ -7614,15 +11607,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [383] = {
+ [545] = {
.class_hid = BNXT_ULP_CLASS_HID_42d2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 30720,
.flow_pattern_id = 0,
@@ -7633,15 +11626,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [384] = {
+ [546] = {
.class_hid = BNXT_ULP_CLASS_HID_5dee,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 30724,
.flow_pattern_id = 0,
@@ -7652,16 +11645,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [385] = {
+ [547] = {
.class_hid = BNXT_ULP_CLASS_HID_59de,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 16384,
.flow_pattern_id = 0,
@@ -7672,12 +11665,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [386] = {
+ [548] = {
.class_hid = BNXT_ULP_CLASS_HID_513a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 16388,
.flow_pattern_id = 0,
@@ -7688,13 +11681,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [387] = {
+ [549] = {
.class_hid = BNXT_ULP_CLASS_HID_1c12,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 24576,
.flow_pattern_id = 0,
@@ -7705,13 +11698,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [388] = {
+ [550] = {
.class_hid = BNXT_ULP_CLASS_HID_177e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 24580,
.flow_pattern_id = 0,
@@ -7722,14 +11715,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [389] = {
+ [551] = {
.class_hid = BNXT_ULP_CLASS_HID_0e92,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 49152,
.flow_pattern_id = 0,
@@ -7740,13 +11733,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [390] = {
+ [552] = {
.class_hid = BNXT_ULP_CLASS_HID_09fe,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 49156,
.flow_pattern_id = 0,
@@ -7757,14 +11750,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [391] = {
+ [553] = {
.class_hid = BNXT_ULP_CLASS_HID_5c1a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 57344,
.flow_pattern_id = 0,
@@ -7775,14 +11768,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [392] = {
+ [554] = {
.class_hid = BNXT_ULP_CLASS_HID_5746,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 57348,
.flow_pattern_id = 0,
@@ -7793,15 +11786,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [393] = {
+ [555] = {
.class_hid = BNXT_ULP_CLASS_HID_79da,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 81920,
.flow_pattern_id = 0,
@@ -7812,13 +11805,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [394] = {
+ [556] = {
.class_hid = BNXT_ULP_CLASS_HID_7106,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 81924,
.flow_pattern_id = 0,
@@ -7829,14 +11822,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [395] = {
+ [557] = {
.class_hid = BNXT_ULP_CLASS_HID_3c1e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 90112,
.flow_pattern_id = 0,
@@ -7847,14 +11840,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [396] = {
+ [558] = {
.class_hid = BNXT_ULP_CLASS_HID_377a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 90116,
.flow_pattern_id = 0,
@@ -7865,15 +11858,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [397] = {
+ [559] = {
.class_hid = BNXT_ULP_CLASS_HID_2e9e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 114688,
.flow_pattern_id = 0,
@@ -7884,14 +11877,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [398] = {
+ [560] = {
.class_hid = BNXT_ULP_CLASS_HID_29fa,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 114692,
.flow_pattern_id = 0,
@@ -7902,15 +11895,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [399] = {
+ [561] = {
.class_hid = BNXT_ULP_CLASS_HID_14d2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 122880,
.flow_pattern_id = 0,
@@ -7921,15 +11914,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [400] = {
+ [562] = {
.class_hid = BNXT_ULP_CLASS_HID_7742,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 122884,
.flow_pattern_id = 0,
@@ -7940,16 +11933,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [401] = {
+ [563] = {
.class_hid = BNXT_ULP_CLASS_HID_3706,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 4096,
.flow_pattern_id = 0,
@@ -7960,12 +11953,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [402] = {
+ [564] = {
.class_hid = BNXT_ULP_CLASS_HID_0fe2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 4100,
.flow_pattern_id = 0,
@@ -7976,13 +11969,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [403] = {
+ [565] = {
.class_hid = BNXT_ULP_CLASS_HID_1f7e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 6144,
.flow_pattern_id = 0,
@@ -7993,13 +11986,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [404] = {
+ [566] = {
.class_hid = BNXT_ULP_CLASS_HID_145a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 6148,
.flow_pattern_id = 0,
@@ -8010,14 +12003,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [405] = {
+ [567] = {
.class_hid = BNXT_ULP_CLASS_HID_417e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 12288,
.flow_pattern_id = 0,
@@ -8028,13 +12021,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [406] = {
+ [568] = {
.class_hid = BNXT_ULP_CLASS_HID_5e5a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 12292,
.flow_pattern_id = 0,
@@ -8045,14 +12038,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [407] = {
+ [569] = {
.class_hid = BNXT_ULP_CLASS_HID_29f6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 14336,
.flow_pattern_id = 0,
@@ -8063,14 +12056,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [408] = {
+ [570] = {
.class_hid = BNXT_ULP_CLASS_HID_26d2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 14340,
.flow_pattern_id = 0,
@@ -8081,15 +12074,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [409] = {
+ [571] = {
.class_hid = BNXT_ULP_CLASS_HID_2e42,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 20480,
.flow_pattern_id = 0,
@@ -8100,13 +12093,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [410] = {
+ [572] = {
.class_hid = BNXT_ULP_CLASS_HID_271e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 20484,
.flow_pattern_id = 0,
@@ -8117,14 +12110,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [411] = {
+ [573] = {
.class_hid = BNXT_ULP_CLASS_HID_36ba,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 22528,
.flow_pattern_id = 0,
@@ -8135,14 +12128,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [412] = {
+ [574] = {
.class_hid = BNXT_ULP_CLASS_HID_0f96,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 22532,
.flow_pattern_id = 0,
@@ -8153,15 +12146,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [413] = {
+ [575] = {
.class_hid = BNXT_ULP_CLASS_HID_1006,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 28672,
.flow_pattern_id = 0,
@@ -8172,14 +12165,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [414] = {
+ [576] = {
.class_hid = BNXT_ULP_CLASS_HID_7196,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 28676,
.flow_pattern_id = 0,
@@ -8190,15 +12183,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [415] = {
+ [577] = {
.class_hid = BNXT_ULP_CLASS_HID_4132,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 30720,
.flow_pattern_id = 0,
@@ -8209,15 +12202,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [416] = {
+ [578] = {
.class_hid = BNXT_ULP_CLASS_HID_5e0e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 30724,
.flow_pattern_id = 0,
@@ -8228,16 +12221,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [417] = {
+ [579] = {
.class_hid = BNXT_ULP_CLASS_HID_59fe,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 16384,
.flow_pattern_id = 0,
@@ -8248,12 +12241,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [418] = {
+ [580] = {
.class_hid = BNXT_ULP_CLASS_HID_511a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 16388,
.flow_pattern_id = 0,
@@ -8264,13 +12257,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [419] = {
+ [581] = {
.class_hid = BNXT_ULP_CLASS_HID_1c32,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 24576,
.flow_pattern_id = 0,
@@ -8281,13 +12274,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [420] = {
+ [582] = {
.class_hid = BNXT_ULP_CLASS_HID_175e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 24580,
.flow_pattern_id = 0,
@@ -8298,14 +12291,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [421] = {
+ [583] = {
.class_hid = BNXT_ULP_CLASS_HID_0eb2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 49152,
.flow_pattern_id = 0,
@@ -8316,13 +12309,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [422] = {
+ [584] = {
.class_hid = BNXT_ULP_CLASS_HID_09de,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 49156,
.flow_pattern_id = 0,
@@ -8333,14 +12326,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [423] = {
+ [585] = {
.class_hid = BNXT_ULP_CLASS_HID_5c3a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 57344,
.flow_pattern_id = 0,
@@ -8351,14 +12344,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [424] = {
+ [586] = {
.class_hid = BNXT_ULP_CLASS_HID_5766,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 57348,
.flow_pattern_id = 0,
@@ -8369,15 +12362,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [425] = {
+ [587] = {
.class_hid = BNXT_ULP_CLASS_HID_79fa,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 81920,
.flow_pattern_id = 0,
@@ -8388,13 +12381,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [426] = {
+ [588] = {
.class_hid = BNXT_ULP_CLASS_HID_7126,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 81924,
.flow_pattern_id = 0,
@@ -8405,14 +12398,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [427] = {
+ [589] = {
.class_hid = BNXT_ULP_CLASS_HID_3c3e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 90112,
.flow_pattern_id = 0,
@@ -8423,14 +12416,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [428] = {
+ [590] = {
.class_hid = BNXT_ULP_CLASS_HID_375a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 90116,
.flow_pattern_id = 0,
@@ -8441,15 +12434,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [429] = {
+ [591] = {
.class_hid = BNXT_ULP_CLASS_HID_2ebe,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 114688,
.flow_pattern_id = 0,
@@ -8460,14 +12453,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [430] = {
+ [592] = {
.class_hid = BNXT_ULP_CLASS_HID_29da,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 114692,
.flow_pattern_id = 0,
@@ -8478,15 +12471,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [431] = {
+ [593] = {
.class_hid = BNXT_ULP_CLASS_HID_14f2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 122880,
.flow_pattern_id = 0,
@@ -8497,15 +12490,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [432] = {
+ [594] = {
.class_hid = BNXT_ULP_CLASS_HID_7762,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 122884,
.flow_pattern_id = 0,
@@ -8516,16 +12509,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [433] = {
+ [595] = {
.class_hid = BNXT_ULP_CLASS_HID_19e8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32768,
.flow_pattern_id = 0,
@@ -8537,12 +12530,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [434] = {
+ [596] = {
.class_hid = BNXT_ULP_CLASS_HID_110c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32772,
.flow_pattern_id = 0,
@@ -8554,13 +12547,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [435] = {
+ [597] = {
.class_hid = BNXT_ULP_CLASS_HID_4d48,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32832,
.flow_pattern_id = 0,
@@ -8572,13 +12565,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [436] = {
+ [598] = {
.class_hid = BNXT_ULP_CLASS_HID_446c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32836,
.flow_pattern_id = 0,
@@ -8590,14 +12583,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [437] = {
+ [599] = {
.class_hid = BNXT_ULP_CLASS_HID_0eac,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49152,
.flow_pattern_id = 0,
@@ -8609,13 +12602,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [438] = {
+ [600] = {
.class_hid = BNXT_ULP_CLASS_HID_09c0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49156,
.flow_pattern_id = 0,
@@ -8627,14 +12620,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [439] = {
+ [601] = {
.class_hid = BNXT_ULP_CLASS_HID_1ad0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49216,
.flow_pattern_id = 0,
@@ -8646,14 +12639,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [440] = {
+ [602] = {
.class_hid = BNXT_ULP_CLASS_HID_15f4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49220,
.flow_pattern_id = 0,
@@ -8665,15 +12658,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [441] = {
+ [603] = {
.class_hid = BNXT_ULP_CLASS_HID_39ec,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98304,
.flow_pattern_id = 0,
@@ -8685,13 +12678,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [442] = {
+ [604] = {
.class_hid = BNXT_ULP_CLASS_HID_3100,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98308,
.flow_pattern_id = 0,
@@ -8703,14 +12696,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [443] = {
+ [605] = {
.class_hid = BNXT_ULP_CLASS_HID_0210,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98368,
.flow_pattern_id = 0,
@@ -8722,14 +12715,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [444] = {
+ [606] = {
.class_hid = BNXT_ULP_CLASS_HID_1d34,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98372,
.flow_pattern_id = 0,
@@ -8741,15 +12734,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [445] = {
+ [607] = {
.class_hid = BNXT_ULP_CLASS_HID_2ea0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114688,
.flow_pattern_id = 0,
@@ -8761,14 +12754,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [446] = {
+ [608] = {
.class_hid = BNXT_ULP_CLASS_HID_29c4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114692,
.flow_pattern_id = 0,
@@ -8780,15 +12773,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [447] = {
+ [609] = {
.class_hid = BNXT_ULP_CLASS_HID_3ad4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114752,
.flow_pattern_id = 0,
@@ -8800,15 +12793,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [448] = {
+ [610] = {
.class_hid = BNXT_ULP_CLASS_HID_35e8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114756,
.flow_pattern_id = 0,
@@ -8820,16 +12813,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [449] = {
+ [611] = {
.class_hid = BNXT_ULP_CLASS_HID_5d80,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163840,
.flow_pattern_id = 0,
@@ -8841,13 +12834,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [450] = {
+ [612] = {
.class_hid = BNXT_ULP_CLASS_HID_54a4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163844,
.flow_pattern_id = 0,
@@ -8859,14 +12852,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [451] = {
+ [613] = {
.class_hid = BNXT_ULP_CLASS_HID_29b4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163904,
.flow_pattern_id = 0,
@@ -8878,14 +12871,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [452] = {
+ [614] = {
.class_hid = BNXT_ULP_CLASS_HID_20c8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163908,
.flow_pattern_id = 0,
@@ -8897,15 +12890,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [453] = {
+ [615] = {
.class_hid = BNXT_ULP_CLASS_HID_7244,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180224,
.flow_pattern_id = 0,
@@ -8917,14 +12910,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [454] = {
+ [616] = {
.class_hid = BNXT_ULP_CLASS_HID_4d98,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180228,
.flow_pattern_id = 0,
@@ -8936,15 +12929,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [455] = {
+ [617] = {
.class_hid = BNXT_ULP_CLASS_HID_5e68,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180288,
.flow_pattern_id = 0,
@@ -8956,15 +12949,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [456] = {
+ [618] = {
.class_hid = BNXT_ULP_CLASS_HID_598c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180292,
.flow_pattern_id = 0,
@@ -8976,16 +12969,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [457] = {
+ [619] = {
.class_hid = BNXT_ULP_CLASS_HID_1248,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229376,
.flow_pattern_id = 0,
@@ -8997,14 +12990,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [458] = {
+ [620] = {
.class_hid = BNXT_ULP_CLASS_HID_74d8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229380,
.flow_pattern_id = 0,
@@ -9016,15 +13009,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [459] = {
+ [621] = {
.class_hid = BNXT_ULP_CLASS_HID_49a8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229440,
.flow_pattern_id = 0,
@@ -9036,15 +13029,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [460] = {
+ [622] = {
.class_hid = BNXT_ULP_CLASS_HID_40cc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229444,
.flow_pattern_id = 0,
@@ -9056,16 +13049,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [461] = {
+ [623] = {
.class_hid = BNXT_ULP_CLASS_HID_0b0c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245760,
.flow_pattern_id = 0,
@@ -9077,15 +13070,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [462] = {
+ [624] = {
.class_hid = BNXT_ULP_CLASS_HID_0220,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245764,
.flow_pattern_id = 0,
@@ -9097,16 +13090,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [463] = {
+ [625] = {
.class_hid = BNXT_ULP_CLASS_HID_1730,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245824,
.flow_pattern_id = 0,
@@ -9118,16 +13111,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [464] = {
+ [626] = {
.class_hid = BNXT_ULP_CLASS_HID_7980,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245828,
.flow_pattern_id = 0,
@@ -9139,17 +13132,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [465] = {
+ [627] = {
.class_hid = BNXT_ULP_CLASS_HID_1db0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131072,
.flow_pattern_id = 0,
@@ -9161,12 +13154,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [466] = {
+ [628] = {
.class_hid = BNXT_ULP_CLASS_HID_1494,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131076,
.flow_pattern_id = 0,
@@ -9178,13 +13171,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [467] = {
+ [629] = {
.class_hid = BNXT_ULP_CLASS_HID_70d0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131136,
.flow_pattern_id = 0,
@@ -9196,13 +13189,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [468] = {
+ [630] = {
.class_hid = BNXT_ULP_CLASS_HID_4834,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131140,
.flow_pattern_id = 0,
@@ -9214,14 +13207,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [469] = {
+ [631] = {
.class_hid = BNXT_ULP_CLASS_HID_3db4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196608,
.flow_pattern_id = 0,
@@ -9233,13 +13226,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [470] = {
+ [632] = {
.class_hid = BNXT_ULP_CLASS_HID_3498,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196612,
.flow_pattern_id = 0,
@@ -9251,14 +13244,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [471] = {
+ [633] = {
.class_hid = BNXT_ULP_CLASS_HID_0988,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196672,
.flow_pattern_id = 0,
@@ -9270,14 +13263,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [472] = {
+ [634] = {
.class_hid = BNXT_ULP_CLASS_HID_00ec,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196676,
.flow_pattern_id = 0,
@@ -9289,15 +13282,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [473] = {
+ [635] = {
.class_hid = BNXT_ULP_CLASS_HID_3f44,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393216,
.flow_pattern_id = 0,
@@ -9309,13 +13302,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [474] = {
+ [636] = {
.class_hid = BNXT_ULP_CLASS_HID_36a8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393220,
.flow_pattern_id = 0,
@@ -9327,14 +13320,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [475] = {
+ [637] = {
.class_hid = BNXT_ULP_CLASS_HID_0b58,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393280,
.flow_pattern_id = 0,
@@ -9346,14 +13339,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [476] = {
+ [638] = {
.class_hid = BNXT_ULP_CLASS_HID_02bc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393284,
.flow_pattern_id = 0,
@@ -9365,15 +13358,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [477] = {
+ [639] = {
.class_hid = BNXT_ULP_CLASS_HID_5f48,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458752,
.flow_pattern_id = 0,
@@ -9385,14 +13378,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [478] = {
+ [640] = {
.class_hid = BNXT_ULP_CLASS_HID_56ac,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458756,
.flow_pattern_id = 0,
@@ -9404,15 +13397,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [479] = {
+ [641] = {
.class_hid = BNXT_ULP_CLASS_HID_2b5c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458816,
.flow_pattern_id = 0,
@@ -9424,15 +13417,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [480] = {
+ [642] = {
.class_hid = BNXT_ULP_CLASS_HID_2280,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458820,
.flow_pattern_id = 0,
@@ -9444,16 +13437,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [481] = {
+ [643] = {
.class_hid = BNXT_ULP_CLASS_HID_4000,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655360,
.flow_pattern_id = 0,
@@ -9465,13 +13458,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [482] = {
+ [644] = {
.class_hid = BNXT_ULP_CLASS_HID_5b64,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655364,
.flow_pattern_id = 0,
@@ -9483,14 +13476,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [483] = {
+ [645] = {
.class_hid = BNXT_ULP_CLASS_HID_2c14,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655424,
.flow_pattern_id = 0,
@@ -9502,14 +13495,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [484] = {
+ [646] = {
.class_hid = BNXT_ULP_CLASS_HID_2778,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655428,
.flow_pattern_id = 0,
@@ -9521,15 +13514,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [485] = {
+ [647] = {
.class_hid = BNXT_ULP_CLASS_HID_18f8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720896,
.flow_pattern_id = 0,
@@ -9541,14 +13534,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [486] = {
+ [648] = {
.class_hid = BNXT_ULP_CLASS_HID_13dc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720900,
.flow_pattern_id = 0,
@@ -9560,15 +13553,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [487] = {
+ [649] = {
.class_hid = BNXT_ULP_CLASS_HID_4c18,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720960,
.flow_pattern_id = 0,
@@ -9580,15 +13573,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [488] = {
+ [650] = {
.class_hid = BNXT_ULP_CLASS_HID_477c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720964,
.flow_pattern_id = 0,
@@ -9600,16 +13593,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [489] = {
+ [651] = {
.class_hid = BNXT_ULP_CLASS_HID_1a88,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917504,
.flow_pattern_id = 0,
@@ -9621,14 +13614,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [490] = {
+ [652] = {
.class_hid = BNXT_ULP_CLASS_HID_15ec,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917508,
.flow_pattern_id = 0,
@@ -9640,15 +13633,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [491] = {
+ [653] = {
.class_hid = BNXT_ULP_CLASS_HID_4e28,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917568,
.flow_pattern_id = 0,
@@ -9660,15 +13653,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [492] = {
+ [654] = {
.class_hid = BNXT_ULP_CLASS_HID_490c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917572,
.flow_pattern_id = 0,
@@ -9680,16 +13673,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [493] = {
+ [655] = {
.class_hid = BNXT_ULP_CLASS_HID_3a8c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983040,
.flow_pattern_id = 0,
@@ -9701,15 +13694,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [494] = {
+ [656] = {
.class_hid = BNXT_ULP_CLASS_HID_35f0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983044,
.flow_pattern_id = 0,
@@ -9721,16 +13714,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [495] = {
+ [657] = {
.class_hid = BNXT_ULP_CLASS_HID_06e0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983104,
.flow_pattern_id = 0,
@@ -9742,16 +13735,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [496] = {
+ [658] = {
.class_hid = BNXT_ULP_CLASS_HID_01c4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983108,
.flow_pattern_id = 0,
@@ -9763,17 +13756,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [497] = {
+ [659] = {
.class_hid = BNXT_ULP_CLASS_HID_1a08,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32768,
.flow_pattern_id = 0,
@@ -9785,12 +13778,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [498] = {
+ [660] = {
.class_hid = BNXT_ULP_CLASS_HID_12ec,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32772,
.flow_pattern_id = 0,
@@ -9802,13 +13795,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [499] = {
+ [661] = {
.class_hid = BNXT_ULP_CLASS_HID_4ea8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32832,
.flow_pattern_id = 0,
@@ -9820,13 +13813,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [500] = {
+ [662] = {
.class_hid = BNXT_ULP_CLASS_HID_478c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32836,
.flow_pattern_id = 0,
@@ -9838,14 +13831,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [501] = {
+ [663] = {
.class_hid = BNXT_ULP_CLASS_HID_0d4c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49152,
.flow_pattern_id = 0,
@@ -9857,13 +13850,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [502] = {
+ [664] = {
.class_hid = BNXT_ULP_CLASS_HID_0a20,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49156,
.flow_pattern_id = 0,
@@ -9875,14 +13868,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [503] = {
+ [665] = {
.class_hid = BNXT_ULP_CLASS_HID_1930,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49216,
.flow_pattern_id = 0,
@@ -9894,14 +13887,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [504] = {
+ [666] = {
.class_hid = BNXT_ULP_CLASS_HID_1614,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49220,
.flow_pattern_id = 0,
@@ -9913,15 +13906,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [505] = {
+ [667] = {
.class_hid = BNXT_ULP_CLASS_HID_3a0c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98304,
.flow_pattern_id = 0,
@@ -9933,13 +13926,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [506] = {
+ [668] = {
.class_hid = BNXT_ULP_CLASS_HID_32e0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98308,
.flow_pattern_id = 0,
@@ -9951,14 +13944,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [507] = {
+ [669] = {
.class_hid = BNXT_ULP_CLASS_HID_01f0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98368,
.flow_pattern_id = 0,
@@ -9970,14 +13963,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [508] = {
+ [670] = {
.class_hid = BNXT_ULP_CLASS_HID_1ed4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98372,
.flow_pattern_id = 0,
@@ -9989,15 +13982,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [509] = {
+ [671] = {
.class_hid = BNXT_ULP_CLASS_HID_2d40,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114688,
.flow_pattern_id = 0,
@@ -10009,14 +14002,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [510] = {
+ [672] = {
.class_hid = BNXT_ULP_CLASS_HID_2a24,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114692,
.flow_pattern_id = 0,
@@ -10028,15 +14021,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [511] = {
+ [673] = {
.class_hid = BNXT_ULP_CLASS_HID_3934,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114752,
.flow_pattern_id = 0,
@@ -10048,15 +14041,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [512] = {
+ [674] = {
.class_hid = BNXT_ULP_CLASS_HID_3608,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114756,
.flow_pattern_id = 0,
@@ -10068,16 +14061,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [513] = {
+ [675] = {
.class_hid = BNXT_ULP_CLASS_HID_5e60,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163840,
.flow_pattern_id = 0,
@@ -10089,13 +14082,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [514] = {
+ [676] = {
.class_hid = BNXT_ULP_CLASS_HID_5744,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163844,
.flow_pattern_id = 0,
@@ -10107,14 +14100,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [515] = {
+ [677] = {
.class_hid = BNXT_ULP_CLASS_HID_2a54,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163904,
.flow_pattern_id = 0,
@@ -10126,14 +14119,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [516] = {
+ [678] = {
.class_hid = BNXT_ULP_CLASS_HID_2328,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163908,
.flow_pattern_id = 0,
@@ -10145,15 +14138,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [517] = {
+ [679] = {
.class_hid = BNXT_ULP_CLASS_HID_71a4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180224,
.flow_pattern_id = 0,
@@ -10165,14 +14158,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [518] = {
+ [680] = {
.class_hid = BNXT_ULP_CLASS_HID_4e78,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180228,
.flow_pattern_id = 0,
@@ -10184,15 +14177,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [519] = {
+ [681] = {
.class_hid = BNXT_ULP_CLASS_HID_5d88,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180288,
.flow_pattern_id = 0,
@@ -10204,15 +14197,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [520] = {
+ [682] = {
.class_hid = BNXT_ULP_CLASS_HID_5a6c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180292,
.flow_pattern_id = 0,
@@ -10224,16 +14217,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [521] = {
+ [683] = {
.class_hid = BNXT_ULP_CLASS_HID_11a8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229376,
.flow_pattern_id = 0,
@@ -10245,14 +14238,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [522] = {
+ [684] = {
.class_hid = BNXT_ULP_CLASS_HID_7738,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229380,
.flow_pattern_id = 0,
@@ -10264,15 +14257,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [523] = {
+ [685] = {
.class_hid = BNXT_ULP_CLASS_HID_4a48,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229440,
.flow_pattern_id = 0,
@@ -10284,15 +14277,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [524] = {
+ [686] = {
.class_hid = BNXT_ULP_CLASS_HID_432c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229444,
.flow_pattern_id = 0,
@@ -10304,16 +14297,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [525] = {
+ [687] = {
.class_hid = BNXT_ULP_CLASS_HID_08ec,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245760,
.flow_pattern_id = 0,
@@ -10325,15 +14318,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [526] = {
+ [688] = {
.class_hid = BNXT_ULP_CLASS_HID_01c0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245764,
.flow_pattern_id = 0,
@@ -10345,16 +14338,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [527] = {
+ [689] = {
.class_hid = BNXT_ULP_CLASS_HID_14d0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245824,
.flow_pattern_id = 0,
@@ -10366,16 +14359,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [528] = {
+ [690] = {
.class_hid = BNXT_ULP_CLASS_HID_7a60,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245828,
.flow_pattern_id = 0,
@@ -10387,17 +14380,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [529] = {
+ [691] = {
.class_hid = BNXT_ULP_CLASS_HID_1d90,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131072,
.flow_pattern_id = 0,
@@ -10409,12 +14402,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [530] = {
+ [692] = {
.class_hid = BNXT_ULP_CLASS_HID_14b4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131076,
.flow_pattern_id = 0,
@@ -10426,13 +14419,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [531] = {
+ [693] = {
.class_hid = BNXT_ULP_CLASS_HID_70f0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131136,
.flow_pattern_id = 0,
@@ -10444,13 +14437,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [532] = {
+ [694] = {
.class_hid = BNXT_ULP_CLASS_HID_4814,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131140,
.flow_pattern_id = 0,
@@ -10462,14 +14455,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [533] = {
+ [695] = {
.class_hid = BNXT_ULP_CLASS_HID_3d94,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196608,
.flow_pattern_id = 0,
@@ -10481,13 +14474,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [534] = {
+ [696] = {
.class_hid = BNXT_ULP_CLASS_HID_34b8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196612,
.flow_pattern_id = 0,
@@ -10499,14 +14492,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [535] = {
+ [697] = {
.class_hid = BNXT_ULP_CLASS_HID_09a8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196672,
.flow_pattern_id = 0,
@@ -10518,14 +14511,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [536] = {
+ [698] = {
.class_hid = BNXT_ULP_CLASS_HID_00cc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196676,
.flow_pattern_id = 0,
@@ -10537,15 +14530,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [537] = {
+ [699] = {
.class_hid = BNXT_ULP_CLASS_HID_3f64,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393216,
.flow_pattern_id = 0,
@@ -10557,13 +14550,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [538] = {
+ [700] = {
.class_hid = BNXT_ULP_CLASS_HID_3688,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393220,
.flow_pattern_id = 0,
@@ -10575,14 +14568,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [539] = {
+ [701] = {
.class_hid = BNXT_ULP_CLASS_HID_0b78,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393280,
.flow_pattern_id = 0,
@@ -10594,14 +14587,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [540] = {
+ [702] = {
.class_hid = BNXT_ULP_CLASS_HID_029c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393284,
.flow_pattern_id = 0,
@@ -10613,15 +14606,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [541] = {
+ [703] = {
.class_hid = BNXT_ULP_CLASS_HID_5f68,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458752,
.flow_pattern_id = 0,
@@ -10633,14 +14626,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [542] = {
+ [704] = {
.class_hid = BNXT_ULP_CLASS_HID_568c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458756,
.flow_pattern_id = 0,
@@ -10652,15 +14645,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [543] = {
+ [705] = {
.class_hid = BNXT_ULP_CLASS_HID_2b7c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458816,
.flow_pattern_id = 0,
@@ -10672,15 +14665,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [544] = {
+ [706] = {
.class_hid = BNXT_ULP_CLASS_HID_22a0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458820,
.flow_pattern_id = 0,
@@ -10692,16 +14685,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [545] = {
+ [707] = {
.class_hid = BNXT_ULP_CLASS_HID_4020,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655360,
.flow_pattern_id = 0,
@@ -10713,13 +14706,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [546] = {
+ [708] = {
.class_hid = BNXT_ULP_CLASS_HID_5b44,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655364,
.flow_pattern_id = 0,
@@ -10731,14 +14724,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [547] = {
+ [709] = {
.class_hid = BNXT_ULP_CLASS_HID_2c34,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655424,
.flow_pattern_id = 0,
@@ -10750,14 +14743,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [548] = {
+ [710] = {
.class_hid = BNXT_ULP_CLASS_HID_2758,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655428,
.flow_pattern_id = 0,
@@ -10769,15 +14762,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [549] = {
+ [711] = {
.class_hid = BNXT_ULP_CLASS_HID_18d8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720896,
.flow_pattern_id = 0,
@@ -10789,14 +14782,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [550] = {
+ [712] = {
.class_hid = BNXT_ULP_CLASS_HID_13fc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720900,
.flow_pattern_id = 0,
@@ -10808,15 +14801,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [551] = {
+ [713] = {
.class_hid = BNXT_ULP_CLASS_HID_4c38,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720960,
.flow_pattern_id = 0,
@@ -10828,15 +14821,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [552] = {
+ [714] = {
.class_hid = BNXT_ULP_CLASS_HID_475c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720964,
.flow_pattern_id = 0,
@@ -10848,16 +14841,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [553] = {
+ [715] = {
.class_hid = BNXT_ULP_CLASS_HID_1aa8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917504,
.flow_pattern_id = 0,
@@ -10869,14 +14862,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [554] = {
+ [716] = {
.class_hid = BNXT_ULP_CLASS_HID_15cc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917508,
.flow_pattern_id = 0,
@@ -10888,15 +14881,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [555] = {
+ [717] = {
.class_hid = BNXT_ULP_CLASS_HID_4e08,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917568,
.flow_pattern_id = 0,
@@ -10908,15 +14901,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [556] = {
+ [718] = {
.class_hid = BNXT_ULP_CLASS_HID_492c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917572,
.flow_pattern_id = 0,
@@ -10928,16 +14921,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [557] = {
+ [719] = {
.class_hid = BNXT_ULP_CLASS_HID_3aac,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983040,
.flow_pattern_id = 0,
@@ -10949,15 +14942,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [558] = {
+ [720] = {
.class_hid = BNXT_ULP_CLASS_HID_35d0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983044,
.flow_pattern_id = 0,
@@ -10969,16 +14962,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [559] = {
+ [721] = {
.class_hid = BNXT_ULP_CLASS_HID_06c0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983104,
.flow_pattern_id = 0,
@@ -10990,16 +14983,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [560] = {
+ [722] = {
.class_hid = BNXT_ULP_CLASS_HID_01e4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983108,
.flow_pattern_id = 0,
@@ -11011,17 +15004,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [561] = {
+ [723] = {
.class_hid = BNXT_ULP_CLASS_HID_4d32,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 4096,
.flow_pattern_id = 1,
@@ -11031,11 +15024,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [562] = {
+ [724] = {
.class_hid = BNXT_ULP_CLASS_HID_54aa,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 6144,
.flow_pattern_id = 1,
@@ -11045,12 +15038,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [563] = {
+ [725] = {
.class_hid = BNXT_ULP_CLASS_HID_0686,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 16384,
.flow_pattern_id = 1,
@@ -11060,11 +15053,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [564] = {
+ [726] = {
.class_hid = BNXT_ULP_CLASS_HID_540e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 24576,
.flow_pattern_id = 1,
@@ -11074,12 +15067,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [565] = {
+ [727] = {
.class_hid = BNXT_ULP_CLASS_HID_2e3c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32768,
.flow_pattern_id = 1,
@@ -11090,11 +15083,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [566] = {
+ [728] = {
.class_hid = BNXT_ULP_CLASS_HID_3a20,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32832,
.flow_pattern_id = 1,
@@ -11105,12 +15098,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [567] = {
+ [729] = {
.class_hid = BNXT_ULP_CLASS_HID_46f0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49152,
.flow_pattern_id = 1,
@@ -11121,12 +15114,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [568] = {
+ [730] = {
.class_hid = BNXT_ULP_CLASS_HID_52e4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49216,
.flow_pattern_id = 1,
@@ -11137,13 +15130,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [569] = {
+ [731] = {
.class_hid = BNXT_ULP_CLASS_HID_55e4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131072,
.flow_pattern_id = 1,
@@ -11154,11 +15147,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [570] = {
+ [732] = {
.class_hid = BNXT_ULP_CLASS_HID_21f8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131136,
.flow_pattern_id = 1,
@@ -11169,12 +15162,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [571] = {
+ [733] = {
.class_hid = BNXT_ULP_CLASS_HID_75e8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196608,
.flow_pattern_id = 1,
@@ -11185,12 +15178,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [572] = {
+ [734] = {
.class_hid = BNXT_ULP_CLASS_HID_41fc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196672,
.flow_pattern_id = 1,
@@ -11201,13 +15194,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [573] = {
+ [735] = {
.class_hid = BNXT_ULP_CLASS_HID_4d12,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 4096,
.flow_pattern_id = 1,
@@ -11218,11 +15211,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [574] = {
+ [736] = {
.class_hid = BNXT_ULP_CLASS_HID_548a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 6144,
.flow_pattern_id = 1,
@@ -11233,12 +15226,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [575] = {
+ [737] = {
.class_hid = BNXT_ULP_CLASS_HID_3356,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 12288,
.flow_pattern_id = 1,
@@ -11249,12 +15242,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [576] = {
+ [738] = {
.class_hid = BNXT_ULP_CLASS_HID_1ace,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 14336,
.flow_pattern_id = 1,
@@ -11265,13 +15258,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [577] = {
+ [739] = {
.class_hid = BNXT_ULP_CLASS_HID_1a9a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 20480,
.flow_pattern_id = 1,
@@ -11282,12 +15275,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [578] = {
+ [740] = {
.class_hid = BNXT_ULP_CLASS_HID_4d46,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 22528,
.flow_pattern_id = 1,
@@ -11298,13 +15291,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [579] = {
+ [741] = {
.class_hid = BNXT_ULP_CLASS_HID_2812,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 28672,
.flow_pattern_id = 1,
@@ -11315,13 +15308,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [580] = {
+ [742] = {
.class_hid = BNXT_ULP_CLASS_HID_338a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 30720,
.flow_pattern_id = 1,
@@ -11332,14 +15325,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [581] = {
+ [743] = {
.class_hid = BNXT_ULP_CLASS_HID_06e6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 16384,
.flow_pattern_id = 1,
@@ -11350,11 +15343,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [582] = {
+ [744] = {
.class_hid = BNXT_ULP_CLASS_HID_546e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 24576,
.flow_pattern_id = 1,
@@ -11365,12 +15358,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [583] = {
+ [745] = {
.class_hid = BNXT_ULP_CLASS_HID_46ee,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 49152,
.flow_pattern_id = 1,
@@ -11381,12 +15374,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [584] = {
+ [746] = {
.class_hid = BNXT_ULP_CLASS_HID_0d22,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 57344,
.flow_pattern_id = 1,
@@ -11397,13 +15390,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [585] = {
+ [747] = {
.class_hid = BNXT_ULP_CLASS_HID_26e2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 81920,
.flow_pattern_id = 1,
@@ -11414,12 +15407,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [586] = {
+ [748] = {
.class_hid = BNXT_ULP_CLASS_HID_746a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 90112,
.flow_pattern_id = 1,
@@ -11430,13 +15423,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [587] = {
+ [749] = {
.class_hid = BNXT_ULP_CLASS_HID_1fa6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 114688,
.flow_pattern_id = 1,
@@ -11447,13 +15440,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [588] = {
+ [750] = {
.class_hid = BNXT_ULP_CLASS_HID_2d2e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 122880,
.flow_pattern_id = 1,
@@ -11464,14 +15457,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [589] = {
+ [751] = {
.class_hid = BNXT_ULP_CLASS_HID_4ef2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 4096,
.flow_pattern_id = 1,
@@ -11482,11 +15475,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [590] = {
+ [752] = {
.class_hid = BNXT_ULP_CLASS_HID_576a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 6144,
.flow_pattern_id = 1,
@@ -11497,12 +15490,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [591] = {
+ [753] = {
.class_hid = BNXT_ULP_CLASS_HID_30b6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 12288,
.flow_pattern_id = 1,
@@ -11513,12 +15506,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [592] = {
+ [754] = {
.class_hid = BNXT_ULP_CLASS_HID_192e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 14336,
.flow_pattern_id = 1,
@@ -11529,13 +15522,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [593] = {
+ [755] = {
.class_hid = BNXT_ULP_CLASS_HID_197a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 20480,
.flow_pattern_id = 1,
@@ -11546,12 +15539,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [594] = {
+ [756] = {
.class_hid = BNXT_ULP_CLASS_HID_4ea6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 22528,
.flow_pattern_id = 1,
@@ -11562,13 +15555,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [595] = {
+ [757] = {
.class_hid = BNXT_ULP_CLASS_HID_2bf2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 28672,
.flow_pattern_id = 1,
@@ -11579,13 +15572,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [596] = {
+ [758] = {
.class_hid = BNXT_ULP_CLASS_HID_306a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 30720,
.flow_pattern_id = 1,
@@ -11596,14 +15589,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [597] = {
+ [759] = {
.class_hid = BNXT_ULP_CLASS_HID_06c6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 16384,
.flow_pattern_id = 1,
@@ -11614,11 +15607,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [598] = {
+ [760] = {
.class_hid = BNXT_ULP_CLASS_HID_544e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 24576,
.flow_pattern_id = 1,
@@ -11629,12 +15622,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [599] = {
+ [761] = {
.class_hid = BNXT_ULP_CLASS_HID_46ce,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 49152,
.flow_pattern_id = 1,
@@ -11645,12 +15638,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [600] = {
+ [762] = {
.class_hid = BNXT_ULP_CLASS_HID_0d02,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 57344,
.flow_pattern_id = 1,
@@ -11661,13 +15654,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [601] = {
+ [763] = {
.class_hid = BNXT_ULP_CLASS_HID_26c2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 81920,
.flow_pattern_id = 1,
@@ -11678,12 +15671,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [602] = {
+ [764] = {
.class_hid = BNXT_ULP_CLASS_HID_744a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 90112,
.flow_pattern_id = 1,
@@ -11694,13 +15687,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [603] = {
+ [765] = {
.class_hid = BNXT_ULP_CLASS_HID_1f86,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 114688,
.flow_pattern_id = 1,
@@ -11711,13 +15704,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [604] = {
+ [766] = {
.class_hid = BNXT_ULP_CLASS_HID_2d0e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 122880,
.flow_pattern_id = 1,
@@ -11728,14 +15721,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [605] = {
+ [767] = {
.class_hid = BNXT_ULP_CLASS_HID_2e1c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32768,
.flow_pattern_id = 1,
@@ -11747,11 +15740,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [606] = {
+ [768] = {
.class_hid = BNXT_ULP_CLASS_HID_3a00,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32832,
.flow_pattern_id = 1,
@@ -11763,12 +15756,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [607] = {
+ [769] = {
.class_hid = BNXT_ULP_CLASS_HID_46d0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49152,
.flow_pattern_id = 1,
@@ -11780,12 +15773,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [608] = {
+ [770] = {
.class_hid = BNXT_ULP_CLASS_HID_52c4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49216,
.flow_pattern_id = 1,
@@ -11797,13 +15790,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [609] = {
+ [771] = {
.class_hid = BNXT_ULP_CLASS_HID_4e10,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98304,
.flow_pattern_id = 1,
@@ -11815,12 +15808,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [610] = {
+ [772] = {
.class_hid = BNXT_ULP_CLASS_HID_5a04,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98368,
.flow_pattern_id = 1,
@@ -11832,13 +15825,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [611] = {
+ [773] = {
.class_hid = BNXT_ULP_CLASS_HID_1f98,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114688,
.flow_pattern_id = 1,
@@ -11850,13 +15843,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [612] = {
+ [774] = {
.class_hid = BNXT_ULP_CLASS_HID_72f8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114752,
.flow_pattern_id = 1,
@@ -11868,14 +15861,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [613] = {
+ [775] = {
.class_hid = BNXT_ULP_CLASS_HID_0a78,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163840,
.flow_pattern_id = 1,
@@ -11887,12 +15880,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [614] = {
+ [776] = {
.class_hid = BNXT_ULP_CLASS_HID_166c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163904,
.flow_pattern_id = 1,
@@ -11904,13 +15897,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [615] = {
+ [777] = {
.class_hid = BNXT_ULP_CLASS_HID_233c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180224,
.flow_pattern_id = 1,
@@ -11922,13 +15915,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [616] = {
+ [778] = {
.class_hid = BNXT_ULP_CLASS_HID_0f20,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180288,
.flow_pattern_id = 1,
@@ -11940,14 +15933,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [617] = {
+ [779] = {
.class_hid = BNXT_ULP_CLASS_HID_2a7c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229376,
.flow_pattern_id = 1,
@@ -11959,13 +15952,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [618] = {
+ [780] = {
.class_hid = BNXT_ULP_CLASS_HID_3660,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229440,
.flow_pattern_id = 1,
@@ -11977,14 +15970,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [619] = {
+ [781] = {
.class_hid = BNXT_ULP_CLASS_HID_4330,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245760,
.flow_pattern_id = 1,
@@ -11996,14 +15989,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [620] = {
+ [782] = {
.class_hid = BNXT_ULP_CLASS_HID_2f24,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245824,
.flow_pattern_id = 1,
@@ -12015,15 +16008,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [621] = {
+ [783] = {
.class_hid = BNXT_ULP_CLASS_HID_5584,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131072,
.flow_pattern_id = 1,
@@ -12035,11 +16028,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [622] = {
+ [784] = {
.class_hid = BNXT_ULP_CLASS_HID_2198,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131136,
.flow_pattern_id = 1,
@@ -12051,12 +16044,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [623] = {
+ [785] = {
.class_hid = BNXT_ULP_CLASS_HID_7588,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196608,
.flow_pattern_id = 1,
@@ -12068,12 +16061,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [624] = {
+ [786] = {
.class_hid = BNXT_ULP_CLASS_HID_419c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196672,
.flow_pattern_id = 1,
@@ -12085,13 +16078,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [625] = {
+ [787] = {
.class_hid = BNXT_ULP_CLASS_HID_7758,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393216,
.flow_pattern_id = 1,
@@ -12103,12 +16096,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [626] = {
+ [788] = {
.class_hid = BNXT_ULP_CLASS_HID_43ac,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393280,
.flow_pattern_id = 1,
@@ -12120,13 +16113,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [627] = {
+ [789] = {
.class_hid = BNXT_ULP_CLASS_HID_0c10,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458752,
.flow_pattern_id = 1,
@@ -12138,13 +16131,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [628] = {
+ [790] = {
.class_hid = BNXT_ULP_CLASS_HID_1864,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458816,
.flow_pattern_id = 1,
@@ -12156,14 +16149,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [629] = {
+ [791] = {
.class_hid = BNXT_ULP_CLASS_HID_30c8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655360,
.flow_pattern_id = 1,
@@ -12175,12 +16168,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [630] = {
+ [792] = {
.class_hid = BNXT_ULP_CLASS_HID_1cdc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655424,
.flow_pattern_id = 1,
@@ -12192,13 +16185,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [631] = {
+ [793] = {
.class_hid = BNXT_ULP_CLASS_HID_50cc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720896,
.flow_pattern_id = 1,
@@ -12210,13 +16203,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [632] = {
+ [794] = {
.class_hid = BNXT_ULP_CLASS_HID_3d20,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720960,
.flow_pattern_id = 1,
@@ -12228,14 +16221,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [633] = {
+ [795] = {
.class_hid = BNXT_ULP_CLASS_HID_529c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917504,
.flow_pattern_id = 1,
@@ -12247,13 +16240,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [634] = {
+ [796] = {
.class_hid = BNXT_ULP_CLASS_HID_3ef0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917568,
.flow_pattern_id = 1,
@@ -12265,14 +16258,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [635] = {
+ [797] = {
.class_hid = BNXT_ULP_CLASS_HID_72e0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983040,
.flow_pattern_id = 1,
@@ -12284,14 +16277,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [636] = {
+ [798] = {
.class_hid = BNXT_ULP_CLASS_HID_5ef4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983104,
.flow_pattern_id = 1,
@@ -12303,15 +16296,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [637] = {
+ [799] = {
.class_hid = BNXT_ULP_CLASS_HID_2dfc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32768,
.flow_pattern_id = 1,
@@ -12323,11 +16316,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [638] = {
+ [800] = {
.class_hid = BNXT_ULP_CLASS_HID_39e0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32832,
.flow_pattern_id = 1,
@@ -12339,12 +16332,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [639] = {
+ [801] = {
.class_hid = BNXT_ULP_CLASS_HID_4530,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49152,
.flow_pattern_id = 1,
@@ -12356,12 +16349,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [640] = {
+ [802] = {
.class_hid = BNXT_ULP_CLASS_HID_5124,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49216,
.flow_pattern_id = 1,
@@ -12373,13 +16366,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [641] = {
+ [803] = {
.class_hid = BNXT_ULP_CLASS_HID_4df0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98304,
.flow_pattern_id = 1,
@@ -12391,12 +16384,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [642] = {
+ [804] = {
.class_hid = BNXT_ULP_CLASS_HID_59e4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98368,
.flow_pattern_id = 1,
@@ -12408,13 +16401,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [643] = {
+ [805] = {
.class_hid = BNXT_ULP_CLASS_HID_1c78,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114688,
.flow_pattern_id = 1,
@@ -12426,13 +16419,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [644] = {
+ [806] = {
.class_hid = BNXT_ULP_CLASS_HID_7118,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114752,
.flow_pattern_id = 1,
@@ -12444,14 +16437,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [645] = {
+ [807] = {
.class_hid = BNXT_ULP_CLASS_HID_0998,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163840,
.flow_pattern_id = 1,
@@ -12463,12 +16456,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [646] = {
+ [808] = {
.class_hid = BNXT_ULP_CLASS_HID_158c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163904,
.flow_pattern_id = 1,
@@ -12480,13 +16473,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [647] = {
+ [809] = {
.class_hid = BNXT_ULP_CLASS_HID_20dc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180224,
.flow_pattern_id = 1,
@@ -12498,13 +16491,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [648] = {
+ [810] = {
.class_hid = BNXT_ULP_CLASS_HID_0cc0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180288,
.flow_pattern_id = 1,
@@ -12516,14 +16509,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [649] = {
+ [811] = {
.class_hid = BNXT_ULP_CLASS_HID_299c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229376,
.flow_pattern_id = 1,
@@ -12535,13 +16528,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [650] = {
+ [812] = {
.class_hid = BNXT_ULP_CLASS_HID_3580,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229440,
.flow_pattern_id = 1,
@@ -12553,14 +16546,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [651] = {
+ [813] = {
.class_hid = BNXT_ULP_CLASS_HID_40d0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245760,
.flow_pattern_id = 1,
@@ -12572,14 +16565,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [652] = {
+ [814] = {
.class_hid = BNXT_ULP_CLASS_HID_2cc4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245824,
.flow_pattern_id = 1,
@@ -12591,15 +16584,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [653] = {
+ [815] = {
.class_hid = BNXT_ULP_CLASS_HID_55a4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131072,
.flow_pattern_id = 1,
@@ -12611,11 +16604,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [654] = {
+ [816] = {
.class_hid = BNXT_ULP_CLASS_HID_21b8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131136,
.flow_pattern_id = 1,
@@ -12627,12 +16620,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [655] = {
+ [817] = {
.class_hid = BNXT_ULP_CLASS_HID_75a8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196608,
.flow_pattern_id = 1,
@@ -12644,12 +16637,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [656] = {
+ [818] = {
.class_hid = BNXT_ULP_CLASS_HID_41bc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196672,
.flow_pattern_id = 1,
@@ -12661,13 +16654,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [657] = {
+ [819] = {
.class_hid = BNXT_ULP_CLASS_HID_7778,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393216,
.flow_pattern_id = 1,
@@ -12679,12 +16672,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [658] = {
+ [820] = {
.class_hid = BNXT_ULP_CLASS_HID_438c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393280,
.flow_pattern_id = 1,
@@ -12696,13 +16689,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [659] = {
+ [821] = {
.class_hid = BNXT_ULP_CLASS_HID_0c30,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458752,
.flow_pattern_id = 1,
@@ -12714,13 +16707,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [660] = {
+ [822] = {
.class_hid = BNXT_ULP_CLASS_HID_1844,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458816,
.flow_pattern_id = 1,
@@ -12732,14 +16725,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [661] = {
+ [823] = {
.class_hid = BNXT_ULP_CLASS_HID_30e8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655360,
.flow_pattern_id = 1,
@@ -12751,12 +16744,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [662] = {
+ [824] = {
.class_hid = BNXT_ULP_CLASS_HID_1cfc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655424,
.flow_pattern_id = 1,
@@ -12768,13 +16761,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [663] = {
+ [825] = {
.class_hid = BNXT_ULP_CLASS_HID_50ec,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720896,
.flow_pattern_id = 1,
@@ -12786,13 +16779,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [664] = {
+ [826] = {
.class_hid = BNXT_ULP_CLASS_HID_3d00,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720960,
.flow_pattern_id = 1,
@@ -12804,14 +16797,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [665] = {
+ [827] = {
.class_hid = BNXT_ULP_CLASS_HID_52bc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917504,
.flow_pattern_id = 1,
@@ -12823,13 +16816,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [666] = {
+ [828] = {
.class_hid = BNXT_ULP_CLASS_HID_3ed0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917568,
.flow_pattern_id = 1,
@@ -12841,14 +16834,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [667] = {
+ [829] = {
.class_hid = BNXT_ULP_CLASS_HID_72c0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983040,
.flow_pattern_id = 1,
@@ -12860,14 +16853,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [668] = {
+ [830] = {
.class_hid = BNXT_ULP_CLASS_HID_5ed4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983104,
.flow_pattern_id = 1,
@@ -12879,15 +16872,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [669] = {
+ [831] = {
.class_hid = BNXT_ULP_CLASS_HID_3866,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -12897,12 +16890,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC }
},
- [670] = {
+ [832] = {
.class_hid = BNXT_ULP_CLASS_HID_381e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -12912,12 +16905,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC }
},
- [671] = {
+ [833] = {
.class_hid = BNXT_ULP_CLASS_HID_3860,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -12928,12 +16921,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC }
},
- [672] = {
+ [834] = {
.class_hid = BNXT_ULP_CLASS_HID_0454,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 68,
.flow_pattern_id = 2,
@@ -12944,13 +16937,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID }
},
- [673] = {
+ [835] = {
.class_hid = BNXT_ULP_CLASS_HID_3818,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -12961,12 +16954,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC }
},
- [674] = {
+ [836] = {
.class_hid = BNXT_ULP_CLASS_HID_042c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 68,
.flow_pattern_id = 2,
@@ -12977,13 +16970,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID }
},
- [675] = {
+ [837] = {
.class_hid = BNXT_ULP_CLASS_HID_3846,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -12994,12 +16987,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC }
},
- [676] = {
+ [838] = {
.class_hid = BNXT_ULP_CLASS_HID_387e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -13010,12 +17003,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC }
},
- [677] = {
+ [839] = {
.class_hid = BNXT_ULP_CLASS_HID_3ba6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -13026,12 +17019,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC }
},
- [678] = {
+ [840] = {
.class_hid = BNXT_ULP_CLASS_HID_385e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -13042,12 +17035,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC }
},
- [679] = {
+ [841] = {
.class_hid = BNXT_ULP_CLASS_HID_3840,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -13059,12 +17052,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC }
},
- [680] = {
+ [842] = {
.class_hid = BNXT_ULP_CLASS_HID_0474,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 68,
.flow_pattern_id = 2,
@@ -13076,13 +17069,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID }
},
- [681] = {
+ [843] = {
.class_hid = BNXT_ULP_CLASS_HID_3878,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -13094,12 +17087,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC }
},
- [682] = {
+ [844] = {
.class_hid = BNXT_ULP_CLASS_HID_044c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 68,
.flow_pattern_id = 2,
@@ -13111,13 +17104,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID }
},
- [683] = {
+ [845] = {
.class_hid = BNXT_ULP_CLASS_HID_3ba0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -13129,12 +17122,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC }
},
- [684] = {
+ [846] = {
.class_hid = BNXT_ULP_CLASS_HID_0794,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 68,
.flow_pattern_id = 2,
@@ -13146,13 +17139,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID }
},
- [685] = {
+ [847] = {
.class_hid = BNXT_ULP_CLASS_HID_3858,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -13164,12 +17157,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC }
},
- [686] = {
+ [848] = {
.class_hid = BNXT_ULP_CLASS_HID_046c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 68,
.flow_pattern_id = 2,
@@ -13181,8 +17174,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID }
}
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
index b6db49cc5d..e55d0923a5 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 13 18:15:56 2021 */
+/* date: Thu May 20 11:56:39 2021 */
#ifndef ULP_TEMPLATE_DB_H_
#define ULP_TEMPLATE_DB_H_
@@ -11,13 +11,13 @@
#define BNXT_ULP_REGFILE_MAX_SZ 40
#define BNXT_ULP_MAX_NUM_DEVICES 4
#define BNXT_ULP_LOG2_MAX_NUM_DEV 2
-#define BNXT_ULP_GEN_TBL_MAX_SZ 10
+#define BNXT_ULP_GEN_TBL_MAX_SZ 12
#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 32768
-#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 687
+#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 849
#define BNXT_ULP_CLASS_HID_LOW_PRIME 6701
#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907
-#define BNXT_ULP_CLASS_HID_SHFTR 23
-#define BNXT_ULP_CLASS_HID_SHFTL 23
+#define BNXT_ULP_CLASS_HID_SHFTR 24
+#define BNXT_ULP_CLASS_HID_SHFTL 24
#define BNXT_ULP_CLASS_HID_MASK 32767
#define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048
#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 86
@@ -36,14 +36,14 @@
#define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7
#define BNXT_ULP_HDR_SIG_ID_SHIFT 4
#define BNXT_ULP_APP_ID_SHIFT 4
-#define BNXT_ULP_GLB_FIELD_TBL_SIZE 5595
-#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 5
-#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 74
-#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 495
-#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 20
-#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 546
-#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 43
-#define ULP_THOR_CLASS_TMPL_LIST_SIZE 5
+#define BNXT_ULP_GLB_FIELD_TBL_SIZE 7643
+#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 6
+#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 89
+#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 600
+#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 26
+#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 619
+#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 49
+#define ULP_THOR_CLASS_TMPL_LIST_SIZE 6
#define ULP_THOR_CLASS_TBL_LIST_SIZE 33
#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 242
#define ULP_THOR_CLASS_IDENT_LIST_SIZE 8
@@ -113,7 +113,8 @@ enum bnxt_ulp_hdr_bit {
BNXT_ULP_HDR_BIT_I_UDP = 0x0000000000010000,
BNXT_ULP_HDR_BIT_I_ICMP = 0x0000000000020000,
BNXT_ULP_HDR_BIT_F1 = 0x0000000000040000,
- BNXT_ULP_HDR_BIT_LAST = 0x0000000000080000
+ BNXT_ULP_HDR_BIT_F2 = 0x0000000000080000,
+ BNXT_ULP_HDR_BIT_LAST = 0x0000000000100000
};
enum bnxt_ulp_accept_opc {
@@ -199,8 +200,10 @@ enum bnxt_ulp_cf_idx {
BNXT_ULP_CF_IDX_FLOW_SIG_ID = 60,
BNXT_ULP_CF_IDX_WC_MATCH = 61,
BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG = 62,
- BNXT_ULP_CF_IDX_F1_DMAC = 63,
- BNXT_ULP_CF_IDX_LAST = 64
+ BNXT_ULP_CF_IDX_TUNNEL_ID = 63,
+ BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID = 64,
+ BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID = 65,
+ BNXT_ULP_CF_IDX_LAST = 66
};
enum bnxt_ulp_cond_list_opc {
@@ -315,7 +318,8 @@ enum bnxt_ulp_func_opc {
BNXT_ULP_FUNC_OPC_COPY_SRC1_TO_RF = 7,
BNXT_ULP_FUNC_OPC_RSS_CONFIG = 8,
BNXT_ULP_FUNC_OPC_GET_PARENT_MAC_ADDR = 9,
- BNXT_ULP_FUNC_OPC_LAST = 10
+ BNXT_ULP_FUNC_OPC_ALLOC_L2_CTX_ID = 10,
+ BNXT_ULP_FUNC_OPC_LAST = 11
};
enum bnxt_ulp_func_src {
@@ -497,7 +501,8 @@ enum bnxt_ulp_tcam_tbl_opc {
BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE = 2,
BNXT_ULP_TCAM_TBL_OPC_ALLOC_REGFILE = 3,
BNXT_ULP_TCAM_TBL_OPC_WR_REGFILE = 4,
- BNXT_ULP_TCAM_TBL_OPC_LAST = 5
+ BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT = 5,
+ BNXT_ULP_TCAM_TBL_OPC_LAST = 6
};
enum bnxt_ulp_template_type {
@@ -549,7 +554,8 @@ enum bnxt_ulp_resource_sub_type {
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM = 1,
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR = 2,
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE = 3,
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE = 4
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE = 4,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE = 5
};
enum bnxt_ulp_act_prop_sz {
@@ -1443,6 +1449,168 @@ enum bnxt_ulp_class_hid {
BNXT_ULP_CLASS_HID_15db = 0x15db,
BNXT_ULP_CLASS_HID_1151 = 0x1151,
BNXT_ULP_CLASS_HID_315d = 0x315d,
+ BNXT_ULP_CLASS_HID_3612 = 0x3612,
+ BNXT_ULP_CLASS_HID_66da = 0x66da,
+ BNXT_ULP_CLASS_HID_6165 = 0x6165,
+ BNXT_ULP_CLASS_HID_2aa1 = 0x2aa1,
+ BNXT_ULP_CLASS_HID_09cd = 0x09cd,
+ BNXT_ULP_CLASS_HID_3845 = 0x3845,
+ BNXT_ULP_CLASS_HID_11e9 = 0x11e9,
+ BNXT_ULP_CLASS_HID_4361 = 0x4361,
+ BNXT_ULP_CLASS_HID_218d = 0x218d,
+ BNXT_ULP_CLASS_HID_5105 = 0x5105,
+ BNXT_ULP_CLASS_HID_0c89 = 0x0c89,
+ BNXT_ULP_CLASS_HID_3e81 = 0x3e81,
+ BNXT_ULP_CLASS_HID_1dad = 0x1dad,
+ BNXT_ULP_CLASS_HID_4ca5 = 0x4ca5,
+ BNXT_ULP_CLASS_HID_25c9 = 0x25c9,
+ BNXT_ULP_CLASS_HID_57c1 = 0x57c1,
+ BNXT_ULP_CLASS_HID_33ed = 0x33ed,
+ BNXT_ULP_CLASS_HID_65e5 = 0x65e5,
+ BNXT_ULP_CLASS_HID_6dd9 = 0x6dd9,
+ BNXT_ULP_CLASS_HID_261d = 0x261d,
+ BNXT_ULP_CLASS_HID_0571 = 0x0571,
+ BNXT_ULP_CLASS_HID_34f9 = 0x34f9,
+ BNXT_ULP_CLASS_HID_1d55 = 0x1d55,
+ BNXT_ULP_CLASS_HID_4fdd = 0x4fdd,
+ BNXT_ULP_CLASS_HID_2d31 = 0x2d31,
+ BNXT_ULP_CLASS_HID_5db9 = 0x5db9,
+ BNXT_ULP_CLASS_HID_0035 = 0x0035,
+ BNXT_ULP_CLASS_HID_323d = 0x323d,
+ BNXT_ULP_CLASS_HID_1111 = 0x1111,
+ BNXT_ULP_CLASS_HID_4019 = 0x4019,
+ BNXT_ULP_CLASS_HID_2975 = 0x2975,
+ BNXT_ULP_CLASS_HID_5b7d = 0x5b7d,
+ BNXT_ULP_CLASS_HID_3f51 = 0x3f51,
+ BNXT_ULP_CLASS_HID_6959 = 0x6959,
+ BNXT_ULP_CLASS_HID_0e85 = 0x0e85,
+ BNXT_ULP_CLASS_HID_380d = 0x380d,
+ BNXT_ULP_CLASS_HID_1f21 = 0x1f21,
+ BNXT_ULP_CLASS_HID_4ea9 = 0x4ea9,
+ BNXT_ULP_CLASS_HID_1705 = 0x1705,
+ BNXT_ULP_CLASS_HID_418d = 0x418d,
+ BNXT_ULP_CLASS_HID_2721 = 0x2721,
+ BNXT_ULP_CLASS_HID_57a9 = 0x57a9,
+ BNXT_ULP_CLASS_HID_1a25 = 0x1a25,
+ BNXT_ULP_CLASS_HID_342d = 0x342d,
+ BNXT_ULP_CLASS_HID_2b01 = 0x2b01,
+ BNXT_ULP_CLASS_HID_5a09 = 0x5a09,
+ BNXT_ULP_CLASS_HID_2325 = 0x2325,
+ BNXT_ULP_CLASS_HID_5d2d = 0x5d2d,
+ BNXT_ULP_CLASS_HID_3101 = 0x3101,
+ BNXT_ULP_CLASS_HID_6309 = 0x6309,
+ BNXT_ULP_CLASS_HID_0bad = 0x0bad,
+ BNXT_ULP_CLASS_HID_2535 = 0x2535,
+ BNXT_ULP_CLASS_HID_1869 = 0x1869,
+ BNXT_ULP_CLASS_HID_4bf1 = 0x4bf1,
+ BNXT_ULP_CLASS_HID_136d = 0x136d,
+ BNXT_ULP_CLASS_HID_43f5 = 0x43f5,
+ BNXT_ULP_CLASS_HID_2129 = 0x2129,
+ BNXT_ULP_CLASS_HID_53b1 = 0x53b1,
+ BNXT_ULP_CLASS_HID_072d = 0x072d,
+ BNXT_ULP_CLASS_HID_3135 = 0x3135,
+ BNXT_ULP_CLASS_HID_1429 = 0x1429,
+ BNXT_ULP_CLASS_HID_4731 = 0x4731,
+ BNXT_ULP_CLASS_HID_2f6d = 0x2f6d,
+ BNXT_ULP_CLASS_HID_5f75 = 0x5f75,
+ BNXT_ULP_CLASS_HID_3d69 = 0x3d69,
+ BNXT_ULP_CLASS_HID_6f71 = 0x6f71,
+ BNXT_ULP_CLASS_HID_0dbd = 0x0dbd,
+ BNXT_ULP_CLASS_HID_3f25 = 0x3f25,
+ BNXT_ULP_CLASS_HID_1239 = 0x1239,
+ BNXT_ULP_CLASS_HID_4da1 = 0x4da1,
+ BNXT_ULP_CLASS_HID_153d = 0x153d,
+ BNXT_ULP_CLASS_HID_45a5 = 0x45a5,
+ BNXT_ULP_CLASS_HID_3bb9 = 0x3bb9,
+ BNXT_ULP_CLASS_HID_55a1 = 0x55a1,
+ BNXT_ULP_CLASS_HID_193d = 0x193d,
+ BNXT_ULP_CLASS_HID_4b25 = 0x4b25,
+ BNXT_ULP_CLASS_HID_2e39 = 0x2e39,
+ BNXT_ULP_CLASS_HID_5921 = 0x5921,
+ BNXT_ULP_CLASS_HID_213d = 0x213d,
+ BNXT_ULP_CLASS_HID_5125 = 0x5125,
+ BNXT_ULP_CLASS_HID_3739 = 0x3739,
+ BNXT_ULP_CLASS_HID_093d = 0x093d,
+ BNXT_ULP_CLASS_HID_684d = 0x684d,
+ BNXT_ULP_CLASS_HID_2389 = 0x2389,
+ BNXT_ULP_CLASS_HID_00e5 = 0x00e5,
+ BNXT_ULP_CLASS_HID_316d = 0x316d,
+ BNXT_ULP_CLASS_HID_18c1 = 0x18c1,
+ BNXT_ULP_CLASS_HID_4a49 = 0x4a49,
+ BNXT_ULP_CLASS_HID_28a5 = 0x28a5,
+ BNXT_ULP_CLASS_HID_582d = 0x582d,
+ BNXT_ULP_CLASS_HID_05a1 = 0x05a1,
+ BNXT_ULP_CLASS_HID_37a9 = 0x37a9,
+ BNXT_ULP_CLASS_HID_1485 = 0x1485,
+ BNXT_ULP_CLASS_HID_458d = 0x458d,
+ BNXT_ULP_CLASS_HID_2ce1 = 0x2ce1,
+ BNXT_ULP_CLASS_HID_5ee9 = 0x5ee9,
+ BNXT_ULP_CLASS_HID_3ac5 = 0x3ac5,
+ BNXT_ULP_CLASS_HID_6ccd = 0x6ccd,
+ BNXT_ULP_CLASS_HID_0b11 = 0x0b11,
+ BNXT_ULP_CLASS_HID_3d99 = 0x3d99,
+ BNXT_ULP_CLASS_HID_1ab5 = 0x1ab5,
+ BNXT_ULP_CLASS_HID_4b3d = 0x4b3d,
+ BNXT_ULP_CLASS_HID_1291 = 0x1291,
+ BNXT_ULP_CLASS_HID_4419 = 0x4419,
+ BNXT_ULP_CLASS_HID_22b5 = 0x22b5,
+ BNXT_ULP_CLASS_HID_523d = 0x523d,
+ BNXT_ULP_CLASS_HID_1fb1 = 0x1fb1,
+ BNXT_ULP_CLASS_HID_31b9 = 0x31b9,
+ BNXT_ULP_CLASS_HID_2e95 = 0x2e95,
+ BNXT_ULP_CLASS_HID_5f9d = 0x5f9d,
+ BNXT_ULP_CLASS_HID_26b1 = 0x26b1,
+ BNXT_ULP_CLASS_HID_58b9 = 0x58b9,
+ BNXT_ULP_CLASS_HID_3495 = 0x3495,
+ BNXT_ULP_CLASS_HID_669d = 0x669d,
+ BNXT_ULP_CLASS_HID_0e39 = 0x0e39,
+ BNXT_ULP_CLASS_HID_20a1 = 0x20a1,
+ BNXT_ULP_CLASS_HID_1dfd = 0x1dfd,
+ BNXT_ULP_CLASS_HID_4e65 = 0x4e65,
+ BNXT_ULP_CLASS_HID_16f9 = 0x16f9,
+ BNXT_ULP_CLASS_HID_4661 = 0x4661,
+ BNXT_ULP_CLASS_HID_24bd = 0x24bd,
+ BNXT_ULP_CLASS_HID_5625 = 0x5625,
+ BNXT_ULP_CLASS_HID_02b9 = 0x02b9,
+ BNXT_ULP_CLASS_HID_34a1 = 0x34a1,
+ BNXT_ULP_CLASS_HID_11bd = 0x11bd,
+ BNXT_ULP_CLASS_HID_42a5 = 0x42a5,
+ BNXT_ULP_CLASS_HID_2af9 = 0x2af9,
+ BNXT_ULP_CLASS_HID_5ae1 = 0x5ae1,
+ BNXT_ULP_CLASS_HID_38fd = 0x38fd,
+ BNXT_ULP_CLASS_HID_6ae5 = 0x6ae5,
+ BNXT_ULP_CLASS_HID_0829 = 0x0829,
+ BNXT_ULP_CLASS_HID_3ab1 = 0x3ab1,
+ BNXT_ULP_CLASS_HID_17ad = 0x17ad,
+ BNXT_ULP_CLASS_HID_4835 = 0x4835,
+ BNXT_ULP_CLASS_HID_10a9 = 0x10a9,
+ BNXT_ULP_CLASS_HID_4031 = 0x4031,
+ BNXT_ULP_CLASS_HID_3e2d = 0x3e2d,
+ BNXT_ULP_CLASS_HID_5035 = 0x5035,
+ BNXT_ULP_CLASS_HID_1ca9 = 0x1ca9,
+ BNXT_ULP_CLASS_HID_4eb1 = 0x4eb1,
+ BNXT_ULP_CLASS_HID_2bad = 0x2bad,
+ BNXT_ULP_CLASS_HID_5cb5 = 0x5cb5,
+ BNXT_ULP_CLASS_HID_24a9 = 0x24a9,
+ BNXT_ULP_CLASS_HID_54b1 = 0x54b1,
+ BNXT_ULP_CLASS_HID_32ad = 0x32ad,
+ BNXT_ULP_CLASS_HID_0ca9 = 0x0ca9,
+ BNXT_ULP_CLASS_HID_7f35 = 0x7f35,
+ BNXT_ULP_CLASS_HID_34f1 = 0x34f1,
+ BNXT_ULP_CLASS_HID_179d = 0x179d,
+ BNXT_ULP_CLASS_HID_2615 = 0x2615,
+ BNXT_ULP_CLASS_HID_0fb9 = 0x0fb9,
+ BNXT_ULP_CLASS_HID_5d31 = 0x5d31,
+ BNXT_ULP_CLASS_HID_3fdd = 0x3fdd,
+ BNXT_ULP_CLASS_HID_4f55 = 0x4f55,
+ BNXT_ULP_CLASS_HID_12d9 = 0x12d9,
+ BNXT_ULP_CLASS_HID_20d1 = 0x20d1,
+ BNXT_ULP_CLASS_HID_03fd = 0x03fd,
+ BNXT_ULP_CLASS_HID_52f5 = 0x52f5,
+ BNXT_ULP_CLASS_HID_3b99 = 0x3b99,
+ BNXT_ULP_CLASS_HID_4991 = 0x4991,
+ BNXT_ULP_CLASS_HID_2dbd = 0x2dbd,
+ BNXT_ULP_CLASS_HID_7bb5 = 0x7bb5,
BNXT_ULP_CLASS_HID_34c6 = 0x34c6,
BNXT_ULP_CLASS_HID_0c22 = 0x0c22,
BNXT_ULP_CLASS_HID_1cbe = 0x1cbe,
@@ -1876,8 +2044,8 @@ enum bnxt_ulp_act_hid {
};
enum bnxt_ulp_df_tpl {
- BNXT_ULP_DF_TPL_DEFAULT_UPLINK_PORT = 3,
- BNXT_ULP_DF_TPL_DEFAULT_VFR = 4
+ BNXT_ULP_DF_TPL_DEFAULT_UPLINK_PORT = 4,
+ BNXT_ULP_DF_TPL_DEFAULT_VFR = 5
};
#endif
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h
index 115bdc644c..1d7bbfe2cc 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Wed Mar 17 11:31:19 2021 */
+/* date: Thu May 20 11:56:39 2021 */
#ifndef ULP_HDR_FIELD_ENUMS_H_
#define ULP_HDR_FIELD_ENUMS_H_
@@ -415,272 +415,460 @@ enum bnxt_ulp_hf_0_2_0_bitmask {
BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_VER = 0x0400000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_TC = 0x0200000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_TTL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_TOS = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_LEN = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_LENGTH = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_CSUM = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_FLAGS = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_RSVD0 = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_VNI = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_RSVD1 = 0x0000020000000000
};
enum bnxt_ulp_hf_0_2_1_bitmask {
BNXT_ULP_HF_0_2_1_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_VER = 0x0400000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TOS = 0x0200000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_LEN = 0x0100000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TTL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000
};
enum bnxt_ulp_hf_0_2_2_bitmask {
BNXT_ULP_HF_0_2_2_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID = 0x0200000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_VER = 0x0080000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_TC = 0x0040000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_TTL = 0x0004000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SENT_SEQ = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_RECV_ACK = 0x0000000008000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DATA_OFF = 0x0000000004000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_TCP_FLAGS = 0x0000000002000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_RX_WIN = 0x0000000001000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_CSUM = 0x0000000000800000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_URP = 0x0000000000400000
};
enum bnxt_ulp_hf_0_2_3_bitmask {
BNXT_ULP_HF_0_2_3_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID = 0x0200000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_VER = 0x0080000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TOS = 0x0040000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_LEN = 0x0020000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TTL = 0x0004000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_LENGTH = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_CSUM = 0x0000000008000000
};
enum bnxt_ulp_hf_0_2_4_bitmask {
BNXT_ULP_HF_0_2_4_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_VER = 0x0400000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_TC = 0x0200000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_TTL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT = 0x0004000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT = 0x0002000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SENT_SEQ = 0x0001000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_RECV_ACK = 0x0000800000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DATA_OFF = 0x0000400000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_TCP_FLAGS = 0x0000200000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_RX_WIN = 0x0000100000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_CSUM = 0x0000080000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_URP = 0x0000040000000000
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_TYPE = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_CODE = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_CSUM = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_IDENT = 0x0000000008000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_SEQ_NUM = 0x0000000004000000
};
-enum bnxt_ulp_hf_0_2_5_bitmask {
- BNXT_ULP_HF_0_2_5_BITMASK_WM = 0x8000000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_VER = 0x0400000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_TOS = 0x0200000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_LEN = 0x0100000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_TTL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT = 0x0000800000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_RX_WIN = 0x0000040000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_CSUM = 0x0000020000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_URP = 0x0000010000000000
+enum bnxt_ulp_hf_0_3_0_bitmask {
+ BNXT_ULP_HF_0_3_0_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_TC = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000
};
-enum bnxt_ulp_hf_0_2_6_bitmask {
- BNXT_ULP_HF_0_2_6_BITMASK_WM = 0x8000000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_VER = 0x0400000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_TC = 0x0200000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_TTL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT = 0x0002000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_LENGTH = 0x0001000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_CSUM = 0x0000800000000000
+enum bnxt_ulp_hf_0_3_1_bitmask {
+ BNXT_ULP_HF_0_3_1_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_TOS = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_LEN = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000
};
-enum bnxt_ulp_hf_0_2_7_bitmask {
- BNXT_ULP_HF_0_2_7_BITMASK_WM = 0x8000000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_VER = 0x0400000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_TOS = 0x0200000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_LEN = 0x0100000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_TTL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT = 0x0000800000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_LENGTH = 0x0000400000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_CSUM = 0x0000200000000000
+enum bnxt_ulp_hf_0_3_2_bitmask {
+ BNXT_ULP_HF_0_3_2_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_VER = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_TC = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_TTL = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000
};
-enum bnxt_ulp_hf_0_2_8_bitmask {
- BNXT_ULP_HF_0_2_8_BITMASK_WM = 0x8000000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID = 0x0200000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_VER = 0x0080000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_TC = 0x0040000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_TTL = 0x0004000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT = 0x0000400000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_RX_WIN = 0x0000020000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_CSUM = 0x0000010000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_URP = 0x0000008000000000
+enum bnxt_ulp_hf_0_3_3_bitmask {
+ BNXT_ULP_HF_0_3_3_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_VER = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_TOS = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_LEN = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_TTL = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000
};
-enum bnxt_ulp_hf_0_2_9_bitmask {
- BNXT_ULP_HF_0_2_9_BITMASK_WM = 0x8000000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID = 0x0200000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_VER = 0x0080000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_TOS = 0x0040000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_LEN = 0x0020000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_TTL = 0x0004000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT = 0x0000100000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_RX_WIN = 0x0000008000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_CSUM = 0x0000004000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_URP = 0x0000002000000000
+enum bnxt_ulp_hf_0_3_4_bitmask {
+ BNXT_ULP_HF_0_3_4_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_TC = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SENT_SEQ = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_RECV_ACK = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DATA_OFF = 0x0000400000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_TCP_FLAGS = 0x0000200000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_RX_WIN = 0x0000100000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_CSUM = 0x0000080000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_URP = 0x0000040000000000
};
-enum bnxt_ulp_hf_0_2_10_bitmask {
- BNXT_ULP_HF_0_2_10_BITMASK_WM = 0x8000000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID = 0x0200000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_VER = 0x0080000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_TC = 0x0040000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_TTL = 0x0004000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT = 0x0000400000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_LENGTH = 0x0000200000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_CSUM = 0x0000100000000000
+enum bnxt_ulp_hf_0_3_5_bitmask {
+ BNXT_ULP_HF_0_3_5_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_TOS = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_LEN = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_RX_WIN = 0x0000040000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_CSUM = 0x0000020000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_URP = 0x0000010000000000
};
-enum bnxt_ulp_hf_0_2_11_bitmask {
- BNXT_ULP_HF_0_2_11_BITMASK_WM = 0x8000000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID = 0x0200000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_VER = 0x0080000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_TOS = 0x0040000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_LEN = 0x0020000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_TTL = 0x0004000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT = 0x0000100000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_LENGTH = 0x0000080000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_CSUM = 0x0000040000000000
+enum bnxt_ulp_hf_0_3_6_bitmask {
+ BNXT_ULP_HF_0_3_6_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_TC = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_LENGTH = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_CSUM = 0x0000800000000000
+};
+
+enum bnxt_ulp_hf_0_3_7_bitmask {
+ BNXT_ULP_HF_0_3_7_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_TOS = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_LEN = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_LENGTH = 0x0000400000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_CSUM = 0x0000200000000000
+};
+
+enum bnxt_ulp_hf_0_3_8_bitmask {
+ BNXT_ULP_HF_0_3_8_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_VER = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_TC = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_TTL = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT = 0x0000400000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_RX_WIN = 0x0000020000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_CSUM = 0x0000010000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_URP = 0x0000008000000000
+};
+
+enum bnxt_ulp_hf_0_3_9_bitmask {
+ BNXT_ULP_HF_0_3_9_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_VER = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_TOS = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_LEN = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_TTL = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT = 0x0000100000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_RX_WIN = 0x0000008000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_CSUM = 0x0000004000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_URP = 0x0000002000000000
+};
+
+enum bnxt_ulp_hf_0_3_10_bitmask {
+ BNXT_ULP_HF_0_3_10_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_VER = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_TC = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_TTL = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT = 0x0000400000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_LENGTH = 0x0000200000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_CSUM = 0x0000100000000000
+};
+
+enum bnxt_ulp_hf_0_3_11_bitmask {
+ BNXT_ULP_HF_0_3_11_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_VER = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_TOS = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_LEN = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_TTL = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT = 0x0000100000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_LENGTH = 0x0000080000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_CSUM = 0x0000040000000000
};
#endif
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
index 2debaea0ca..58b4dba63c 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 13 18:15:56 2021 */
+/* date: Thu May 20 11:56:39 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -111,6 +111,26 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = {
.num_buckets = 0,
.hash_tbl_entries = 0,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE << 1 |
+ BNXT_ULP_DIRECTION_INGRESS] = {
+ .name = "INGRESS GENERIC_TABLE_TUNNEL_CACHE",
+ .result_num_entries = 256,
+ .result_num_bytes = 7,
+ .key_num_bytes = 2,
+ .num_buckets = 8,
+ .hash_tbl_entries = 1024,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE << 1 |
+ BNXT_ULP_DIRECTION_EGRESS] = {
+ .name = "EGRESS GENERIC_TABLE_TUNNEL_CACHE",
+ .result_num_entries = 256,
+ .result_num_bytes = 7,
+ .key_num_bytes = 2,
+ .num_buckets = 8,
+ .hash_tbl_entries = 1024,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
}
};
@@ -3098,238 +3118,411 @@ uint8_t ulp_glb_field_tbl[] = {
[4098] = 2,
[4100] = 3,
[4102] = 4,
- [4136] = 5,
- [4138] = 6,
- [4140] = 7,
- [4142] = 8,
- [4144] = 9,
- [4146] = 10,
- [4148] = 11,
- [4150] = 12,
+ [4116] = 5,
+ [4118] = 6,
+ [4120] = 7,
+ [4122] = 8,
+ [4124] = 9,
+ [4126] = 10,
+ [4128] = 11,
+ [4130] = 12,
+ [4132] = 13,
+ [4134] = 14,
+ [4170] = 15,
+ [4172] = 16,
+ [4174] = 17,
+ [4176] = 18,
+ [4190] = 19,
+ [4191] = 20,
+ [4192] = 21,
+ [4193] = 22,
[4224] = 0,
[4225] = 1,
- [4226] = 2,
- [4228] = 3,
- [4230] = 4,
- [4244] = 5,
- [4246] = 6,
- [4248] = 7,
- [4250] = 8,
- [4252] = 9,
- [4254] = 10,
- [4256] = 11,
- [4258] = 12,
- [4260] = 13,
- [4262] = 14,
+ [4227] = 20,
+ [4229] = 21,
+ [4231] = 22,
+ [4244] = 2,
+ [4245] = 23,
+ [4246] = 3,
+ [4247] = 24,
+ [4248] = 4,
+ [4249] = 25,
+ [4250] = 5,
+ [4251] = 26,
+ [4252] = 6,
+ [4253] = 27,
+ [4254] = 7,
+ [4255] = 28,
+ [4256] = 8,
+ [4257] = 29,
+ [4258] = 9,
+ [4259] = 30,
+ [4260] = 10,
+ [4261] = 31,
+ [4262] = 11,
+ [4263] = 32,
+ [4298] = 12,
+ [4300] = 13,
+ [4302] = 14,
+ [4304] = 15,
+ [4318] = 16,
+ [4319] = 17,
+ [4320] = 18,
+ [4321] = 19,
[4352] = 0,
[4353] = 1,
- [4354] = 2,
- [4356] = 3,
- [4358] = 4,
- [4392] = 8,
- [4394] = 9,
- [4396] = 10,
- [4398] = 11,
- [4400] = 12,
- [4402] = 13,
- [4404] = 14,
- [4406] = 15,
- [4434] = 5,
- [4438] = 6,
- [4442] = 7,
+ [4355] = 20,
+ [4357] = 21,
+ [4359] = 22,
+ [4372] = 2,
+ [4373] = 23,
+ [4374] = 3,
+ [4375] = 24,
+ [4376] = 4,
+ [4377] = 25,
+ [4378] = 5,
+ [4379] = 26,
+ [4380] = 6,
+ [4381] = 27,
+ [4382] = 7,
+ [4383] = 28,
+ [4384] = 8,
+ [4385] = 29,
+ [4386] = 9,
+ [4387] = 30,
+ [4388] = 10,
+ [4389] = 31,
+ [4390] = 11,
+ [4391] = 32,
+ [4409] = 33,
+ [4411] = 34,
+ [4413] = 35,
+ [4415] = 36,
+ [4417] = 37,
+ [4419] = 38,
+ [4421] = 39,
+ [4423] = 40,
+ [4425] = 41,
+ [4426] = 12,
+ [4428] = 13,
+ [4430] = 14,
+ [4432] = 15,
+ [4446] = 16,
+ [4447] = 17,
+ [4448] = 18,
+ [4449] = 19,
[4480] = 0,
[4481] = 1,
- [4482] = 2,
- [4484] = 3,
- [4486] = 4,
- [4500] = 8,
- [4502] = 9,
- [4504] = 10,
- [4506] = 11,
- [4508] = 12,
- [4510] = 13,
- [4512] = 14,
- [4514] = 15,
- [4516] = 16,
- [4518] = 17,
- [4562] = 5,
- [4566] = 6,
- [4570] = 7,
+ [4483] = 20,
+ [4485] = 21,
+ [4487] = 22,
+ [4500] = 2,
+ [4501] = 23,
+ [4502] = 3,
+ [4503] = 24,
+ [4504] = 4,
+ [4505] = 25,
+ [4506] = 5,
+ [4507] = 26,
+ [4508] = 6,
+ [4509] = 27,
+ [4510] = 7,
+ [4511] = 28,
+ [4512] = 8,
+ [4513] = 29,
+ [4514] = 9,
+ [4515] = 30,
+ [4516] = 10,
+ [4517] = 31,
+ [4518] = 11,
+ [4519] = 32,
+ [4554] = 12,
+ [4555] = 33,
+ [4556] = 13,
+ [4557] = 34,
+ [4558] = 14,
+ [4559] = 35,
+ [4560] = 15,
+ [4561] = 36,
+ [4574] = 16,
+ [4575] = 17,
+ [4576] = 18,
+ [4577] = 19,
[4608] = 0,
[4609] = 1,
- [4610] = 2,
- [4612] = 3,
- [4614] = 4,
- [4648] = 5,
- [4650] = 6,
- [4652] = 7,
- [4654] = 8,
- [4656] = 9,
- [4658] = 10,
- [4660] = 11,
- [4662] = 12,
- [4664] = 13,
- [4666] = 14,
- [4668] = 15,
- [4670] = 16,
- [4672] = 17,
- [4674] = 18,
- [4676] = 19,
- [4678] = 20,
- [4680] = 21,
- [4736] = 0,
- [4737] = 1,
- [4738] = 2,
- [4740] = 3,
- [4742] = 4,
- [4756] = 5,
- [4758] = 6,
- [4760] = 7,
- [4762] = 8,
- [4764] = 9,
- [4766] = 10,
- [4768] = 11,
- [4770] = 12,
- [4772] = 13,
- [4774] = 14,
- [4792] = 15,
- [4794] = 16,
- [4796] = 17,
- [4798] = 18,
- [4800] = 19,
- [4802] = 20,
- [4804] = 21,
- [4806] = 22,
- [4808] = 23,
- [4864] = 0,
- [4865] = 1,
- [4866] = 2,
- [4868] = 3,
- [4870] = 4,
- [4904] = 5,
- [4906] = 6,
- [4908] = 7,
- [4910] = 8,
- [4912] = 9,
- [4914] = 10,
- [4916] = 11,
- [4918] = 12,
- [4938] = 13,
- [4940] = 14,
- [4942] = 15,
- [4944] = 16,
- [4992] = 0,
- [4993] = 1,
- [4994] = 2,
- [4996] = 3,
- [4998] = 4,
- [5012] = 5,
- [5014] = 6,
- [5016] = 7,
- [5018] = 8,
- [5020] = 9,
- [5022] = 10,
- [5024] = 11,
- [5026] = 12,
- [5028] = 13,
- [5030] = 14,
- [5066] = 15,
- [5068] = 16,
- [5070] = 17,
- [5072] = 18,
- [5120] = 0,
- [5121] = 1,
- [5122] = 2,
- [5124] = 3,
- [5126] = 4,
- [5160] = 8,
- [5162] = 9,
- [5164] = 10,
- [5166] = 11,
- [5168] = 12,
- [5170] = 13,
- [5172] = 14,
- [5174] = 15,
- [5176] = 16,
- [5178] = 17,
- [5180] = 18,
- [5182] = 19,
- [5184] = 20,
- [5186] = 21,
- [5188] = 22,
- [5190] = 23,
- [5192] = 24,
- [5202] = 5,
- [5206] = 6,
- [5210] = 7,
- [5248] = 0,
- [5249] = 1,
- [5250] = 2,
- [5252] = 3,
- [5254] = 4,
- [5268] = 8,
- [5270] = 9,
- [5272] = 10,
- [5274] = 11,
- [5276] = 12,
- [5278] = 13,
- [5280] = 14,
- [5282] = 15,
- [5284] = 16,
- [5286] = 17,
- [5304] = 18,
- [5306] = 19,
- [5308] = 20,
- [5310] = 21,
- [5312] = 22,
- [5314] = 23,
- [5316] = 24,
- [5318] = 25,
- [5320] = 26,
- [5330] = 5,
- [5334] = 6,
- [5338] = 7,
- [5376] = 0,
- [5377] = 1,
- [5378] = 2,
- [5380] = 3,
- [5382] = 4,
- [5416] = 8,
- [5418] = 9,
- [5420] = 10,
- [5422] = 11,
- [5424] = 12,
- [5426] = 13,
- [5428] = 14,
- [5430] = 15,
- [5450] = 16,
- [5452] = 17,
- [5454] = 18,
- [5456] = 19,
- [5458] = 5,
- [5462] = 6,
- [5466] = 7,
- [5504] = 0,
- [5505] = 1,
- [5506] = 2,
- [5508] = 3,
- [5510] = 4,
- [5524] = 8,
- [5526] = 9,
- [5528] = 10,
- [5530] = 11,
- [5532] = 12,
- [5534] = 13,
- [5536] = 14,
- [5538] = 15,
- [5540] = 16,
- [5542] = 17,
- [5578] = 18,
- [5580] = 19,
- [5582] = 20,
- [5584] = 21,
- [5586] = 5,
- [5590] = 6,
- [5594] = 7
+ [4611] = 20,
+ [4613] = 21,
+ [4615] = 22,
+ [4619] = 33,
+ [4621] = 34,
+ [4623] = 35,
+ [4625] = 36,
+ [4627] = 37,
+ [4628] = 2,
+ [4629] = 23,
+ [4630] = 3,
+ [4631] = 24,
+ [4632] = 4,
+ [4633] = 25,
+ [4634] = 5,
+ [4635] = 26,
+ [4636] = 6,
+ [4637] = 27,
+ [4638] = 7,
+ [4639] = 28,
+ [4640] = 8,
+ [4641] = 29,
+ [4642] = 9,
+ [4643] = 30,
+ [4644] = 10,
+ [4645] = 31,
+ [4646] = 11,
+ [4647] = 32,
+ [4682] = 12,
+ [4684] = 13,
+ [4686] = 14,
+ [4688] = 15,
+ [4702] = 16,
+ [4703] = 17,
+ [4704] = 18,
+ [4705] = 19,
+ [6144] = 0,
+ [6145] = 1,
+ [6146] = 2,
+ [6148] = 3,
+ [6150] = 4,
+ [6184] = 5,
+ [6186] = 6,
+ [6188] = 7,
+ [6190] = 8,
+ [6192] = 9,
+ [6194] = 10,
+ [6196] = 11,
+ [6198] = 12,
+ [6272] = 0,
+ [6273] = 1,
+ [6274] = 2,
+ [6276] = 3,
+ [6278] = 4,
+ [6292] = 5,
+ [6294] = 6,
+ [6296] = 7,
+ [6298] = 8,
+ [6300] = 9,
+ [6302] = 10,
+ [6304] = 11,
+ [6306] = 12,
+ [6308] = 13,
+ [6310] = 14,
+ [6400] = 0,
+ [6401] = 1,
+ [6402] = 2,
+ [6404] = 3,
+ [6406] = 4,
+ [6440] = 8,
+ [6442] = 9,
+ [6444] = 10,
+ [6446] = 11,
+ [6448] = 12,
+ [6450] = 13,
+ [6452] = 14,
+ [6454] = 15,
+ [6482] = 5,
+ [6486] = 6,
+ [6490] = 7,
+ [6528] = 0,
+ [6529] = 1,
+ [6530] = 2,
+ [6532] = 3,
+ [6534] = 4,
+ [6548] = 8,
+ [6550] = 9,
+ [6552] = 10,
+ [6554] = 11,
+ [6556] = 12,
+ [6558] = 13,
+ [6560] = 14,
+ [6562] = 15,
+ [6564] = 16,
+ [6566] = 17,
+ [6610] = 5,
+ [6614] = 6,
+ [6618] = 7,
+ [6656] = 0,
+ [6657] = 1,
+ [6658] = 2,
+ [6660] = 3,
+ [6662] = 4,
+ [6696] = 5,
+ [6698] = 6,
+ [6700] = 7,
+ [6702] = 8,
+ [6704] = 9,
+ [6706] = 10,
+ [6708] = 11,
+ [6710] = 12,
+ [6712] = 13,
+ [6714] = 14,
+ [6716] = 15,
+ [6718] = 16,
+ [6720] = 17,
+ [6722] = 18,
+ [6724] = 19,
+ [6726] = 20,
+ [6728] = 21,
+ [6784] = 0,
+ [6785] = 1,
+ [6786] = 2,
+ [6788] = 3,
+ [6790] = 4,
+ [6804] = 5,
+ [6806] = 6,
+ [6808] = 7,
+ [6810] = 8,
+ [6812] = 9,
+ [6814] = 10,
+ [6816] = 11,
+ [6818] = 12,
+ [6820] = 13,
+ [6822] = 14,
+ [6840] = 15,
+ [6842] = 16,
+ [6844] = 17,
+ [6846] = 18,
+ [6848] = 19,
+ [6850] = 20,
+ [6852] = 21,
+ [6854] = 22,
+ [6856] = 23,
+ [6912] = 0,
+ [6913] = 1,
+ [6914] = 2,
+ [6916] = 3,
+ [6918] = 4,
+ [6952] = 5,
+ [6954] = 6,
+ [6956] = 7,
+ [6958] = 8,
+ [6960] = 9,
+ [6962] = 10,
+ [6964] = 11,
+ [6966] = 12,
+ [6986] = 13,
+ [6988] = 14,
+ [6990] = 15,
+ [6992] = 16,
+ [7040] = 0,
+ [7041] = 1,
+ [7042] = 2,
+ [7044] = 3,
+ [7046] = 4,
+ [7060] = 5,
+ [7062] = 6,
+ [7064] = 7,
+ [7066] = 8,
+ [7068] = 9,
+ [7070] = 10,
+ [7072] = 11,
+ [7074] = 12,
+ [7076] = 13,
+ [7078] = 14,
+ [7114] = 15,
+ [7116] = 16,
+ [7118] = 17,
+ [7120] = 18,
+ [7168] = 0,
+ [7169] = 1,
+ [7170] = 2,
+ [7172] = 3,
+ [7174] = 4,
+ [7208] = 8,
+ [7210] = 9,
+ [7212] = 10,
+ [7214] = 11,
+ [7216] = 12,
+ [7218] = 13,
+ [7220] = 14,
+ [7222] = 15,
+ [7224] = 16,
+ [7226] = 17,
+ [7228] = 18,
+ [7230] = 19,
+ [7232] = 20,
+ [7234] = 21,
+ [7236] = 22,
+ [7238] = 23,
+ [7240] = 24,
+ [7250] = 5,
+ [7254] = 6,
+ [7258] = 7,
+ [7296] = 0,
+ [7297] = 1,
+ [7298] = 2,
+ [7300] = 3,
+ [7302] = 4,
+ [7316] = 8,
+ [7318] = 9,
+ [7320] = 10,
+ [7322] = 11,
+ [7324] = 12,
+ [7326] = 13,
+ [7328] = 14,
+ [7330] = 15,
+ [7332] = 16,
+ [7334] = 17,
+ [7352] = 18,
+ [7354] = 19,
+ [7356] = 20,
+ [7358] = 21,
+ [7360] = 22,
+ [7362] = 23,
+ [7364] = 24,
+ [7366] = 25,
+ [7368] = 26,
+ [7378] = 5,
+ [7382] = 6,
+ [7386] = 7,
+ [7424] = 0,
+ [7425] = 1,
+ [7426] = 2,
+ [7428] = 3,
+ [7430] = 4,
+ [7464] = 8,
+ [7466] = 9,
+ [7468] = 10,
+ [7470] = 11,
+ [7472] = 12,
+ [7474] = 13,
+ [7476] = 14,
+ [7478] = 15,
+ [7498] = 16,
+ [7500] = 17,
+ [7502] = 18,
+ [7504] = 19,
+ [7506] = 5,
+ [7510] = 6,
+ [7514] = 7,
+ [7552] = 0,
+ [7553] = 1,
+ [7554] = 2,
+ [7556] = 3,
+ [7558] = 4,
+ [7572] = 8,
+ [7574] = 9,
+ [7576] = 10,
+ [7578] = 11,
+ [7580] = 12,
+ [7582] = 13,
+ [7584] = 14,
+ [7586] = 15,
+ [7588] = 16,
+ [7590] = 17,
+ [7626] = 18,
+ [7628] = 19,
+ [7630] = 20,
+ [7632] = 21,
+ [7634] = 5,
+ [7638] = 6,
+ [7642] = 7
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
index e342f340d9..d20c4197fa 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 13 18:15:56 2021 */
+/* date: Thu May 20 11:56:39 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -22,8 +22,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {
.cond_start_idx = 0,
.cond_nums = 4 }
},
- /* class_tid: 3, ingress */
- [3] = {
+ /* class_tid: 4, ingress */
+ [4] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
.num_tbls = 15,
.start_tbl_idx = 12,
@@ -32,8 +32,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {
.cond_start_idx = 8,
.cond_nums = 1 }
},
- /* class_tid: 4, egress */
- [4] = {
+ /* class_tid: 5, egress */
+ [5] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
.num_tbls = 6,
.start_tbl_idx = 27,
@@ -306,7 +306,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 38,
.result_num_fields = 5
},
- { /* class_tid: 3, , table: int_full_act_record.0 */
+ { /* class_tid: 4, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@@ -327,7 +327,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 128,
.result_num_fields = 17
},
- { /* class_tid: 3, , table: port_table.wr_0 */
+ { /* class_tid: 4, , table: port_table.wr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
@@ -350,7 +350,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 152,
.result_num_fields = 5
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
@@ -372,7 +372,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.ident_start_idx = 6,
.ident_nums = 0
},
- { /* class_tid: 3, , table: control.ing_0 */
+ { /* class_tid: 4, , table: control.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
@@ -385,7 +385,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
+ { /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.direction = TF_DIR_RX,
@@ -414,7 +414,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.ident_start_idx = 6,
.ident_nums = 1
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
@@ -437,7 +437,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */
+ { /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
.direction = TF_DIR_RX,
@@ -455,7 +455,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */
+ { /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
.direction = TF_DIR_RX,
@@ -473,7 +473,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 3, , table: control.egr_0 */
+ { /* class_tid: 4, , table: control.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
@@ -485,7 +485,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 3, , table: int_full_act_record.egr_0 */
+ { /* class_tid: 4, , table: int_full_act_record.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@@ -507,7 +507,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_num_fields = 17,
.encap_num_fields = 0
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
@@ -529,7 +529,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.ident_start_idx = 7,
.ident_nums = 0
},
- { /* class_tid: 3, , table: control.egr_1 */
+ { /* class_tid: 4, , table: control.egr_1 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
@@ -542,7 +542,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
+ { /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.direction = TF_DIR_TX,
@@ -569,7 +569,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.ident_start_idx = 7,
.ident_nums = 1
},
- { /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */
+ { /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
.direction = TF_DIR_TX,
@@ -587,7 +587,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */
+ { /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
.direction = TF_DIR_TX,
@@ -605,7 +605,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 4, , table: int_full_act_record.loopback */
+ { /* class_tid: 5, , table: int_full_act_record.loopback */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@@ -627,7 +627,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_num_fields = 17,
.encap_num_fields = 0
},
- { /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */
+ { /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
.direction = TF_DIR_TX,
@@ -645,7 +645,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */
+ { /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
.direction = TF_DIR_TX,
@@ -663,7 +663,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 4, , table: int_full_act_record.vf_ing */
+ { /* class_tid: 5, , table: int_full_act_record.vf_ing */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@@ -685,7 +685,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_num_fields = 17,
.encap_num_fields = 0
},
- { /* class_tid: 4, , table: vtag_encap_record.vfr_egr0 */
+ { /* class_tid: 5, , table: vtag_encap_record.vfr_egr0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
.resource_sub_type =
@@ -707,7 +707,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_num_fields = 0,
.encap_num_fields = 11
},
- { /* class_tid: 4, , table: int_full_act_record.vfr_egr0 */
+ { /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@@ -768,27 +768,27 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
.cond_operand = BNXT_ULP_CF_IDX_O_L4
},
- /* cond_reject: thor, class_tid: 3 */
+ /* cond_reject: thor, class_tid: 4 */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
},
- /* cond_execute: class_tid: 3, control.ing_0 */
+ /* cond_execute: class_tid: 4, control.ing_0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 3, control.egr_0 */
+ /* cond_execute: class_tid: 4, control.egr_0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
},
- /* cond_execute: class_tid: 3, control.egr_1 */
+ /* cond_execute: class_tid: 4, control.egr_1 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_reject: thor, class_tid: 4 */
+ /* cond_reject: thor, class_tid: 5 */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
@@ -3612,7 +3612,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
- /* class_tid: 3, , table: port_table.wr_0 */
+ /* class_tid: 4, , table: port_table.wr_0 */
{
.field_info_mask = {
.description = "dev.port_id",
@@ -3633,7 +3633,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
{
.field_info_mask = {
.description = "svif",
@@ -3653,7 +3653,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
.field_info_mask = {
.description = "etype",
@@ -3958,7 +3958,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
1}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
{
.field_info_mask = {
.description = "svif",
@@ -3978,7 +3978,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */
{
.field_info_mask = {
.description = "svif",
@@ -3998,7 +3998,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
.field_info_mask = {
.description = "etype",
@@ -5187,7 +5187,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 3, , table: int_full_act_record.0 */
+ /* class_tid: 4, , table: int_full_act_record.0 */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -5295,7 +5295,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 3, , table: port_table.wr_0 */
+ /* class_tid: 4, , table: port_table.wr_0 */
{
.description = "rid",
.field_bit_size = 32,
@@ -5329,7 +5329,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
- /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
.description = "prof_func_id",
.field_bit_size = 7,
@@ -5380,7 +5380,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -5414,7 +5414,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */
+ /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -5424,7 +5424,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
- /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */
+ /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -5434,7 +5434,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
- /* class_tid: 3, , table: int_full_act_record.egr_0 */
+ /* class_tid: 4, , table: int_full_act_record.egr_0 */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -5542,7 +5542,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
.description = "prof_func_id",
.field_bit_size = 7,
@@ -5593,7 +5593,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
},
- /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */
+ /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -5603,7 +5603,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */
+ /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -5613,7 +5613,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 4, , table: int_full_act_record.loopback */
+ /* class_tid: 5, , table: int_full_act_record.loopback */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -5721,7 +5721,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */
+ /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -5731,7 +5731,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
- /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */
+ /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -5741,7 +5741,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
- /* class_tid: 4, , table: int_full_act_record.vf_ing */
+ /* class_tid: 5, , table: int_full_act_record.vf_ing */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -5849,7 +5849,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 4, , table: vtag_encap_record.vfr_egr0 */
+ /* class_tid: 5, , table: vtag_encap_record.vfr_egr0 */
{
.description = "ecv_tun_type",
.field_bit_size = 3,
@@ -5929,7 +5929,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
},
- /* class_tid: 4, , table: int_full_act_record.vfr_egr0 */
+ /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -6085,7 +6085,7 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 29
},
- /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
.description = "l2_cntxt_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -6094,7 +6094,7 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 29
},
- /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
.description = "l2_cntxt_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
index b6d2afd55b..de924fe81a 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 13 18:15:56 2021 */
+/* date: Mon May 17 15:54:03 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
index 85b8950e49..7b6ee03a4b 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Fri May 14 10:26:31 2021 */
+/* date: Mon May 17 15:54:03 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -22,7 +22,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = {
.cond_start_idx = 0,
.cond_nums = 1 }
},
- /* class_tid: 2, egress */
+ /* class_tid: 2, ingress */
[2] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
.num_tbls = 15,
@@ -32,24 +32,34 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = {
.cond_start_idx = 24,
.cond_nums = 1 }
},
- /* class_tid: 3, ingress */
+ /* class_tid: 3, egress */
[3] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .num_tbls = 22,
+ .num_tbls = 15,
.start_tbl_idx = 33,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 30,
+ .cond_nums = 1 }
+ },
+ /* class_tid: 4, ingress */
+ [4] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 22,
+ .start_tbl_idx = 48,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 35,
+ .cond_start_idx = 41,
.cond_nums = 0 }
},
- /* class_tid: 4, egress */
- [4] = {
+ /* class_tid: 5, egress */
+ [5] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
.num_tbls = 19,
- .start_tbl_idx = 55,
+ .start_tbl_idx = 70,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 41,
+ .cond_start_idx = 47,
.cond_nums = 0 }
}
};
@@ -455,58 +465,133 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.result_bit_size = 64,
.result_num_fields = 9
},
- { /* class_tid: 2, , table: l2_cntxt_tcam_cache.rd */
+ { /* class_tid: 2, , table: tunnel_cache.rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 5,
+ .cond_true_goto = 1,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 25,
- .cond_nums = 1 },
+ .cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 223,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
+ .blob_key_bit_size = 16,
+ .key_bit_size = 16,
+ .key_num_fields = 2,
.ident_start_idx = 9,
.ident_nums = 1
},
+ { /* class_tid: 2, , table: control.tunnel_cache_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 25,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ { /* class_tid: 2, , table: l2_cntxt_tcam.1 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 26,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 225,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 127,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .ident_start_idx = 10,
+ .ident_nums = 1
+ },
+ { /* class_tid: 2, , table: tunnel_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 26,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 238,
+ .blob_key_bit_size = 16,
+ .key_bit_size = 16,
+ .key_num_fields = 2,
+ .result_start_idx = 140,
+ .result_bit_size = 52,
+ .result_num_fields = 3
+ },
+ { /* class_tid: 2, , table: control.flow_type_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 5,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 26,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
{ /* class_tid: 2, , table: mac_addr_cache.rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 26,
+ .cond_start_idx = 27,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 224,
+ .key_start_idx = 240,
.blob_key_bit_size = 73,
.key_bit_size = 73,
.key_num_fields = 5,
- .ident_start_idx = 10,
+ .ident_start_idx = 11,
.ident_nums = 1
},
- { /* class_tid: 2, , table: control.0 */
+ { /* class_tid: 2, , table: control.mac_addr_cache_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 3,
+ .cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 26,
+ .cond_start_idx = 27,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
@@ -515,12 +600,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
{ /* class_tid: 2, , table: l2_cntxt_tcam.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 27,
+ .cond_start_idx = 28,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
@@ -529,323 +614,236 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 229,
+ .key_start_idx = 245,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 127,
+ .result_start_idx = 143,
.result_bit_size = 64,
.result_num_fields = 13,
- .ident_start_idx = 11,
- .ident_nums = 1
+ .ident_start_idx = 12,
+ .ident_nums = 0
},
{ /* class_tid: 2, , table: mac_addr_cache.wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 27,
+ .cond_start_idx = 28,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 242,
+ .key_start_idx = 258,
.blob_key_bit_size = 73,
.key_bit_size = 73,
.key_num_fields = 5,
- .result_start_idx = 140,
+ .result_start_idx = 156,
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 2, , table: profile_tcam_cache.rd */
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 27,
+ .cond_start_idx = 28,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 247,
+ .key_start_idx = 263,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
.ident_start_idx = 12,
.ident_nums = 3
},
- { /* class_tid: 2, , table: control.gen_tbl_miss */
+ { /* class_tid: 2, , table: control.profile_tcam_cache.f2_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 2,
- .cond_false_goto = 1,
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 27,
+ .cond_start_idx = 28,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 2, , table: control.conflict_check */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 4,
- .cond_false_goto = 1023,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 28,
- .cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .func_info = {
- .func_opc = BNXT_ULP_FUNC_OPC_EQ,
- .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
- .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
- .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
- .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
- .func_dst_opr = BNXT_ULP_RF_IDX_CC },
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
- },
- { /* class_tid: 2, , table: profile_tcam.ipv4 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 2,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 29,
- .cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 250,
- .blob_key_bit_size = 81,
- .key_bit_size = 81,
- .key_num_fields = 43,
- .result_start_idx = 144,
- .result_bit_size = 38,
- .result_num_fields = 17,
- .ident_start_idx = 15,
- .ident_nums = 1
- },
- { /* class_tid: 2, , table: profile_tcam.ipv6 */
+ { /* class_tid: 2, , table: profile_tcam.f2 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 30,
+ .cond_start_idx = 29,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 1,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 293,
+ .key_start_idx = 266,
.blob_key_bit_size = 81,
.key_bit_size = 81,
.key_num_fields = 43,
- .result_start_idx = 161,
+ .result_start_idx = 160,
.result_bit_size = 38,
- .result_num_fields = 17,
- .ident_start_idx = 16,
- .ident_nums = 1
+ .result_num_fields = 17
},
- { /* class_tid: 2, , table: profile_tcam_cache.wr */
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 30,
+ .cond_start_idx = 29,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 336,
+ .key_start_idx = 309,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
- .result_start_idx = 178,
+ .result_start_idx = 177,
.result_bit_size = 122,
.result_num_fields = 5
},
- { /* class_tid: 2, , table: em.ipv4 */
+ { /* class_tid: 2, , table: em.tun */
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_MEM_INTERNAL,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 0,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 30,
- .cond_nums = 2 },
+ .cond_start_idx = 29,
+ .cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 339,
- .blob_key_bit_size = 176,
- .key_bit_size = 176,
- .key_num_fields = 10,
- .result_start_idx = 183,
+ .key_start_idx = 312,
+ .blob_key_bit_size = 112,
+ .key_bit_size = 112,
+ .key_num_fields = 8,
+ .result_start_idx = 182,
.result_bit_size = 64,
.result_num_fields = 9
},
- { /* class_tid: 2, , table: eem.ipv4 */
+ { /* class_tid: 2, , table: eem.tun */
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_MEM_EXTERNAL,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 0,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 32,
- .cond_nums = 2 },
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 30,
+ .cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 349,
+ .key_start_idx = 320,
.blob_key_bit_size = 448,
.key_bit_size = 448,
- .key_num_fields = 10,
- .result_start_idx = 192,
+ .key_num_fields = 8,
+ .result_start_idx = 191,
.result_bit_size = 64,
.result_num_fields = 9
},
- { /* class_tid: 2, , table: em.ipv6 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
- .resource_type = TF_MEM_INTERNAL,
+ { /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 0,
+ .cond_true_goto = 5,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 34,
+ .cond_start_idx = 31,
.cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 359,
- .blob_key_bit_size = 416,
- .key_bit_size = 416,
- .key_num_fields = 11,
- .result_start_idx = 201,
- .result_bit_size = 64,
- .result_num_fields = 9
+ .key_start_idx = 328,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 15,
+ .ident_nums = 1
},
- { /* class_tid: 2, , table: eem.ipv6 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
- .resource_type = TF_MEM_EXTERNAL,
+ { /* class_tid: 3, , table: mac_addr_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 0,
- .cond_false_goto = 0,
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 35,
+ .cond_start_idx = 32,
.cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 370,
- .blob_key_bit_size = 448,
- .key_bit_size = 448,
- .key_num_fields = 11,
- .result_start_idx = 210,
- .result_bit_size = 64,
- .result_num_fields = 9
+ .key_start_idx = 329,
+ .blob_key_bit_size = 73,
+ .key_bit_size = 73,
+ .key_num_fields = 5,
+ .ident_start_idx = 16,
+ .ident_nums = 1
},
- { /* class_tid: 3, , table: int_full_act_record.ing_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 35,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 219,
- .result_bit_size = 128,
- .result_num_fields = 26
- },
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 35,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 381,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .ident_start_idx = 17,
- .ident_nums = 0
- },
- { /* class_tid: 3, , table: control.ing_0 */
+ { /* class_tid: 3, , table: control.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_RX,
+ .direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 3,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 35,
+ .cond_start_idx = 32,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
+ { /* class_tid: 3, , table: l2_cntxt_tcam.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .direction = TF_DIR_RX,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 36,
+ .cond_start_idx = 33,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
@@ -853,361 +851,240 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 382,
+ .key_start_idx = 334,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 245,
+ .result_start_idx = 200,
.result_bit_size = 64,
.result_num_fields = 13,
.ident_start_idx = 17,
.ident_nums = 1
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */
+ { /* class_tid: 3, , table: mac_addr_cache.wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
- .direction = TF_DIR_RX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
+ .direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 36,
+ .cond_start_idx = 33,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 395,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .result_start_idx = 258,
+ .key_start_idx = 347,
+ .blob_key_bit_size = 73,
+ .key_bit_size = 73,
+ .key_num_fields = 5,
+ .result_start_idx = 213,
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 3, , table: parif_def_lkup_arec_ptr.ing_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 36,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 262,
- .result_bit_size = 32,
- .result_num_fields = 1
- },
- { /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
- .direction = TF_DIR_RX,
+ { /* class_tid: 3, , table: profile_tcam_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 36,
+ .cond_start_idx = 33,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 263,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .key_start_idx = 352,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .ident_start_idx = 18,
+ .ident_nums = 3
},
- { /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
- .direction = TF_DIR_RX,
+ { /* class_tid: 3, , table: control.gen_tbl_miss */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 2,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 36,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 264,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 33,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 3, , table: control.egr_0 */
+ { /* class_tid: 3, , table: control.conflict_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_RX,
+ .direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 6,
+ .cond_true_goto = 4,
+ .cond_false_goto = 1023,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 36,
+ .cond_start_idx = 34,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .func_info = {
+ .func_opc = BNXT_ULP_FUNC_OPC_EQ,
+ .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
+ .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
+ .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC },
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 3, , table: int_full_act_record.egr_vfr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 37,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 265,
- .result_bit_size = 128,
- .result_num_fields = 26,
- .encap_num_fields = 0
- },
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd_vfr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ { /* class_tid: 3, , table: profile_tcam.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 2,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 37,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 396,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .ident_start_idx = 18,
- .ident_nums = 0
- },
- { /* class_tid: 3, , table: control.egr_1 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 37,
+ .cond_start_idx = 35,
.cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 355,
+ .blob_key_bit_size = 81,
+ .key_bit_size = 81,
+ .key_num_fields = 43,
+ .result_start_idx = 217,
+ .result_bit_size = 38,
+ .result_num_fields = 17,
+ .ident_start_idx = 21,
+ .ident_nums = 1
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_bypass.egr_vfr */
+ { /* class_tid: 3, , table: profile_tcam.ipv6 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 38,
+ .cond_start_idx = 36,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
- .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 397,
- .blob_key_bit_size = 167,
- .key_bit_size = 167,
- .key_num_fields = 13,
- .result_start_idx = 291,
- .result_bit_size = 64,
- .result_num_fields = 13,
- .ident_start_idx = 18,
- .ident_nums = 0
+ .key_start_idx = 398,
+ .blob_key_bit_size = 81,
+ .key_bit_size = 81,
+ .key_num_fields = 43,
+ .result_start_idx = 234,
+ .result_bit_size = 38,
+ .result_num_fields = 17,
+ .ident_start_idx = 22,
+ .ident_nums = 1
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
+ { /* class_tid: 3, , table: profile_tcam_cache.wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 0,
+ .cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 38,
+ .cond_start_idx = 36,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 410,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .result_start_idx = 304,
- .result_bit_size = 62,
- .result_num_fields = 4
+ .key_start_idx = 441,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .result_start_idx = 251,
+ .result_bit_size = 122,
+ .result_num_fields = 5
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ { /* class_tid: 3, , table: em.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_INTERNAL,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 38,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 36,
+ .cond_nums = 2 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 411,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .ident_start_idx = 18,
- .ident_nums = 0
- },
- { /* class_tid: 3, , table: control.egr_2 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 3,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 38,
- .cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
- },
- { /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 39,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 412,
- .blob_key_bit_size = 167,
- .key_bit_size = 167,
- .key_num_fields = 13,
- .result_start_idx = 308,
+ .key_start_idx = 444,
+ .blob_key_bit_size = 176,
+ .key_bit_size = 176,
+ .key_num_fields = 10,
+ .result_start_idx = 256,
.result_bit_size = 64,
- .result_num_fields = 13,
- .ident_start_idx = 18,
- .ident_nums = 1
+ .result_num_fields = 9
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ { /* class_tid: 3, , table: eem.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_EXTERNAL,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 39,
+ .cond_start_idx = 38,
.cond_nums = 2 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 425,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .result_start_idx = 321,
- .result_bit_size = 62,
- .result_num_fields = 4
- },
- { /* class_tid: 3, , table: int_full_act_record.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 41,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 325,
- .result_bit_size = 128,
- .result_num_fields = 26,
- .encap_num_fields = 0
- },
- { /* class_tid: 3, , table: parif_def_lkup_arec_ptr.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 41,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 351,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .key_start_idx = 454,
+ .blob_key_bit_size = 448,
+ .key_bit_size = 448,
+ .key_num_fields = 10,
+ .result_start_idx = 265,
+ .result_bit_size = 64,
+ .result_num_fields = 9
},
- { /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+ { /* class_tid: 3, , table: em.ipv6 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_INTERNAL,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 41,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 40,
+ .cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 352,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .key_start_idx = 464,
+ .blob_key_bit_size = 416,
+ .key_bit_size = 416,
+ .key_num_fields = 11,
+ .result_start_idx = 274,
+ .result_bit_size = 64,
+ .result_num_fields = 9
},
- { /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
+ { /* class_tid: 3, , table: eem.ipv6 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_EXTERNAL,
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 0,
@@ -1215,41 +1092,44 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 41,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 353,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .key_start_idx = 475,
+ .blob_key_bit_size = 448,
+ .key_bit_size = 448,
+ .key_num_fields = 11,
+ .result_start_idx = 283,
+ .result_bit_size = 64,
+ .result_num_fields = 9
},
- { /* class_tid: 4, , table: int_full_act_record.loopback */
+ { /* class_tid: 4, , table: int_full_act_record.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 41,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE,
- .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 354,
+ .result_start_idx = 292,
.result_bit_size = 128,
- .result_num_fields = 26,
- .encap_num_fields = 0
+ .result_num_fields = 26
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_rd_egr */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
@@ -1260,16 +1140,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 426,
+ .key_start_idx = 486,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .ident_start_idx = 19,
+ .ident_start_idx = 23,
.ident_nums = 0
},
- { /* class_tid: 4, , table: control.vf_0 */
+ { /* class_tid: 4, , table: control.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 3,
@@ -1280,10 +1160,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */
+ { /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
@@ -1296,22 +1176,24 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 427,
+ .key_start_idx = 487,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 380,
+ .result_start_idx = 318,
.result_bit_size = 64,
.result_num_fields = 13,
- .ident_start_idx = 19,
+ .ident_start_idx = 23,
.ident_nums = 1
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
@@ -1322,119 +1204,103 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 440,
+ .key_start_idx = 500,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .result_start_idx = 393,
+ .result_start_idx = 331,
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 4, , table: parif_def_lkup_arec_ptr.vf_egr */
+ { /* class_tid: 4, , table: parif_def_lkup_arec_ptr.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 42,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
- .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 397,
+ .result_start_idx = 335,
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */
+ { /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 42,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
- .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 398,
+ .result_start_idx = 336,
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */
+ { /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 42,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
- .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 399,
+ .result_start_idx = 337,
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 4, , table: int_full_act_record.vf_ing */
+ { /* class_tid: 4, , table: control.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 6,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 42,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ { /* class_tid: 4, , table: int_full_act_record.egr_vfr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_RX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 400,
+ .result_start_idx = 338,
.result_bit_size = 128,
.result_num_fields = 26,
.encap_num_fields = 0
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vf_ing */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
- .pri_operand = 0,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 441,
- .blob_key_bit_size = 167,
- .key_bit_size = 167,
- .key_num_fields = 13,
- .result_start_idx = 426,
- .result_bit_size = 64,
- .result_num_fields = 13,
- .ident_start_idx = 20,
- .ident_nums = 0
- },
- { /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_rd_egr0 */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd_vfr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
@@ -1443,33 +1309,33 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 454,
+ .key_start_idx = 501,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .ident_start_idx = 20,
+ .ident_start_idx = 24,
.ident_nums = 0
},
- { /* class_tid: 4, , table: control.vfr_0 */
+ { /* class_tid: 4, , table: control.egr_1 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 3,
+ .cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_egr0 */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.egr_vfr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.direction = TF_DIR_TX,
@@ -1477,7 +1343,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 43,
+ .cond_start_idx = 44,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
@@ -1486,140 +1352,392 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 455,
+ .key_start_idx = 502,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 439,
+ .result_start_idx = 364,
.result_bit_size = 64,
.result_num_fields = 13,
- .ident_start_idx = 20,
+ .ident_start_idx = 24,
.ident_nums = 0
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 43,
+ .cond_start_idx = 44,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 468,
+ .key_start_idx = 515,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .result_start_idx = 452,
+ .result_start_idx = 377,
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 4, , table: int_vtag_encap_record.vfr_egr0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 43,
+ .cond_start_idx = 44,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 456,
- .result_bit_size = 0,
- .result_num_fields = 0,
- .encap_num_fields = 12
+ .key_start_idx = 516,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 24,
+ .ident_nums = 0
},
- { /* class_tid: 4, , table: int_full_act_record.vfr_egr0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
- .execute_info = {
+ { /* class_tid: 4, , table: control.egr_2 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 44,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .direction = TF_DIR_TX,
+ .execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 43,
+ .cond_start_idx = 45,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 517,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 381,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .ident_start_idx = 24,
+ .ident_nums = 1
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 45,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 530,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 394,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 4, , table: int_full_act_record.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 47,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 468,
+ .result_start_idx = 398,
.result_bit_size = 128,
- .result_num_fields = 26
+ .result_num_fields = 26,
+ .encap_num_fields = 0
+ },
+ { /* class_tid: 4, , table: parif_def_lkup_arec_ptr.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 47,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 424,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 47,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 425,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 47,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 426,
+ .result_bit_size = 32,
+ .result_num_fields = 1
},
- { /* class_tid: 4, , table: int_full_act_record.vfr_ing0 */
+ { /* class_tid: 5, , table: int_full_act_record.loopback */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_RX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 43,
+ .cond_start_idx = 47,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 494,
+ .result_start_idx = 427,
.result_bit_size = 128,
- .result_num_fields = 26
+ .result_num_fields = 26,
+ .encap_num_fields = 0
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 47,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 531,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 25,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: control.vf_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 47,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */
+ { /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .direction = TF_DIR_RX,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 43,
+ .cond_start_idx = 48,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 469,
+ .key_start_idx = 532,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 520,
+ .result_start_idx = 453,
.result_bit_size = 64,
.result_num_fields = 13,
- .ident_start_idx = 20,
- .ident_nums = 0
+ .ident_start_idx = 25,
+ .ident_nums = 1
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 545,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 466,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 5, , table: parif_def_lkup_arec_ptr.vf_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
+ .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 470,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
+ .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 471,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
+ .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 472,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 5, , table: int_full_act_record.vf_ing */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 473,
+ .result_bit_size = 128,
+ .result_num_fields = 26,
+ .encap_num_fields = 0
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */
+ { /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vf_ing */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
.direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 0,
- .cond_false_goto = 0,
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 43,
+ .cond_start_idx = 48,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
@@ -1629,19 +1747,224 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 482,
+ .key_start_idx = 546,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 533,
+ .result_start_idx = 499,
.result_bit_size = 64,
.result_num_fields = 13,
- .ident_start_idx = 20,
+ .ident_start_idx = 26,
.ident_nums = 0
- }
-};
-
-struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_rd_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 559,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 26,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: control.vfr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 48,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 560,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 512,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .ident_start_idx = 26,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 573,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 525,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 5, , table: int_vtag_encap_record.vfr_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 529,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 12
+ },
+ { /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 541,
+ .result_bit_size = 128,
+ .result_num_fields = 26
+ },
+ { /* class_tid: 5, , table: int_full_act_record.vfr_ing0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 567,
+ .result_bit_size = 128,
+ .result_num_fields = 26
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 574,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 593,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .ident_start_idx = 26,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 587,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 606,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .ident_start_idx = 26,
+ .ident_nums = 0
+ }
+};
+
+struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {
/* cond_reject: wh_plus, class_tid: 1 */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
@@ -1751,32 +2074,61 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
.cond_operand = BNXT_ULP_CF_IDX_WC_MATCH
},
- /* cond_execute: class_tid: 2, l2_cntxt_tcam_cache.rd */
+ /* cond_execute: class_tid: 2, control.tunnel_cache_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 2, control.flow_type_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_F1
+ },
+ /* cond_execute: class_tid: 2, control.mac_addr_cache_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 2, control.profile_tcam_cache.f2_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 2, em.tun */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET,
+ },
+ /* cond_reject: wh_plus, class_tid: 3 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH
+ },
+ /* cond_execute: class_tid: 3, l2_cntxt_tcam_cache.rd */
{
.cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET,
.cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC
},
- /* cond_execute: class_tid: 2, control.0 */
+ /* cond_execute: class_tid: 3, control.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 2, control.gen_tbl_miss */
+ /* cond_execute: class_tid: 3, control.gen_tbl_miss */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 2, control.conflict_check */
+ /* cond_execute: class_tid: 3, control.conflict_check */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_CC
},
- /* cond_execute: class_tid: 2, profile_tcam.ipv4 */
+ /* cond_execute: class_tid: 3, profile_tcam.ipv4 */
{
.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
},
- /* cond_execute: class_tid: 2, em.ipv4 */
+ /* cond_execute: class_tid: 3, em.ipv4 */
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET,
},
@@ -1784,7 +2136,7 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
},
- /* cond_execute: class_tid: 2, eem.ipv4 */
+ /* cond_execute: class_tid: 3, eem.ipv4 */
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_IS_SET,
},
@@ -1792,31 +2144,31 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
},
- /* cond_execute: class_tid: 2, em.ipv6 */
+ /* cond_execute: class_tid: 3, em.ipv6 */
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET,
},
- /* cond_execute: class_tid: 3, control.ing_0 */
+ /* cond_execute: class_tid: 4, control.ing_0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 3, control.egr_0 */
+ /* cond_execute: class_tid: 4, control.egr_0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
},
- /* cond_execute: class_tid: 3, control.egr_1 */
+ /* cond_execute: class_tid: 4, control.egr_1 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 3, control.egr_2 */
+ /* cond_execute: class_tid: 4, control.egr_2 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 3, l2_cntxt_tcam_cache.egr_wr */
+ /* cond_execute: class_tid: 4, l2_cntxt_tcam_cache.egr_wr */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
@@ -1825,12 +2177,12 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 4, control.vf_0 */
+ /* cond_execute: class_tid: 5, control.vf_0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 4, control.vfr_0 */
+ /* cond_execute: class_tid: 5, control.vfr_0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
@@ -5669,7 +6021,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
}
},
- /* class_tid: 2, , table: l2_cntxt_tcam_cache.rd */
+ /* class_tid: 2, , table: tunnel_cache.rd */
{
.field_info_mask = {
.description = "svif",
@@ -5690,181 +6042,52 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
}
},
- /* class_tid: 2, , table: mac_addr_cache.rd */
{
.field_info_mask = {
- .description = "svif",
+ .description = "tunnel_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ 0xff}
},
.field_info_spec = {
- .description = "svif",
+ .description = "tunnel_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ (BNXT_ULP_CF_IDX_TUNNEL_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_TUNNEL_ID & 0xff}
}
},
+ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
{
.field_info_mask = {
- .description = "tun_hdr",
- .field_bit_size = 4,
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr",
- .field_bit_size = 4,
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "one_tag",
- .field_bit_size = 1,
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "one_tag",
- .field_bit_size = 1,
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
- }
- },
- {
- .field_info_mask = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
- },
- .field_info_spec = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
- }
- },
- /* class_tid: 2, , table: l2_cntxt_tcam.0 */
- {
- .field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -5872,19 +6095,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "mac0_addr",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "mac0_addr",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -5892,19 +6109,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "svif",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "svif",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -5968,18 +6179,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "l2_num_vtags",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l2_num_vtags",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -6046,7 +6252,47 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
1}
}
},
- /* class_tid: 2, , table: mac_addr_cache.wr */
+ /* class_tid: 2, , table: tunnel_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_TUNNEL_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_TUNNEL_ID & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: mac_addr_cache.rd */
{
.field_info_mask = {
.description = "svif",
@@ -6072,17 +6318,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "tun_hdr",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ 0xff}
},
.field_info_spec = {
.description = "tun_hdr",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -6090,60 +6334,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "one_tag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "one_tag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
.description = "vid",
.field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "vid",
.field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -6153,8 +6364,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
},
.field_info_spec = {
.description = "mac_addr",
@@ -6162,204 +6373,166 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
- /* class_tid: 2, , table: profile_tcam_cache.rd */
+ /* class_tid: 2, , table: l2_cntxt_tcam.0 */
{
.field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
+ .description = "mac0_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
+ .description = "mac0_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
- /* class_tid: 2, , table: profile_tcam.ipv4 */
{
.field_info_mask = {
- .description = "l4_hdr_is_udp_tcp",
- .field_bit_size = 1,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
},
.field_info_spec = {
- .description = "l4_hdr_is_udp_tcp",
- .field_bit_size = 1,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
}
},
{
.field_info_mask = {
- .description = "l4_hdr_type",
+ .description = "sparif",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l4_hdr_type",
+ .description = "sparif",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_WP_SYM_L4_HDR_TYPE_TCP},
- .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr3 = {
- ULP_WP_SYM_L4_HDR_TYPE_UDP}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4_hdr_error",
- .field_bit_size = 1,
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l4_hdr_error",
- .field_bit_size = 1,
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4_hdr_valid",
- .field_bit_size = 1,
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l4_hdr_valid",
- .field_bit_size = 1,
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_ipv6_cmp_dst",
- .field_bit_size = 1,
+ .description = "mac1_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_ipv6_cmp_dst",
- .field_bit_size = 1,
+ .description = "mac1_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_hdr_type",
+ .description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
@@ -6367,7 +6540,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "l3_hdr_type",
+ .description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6375,162 +6548,200 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "l3_hdr_error",
- .field_bit_size = 1,
+ .description = "key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_hdr_error",
- .field_bit_size = 1,
+ .description = "key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_hdr_valid",
+ .description = "valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 0xff}
+ 1}
},
.field_info_spec = {
- .description = "l3_hdr_valid",
+ .description = "valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ULP_WP_SYM_L3_HDR_VALID_YES}
+ 1}
}
},
+ /* class_tid: 2, , table: mac_addr_cache.wr */
{
.field_info_mask = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
+ .description = "tun_hdr",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_vtag_present",
+ .description = "one_tag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_vtag_present",
+ .description = "one_tag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_uc_mc_bc",
- .field_bit_size = 2,
+ .description = "vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_uc_mc_bc",
- .field_bit_size = 2,
+ .description = "vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_hdr_type",
- .field_bit_size = 2,
+ .description = "mac_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "l2_hdr_type",
- .field_bit_size = 2,
+ .description = "mac_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
+ /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
{
.field_info_mask = {
- .description = "l2_hdr_error",
- .field_bit_size = 1,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l2_hdr_error",
- .field_bit_size = 1,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_hdr_valid",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l2_hdr_valid",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- ULP_WP_SYM_L2_HDR_VALID_YES}
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "tun_hdr_flags",
- .field_bit_size = 3,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: profile_tcam.f2 */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_flags",
- .field_bit_size = 3,
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
+ .description = "l4_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_type",
+ .description = "l4_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6538,13 +6749,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tun_hdr_err",
+ .description = "l4_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_err",
+ .description = "l4_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6552,15 +6763,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tun_hdr_valid",
+ .description = "l4_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_valid",
+ .description = "l4_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6568,13 +6777,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl4_hdr_is_udp_tcp",
+ .description = "l3_ipv6_cmp_dst",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4_hdr_is_udp_tcp",
+ .description = "l3_ipv6_cmp_dst",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6582,27 +6791,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl4_hdr_type",
- .field_bit_size = 4,
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4_hdr_type",
- .field_bit_size = 4,
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4_hdr_error",
+ .description = "l3_hdr_isIP",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4_hdr_error",
+ .description = "l3_hdr_isIP",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6610,29 +6819,44 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl4_hdr_valid",
- .field_bit_size = 1,
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "tl4_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_WP_SYM_L3_HDR_TYPE_IPV4},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_WP_SYM_L3_HDR_TYPE_IPV6}
}
},
{
.field_info_mask = {
- .description = "tl3_ipv6_cmp_dst",
+ .description = "l3_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3_ipv6_cmp_dst",
+ .description = "l3_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6640,27 +6864,31 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl3_ipv6_cmp_src",
+ .description = "l3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3_ipv6_cmp_src",
+ .description = "l3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_L3_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl3_hdr_isIP",
+ .description = "l2_two_vtags",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3_hdr_isIP",
+ .description = "l2_two_vtags",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6668,57 +6896,55 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl3_hdr_type",
- .field_bit_size = 4,
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3_hdr_type",
- .field_bit_size = 4,
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3_hdr_error",
- .field_bit_size = 1,
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3_hdr_error",
- .field_bit_size = 1,
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3_hdr_valid",
- .field_bit_size = 1,
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3_hdr_valid",
- .field_bit_size = 1,
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_two_vtags",
+ .description = "l2_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_two_vtags",
+ .description = "l2_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6726,13 +6952,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl2_vtag_present",
+ .description = "l2_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_vtag_present",
+ .description = "l2_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6740,35 +6966,37 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl2_uc_mc_bc",
- .field_bit_size = 2,
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_uc_mc_bc",
- .field_bit_size = 2,
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_hdr_type",
- .field_bit_size = 2,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_hdr_type",
- .field_bit_size = 2,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_hdr_valid",
+ .description = "tun_hdr_err",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
@@ -6776,7 +7004,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "tl2_hdr_valid",
+ .description = "tun_hdr_err",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6784,68 +7012,65 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "hrec_next",
+ .description = "tun_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "hrec_next",
+ .description = "tun_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_TUN_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "reserved",
- .field_bit_size = 9,
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "reserved",
- .field_bit_size = 9,
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ ULP_WP_SYM_TL4_HDR_TYPE_UDP}
}
},
{
.field_info_mask = {
- .description = "agg_error",
+ .description = "tl4_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "agg_error",
+ .description = "tl4_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6853,159 +7078,137 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_TL4_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "pkt_type_0",
- .field_bit_size = 2,
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "pkt_type_0",
- .field_bit_size = 2,
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "pkt_type_1",
- .field_bit_size = 2,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "pkt_type_1",
- .field_bit_size = 2,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "valid",
+ .description = "tl3_hdr_isIP",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "valid",
+ .description = "tl3_hdr_isIP",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 2, , table: profile_tcam.ipv6 */
{
.field_info_mask = {
- .description = "l4_hdr_is_udp_tcp",
- .field_bit_size = 1,
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "l4_hdr_is_udp_tcp",
- .field_bit_size = 1,
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ 0xff}
},
.field_info_spec = {
- .description = "l4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_WP_SYM_L4_HDR_TYPE_TCP},
- .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr3 = {
- ULP_WP_SYM_L4_HDR_TYPE_UDP}
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4_hdr_error",
+ .description = "tl3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ 0xff}
},
.field_info_spec = {
- .description = "l4_hdr_error",
+ .description = "tl3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_TL3_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "l4_hdr_valid",
+ .description = "tl2_two_vtags",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l4_hdr_valid",
+ .description = "tl2_two_vtags",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_ipv6_cmp_dst",
+ .description = "tl2_vtag_present",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_ipv6_cmp_dst",
+ .description = "tl2_vtag_present",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -7013,61 +7216,61 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_hdr_type",
- .field_bit_size = 4,
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l3_hdr_type",
- .field_bit_size = 4,
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ULP_WP_SYM_L3_HDR_TYPE_IPV6}
+ ULP_WP_SYM_TL2_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "l3_hdr_error",
+ .description = "hrec_next",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_hdr_error",
+ .description = "hrec_next",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -7075,68 +7278,60 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "l3_hdr_valid",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_hdr_valid",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_L3_HDR_VALID_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "l2_vtag_present",
+ .description = "agg_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_vtag_present",
+ .description = "agg_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_uc_mc_bc",
+ .description = "recycle_cnt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_uc_mc_bc",
+ .description = "recycle_cnt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -7144,15 +7339,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "l2_hdr_type",
+ .description = "pkt_type_0",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_hdr_type",
+ .description = "pkt_type_0",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -7160,1487 +7353,1459 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "l2_hdr_error",
- .field_bit_size = 1,
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_hdr_error",
- .field_bit_size = 1,
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_hdr_valid",
+ .description = "valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 0xff}
+ 1}
},
.field_info_spec = {
- .description = "l2_hdr_valid",
+ .description = "valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ULP_WP_SYM_L2_HDR_VALID_YES}
+ 1}
}
},
+ /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
{
.field_info_mask = {
- .description = "tun_hdr_flags",
- .field_bit_size = 3,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tun_hdr_flags",
- .field_bit_size = 3,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "tun_hdr_err",
- .field_bit_size = 1,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tun_hdr_err",
- .field_bit_size = 1,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
}
},
+ /* class_tid: 2, , table: em.tun */
{
.field_info_mask = {
- .description = "tun_hdr_valid",
- .field_bit_size = 1,
+ .description = "spare",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_valid",
- .field_bit_size = 1,
+ .description = "spare",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4_hdr_is_udp_tcp",
- .field_bit_size = 1,
+ .description = "l2.ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4_hdr_is_udp_tcp",
- .field_bit_size = 1,
+ .description = "l2.ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2.dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "tl4_hdr_type",
- .field_bit_size = 4,
+ .description = "l2.dmac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl4_hdr_error",
- .field_bit_size = 1,
+ .description = "tun_id",
+ .field_bit_size = 24,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}
},
.field_info_spec = {
- .description = "tl4_hdr_error",
- .field_bit_size = 1,
+ .description = "tun_id",
+ .field_bit_size = 24,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl4_hdr_valid",
- .field_bit_size = 1,
+ .description = "tun_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4_hdr_valid",
- .field_bit_size = 1,
+ .description = "tun_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3_ipv6_cmp_dst",
- .field_bit_size = 1,
+ .description = "tun_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3_ipv6_cmp_dst",
- .field_bit_size = 1,
+ .description = "tun_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3_ipv6_cmp_src",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "tl3_ipv6_cmp_src",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl3_hdr_isIP",
- .field_bit_size = 1,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3_hdr_isIP",
- .field_bit_size = 1,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
}
},
+ /* class_tid: 2, , table: eem.tun */
{
.field_info_mask = {
- .description = "tl3_hdr_type",
- .field_bit_size = 4,
+ .description = "spare",
+ .field_bit_size = 339,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3_hdr_type",
- .field_bit_size = 4,
+ .description = "spare",
+ .field_bit_size = 339,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3_hdr_error",
- .field_bit_size = 1,
+ .description = "l2.ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3_hdr_error",
- .field_bit_size = 1,
+ .description = "l2.ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3_hdr_valid",
- .field_bit_size = 1,
+ .description = "l2.dmac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "tl3_hdr_valid",
- .field_bit_size = 1,
+ .description = "l2.dmac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl2_two_vtags",
- .field_bit_size = 1,
+ .description = "tun_id",
+ .field_bit_size = 24,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}
},
.field_info_spec = {
- .description = "tl2_two_vtags",
- .field_bit_size = 1,
+ .description = "tun_id",
+ .field_bit_size = 24,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl2_vtag_present",
- .field_bit_size = 1,
+ .description = "tun_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_vtag_present",
- .field_bit_size = 1,
+ .description = "tun_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_uc_mc_bc",
- .field_bit_size = 2,
+ .description = "tun_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_uc_mc_bc",
- .field_bit_size = 2,
+ .description = "tun_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_hdr_type",
- .field_bit_size = 2,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_hdr_type",
- .field_bit_size = 2,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl2_hdr_valid",
- .field_bit_size = 1,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "tl2_hdr_valid",
- .field_bit_size = 1,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
}
},
+ /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
{
.field_info_mask = {
- .description = "hrec_next",
- .field_bit_size = 1,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
},
.field_info_spec = {
- .description = "hrec_next",
- .field_bit_size = 1,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
}
},
+ /* class_tid: 3, , table: mac_addr_cache.rd */
{
.field_info_mask = {
- .description = "reserved",
- .field_bit_size = 9,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
},
.field_info_spec = {
- .description = "reserved",
- .field_bit_size = 9,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
}
},
{
.field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "tun_hdr",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 0xff}
+ ULP_WP_SYM_TUN_HDR_TYPE_NONE}
},
.field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ ULP_WP_SYM_TUN_HDR_TYPE_NONE}
}
},
{
.field_info_mask = {
- .description = "agg_error",
+ .description = "one_tag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "agg_error",
+ .description = "one_tag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
}
},
{
.field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "pkt_type_0",
- .field_bit_size = 2,
+ .description = "mac_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
},
.field_info_spec = {
- .description = "pkt_type_0",
- .field_bit_size = 2,
+ .description = "mac_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
}
},
+ /* class_tid: 3, , table: l2_cntxt_tcam.0 */
{
.field_info_mask = {
- .description = "pkt_type_1",
- .field_bit_size = 2,
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "pkt_type_1",
- .field_bit_size = 2,
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
+ .description = "mac0_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
},
.field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
+ .description = "mac0_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
}
},
- /* class_tid: 2, , table: profile_tcam_cache.wr */
{
.field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 0xff}
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
},
.field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
}
},
{
.field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "sparif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 2, , table: em.ipv4 */
{
.field_info_mask = {
- .description = "spare",
- .field_bit_size = 3,
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "spare",
- .field_bit_size = 3,
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "mac1_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "mac1_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4.dst",
- .field_bit_size = 16,
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff}
}
},
{
.field_info_mask = {
- .description = "l4.src",
- .field_bit_size = 16,
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3.prot",
- .field_bit_size = 8,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 0xff}
+ ULP_WP_SYM_TUN_HDR_TYPE_NONE}
},
.field_info_spec = {
- .description = "l3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ ULP_WP_SYM_TUN_HDR_TYPE_NONE}
}
},
{
.field_info_mask = {
- .description = "l3.dst",
- .field_bit_size = 32,
+ .description = "key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3.dst",
- .field_bit_size = 32,
+ .description = "key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3.src",
- .field_bit_size = 32,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ 1}
},
.field_info_spec = {
- .description = "l3.src",
- .field_bit_size = 32,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ 1}
}
},
+ /* class_tid: 3, , table: mac_addr_cache.wr */
{
.field_info_mask = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
},
.field_info_spec = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
}
},
{
.field_info_mask = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "tun_hdr",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 0xff,
- 0xff}
+ ULP_WP_SYM_TUN_HDR_TYPE_NONE}
},
.field_info_spec = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "tun_hdr",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ ULP_WP_SYM_TUN_HDR_TYPE_NONE}
}
},
{
.field_info_mask = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "one_tag",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "one_tag",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
}
},
- /* class_tid: 2, , table: eem.ipv4 */
{
.field_info_mask = {
- .description = "spare",
- .field_bit_size = 275,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "spare",
- .field_bit_size = 275,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "mac_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
},
.field_info_spec = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "mac_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
}
},
+ /* class_tid: 3, , table: profile_tcam_cache.rd */
{
.field_info_mask = {
- .description = "l4.dst",
- .field_bit_size = 16,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4.src",
- .field_bit_size = 16,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l4.src",
- .field_bit_size = 16,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "l3.prot",
- .field_bit_size = 8,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
}
},
+ /* class_tid: 3, , table: profile_tcam.ipv4 */
{
.field_info_mask = {
- .description = "l3.dst",
- .field_bit_size = 32,
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3.dst",
- .field_bit_size = 32,
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3.src",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3.src",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_WP_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_WP_SYM_L4_HDR_TYPE_UDP}
}
},
{
.field_info_mask = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
},
.field_info_spec = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 0xff,
- 0xff}
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
},
.field_info_spec = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
}
},
{
.field_info_mask = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 2, , table: em.ipv6 */
{
.field_info_mask = {
- .description = "spare",
- .field_bit_size = 3,
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "spare",
- .field_bit_size = 3,
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4.dst",
- .field_bit_size = 16,
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4.src",
- .field_bit_size = 16,
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3.prot",
- .field_bit_size = 8,
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ ULP_WP_SYM_L3_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "l3.dst",
- .field_bit_size = 128,
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ 0xff}
},
.field_info_spec = {
- .description = "l3.dst",
- .field_bit_size = 128,
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3.src",
- .field_bit_size = 128,
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ 0xff}
},
.field_info_spec = {
- .description = "l3.src",
- .field_bit_size = 128,
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
}
},
{
.field_info_mask = {
- .description = "l2.smac",
- .field_bit_size = 48,
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "l2.smac",
- .field_bit_size = 48,
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ 0xff}
},
.field_info_spec = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ ULP_WP_SYM_L2_HDR_VALID_YES}
}
},
- /* class_tid: 2, , table: eem.ipv6 */
{
.field_info_mask = {
- .description = "spare",
- .field_bit_size = 35,
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "spare",
- .field_bit_size = 35,
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4.dst",
- .field_bit_size = 16,
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l4.src",
- .field_bit_size = 16,
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3.prot",
- .field_bit_size = 8,
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l3.dst",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
- },
- .field_info_spec = {
- .description = "l3.dst",
- .field_bit_size = 128,
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3.src",
- .field_bit_size = 128,
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3.src",
- .field_bit_size = 128,
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2.smac",
- .field_bit_size = 48,
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2.smac",
- .field_bit_size = 48,
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l2_num_vtags",
+ .description = "tl2_hdr_type",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_num_vtags",
+ .description = "tl2_hdr_type",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -8648,491 +8813,511 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "hrec_next",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "hrec_next",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "reserved",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "reserved",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- .field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- }
- },
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */
- {
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd_vfr */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "agg_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "agg_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_bypass.egr_vfr */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 0xff}
+ 1}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ 1}
}
},
+ /* class_tid: 3, , table: profile_tcam.ipv6 */
{
.field_info_mask = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_WP_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_WP_SYM_L4_HDR_TYPE_UDP}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
},
.field_info_spec = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
},
.field_info_spec = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
}
},
{
.field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
+ .description = "l3_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tun_hdr_type",
+ .description = "l3_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_L3_HDR_TYPE_IPV6}
}
},
{
.field_info_mask = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "valid",
+ .description = "l3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 1}
+ 0xff}
},
.field_info_spec = {
- .description = "valid",
+ .description = "l3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ ULP_WP_SYM_L3_HDR_VALID_YES}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
- }
- },
- {
- .field_info_mask = {
- .description = "sparif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "sparif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ ULP_WP_SYM_L2_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
+ .description = "tl4_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_type",
+ .description = "tl4_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -9140,203 +9325,171 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "valid",
+ .description = "tl4_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 1}
+ 0xff}
},
.field_info_spec = {
- .description = "valid",
+ .description = "tl4_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_rd_egr */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "sparif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_num_vtags",
+ .description = "tl2_hdr_type",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_num_vtags",
+ .description = "tl2_hdr_type",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -9344,280 +9497,294 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "hrec_next",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "hrec_next",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "reserved",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "reserved",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 1}
+ 0xff}
},
.field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_egr_wr */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "agg_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "agg_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vf_ing */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 0xff}
+ 1}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ 1}
}
},
+ /* class_tid: 3, , table: profile_tcam_cache.wr */
{
.field_info_mask = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
}
},
+ /* class_tid: 3, , table: em.ipv4 */
{
.field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "spare",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "spare",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "local_cos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "local_cos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "l4.dst",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "l4.src",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "key_type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "key_type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- .field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_rd_egr0 */
{
.field_info_mask = {
- .description = "svif",
+ .description = "l3.prot",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
@@ -9625,211 +9792,305 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "svif",
+ .description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_egr0 */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l3.dst",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l3.dst",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l3.src",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l3.src",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
+ .description = "l2.dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "mac0_addr",
+ .description = "l2.dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
+ 0xff,
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
}
},
{
.field_info_mask = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
}
},
+ /* class_tid: 3, , table: eem.ipv4 */
{
.field_info_mask = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "spare",
+ .field_bit_size = 275,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "spare",
+ .field_bit_size = 275,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "local_cos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "local_cos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "l4.dst",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "l4.src",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "l3.prot",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "l3.dst",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
},
.field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "l3.dst",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
}
},
{
.field_info_mask = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "l3.src",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
},
.field_info_spec = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "l3.src",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
}
},
{
.field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
+ .description = "l2.dmac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
+ .description = "l2.dmac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
{
.field_info_mask = {
- .description = "svif",
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "em_profile_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
@@ -9837,34 +10098,48 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "svif",
+ .description = "em_profile_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */
+ /* class_tid: 3, , table: em.ipv6 */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "spare",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "spare",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "local_cos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "local_cos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
@@ -9872,32 +10147,48 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "l4.src",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "svif",
+ .description = "l3.prot",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
@@ -9905,154 +10196,314 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "svif",
+ .description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "l3.dst",
+ .field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
},
.field_info_spec = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "l3.dst",
+ .field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l3.src",
+ .field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
},
.field_info_spec = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l3.src",
+ .field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l2.smac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l2.smac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac1_addr",
+ .description = "l2.dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "mac1_addr",
+ .description = "l2.dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
{
.field_info_mask = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
+ 0xff,
0xff}
},
.field_info_spec = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- 2}
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
}
},
+ /* class_tid: 3, , table: eem.ipv6 */
{
.field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "spare",
+ .field_bit_size = 35,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "spare",
+ .field_bit_size = 35,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "local_cos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "local_cos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
+ .description = "l4.dst",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 1}
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 1}
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dst",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3.dst",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.src",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3.src",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2.smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2.smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2.dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2.dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
@@ -10060,13 +10511,67 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -10112,8 +10617,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
}
},
{
@@ -10177,17 +10682,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "l2_num_vtags",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l2_num_vtags",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -10249,529 +10750,2581 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.field_opr1 = {
1}
}
- }
-};
-
-struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
- /* class_tid: 1, , table: l2_cntxt_tcam.0 */
- {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
{
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ }
},
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd_vfr */
{
- .description = "l2_byp_lkup_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_bypass.egr_vfr */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vf_ing */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_rd_egr0 */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_egr0 */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 2}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ }
+};
+
+struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
+ /* class_tid: 1, , table: l2_cntxt_tcam.0 */
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}
+ },
+ {
+ .description = "l2_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ },
+ {
+ .description = "allowed_pri",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "default_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "allowed_tpid",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "default_tpid",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "bd_act_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "byp_sp_lkup",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "pri_anti_spoof_ctl",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tpid_anti_spoof_ctl",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: mac_addr_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.ipv4 */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.0",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_mask.1",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ },
+ {
+ .description = "em_key_mask.2",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ },
+ {
+ .description = "em_key_mask.3",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ },
+ {
+ .description = "em_key_mask.4",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}
+ },
+ {
+ .description = "em_key_mask.5",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}
+ },
+ {
+ .description = "em_key_mask.6",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}
+ },
+ {
+ .description = "em_key_mask.7",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.8",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.9",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.ipv6 */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.0",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_mask.1",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.2",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ },
+ {
+ .description = "em_key_mask.3",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
},
{
- .description = "parif",
+ .description = "em_key_mask.4",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ },
+ {
+ .description = "em_key_mask.5",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}
+ },
+ {
+ .description = "em_key_mask.6",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}
+ },
+ {
+ .description = "em_key_mask.7",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}
+ },
+ {
+ .description = "em_key_mask.8",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.9",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 7}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.ipv4_vxlan */
+ {
+ .description = "wc_key_id",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.0",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_mask.1",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.2",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.3",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.4",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_mask.5",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_mask.6",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_mask.7",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.8",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.9",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 20}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
+ /* class_tid: 1, , table: em.ipv4 */
{
- .description = "allowed_pri",
- .field_bit_size = 8,
+ .description = "act_rec_ptr",
+ .field_bit_size = 33,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "default_pri",
- .field_bit_size = 3,
+ .description = "ext_flow_cntr",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "allowed_tpid",
- .field_bit_size = 6,
+ .description = "act_rec_int",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "default_tpid",
- .field_bit_size = 3,
+ .description = "act_rec_size",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "bd_act_en",
- .field_bit_size = 1,
+ .description = "key_size",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
+ .description = "reserved",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "byp_sp_lkup",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ 3}
},
{
- .description = "pri_anti_spoof_ctl",
- .field_bit_size = 2,
+ .description = "l1_cacheable",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tpid_anti_spoof_ctl",
- .field_bit_size = 2,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
- /* class_tid: 1, , table: mac_addr_cache.wr */
+ /* class_tid: 1, , table: eem.ipv4 */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "act_rec_ptr",
+ .field_bit_size = 33,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "l2_cntxt_tcam_index",
- .field_bit_size = 10,
+ .description = "ext_flow_cntr",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "act_rec_int",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "act_rec_size",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "key_size",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ (173 >> 8) & 0xff,
+ 173 & 0xff}
},
- /* class_tid: 1, , table: profile_tcam.ipv4 */
{
- .description = "wc_key_id",
- .field_bit_size = 4,
+ .description = "reserved",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
},
{
- .description = "wc_search_en",
+ .description = "l1_cacheable",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.0",
+ .description = "valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 1, , table: em.ipv6 */
{
- .description = "em_key_mask.1",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 33,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "em_key_mask.2",
+ .description = "ext_flow_cntr",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.3",
+ .description = "act_rec_int",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.4",
- .field_bit_size = 1,
+ .description = "act_rec_size",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "key_size",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}
+ 3}
},
{
- .description = "em_key_mask.5",
+ .description = "l1_cacheable",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.6",
+ .description = "valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}
+ 1}
},
+ /* class_tid: 1, , table: eem.ipv6 */
{
- .description = "em_key_mask.7",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 33,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "em_key_mask.8",
+ .description = "ext_flow_cntr",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.9",
+ .description = "act_rec_int",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
+ .description = "act_rec_size",
.field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- 3}
+ (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "key_size",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ (413 >> 8) & 0xff,
+ 413 & 0xff}
},
{
- .description = "em_search_en",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ 3}
},
{
- .description = "pl_byp_lkup_en",
+ .description = "l1_cacheable",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam.ipv6 */
{
- .description = "wc_key_id",
- .field_bit_size = 4,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 1, , table: em.vxlan */
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "act_rec_ptr",
+ .field_bit_size = 33,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "wc_search_en",
+ .description = "ext_flow_cntr",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.0",
+ .description = "act_rec_int",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.1",
- .field_bit_size = 1,
+ .description = "act_rec_size",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.2",
- .field_bit_size = 1,
+ .description = "key_size",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.3",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.4",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ 3}
},
{
- .description = "em_key_mask.5",
+ .description = "l1_cacheable",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.6",
+ .description = "valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}
+ 1}
},
+ /* class_tid: 1, , table: eem.vxlan */
{
- .description = "em_key_mask.7",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .description = "act_rec_ptr",
+ .field_bit_size = 33,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "em_key_mask.8",
+ .description = "ext_flow_cntr",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.9",
+ .description = "act_rec_int",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
+ .description = "act_rec_size",
.field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 7}
- },
- {
- .description = "em_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}
},
{
- .description = "em_search_en",
- .field_bit_size = 1,
+ .description = "key_size",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
- },
- {
- .description = "pl_byp_lkup_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (197 >> 8) & 0xff,
+ 197 & 0xff}
},
- /* class_tid: 1, , table: profile_tcam.ipv4_vxlan */
{
- .description = "wc_key_id",
- .field_bit_size = 4,
+ .description = "reserved",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
},
{
- .description = "wc_search_en",
+ .description = "l1_cacheable",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.0",
+ .description = "valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
{
- .description = "em_key_mask.1",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.2",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.3",
+ .description = "l2_byp_lkup_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.4",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.5",
- .field_bit_size = 1,
+ .description = "allowed_pri",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.6",
- .field_bit_size = 1,
+ .description = "default_pri",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.7",
- .field_bit_size = 1,
+ .description = "allowed_tpid",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.8",
- .field_bit_size = 1,
+ .description = "default_tpid",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.9",
+ .description = "bd_act_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 20}
- },
- {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_search_en",
+ .description = "byp_sp_lkup",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -10779,12 +13332,18 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
1}
},
{
- .description = "pl_byp_lkup_en",
- .field_bit_size = 1,
+ .description = "pri_anti_spoof_ctl",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam_cache.wr */
+ {
+ .description = "tpid_anti_spoof_ctl",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 2, , table: tunnel_cache.wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -10795,299 +13354,303 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "profile_tcam_index",
+ .description = "l2_cntxt_tcam_index",
.field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
- },
- {
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
+ /* class_tid: 2, , table: l2_cntxt_tcam.0 */
{
- .description = "flow_sig_id",
- .field_bit_size = 64,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
- /* class_tid: 1, , table: em.ipv4 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 33,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
},
{
- .description = "ext_flow_cntr",
+ .description = "l2_byp_lkup_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "act_rec_int",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ },
+ {
+ .description = "allowed_pri",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "act_rec_size",
- .field_bit_size = 5,
+ .description = "default_pri",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "key_size",
- .field_bit_size = 9,
+ .description = "allowed_tpid",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "reserved",
- .field_bit_size = 11,
+ .description = "default_tpid",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "bd_act_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 3}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l1_cacheable",
- .field_bit_size = 1,
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "valid",
+ .description = "byp_sp_lkup",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
- /* class_tid: 1, , table: eem.ipv4 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 33,
+ .description = "pri_anti_spoof_ctl",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ext_flow_cntr",
- .field_bit_size = 1,
+ .description = "tpid_anti_spoof_ctl",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 2, , table: mac_addr_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
{
- .description = "act_rec_int",
- .field_bit_size = 1,
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "act_rec_size",
- .field_bit_size = 5,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,
- BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .description = "key_size",
- .field_bit_size = 9,
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- (173 >> 8) & 0xff,
- 173 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 2, , table: profile_tcam.f2 */
{
- .description = "reserved",
- .field_bit_size = 11,
+ .description = "wc_key_id",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 3}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l1_cacheable",
+ .description = "wc_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "valid",
+ .description = "em_key_mask.0",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
- /* class_tid: 1, , table: em.ipv6 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 33,
+ .description = "em_key_mask.1",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ 1}
},
{
- .description = "ext_flow_cntr",
+ .description = "em_key_mask.2",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "act_rec_int",
+ .description = "em_key_mask.3",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "act_rec_size",
- .field_bit_size = 5,
+ .description = "em_key_mask.4",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "key_size",
- .field_bit_size = 9,
+ .description = "em_key_mask.5",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "reserved",
- .field_bit_size = 11,
+ .description = "em_key_mask.6",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "em_key_mask.7",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 3}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l1_cacheable",
+ .description = "em_key_mask.8",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "valid",
+ .description = "em_key_mask.9",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ 8}
},
- /* class_tid: 1, , table: eem.ipv6 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 33,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
},
{
- .description = "ext_flow_cntr",
+ .description = "em_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "act_rec_int",
+ .description = "pl_byp_lkup_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
{
- .description = "act_rec_size",
- .field_bit_size = 5,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,
- BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "key_size",
- .field_bit_size = 9,
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (413 >> 8) & 0xff,
- 413 & 0xff}
- },
- {
- .description = "reserved",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- 3}
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
},
{
- .description = "l1_cacheable",
- .field_bit_size = 1,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "valid",
- .field_bit_size = 1,
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
- /* class_tid: 1, , table: em.vxlan */
+ /* class_tid: 2, , table: em.tun */
{
.description = "act_rec_ptr",
.field_bit_size = 33,
@@ -11149,7 +13712,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 1, , table: eem.vxlan */
+ /* class_tid: 2, , table: eem.tun */
{
.description = "act_rec_ptr",
.field_bit_size = 33,
@@ -11186,8 +13749,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (197 >> 8) & 0xff,
- 197 & 0xff}
+ (109 >> 8) & 0xff,
+ 109 & 0xff}
},
{
.description = "reserved",
@@ -11217,7 +13780,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 2, , table: l2_cntxt_tcam.0 */
+ /* class_tid: 3, , table: l2_cntxt_tcam.0 */
{
.description = "l2_cntxt_id",
.field_bit_size = 10,
@@ -11317,7 +13880,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: mac_addr_cache.wr */
+ /* class_tid: 3, , table: mac_addr_cache.wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -11351,7 +13914,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: profile_tcam.ipv4 */
+ /* class_tid: 3, , table: profile_tcam.ipv4 */
{
.description = "wc_key_id",
.field_bit_size = 4,
@@ -11497,7 +14060,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: profile_tcam.ipv6 */
+ /* class_tid: 3, , table: profile_tcam.ipv6 */
{
.description = "wc_key_id",
.field_bit_size = 4,
@@ -11643,7 +14206,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: profile_tcam_cache.wr */
+ /* class_tid: 3, , table: profile_tcam_cache.wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -11686,7 +14249,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
- /* class_tid: 2, , table: em.ipv4 */
+ /* class_tid: 3, , table: em.ipv4 */
{
.description = "act_rec_ptr",
.field_bit_size = 33,
@@ -11748,7 +14311,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 2, , table: eem.ipv4 */
+ /* class_tid: 3, , table: eem.ipv4 */
{
.description = "act_rec_ptr",
.field_bit_size = 33,
@@ -11816,7 +14379,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 2, , table: em.ipv6 */
+ /* class_tid: 3, , table: em.ipv6 */
{
.description = "act_rec_ptr",
.field_bit_size = 33,
@@ -11878,7 +14441,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 2, , table: eem.ipv6 */
+ /* class_tid: 3, , table: eem.ipv6 */
{
.description = "act_rec_ptr",
.field_bit_size = 33,
@@ -11946,7 +14509,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 3, , table: int_full_act_record.ing_0 */
+ /* class_tid: 4, , table: int_full_act_record.ing_0 */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -12106,7 +14669,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
.description = "l2_cntxt_id",
.field_bit_size = 10,
@@ -12196,7 +14759,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -12230,7 +14793,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: parif_def_lkup_arec_ptr.ing_0 */
+ /* class_tid: 4, , table: parif_def_lkup_arec_ptr.ing_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -12240,7 +14803,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */
+ /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -12250,7 +14813,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */
+ /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -12260,7 +14823,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 3, , table: int_full_act_record.egr_vfr */
+ /* class_tid: 4, , table: int_full_act_record.egr_vfr */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -12420,7 +14983,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: l2_cntxt_tcam_bypass.egr_vfr */
+ /* class_tid: 4, , table: l2_cntxt_tcam_bypass.egr_vfr */
{
.description = "act_record_ptr",
.field_bit_size = 16,
@@ -12508,7 +15071,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
{
.description = "rid",
.field_bit_size = 32,
@@ -12539,7 +15102,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
.description = "l2_cntxt_id",
.field_bit_size = 10,
@@ -12629,7 +15192,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -12663,7 +15226,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: int_full_act_record.egr_0 */
+ /* class_tid: 4, , table: int_full_act_record.egr_0 */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -12823,7 +15386,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: parif_def_lkup_arec_ptr.egr_0 */
+ /* class_tid: 4, , table: parif_def_lkup_arec_ptr.egr_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -12833,7 +15396,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */
+ /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -12843,7 +15406,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */
+ /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -12853,7 +15416,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 4, , table: int_full_act_record.loopback */
+ /* class_tid: 5, , table: int_full_act_record.loopback */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -13013,7 +15576,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
{
.description = "l2_cntxt_id",
.field_bit_size = 10,
@@ -13102,7 +15665,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -13136,7 +15699,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: parif_def_lkup_arec_ptr.vf_egr */
+ /* class_tid: 5, , table: parif_def_lkup_arec_ptr.vf_egr */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -13146,7 +15709,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
- /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */
+ /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -13156,7 +15719,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
- /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */
+ /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -13166,7 +15729,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
- /* class_tid: 4, , table: int_full_act_record.vf_ing */
+ /* class_tid: 5, , table: int_full_act_record.vf_ing */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -13326,7 +15889,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vf_ing */
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vf_ing */
{
.description = "act_record_ptr",
.field_bit_size = 16,
@@ -13412,7 +15975,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_egr0 */
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_egr0 */
{
.description = "act_record_ptr",
.field_bit_size = 16,
@@ -13497,7 +16060,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
{
.description = "rid",
.field_bit_size = 32,
@@ -13528,7 +16091,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: int_vtag_encap_record.vfr_egr0 */
+ /* class_tid: 5, , table: int_vtag_encap_record.vfr_egr0 */
{
.description = "ecv_tun_type",
.field_bit_size = 3,
@@ -13611,7 +16174,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: int_full_act_record.vfr_egr0 */
+ /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -13774,7 +16337,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: int_full_act_record.vfr_ing0 */
+ /* class_tid: 5, , table: int_full_act_record.vfr_ing0 */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -13936,7 +16499,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */
{
.description = "act_record_ptr",
.field_bit_size = 16,
@@ -14022,7 +16585,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */
{
.description = "act_record_ptr",
.field_bit_size = 16,
@@ -14180,13 +16743,22 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 8,
.ident_bit_pos = 28
},
- /* class_tid: 2, , table: l2_cntxt_tcam_cache.rd */
+ /* class_tid: 2, , table: tunnel_cache.rd */
{
.description = "l2_cntxt_id",
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 42
},
+ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
+ {
+ .description = "l2_cntxt_id",
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 0
+ },
/* class_tid: 2, , table: mac_addr_cache.rd */
{
.description = "l2_cntxt_id",
@@ -14194,7 +16766,40 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 42
},
- /* class_tid: 2, , table: l2_cntxt_tcam.0 */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
+ {
+ .description = "em_profile_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 42
+ },
+ {
+ .description = "flow_sig_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .ident_bit_size = 64,
+ .ident_bit_pos = 58
+ },
+ {
+ .description = "profile_tcam_index",
+ .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ {
+ .description = "l2_cntxt_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 42
+ },
+ /* class_tid: 3, , table: mac_addr_cache.rd */
+ {
+ .description = "l2_cntxt_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 42
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam.0 */
{
.description = "l2_cntxt_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -14203,7 +16808,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 0
},
- /* class_tid: 2, , table: profile_tcam_cache.rd */
+ /* class_tid: 3, , table: profile_tcam_cache.rd */
{
.description = "em_profile_id",
.regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
@@ -14222,7 +16827,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 32
},
- /* class_tid: 2, , table: profile_tcam.ipv4 */
+ /* class_tid: 3, , table: profile_tcam.ipv4 */
{
.description = "em_profile_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -14231,7 +16836,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 8,
.ident_bit_pos = 28
},
- /* class_tid: 2, , table: profile_tcam.ipv6 */
+ /* class_tid: 3, , table: profile_tcam.ipv6 */
{
.description = "em_profile_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -14240,7 +16845,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 8,
.ident_bit_pos = 28
},
- /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
.description = "l2_cntxt_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -14249,7 +16854,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 0
},
- /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
.description = "l2_cntxt_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -14258,7 +16863,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 0
},
- /* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
{
.description = "l2_cntxt_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
index 22c51976ac..d6b4f93d31 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
@@ -413,11 +413,13 @@ static int ulp_get_single_flow_stat(struct bnxt_ulp_context *ctxt,
}
/* Update the parent counters if it is child flow */
- if (sw_acc_tbl_entry->parent_flow_id) {
+ if (sw_acc_tbl_entry->pc_flow_idx & FLOW_CNTR_PC_FLOW_VALID) {
+ uint32_t pc_idx;
+
/* Update the parent counters */
t_sw = sw_acc_tbl_entry;
- if (ulp_flow_db_parent_flow_count_update(ctxt,
- t_sw->parent_flow_id,
+ pc_idx = t_sw->pc_flow_idx & ~FLOW_CNTR_PC_FLOW_VALID;
+ if (ulp_flow_db_parent_flow_count_update(ctxt, pc_idx,
t_sw->pkt_count,
t_sw->byte_count)) {
PMD_DRV_LOG(ERR, "Error updating parent counters\n");
@@ -658,6 +660,7 @@ int32_t ulp_fc_mgr_cntr_reset(struct bnxt_ulp_context *ctxt, enum tf_dir dir,
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].hw_cntr_id = 0;
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].pkt_count = 0;
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].byte_count = 0;
+ ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].pc_flow_idx = 0;
ulp_fc_info->num_entries--;
pthread_mutex_unlock(&ulp_fc_info->fc_lock);
@@ -688,6 +691,8 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
uint32_t hw_cntr_id = 0, sw_cntr_idx = 0;
struct sw_acc_counter *sw_acc_tbl_entry;
bool found_cntr_resource = false;
+ bool found_parent_flow = false;
+ uint32_t pc_idx = 0;
ulp_fc_info = bnxt_ulp_cntxt_ptr2_fc_info_get(ctxt);
if (!ulp_fc_info)
@@ -707,12 +712,16 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
(params.resource_sub_type ==
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT ||
params.resource_sub_type ==
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_EXT_COUNT ||
- params.resource_sub_type ==
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC)) {
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_EXT_COUNT)) {
found_cntr_resource = true;
break;
}
+ if (params.resource_func ==
+ BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW) {
+ found_parent_flow = true;
+ pc_idx = params.resource_hndl;
+ }
+
} while (!rc && nxt_resource_index);
bnxt_ulp_cntxt_release_fdb_lock(ctxt);
@@ -722,7 +731,8 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
dir = params.direction;
hw_cntr_id = params.resource_hndl;
- if (params.resource_sub_type ==
+ if (!found_parent_flow &&
+ params.resource_sub_type ==
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT) {
if (!ulp_fc_info->num_counters)
return ulp_fc_tf_flow_stat_get(ctxt, ¶ms, count);
@@ -745,14 +755,17 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
sw_acc_tbl_entry->byte_count = 0;
}
pthread_mutex_unlock(&ulp_fc_info->fc_lock);
- } else if (params.resource_sub_type ==
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC) {
+ } else if (found_parent_flow &&
+ params.resource_sub_type ==
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT) {
/* Get stats from the parent child table */
- ulp_flow_db_parent_flow_count_get(ctxt, flow_id,
+ ulp_flow_db_parent_flow_count_get(ctxt, pc_idx,
&count->hits, &count->bytes,
count->reset);
- count->hits_set = 1;
- count->bytes_set = 1;
+ if (count->hits)
+ count->hits_set = 1;
+ if (count->bytes)
+ count->bytes_set = 1;
} else {
/* TBD: Handle External counters */
rc = -EINVAL;
@@ -770,13 +783,13 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
*
* hw_cntr_id [in] The HW flow counter ID
*
- * fid [in] parent flow id
+ * pc_idx [in] parent child db index
*
*/
int32_t ulp_fc_mgr_cntr_parent_flow_set(struct bnxt_ulp_context *ctxt,
enum tf_dir dir,
uint32_t hw_cntr_id,
- uint32_t fid)
+ uint32_t pc_idx)
{
struct bnxt_ulp_fc_info *ulp_fc_info;
uint32_t sw_cntr_idx;
@@ -789,10 +802,11 @@ int32_t ulp_fc_mgr_cntr_parent_flow_set(struct bnxt_ulp_context *ctxt,
pthread_mutex_lock(&ulp_fc_info->fc_lock);
sw_cntr_idx = hw_cntr_id - ulp_fc_info->shadow_hw_tbl[dir].start_idx;
if (ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].valid) {
- ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].parent_flow_id = fid;
+ pc_idx |= FLOW_CNTR_PC_FLOW_VALID;
+ ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].pc_flow_idx = pc_idx;
} else {
BNXT_TF_DBG(ERR, "Failed to set parent flow id %x:%x\n",
- hw_cntr_id, fid);
+ hw_cntr_id, pc_idx);
rc = -ENOENT;
}
pthread_mutex_unlock(&ulp_fc_info->fc_lock);
diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
index 448d05c118..9825ed2a27 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
@@ -21,12 +21,14 @@
#define FLOW_CNTR_BYTES(v, d) (((v) & (d)->byte_count_mask) >> \
(d)->byte_count_shift)
+#define FLOW_CNTR_PC_FLOW_VALID 0x1000000
+
struct sw_acc_counter {
uint64_t pkt_count;
uint64_t byte_count;
bool valid;
uint32_t hw_cntr_id;
- uint32_t parent_flow_id;
+ uint32_t pc_flow_idx;
};
struct hw_fc_mem_info {
@@ -175,12 +177,12 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ulp_ctx,
*
* hw_cntr_id [in] The HW flow counter ID
*
- * fid [in] parent flow id
+ * pc_idx [in] parent child db index
*
*/
int32_t ulp_fc_mgr_cntr_parent_flow_set(struct bnxt_ulp_context *ctxt,
enum tf_dir dir,
uint32_t hw_cntr_id,
- uint32_t fid);
+ uint32_t pc_idx);
#endif /* _ULP_FC_MGR_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
index 747a360aa0..039c9c2a6b 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
@@ -386,101 +386,6 @@ ulp_flow_db_parent_tbl_deinit(struct bnxt_ulp_flow_db *flow_db)
}
}
-/* internal validation function for parent flow tbl */
-static struct bnxt_ulp_flow_db *
-ulp_flow_db_parent_arg_validation(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t fid)
-{
- struct bnxt_ulp_flow_db *flow_db;
-
- flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
- if (!flow_db) {
- BNXT_TF_DBG(ERR, "Invalid Arguments\n");
- return NULL;
- }
-
- /* check for max flows */
- if (fid >= flow_db->flow_tbl.num_flows || !fid) {
- BNXT_TF_DBG(ERR, "Invalid flow index\n");
- return NULL;
- }
-
- /* No support for parent child db then just exit */
- if (!flow_db->parent_child_db.entries_count) {
- BNXT_TF_DBG(ERR, "parent child db not supported\n");
- return NULL;
- }
-
- return flow_db;
-}
-
-/*
- * Set the tunnel index in the parent flow
- *
- * ulp_ctxt [in] Ptr to ulp_context
- * parent_idx [in] The parent index of the parent flow entry
- *
- * returns index on success and negative on failure.
- */
-static int32_t
-ulp_flow_db_parent_tun_idx_set(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_idx, uint8_t tun_idx)
-{
- struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
-
- flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
- if (!flow_db) {
- BNXT_TF_DBG(ERR, "Invalid Arguments\n");
- return -EINVAL;
- }
-
- /* check for parent idx validity */
- p_pdb = &flow_db->parent_child_db;
- if (parent_idx >= p_pdb->entries_count ||
- !p_pdb->parent_flow_tbl[parent_idx].parent_fid) {
- BNXT_TF_DBG(ERR, "Invalid parent flow index %x\n", parent_idx);
- return -EINVAL;
- }
-
- p_pdb->parent_flow_tbl[parent_idx].tun_idx = tun_idx;
- return 0;
-}
-
-/*
- * Get the tunnel index from the parent flow
- *
- * ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
- *
- * returns 0 if counter accum is set else -1.
- */
-static int32_t
-ulp_flow_db_parent_tun_idx_get(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid, uint8_t *tun_idx)
-{
- struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
- uint32_t idx;
-
- /* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
- if (!flow_db) {
- BNXT_TF_DBG(ERR, "parent child db validation failed\n");
- return -EINVAL;
- }
-
- p_pdb = &flow_db->parent_child_db;
- for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
- *tun_idx = p_pdb->parent_flow_tbl[idx].tun_idx;
- return 0;
- }
- }
-
- return -EINVAL;
-}
-
/*
* Initialize the flow database. Memory is allocated in this
* call and assigned to the flow database.
@@ -783,9 +688,6 @@ ulp_flow_db_resource_del(struct bnxt_ulp_context *ulp_ctxt,
struct bnxt_ulp_flow_tbl *flow_tbl;
struct ulp_fdb_resource_info *nxt_resource, *fid_resource;
uint32_t nxt_idx = 0;
- struct bnxt_tun_cache_entry *tun_tbl;
- uint8_t tun_idx = 0;
- int rc;
flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
if (!flow_db) {
@@ -862,18 +764,6 @@ ulp_flow_db_resource_del(struct bnxt_ulp_context *ulp_ctxt,
params->resource_hndl);
}
- if (params->resource_func == BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW) {
- tun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(ulp_ctxt);
- if (!tun_tbl)
- return -EINVAL;
-
- rc = ulp_flow_db_parent_tun_idx_get(ulp_ctxt, fid, &tun_idx);
- if (rc)
- return rc;
-
- ulp_clear_tun_entry(tun_tbl, tun_idx);
- }
-
/* all good, return success */
return 0;
}
@@ -892,7 +782,6 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt,
enum bnxt_ulp_fdb_type flow_type,
uint32_t fid)
{
- struct bnxt_tun_cache_entry *tun_tbl;
struct bnxt_ulp_flow_tbl *flow_tbl;
struct bnxt_ulp_flow_db *flow_db;
@@ -934,12 +823,6 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt,
if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR)
ulp_flow_db_func_id_set(flow_db, fid, 0);
- tun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(ulp_ctxt);
- if (!tun_tbl)
- return -EINVAL;
-
- ulp_clear_tun_inner_entry(tun_tbl, fid);
-
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
BNXT_TF_DBG(ERR, "flow_id = %u:%u freed\n", flow_type, fid);
#endif
@@ -1307,24 +1190,84 @@ ulp_default_flow_db_cfa_action_get(struct bnxt_ulp_context *ulp_ctx,
return 0;
}
+/* internal validation function for parent flow tbl */
+static struct ulp_fdb_parent_info *
+ulp_flow_db_pc_db_entry_get(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t pc_idx)
+{
+ struct bnxt_ulp_flow_db *flow_db;
+
+ flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
+ if (!flow_db) {
+ BNXT_TF_DBG(ERR, "Invalid Arguments\n");
+ return NULL;
+ }
+
+ /* check for max flows */
+ if (pc_idx >= BNXT_ULP_MAX_TUN_CACHE_ENTRIES) {
+ BNXT_TF_DBG(ERR, "Invalid tunnel index\n");
+ return NULL;
+ }
+
+ /* No support for parent child db then just exit */
+ if (!flow_db->parent_child_db.entries_count) {
+ BNXT_TF_DBG(ERR, "parent child db not supported\n");
+ return NULL;
+ }
+ if (!flow_db->parent_child_db.parent_flow_tbl[pc_idx].valid) {
+ BNXT_TF_DBG(ERR, "Not a valid tunnel index\n");
+ return NULL;
+ }
+
+ return &flow_db->parent_child_db.parent_flow_tbl[pc_idx];
+}
+
+/* internal validation function for parent flow tbl */
+static struct bnxt_ulp_flow_db *
+ulp_flow_db_parent_arg_validation(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t tun_idx)
+{
+ struct bnxt_ulp_flow_db *flow_db;
+
+ flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
+ if (!flow_db) {
+ BNXT_TF_DBG(ERR, "Invalid Arguments\n");
+ return NULL;
+ }
+
+ /* check for max flows */
+ if (tun_idx >= BNXT_ULP_MAX_TUN_CACHE_ENTRIES) {
+ BNXT_TF_DBG(ERR, "Invalid tunnel index\n");
+ return NULL;
+ }
+
+ /* No support for parent child db then just exit */
+ if (!flow_db->parent_child_db.entries_count) {
+ BNXT_TF_DBG(ERR, "parent child db not supported\n");
+ return NULL;
+ }
+
+ return flow_db;
+}
+
/*
* Allocate the entry in the parent-child database
*
* ulp_ctxt [in] Ptr to ulp_context
- * fid [in] The flow id to the flow entry
+ * tun_idx [in] The tunnel index of the flow entry
*
* returns index on success and negative on failure.
*/
-int32_t
-ulp_flow_db_parent_flow_alloc(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t fid)
+static int32_t
+ulp_flow_db_pc_db_idx_alloc(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t tun_idx)
{
struct bnxt_ulp_flow_db *flow_db;
struct ulp_fdb_parent_child_db *p_pdb;
uint32_t idx, free_idx = 0;
/* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, fid);
+ flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, tun_idx);
if (!flow_db) {
BNXT_TF_DBG(ERR, "parent child db validation failed\n");
return -EINVAL;
@@ -1332,11 +1275,11 @@ ulp_flow_db_parent_flow_alloc(struct bnxt_ulp_context *ulp_ctxt,
p_pdb = &flow_db->parent_child_db;
for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == fid) {
- BNXT_TF_DBG(ERR, "fid is already allocated\n");
- return -EINVAL;
+ if (p_pdb->parent_flow_tbl[idx].valid &&
+ p_pdb->parent_flow_tbl[idx].tun_idx == tun_idx) {
+ return idx;
}
- if (!p_pdb->parent_flow_tbl[idx].parent_fid && !free_idx)
+ if (!p_pdb->parent_flow_tbl[idx].valid && !free_idx)
free_idx = idx + 1;
}
/* no free slots */
@@ -1347,132 +1290,148 @@ ulp_flow_db_parent_flow_alloc(struct bnxt_ulp_context *ulp_ctxt,
free_idx -= 1;
/* set the Fid in the parent child */
- p_pdb->parent_flow_tbl[free_idx].parent_fid = fid;
+ p_pdb->parent_flow_tbl[free_idx].tun_idx = tun_idx;
+ p_pdb->parent_flow_tbl[free_idx].valid = 1;
return free_idx;
}
/*
* Free the entry in the parent-child database
*
- * ulp_ctxt [in] Ptr to ulp_context
- * fid [in] The flow id to the flow entry
+ * pc_entry [in] Ptr to parent child db entry
*
- * returns 0 on success and negative on failure.
+ * returns none.
*/
-int32_t
-ulp_flow_db_parent_flow_free(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t fid)
+static void
+ulp_flow_db_pc_db_entry_free(struct bnxt_ulp_context *ulp_ctxt,
+ struct ulp_fdb_parent_info *pc_entry)
{
+ struct bnxt_tun_cache_entry *tun_tbl;
struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
- uint32_t idx;
+ uint64_t *tmp_bitset;
- /* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, fid);
- if (!flow_db) {
- BNXT_TF_DBG(ERR, "parent child db validation failed\n");
- return -EINVAL;
- }
+ /* free the tunnel entry */
+ tun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(ulp_ctxt);
+ if (tun_tbl)
+ ulp_tunnel_offload_entry_clear(tun_tbl, pc_entry->tun_idx);
- p_pdb = &flow_db->parent_child_db;
- for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == fid) {
- /* free the contents */
- p_pdb->parent_flow_tbl[idx].parent_fid = 0;
- memset(p_pdb->parent_flow_tbl[idx].child_fid_bitset,
- 0, p_pdb->child_bitset_size);
- return 0;
- }
- }
- BNXT_TF_DBG(ERR, "parent entry not found = %x\n", fid);
- return -EINVAL;
+ /* free the child bitset*/
+ flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
+ if (flow_db)
+ memset(pc_entry->child_fid_bitset, 0,
+ flow_db->parent_child_db.child_bitset_size);
+
+ /* free the contents */
+ tmp_bitset = pc_entry->child_fid_bitset;
+ memset(pc_entry, 0, sizeof(struct ulp_fdb_parent_info));
+ pc_entry->child_fid_bitset = tmp_bitset;
}
/*
- * Set or reset the child flow in the parent-child database
+ * Set or reset the parent flow in the parent-child database
*
* ulp_ctxt [in] Ptr to ulp_context
+ * pc_idx [in] The index to parent child db
* parent_fid [in] The flow id of the parent flow entry
- * child_fid [in] The flow id of the child flow entry
* set_flag [in] Use 1 for setting child, 0 to reset
*
* returns zero on success and negative on failure.
*/
int32_t
-ulp_flow_db_parent_child_flow_set(struct bnxt_ulp_context *ulp_ctxt,
+ulp_flow_db_pc_db_parent_flow_set(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t pc_idx,
uint32_t parent_fid,
- uint32_t child_fid,
uint32_t set_flag)
{
+ struct ulp_fdb_parent_info *pc_entry;
struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
- uint32_t idx, a_idx;
- uint64_t *t;
- /* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
+ flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
if (!flow_db) {
BNXT_TF_DBG(ERR, "parent child db validation failed\n");
return -EINVAL;
}
/* check for fid validity */
- if (child_fid >= flow_db->flow_tbl.num_flows || !child_fid) {
- BNXT_TF_DBG(ERR, "Invalid child flow index %x\n", child_fid);
+ if (parent_fid >= flow_db->flow_tbl.num_flows || !parent_fid) {
+ BNXT_TF_DBG(ERR, "Invalid parent flow index %x\n", parent_fid);
return -EINVAL;
}
- p_pdb = &flow_db->parent_child_db;
- a_idx = child_fid / ULP_INDEX_BITMAP_SIZE;
- for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
- t = p_pdb->parent_flow_tbl[idx].child_fid_bitset;
- if (set_flag)
- ULP_INDEX_BITMAP_SET(t[a_idx], child_fid);
- else
- ULP_INDEX_BITMAP_RESET(t[a_idx], child_fid);
- return 0;
- }
+ /* validate the arguments and parent child entry */
+ pc_entry = ulp_flow_db_pc_db_entry_get(ulp_ctxt, pc_idx);
+ if (!pc_entry) {
+ BNXT_TF_DBG(ERR, "failed to get the parent child entry\n");
+ return -EINVAL;
}
- BNXT_TF_DBG(ERR, "Unable to set the parent-child flow %x:%x\n",
- parent_fid, child_fid);
- return -1;
+
+ if (set_flag) {
+ pc_entry->parent_fid = parent_fid;
+ } else {
+ if (pc_entry->parent_fid != parent_fid)
+ BNXT_TF_DBG(ERR, "Panic: invalid parent id\n");
+ pc_entry->parent_fid = 0;
+
+ /* Free the parent child db entry if no user present */
+ if (!pc_entry->f2_cnt)
+ ulp_flow_db_pc_db_entry_free(ulp_ctxt, pc_entry);
+ }
+ return 0;
}
/*
- * Get the parent index from the parent-child database
+ * Set or reset the child flow in the parent-child database
*
* ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
- * parent_idx [out] The parent index of parent flow entry
+ * pc_idx [in] The index to parent child db
+ * child_fid [in] The flow id of the child flow entry
+ * set_flag [in] Use 1 for setting child, 0 to reset
*
* returns zero on success and negative on failure.
*/
int32_t
-ulp_flow_db_parent_flow_idx_get(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid,
- uint32_t *parent_idx)
+ulp_flow_db_pc_db_child_flow_set(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t pc_idx,
+ uint32_t child_fid,
+ uint32_t set_flag)
{
+ struct ulp_fdb_parent_info *pc_entry;
struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
- uint32_t idx;
+ uint32_t a_idx;
+ uint64_t *t;
- /* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
+ flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
if (!flow_db) {
BNXT_TF_DBG(ERR, "parent child db validation failed\n");
return -EINVAL;
}
- p_pdb = &flow_db->parent_child_db;
- for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
- *parent_idx = idx;
- return 0;
- }
+ /* check for fid validity */
+ if (child_fid >= flow_db->flow_tbl.num_flows || !child_fid) {
+ BNXT_TF_DBG(ERR, "Invalid child flow index %x\n", child_fid);
+ return -EINVAL;
}
- BNXT_TF_DBG(ERR, "Unable to get the parent flow %x\n", parent_fid);
- return -1;
+
+ /* validate the arguments and parent child entry */
+ pc_entry = ulp_flow_db_pc_db_entry_get(ulp_ctxt, pc_idx);
+ if (!pc_entry) {
+ BNXT_TF_DBG(ERR, "failed to get the parent child entry\n");
+ return -EINVAL;
+ }
+
+ a_idx = child_fid / ULP_INDEX_BITMAP_SIZE;
+ t = pc_entry->child_fid_bitset;
+ if (set_flag) {
+ ULP_INDEX_BITMAP_SET(t[a_idx], child_fid);
+ pc_entry->f2_cnt++;
+ } else {
+ ULP_INDEX_BITMAP_RESET(t[a_idx], child_fid);
+ if (pc_entry->f2_cnt)
+ pc_entry->f2_cnt--;
+ if (!pc_entry->f2_cnt && !pc_entry->parent_fid)
+ ulp_flow_db_pc_db_entry_free(ulp_ctxt, pc_entry);
+ }
+ return 0;
}
/*
@@ -1541,13 +1500,13 @@ ulp_flow_db_parent_child_flow_next_entry_get(struct bnxt_ulp_flow_db *flow_db,
* Set the counter accumulation in the parent flow
*
* ulp_ctxt [in] Ptr to ulp_context
- * parent_idx [in] The parent index of the parent flow entry
+ * pc_idx [in] The parent child index of the parent flow entry
*
* returns index on success and negative on failure.
*/
static int32_t
ulp_flow_db_parent_flow_count_accum_set(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_idx)
+ uint32_t pc_idx)
{
struct bnxt_ulp_flow_db *flow_db;
struct ulp_fdb_parent_child_db *p_pdb;
@@ -1560,50 +1519,16 @@ ulp_flow_db_parent_flow_count_accum_set(struct bnxt_ulp_context *ulp_ctxt,
/* check for parent idx validity */
p_pdb = &flow_db->parent_child_db;
- if (parent_idx >= p_pdb->entries_count ||
- !p_pdb->parent_flow_tbl[parent_idx].parent_fid) {
- BNXT_TF_DBG(ERR, "Invalid parent flow index %x\n", parent_idx);
+ if (pc_idx >= p_pdb->entries_count ||
+ !p_pdb->parent_flow_tbl[pc_idx].parent_fid) {
+ BNXT_TF_DBG(ERR, "Invalid parent child index %x\n", pc_idx);
return -EINVAL;
}
- p_pdb->parent_flow_tbl[parent_idx].counter_acc = 1;
+ p_pdb->parent_flow_tbl[pc_idx].counter_acc = 1;
return 0;
}
-/*
- * Get the counter accumulation in the parent flow
- *
- * ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
- *
- * returns 0 if counter accum is set else -1.
- */
-static int32_t
-ulp_flow_db_parent_flow_count_accum_get(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid)
-{
- struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
- uint32_t idx;
-
- /* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
- if (!flow_db) {
- BNXT_TF_DBG(ERR, "parent child db validation failed\n");
- return -EINVAL;
- }
-
- p_pdb = &flow_db->parent_child_db;
- for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
- if (p_pdb->parent_flow_tbl[idx].counter_acc)
- return 0;
- break;
- }
- }
- return -1;
-}
-
/*
* Orphan the child flow entry
* This is called only for child flows that have
@@ -1677,22 +1602,30 @@ int32_t
ulp_flow_db_parent_flow_create(struct bnxt_ulp_mapper_parms *parms)
{
struct ulp_flow_db_res_params fid_parms;
- uint32_t sub_typ = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC;
+ uint32_t sub_typ = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT;
struct ulp_flow_db_res_params res_params;
- int32_t fid_idx, rc;
+ int32_t pc_idx;
- /* create the child flow entry in parent flow table */
- fid_idx = ulp_flow_db_parent_flow_alloc(parms->ulp_ctx, parms->fid);
- if (fid_idx < 0) {
- BNXT_TF_DBG(ERR, "Error in creating parent flow fid %x\n",
- parms->fid);
- return -1;
+ /* create or get the parent child database */
+ pc_idx = ulp_flow_db_pc_db_idx_alloc(parms->ulp_ctx, parms->tun_idx);
+ if (pc_idx < 0) {
+ BNXT_TF_DBG(ERR, "Error in getting parent child db %x\n",
+ parms->tun_idx);
+ return -EINVAL;
+ }
+
+ /* Update the parent fid */
+ if (ulp_flow_db_pc_db_parent_flow_set(parms->ulp_ctx, pc_idx,
+ parms->fid, 1)) {
+ BNXT_TF_DBG(ERR, "Error in setting parent fid %x\n",
+ parms->tun_idx);
+ return -EINVAL;
}
/* Add the parent details in the resource list of the flow */
memset(&fid_parms, 0, sizeof(fid_parms));
fid_parms.resource_func = BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW;
- fid_parms.resource_hndl = fid_idx;
+ fid_parms.resource_hndl = pc_idx;
fid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO;
if (ulp_flow_db_resource_add(parms->ulp_ctx, BNXT_ULP_FDB_TYPE_REGULAR,
parms->fid, &fid_parms)) {
@@ -1710,20 +1643,13 @@ ulp_flow_db_parent_flow_create(struct bnxt_ulp_mapper_parms *parms)
&res_params)) {
/* Enable the counter accumulation in parent entry */
if (ulp_flow_db_parent_flow_count_accum_set(parms->ulp_ctx,
- fid_idx)) {
+ pc_idx)) {
BNXT_TF_DBG(ERR, "Error in setting counter acc %x\n",
parms->fid);
return -1;
}
}
- rc = ulp_flow_db_parent_tun_idx_set(parms->ulp_ctx, fid_idx,
- parms->tun_idx);
- if (rc) {
- BNXT_TF_DBG(ERR, "Error setting tun_idx in the parent flow\n");
- return rc;
- }
-
return 0;
}
@@ -1741,13 +1667,19 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
uint32_t sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT;
enum bnxt_ulp_resource_func res_fun;
struct ulp_flow_db_res_params res_p;
- uint32_t parent_fid = parms->parent_fid;
- int32_t rc;
+ int32_t rc, pc_idx;
+
+ /* create or get the parent child database */
+ pc_idx = ulp_flow_db_pc_db_idx_alloc(parms->ulp_ctx, parms->tun_idx);
+ if (pc_idx < 0) {
+ BNXT_TF_DBG(ERR, "Error in getting parent child db %x\n",
+ parms->tun_idx);
+ return -1;
+ }
/* create the parent flow entry in parent flow table */
- rc = ulp_flow_db_parent_child_flow_set(parms->ulp_ctx,
- parms->parent_fid,
- parms->fid, 1);
+ rc = ulp_flow_db_pc_db_child_flow_set(parms->ulp_ctx, pc_idx,
+ parms->fid, 1);
if (rc) {
BNXT_TF_DBG(ERR, "Error in setting child fid %x\n", parms->fid);
return rc;
@@ -1756,7 +1688,7 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
/* Add the parent details in the resource list of the flow */
memset(&fid_parms, 0, sizeof(fid_parms));
fid_parms.resource_func = BNXT_ULP_RESOURCE_FUNC_CHILD_FLOW;
- fid_parms.resource_hndl = parms->parent_fid;
+ fid_parms.resource_hndl = pc_idx;
fid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO;
rc = ulp_flow_db_resource_add(parms->ulp_ctx,
BNXT_ULP_FDB_TYPE_REGULAR,
@@ -1767,30 +1699,26 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
return rc;
}
- /* check if accumulation count is set for parent flow */
- rc = ulp_flow_db_parent_flow_count_accum_get(parms->ulp_ctx,
- parms->parent_fid);
+ /* check if internal count action included for this flow.*/
+ res_fun = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE;
+ rc = ulp_flow_db_resource_params_get(parms->ulp_ctx,
+ BNXT_ULP_FDB_TYPE_REGULAR,
+ parms->fid,
+ res_fun,
+ sub_type,
+ &res_p);
if (!rc) {
- /* check if internal count action included for this flow.*/
- res_fun = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE;
- rc = ulp_flow_db_resource_params_get(parms->ulp_ctx,
- BNXT_ULP_FDB_TYPE_REGULAR,
- parms->fid,
- res_fun,
- sub_type,
- &res_p);
- if (!rc) {
- /* update the counter manager to include parent fid */
- if (ulp_fc_mgr_cntr_parent_flow_set(parms->ulp_ctx,
- res_p.direction,
- res_p.resource_hndl,
- parent_fid)) {
- BNXT_TF_DBG(ERR, "Error in setting child %x\n",
- parms->fid);
- return -1;
- }
+ /* update the counter manager to include parent fid */
+ if (ulp_fc_mgr_cntr_parent_flow_set(parms->ulp_ctx,
+ res_p.direction,
+ res_p.resource_hndl,
+ pc_idx)) {
+ BNXT_TF_DBG(ERR, "Error in setting child %x\n",
+ parms->fid);
+ return -1;
}
}
+
/* return success */
return 0;
}
@@ -1799,7 +1727,7 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
* Update the parent counters
*
* ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
+ * pc_idx [in] The parent flow entry idx
* packet_count [in] - packet count
* byte_count [in] - byte count
*
@@ -1807,41 +1735,31 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
*/
int32_t
ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid,
+ uint32_t pc_idx,
uint64_t packet_count,
uint64_t byte_count)
{
- struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
- uint32_t idx;
+ struct ulp_fdb_parent_info *pc_entry;
- /* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
- if (!flow_db) {
- BNXT_TF_DBG(ERR, "parent child db validation failed\n");
+ /* validate the arguments and get parent child entry */
+ pc_entry = ulp_flow_db_pc_db_entry_get(ulp_ctxt, pc_idx);
+ if (!pc_entry) {
+ BNXT_TF_DBG(ERR, "failed to get the parent child entry\n");
return -EINVAL;
}
- p_pdb = &flow_db->parent_child_db;
- for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
- if (p_pdb->parent_flow_tbl[idx].counter_acc) {
- p_pdb->parent_flow_tbl[idx].pkt_count +=
- packet_count;
- p_pdb->parent_flow_tbl[idx].byte_count +=
- byte_count;
- }
- return 0;
- }
+ if (pc_entry->counter_acc) {
+ pc_entry->pkt_count += packet_count;
+ pc_entry->byte_count += byte_count;
}
- return -ENOENT;
+ return 0;
}
/*
* Get the parent accumulation counters
*
* ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
+ * pc_idx [in] The parent flow entry idx
* packet_count [out] - packet count
* byte_count [out] - byte count
*
@@ -1849,37 +1767,27 @@ ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt,
*/
int32_t
ulp_flow_db_parent_flow_count_get(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid, uint64_t *packet_count,
+ uint32_t pc_idx, uint64_t *packet_count,
uint64_t *byte_count, uint8_t count_reset)
{
- struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
- uint32_t idx;
+ struct ulp_fdb_parent_info *pc_entry;
- /* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
- if (!flow_db) {
- BNXT_TF_DBG(ERR, "parent child db validation failed\n");
+ /* validate the arguments and get parent child entry */
+ pc_entry = ulp_flow_db_pc_db_entry_get(ulp_ctxt, pc_idx);
+ if (!pc_entry) {
+ BNXT_TF_DBG(ERR, "failed to get the parent child entry\n");
return -EINVAL;
}
- p_pdb = &flow_db->parent_child_db;
- for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
- if (p_pdb->parent_flow_tbl[idx].counter_acc) {
- *packet_count =
- p_pdb->parent_flow_tbl[idx].pkt_count;
- *byte_count =
- p_pdb->parent_flow_tbl[idx].byte_count;
- if (count_reset) {
- p_pdb->parent_flow_tbl[idx].pkt_count = 0;
- p_pdb->parent_flow_tbl[idx].byte_count = 0;
- }
- }
- return 0;
+ if (pc_entry->counter_acc) {
+ *packet_count = pc_entry->pkt_count;
+ *byte_count = pc_entry->byte_count;
+ if (count_reset) {
+ pc_entry->pkt_count = 0;
+ pc_entry->byte_count = 0;
}
}
- return -ENOENT;
+ return 0;
}
/*
@@ -1897,7 +1805,7 @@ ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt)
uint32_t idx;
/* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, 1);
+ flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
if (!flow_db) {
BNXT_TF_DBG(ERR, "parent child db validation failed\n");
return;
@@ -1905,7 +1813,7 @@ ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt)
p_pdb = &flow_db->parent_child_db;
for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid &&
+ if (p_pdb->parent_flow_tbl[idx].valid &&
p_pdb->parent_flow_tbl[idx].counter_acc) {
p_pdb->parent_flow_tbl[idx].pkt_count = 0;
p_pdb->parent_flow_tbl[idx].byte_count = 0;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
index 0ddfa6f66d..8680ee8f65 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
@@ -58,6 +58,7 @@ struct bnxt_ulp_flow_tbl {
/* Structure to maintain parent-child flow relationships */
struct ulp_fdb_parent_info {
+ uint32_t valid;
uint32_t parent_fid;
uint32_t counter_acc;
uint64_t pkt_count;
@@ -259,45 +260,38 @@ int32_t
ulp_default_flow_db_cfa_action_get(struct bnxt_ulp_context *ulp_ctx,
uint32_t flow_id,
uint16_t *cfa_action);
-/*
- * Allocate the entry in the parent-child database
- *
- * ulp_ctxt [in] Ptr to ulp_context
- * fid [in] The flow id to the flow entry
- *
- * returns index on success and negative on failure.
- */
-int32_t
-ulp_flow_db_parent_flow_alloc(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t fid);
/*
- * Free the entry in the parent-child database
+ * Set or reset the parent flow in the parent-child database
*
* ulp_ctxt [in] Ptr to ulp_context
- * fid [in] The flow id to the flow entry
+ * pc_idx [in] The index to parent child db
+ * parent_fid [in] The flow id of the parent flow entry
+ * set_flag [in] Use 1 for setting child, 0 to reset
*
- * returns 0 on success and negative on failure.
+ * returns zero on success and negative on failure.
*/
int32_t
-ulp_flow_db_parent_flow_free(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t fid);
+ulp_flow_db_pc_db_parent_flow_set(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t pc_idx,
+ uint32_t parent_fid,
+ uint32_t set_flag);
/*
* Set or reset the child flow in the parent-child database
*
* ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
+ * pc_idx [in] The index to parent child db
* child_fid [in] The flow id of the child flow entry
* set_flag [in] Use 1 for setting child, 0 to reset
*
* returns zero on success and negative on failure.
*/
int32_t
-ulp_flow_db_parent_child_flow_set(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid,
- uint32_t child_fid,
- uint32_t set_flag);
+ulp_flow_db_pc_db_child_flow_set(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t pc_idx,
+ uint32_t child_fid,
+ uint32_t set_flag);
/*
* Get the parent index from the parent-child database
@@ -368,7 +362,7 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms);
* Update the parent counters
*
* ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
+ * pc_idx [in] The parent flow entry idx
* packet_count [in] - packet count
* byte_count [in] - byte count
*
@@ -376,14 +370,14 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms);
*/
int32_t
ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid,
+ uint32_t pc_idx,
uint64_t packet_count,
uint64_t byte_count);
/*
* Get the parent accumulation counters
*
* ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
+ * pc_idx [in] The parent flow entry idx
* packet_count [out] - packet count
* byte_count [out] - byte count
*
@@ -391,7 +385,7 @@ ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt,
*/
int32_t
ulp_flow_db_parent_flow_count_get(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid,
+ uint32_t pc_idx,
uint64_t *packet_count,
uint64_t *byte_count,
uint8_t count_reset);
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 7fc3767b33..6d804c7ef9 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -544,34 +544,14 @@ ulp_mapper_parent_flow_free(struct bnxt_ulp_context *ulp,
uint32_t parent_fid,
struct ulp_flow_db_res_params *res)
{
- uint32_t idx, child_fid = 0, parent_idx;
- struct bnxt_ulp_flow_db *flow_db;
+ uint32_t pc_idx;
- parent_idx = (uint32_t)res->resource_hndl;
+ pc_idx = (uint32_t)res->resource_hndl;
- /* check the validity of the parent fid */
- if (ulp_flow_db_parent_flow_idx_get(ulp, parent_fid, &idx) ||
- idx != parent_idx) {
- BNXT_TF_DBG(ERR, "invalid parent flow id %x\n", parent_fid);
- return -EINVAL;
- }
-
- /* Clear all the child flows parent index */
- flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp);
- while (!ulp_flow_db_parent_child_flow_next_entry_get(flow_db, idx,
- &child_fid)) {
- /* update the child flows resource handle */
- if (ulp_flow_db_child_flow_reset(ulp, BNXT_ULP_FDB_TYPE_REGULAR,
- child_fid)) {
- BNXT_TF_DBG(ERR, "failed to reset child flow %x\n",
- child_fid);
- return -EINVAL;
- }
- }
-
- /* free the parent entry in the parent table flow */
- if (ulp_flow_db_parent_flow_free(ulp, parent_fid)) {
- BNXT_TF_DBG(ERR, "failed to free parent flow %x\n", parent_fid);
+ /* reset the child flow bitset*/
+ if (ulp_flow_db_pc_db_parent_flow_set(ulp, pc_idx, parent_fid, 0)) {
+ BNXT_TF_DBG(ERR, "error in reset parent flow bitset %x:%x\n",
+ pc_idx, parent_fid);
return -EINVAL;
}
return 0;
@@ -582,16 +562,14 @@ ulp_mapper_child_flow_free(struct bnxt_ulp_context *ulp,
uint32_t child_fid,
struct ulp_flow_db_res_params *res)
{
- uint32_t parent_fid;
+ uint32_t pc_idx;
- parent_fid = (uint32_t)res->resource_hndl;
- if (!parent_fid)
- return 0; /* Already freed - orphan child*/
+ pc_idx = (uint32_t)res->resource_hndl;
/* reset the child flow bitset*/
- if (ulp_flow_db_parent_child_flow_set(ulp, parent_fid, child_fid, 0)) {
+ if (ulp_flow_db_pc_db_child_flow_set(ulp, pc_idx, child_fid, 0)) {
BNXT_TF_DBG(ERR, "error in resetting child flow bitset %x:%x\n",
- parent_fid, child_fid);
+ pc_idx, child_fid);
return -EINVAL;
}
return 0;
@@ -1944,6 +1922,12 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
+ /* If only allocation of identifier then perform and exit */
+ if (tbl->tbl_opcode == BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT) {
+ rc = ulp_mapper_tcam_tbl_scan_ident_alloc(parms, tbl);
+ return rc;
+ }
+
kflds = ulp_mapper_key_fields_get(parms, tbl, &num_kflds);
if (!kflds || !num_kflds) {
BNXT_TF_DBG(ERR, "Failed to get key fields\n");
@@ -3889,7 +3873,7 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
parms.class_tid = cparms->class_tid;
parms.flow_type = cparms->flow_type;
parms.parent_flow = cparms->parent_flow;
- parms.parent_fid = cparms->parent_fid;
+ parms.child_flow = cparms->child_flow;
parms.fid = cparms->flow_id;
parms.tun_idx = cparms->tun_idx;
parms.app_priority = cparms->app_priority;
@@ -3954,7 +3938,7 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
rc = ulp_flow_db_parent_flow_create(&parms);
if (rc)
goto flow_error;
- } else if (parms.parent_fid) {
+ } else if (parms.child_flow) {
/* create a child flow details */
rc = ulp_flow_db_child_flow_create(&parms);
if (rc)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
index 004e89ac2b..d4d6969bb5 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
@@ -53,7 +53,7 @@ struct bnxt_ulp_mapper_parms {
enum bnxt_ulp_fdb_type flow_type;
struct bnxt_ulp_mapper_data *mapper_data;
struct bnxt_ulp_device_params *device_params;
- uint32_t parent_fid;
+ uint32_t child_flow;
uint32_t parent_flow;
uint8_t tun_idx;
uint32_t app_priority;
@@ -79,8 +79,8 @@ struct bnxt_ulp_mapper_create_parms {
enum bnxt_ulp_fdb_type flow_type;
uint32_t flow_id;
- /* if set then create it as a child flow with parent as parent_fid */
- uint32_t parent_fid;
+ /* if set then create it as a child flow */
+ uint32_t child_flow;
/* if set then create a parent flow */
uint32_t parent_flow;
uint8_t tun_idx;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
index 35e9858727..9b165c12b5 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
@@ -215,6 +215,21 @@ struct bnxt_ulp_rte_act_info ulp_act_info[] = {
}
};
+struct bnxt_ulp_rte_act_info ulp_vendor_act_info[] = {
+ [BNXT_RTE_FLOW_ACTION_TYPE_END - BNXT_RTE_FLOW_ACTION_TYPE_END] = {
+ .act_type = BNXT_ULP_ACT_TYPE_END,
+ .proto_act_func = NULL
+ },
+ [BNXT_RTE_FLOW_ACTION_TYPE_VXLAN_DECAP - BNXT_RTE_FLOW_ACTION_TYPE_END] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_vendor_vxlan_decap_act_handler
+ },
+ [BNXT_RTE_FLOW_ACTION_TYPE_LAST - BNXT_RTE_FLOW_ACTION_TYPE_END] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ }
+};
+
/*
* This table has to be indexed based on the rte_flow_item_type that is part of
* DPDK. The below array is list of parsing functions for each of the flow items
@@ -414,3 +429,19 @@ struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = {
.proto_hdr_func = NULL
}
};
+
+struct bnxt_ulp_rte_hdr_info ulp_vendor_hdr_info[] = {
+ [BNXT_RTE_FLOW_ITEM_TYPE_END - BNXT_RTE_FLOW_ITEM_TYPE_END] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_END,
+ .proto_hdr_func = NULL
+ },
+ [BNXT_RTE_FLOW_ITEM_TYPE_VXLAN_DECAP - BNXT_RTE_FLOW_ITEM_TYPE_END] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_vendor_vxlan_decap_hdr_handler
+ },
+ [BNXT_RTE_FLOW_ITEM_TYPE_LAST - BNXT_RTE_FLOW_ITEM_TYPE_END] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+
+};
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index 79b9957781..fadcd3873c 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -125,13 +125,21 @@ bnxt_ulp_rte_parser_hdr_parse(const struct rte_flow_item pattern[],
/* Parse all the items in the pattern */
while (item && item->type != RTE_FLOW_ITEM_TYPE_END) {
- /* get the header information from the flow_hdr_info table */
- hdr_info = &ulp_hdr_info[item->type];
+ if (item->type >= (uint32_t)
+ BNXT_RTE_FLOW_ITEM_TYPE_END) {
+ if (item->type >=
+ (uint32_t)BNXT_RTE_FLOW_ITEM_TYPE_LAST)
+ goto hdr_parser_error;
+ /* get the header information */
+ hdr_info = &ulp_vendor_hdr_info[item->type -
+ BNXT_RTE_FLOW_ITEM_TYPE_END];
+ } else {
+ if (item->type > RTE_FLOW_ITEM_TYPE_HIGIG2)
+ goto hdr_parser_error;
+ hdr_info = &ulp_hdr_info[item->type];
+ }
if (hdr_info->hdr_type == BNXT_ULP_HDR_TYPE_NOT_SUPPORTED) {
- BNXT_TF_DBG(ERR,
- "Truflow parser does not support type %d\n",
- item->type);
- return BNXT_TF_RC_PARSE_ERR;
+ goto hdr_parser_error;
} else if (hdr_info->hdr_type == BNXT_ULP_HDR_TYPE_SUPPORTED) {
/* call the registered callback handler */
if (hdr_info->proto_hdr_func) {
@@ -145,6 +153,11 @@ bnxt_ulp_rte_parser_hdr_parse(const struct rte_flow_item pattern[],
}
/* update the implied SVIF */
return ulp_rte_parser_implicit_match_port_process(params);
+
+hdr_parser_error:
+ BNXT_TF_DBG(ERR, "Truflow parser does not support type %d\n",
+ item->type);
+ return BNXT_TF_RC_PARSE_ERR;
}
/*
@@ -160,16 +173,23 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[],
/* Parse all the items in the pattern */
while (action_item && action_item->type != RTE_FLOW_ACTION_TYPE_END) {
- /* get the header information from the flow_hdr_info table */
- hdr_info = &ulp_act_info[action_item->type];
- if (hdr_info->act_type ==
- BNXT_ULP_ACT_TYPE_NOT_SUPPORTED) {
- BNXT_TF_DBG(ERR,
- "Truflow parser does not support act %u\n",
- action_item->type);
- return BNXT_TF_RC_ERROR;
- } else if (hdr_info->act_type ==
- BNXT_ULP_ACT_TYPE_SUPPORTED) {
+ if (action_item->type >=
+ (uint32_t)BNXT_RTE_FLOW_ACTION_TYPE_END) {
+ if (action_item->type >=
+ (uint32_t)BNXT_RTE_FLOW_ACTION_TYPE_LAST)
+ goto act_parser_error;
+ /* get the header information from bnxt actinfo table */
+ hdr_info = &ulp_vendor_act_info[action_item->type -
+ BNXT_RTE_FLOW_ACTION_TYPE_END];
+ } else {
+ if (action_item->type > RTE_FLOW_ACTION_TYPE_SHARED)
+ goto act_parser_error;
+ /* get the header information from the act info table */
+ hdr_info = &ulp_act_info[action_item->type];
+ }
+ if (hdr_info->act_type == BNXT_ULP_ACT_TYPE_NOT_SUPPORTED) {
+ goto act_parser_error;
+ } else if (hdr_info->act_type == BNXT_ULP_ACT_TYPE_SUPPORTED) {
/* call the registered callback handler */
if (hdr_info->proto_act_func) {
if (hdr_info->proto_act_func(action_item,
@@ -184,6 +204,11 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[],
/* update the implied port details */
ulp_rte_parser_implicit_act_port_process(params);
return BNXT_TF_RC_SUCCESS;
+
+act_parser_error:
+ BNXT_TF_DBG(ERR, "Truflow parser does not support act %u\n",
+ action_item->type);
+ return BNXT_TF_RC_ERROR;
}
/*
@@ -325,11 +350,10 @@ ulp_post_process_normal_flow(struct ulp_rte_parser_params *params)
/*
* Function to handle the post processing of the parsing details
*/
-int32_t
+void
bnxt_ulp_rte_parser_post_process(struct ulp_rte_parser_params *params)
{
ulp_post_process_normal_flow(params);
- return ulp_post_process_tun_flow(params);
}
/*
@@ -660,7 +684,7 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item,
{
const struct rte_flow_item_eth *eth_spec = item->spec;
const struct rte_flow_item_eth *eth_mask = item->mask;
- uint32_t idx = 0;
+ uint32_t idx = 0, dmac_idx = 0;
uint32_t size;
uint16_t eth_type = 0;
uint32_t inner_flag = 0;
@@ -686,6 +710,7 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item,
* Copy the rte_flow_item for eth into hdr_field using ethernet
* header fields
*/
+ dmac_idx = idx;
size = sizeof(((struct rte_flow_item_eth *)NULL)->dst.addr_bytes);
ulp_rte_prsr_fld_mask(params, &idx, size,
ulp_deference_struct(eth_spec, dst.addr_bytes),
@@ -719,6 +744,8 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item,
inner_flag = 1;
} else {
ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_ETH);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID,
+ dmac_idx);
}
/* Update the field protocol hdr bitmap */
ulp_rte_l2_proto_type_update(params, eth_type, inner_flag);
@@ -926,7 +953,7 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
const struct rte_flow_item_ipv4 *ipv4_spec = item->spec;
const struct rte_flow_item_ipv4 *ipv4_mask = item->mask;
struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap;
- uint32_t idx = 0;
+ uint32_t idx = 0, dip_idx = 0;
uint32_t size;
uint8_t proto = 0;
uint32_t inner_flag = 0;
@@ -939,22 +966,6 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
return BNXT_TF_RC_ERROR;
}
- if (!ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
- BNXT_ULP_HDR_BIT_O_ETH) &&
- !ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
- BNXT_ULP_HDR_BIT_I_ETH)) {
- /* Since F2 flow does not include eth item, when parser detects
- * IPv4/IPv6 item list and it belongs to the outer header; i.e.,
- * o_ipv4/o_ipv6, check if O_ETH and I_ETH is set. If not set,
- * then add offset sizeof(o_eth/oo_vlan/oi_vlan) to the index.
- * This will allow the parser post processor to update the
- * t_dmac in hdr_field[o_eth.dmac]
- */
- idx += (BNXT_ULP_PROTO_HDR_ETH_NUM +
- BNXT_ULP_PROTO_HDR_VLAN_NUM);
- params->field_idx = idx;
- }
-
if (ulp_rte_prsr_fld_size_validate(params, &idx,
BNXT_ULP_PROTO_HDR_IPV4_NUM)) {
BNXT_TF_DBG(ERR, "Error parsing protocol header\n");
@@ -1033,6 +1044,7 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
ulp_deference_struct(ipv4_mask, hdr.src_addr),
ULP_PRSR_ACT_DEFAULT);
+ dip_idx = idx;
size = sizeof(((struct rte_flow_item_ipv4 *)NULL)->hdr.dst_addr);
ulp_rte_prsr_fld_mask(params, &idx, size,
ulp_deference_struct(ipv4_spec, hdr.dst_addr),
@@ -1048,6 +1060,9 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
} else {
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3, 1);
+ /* Update the tunnel offload dest ip offset */
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID,
+ dip_idx);
}
/* Some of the PMD applications may set the protocol field
@@ -1071,7 +1086,7 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
const struct rte_flow_item_ipv6 *ipv6_spec = item->spec;
const struct rte_flow_item_ipv6 *ipv6_mask = item->mask;
struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap;
- uint32_t idx = 0;
+ uint32_t idx = 0, dip_idx = 0;
uint32_t size;
uint32_t ver_spec = 0, ver_mask = 0;
uint32_t tc_spec = 0, tc_mask = 0;
@@ -1087,22 +1102,6 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
return BNXT_TF_RC_ERROR;
}
- if (!ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
- BNXT_ULP_HDR_BIT_O_ETH) &&
- !ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
- BNXT_ULP_HDR_BIT_I_ETH)) {
- /* Since F2 flow does not include eth item, when parser detects
- * IPv4/IPv6 item list and it belongs to the outer header; i.e.,
- * o_ipv4/o_ipv6, check if O_ETH and I_ETH is set. If not set,
- * then add offset sizeof(o_eth/oo_vlan/oi_vlan) to the index.
- * This will allow the parser post processor to update the
- * t_dmac in hdr_field[o_eth.dmac]
- */
- idx += (BNXT_ULP_PROTO_HDR_ETH_NUM +
- BNXT_ULP_PROTO_HDR_VLAN_NUM);
- params->field_idx = idx;
- }
-
if (ulp_rte_prsr_fld_size_validate(params, &idx,
BNXT_ULP_PROTO_HDR_IPV6_NUM)) {
BNXT_TF_DBG(ERR, "Error parsing protocol header\n");
@@ -1171,6 +1170,7 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
ulp_deference_struct(ipv6_mask, hdr.src_addr),
ULP_PRSR_ACT_DEFAULT);
+ dip_idx = idx;
size = sizeof(((struct rte_flow_item_ipv6 *)NULL)->hdr.dst_addr);
ulp_rte_prsr_fld_mask(params, &idx, size,
ulp_deference_struct(ipv6_spec, hdr.dst_addr),
@@ -1186,6 +1186,9 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
} else {
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3, 1);
+ /* Update the tunnel offload dest ip offset */
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID,
+ dip_idx);
}
/* Update the field protocol hdr bitmap */
@@ -1200,9 +1203,11 @@ static void
ulp_rte_l4_proto_type_update(struct ulp_rte_parser_params *param,
uint16_t dst_port)
{
- if (dst_port == tfp_cpu_to_be_16(ULP_UDP_PORT_VXLAN))
+ if (dst_port == tfp_cpu_to_be_16(ULP_UDP_PORT_VXLAN)) {
ULP_BITMAP_SET(param->hdr_fp_bit.bits,
BNXT_ULP_HDR_BIT_T_VXLAN);
+ ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_L3_TUN, 1);
+ }
if (ULP_BITMAP_ISSET(param->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_T_VXLAN) ||
@@ -2484,3 +2489,24 @@ ulp_rte_sample_act_handler(const struct rte_flow_action *action_item,
return ret;
}
+
+/* Function to handle the parsing of bnxt vendor Flow action vxlan Header. */
+int32_t
+ulp_vendor_vxlan_decap_act_handler(const struct rte_flow_action *action_item,
+ struct ulp_rte_parser_params *params)
+{
+ /* Set the F1 flow header bit */
+ ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F1);
+ return ulp_rte_vxlan_decap_act_handler(action_item, params);
+}
+
+/* Function to handle the parsing of bnxt vendor Flow item vxlan Header. */
+int32_t
+ulp_rte_vendor_vxlan_decap_hdr_handler(const struct rte_flow_item *item,
+ struct ulp_rte_parser_params *params)
+{
+ RTE_SET_USED(item);
+ /* Set the F2 flow header bit */
+ ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F2);
+ return ulp_rte_vxlan_decap_act_handler(NULL, params);
+}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
index 4431f1bbd0..673172c811 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
@@ -75,7 +75,7 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[],
/*
* Function to handle the post processing of the parsing details
*/
-int32_t
+void
bnxt_ulp_rte_parser_post_process(struct ulp_rte_parser_params *params);
/* Function to handle the parsing of RTE Flow item PF Header. */
@@ -270,4 +270,12 @@ int32_t
ulp_rte_shared_act_handler(const struct rte_flow_action *action_item,
struct ulp_rte_parser_params *params);
+int32_t
+ulp_vendor_vxlan_decap_act_handler(const struct rte_flow_action *action_item,
+ struct ulp_rte_parser_params *params);
+
+int32_t
+ulp_rte_vendor_vxlan_decap_hdr_handler(const struct rte_flow_item *item,
+ struct ulp_rte_parser_params *params);
+
#endif /* _ULP_RTE_PARSER_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index 0cbac66237..2685e63432 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -78,17 +78,19 @@ struct ulp_rte_parser_params {
uint32_t priority;
uint32_t fid;
uint32_t parent_flow;
- uint32_t parent_fid;
+ uint32_t child_flow;
uint16_t func_id;
uint16_t port_id;
uint32_t class_id;
uint32_t act_tmpl;
struct bnxt_ulp_context *ulp_ctx;
uint32_t hdr_sig_id;
- uint32_t flow_sig_id;
+ uint64_t flow_sig_id;
uint32_t flow_pattern_id;
uint32_t act_pattern_id;
uint8_t app_id;
+ uint8_t tun_idx;
+
};
/* Flow Parser Header Information Structure */
@@ -101,6 +103,7 @@ struct bnxt_ulp_rte_hdr_info {
/* Flow Parser Header Information Structure Array defined in template source*/
extern struct bnxt_ulp_rte_hdr_info ulp_hdr_info[];
+extern struct bnxt_ulp_rte_hdr_info ulp_vendor_hdr_info[];
/* Flow Parser Action Information Structure */
struct bnxt_ulp_rte_act_info {
@@ -113,6 +116,7 @@ struct bnxt_ulp_rte_act_info {
/* Flow Parser Action Information Structure Array defined in template source*/
extern struct bnxt_ulp_rte_act_info ulp_act_info[];
+extern struct bnxt_ulp_rte_act_info ulp_vendor_act_info[];
/* Flow Matcher structures */
struct bnxt_ulp_header_match_info {
@@ -136,7 +140,7 @@ struct bnxt_ulp_class_match_info {
uint8_t wc_pri;
uint8_t app_sig;
uint32_t hdr_sig_id;
- uint32_t flow_sig_id;
+ uint64_t flow_sig_id;
uint32_t flow_pattern_id;
};
diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.c b/drivers/net/bnxt/tf_ulp/ulp_tun.c
index a1dd5b902c..7ce6740633 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_tun.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_tun.c
@@ -3,225 +3,111 @@
* All rights reserved.
*/
-#include <sys/queue.h>
-
-#include <rte_malloc.h>
-
+#include "bnxt.h"
+#include "bnxt_ulp.h"
#include "ulp_tun.h"
-#include "ulp_rte_parser.h"
-#include "ulp_template_db_enum.h"
-#include "ulp_template_struct.h"
-#include "ulp_matcher.h"
-#include "ulp_mapper.h"
-#include "ulp_flow_db.h"
+#include "ulp_utils.h"
-/* This function programs the outer tunnel flow in the hardware. */
-static int32_t
-ulp_install_outer_tun_flow(struct ulp_rte_parser_params *params,
- struct bnxt_tun_cache_entry *tun_entry,
- uint16_t tun_idx)
+/* returns negative on error, 1 if new entry is allocated or zero if old */
+int32_t
+ulp_app_tun_search_entry(struct bnxt_ulp_context *ulp_ctx,
+ struct rte_flow_tunnel *app_tunnel,
+ struct bnxt_flow_app_tun_ent **tun_entry)
{
- struct bnxt_ulp_mapper_create_parms mparms = { 0 };
- int ret;
-
- /* Reset the JUMP action bit in the action bitmap as we don't
- * offload this action.
- */
- ULP_BITMAP_RESET(params->act_bitmap.bits, BNXT_ULP_ACT_BIT_JUMP);
-
- ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F1);
-
-#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
-#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER
- /* Dump the rte flow pattern */
- ulp_parser_hdr_info_dump(params);
- /* Dump the rte flow action */
- ulp_parser_act_info_dump(params);
-#endif
-#endif
-
- ret = ulp_matcher_pattern_match(params, ¶ms->class_id);
- if (ret != BNXT_TF_RC_SUCCESS)
- goto err;
+ struct bnxt_flow_app_tun_ent *tun_ent_list;
+ int32_t i, rc = 0, free_entry = -1;
- ret = ulp_matcher_action_match(params, ¶ms->act_tmpl);
- if (ret != BNXT_TF_RC_SUCCESS)
- goto err;
-
- params->parent_flow = true;
- bnxt_ulp_init_mapper_params(&mparms, params,
- BNXT_ULP_FDB_TYPE_REGULAR);
- mparms.tun_idx = tun_idx;
-
- /* Call the ulp mapper to create the flow in the hardware. */
- ret = ulp_mapper_flow_create(params->ulp_ctx, &mparms);
- if (ret)
- goto err;
-
- /* Store the tunnel dmac in the tunnel cache table and use it while
- * programming tunnel inner flow.
- */
- memcpy(tun_entry->t_dmac,
- ¶ms->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX].spec,
- RTE_ETHER_ADDR_LEN);
-
- tun_entry->tun_flow_info[params->port_id].state =
- BNXT_ULP_FLOW_STATE_TUN_O_OFFLD;
- tun_entry->outer_tun_flow_id = params->fid;
-
- /* Tunnel outer flow and it's related inner flows are correlated
- * based on Tunnel Destination IP Address.
- */
- if (tun_entry->t_dst_ip_valid)
- goto done;
- if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV4))
- memcpy(&tun_entry->t_dst_ip,
- ¶ms->hdr_field[ULP_TUN_O_IPV4_DIP_INDEX].spec,
- sizeof(rte_be32_t));
- else
- memcpy(tun_entry->t_dst_ip6,
- ¶ms->hdr_field[ULP_TUN_O_IPV6_DIP_INDEX].spec,
- sizeof(tun_entry->t_dst_ip6));
- tun_entry->t_dst_ip_valid = true;
+ tun_ent_list = bnxt_ulp_cntxt_ptr2_app_tun_list_get(ulp_ctx);
+ if (!tun_ent_list) {
+ BNXT_TF_DBG(ERR, "unable to get the app tunnel list\n");
+ return -EINVAL;
+ }
-done:
- return BNXT_TF_RC_FID;
+ for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {
+ if (!tun_ent_list[i].ref_cnt) {
+ if (free_entry < 0)
+ free_entry = i;
+ } else {
+ if (!memcmp(&tun_ent_list[i].app_tunnel,
+ app_tunnel,
+ sizeof(struct rte_flow_tunnel))) {
+ *tun_entry = &tun_ent_list[i];
+ tun_ent_list[free_entry].ref_cnt++;
+ return rc;
+ }
+ }
+ }
+ if (free_entry >= 0) {
+ *tun_entry = &tun_ent_list[free_entry];
+ memcpy(&tun_ent_list[free_entry].app_tunnel, app_tunnel,
+ sizeof(struct rte_flow_tunnel));
+ tun_ent_list[free_entry].ref_cnt = 1;
+ rc = 1;
+ } else {
+ BNXT_TF_DBG(ERR, "ulp app tunnel list is full\n");
+ return -ENOMEM;
+ }
-err:
- memset(tun_entry, 0, sizeof(struct bnxt_tun_cache_entry));
- return BNXT_TF_RC_ERROR;
+ return rc;
}
-/* This function programs the inner tunnel flow in the hardware. */
-static void
-ulp_install_inner_tun_flow(struct bnxt_tun_cache_entry *tun_entry,
- struct ulp_rte_parser_params *tun_o_params)
+void
+ulp_app_tun_entry_delete(struct bnxt_flow_app_tun_ent *tun_entry)
{
- struct bnxt_ulp_mapper_create_parms mparms = { 0 };
- struct ulp_per_port_flow_info *flow_info;
- struct ulp_rte_parser_params *inner_params;
- int ret;
-
- /* Tunnel inner flow doesn't have tunnel dmac, use the tunnel
- * dmac that was stored during F1 programming.
- */
- flow_info = &tun_entry->tun_flow_info[tun_o_params->port_id];
- STAILQ_FOREACH(inner_params, &flow_info->tun_i_prms_list, next) {
- memcpy(&inner_params->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX],
- tun_entry->t_dmac, RTE_ETHER_ADDR_LEN);
- inner_params->parent_fid = tun_entry->outer_tun_flow_id;
-
- bnxt_ulp_init_mapper_params(&mparms, inner_params,
- BNXT_ULP_FDB_TYPE_REGULAR);
-
- ret = ulp_mapper_flow_create(inner_params->ulp_ctx, &mparms);
- if (ret)
- PMD_DRV_LOG(ERR,
- "Failed to create inner tun flow, FID:%u.",
- inner_params->fid);
+ if (tun_entry) {
+ if (tun_entry->ref_cnt) {
+ tun_entry->ref_cnt--;
+ if (!tun_entry->ref_cnt)
+ memset(tun_entry, 0,
+ sizeof(struct bnxt_flow_app_tun_ent));
+ }
}
}
-/* This function either install outer tunnel flow & inner tunnel flow
- * or just the outer tunnel flow based on the flow state.
- */
-static int32_t
-ulp_post_process_outer_tun_flow(struct ulp_rte_parser_params *params,
- struct bnxt_tun_cache_entry *tun_entry,
- uint16_t tun_idx)
+int32_t
+ulp_app_tun_entry_set_decap_action(struct bnxt_flow_app_tun_ent *tun_entry)
{
- int ret;
-
- ret = ulp_install_outer_tun_flow(params, tun_entry, tun_idx);
- if (ret == BNXT_TF_RC_ERROR) {
- PMD_DRV_LOG(ERR, "Failed to create outer tunnel flow.");
- return ret;
- }
+ if (!tun_entry)
+ return -EINVAL;
- /* Install any cached tunnel inner flows that came before tunnel
- * outer flow.
- */
- ulp_install_inner_tun_flow(tun_entry, params);
-
- return BNXT_TF_RC_FID;
+ tun_entry->action.type = (typeof(tun_entry->action.type))
+ BNXT_RTE_FLOW_ACTION_TYPE_VXLAN_DECAP;
+ tun_entry->action.conf = tun_entry;
+ return 0;
}
-/* This function will be called if inner tunnel flow request comes before
- * outer tunnel flow request.
- */
-static int32_t
-ulp_post_process_cache_inner_tun_flow(struct ulp_rte_parser_params *params,
- struct bnxt_tun_cache_entry *tun_entry)
+int32_t
+ulp_app_tun_entry_set_decap_item(struct bnxt_flow_app_tun_ent *tun_entry)
{
- struct ulp_rte_parser_params *inner_tun_params;
- struct ulp_per_port_flow_info *flow_info;
- int ret;
-
-#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
-#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER
- /* Dump the rte flow pattern */
- ulp_parser_hdr_info_dump(params);
- /* Dump the rte flow action */
- ulp_parser_act_info_dump(params);
-#endif
-#endif
-
- ret = ulp_matcher_pattern_match(params, ¶ms->class_id);
- if (ret != BNXT_TF_RC_SUCCESS)
- return BNXT_TF_RC_ERROR;
-
- ret = ulp_matcher_action_match(params, ¶ms->act_tmpl);
- if (ret != BNXT_TF_RC_SUCCESS)
- return BNXT_TF_RC_ERROR;
-
- /* If Tunnel inner flow comes first then we can't install it in the
- * hardware, because, Tunnel inner flow will not have L2 context
- * information. So, just cache the Tunnel inner flow information
- * and program it in the context of F1 flow installation.
- */
- flow_info = &tun_entry->tun_flow_info[params->port_id];
- inner_tun_params = rte_zmalloc("ulp_inner_tun_params",
- sizeof(struct ulp_rte_parser_params), 0);
- if (!inner_tun_params)
- return BNXT_TF_RC_ERROR;
- memcpy(inner_tun_params, params, sizeof(struct ulp_rte_parser_params));
- STAILQ_INSERT_TAIL(&flow_info->tun_i_prms_list, inner_tun_params,
- next);
- flow_info->tun_i_cnt++;
-
- /* F1 and it's related Tunnel inner flows are correlated based on
- * Tunnel Destination IP Address. It could be already set, if
- * the inner flow got offloaded first.
- */
- if (tun_entry->t_dst_ip_valid)
- goto done;
- if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV4))
- memcpy(&tun_entry->t_dst_ip,
- ¶ms->hdr_field[ULP_TUN_O_IPV4_DIP_INDEX].spec,
- sizeof(rte_be32_t));
- else
- memcpy(tun_entry->t_dst_ip6,
- ¶ms->hdr_field[ULP_TUN_O_IPV6_DIP_INDEX].spec,
- sizeof(tun_entry->t_dst_ip6));
- tun_entry->t_dst_ip_valid = true;
-
-done:
- return BNXT_TF_RC_FID;
+ if (!tun_entry)
+ return -EINVAL;
+
+ tun_entry->item.type = (typeof(tun_entry->item.type))
+ BNXT_RTE_FLOW_ITEM_TYPE_VXLAN_DECAP;
+ tun_entry->item.spec = tun_entry;
+ tun_entry->item.last = NULL;
+ tun_entry->item.mask = NULL;
+ return 0;
}
-/* This function will be called if inner tunnel flow request comes after
- * the outer tunnel flow request.
- */
-static int32_t
-ulp_post_process_inner_tun_flow(struct ulp_rte_parser_params *params,
- struct bnxt_tun_cache_entry *tun_entry)
+struct bnxt_flow_app_tun_ent *
+ulp_app_tun_match_entry(struct bnxt_ulp_context *ulp_ctx,
+ const void *ctx)
{
- memcpy(¶ms->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX],
- tun_entry->t_dmac, RTE_ETHER_ADDR_LEN);
+ struct bnxt_flow_app_tun_ent *tun_ent_list;
+ int32_t i;
- params->parent_fid = tun_entry->outer_tun_flow_id;
+ tun_ent_list = bnxt_ulp_cntxt_ptr2_app_tun_list_get(ulp_ctx);
+ if (!tun_ent_list) {
+ BNXT_TF_DBG(ERR, "unable to get the app tunnel list\n");
+ return NULL;
+ }
- return BNXT_TF_RC_NORMAL;
+ for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {
+ if (&tun_ent_list[i] == ctx)
+ return &tun_ent_list[i];
+ }
+ return NULL;
}
static int32_t
@@ -229,203 +115,116 @@ ulp_get_tun_entry(struct ulp_rte_parser_params *params,
struct bnxt_tun_cache_entry **tun_entry,
uint16_t *tun_idx)
{
- int i, first_free_entry = BNXT_ULP_TUN_ENTRY_INVALID;
+ int32_t i, first_free_entry = BNXT_ULP_TUN_ENTRY_INVALID;
struct bnxt_tun_cache_entry *tun_tbl;
- bool tun_entry_found = false, free_entry_found = false;
+ uint32_t dip_idx, dmac_idx, use_ipv4 = 0;
tun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(params->ulp_ctx);
- if (!tun_tbl)
+ if (!tun_tbl) {
+ BNXT_TF_DBG(ERR, "Error: could not get Tunnel table\n");
return BNXT_TF_RC_ERROR;
+ }
+
+ /* get the outer destination ip field index */
+ dip_idx = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID);
+ dmac_idx = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID);
+ if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV4))
+ use_ipv4 = 1;
for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {
- if (!memcmp(&tun_tbl[i].t_dst_ip,
- ¶ms->hdr_field[ULP_TUN_O_IPV4_DIP_INDEX].spec,
- sizeof(rte_be32_t)) ||
- !memcmp(&tun_tbl[i].t_dst_ip6,
- ¶ms->hdr_field[ULP_TUN_O_IPV6_DIP_INDEX].spec,
- 16)) {
- tun_entry_found = true;
- break;
+ if (!tun_tbl[i].t_dst_ip_valid) {
+ if (first_free_entry == BNXT_ULP_TUN_ENTRY_INVALID)
+ first_free_entry = i;
+ continue;
}
-
- if (!tun_tbl[i].t_dst_ip_valid && !free_entry_found) {
- first_free_entry = i;
- free_entry_found = true;
+ /* match on the destination ip of the tunnel */
+ if ((use_ipv4 && !memcmp(&tun_tbl[i].t_dst_ip,
+ params->hdr_field[dip_idx].spec,
+ sizeof(rte_be32_t))) ||
+ (!use_ipv4 &&
+ !memcmp(tun_tbl[i].t_dst_ip6,
+ params->hdr_field[dip_idx].spec,
+ sizeof(((struct bnxt_tun_cache_entry *)
+ NULL)->t_dst_ip6)))) {
+ *tun_entry = &tun_tbl[i];
+ *tun_idx = i;
+ return 0;
}
}
-
- if (tun_entry_found) {
- *tun_entry = &tun_tbl[i];
- *tun_idx = i;
- } else {
- if (first_free_entry == BNXT_ULP_TUN_ENTRY_INVALID)
- return BNXT_TF_RC_ERROR;
- *tun_entry = &tun_tbl[first_free_entry];
- *tun_idx = first_free_entry;
- }
-
- return 0;
-}
-
-int32_t
-ulp_post_process_tun_flow(struct ulp_rte_parser_params *params)
-{
- bool inner_tun_sig, cache_inner_tun_flow;
- bool outer_tun_reject, outer_tun_flow, inner_tun_flow;
- enum bnxt_ulp_tun_flow_state flow_state;
- struct bnxt_tun_cache_entry *tun_entry;
- uint32_t l3_tun, l3_tun_decap;
- uint16_t tun_idx;
- int rc;
-
- /* Computational fields that indicate it's a TUNNEL DECAP flow */
- l3_tun = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_TUN);
- l3_tun_decap = ULP_COMP_FLD_IDX_RD(params,
- BNXT_ULP_CF_IDX_L3_TUN_DECAP);
- if (!l3_tun)
- return BNXT_TF_RC_NORMAL;
-
- rc = ulp_get_tun_entry(params, &tun_entry, &tun_idx);
- if (rc == BNXT_TF_RC_ERROR)
- return rc;
-
- if (params->port_id >= RTE_MAX_ETHPORTS)
+ if (first_free_entry == BNXT_ULP_TUN_ENTRY_INVALID) {
+ BNXT_TF_DBG(ERR, "Error: No entry available in tunnel table\n");
return BNXT_TF_RC_ERROR;
- flow_state = tun_entry->tun_flow_info[params->port_id].state;
- /* Outer tunnel flow validation */
- outer_tun_flow = BNXT_OUTER_TUN_FLOW(l3_tun, params);
- outer_tun_reject = BNXT_REJECT_OUTER_TUN_FLOW(flow_state,
- outer_tun_flow);
-
- /* Inner tunnel flow validation */
- inner_tun_sig = BNXT_INNER_TUN_SIGNATURE(l3_tun, l3_tun_decap, params);
- cache_inner_tun_flow = BNXT_CACHE_INNER_TUN_FLOW(flow_state,
- inner_tun_sig);
- inner_tun_flow = BNXT_INNER_TUN_FLOW(flow_state, inner_tun_sig);
-
- if (outer_tun_reject) {
- tun_entry->outer_tun_rej_cnt++;
- BNXT_TF_DBG(ERR,
- "Tunnel F1 flow rejected, COUNT: %d\n",
- tun_entry->outer_tun_rej_cnt);
}
- if (outer_tun_reject)
- return BNXT_TF_RC_ERROR;
- else if (cache_inner_tun_flow)
- return ulp_post_process_cache_inner_tun_flow(params, tun_entry);
- else if (outer_tun_flow)
- return ulp_post_process_outer_tun_flow(params, tun_entry,
- tun_idx);
- else if (inner_tun_flow)
- return ulp_post_process_inner_tun_flow(params, tun_entry);
- else
- return BNXT_TF_RC_NORMAL;
-}
+ *tun_idx = first_free_entry;
+ *tun_entry = &tun_tbl[first_free_entry];
+ tun_tbl[first_free_entry].t_dst_ip_valid = true;
-void
-ulp_tun_tbl_init(struct bnxt_tun_cache_entry *tun_tbl)
-{
- struct ulp_per_port_flow_info *flow_info;
- int i, j;
+ /* Update the destination ip and mac */
+ if (use_ipv4)
+ memcpy(&tun_tbl[first_free_entry].t_dst_ip,
+ params->hdr_field[dip_idx].spec, sizeof(rte_be32_t));
+ else
+ memcpy(tun_tbl[first_free_entry].t_dst_ip6,
+ params->hdr_field[dip_idx].spec,
+ sizeof(((struct bnxt_tun_cache_entry *)
+ NULL)->t_dst_ip6));
+ memcpy(tun_tbl[first_free_entry].t_dmac,
+ params->hdr_field[dmac_idx].spec, RTE_ETHER_ADDR_LEN);
- for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {
- for (j = 0; j < RTE_MAX_ETHPORTS; j++) {
- flow_info = &tun_tbl[i].tun_flow_info[j];
- STAILQ_INIT(&flow_info->tun_i_prms_list);
- }
- }
+ return 0;
}
+/* Tunnel API to delete the tunnel entry */
void
-ulp_clear_tun_entry(struct bnxt_tun_cache_entry *tun_tbl, uint8_t tun_idx)
+ulp_tunnel_offload_entry_clear(struct bnxt_tun_cache_entry *tun_tbl,
+ uint8_t tun_idx)
{
- struct ulp_rte_parser_params *inner_params;
- struct ulp_per_port_flow_info *flow_info;
- int j;
-
- for (j = 0; j < RTE_MAX_ETHPORTS; j++) {
- flow_info = &tun_tbl[tun_idx].tun_flow_info[j];
- STAILQ_FOREACH(inner_params,
- &flow_info->tun_i_prms_list,
- next) {
- STAILQ_REMOVE(&flow_info->tun_i_prms_list,
- inner_params,
- ulp_rte_parser_params, next);
- rte_free(inner_params);
- }
- }
-
- memset(&tun_tbl[tun_idx], 0,
- sizeof(struct bnxt_tun_cache_entry));
-
- for (j = 0; j < RTE_MAX_ETHPORTS; j++) {
- flow_info = &tun_tbl[tun_idx].tun_flow_info[j];
- STAILQ_INIT(&flow_info->tun_i_prms_list);
- }
+ memset(&tun_tbl[tun_idx], 0, sizeof(struct bnxt_tun_cache_entry));
}
-static bool
-ulp_chk_and_rem_tun_i_flow(struct bnxt_tun_cache_entry *tun_entry,
- struct ulp_per_port_flow_info *flow_info,
- uint32_t fid)
+/* Tunnel API to perform tunnel offload process when there is F1/F2 flows */
+int32_t
+ulp_tunnel_offload_process(struct ulp_rte_parser_params *params)
{
- struct ulp_rte_parser_params *inner_params;
- int j;
-
- STAILQ_FOREACH(inner_params,
- &flow_info->tun_i_prms_list,
- next) {
- if (inner_params->fid == fid) {
- STAILQ_REMOVE(&flow_info->tun_i_prms_list,
- inner_params,
- ulp_rte_parser_params,
- next);
- rte_free(inner_params);
- flow_info->tun_i_cnt--;
- /* When a dpdk application offloads a duplicate
- * tunnel inner flow on a port that it is not
- * destined to, there won't be a tunnel outer flow
- * associated with these duplicate tunnel inner flows.
- * So, when the last tunnel inner flow ages out, the
- * driver has to clear the tunnel entry, otherwise
- * the tunnel entry cannot be reused.
- */
- if (!flow_info->tun_i_cnt &&
- flow_info->state != BNXT_ULP_FLOW_STATE_TUN_O_OFFLD) {
- memset(tun_entry, 0,
- sizeof(struct bnxt_tun_cache_entry));
- for (j = 0; j < RTE_MAX_ETHPORTS; j++)
- STAILQ_INIT(&flow_info->tun_i_prms_list);
- }
- return true;
- }
- }
+ struct bnxt_tun_cache_entry *tun_entry;
+ uint16_t tun_idx;
+ int32_t rc = BNXT_TF_RC_SUCCESS;
- return false;
-}
+ /* Perform the tunnel offload only for F1 and F2 flows */
+ if (!ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
+ BNXT_ULP_HDR_BIT_F1) &&
+ !ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
+ BNXT_ULP_HDR_BIT_F2))
+ return rc;
-/* When a dpdk application offloads the same tunnel inner flow
- * on all the uplink ports, a tunnel inner flow entry is cached
- * even if it is not for the right uplink port. Such tunnel
- * inner flows will eventually get aged out as there won't be
- * any traffic on these ports. When such a flow destroy is
- * called, cleanup the tunnel inner flow entry.
- */
-void
-ulp_clear_tun_inner_entry(struct bnxt_tun_cache_entry *tun_tbl, uint32_t fid)
-{
- struct ulp_per_port_flow_info *flow_info;
- int i, j;
+ /* search for the tunnel entry if not found create one */
+ rc = ulp_get_tun_entry(params, &tun_entry, &tun_idx);
+ if (rc == BNXT_TF_RC_ERROR)
+ return rc;
- for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {
- if (!tun_tbl[i].t_dst_ip_valid)
- continue;
- for (j = 0; j < RTE_MAX_ETHPORTS; j++) {
- flow_info = &tun_tbl[i].tun_flow_info[j];
- if (ulp_chk_and_rem_tun_i_flow(&tun_tbl[i],
- flow_info, fid) == true)
- return;
- }
+ /* Tunnel offload for the outer Tunnel flow */
+ if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
+ BNXT_ULP_HDR_BIT_F1)) {
+ /* Reset the JUMP action bit in the action bitmap as we don't
+ * offload this action.
+ */
+ ULP_BITMAP_RESET(params->act_bitmap.bits,
+ BNXT_ULP_ACT_BIT_JUMP);
+ params->parent_flow = true;
+ params->tun_idx = tun_idx;
+ tun_entry->outer_tun_flow_id = params->fid;
+ } else if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
+ BNXT_ULP_HDR_BIT_F2)) {
+ ULP_BITMAP_RESET(params->hdr_bitmap.bits,
+ BNXT_ULP_HDR_BIT_F2);
+ /* add the vxlan decap action for F2 flows */
+ ULP_BITMAP_SET(params->act_bitmap.bits,
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP);
+ params->child_flow = true;
+ params->tun_idx = tun_idx;
+ params->parent_flow = false;
}
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_TUNNEL_ID, tun_idx);
+ return rc;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.h b/drivers/net/bnxt/tf_ulp/ulp_tun.h
index 898071bfe7..0fc2ac39d1 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_tun.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_tun.h
@@ -8,7 +8,6 @@
#include <inttypes.h>
#include <stdbool.h>
-#include <sys/queue.h>
#include "rte_version.h"
#include "rte_ethdev.h"
@@ -16,60 +15,6 @@
#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
-#define BNXT_OUTER_TUN_FLOW(l3_tun, params) \
- ((l3_tun) && \
- ULP_BITMAP_ISSET((params)->act_bitmap.bits, \
- BNXT_ULP_ACT_BIT_JUMP))
-#define BNXT_INNER_TUN_SIGNATURE(l3_tun, l3_tun_decap, params) \
- ((l3_tun) && (l3_tun_decap) && \
- !ULP_BITMAP_ISSET((params)->hdr_bitmap.bits, \
- BNXT_ULP_HDR_BIT_O_ETH))
-
-#define BNXT_CACHE_INNER_TUN_FLOW(state, inner_tun_sig) \
- ((state) == BNXT_ULP_FLOW_STATE_NORMAL && (inner_tun_sig))
-#define BNXT_INNER_TUN_FLOW(state, inner_tun_sig) \
- ((state) == BNXT_ULP_FLOW_STATE_TUN_O_OFFLD && (inner_tun_sig))
-
-/* It is invalid to get another outer flow offload request
- * for the same tunnel, while the outer flow is already offloaded.
- */
-#define BNXT_REJECT_OUTER_TUN_FLOW(state, outer_tun_sig) \
- ((state) == BNXT_ULP_FLOW_STATE_TUN_O_OFFLD && (outer_tun_sig))
-
-#define ULP_TUN_O_DMAC_HDR_FIELD_INDEX 1
-#define ULP_TUN_O_IPV4_DIP_INDEX 19
-#define ULP_TUN_O_IPV6_DIP_INDEX 17
-
-/* When a flow offload request comes the following state transitions
- * happen based on the order in which the outer & inner flow offload
- * requests arrive.
- *
- * If inner tunnel flow offload request arrives first then the flow
- * state will remain in BNXT_ULP_FLOW_STATE_NORMAL state.
- * The following outer tunnel flow offload request will change the
- * state of the flow to BNXT_ULP_FLOW_STATE_TUN_O_OFFLD from
- * BNXT_ULP_FLOW_STATE_NORMAL.
- *
- * If outer tunnel flow offload request arrives first then the flow state
- * will change from BNXT_ULP_FLOW_STATE_NORMAL to
- * BNXT_ULP_FLOW_STATE_TUN_O_OFFLD.
- *
- * Once the flow state is in BNXT_ULP_FLOW_STATE_TUN_O_OFFLD, any inner
- * tunnel flow offload requests after that point will be treated as a
- * normal flow and the tunnel flow state remains in
- * BNXT_ULP_FLOW_STATE_TUN_O_OFFLD
- */
-enum bnxt_ulp_tun_flow_state {
- BNXT_ULP_FLOW_STATE_NORMAL = 0,
- BNXT_ULP_FLOW_STATE_TUN_O_OFFLD,
-};
-
-struct ulp_per_port_flow_info {
- enum bnxt_ulp_tun_flow_state state;
- uint32_t tun_i_cnt;
- STAILQ_HEAD(, ulp_rte_parser_params) tun_i_prms_list;
-};
-
struct bnxt_tun_cache_entry {
bool t_dst_ip_valid;
uint8_t t_dmac[RTE_ETHER_ADDR_LEN];
@@ -78,17 +23,39 @@ struct bnxt_tun_cache_entry {
uint8_t t_dst_ip6[16];
};
uint32_t outer_tun_flow_id;
- uint16_t outer_tun_rej_cnt;
- struct ulp_per_port_flow_info tun_flow_info[RTE_MAX_ETHPORTS];
};
-void
-ulp_tun_tbl_init(struct bnxt_tun_cache_entry *tun_tbl);
+struct bnxt_flow_app_tun_ent {
+ struct rte_flow_tunnel app_tunnel;
+ uint32_t tun_id;
+ uint32_t ref_cnt;
+ struct rte_flow_action action;
+ struct rte_flow_item item;
+};
+
+int32_t
+ulp_app_tun_search_entry(struct bnxt_ulp_context *ulp_ctx,
+ struct rte_flow_tunnel *app_tunnel,
+ struct bnxt_flow_app_tun_ent **tun_entry);
void
-ulp_clear_tun_entry(struct bnxt_tun_cache_entry *tun_tbl, uint8_t tun_idx);
+ulp_app_tun_entry_delete(struct bnxt_flow_app_tun_ent *tun_entry);
+int32_t
+ulp_app_tun_entry_set_decap_action(struct bnxt_flow_app_tun_ent *tun_entry);
+
+int32_t
+ulp_app_tun_entry_set_decap_item(struct bnxt_flow_app_tun_ent *tun_entry);
+
+struct bnxt_flow_app_tun_ent *
+ulp_app_tun_match_entry(struct bnxt_ulp_context *ulp_ctx, const void *ctx);
+
+/* Tunnel API to delete the tunnel entry */
void
-ulp_clear_tun_inner_entry(struct bnxt_tun_cache_entry *tun_tbl, uint32_t fid);
+ulp_tunnel_offload_entry_clear(struct bnxt_tun_cache_entry *tun_tbl,
+ uint8_t tun_idx);
+
+int32_t
+ulp_tunnel_offload_process(struct ulp_rte_parser_params *params);
#endif
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v3 07/13] net/bnxt: add support for dynamic encap action
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 00/13] enhancements to host based flow table management Venkat Duvvuru
` (5 preceding siblings ...)
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 06/13] net/bnxt: add support for tunnel offloads Venkat Duvvuru
@ 2021-09-11 15:30 ` Venkat Duvvuru
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 08/13] net/bnxt: add wild card TCAM byte order for Thor Venkat Duvvuru
` (7 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-11 15:30 UTC (permalink / raw)
To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
The encapsulation record processing is enhanced to handle data
dynamically. Different combinations of VXLAN encapsulation using
no VLAN or single or double VLAN can be supported and also supports
both IPv4 and IPv6 versions.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
---
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 25 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 2 +
.../generic_templates/ulp_template_db_enum.h | 44 +-
.../generic_templates/ulp_template_db_tbl.c | 8 +-
.../ulp_template_db_thor_act.c | 4 +-
.../ulp_template_db_thor_class.c | 46 +-
.../ulp_template_db_wh_plus_act.c | 1700 ++++++++++++-----
.../ulp_template_db_wh_plus_class.c | 222 +--
drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 6 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 2 +-
drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 152 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.h | 4 +
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 337 ++--
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 2 +
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 10 +-
drivers/net/bnxt/tf_ulp/ulp_utils.c | 73 +-
drivers/net/bnxt/tf_ulp/ulp_utils.h | 27 +-
18 files changed, 1717 insertions(+), 949 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index dfafd9ff5b..3b86410fb1 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -830,13 +830,12 @@ ulp_ctx_init(struct bnxt *bp,
goto error_deinit;
}
- /* TODO: For now we are overriding to APP:1 on this branch*/
- bp->app_id = 1;
rc = bnxt_ulp_cntxt_app_id_set(bp->ulp_ctx, bp->app_id);
if (rc) {
BNXT_TF_DBG(ERR, "Unable to set app_id for ULP init.\n");
goto error_deinit;
}
+ BNXT_TF_DBG(DEBUG, "Ulp initialized with app id %d\n", bp->app_id);
rc = bnxt_ulp_cntxt_app_caps_init(bp->ulp_ctx, bp->app_id, devid);
if (rc) {
@@ -1393,13 +1392,17 @@ bnxt_ulp_port_init(struct bnxt *bp)
uint32_t ulp_flags;
int32_t rc = 0;
- if (!bp || !BNXT_TRUFLOW_EN(bp))
- return rc;
-
if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
BNXT_TF_DBG(ERR,
"Skip ulp init for port: %d, not a TVF or PF\n",
- bp->eth_dev->data->port_id);
+ bp->eth_dev->data->port_id);
+ return rc;
+ }
+
+ if (!BNXT_TRUFLOW_EN(bp)) {
+ BNXT_TF_DBG(ERR,
+ "Skip ulp init for port: %d, truflow is not enabled\n",
+ bp->eth_dev->data->port_id);
return rc;
}
@@ -1520,9 +1523,6 @@ bnxt_ulp_port_deinit(struct bnxt *bp)
struct rte_pci_device *pci_dev;
struct rte_pci_addr *pci_addr;
- if (!BNXT_TRUFLOW_EN(bp))
- return;
-
if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
BNXT_TF_DBG(ERR,
"Skip ULP deinit port:%d, not a TVF or PF\n",
@@ -1530,6 +1530,13 @@ bnxt_ulp_port_deinit(struct bnxt *bp)
return;
}
+ if (!BNXT_TRUFLOW_EN(bp)) {
+ BNXT_TF_DBG(ERR,
+ "Skip ULP deinit for port:%d, truflow is not enabled\n",
+ bp->eth_dev->data->port_id);
+ return;
+ }
+
if (!bp->ulp_ctx) {
BNXT_TF_DBG(DEBUG, "ulp ctx already de-allocated\n");
return;
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
index 3daf5942e8..413e4c3b26 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
@@ -96,7 +96,9 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms,
mapper_cparms->act_tid = params->act_tmpl;
mapper_cparms->func_id = params->func_id;
mapper_cparms->hdr_bitmap = ¶ms->hdr_bitmap;
+ mapper_cparms->enc_hdr_bitmap = ¶ms->enc_hdr_bitmap;
mapper_cparms->hdr_field = params->hdr_field;
+ mapper_cparms->enc_field = params->enc_field;
mapper_cparms->comp_fld = params->comp_fld;
mapper_cparms->act = ¶ms->act_bitmap;
mapper_cparms->act_prop = ¶ms->act_prop;
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
index e55d0923a5..9010d9a749 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 20 11:56:39 2021 */
+/* date: Thu May 27 17:35:19 2021 */
#ifndef ULP_TEMPLATE_DB_H_
#define ULP_TEMPLATE_DB_H_
@@ -41,7 +41,7 @@
#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 89
#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 600
#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 26
-#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 619
+#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 618
#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 49
#define ULP_THOR_CLASS_TMPL_LIST_SIZE 6
#define ULP_THOR_CLASS_TBL_LIST_SIZE 33
@@ -53,7 +53,7 @@
#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 35
#define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2
#define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 1
-#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 512
+#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 527
#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 39
#define ULP_THOR_ACT_TMPL_LIST_SIZE 7
#define ULP_THOR_ACT_TBL_LIST_SIZE 2
@@ -229,7 +229,9 @@ enum bnxt_ulp_cond_opc {
BNXT_ULP_COND_OPC_ACT_PAT_MATCH = 11,
BNXT_ULP_COND_OPC_EXT_MEM_IS_SET = 12,
BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET = 13,
- BNXT_ULP_COND_OPC_LAST = 14
+ BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET = 14,
+ BNXT_ULP_COND_OPC_ENC_HDR_BIT_NOT_SET = 15,
+ BNXT_ULP_COND_OPC_LAST = 16
};
enum bnxt_ulp_critical_resource {
@@ -257,6 +259,36 @@ enum bnxt_ulp_direction {
BNXT_ULP_DIRECTION_LAST = 2
};
+enum bnxt_ulp_enc_field {
+ BNXT_ULP_ENC_FIELD_ETH_DMAC = 0,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC = 1,
+ BNXT_ULP_ENC_FIELD_ETH_TYPE = 2,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TCI = 3,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TYPE = 4,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TCI = 5,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TYPE = 6,
+ BNXT_ULP_ENC_FIELD_IPV4_IHL = 7,
+ BNXT_ULP_ENC_FIELD_IPV4_TOS = 8,
+ BNXT_ULP_ENC_FIELD_IPV4_PKT_ID = 9,
+ BNXT_ULP_ENC_FIELD_IPV4_FRAG = 10,
+ BNXT_ULP_ENC_FIELD_IPV4_TTL = 11,
+ BNXT_ULP_ENC_FIELD_IPV4_PROTO = 12,
+ BNXT_ULP_ENC_FIELD_IPV4_SADDR = 13,
+ BNXT_ULP_ENC_FIELD_IPV4_DADDR = 14,
+ BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW = 15,
+ BNXT_ULP_ENC_FIELD_IPV6_PROTO = 16,
+ BNXT_ULP_ENC_FIELD_IPV6_TTL = 17,
+ BNXT_ULP_ENC_FIELD_IPV6_SADDR = 18,
+ BNXT_ULP_ENC_FIELD_IPV6_DADDR = 19,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT = 20,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT = 21,
+ BNXT_ULP_ENC_FIELD_VXLAN_FLAGS = 22,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 = 23,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI = 24,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 = 25,
+ BNXT_ULP_ENC_FIELD_LAST = 26
+};
+
enum bnxt_ulp_fdb_opc {
BNXT_ULP_FDB_OPC_PUSH_FID = 0,
BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE = 1,
@@ -304,7 +336,9 @@ enum bnxt_ulp_field_src {
BNXT_ULP_FIELD_SRC_SKIP = 13,
BNXT_ULP_FIELD_SRC_REJECT = 14,
BNXT_ULP_FIELD_SRC_PORT_TABLE = 15,
- BNXT_ULP_FIELD_SRC_LAST = 16
+ BNXT_ULP_FIELD_SRC_ENC_HDR_BIT = 16,
+ BNXT_ULP_FIELD_SRC_ENC_FIELD = 17,
+ BNXT_ULP_FIELD_SRC_LAST = 18
};
enum bnxt_ulp_func_opc {
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
index 58b4dba63c..b5bce6f4c7 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
@@ -198,7 +198,9 @@ const struct bnxt_ulp_template_device_tbls ulp_template_thor_tbls[] = {
struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
[BNXT_ULP_DEVICE_ID_WH_PLUS] = {
.description = "Whitney_Plus",
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .encap_byte_order = BNXT_ULP_BYTE_ORDER_BE,
.encap_byte_swap = 1,
.int_flow_db_num_entries = 16384,
.ext_flow_db_num_entries = 32768,
@@ -218,7 +220,9 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
},
[BNXT_ULP_DEVICE_ID_THOR] = {
.description = "Thor",
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .encap_byte_order = BNXT_ULP_BYTE_ORDER_BE,
.encap_byte_swap = 1,
.int_flow_db_num_entries = 16384,
.ext_flow_db_num_entries = 32768,
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
index ce5a70b0c5..9faf25aaf0 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 13 18:15:56 2021 */
+/* date: Wed May 26 15:11:34 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -41,7 +41,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 0,
.result_bit_size = 64,
.result_num_fields = 1
@@ -62,7 +61,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 1,
.result_bit_size = 128,
.result_num_fields = 17
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
index d20c4197fa..ea9b9773a5 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 20 11:56:39 2021 */
+/* date: Wed May 26 15:11:34 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -59,7 +59,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 0,
.blob_key_bit_size = 10,
.key_bit_size = 10,
@@ -82,7 +81,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 1,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -104,7 +102,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 2,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -122,8 +119,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_start_idx = 5,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 1, , table: l2_cntxt_tcam.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -141,7 +137,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 7,
.blob_key_bit_size = 213,
.key_bit_size = 213,
@@ -166,7 +161,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 28,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -189,7 +183,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 33,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -207,8 +200,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_start_idx = 6,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 1, , table: fkb_select.l3_l4_wm */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -223,7 +215,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 10,
.result_bit_size = 106,
.result_num_fields = 106
@@ -246,7 +237,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 36,
.blob_key_bit_size = 94,
.key_bit_size = 94,
@@ -271,7 +261,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 79,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -297,7 +286,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_BE,
.key_start_idx = 82,
.blob_key_bit_size = 0,
.key_bit_size = 0,
@@ -322,7 +310,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 136,
.result_bit_size = 128,
.result_num_fields = 17
@@ -341,7 +328,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 196,
.blob_key_bit_size = 10,
.key_bit_size = 10,
@@ -364,7 +350,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 197,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -382,8 +367,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_start_idx = 9,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -403,7 +387,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 198,
.blob_key_bit_size = 213,
.key_bit_size = 213,
@@ -428,7 +411,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 219,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -450,7 +432,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 168,
.result_bit_size = 32,
.result_num_fields = 1
@@ -468,7 +449,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 169,
.result_bit_size = 32,
.result_num_fields = 1
@@ -482,8 +462,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 10,
.cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
{ /* class_tid: 4, , table: int_full_act_record.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -501,7 +480,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 170,
.result_bit_size = 128,
.result_num_fields = 17,
@@ -521,7 +499,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 220,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -539,8 +516,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_start_idx = 11,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -558,7 +534,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 221,
.blob_key_bit_size = 213,
.key_bit_size = 213,
@@ -582,7 +557,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 193,
.result_bit_size = 32,
.result_num_fields = 1
@@ -600,7 +574,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 194,
.result_bit_size = 32,
.result_num_fields = 1
@@ -621,7 +594,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 195,
.result_bit_size = 128,
.result_num_fields = 17,
@@ -640,7 +612,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 212,
.result_bit_size = 32,
.result_num_fields = 1
@@ -658,7 +629,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 213,
.result_bit_size = 32,
.result_num_fields = 1
@@ -679,7 +649,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 214,
.result_bit_size = 128,
.result_num_fields = 17,
@@ -701,7 +670,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .record_size = 16,
.result_start_idx = 231,
.result_bit_size = 0,
.result_num_fields = 0,
@@ -723,7 +692,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 242,
.result_bit_size = 128,
.result_num_fields = 17
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
index de924fe81a..578ede8bba 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Mon May 17 15:54:03 2021 */
+/* date: Tue Jun 1 16:05:30 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -90,7 +90,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 0,
.blob_key_bit_size = 1,
.key_bit_size = 1,
@@ -114,14 +113,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 0,
.result_bit_size = 64,
.result_num_fields = 1
},
{ /* act_tid: 1, , table: int_vtag_encap_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
.direction = TF_DIR_RX,
@@ -135,11 +133,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .record_size = 8,
.result_start_idx = 1,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 1, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -157,8 +155,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 13,
+ .result_start_idx = 12,
.result_bit_size = 128,
.result_num_fields = 26,
.encap_num_fields = 0
@@ -179,11 +176,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 39,
+ .result_start_idx = 38,
.result_bit_size = 128,
.result_num_fields = 26,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 2, , table: control.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
@@ -195,8 +191,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_start_idx = 14,
.cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* act_tid: 2, , table: mirror_tbl.alloc */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -215,8 +210,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 77,
+ .result_start_idx = 75,
.result_bit_size = 32,
.result_num_fields = 6
},
@@ -237,8 +231,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 83,
+ .result_start_idx = 81,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -259,8 +252,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 84,
+ .result_start_idx = 82,
.result_bit_size = 128,
.result_num_fields = 26,
.encap_num_fields = 0
@@ -282,11 +274,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 110,
+ .result_start_idx = 108,
.result_bit_size = 128,
.result_num_fields = 26,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 2, , table: mirror_tbl.wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -304,8 +295,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 148,
+ .result_start_idx = 145,
.result_bit_size = 32,
.result_num_fields = 6
},
@@ -324,12 +314,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 1,
.blob_key_bit_size = 1,
.key_bit_size = 1,
.key_num_fields = 1,
- .result_start_idx = 154,
+ .result_start_idx = 151,
.result_bit_size = 34,
.result_num_fields = 2
},
@@ -348,8 +337,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 156,
+ .result_start_idx = 153,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -368,8 +356,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 157,
+ .result_start_idx = 154,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -388,8 +375,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 158,
+ .result_start_idx = 155,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -408,11 +394,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 159,
+ .record_size = 16,
+ .result_start_idx = 156,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 3, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -429,8 +415,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 171,
+ .result_start_idx = 167,
.result_bit_size = 128,
.result_num_fields = 26
},
@@ -449,11 +434,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 197,
+ .result_start_idx = 193,
.result_bit_size = 128,
.result_num_fields = 26,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 4, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -470,8 +454,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 235,
+ .result_start_idx = 230,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -490,11 +473,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 236,
+ .record_size = 8,
+ .result_start_idx = 231,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 4, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -511,8 +494,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 248,
+ .result_start_idx = 242,
.result_bit_size = 128,
.result_num_fields = 26
},
@@ -531,11 +513,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 274,
+ .result_start_idx = 268,
.result_bit_size = 128,
.result_num_fields = 26,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 4, , table: ext_full_act_record.one_tag */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -552,11 +533,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 312,
+ .result_start_idx = 305,
.result_bit_size = 128,
.result_num_fields = 26,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 5, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -573,8 +553,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 350,
+ .result_start_idx = 342,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -593,8 +572,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 351,
+ .result_start_idx = 343,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -613,8 +591,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 352,
+ .result_start_idx = 344,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -633,11 +610,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 353,
+ .record_size = 16,
+ .result_start_idx = 345,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 5, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -654,8 +631,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 365,
+ .result_start_idx = 356,
.result_bit_size = 128,
.result_num_fields = 26
},
@@ -674,11 +650,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 391,
+ .result_start_idx = 382,
.result_bit_size = 128,
.result_num_fields = 26,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 6, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -695,8 +670,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 429,
+ .result_start_idx = 419,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -715,11 +689,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 430,
+ .record_size = 16,
+ .result_start_idx = 420,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 3
+ .encap_num_fields = 2
},
{ /* act_tid: 6, , table: sp_smac_ipv6.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -736,11 +710,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 433,
+ .record_size = 24,
+ .result_start_idx = 422,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 3
+ .encap_num_fields = 2
},
{ /* act_tid: 6, , table: int_tun_encap_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -757,11 +731,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 436,
+ .record_size = 64,
+ .result_start_idx = 424,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 12
+ .encap_num_fields = 30
},
{ /* act_tid: 6, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -778,8 +752,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 448,
+ .result_start_idx = 454,
.result_bit_size = 128,
.result_num_fields = 26
},
@@ -798,11 +771,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 474,
+ .result_start_idx = 480,
.result_bit_size = 128,
.result_num_fields = 26,
- .encap_num_fields = 12
+ .encap_num_fields = 30
}
};
@@ -1033,22 +1005,26 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
},
/* act_tid: 1, , table: int_vtag_encap_record.0 */
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
},
{
.description = "ecv_l2_en",
@@ -1057,26 +1033,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "vtag_tpid",
@@ -1088,13 +1060,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
},
{
.description = "vtag_de",
@@ -1103,19 +1075,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
- },
- {
- .description = "spare",
- .field_bit_size = 80,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
},
/* act_tid: 1, , table: int_full_act_record.0 */
{
@@ -1628,20 +1594,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -1649,25 +1617,23 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.description = "ecv_l2_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_L2_EN_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -1678,8 +1644,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -1690,14 +1656,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 0,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2105,20 +2065,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2126,25 +2088,23 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.description = "ecv_l2_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_L2_EN_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2155,8 +2115,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2167,14 +2127,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 0,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2268,20 +2222,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
},
/* act_tid: 3, , table: int_encap_mac_record.0 */
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2294,24 +2250,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
ULP_WP_SYM_ECV_L2_EN_YES}
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "vtag_tpid",
@@ -2320,8 +2274,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2332,14 +2286,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 80,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2806,20 +2754,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2827,25 +2777,23 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.description = "ecv_l2_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_L2_EN_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2856,8 +2804,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2868,14 +2816,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 0,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2888,23 +2830,27 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
},
/* act_tid: 4, , table: int_vtag_encap_record.0 */
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
+ },
{
.description = "ecv_l2_en",
.field_bit_size = 1,
@@ -2912,26 +2858,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "vtag_tpid",
@@ -2943,13 +2885,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
},
{
.description = "vtag_de",
@@ -2958,19 +2900,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
- },
- {
- .description = "spare",
- .field_bit_size = 80,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
},
/* act_tid: 4, , table: int_full_act_record.0 */
{
@@ -3350,20 +3286,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -3371,25 +3309,23 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.description = "ecv_l2_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_L2_EN_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -3400,8 +3336,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -3412,14 +3348,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 0,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -3620,22 +3550,26 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
},
{
.description = "ecv_l2_en",
@@ -3644,26 +3578,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "vtag_tpid",
@@ -3675,13 +3605,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
},
{
.description = "vtag_de",
@@ -3690,19 +3620,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
- },
- {
- .description = "spare",
- .field_bit_size = 0,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
},
/* act_tid: 5, , table: int_flow_counter_tbl.0 */
{
@@ -3733,20 +3657,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
},
/* act_tid: 5, , table: int_encap_mac_record.dummy */
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -3759,24 +3685,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
ULP_WP_SYM_ECV_L2_EN_YES}
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "vtag_tpid",
@@ -3785,8 +3709,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -3797,14 +3721,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 80,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -4271,20 +4189,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -4292,25 +4212,23 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.description = "ecv_l2_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_L2_EN_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -4321,8 +4239,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -4333,14 +4251,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 0,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -4356,76 +4268,62 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.description = "smac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC & 0xff}
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
},
{
.description = "ipv4_src_addr",
.field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC & 0xff}
- },
- {
- .description = "reserved",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}
},
/* act_tid: 6, , table: sp_smac_ipv6.0 */
{
.description = "smac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC & 0xff}
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
},
{
.description = "ipv6_src_addr",
.field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC & 0xff}
- },
- {
- .description = "reserved",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ENC_FIELD_IPV6_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_SADDR & 0xff}
},
/* act_tid: 6, , table: int_tun_encap_record.0 */
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ULP_WP_SYM_ECV_TUN_TYPE_VXLAN}
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
},
{
.description = "ecv_l2_en",
@@ -4433,81 +4331,478 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ ULP_WP_SYM_ECV_L2_EN_YES}
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM}
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ ULP_WP_SYM_ECV_TUN_TYPE_VXLAN}
},
{
- .description = "encap_l2_dmac",
+ .description = "enc_eth_dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC & 0xff}
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
},
{
- .description = "encap_vtag",
- .field_bit_size = 0,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ,
+ .description = "enc_o_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_o_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_ihl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_tos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_pkt_id",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_frag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_daddr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_vtc",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_zero",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG & 0xff,
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ZERO,
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
- .description = "encap_ip",
- .field_bit_size = 0,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ,
+ .description = "enc_ipv6_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_daddr",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_vxlan_flags",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_IP & 0xff,
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
- .description = "encap_udp",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .description = "enc_vxlan_rsvd0",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
- .description = "encap_tun",
- .field_bit_size = 0,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ,
+ .description = "enc_vxlan_vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN & 0xff,
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_vxlan_rsvd1",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
/* act_tid: 6, , table: int_full_act_record.0 */
{
@@ -4857,29 +5152,27 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ULP_WP_SYM_ECV_TUN_TYPE_VXLAN}
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
},
{
.description = "ecv_l2_en",
@@ -4887,79 +5180,478 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ ULP_WP_SYM_ECV_L2_EN_YES}
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM}
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ ULP_WP_SYM_ECV_TUN_TYPE_VXLAN}
},
{
- .description = "encap_l2_dmac",
+ .description = "enc_eth_dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC & 0xff}
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
},
{
- .description = "encap_vtag",
- .field_bit_size = 0,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ,
+ .description = "enc_o_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_o_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_ihl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_tos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_pkt_id",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_frag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_daddr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_vtc",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_zero",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG & 0xff,
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ZERO,
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
- .description = "encap_ip",
- .field_bit_size = 0,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ,
+ .description = "enc_ipv6_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_daddr",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_vxlan_flags",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_vxlan_rsvd0",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_IP & 0xff,
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
- .description = "encap_udp",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .description = "enc_vxlan_vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
- .description = "encap_tun",
- .field_bit_size = 80,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .description = "enc_vxlan_rsvd1",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
index 7b6ee03a4b..7203dcf1fb 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Mon May 17 15:54:03 2021 */
+/* date: Fri May 28 16:46:46 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -80,7 +80,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 0,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -102,7 +101,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 1,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -120,8 +118,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 2,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 1, , table: l2_cntxt_tcam.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -139,7 +136,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 6,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -164,7 +160,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 19,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -188,7 +183,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 24,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -206,8 +200,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 3,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 1, , table: control.2 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
@@ -225,8 +218,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
.func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
.func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
- .func_dst_opr = BNXT_ULP_RF_IDX_CC },
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
},
{ /* class_tid: 1, , table: profile_tcam.ipv4 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -244,7 +236,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 27,
.blob_key_bit_size = 81,
.key_bit_size = 81,
@@ -271,7 +262,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 70,
.blob_key_bit_size = 81,
.key_bit_size = 81,
@@ -298,7 +288,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 113,
.blob_key_bit_size = 81,
.key_bit_size = 81,
@@ -324,7 +313,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 156,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -346,7 +334,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 159,
.blob_key_bit_size = 176,
.key_bit_size = 176,
@@ -368,7 +355,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 169,
.blob_key_bit_size = 448,
.key_bit_size = 448,
@@ -390,7 +376,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 179,
.blob_key_bit_size = 416,
.key_bit_size = 416,
@@ -412,7 +397,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 190,
.blob_key_bit_size = 448,
.key_bit_size = 448,
@@ -434,7 +418,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 201,
.blob_key_bit_size = 200,
.key_bit_size = 200,
@@ -456,7 +439,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 212,
.blob_key_bit_size = 448,
.key_bit_size = 448,
@@ -479,7 +461,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 223,
.blob_key_bit_size = 16,
.key_bit_size = 16,
@@ -497,8 +478,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 25,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -516,7 +496,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 225,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -541,7 +520,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 238,
.blob_key_bit_size = 16,
.key_bit_size = 16,
@@ -559,8 +537,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 26,
.cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
{ /* class_tid: 2, , table: mac_addr_cache.rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
@@ -576,7 +553,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 240,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -594,8 +570,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 27,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 2, , table: l2_cntxt_tcam.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -613,7 +588,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 245,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -638,7 +612,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 258,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -662,7 +635,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 263,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -680,8 +652,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 28,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 2, , table: profile_tcam.f2 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -701,7 +672,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_operand = 1,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 266,
.blob_key_bit_size = 81,
.key_bit_size = 81,
@@ -725,7 +695,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 309,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -747,7 +716,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 312,
.blob_key_bit_size = 112,
.key_bit_size = 112,
@@ -769,7 +737,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 320,
.blob_key_bit_size = 448,
.key_bit_size = 448,
@@ -792,7 +759,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 328,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -814,7 +780,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 329,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -832,8 +797,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 32,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 3, , table: l2_cntxt_tcam.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -851,7 +815,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 334,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -876,7 +839,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 347,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -899,7 +861,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 352,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -917,8 +878,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 33,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 3, , table: control.conflict_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
@@ -936,8 +896,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
.func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
.func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
- .func_dst_opr = BNXT_ULP_RF_IDX_CC },
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
},
{ /* class_tid: 3, , table: profile_tcam.ipv4 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -955,7 +914,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 355,
.blob_key_bit_size = 81,
.key_bit_size = 81,
@@ -982,7 +940,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 398,
.blob_key_bit_size = 81,
.key_bit_size = 81,
@@ -1007,7 +964,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 441,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -1029,7 +985,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 444,
.blob_key_bit_size = 176,
.key_bit_size = 176,
@@ -1051,7 +1006,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 454,
.blob_key_bit_size = 448,
.key_bit_size = 448,
@@ -1073,7 +1027,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 464,
.blob_key_bit_size = 416,
.key_bit_size = 416,
@@ -1095,7 +1048,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 475,
.blob_key_bit_size = 448,
.key_bit_size = 448,
@@ -1120,7 +1072,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 292,
.result_bit_size = 128,
.result_num_fields = 26
@@ -1139,7 +1090,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 486,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1157,8 +1107,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 41,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1178,7 +1127,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 487,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -1203,7 +1151,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 500,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1225,7 +1172,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 335,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1243,7 +1189,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 336,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1261,7 +1206,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 337,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1275,8 +1219,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 42,
.cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
{ /* class_tid: 4, , table: int_full_act_record.egr_vfr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1294,7 +1237,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 338,
.result_bit_size = 128,
.result_num_fields = 26,
@@ -1314,7 +1256,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 501,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1332,8 +1273,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 43,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 4, , table: l2_cntxt_tcam_bypass.egr_vfr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1351,7 +1291,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 502,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -1376,7 +1315,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 515,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1399,7 +1337,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 516,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1417,8 +1354,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 44,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1436,7 +1372,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 517,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -1461,7 +1396,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 530,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1486,7 +1420,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 398,
.result_bit_size = 128,
.result_num_fields = 26,
@@ -1505,7 +1438,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 424,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1523,7 +1455,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 425,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1541,7 +1472,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 426,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1562,7 +1492,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 427,
.result_bit_size = 128,
.result_num_fields = 26,
@@ -1582,7 +1511,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 531,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1600,8 +1528,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 47,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1619,7 +1546,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 532,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -1644,7 +1570,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 545,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1666,7 +1591,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 470,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1684,7 +1608,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 471,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1702,7 +1625,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 472,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1723,7 +1645,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 473,
.result_bit_size = 128,
.result_num_fields = 26,
@@ -1746,7 +1667,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 546,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -1771,7 +1691,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 559,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1789,8 +1708,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 48,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_egr0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1808,7 +1726,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 560,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -1833,7 +1750,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 573,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1858,11 +1774,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .record_size = 8,
.result_start_idx = 529,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1880,8 +1796,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 541,
+ .result_start_idx = 540,
.result_bit_size = 128,
.result_num_fields = 26
},
@@ -1901,8 +1816,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 567,
+ .result_start_idx = 566,
.result_bit_size = 128,
.result_num_fields = 26
},
@@ -1923,12 +1837,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 574,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 593,
+ .result_start_idx = 592,
.result_bit_size = 64,
.result_num_fields = 13,
.ident_start_idx = 26,
@@ -1951,12 +1864,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 587,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 606,
+ .result_start_idx = 605,
.result_bit_size = 64,
.result_num_fields = 13,
.ident_start_idx = 26,
@@ -2522,17 +2434,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -6207,17 +6115,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -8046,17 +7950,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -16093,22 +15993,26 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
},
/* class_tid: 5, , table: int_vtag_encap_record.vfr_egr0 */
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
},
{
.description = "ecv_l2_en",
@@ -16117,26 +16021,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "vtag_tpid",
@@ -16148,13 +16048,10 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
0x00}
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "vtag_de",
@@ -16163,16 +16060,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 80,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
},
/* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
{
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
index 039c9c2a6b..1cb52e9bfa 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
@@ -116,7 +116,7 @@ ulp_flow_db_resource_func_get(struct ulp_fdb_resource_info *res_info)
func = (((res_info->nxt_resource_idx & ULP_FLOW_DB_RES_FUNC_MASK) >>
ULP_FLOW_DB_RES_FUNC_BITS) << ULP_FLOW_DB_RES_FUNC_UPPER);
- /* The reource func is split into upper and lower */
+ /* The resource func is split into upper and lower */
if (func & ULP_FLOW_DB_RES_FUNC_NEED_LOWER)
return (func | res_info->resource_func_lower);
return func;
@@ -622,7 +622,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt,
if (params->critical_resource && fid_resource->resource_em_handle) {
BNXT_TF_DBG(DEBUG, "Ignore multiple critical resources\n");
- /* Ignore the multiple criticial resources */
+ /* Ignore the multiple critical resources */
params->critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO;
}
@@ -674,7 +674,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt,
* flow_type [in] Specify it is regular or default flow
* fid [in] The index to the flow entry
* params [in/out] The contents to be copied into params.
- * Onlythe critical_resource needs to be set by the caller.
+ * Only the critical_resource needs to be set by the caller.
*
* Returns 0 on success and negative on failure.
*/
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
index 8680ee8f65..6dbec92745 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
@@ -18,7 +18,7 @@
/*
* Structure for the flow database resource information
- * The below structure is based on the below paritions
+ * The below structure is based on the below partitions
* nxt_resource_idx = dir[31],resource_func_upper[30:28],nxt_resource_idx[27:0]
* If resource_func is EM_TBL then use resource_em_handle.
* Else the other part of the union is used and
diff --git a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
index bc5627ec5b..5f5b5d639e 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
@@ -185,7 +185,7 @@ ulp_ha_mgr_timer_cb(void *arg __rte_unused)
rc = ulp_ha_mgr_state_get(ulp_ctx, &curr_state);
if (rc) {
/*
- * This shouldn't happen, if it does, resetart the timer
+ * This shouldn't happen, if it does, reset the timer
* and try again next time.
*/
BNXT_TF_DBG(ERR, "Failed(%d) to get state.\n",
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 6d804c7ef9..2687a545f3 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -1010,7 +1010,7 @@ ulp_mapper_field_src_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
idx = tfp_be_to_cpu_16(idx);
- if (idx >= BNXT_ULP_CF_IDX_LAST || bytelen > sizeof(uint32_t)) {
+ if (idx >= BNXT_ULP_CF_IDX_LAST || bytelen > sizeof(uint64_t)) {
BNXT_TF_DBG(ERR, "comp field [%d] read oob %d\n", idx,
bytelen);
return -EINVAL;
@@ -1215,8 +1215,47 @@ ulp_mapper_field_src_process(struct bnxt_ulp_mapper_parms *parms,
BNXT_TF_DBG(ERR, "field port table failed\n");
return -EINVAL;
}
+ break;
+ case BNXT_ULP_FIELD_SRC_ENC_HDR_BIT:
+ if (!ulp_operand_read(field_opr,
+ (uint8_t *)&lregval, sizeof(uint64_t))) {
+ BNXT_TF_DBG(ERR, "Header bit read failed\n");
+ return -EINVAL;
+ }
+ lregval = tfp_be_to_cpu_64(lregval);
+ if (ULP_BITMAP_ISSET(parms->enc_hdr_bitmap->bits, lregval)) {
+ *val = mapper_fld_one;
+ *value = 1;
+ } else {
+ *val = mapper_fld_zeros;
+ }
+ break;
+ case BNXT_ULP_FIELD_SRC_ENC_FIELD:
+ if (!ulp_operand_read(field_opr,
+ (uint8_t *)&idx, sizeof(uint16_t))) {
+ BNXT_TF_DBG(ERR, "Header field read failed\n");
+ return -EINVAL;
+ }
+ idx = tfp_be_to_cpu_16(idx);
+ /* get the index from the global field list */
+ if (idx >= BNXT_ULP_ENC_FIELD_LAST) {
+ BNXT_TF_DBG(ERR, "invalid encap field tbl idx %d\n",
+ idx);
+ return -EINVAL;
+ }
+ buffer = parms->enc_field[idx].spec;
+ field_size = parms->enc_field[idx].size;
+ if (bytelen > field_size) {
+ BNXT_TF_DBG(ERR, "Encap field[%d] size small %u\n",
+ idx, field_size);
+ return -EINVAL;
+ }
+ *val = &buffer[field_size - bytelen];
+ break;
case BNXT_ULP_FIELD_SRC_SKIP:
/* do nothing */
+ *val = mapper_fld_zeros;
+ *val_len = 0;
break;
case BNXT_ULP_FIELD_SRC_REJECT:
return -EINVAL;
@@ -1270,6 +1309,8 @@ static int32_t ulp_mapper_field_blob_write(enum bnxt_ulp_field_src fld_src,
BNXT_TF_DBG(ERR, "encap blob push failed\n");
return -EINVAL;
}
+ } else if (fld_src == BNXT_ULP_FIELD_SRC_SKIP) {
+ /* do nothing */
} else {
if (!ulp_blob_push(blob, val, val_len)) {
BNXT_TF_DBG(ERR, "push of val1 failed\n");
@@ -1465,7 +1506,7 @@ ulp_mapper_field_opc_process(struct bnxt_ulp_mapper_parms *parms,
if (!rc) {
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
- if (fld->field_src1 != BNXT_ULP_FIELD_SRC_ZERO)
+ if (fld->field_src1 != BNXT_ULP_FIELD_SRC_ZERO && val_len)
ulp_mapper_field_dump(name, fld, blob, write_idx, val,
val_len);
#endif
@@ -1489,7 +1530,8 @@ ulp_mapper_tbl_result_build(struct bnxt_ulp_mapper_parms *parms,
const char *name)
{
struct bnxt_ulp_mapper_field_info *dflds;
- uint32_t i, num_flds = 0, encap_flds = 0;
+ uint32_t i = 0, num_flds = 0, encap_flds = 0;
+ struct ulp_blob encap_blob;
int32_t rc = 0;
/* Get the result field list */
@@ -1506,33 +1548,60 @@ ulp_mapper_tbl_result_build(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
- /* process the result fields, loop through them */
- for (i = 0; i < (num_flds + encap_flds); i++) {
- /* set the swap index if encap swap bit is enabled */
- if (parms->device_params->encap_byte_swap && encap_flds &&
- i == num_flds)
- ulp_blob_encap_swap_idx_set(data);
-
- /* Process the result fields */
+ /* process the result fields */
+ for (i = 0; i < num_flds; i++) {
rc = ulp_mapper_field_opc_process(parms, tbl->direction,
&dflds[i], data, 0, name);
if (rc) {
- BNXT_TF_DBG(ERR, "data field failed\n");
+ BNXT_TF_DBG(ERR, "result field processing failed\n");
return rc;
}
}
- /* if encap bit swap is enabled perform the bit swap */
- if (parms->device_params->encap_byte_swap && encap_flds) {
- ulp_blob_perform_encap_swap(data);
+ /* process encap fields if any */
+ if (encap_flds) {
+ uint32_t pad = 0;
+ /* Initialize the encap blob */
+ if (!tbl->record_size) {
+ BNXT_TF_DBG(ERR, "Encap tbl record size incorrect\n");
+ return -EINVAL;
+ }
+ if (!ulp_blob_init(&encap_blob,
+ ULP_BYTE_2_BITS(tbl->record_size),
+ parms->device_params->encap_byte_order)) {
+ BNXT_TF_DBG(ERR, "blob inits failed.\n");
+ return -EINVAL;
+ }
+ for (; i < encap_flds; i++) {
+ rc = ulp_mapper_field_opc_process(parms, tbl->direction,
+ &dflds[i],
+ &encap_blob, 0, name);
+ if (rc) {
+ BNXT_TF_DBG(ERR,
+ "encap field processing failed\n");
+ return rc;
+ }
+ }
+ /* add the dynamic pad push */
+ pad = ULP_BYTE_2_BITS(tbl->record_size) -
+ ulp_blob_data_len_get(&encap_blob);
+ ulp_blob_pad_push(&encap_blob, pad);
+
+ /* perform the 64 bit byte swap */
+ ulp_blob_perform_64B_byte_swap(&encap_blob);
+ /* Append encap blob to the result blob */
+ rc = ulp_blob_buffer_copy(data, &encap_blob);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "encap buffer copy failed\n");
+ return rc;
+ }
+ }
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
- BNXT_TF_DBG(INFO, "Dump after encap swap\n");
- ulp_mapper_blob_dump(data);
+ BNXT_TF_DBG(DEBUG, "Result dump\n");
+ ulp_mapper_blob_dump(data);
#endif
#endif
- }
-
return rc;
}
@@ -1934,11 +2003,14 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
- if (!ulp_blob_init(key, tbl->blob_key_bit_size, tbl->byte_order) ||
- !ulp_blob_init(mask, tbl->blob_key_bit_size, tbl->byte_order) ||
- !ulp_blob_init(&data, tbl->result_bit_size, dparms->byte_order) ||
+ if (!ulp_blob_init(key, tbl->blob_key_bit_size,
+ dparms->key_byte_order) ||
+ !ulp_blob_init(mask, tbl->blob_key_bit_size,
+ dparms->key_byte_order) ||
+ !ulp_blob_init(&data, tbl->result_bit_size,
+ dparms->result_byte_order) ||
!ulp_blob_init(&update_data, tbl->result_bit_size,
- dparms->byte_order)) {
+ dparms->result_byte_order)) {
BNXT_TF_DBG(ERR, "blob inits failed.\n");
return -EINVAL;
}
@@ -2145,9 +2217,9 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
/* Initialize the key/result blobs */
if (!ulp_blob_init(&key, tbl->blob_key_bit_size,
- tbl->byte_order) ||
+ dparms->key_byte_order) ||
!ulp_blob_init(&data, tbl->result_bit_size,
- tbl->byte_order)) {
+ dparms->result_byte_order)) {
BNXT_TF_DBG(ERR, "blob inits failed.\n");
return -EINVAL;
}
@@ -2336,7 +2408,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
/* Initialize the blob data */
if (!ulp_blob_init(&data, bit_size,
- parms->device_params->byte_order)) {
+ parms->device_params->result_byte_order)) {
BNXT_TF_DBG(ERR, "Failed to initialize index table blob\n");
return -EINVAL;
}
@@ -2627,7 +2699,7 @@ ulp_mapper_if_tbl_process(struct bnxt_ulp_mapper_parms *parms,
tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session);
/* Initialize the blob data */
if (!ulp_blob_init(&data, tbl->result_bit_size,
- parms->device_params->byte_order)) {
+ parms->device_params->result_byte_order)) {
BNXT_TF_DBG(ERR, "Failed initial index table blob\n");
return -EINVAL;
}
@@ -2658,7 +2730,7 @@ ulp_mapper_if_tbl_process(struct bnxt_ulp_mapper_parms *parms,
case BNXT_ULP_IF_TBL_OPC_RD_COMP_FIELD:
/* Initialize the result blob */
if (!ulp_blob_init(&res_blob, tbl->result_bit_size,
- parms->device_params->byte_order)) {
+ parms->device_params->result_byte_order)) {
BNXT_TF_DBG(ERR, "Failed initial result blob\n");
return -EINVAL;
}
@@ -2747,7 +2819,7 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms,
}
if (!ulp_blob_init(&key, tbl->key_bit_size,
- parms->device_params->byte_order)) {
+ parms->device_params->key_byte_order)) {
BNXT_TF_DBG(ERR, "Failed to alloc blob\n");
return -EINVAL;
}
@@ -3252,6 +3324,26 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms,
}
*res = (mtype == BNXT_ULP_FLOW_MEM_TYPE_INT) ? 1 : 0;
break;
+ case BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET:
+ if (operand < BNXT_ULP_HDR_BIT_LAST) {
+ *res = ULP_BITMAP_ISSET(parms->enc_hdr_bitmap->bits,
+ operand);
+ } else {
+ BNXT_TF_DBG(ERR, "header bit out of bounds %d\n",
+ operand);
+ rc = -EINVAL;
+ }
+ break;
+ case BNXT_ULP_COND_OPC_ENC_HDR_BIT_NOT_SET:
+ if (operand < BNXT_ULP_HDR_BIT_LAST) {
+ *res = !ULP_BITMAP_ISSET(parms->enc_hdr_bitmap->bits,
+ operand);
+ } else {
+ BNXT_TF_DBG(ERR, "header bit out of bounds %d\n",
+ operand);
+ rc = -EINVAL;
+ }
+ break;
default:
BNXT_TF_DBG(ERR, "Invalid conditional opcode %d\n", opc);
rc = -EINVAL;
@@ -3864,8 +3956,10 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
parms.act_prop = cparms->act_prop;
parms.act_bitmap = cparms->act;
parms.hdr_bitmap = cparms->hdr_bitmap;
+ parms.enc_hdr_bitmap = cparms->enc_hdr_bitmap;
parms.regfile = ®file;
parms.hdr_field = cparms->hdr_field;
+ parms.enc_field = cparms->enc_field;
parms.fld_bitmap = cparms->fld_bitmap;
parms.comp_fld = cparms->comp_fld;
parms.ulp_ctx = ulp_ctx;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
index d4d6969bb5..4d6ba0f73a 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
@@ -44,7 +44,9 @@ struct bnxt_ulp_mapper_parms {
struct ulp_rte_act_prop *act_prop;
struct ulp_rte_act_bitmap *act_bitmap;
struct ulp_rte_hdr_bitmap *hdr_bitmap;
+ struct ulp_rte_hdr_bitmap *enc_hdr_bitmap;
struct ulp_rte_hdr_field *hdr_field;
+ struct ulp_rte_hdr_field *enc_field;
struct ulp_rte_field_bitmap *fld_bitmap;
uint64_t *comp_fld;
struct ulp_regfile *regfile;
@@ -67,7 +69,9 @@ struct bnxt_ulp_mapper_parms {
struct bnxt_ulp_mapper_create_parms {
uint32_t app_priority;
struct ulp_rte_hdr_bitmap *hdr_bitmap;
+ struct ulp_rte_hdr_bitmap *enc_hdr_bitmap;
struct ulp_rte_hdr_field *hdr_field;
+ struct ulp_rte_hdr_field *enc_field;
uint64_t *comp_fld;
struct ulp_rte_act_bitmap *act;
struct ulp_rte_act_prop *act_prop;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index fadcd3873c..4e9968e5fa 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -40,6 +40,18 @@ ulp_rte_item_skip_void(const struct rte_flow_item **item, uint32_t increment)
return 0;
}
+/* Utility function to copy field spec items */
+static struct ulp_rte_hdr_field *
+ulp_rte_parser_fld_copy(struct ulp_rte_hdr_field *field,
+ const void *buffer,
+ uint32_t size)
+{
+ field->size = size;
+ memcpy(field->spec, buffer, field->size);
+ field++;
+ return field;
+}
+
/* Utility function to update the field_bitmap */
static void
ulp_rte_parser_field_bitmap_update(struct ulp_rte_parser_params *params,
@@ -883,7 +895,7 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
BNXT_ULP_HDR_BIT_II_VLAN);
inner_flag = 1;
} else {
- BNXT_TF_DBG(ERR, "Error Parsing:Vlan hdr found withtout eth\n");
+ BNXT_TF_DBG(ERR, "Error Parsing:Vlan hdr found without eth\n");
return BNXT_TF_RC_ERROR;
}
/* Update the field protocol hdr bitmap */
@@ -1726,6 +1738,184 @@ ulp_rte_rss_act_handler(const struct rte_flow_action *action_item,
return BNXT_TF_RC_SUCCESS;
}
+/* Function to handle the parsing of RTE Flow item eth Header. */
+static void
+ulp_rte_enc_eth_hdr_handler(struct ulp_rte_parser_params *params,
+ const struct rte_flow_item_eth *eth_spec)
+{
+ struct ulp_rte_hdr_field *field;
+ uint32_t size;
+
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_ETH_DMAC];
+ size = sizeof(eth_spec->dst.addr_bytes);
+ field = ulp_rte_parser_fld_copy(field, eth_spec->dst.addr_bytes, size);
+
+ size = sizeof(eth_spec->src.addr_bytes);
+ field = ulp_rte_parser_fld_copy(field, eth_spec->src.addr_bytes, size);
+
+ size = sizeof(eth_spec->type);
+ field = ulp_rte_parser_fld_copy(field, ð_spec->type, size);
+
+ ULP_BITMAP_SET(params->enc_hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_ETH);
+}
+
+/* Function to handle the parsing of RTE Flow item vlan Header. */
+static void
+ulp_rte_enc_vlan_hdr_handler(struct ulp_rte_parser_params *params,
+ const struct rte_flow_item_vlan *vlan_spec,
+ uint32_t inner)
+{
+ struct ulp_rte_hdr_field *field;
+ uint32_t size;
+
+ if (!inner) {
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_O_VLAN_TCI];
+ ULP_BITMAP_SET(params->enc_hdr_bitmap.bits,
+ BNXT_ULP_HDR_BIT_OO_VLAN);
+ } else {
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_I_VLAN_TCI];
+ ULP_BITMAP_SET(params->enc_hdr_bitmap.bits,
+ BNXT_ULP_HDR_BIT_OI_VLAN);
+ }
+
+ size = sizeof(vlan_spec->tci);
+ field = ulp_rte_parser_fld_copy(field, &vlan_spec->tci, size);
+
+ size = sizeof(vlan_spec->inner_type);
+ field = ulp_rte_parser_fld_copy(field, &vlan_spec->inner_type, size);
+}
+
+/* Function to handle the parsing of RTE Flow item ipv4 Header. */
+static void
+ulp_rte_enc_ipv4_hdr_handler(struct ulp_rte_parser_params *params,
+ const struct rte_flow_item_ipv4 *ip)
+{
+ struct ulp_rte_hdr_field *field;
+ uint32_t size;
+ uint8_t val8;
+
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_IPV4_IHL];
+ size = sizeof(ip->hdr.version_ihl);
+ if (!ip->hdr.version_ihl)
+ val8 = RTE_IPV4_VHL_DEF;
+ else
+ val8 = ip->hdr.version_ihl;
+ field = ulp_rte_parser_fld_copy(field, &val8, size);
+
+ size = sizeof(ip->hdr.type_of_service);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.type_of_service, size);
+
+ size = sizeof(ip->hdr.packet_id);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.packet_id, size);
+
+ size = sizeof(ip->hdr.fragment_offset);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.fragment_offset, size);
+
+ size = sizeof(ip->hdr.time_to_live);
+ if (!ip->hdr.time_to_live)
+ val8 = BNXT_ULP_DEFAULT_TTL;
+ else
+ val8 = ip->hdr.time_to_live;
+ field = ulp_rte_parser_fld_copy(field, &val8, size);
+
+ size = sizeof(ip->hdr.next_proto_id);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.next_proto_id, size);
+
+ size = sizeof(ip->hdr.src_addr);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.src_addr, size);
+
+ size = sizeof(ip->hdr.dst_addr);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.dst_addr, size);
+
+ ULP_BITMAP_SET(params->enc_hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV4);
+}
+
+/* Function to handle the parsing of RTE Flow item ipv6 Header. */
+static void
+ulp_rte_enc_ipv6_hdr_handler(struct ulp_rte_parser_params *params,
+ const struct rte_flow_item_ipv6 *ip)
+{
+ struct ulp_rte_hdr_field *field;
+ uint32_t size;
+ uint32_t val32;
+ uint8_t val8;
+
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW];
+ size = sizeof(ip->hdr.vtc_flow);
+ if (!ip->hdr.vtc_flow)
+ val32 = rte_cpu_to_be_32(BNXT_ULP_IPV6_DFLT_VER);
+ else
+ val32 = ip->hdr.vtc_flow;
+ field = ulp_rte_parser_fld_copy(field, &val32, size);
+
+ size = sizeof(ip->hdr.proto);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.proto, size);
+
+ size = sizeof(ip->hdr.hop_limits);
+ if (!ip->hdr.hop_limits)
+ val8 = BNXT_ULP_DEFAULT_TTL;
+ else
+ val8 = ip->hdr.hop_limits;
+ field = ulp_rte_parser_fld_copy(field, &val8, size);
+
+ size = sizeof(ip->hdr.src_addr);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.src_addr, size);
+
+ size = sizeof(ip->hdr.dst_addr);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.dst_addr, size);
+
+ ULP_BITMAP_SET(params->enc_hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV6);
+}
+
+/* Function to handle the parsing of RTE Flow item UDP Header. */
+static void
+ulp_rte_enc_udp_hdr_handler(struct ulp_rte_parser_params *params,
+ const struct rte_flow_item_udp *udp_spec)
+{
+ struct ulp_rte_hdr_field *field;
+ uint32_t size;
+ uint8_t type = IPPROTO_UDP;
+
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_UDP_SPORT];
+ size = sizeof(udp_spec->hdr.src_port);
+ field = ulp_rte_parser_fld_copy(field, &udp_spec->hdr.src_port, size);
+
+ size = sizeof(udp_spec->hdr.dst_port);
+ field = ulp_rte_parser_fld_copy(field, &udp_spec->hdr.dst_port, size);
+
+ ULP_BITMAP_SET(params->enc_hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_UDP);
+
+ /* Update thhe ip header protocol */
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_IPV4_PROTO];
+ ulp_rte_parser_fld_copy(field, &type, sizeof(type));
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_IPV6_PROTO];
+ ulp_rte_parser_fld_copy(field, &type, sizeof(type));
+}
+
+/* Function to handle the parsing of RTE Flow item vxlan Header. */
+static void
+ulp_rte_enc_vxlan_hdr_handler(struct ulp_rte_parser_params *params,
+ struct rte_flow_item_vxlan *vxlan_spec)
+{
+ struct ulp_rte_hdr_field *field;
+ uint32_t size;
+
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_VXLAN_FLAGS];
+ size = sizeof(vxlan_spec->flags);
+ field = ulp_rte_parser_fld_copy(field, &vxlan_spec->flags, size);
+
+ size = sizeof(vxlan_spec->rsvd0);
+ field = ulp_rte_parser_fld_copy(field, &vxlan_spec->rsvd0, size);
+
+ size = sizeof(vxlan_spec->vni);
+ field = ulp_rte_parser_fld_copy(field, &vxlan_spec->vni, size);
+
+ size = sizeof(vxlan_spec->rsvd1);
+ field = ulp_rte_parser_fld_copy(field, &vxlan_spec->rsvd1, size);
+
+ ULP_BITMAP_SET(params->enc_hdr_bitmap.bits, BNXT_ULP_HDR_BIT_T_VXLAN);
+}
+
/* Function to handle the parsing of RTE Flow action vxlan_encap Header. */
int32_t
ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
@@ -1733,23 +1923,14 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
{
const struct rte_flow_action_vxlan_encap *vxlan_encap;
const struct rte_flow_item *item;
- const struct rte_flow_item_eth *eth_spec;
const struct rte_flow_item_ipv4 *ipv4_spec;
const struct rte_flow_item_ipv6 *ipv6_spec;
struct rte_flow_item_vxlan vxlan_spec;
uint32_t vlan_num = 0, vlan_size = 0;
uint32_t ip_size = 0, ip_type = 0;
uint32_t vxlan_size = 0;
- uint8_t *buff;
- /* IP header per byte - ver/hlen, TOS, ID, ID, FRAG, FRAG, TTL, PROTO */
- const uint8_t def_ipv4_hdr[] = {0x45, 0x00, 0x00, 0x01, 0x00,
- 0x00, 0x40, 0x11};
- /* IPv6 header per byte - vtc-flow,flow,zero,nexthdr-ttl */
- const uint8_t def_ipv6_hdr[] = {0x60, 0x00, 0x00, 0x01, 0x00,
- 0x00, 0x11, 0xf6};
struct ulp_rte_act_bitmap *act = ¶ms->act_bitmap;
struct ulp_rte_act_prop *ap = ¶ms->act_prop;
- const uint8_t *tmp_buff;
vxlan_encap = action_item->conf;
if (!vxlan_encap) {
@@ -1771,18 +1952,10 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
BNXT_TF_DBG(ERR, "Parse Error:vxlan encap does not have eth\n");
return BNXT_TF_RC_ERROR;
}
- eth_spec = item->spec;
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC];
- ulp_encap_buffer_copy(buff,
- eth_spec->dst.addr_bytes,
- BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_DMAC,
- ULP_BUFFER_ALIGN_8_BYTE);
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC];
- ulp_encap_buffer_copy(buff,
- eth_spec->src.addr_bytes,
- BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_SMAC,
- ULP_BUFFER_ALIGN_8_BYTE);
+ /* Parse the ethernet header */
+ if (item->spec)
+ ulp_rte_enc_eth_hdr_handler(params, item->spec);
/* Goto the next item */
if (!ulp_rte_item_skip_void(&item, 1))
@@ -1791,11 +1964,8 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
/* May have vlan header */
if (item->type == RTE_FLOW_ITEM_TYPE_VLAN) {
vlan_num++;
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG];
- ulp_encap_buffer_copy(buff,
- item->spec,
- sizeof(struct rte_flow_item_vlan),
- ULP_BUFFER_ALIGN_8_BYTE);
+ if (item->spec)
+ ulp_rte_enc_vlan_hdr_handler(params, item->spec, 0);
if (!ulp_rte_item_skip_void(&item, 1))
return BNXT_TF_RC_ERROR;
@@ -1804,13 +1974,13 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
/* may have two vlan headers */
if (item->type == RTE_FLOW_ITEM_TYPE_VLAN) {
vlan_num++;
- memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG +
- sizeof(struct rte_flow_item_vlan)],
- item->spec,
- sizeof(struct rte_flow_item_vlan));
+ if (item->spec)
+ ulp_rte_enc_vlan_hdr_handler(params, item->spec, 1);
+
if (!ulp_rte_item_skip_void(&item, 1))
return BNXT_TF_RC_ERROR;
}
+
/* Update the vlan count and size of more than one */
if (vlan_num) {
vlan_size = vlan_num * sizeof(struct rte_flow_item_vlan);
@@ -1829,49 +1999,6 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
ipv4_spec = item->spec;
ip_size = BNXT_ULP_ENCAP_IPV4_SIZE;
- /* copy the ipv4 details */
- if (ulp_buffer_is_empty(&ipv4_spec->hdr.version_ihl,
- BNXT_ULP_ENCAP_IPV4_VER_HLEN_TOS)) {
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP];
- ulp_encap_buffer_copy(buff,
- def_ipv4_hdr,
- BNXT_ULP_ENCAP_IPV4_VER_HLEN_TOS +
- BNXT_ULP_ENCAP_IPV4_ID_PROTO,
- ULP_BUFFER_ALIGN_8_BYTE);
- } else {
- /* Total length being ignored in the ip hdr. */
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP];
- tmp_buff = (const uint8_t *)&ipv4_spec->hdr.packet_id;
- ulp_encap_buffer_copy(buff,
- tmp_buff,
- BNXT_ULP_ENCAP_IPV4_ID_PROTO,
- ULP_BUFFER_ALIGN_8_BYTE);
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP +
- BNXT_ULP_ENCAP_IPV4_ID_PROTO];
- ulp_encap_buffer_copy(buff,
- &ipv4_spec->hdr.version_ihl,
- BNXT_ULP_ENCAP_IPV4_VER_HLEN_TOS,
- ULP_BUFFER_ALIGN_8_BYTE);
- }
-
- /* Update the dst ip address in ip encap buffer */
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP +
- BNXT_ULP_ENCAP_IPV4_VER_HLEN_TOS +
- BNXT_ULP_ENCAP_IPV4_ID_PROTO];
- ulp_encap_buffer_copy(buff,
- (const uint8_t *)&ipv4_spec->hdr.dst_addr,
- sizeof(ipv4_spec->hdr.dst_addr),
- ULP_BUFFER_ALIGN_8_BYTE);
-
- /* Update the src ip address */
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC +
- BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SRC -
- sizeof(ipv4_spec->hdr.src_addr)];
- ulp_encap_buffer_copy(buff,
- (const uint8_t *)&ipv4_spec->hdr.src_addr,
- sizeof(ipv4_spec->hdr.src_addr),
- ULP_BUFFER_ALIGN_8_BYTE);
-
/* Update the ip size details */
ip_size = tfp_cpu_to_be_32(ip_size);
memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ],
@@ -1885,6 +2012,8 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
/* update the computed field to notify it is ipv4 header */
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG,
1);
+ if (ipv4_spec)
+ ulp_rte_enc_ipv4_hdr_handler(params, ipv4_spec);
if (!ulp_rte_item_skip_void(&item, 1))
return BNXT_TF_RC_ERROR;
@@ -1892,47 +2021,6 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
ipv6_spec = item->spec;
ip_size = BNXT_ULP_ENCAP_IPV6_SIZE;
- /* copy the ipv6 details */
- tmp_buff = (const uint8_t *)&ipv6_spec->hdr.vtc_flow;
- if (ulp_buffer_is_empty(tmp_buff,
- BNXT_ULP_ENCAP_IPV6_VTC_FLOW)) {
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP];
- ulp_encap_buffer_copy(buff,
- def_ipv6_hdr,
- sizeof(def_ipv6_hdr),
- ULP_BUFFER_ALIGN_8_BYTE);
- } else {
- /* The payload length being ignored in the ip hdr. */
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP];
- tmp_buff = (const uint8_t *)&ipv6_spec->hdr.proto;
- ulp_encap_buffer_copy(buff,
- tmp_buff,
- BNXT_ULP_ENCAP_IPV6_PROTO_TTL,
- ULP_BUFFER_ALIGN_8_BYTE);
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP +
- BNXT_ULP_ENCAP_IPV6_PROTO_TTL +
- BNXT_ULP_ENCAP_IPV6_DO];
- tmp_buff = (const uint8_t *)&ipv6_spec->hdr.vtc_flow;
- ulp_encap_buffer_copy(buff,
- tmp_buff,
- BNXT_ULP_ENCAP_IPV6_VTC_FLOW,
- ULP_BUFFER_ALIGN_8_BYTE);
- }
- /* Update the dst ip address in ip encap buffer */
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP +
- sizeof(def_ipv6_hdr)];
- ulp_encap_buffer_copy(buff,
- (const uint8_t *)ipv6_spec->hdr.dst_addr,
- sizeof(ipv6_spec->hdr.dst_addr),
- ULP_BUFFER_ALIGN_8_BYTE);
-
- /* Update the src ip address */
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC];
- ulp_encap_buffer_copy(buff,
- (const uint8_t *)ipv6_spec->hdr.src_addr,
- sizeof(ipv6_spec->hdr.src_addr),
- ULP_BUFFER_ALIGN_16_BYTE);
-
/* Update the ip size details */
ip_size = tfp_cpu_to_be_32(ip_size);
memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ],
@@ -1946,6 +2034,8 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
/* update the computed field to notify it is ipv6 header */
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG,
1);
+ if (ipv6_spec)
+ ulp_rte_enc_ipv6_hdr_handler(params, ipv6_spec);
if (!ulp_rte_item_skip_void(&item, 1))
return BNXT_TF_RC_ERROR;
@@ -1959,10 +2049,8 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
BNXT_TF_DBG(ERR, "vxlan encap does not have udp\n");
return BNXT_TF_RC_ERROR;
}
- /* copy the udp details */
- ulp_encap_buffer_copy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP],
- item->spec, BNXT_ULP_ENCAP_UDP_SIZE,
- ULP_BUFFER_ALIGN_8_BYTE);
+ if (item->spec)
+ ulp_rte_enc_udp_hdr_handler(params, item->spec);
if (!ulp_rte_item_skip_void(&item, 1))
return BNXT_TF_RC_ERROR;
@@ -1976,21 +2064,12 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
/* copy the vxlan details */
memcpy(&vxlan_spec, item->spec, vxlan_size);
vxlan_spec.flags = 0x08;
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN];
- if (ip_type == rte_cpu_to_be_32(BNXT_ULP_ETH_IPV4)) {
- ulp_encap_buffer_copy(buff, (const uint8_t *)&vxlan_spec,
- vxlan_size, ULP_BUFFER_ALIGN_8_BYTE);
- } else {
- ulp_encap_buffer_copy(buff, (const uint8_t *)&vxlan_spec,
- vxlan_size / 2, ULP_BUFFER_ALIGN_8_BYTE);
- ulp_encap_buffer_copy(buff + (vxlan_size / 2),
- (const uint8_t *)&vxlan_spec.vni,
- vxlan_size / 2, ULP_BUFFER_ALIGN_8_BYTE);
- }
vxlan_size = tfp_cpu_to_be_32(vxlan_size);
memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ],
&vxlan_size, sizeof(uint32_t));
+ ulp_rte_enc_vxlan_hdr_handler(params, &vxlan_spec);
+
/* update the hdr_bitmap with vxlan */
ULP_BITMAP_SET(act->bits, BNXT_ULP_ACT_BIT_VXLAN_ENCAP);
return BNXT_TF_RC_SUCCESS;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
index 673172c811..e14f86278a 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
@@ -33,8 +33,10 @@
#define BNXT_ULP_GET_IPV6_FLOWLABEL(vtcf) \
((vtcf) & BNXT_ULP_PARSER_IPV6_FLOW_LABEL)
#define BNXT_ULP_PARSER_IPV6_VER_MASK 0xf0000000
+#define BNXT_ULP_IPV6_DFLT_VER 0x60000000
#define BNXT_ULP_PARSER_IPV6_TC 0x0ff00000
#define BNXT_ULP_PARSER_IPV6_FLOW_LABEL 0x000fffff
+#define BNXT_ULP_DEFAULT_TTL 64
enum bnxt_ulp_prsr_action {
ULP_PRSR_ACT_DEFAULT = 0,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index 2685e63432..904763f27d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -30,6 +30,7 @@
#define BNXT_ULP_PROTO_HDR_GRE_NUM 6
#define BNXT_ULP_PROTO_HDR_ICMP_NUM 5
#define BNXT_ULP_PROTO_HDR_MAX 128
+#define BNXT_ULP_PROTO_HDR_ENCAP_MAX 64
#define BNXT_ULP_PROTO_HDR_FIELD_SVIF_IDX 1
/* Direction attributes */
@@ -64,12 +65,13 @@ struct ulp_rte_act_prop {
/* Structure to be used for passing all the parser functions */
struct ulp_rte_parser_params {
- STAILQ_ENTRY(ulp_rte_parser_params) next;
struct ulp_rte_hdr_bitmap hdr_bitmap;
+ struct ulp_rte_hdr_bitmap enc_hdr_bitmap;
struct ulp_rte_hdr_bitmap hdr_fp_bit;
struct ulp_rte_field_bitmap fld_bitmap;
struct ulp_rte_field_bitmap fld_s_bitmap;
struct ulp_rte_hdr_field hdr_field[BNXT_ULP_PROTO_HDR_MAX];
+ struct ulp_rte_hdr_field enc_field[BNXT_ULP_PROTO_HDR_ENCAP_MAX];
uint64_t comp_fld[BNXT_ULP_CF_IDX_LAST];
uint32_t field_idx;
struct ulp_rte_act_bitmap act_bitmap;
@@ -207,7 +209,9 @@ struct bnxt_ulp_template_device_tbls {
/* Device specific parameters */
struct bnxt_ulp_device_params {
uint8_t description[16];
- enum bnxt_ulp_byte_order byte_order;
+ enum bnxt_ulp_byte_order key_byte_order;
+ enum bnxt_ulp_byte_order result_byte_order;
+ enum bnxt_ulp_byte_order encap_byte_order;
uint8_t encap_byte_swap;
uint8_t num_phy_ports;
uint32_t mark_db_lfid_entries;
@@ -254,7 +258,6 @@ struct bnxt_ulp_mapper_tbl_info {
uint8_t direction;
enum bnxt_ulp_pri_opc pri_opcode;
uint32_t pri_operand;
- enum bnxt_ulp_byte_order byte_order;
/* conflict resolution opcode */
enum bnxt_ulp_accept_opc accept_opcode;
@@ -267,6 +270,7 @@ struct bnxt_ulp_mapper_tbl_info {
uint16_t key_num_fields;
/* Size of the blob that holds the key */
uint16_t blob_key_bit_size;
+ uint16_t record_size;
/* Information for accessing the ulp_class_result_field_list */
uint32_t result_start_idx;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c
index 1649e157f2..fc4f435c97 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c
@@ -62,7 +62,7 @@ ulp_regfile_read(struct ulp_regfile *regfile,
* data [in] The value is written into this variable. It is going to be in the
* same byte order as it was written.
*
- * size [in] The size in bytes of the value beingritten into this
+ * size [in] The size in bytes of the value being written into this
* variable.
*
* returns 0 on success
@@ -295,7 +295,7 @@ ulp_blob_push(struct ulp_blob *blob,
datalen,
data);
if (!rc) {
- BNXT_TF_DBG(ERR, "Failed ro write blob\n");
+ BNXT_TF_DBG(ERR, "Failed to write blob\n");
return 0;
}
blob->write_idx += datalen;
@@ -355,7 +355,7 @@ ulp_blob_insert(struct ulp_blob *blob, uint32_t offset,
datalen,
data);
if (!rc) {
- BNXT_TF_DBG(ERR, "Failed ro write blob\n");
+ BNXT_TF_DBG(ERR, "Failed to write blob\n");
return 0;
}
/* copy the previously stored data */
@@ -409,7 +409,7 @@ ulp_blob_push_64(struct ulp_blob *blob,
*
* data [in] 32-bit value to be added to the blob.
*
- * datalen [in] The number of bits to be added ot the blob.
+ * datalen [in] The number of bits to be added to the blob.
*
* The offset of the data is updated after each push of data.
* NULL returned on error, pointer pushed value otherwise.
@@ -987,6 +987,33 @@ ulp_blob_append(struct ulp_blob *dst, struct ulp_blob *src,
return 0;
}
+/*
+ * Perform the blob buffer copy.
+ * This api makes the src blob merged to the dst blob.
+ *
+ * dst [in] The destination blob, the blob to be merged.
+ * src [in] The src blob.
+ *
+ * returns 0 on success.
+ */
+int32_t
+ulp_blob_buffer_copy(struct ulp_blob *dst, struct ulp_blob *src)
+{
+ if ((dst->write_idx + src->write_idx) > dst->bitlen) {
+ BNXT_TF_DBG(ERR, "source buffer too large\n");
+ return -EINVAL;
+ }
+ if (ULP_BITS_IS_BYTE_NOT_ALIGNED(dst->write_idx) ||
+ ULP_BITS_IS_BYTE_NOT_ALIGNED(src->write_idx)) {
+ BNXT_TF_DBG(ERR, "source buffer is not aligned\n");
+ return -EINVAL;
+ }
+ memcpy(&dst->data[ULP_BITS_2_BYTE_NR(dst->write_idx)],
+ src->data, ULP_BITS_2_BYTE_NR(src->write_idx));
+ dst->write_idx += src->write_idx;
+ return 0;
+}
+
/*
* Read data from the operand
*
@@ -1012,44 +1039,6 @@ ulp_operand_read(uint8_t *operand,
return bytes;
}
-/*
- * copy the buffer in the encap format which is 2 bytes.
- * The MSB of the src is placed at the LSB of dst.
- *
- * dst [out] The destination buffer
- * src [in] The source buffer dst
- * size[in] size of the buffer.
- * align[in] The alignment is either 8 or 16.
- */
-void
-ulp_encap_buffer_copy(uint8_t *dst,
- const uint8_t *src,
- uint16_t size,
- uint16_t align)
-{
- uint16_t idx, tmp_size = 0;
-
- do {
- dst += tmp_size;
- src += tmp_size;
- idx = 0;
- if (size > align) {
- tmp_size = align;
- size -= align;
- } else {
- tmp_size = size;
- size = 0;
- }
- /* copy 2 bytes at a time. Write MSB to LSB */
- while ((idx + sizeof(uint16_t)) <= tmp_size) {
- memcpy(&dst[idx],
- &src[tmp_size - idx - sizeof(uint16_t)],
- sizeof(uint16_t));
- idx += sizeof(uint16_t);
- }
- } while (size);
-}
-
/*
* Check the buffer is empty
*
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.h b/drivers/net/bnxt/tf_ulp/ulp_utils.h
index e1b0e773f3..68a537fa0a 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.h
@@ -475,6 +475,18 @@ int32_t
ulp_blob_append(struct ulp_blob *dst, struct ulp_blob *src,
uint16_t src_offset, uint16_t src_len);
+/*
+ * Perform the blob buffer copy.
+ * This api makes the src blob merged to the dst blob.
+ *
+ * dst [in] The destination blob, the blob to be merged.
+ * src [in] The src blob.
+ *
+ * returns 0 on success.
+ */
+int32_t
+ulp_blob_buffer_copy(struct ulp_blob *dst, struct ulp_blob *src);
+
/*
* Read data from the operand
*
@@ -491,21 +503,6 @@ ulp_operand_read(uint8_t *operand,
uint8_t *val,
uint16_t bitlen);
-/*
- * copy the buffer in the encap format which is 2 bytes.
- * The MSB of the src is placed at the LSB of dst.
- *
- * dst [out] The destination buffer
- * src [in] The source buffer dst
- * size[in] size of the buffer.
- * align[in] The alignment is either 8 or 16.
- */
-void
-ulp_encap_buffer_copy(uint8_t *dst,
- const uint8_t *src,
- uint16_t size,
- uint16_t align);
-
/*
* Check the buffer is empty
*
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v3 08/13] net/bnxt: add wild card TCAM byte order for Thor
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 00/13] enhancements to host based flow table management Venkat Duvvuru
` (6 preceding siblings ...)
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 07/13] net/bnxt: add support for dynamic encap action Venkat Duvvuru
@ 2021-09-11 15:30 ` Venkat Duvvuru
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 09/13] net/bnxt: add flow templates " Venkat Duvvuru
` (6 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-11 15:30 UTC (permalink / raw)
To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
The wild card tcam for Thor platform is different from the profile tcam
byte order.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Shuanglin Wang <shuanglin.wang@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
.../generic_templates/ulp_template_db_tbl.c | 2 ++
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 25 +++++++++++++------
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 1 +
3 files changed, 21 insertions(+), 7 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
index b5bce6f4c7..68f1b5fd00 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
@@ -201,6 +201,7 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
.key_byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE,
.encap_byte_order = BNXT_ULP_BYTE_ORDER_BE,
+ .wc_key_byte_order = BNXT_ULP_BYTE_ORDER_BE,
.encap_byte_swap = 1,
.int_flow_db_num_entries = 16384,
.ext_flow_db_num_entries = 32768,
@@ -223,6 +224,7 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
.key_byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE,
.encap_byte_order = BNXT_ULP_BYTE_ORDER_BE,
+ .wc_key_byte_order = BNXT_ULP_BYTE_ORDER_BE,
.encap_byte_swap = 1,
.int_flow_db_num_entries = 16384,
.ext_flow_db_num_entries = 32768,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 2687a545f3..bcc089b3e1 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -1953,6 +1953,15 @@ static void ulp_mapper_wc_tcam_tbl_post_process(struct ulp_blob *blob)
#endif
}
+static int32_t ulp_mapper_tcam_is_wc_tcam(struct bnxt_ulp_mapper_tbl_info *tbl)
+{
+ if (tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM ||
+ tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM_HIGH ||
+ tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM_LOW)
+ return 1;
+ return 0;
+}
+
static int32_t
ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
struct bnxt_ulp_mapper_tbl_info *tbl)
@@ -1972,6 +1981,7 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
uint32_t hit = 0;
uint16_t tmplen = 0;
uint16_t idx;
+ enum bnxt_ulp_byte_order key_byte_order;
/* Set the key and mask to the original key and mask. */
key = &okey;
@@ -2003,10 +2013,13 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
- if (!ulp_blob_init(key, tbl->blob_key_bit_size,
- dparms->key_byte_order) ||
- !ulp_blob_init(mask, tbl->blob_key_bit_size,
- dparms->key_byte_order) ||
+ if (ulp_mapper_tcam_is_wc_tcam(tbl))
+ key_byte_order = dparms->wc_key_byte_order;
+ else
+ key_byte_order = dparms->key_byte_order;
+
+ if (!ulp_blob_init(key, tbl->blob_key_bit_size, key_byte_order) ||
+ !ulp_blob_init(mask, tbl->blob_key_bit_size, key_byte_order) ||
!ulp_blob_init(&data, tbl->result_bit_size,
dparms->result_byte_order) ||
!ulp_blob_init(&update_data, tbl->result_bit_size,
@@ -2043,9 +2056,7 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
}
/* For wild card tcam perform the post process to swap the blob */
- if (tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM ||
- tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM_HIGH ||
- tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM_LOW) {
+ if (ulp_mapper_tcam_is_wc_tcam(tbl)) {
if (dparms->dynamic_pad_en) {
/* Sets up the slices for writing to the WC TCAM */
rc = ulp_mapper_wc_tcam_tbl_dyn_post_process(dparms,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index 904763f27d..e2a4b81cec 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -212,6 +212,7 @@ struct bnxt_ulp_device_params {
enum bnxt_ulp_byte_order key_byte_order;
enum bnxt_ulp_byte_order result_byte_order;
enum bnxt_ulp_byte_order encap_byte_order;
+ enum bnxt_ulp_byte_order wc_key_byte_order;
uint8_t encap_byte_swap;
uint8_t num_phy_ports;
uint32_t mark_db_lfid_entries;
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v3 09/13] net/bnxt: add flow templates for Thor
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 00/13] enhancements to host based flow table management Venkat Duvvuru
` (7 preceding siblings ...)
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 08/13] net/bnxt: add wild card TCAM byte order for Thor Venkat Duvvuru
@ 2021-09-11 15:30 ` Venkat Duvvuru
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 10/13] net/bnxt: tf core SRAM Manager Venkat Duvvuru
` (5 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-11 15:30 UTC (permalink / raw)
To: dev; +Cc: Kishore Padmanabha, Mike Baucom, Venkat Duvvuru
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
1. Add support for egress flows with port and count action for
Thor platform.
2. Added templates to support VXLAN encapsulation feature for Thor.
3. Added support for VXLAN decap and VLAN pop actions along with
the ingress flow.
4. Added templates to enable VXLAN decap support for f1 and f2 flows.
5. Added templates Thor VF Rep support
6. Added Thor ingress mod table actions for NAT, NAPT, and TTL.
7. Added mirror/sample table support
8. Added supported for IPv6 flows for Thor.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Mike Baucom <michael.baucom@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
Reviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com>
---
drivers/net/bnxt/tf_core/tf_tcam.c | 6 +-
.../generic_templates/ulp_template_db_enum.h | 123 +-
.../generic_templates/ulp_template_db_tbl.c | 182 +-
.../ulp_template_db_thor_act.c | 4329 +-
.../ulp_template_db_thor_class.c | 44219 ++++++++++++++--
.../ulp_template_db_wh_plus_class.c | 4 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 10 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 18 +-
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 1 +
drivers/net/bnxt/tf_ulp/ulp_utils.c | 3 +
10 files changed, 44734 insertions(+), 4161 deletions(-)
diff --git a/drivers/net/bnxt/tf_core/tf_tcam.c b/drivers/net/bnxt/tf_core/tf_tcam.c
index 806af3070a..273f20858b 100644
--- a/drivers/net/bnxt/tf_core/tf_tcam.c
+++ b/drivers/net/bnxt/tf_core/tf_tcam.c
@@ -323,8 +323,12 @@ tf_tcam_alloc(struct tf *tfp,
}
/* return the start index of each row */
- if (i == 0)
+ if (parms->priority == 0) {
+ if (i == 0)
+ parms->idx = index;
+ } else {
parms->idx = index;
+ }
}
return 0;
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
index 9010d9a749..84e3d92f41 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
@@ -3,12 +3,12 @@
* All rights reserved.
*/
-/* date: Thu May 27 17:35:19 2021 */
+/* date: Tue Jul 13 12:36:40 2021 */
#ifndef ULP_TEMPLATE_DB_H_
#define ULP_TEMPLATE_DB_H_
-#define BNXT_ULP_REGFILE_MAX_SZ 40
+#define BNXT_ULP_REGFILE_MAX_SZ 42
#define BNXT_ULP_MAX_NUM_DEVICES 4
#define BNXT_ULP_LOG2_MAX_NUM_DEV 2
#define BNXT_ULP_GEN_TBL_MAX_SZ 12
@@ -27,9 +27,9 @@
#define BNXT_ULP_ACT_HID_SHFTL 26
#define BNXT_ULP_ACT_HID_MASK 2047
#define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 8
-#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 43
+#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 62
#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 50
-#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 204
+#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 206
#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 6
#define BNXT_ULP_COND_GOTO_REJECT 1023
#define BNXT_ULP_COND_GOTO_RF 0x10000
@@ -44,23 +44,23 @@
#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 618
#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 49
#define ULP_THOR_CLASS_TMPL_LIST_SIZE 6
-#define ULP_THOR_CLASS_TBL_LIST_SIZE 33
-#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 242
-#define ULP_THOR_CLASS_IDENT_LIST_SIZE 8
-#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 259
-#define ULP_THOR_CLASS_COND_LIST_SIZE 13
+#define ULP_THOR_CLASS_TBL_LIST_SIZE 114
+#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 2305
+#define ULP_THOR_CLASS_IDENT_LIST_SIZE 39
+#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1192
+#define ULP_THOR_CLASS_COND_LIST_SIZE 55
#define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7
#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 35
#define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2
#define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 1
-#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 527
+#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 536
#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 39
#define ULP_THOR_ACT_TMPL_LIST_SIZE 7
-#define ULP_THOR_ACT_TBL_LIST_SIZE 2
-#define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 0
-#define ULP_THOR_ACT_IDENT_LIST_SIZE 0
-#define ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE 18
-#define ULP_THOR_ACT_COND_LIST_SIZE 5
+#define ULP_THOR_ACT_TBL_LIST_SIZE 28
+#define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 2
+#define ULP_THOR_ACT_IDENT_LIST_SIZE 1
+#define ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE 479
+#define ULP_THOR_ACT_COND_LIST_SIZE 20
enum bnxt_ulp_act_bit {
BNXT_ULP_ACT_BIT_MARK = 0x0000000000000001,
@@ -203,7 +203,11 @@ enum bnxt_ulp_cf_idx {
BNXT_ULP_CF_IDX_TUNNEL_ID = 63,
BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID = 64,
BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID = 65,
- BNXT_ULP_CF_IDX_LAST = 66
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID = 66,
+ BNXT_ULP_CF_IDX_OI_VLAN_FB_VID = 67,
+ BNXT_ULP_CF_IDX_IO_VLAN_FB_VID = 68,
+ BNXT_ULP_CF_IDX_II_VLAN_FB_VID = 69,
+ BNXT_ULP_CF_IDX_LAST = 70
};
enum bnxt_ulp_cond_list_opc {
@@ -386,29 +390,42 @@ enum bnxt_ulp_glb_rf_idx {
BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR = 5,
BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 = 6,
BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 = 7,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0 = 8,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1 = 9,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 = 10,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 = 11,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0 = 12,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1 = 13,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 14,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 = 15,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2 = 16,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 17,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 18,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 19,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 20,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 21,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 22,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 23,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 24,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 25,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 26,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 27,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 28,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 29,
- BNXT_ULP_GLB_RF_IDX_LAST = 30
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 = 8,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 = 9,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 = 10,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 = 11,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0 = 12,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1 = 13,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 = 14,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 = 15,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 = 16,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3 = 17,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4 = 18,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0 = 19,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1 = 20,
+ BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0 = 21,
+ BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_1 = 22,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 = 23,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 = 24,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 = 25,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 26,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 = 27,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2 = 28,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 29,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 30,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 31,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 32,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 33,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 34,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 35,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 36,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 37,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 38,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 39,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 40,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 41,
+ BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID = 42,
+ BNXT_ULP_GLB_RF_IDX_LAST = 43
};
enum bnxt_ulp_hdr_type {
@@ -520,7 +537,9 @@ enum bnxt_ulp_rf_idx {
BNXT_ULP_RF_IDX_CC = 37,
BNXT_ULP_RF_IDX_CF_FLOW_SIG_ID = 38,
BNXT_ULP_RF_IDX_PHY_PORT = 39,
- BNXT_ULP_RF_IDX_LAST = 40
+ BNXT_ULP_RF_IDX_METADATA_PROF = 40,
+ BNXT_ULP_RF_IDX_MODIFY_PTR = 41,
+ BNXT_ULP_RF_IDX_LAST = 42
};
enum bnxt_ulp_shared_session {
@@ -693,6 +712,13 @@ enum bnxt_ulp_act_prop_idx {
};
enum ulp_wp_sym {
+ ULP_WP_SYM_METADATA_OP_NORMAL = 0,
+ ULP_WP_SYM_METADATA_OP_L2_HASH = 0,
+ ULP_WP_SYM_METADATA_OP_L4_HASH = 0,
+ ULP_WP_SYM_FWD_OP_BYPASS_CFA = 0,
+ ULP_WP_SYM_FWD_OP_BYPASS_CFA_ROCE = 0,
+ ULP_WP_SYM_FWD_OP_BYPASS_LKUP = 0,
+ ULP_WP_SYM_FWD_OP_NORMAL_FLOW = 0,
ULP_WP_SYM_CTXT_OPCODE_BYPASS_CFA = 0,
ULP_WP_SYM_CTXT_OPCODE_BYPASS_LKUP = 0,
ULP_WP_SYM_CTXT_OPCODE_META_UPDATE = 0,
@@ -843,6 +869,10 @@ enum ulp_wp_sym {
ULP_WP_SYM_L4_HDR_IS_UDP_TCP_YES = 1,
ULP_WP_SYM_POP_VLAN_NO = 0,
ULP_WP_SYM_POP_VLAN_YES = 1,
+ ULP_WP_SYM_VLAN_DEL_RPT_DISABLED = 0,
+ ULP_WP_SYM_VLAN_DEL_RPT_STRIP_OUTER = 0,
+ ULP_WP_SYM_VLAN_DEL_RPT_STRIP_BOTH = 0,
+ ULP_WP_SYM_VLAN_DEL_RPT_DYN_STRIP = 0,
ULP_WP_SYM_DECAP_FUNC_NONE = 0,
ULP_WP_SYM_DECAP_FUNC_THRU_TL2 = 3,
ULP_WP_SYM_DECAP_FUNC_THRU_TL3 = 8,
@@ -916,6 +946,13 @@ enum ulp_wp_sym {
};
enum ulp_thor_sym {
+ ULP_THOR_SYM_METADATA_OP_NORMAL = 0,
+ ULP_THOR_SYM_METADATA_OP_L2_HASH = 1,
+ ULP_THOR_SYM_METADATA_OP_L4_HASH = 2,
+ ULP_THOR_SYM_FWD_OP_BYPASS_CFA = 0,
+ ULP_THOR_SYM_FWD_OP_BYPASS_CFA_ROCE = 1,
+ ULP_THOR_SYM_FWD_OP_BYPASS_LKUP = 2,
+ ULP_THOR_SYM_FWD_OP_NORMAL_FLOW = 3,
ULP_THOR_SYM_CTXT_OPCODE_BYPASS_CFA = 0,
ULP_THOR_SYM_CTXT_OPCODE_BYPASS_LKUP = 1,
ULP_THOR_SYM_CTXT_OPCODE_META_UPDATE = 2,
@@ -1066,6 +1103,10 @@ enum ulp_thor_sym {
ULP_THOR_SYM_L4_HDR_IS_UDP_TCP_YES = 1,
ULP_THOR_SYM_POP_VLAN_NO = 0,
ULP_THOR_SYM_POP_VLAN_YES = 1,
+ ULP_THOR_SYM_VLAN_DEL_RPT_DISABLED = 0,
+ ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER = 1,
+ ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_BOTH = 2,
+ ULP_THOR_SYM_VLAN_DEL_RPT_DYN_STRIP = 3,
ULP_THOR_SYM_DECAP_FUNC_NONE = 0,
ULP_THOR_SYM_DECAP_FUNC_THRU_TL2 = 3,
ULP_THOR_SYM_DECAP_FUNC_THRU_TL3 = 8,
@@ -1122,7 +1163,7 @@ enum ulp_thor_sym {
ULP_THOR_SYM_ACT_REC_POP_VLAN_NO = 0,
ULP_THOR_SYM_ACT_REC_METER_EN_YES = 1,
ULP_THOR_SYM_ACT_REC_METER_EN_NO = 0,
- ULP_THOR_SYM_LOOPBACK_PORT = 3,
+ ULP_THOR_SYM_LOOPBACK_PORT = 16,
ULP_THOR_SYM_LOOPBACK_PARIF = 15,
ULP_THOR_SYM_EXT_EM_MAX_KEY_SIZE = 0,
ULP_THOR_SYM_MATCH_TYPE_EM = 0,
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
index 68f1b5fd00..3d1e95d18c 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 20 11:56:39 2021 */
+/* date: Thu Jul 8 08:44:00 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -187,6 +187,10 @@ const struct bnxt_ulp_template_device_tbls ulp_template_thor_tbls[] = {
.tmpl_list_size = ULP_THOR_ACT_TMPL_LIST_SIZE,
.tbl_list = ulp_thor_act_tbl_list,
.tbl_list_size = ULP_THOR_ACT_TBL_LIST_SIZE,
+ .key_info_list = ulp_thor_act_key_info_list,
+ .key_info_list_size = ULP_THOR_ACT_KEY_INFO_LIST_SIZE,
+ .ident_list = ulp_thor_act_ident_list,
+ .ident_list_size = ULP_THOR_ACT_IDENT_LIST_SIZE,
.cond_list = ulp_thor_act_cond_list,
.cond_list_size = ULP_THOR_ACT_COND_LIST_SIZE,
.result_field_list = ulp_thor_act_result_field_list,
@@ -202,6 +206,7 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE,
.encap_byte_order = BNXT_ULP_BYTE_ORDER_BE,
.wc_key_byte_order = BNXT_ULP_BYTE_ORDER_BE,
+ .em_byte_order = BNXT_ULP_BYTE_ORDER_LE,
.encap_byte_swap = 1,
.int_flow_db_num_entries = 16384,
.ext_flow_db_num_entries = 32768,
@@ -225,11 +230,12 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE,
.encap_byte_order = BNXT_ULP_BYTE_ORDER_BE,
.wc_key_byte_order = BNXT_ULP_BYTE_ORDER_BE,
+ .em_byte_order = BNXT_ULP_BYTE_ORDER_BE,
.encap_byte_swap = 1,
.int_flow_db_num_entries = 16384,
.ext_flow_db_num_entries = 32768,
- .mark_db_lfid_entries = 0,
- .mark_db_gfid_entries = 0,
+ .mark_db_lfid_entries = 65536,
+ .mark_db_gfid_entries = 65536,
.flow_count_db_entries = 16384,
.fdb_parent_flow_entries = 2,
.num_resources_per_flow = 8,
@@ -909,6 +915,14 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = {
{
.app_id = 0,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
@@ -941,12 +955,156 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = {
{
.app_id = 0,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
.direction = TF_DIR_RX
},
{
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
.app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1204,7 +1362,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 63
+ .count = 15
},
{
.app_id = 0,
@@ -1666,6 +1824,14 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.app_id = 0,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
.count = 200
@@ -1703,6 +1869,14 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 15232
},
{
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .count = 1
+ },
+ {
.app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
index 9faf25aaf0..223ecbf843 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Wed May 26 15:11:34 2021 */
+/* date: Thu Jul 8 08:44:00 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -15,16 +15,88 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {
/* act_tid: 1, ingress */
[1] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 2,
+ .num_tbls = 4,
.start_tbl_idx = 0,
.reject_info = {
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
.cond_start_idx = 0,
- .cond_nums = 4 }
+ .cond_nums = 0 }
+ },
+ /* act_tid: 2, ingress */
+ [2] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 6,
+ .start_tbl_idx = 4,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 3,
+ .cond_nums = 0 }
+ },
+ /* act_tid: 3, ingress */
+ [3] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 4,
+ .start_tbl_idx = 10,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 4,
+ .cond_nums = 0 }
+ },
+ /* act_tid: 4, egress */
+ [4] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 4,
+ .start_tbl_idx = 14,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 7,
+ .cond_nums = 0 }
+ },
+ /* act_tid: 5, egress */
+ [5] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 4,
+ .start_tbl_idx = 18,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 10,
+ .cond_nums = 0 }
+ },
+ /* act_tid: 6, egress */
+ [6] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 6,
+ .start_tbl_idx = 22,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 13,
+ .cond_nums = 0 }
}
};
struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
+ { /* act_tid: 1, , table: shared_mirror_record.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 0,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .key_start_idx = 0,
+ .blob_key_bit_size = 1,
+ .key_bit_size = 1,
+ .key_num_fields = 1,
+ .ident_start_idx = 0,
+ .ident_nums = 1
+ },
{ /* act_tid: 1, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
@@ -35,7 +107,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 4,
+ .cond_start_idx = 1,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
@@ -45,73 +117,4205 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.result_bit_size = 64,
.result_num_fields = 1
},
- { /* act_tid: 1, , table: int_full_act_record.0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 0,
- .cond_false_goto = 0,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 5,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 1,
- .result_bit_size = 128,
- .result_num_fields = 17
- }
-};
-
-struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = {
- /* cond_reject: thor, act_tid: 1 */
+ { /* act_tid: 1, , table: mod_record.ing_ttl */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 2,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 1,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 1, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 3,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 48,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* act_tid: 2, , table: control.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 3,
+ .cond_nums = 0 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* act_tid: 2, , table: mirror_tbl.alloc */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 3,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 65,
+ .result_bit_size = 32,
+ .result_num_fields = 5
+ },
+ { /* act_tid: 2, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 3,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 70,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 2, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 4,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 71,
+ .result_bit_size = 128,
+ .result_num_fields = 17,
+ .encap_num_fields = 0
+ },
+ { /* act_tid: 2, , table: mirror_tbl.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 4,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 88,
+ .result_bit_size = 32,
+ .result_num_fields = 5
+ },
+ { /* act_tid: 2, , table: shared_mirror_record.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 4,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .key_start_idx = 1,
+ .blob_key_bit_size = 1,
+ .key_bit_size = 1,
+ .key_num_fields = 1,
+ .result_start_idx = 93,
+ .result_bit_size = 36,
+ .result_num_fields = 2
+ },
+ { /* act_tid: 3, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 4,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 95,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 3, , table: mod_record.ing_ttl */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 5,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 96,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 3, , table: mod_record.ing_no_ttl */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 6,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 143,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 3, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 7,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 190,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* act_tid: 4, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 7,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 207,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 4, , table: int_vtag_encap_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 8,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 8,
+ .result_start_idx = 208,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 11
+ },
+ { /* act_tid: 4, , table: mod_record.dec_ttl_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 9,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 219,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 4, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 10,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 266,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* act_tid: 5, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 10,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 283,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 5, , table: mod_record.ing_ttl */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 11,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 284,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 5, , table: mod_record.ing_no_ttl */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 12,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 331,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 5, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 13,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 378,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* act_tid: 6, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 13,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 395,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 6, , table: sp_smac_ipv4.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 14,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 16,
+ .result_start_idx = 396,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 3
+ },
+ { /* act_tid: 6, , table: sp_smac_ipv6.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 15,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 32,
+ .result_start_idx = 399,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 3
+ },
+ { /* act_tid: 6, , table: int_tun_encap_record.ipv4_vxlan */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 16,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 402,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 30
+ },
+ { /* act_tid: 6, , table: int_tun_encap_record.ipv6_vxlan */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 18,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 432,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 30
+ },
+ { /* act_tid: 6, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 20,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 462,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ }
+};
+
+struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = {
+ /* cond_execute: act_tid: 1, shared_mirror_record.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+ },
+ /* cond_execute: act_tid: 1, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 1, mod_record.ing_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 2, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 3, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 3, mod_record.ing_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 3, mod_record.ing_no_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 4, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 4, int_vtag_encap_record.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
+ },
+ /* cond_execute: act_tid: 4, mod_record.dec_ttl_egr */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 5, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 5, mod_record.ing_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 5, mod_record.ing_no_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 6, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 6, sp_smac_ipv4.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG
+ },
+ /* cond_execute: act_tid: 6, sp_smac_ipv6.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG
+ },
+ /* cond_execute: act_tid: 6, int_tun_encap_record.ipv4_vxlan */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: act_tid: 6, int_tun_encap_record.ipv6_vxlan */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ }
+};
+
+struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = {
+ /* act_tid: 1, , table: shared_mirror_record.rd */
+ {
+ .field_info_mask = {
+ .description = "shared_index",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "shared_index",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff}
+ }
+ },
+ /* act_tid: 2, , table: shared_mirror_record.wr */
+ {
+ .field_info_mask = {
+ .description = "shared_index",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "shared_index",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
+ }
+ }
+};
+
+struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
+ /* act_tid: 1, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 1, , table: mod_record.ing_ttl */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ /* act_tid: 1, , table: int_full_act_record.0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr2 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_DECAP_FUNC_THRU_TUN},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_DECAP_FUNC_NONE}
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr2 = {
+ (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 2, , table: mirror_tbl.alloc */
+ {
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 13,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ignore_drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "copy_ing_or_egr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "enable",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 2, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 2, , table: int_full_act_record.0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 2, , table: mirror_tbl.wr */
+ {
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 13,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ignore_drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "copy_ing_or_egr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "enable",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 2, , table: shared_mirror_record.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "mirror_id",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
+ },
+ /* act_tid: 3, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 3, , table: mod_record.ing_ttl */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ /* act_tid: 3, , table: mod_record.ing_no_ttl */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ /* act_tid: 3, , table: int_full_act_record.0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 4, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 4, , table: int_vtag_encap_record.0 */
+ {
+ .description = "ecv_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
+ },
+ {
+ .description = "ecv_l2_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vtag_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}
+ },
+ {
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
+ },
+ {
+ .description = "vtag_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vtag_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
+ },
+ /* act_tid: 4, , table: mod_record.dec_ttl_egr */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ /* act_tid: 4, , table: int_full_act_record.0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
+ },
+ {
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 5, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 5, , table: mod_record.ing_ttl */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ /* act_tid: 5, , table: mod_record.ing_no_ttl */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ /* act_tid: 5, , table: int_full_act_record.0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 6, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 6, , table: sp_smac_ipv4.0 */
+ {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
+ },
+ {
+ .description = "ipv4_src_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 6, , table: sp_smac_ipv6.0 */
+ {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
+ },
+ {
+ .description = "ipv6_src_addr",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_SADDR & 0xff}
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 6, , table: int_tun_encap_record.ipv4_vxlan */
+ {
+ .description = "ecv_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_VALID_YES}
+ },
+ {
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
+ },
+ {
+ .description = "ecv_l2_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_L2_EN_YES}
+ },
+ {
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
+ },
+ {
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_L4_TYPE_UDP_CSUM}
+ },
+ {
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_TUN_TYPE_VXLAN}
+ },
+ {
+ .description = "enc_eth_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
+ },
+ {
+ .description = "enc_o_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_o_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_ihl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff}
+ },
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_POP_VLAN
+ .description = "enc_ipv4_tos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff}
},
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ .description = "enc_ipv4_pkt_id",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff}
},
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_VXLAN_DECAP
+ .description = "enc_ipv4_frag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff}
},
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+ .description = "enc_ipv4_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff}
},
- /* cond_execute: act_tid: 1, int_flow_counter_tbl.0 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_COUNT
- }
-};
-
-struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
- /* act_tid: 1, , table: int_flow_counter_tbl.0 */
+ .description = "enc_ipv4_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff}
+ },
{
- .description = "count",
- .field_bit_size = 64,
+ .description = "enc_ipv4_daddr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}
+ },
+ {
+ .description = "enc_ipv6_vtc",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv6_zero",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv6_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv6_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv6_daddr",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
+ },
+ {
+ .description = "enc_udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
+ },
+ {
+ .description = "enc_vxlan_flags",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}
+ },
+ {
+ .description = "enc_vxlan_rsvd0",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}
+ },
+ {
+ .description = "enc_vxlan_vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
+ },
+ {
+ .description = "enc_vxlan_rsvd1",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}
+ },
+ /* act_tid: 6, , table: int_tun_encap_record.ipv6_vxlan */
+ {
+ .description = "ecv_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_VALID_YES}
+ },
+ {
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 1, , table: int_full_act_record.0 */
{
- .description = "sp_rec_ptr",
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
+ },
+ {
+ .description = "ecv_l2_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_L2_EN_YES}
+ },
+ {
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
+ },
+ {
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_L4_TYPE_UDP_CSUM}
+ },
+ {
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_TUN_TYPE_VXLAN}
+ },
+ {
+ .description = "enc_eth_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
+ },
+ {
+ .description = "enc_o_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_o_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_ihl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv4_tos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv4_pkt_id",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv4_frag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv4_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv4_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv4_daddr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv6_vtc",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff}
+ },
+ {
+ .description = "enc_ipv6_zero",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
+ .description = "enc_ipv6_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff}
+ },
+ {
+ .description = "enc_ipv6_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff}
+ },
+ {
+ .description = "enc_ipv6_daddr",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff}
+ },
+ {
+ .description = "enc_udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
+ },
+ {
+ .description = "enc_udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
+ },
+ {
+ .description = "enc_vxlan_flags",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}
+ },
+ {
+ .description = "enc_vxlan_rsvd0",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}
+ },
+ {
+ .description = "enc_vxlan_vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
+ },
+ {
+ .description = "enc_vxlan_rsvd1",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}
+ },
+ /* act_tid: 6, , table: int_full_act_record.0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_SP_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_SP_PTR & 0xff}
+ },
+ {
.description = "encap_ptr",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
},
{
.description = "mod_rec_ptr",
@@ -164,8 +4368,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
},
{
.description = "use_default",
@@ -195,16 +4399,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "drop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "hit",
@@ -221,3 +4416,13 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
1}
}
};
+
+struct bnxt_ulp_mapper_ident_info ulp_thor_act_ident_list[] = {
+ /* act_tid: 1, , table: shared_mirror_record.rd */
+ {
+ .description = "mirror_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_MIRROR_ID_0,
+ .ident_bit_size = 4,
+ .ident_bit_pos = 32
+ }
+};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
index ea9b9773a5..bcb204ae13 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Wed May 26 15:11:34 2021 */
+/* date: Fri Jul 30 09:57:44 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -15,32 +15,52 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {
/* class_tid: 1, ingress */
[1] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 12,
+ .num_tbls = 28,
.start_tbl_idx = 0,
.reject_info = {
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 0,
- .cond_nums = 4 }
+ .cond_nums = 1 }
+ },
+ /* class_tid: 2, ingress */
+ [2] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 17,
+ .start_tbl_idx = 28,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 29,
+ .cond_nums = 0 }
+ },
+ /* class_tid: 3, egress */
+ [3] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 24,
+ .start_tbl_idx = 45,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 36,
+ .cond_nums = 0 }
},
/* class_tid: 4, ingress */
[4] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 15,
- .start_tbl_idx = 12,
+ .num_tbls = 21,
+ .start_tbl_idx = 69,
.reject_info = {
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 8,
- .cond_nums = 1 }
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 }
},
/* class_tid: 5, egress */
[5] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 6,
- .start_tbl_idx = 27,
+ .num_tbls = 24,
+ .start_tbl_idx = 90,
.reject_info = {
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 12,
- .cond_nums = 1 }
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 }
}
};
@@ -54,7 +74,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 4,
+ .cond_start_idx = 1,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
@@ -76,7 +96,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 5,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 4,
+ .cond_start_idx = 1,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
@@ -97,7 +117,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 5,
+ .cond_start_idx = 2,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
@@ -116,7 +136,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 3,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 5,
+ .cond_start_idx = 2,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
@@ -129,7 +149,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 6,
+ .cond_start_idx = 3,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
@@ -156,7 +176,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 6,
+ .cond_start_idx = 3,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
@@ -169,17 +189,28 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 1, , table: profile_tcam_cache.l3_l4_rd */
+ { /* class_tid: 1, , table: control.ipv6_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 8,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 3,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* class_tid: 1, , table: profile_tcam_cache.ipv6_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 6,
- .cond_nums = 0 },
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 4,
+ .cond_nums = 1 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
@@ -188,23 +219,41 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.key_bit_size = 14,
.key_num_fields = 3,
.ident_start_idx = 6,
- .ident_nums = 0
+ .ident_nums = 4
},
- { /* class_tid: 1, , table: control.l3_l4 */
+ { /* class_tid: 1, , table: control.ipv6_prof_cache_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 4,
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 6,
+ .cond_start_idx = 5,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 1, , table: fkb_select.l3_l4_wm */
+ { /* class_tid: 1, , table: control.v6_conflict_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 4,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 6,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .func_info = {
+ .func_opc = BNXT_ULP_FUNC_OPC_EQ,
+ .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
+ .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
+ .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
+ },
+ { /* class_tid: 1, , table: fkb_select.l2_l3_l4_v6_em */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
@@ -212,23 +261,24 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 7,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
- .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
.result_start_idx = 10,
.result_bit_size = 106,
.result_num_fields = 106
},
- { /* class_tid: 1, , table: profile_tcam.l3_l4 */
+ { /* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 7,
- .cond_nums = 0 },
+ .cond_nums = 1 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
@@ -244,11 +294,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_start_idx = 116,
.result_bit_size = 33,
.result_num_fields = 8,
- .ident_start_idx = 6,
- .ident_nums = 0
+ .ident_start_idx = 10,
+ .ident_nums = 1
},
- { /* class_tid: 1, , table: profile_tcam_cache.l3_l4_wr */
+ { /* class_tid: 1, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_RX,
@@ -256,7 +307,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 7,
+ .cond_start_idx = 8,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
@@ -269,4026 +320,39779 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 138,
.result_num_fields = 7
},
- { /* class_tid: 1, , table: wm.l3_l4 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ { /* class_tid: 1, , table: em.l2_l3_l4_v6.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_INTERNAL,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 0,
- .cond_false_goto = 0,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 7,
- .cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 8,
+ .cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
- .pri_operand = 0,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.key_start_idx = 82,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
.result_start_idx = 131,
- .result_bit_size = 38,
- .result_num_fields = 5
+ .result_bit_size = 0,
+ .result_num_fields = 6
},
- { /* class_tid: 4, , table: int_full_act_record.0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ { /* class_tid: 1, , table: profile_tcam_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 9,
+ .cond_start_idx = 8,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 136,
- .result_bit_size = 128,
- .result_num_fields = 17
+ .key_start_idx = 196,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .ident_start_idx = 11,
+ .ident_nums = 2
},
- { /* class_tid: 4, , table: port_table.wr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
+ { /* class_tid: 1, , table: control.gen_tbl_miss */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 9,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 196,
- .blob_key_bit_size = 10,
- .key_bit_size = 10,
- .key_num_fields = 1,
- .result_start_idx = 153,
- .result_bit_size = 152,
- .result_num_fields = 5
+ .cond_false_goto = 6,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 8,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ { /* class_tid: 1, , table: fkb_select.l3_l4_wm */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 9,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 197,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .ident_start_idx = 6,
- .ident_nums = 0
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 137,
+ .result_bit_size = 106,
+ .result_num_fields = 106
},
- { /* class_tid: 4, , table: control.ing_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ { /* class_tid: 1, , table: fkb_select.l3_l4_wm_vxlan */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 3,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 9,
+ .cond_start_idx = 10,
.cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 243,
+ .result_bit_size = 106,
+ .result_num_fields = 106
},
- { /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
+ { /* class_tid: 1, , table: profile_tcam.l3_l4.ip */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 11,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 199,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 349,
+ .result_bit_size = 33,
+ .result_num_fields = 8,
+ .ident_start_idx = 13,
+ .ident_nums = 0
+ },
+ { /* class_tid: 1, , table: profile_tcam.l3_l4.vxlan */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 10,
- .cond_nums = 0 },
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 13,
+ .cond_nums = 1 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 198,
- .blob_key_bit_size = 213,
- .key_bit_size = 213,
- .key_num_fields = 21,
- .result_start_idx = 158,
- .result_bit_size = 43,
- .result_num_fields = 6,
- .ident_start_idx = 6,
- .ident_nums = 1
+ .key_start_idx = 242,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 357,
+ .result_bit_size = 33,
+ .result_num_fields = 8,
+ .ident_start_idx = 13,
+ .ident_nums = 0
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
+ { /* class_tid: 1, , table: profile_tcam_cache.wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 10,
+ .cond_start_idx = 14,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 219,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .result_start_idx = 164,
- .result_bit_size = 62,
- .result_num_fields = 4
+ .key_start_idx = 285,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .result_start_idx = 365,
+ .result_bit_size = 138,
+ .result_num_fields = 7
},
- { /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+ { /* class_tid: 1, , table: wm.l3_l4.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 10,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 168,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 14,
+ .cond_nums = 3 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 288,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 372,
+ .result_bit_size = 38,
+ .result_num_fields = 5
},
- { /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
- .direction = TF_DIR_RX,
+ { /* class_tid: 1, , table: wm.l3_l4.ipv6 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 10,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 169,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 17,
+ .cond_nums = 3 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 402,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 377,
+ .result_bit_size = 38,
+ .result_num_fields = 5
},
- { /* class_tid: 4, , table: control.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ { /* class_tid: 1, , table: wm.l3.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 0,
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 10,
+ .cond_start_idx = 20,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 516,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 382,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 1, , table: wm.l3.ipv6 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 22,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 630,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 387,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 1, , table: wm.l2 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 24,
.cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 744,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 392,
+ .result_bit_size = 38,
+ .result_num_fields = 5
},
- { /* class_tid: 4, , table: int_full_act_record.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ { /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 25,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 858,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 397,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv6 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 27,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 972,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 402,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 2, , table: port_table.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 11,
+ .cond_start_idx = 29,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 170,
- .result_bit_size = 128,
- .result_num_fields = 17,
- .encap_num_fields = 0
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .key_start_idx = 1086,
+ .blob_key_bit_size = 10,
+ .key_bit_size = 10,
+ .key_num_fields = 1,
+ .ident_start_idx = 13,
+ .ident_nums = 3
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */
+ { /* class_tid: 2, , table: tunnel_cache.rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 11,
+ .cond_start_idx = 29,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 220,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .ident_start_idx = 7,
- .ident_nums = 0
+ .key_start_idx = 1087,
+ .blob_key_bit_size = 16,
+ .key_bit_size = 16,
+ .key_num_fields = 2,
+ .ident_start_idx = 16,
+ .ident_nums = 1
},
- { /* class_tid: 4, , table: control.egr_1 */
+ { /* class_tid: 2, , table: control.tunnel_cache_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 2,
+ .cond_false_goto = 3,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 11,
+ .cond_start_idx = 29,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
+ { /* class_tid: 2, , table: l2_cntxt_tcam.1 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .direction = TF_DIR_TX,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 12,
+ .cond_start_idx = 30,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT,
.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 221,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .key_start_idx = 1089,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
- .result_start_idx = 187,
+ .result_start_idx = 407,
.result_bit_size = 43,
.result_num_fields = 6,
- .ident_start_idx = 7,
+ .ident_start_idx = 17,
.ident_nums = 1
},
- { /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
- .direction = TF_DIR_TX,
+ { /* class_tid: 2, , table: tunnel_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 12,
+ .cond_start_idx = 30,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 193,
- .result_bit_size = 32,
- .result_num_fields = 1
- },
- { /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
- .direction = TF_DIR_TX,
+ .key_start_idx = 1110,
+ .blob_key_bit_size = 16,
+ .key_bit_size = 16,
+ .key_num_fields = 2,
+ .result_start_idx = 413,
+ .result_bit_size = 52,
+ .result_num_fields = 3
+ },
+ { /* class_tid: 2, , table: control.flow_type_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 0,
- .cond_false_goto = 0,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 12,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 194,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .cond_true_goto = 1,
+ .cond_false_goto = 5,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 30,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
- { /* class_tid: 5, , table: int_full_act_record.loopback */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ { /* class_tid: 2, , table: mac_addr_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 13,
+ .cond_start_idx = 31,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE,
- .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 195,
- .result_bit_size = 128,
- .result_num_fields = 17,
- .encap_num_fields = 0
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1112,
+ .blob_key_bit_size = 73,
+ .key_bit_size = 73,
+ .key_num_fields = 5,
+ .ident_start_idx = 18,
+ .ident_nums = 1
},
- { /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
- .direction = TF_DIR_TX,
+ { /* class_tid: 2, , table: control.mac_addr_cache_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 31,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 2, , table: l2_cntxt_tcam.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 13,
+ .cond_start_idx = 32,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
- .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 212,
- .result_bit_size = 32,
- .result_num_fields = 1
- },
- { /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
- .direction = TF_DIR_TX,
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .key_start_idx = 1117,
+ .blob_key_bit_size = 213,
+ .key_bit_size = 213,
+ .key_num_fields = 21,
+ .result_start_idx = 416,
+ .result_bit_size = 43,
+ .result_num_fields = 6,
+ .ident_start_idx = 19,
+ .ident_nums = 0
+ },
+ { /* class_tid: 2, , table: mac_addr_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 13,
+ .cond_start_idx = 32,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
- .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 213,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .key_start_idx = 1138,
+ .blob_key_bit_size = 73,
+ .key_bit_size = 73,
+ .key_num_fields = 5,
+ .result_start_idx = 422,
+ .result_bit_size = 62,
+ .result_num_fields = 4
},
- { /* class_tid: 5, , table: int_full_act_record.vf_ing */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 13,
+ .cond_start_idx = 32,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
- .result_start_idx = 214,
- .result_bit_size = 128,
- .result_num_fields = 17,
- .encap_num_fields = 0
+ .key_start_idx = 1143,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .ident_start_idx = 19,
+ .ident_nums = 3
+ },
+ { /* class_tid: 2, , table: control.profile_tcam_cache.f2_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 4,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 32,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 5, , table: vtag_encap_record.vfr_egr0 */
+ { /* class_tid: 2, , table: fkb_select.f2_wm */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 33,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 426,
+ .result_bit_size = 106,
+ .result_num_fields = 106
+ },
+ { /* class_tid: 2, , table: profile_tcam.f2 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 34,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 1,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 1146,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 532,
+ .result_bit_size = 33,
+ .result_num_fields = 8
+ },
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 13,
+ .cond_start_idx = 34,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1189,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .result_start_idx = 540,
+ .result_bit_size = 138,
+ .result_num_fields = 7
+ },
+ { /* class_tid: 2, , table: wm.l3_l4.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 34,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .record_size = 16,
- .result_start_idx = 231,
- .result_bit_size = 0,
- .result_num_fields = 0,
- .encap_num_fields = 11
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 1192,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 547,
+ .result_bit_size = 38,
+ .result_num_fields = 5
},
- { /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
+ { /* class_tid: 2, , table: wm.l3_l4.ipv6 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 0,
.cond_false_goto = 0,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 13,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 35,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 242,
- .result_bit_size = 128,
- .result_num_fields = 17
- }
-};
-
-struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {
- /* cond_reject: thor, class_tid: 1 */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
- .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 1306,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 552,
+ .result_bit_size = 38,
+ .result_num_fields = 5
},
- {
- .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET,
- .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC
+ { /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 6,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 36,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1420,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 22,
+ .ident_nums = 1
},
- {
- .cond_opcode = BNXT_ULP_COND_OPC_FLOW_PAT_MATCH,
- .cond_operand = 2
+ { /* class_tid: 3, , table: mac_addr_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 37,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1421,
+ .blob_key_bit_size = 73,
+ .key_bit_size = 73,
+ .key_num_fields = 5,
+ .ident_start_idx = 23,
+ .ident_nums = 1
},
- {
- .cond_opcode = BNXT_ULP_COND_OPC_FLOW_PAT_MATCH,
- .cond_operand = 3
+ { /* class_tid: 3, , table: control.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 4,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 37,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
- /* cond_execute: class_tid: 1, l2_cntxt_tcam_cache.rd */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET,
- .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC
+ { /* class_tid: 3, , table: port_table.egr.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 38,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .key_start_idx = 1426,
+ .blob_key_bit_size = 10,
+ .key_bit_size = 10,
+ .key_num_fields = 1,
+ .ident_start_idx = 24,
+ .ident_nums = 3
},
- /* cond_execute: class_tid: 1, control.0 */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
- .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ { /* class_tid: 3, , table: l2_cntxt_tcam.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 38,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .key_start_idx = 1427,
+ .blob_key_bit_size = 213,
+ .key_bit_size = 213,
+ .key_num_fields = 21,
+ .result_start_idx = 557,
+ .result_bit_size = 43,
+ .result_num_fields = 6,
+ .ident_start_idx = 27,
+ .ident_nums = 1
},
- /* cond_execute: class_tid: 1, control.l3_l4 */
- {
+ { /* class_tid: 3, , table: mac_addr_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 38,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1448,
+ .blob_key_bit_size = 73,
+ .key_bit_size = 73,
+ .key_num_fields = 5,
+ .result_start_idx = 563,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 3, , table: control.ipv6_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 8,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 38,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* class_tid: 3, , table: profile_tcam_cache.ipv6_rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 39,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1453,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .ident_start_idx = 28,
+ .ident_nums = 4
+ },
+ { /* class_tid: 3, , table: control.ipv6_prof_cache_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 40,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 3, , table: control.v6_conflict_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 4,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 41,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .func_info = {
+ .func_opc = BNXT_ULP_FUNC_OPC_EQ,
+ .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
+ .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
+ .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
+ },
+ { /* class_tid: 3, , table: fkb_select.l2_l3_l4_v6_em */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 42,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .result_start_idx = 567,
+ .result_bit_size = 106,
+ .result_num_fields = 106
+ },
+ { /* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 42,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 1456,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 673,
+ .result_bit_size = 33,
+ .result_num_fields = 8,
+ .ident_start_idx = 32,
+ .ident_nums = 1
+ },
+ { /* class_tid: 3, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 42,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1499,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .result_start_idx = 681,
+ .result_bit_size = 138,
+ .result_num_fields = 7
+ },
+ { /* class_tid: 3, , table: em.l2_l3_l4_v6.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_INTERNAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 42,
+ .cond_nums = 0 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 1502,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 688,
+ .result_bit_size = 0,
+ .result_num_fields = 6
+ },
+ { /* class_tid: 3, , table: profile_tcam_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 42,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1616,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .ident_start_idx = 33,
+ .ident_nums = 2
+ },
+ { /* class_tid: 3, , table: control.gen_tbl_miss */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 42,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 3, , table: control.conflict_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 5,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 43,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .func_info = {
+ .func_opc = BNXT_ULP_FUNC_OPC_EQ,
+ .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
+ .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
+ .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
+ },
+ { /* class_tid: 3, , table: fkb_select.l3_l4_wc */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 44,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 694,
+ .result_bit_size = 106,
+ .result_num_fields = 106
+ },
+ { /* class_tid: 3, , table: profile_tcam.l3_l4.ip */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 44,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 1619,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 800,
+ .result_bit_size = 33,
+ .result_num_fields = 8,
+ .ident_start_idx = 35,
+ .ident_nums = 0
+ },
+ { /* class_tid: 3, , table: profile_tcam.l3_l4.nonip */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 45,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 1662,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 808,
+ .result_bit_size = 33,
+ .result_num_fields = 8,
+ .ident_start_idx = 35,
+ .ident_nums = 0
+ },
+ { /* class_tid: 3, , table: profile_tcam_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 45,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1705,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .result_start_idx = 816,
+ .result_bit_size = 138,
+ .result_num_fields = 7
+ },
+ { /* class_tid: 3, , table: wm.l3_l4.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 45,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 1708,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 823,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 3, , table: wm.l3.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 47,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 1822,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 828,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 3, , table: wm.l2 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 1936,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 833,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 4, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 838,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* class_tid: 4, , table: port_table.ing_wr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2050,
+ .blob_key_bit_size = 10,
+ .key_bit_size = 10,
+ .key_num_fields = 1,
+ .result_start_idx = 855,
+ .result_bit_size = 152,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2051,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 35,
+ .ident_nums = 0
+ },
+ { /* class_tid: 4, , table: control.ing_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 48,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 2052,
+ .blob_key_bit_size = 213,
+ .key_bit_size = 213,
+ .key_num_fields = 21,
+ .result_start_idx = 860,
+ .result_bit_size = 43,
+ .result_num_fields = 6,
+ .ident_start_idx = 35,
+ .ident_nums = 1
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2073,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 866,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 870,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 871,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 4, , table: int_full_act_record.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 872,
+ .result_bit_size = 128,
+ .result_num_fields = 17,
+ .encap_num_fields = 0
+ },
+ { /* class_tid: 4, , table: port_table.egr_wr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2074,
+ .blob_key_bit_size = 10,
+ .key_bit_size = 10,
+ .key_num_fields = 1,
+ .result_start_idx = 889,
+ .result_bit_size = 152,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 4, , table: control.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 5,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 49,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd_vfr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 50,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2075,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 36,
+ .ident_nums = 0
+ },
+ { /* class_tid: 4, , table: control.egr_1 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 50,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 4, , table: ilt_tbl.egr_vfr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_ILT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 51,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .result_start_idx = 894,
+ .result_bit_size = 64,
+ .result_num_fields = 8
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 51,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2076,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 902,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 51,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2077,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 36,
+ .ident_nums = 0
+ },
+ { /* class_tid: 4, , table: control.egr_2 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 51,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 2078,
+ .blob_key_bit_size = 213,
+ .key_bit_size = 213,
+ .key_num_fields = 21,
+ .result_start_idx = 906,
+ .result_bit_size = 43,
+ .result_num_fields = 6,
+ .ident_start_idx = 36,
+ .ident_nums = 1
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2099,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 912,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 916,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 917,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 5, , table: int_full_act_record.loopback */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 918,
+ .result_bit_size = 128,
+ .result_num_fields = 17,
+ .encap_num_fields = 0
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2100,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 37,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: control.vf_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 52,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 53,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .key_start_idx = 2101,
+ .blob_key_bit_size = 213,
+ .key_bit_size = 213,
+ .key_num_fields = 21,
+ .result_start_idx = 935,
+ .result_bit_size = 43,
+ .result_num_fields = 6,
+ .ident_start_idx = 37,
+ .ident_nums = 1
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 53,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2122,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 941,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 53,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
+ .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 945,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 53,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
+ .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 946,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 5, , table: int_full_act_record.vf_ing */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 53,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
+ .result_start_idx = 947,
+ .result_bit_size = 128,
+ .result_num_fields = 17,
+ .encap_num_fields = 0
+ },
+ { /* class_tid: 5, , table: ilt_tbl.vf_ing */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_ILT,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 53,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_SVIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 964,
+ .result_bit_size = 64,
+ .result_num_fields = 8
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.rd_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 53,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2123,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 38,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: control.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 53,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 5, , table: ilt_tbl.vfr_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_ILT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .result_start_idx = 972,
+ .result_bit_size = 64,
+ .result_num_fields = 8
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2124,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 980,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 5, , table: metadata_record.vfr_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 984,
+ .result_bit_size = 16,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 5, , table: mod_record.vfr_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 985,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* class_tid: 5, , table: int_full_act_record.vfr_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 1032,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_rd_vfr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2125,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 38,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: control.ing_rd_vfr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 5,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 54,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam.vfr_ing0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 2126,
+ .blob_key_bit_size = 213,
+ .key_bit_size = 213,
+ .key_num_fields = 21,
+ .result_start_idx = 1049,
+ .result_bit_size = 43,
+ .result_num_fields = 6,
+ .ident_start_idx = 38,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: fkb_select.vfr_em */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 1055,
+ .result_bit_size = 106,
+ .result_num_fields = 106
+ },
+ { /* class_tid: 5, , table: profile_tcam.vfr_ing0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 2147,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 1161,
+ .result_bit_size = 33,
+ .result_num_fields = 8
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_wr_vfr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2190,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 38,
+ .ident_nums = 1
+ },
+ { /* class_tid: 5, , table: int_full_act_record.vfr_ing0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 1169,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* class_tid: 5, , table: em.vfr.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_INTERNAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 2191,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 1186,
+ .result_bit_size = 0,
+ .result_num_fields = 6
+ }
+};
+
+struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {
+ /* cond_reject: thor, class_tid: 1 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH
+ },
+ /* cond_execute: class_tid: 1, l2_cntxt_tcam_cache.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC
+ },
+ /* cond_execute: class_tid: 1, control.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 1, control.ipv6_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ },
+ /* cond_execute: class_tid: 1, profile_tcam_cache.ipv6_rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH
+ },
+ /* cond_execute: class_tid: 1, control.ipv6_prof_cache_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 1, control.v6_conflict_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_CC
+ },
+ /* cond_execute: class_tid: 1, profile_tcam.l2_l3_l4_v6_em */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, control.gen_tbl_miss */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 1, fkb_select.l3_l4_wm */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, fkb_select.l3_l4_wm_vxlan */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, profile_tcam.l3_l4.ip */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_O_L3
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, profile_tcam.l3_l4.vxlan */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, wm.l3_l4.ipv4 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_O_L4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, wm.l3_l4.ipv6 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_O_L4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, wm.l3.ipv4 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, wm.l3.ipv6 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, wm.l2 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, wm.l3_l4.vxlan.ipv4 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ /* cond_execute: class_tid: 1, wm.l3_l4.vxlan.ipv6 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ },
+ /* cond_execute: class_tid: 2, control.tunnel_cache_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 2, control.flow_type_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_F1
+ },
+ /* cond_execute: class_tid: 2, control.mac_addr_cache_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 2, control.profile_tcam_cache.f2_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 2, fkb_select.f2_wm */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 2, wm.l3_l4.ipv4 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ /* cond_execute: class_tid: 2, wm.l3_l4.ipv6 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ },
+ /* cond_execute: class_tid: 3, l2_cntxt_tcam_cache.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC
+ },
+ /* cond_execute: class_tid: 3, control.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 3, control.ipv6_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ },
+ /* cond_execute: class_tid: 3, profile_tcam_cache.ipv6_rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH
+ },
+ /* cond_execute: class_tid: 3, control.ipv6_prof_cache_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 3, control.v6_conflict_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_CC
+ },
+ /* cond_execute: class_tid: 3, control.gen_tbl_miss */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 3, control.conflict_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_CC
+ },
+ /* cond_execute: class_tid: 3, profile_tcam.l3_l4.ip */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_O_L3
+ },
+ /* cond_execute: class_tid: 3, wm.l3_l4.ipv4 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_O_L4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ /* cond_execute: class_tid: 3, wm.l3.ipv4 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ /* cond_execute: class_tid: 4, control.ing_0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 4, control.egr_0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
+ },
+ /* cond_execute: class_tid: 4, control.egr_1 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 4, control.egr_2 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 5, control.vf_0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 5, control.0 */
+ {
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 1, wm.l3_l4 */
+ /* cond_execute: class_tid: 5, control.ing_rd_vfr */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ }
+};
+
+struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
+ /* class_tid: 1, , table: port_table.rd */
+ {
+ .field_info_mask = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: l2_cntxt_tcam_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: mac_addr_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: l2_cntxt_tcam.0 */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 2}
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 1, , table: mac_addr_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.ipv6_rd */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_UDP}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_YES},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_NO}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: em.l2_l3_l4_v6.0 */
+ {
+ .field_info_mask = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: profile_tcam.l3_l4.ip */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_UDP}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L4_HDR_VALID_YES},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L4_HDR_VALID_IGNORE}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV4},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_YES},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_NO}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 1, , table: profile_tcam.l3_l4.vxlan */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL4_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV4},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_TL2_VTAG_PRESENT_YES},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_TL2_VTAG_PRESENT_NO}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: wm.l3_l4.ipv4 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 1, , table: wm.l3_l4.ipv6 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 1, , table: wm.l3.ipv4 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 1, , table: wm.l3.ipv6 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 1, , table: wm.l2 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv4 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv6 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 2, , table: port_table.rd */
+ {
+ .field_info_mask = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: tunnel_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_TUNNEL_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_TUNNEL_ID & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 2, , table: tunnel_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_TUNNEL_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_TUNNEL_ID & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: mac_addr_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: l2_cntxt_tcam.0 */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 2}
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 2, , table: mac_addr_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: profile_tcam.f2 */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL4_HDR_TYPE_UDP}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL4_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: wm.l3_l4.ipv4 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 2, , table: wm.l3_l4.ipv6 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: mac_addr_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: port_table.egr.rd */
+ {
+ .field_info_mask = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam.0 */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 3, , table: mac_addr_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam_cache.ipv6_rd */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_UDP}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_YES},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_NO}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: em.l2_l3_l4_v6.0 */
+ {
+ .field_info_mask = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam.l3_l4.ip */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_UDP}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV4},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_YES},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_NO}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam.l3_l4.nonip */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_YES},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_NO}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: wm.l3_l4.ipv4 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 3, , table: wm.l3.ipv4 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 3, , table: wm.l2 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 4, , table: port_table.ing_wr_0 */
+ {
+ .field_info_mask = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: port_table.egr_wr_0 */
+ {
+ .field_info_mask = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd_vfr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.rd_egr0 */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_rd_vfr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam.vfr_ing0 */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: profile_tcam.vfr_ing0 */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_wr_vfr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: em.vfr.0 */
+ {
+ .field_info_mask = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ }
+};
+
+struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
+ /* class_tid: 1, , table: l2_cntxt_tcam.0 */
+ {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ },
+ {
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ },
+ {
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ },
+ /* class_tid: 1, , table: mac_addr_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: fkb_select.l2_l3_l4_v6_em */
+ {
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "parif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "spif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "lcos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "loopback.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tuntype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tflags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tqos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "terr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ },
+ {
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ },
+ {
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ },
+ {
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}
+ },
+ {
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}
+ },
+ {
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_win.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ },
+ /* class_tid: 1, , table: em.l2_l3_l4_v6.0 */
+ {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: fkb_select.l3_l4_wm */
+ {
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "parif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "spif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "lcos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "loopback.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tuntype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tflags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tqos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "terr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_win.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: fkb_select.l3_l4_wm_vxlan */
+ {
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "parif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "spif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "lcos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "loopback.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tuntype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tflags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tqos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "terr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_win.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.l3_l4.ip */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.l3_l4.vxlan */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 & 0xff}
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ },
+ /* class_tid: 1, , table: wm.l3_l4.ipv4 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 1, , table: wm.l3_l4.ipv6 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 1, , table: wm.l3.ipv4 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 1, , table: wm.l3.ipv6 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 1, , table: wm.l2 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv4 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv6 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
+ {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 2, , table: tunnel_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ /* class_tid: 2, , table: l2_cntxt_tcam.0 */
+ {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
+ },
+ {
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ },
+ {
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ },
+ /* class_tid: 2, , table: mac_addr_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 2, , table: fkb_select.f2_wm */
+ {
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "parif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "spif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "lcos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "loopback.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tuntype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tflags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tqos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "terr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_win.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 2, , table: profile_tcam.f2 */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 & 0xff}
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ },
+ /* class_tid: 2, , table: wm.l3_l4.ipv4 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 2, , table: wm.l3_l4.ipv6 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam.0 */
+ {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}
+ },
+ {
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ },
+ {
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ },
+ /* class_tid: 3, , table: mac_addr_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 3, , table: fkb_select.l2_l3_l4_v6_em */
+ {
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "parif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "spif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "lcos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "loopback.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
{
- .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
- .cond_operand = BNXT_ULP_CF_IDX_O_L4
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_reject: thor, class_tid: 4 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
- .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: class_tid: 4, control.ing_0 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
- .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: class_tid: 4, control.egr_0 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
- .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: class_tid: 4, control.egr_1 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
- .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tuntype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tflags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tqos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "terr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ {
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ },
+ {
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ },
+ {
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_reject: thor, class_tid: 5 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
- .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
- }
-};
-
-struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
- /* class_tid: 1, , table: port_table.rd */
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
{
- .field_info_mask = {
- .description = "dev.port_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "dev.port_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
- }
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: l2_cntxt_tcam_cache.rd */
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- }
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: mac_addr_cache.rd */
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- }
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
- },
- .field_info_spec = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
- }
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
- },
- .field_info_spec = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
- }
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: l2_cntxt_tcam.0 */
{
- .field_info_mask = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}
},
{
- .field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}
},
{
- .field_info_mask = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_win.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
- },
- .field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
- }
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
- },
- .field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
- }
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- }
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 2}
- },
- .field_info_spec = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- .field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- }
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: mac_addr_cache.wr */
+ /* class_tid: 3, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- }
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .field_info_mask = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
- },
- .field_info_spec = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
- }
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "em_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
- },
- .field_info_spec = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
- }
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam_cache.l3_l4_rd */
{
- .field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "wc_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
- }
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
+ /* class_tid: 3, , table: em.l2_l3_l4_v6.0 */
{
- .field_info_mask = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
- }
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
- /* class_tid: 1, , table: profile_tcam.l3_l4 */
{
- .field_info_mask = {
- .description = "l4_hdr_is_udp_tcp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l4_hdr_is_udp_tcp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
},
{
- .field_info_mask = {
- .description = "l4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_THOR_SYM_L4_HDR_TYPE_TCP},
- .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr3 = {
- ULP_THOR_SYM_L4_HDR_TYPE_UDP}
- }
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
- },
- .field_info_spec = {
- .description = "l4_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
- },
- .field_info_spec = {
- .description = "l4_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
- }
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 3, , table: fkb_select.l3_l4_wc */
{
- .field_info_mask = {
- .description = "ieh",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "ieh",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "l3_ipv6_cmp_dst",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l3_ipv6_cmp_dst",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "parif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "spif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "l3_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "lcos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "l3_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "meta.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "l3_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_L3_HDR_VALID_YES}
- }
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "loopback.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_uc_mc_bc",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "l2_uc_mc_bc",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_hdr_type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "l2_hdr_type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "l2_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "l2_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_L2_HDR_VALID_YES}
- }
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tun_hdr_flags",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tun_hdr_flags",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tun_hdr_err",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tun_hdr_err",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tun_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "tun_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4_hdr_is_udp_tcp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl4_hdr_is_udp_tcp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl4_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "tl4_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3_ipv6_cmp_dst",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl3_ipv6_cmp_dst",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3_ipv6_cmp_src",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl3_ipv6_cmp_src",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3_hdr_isIP",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl3_hdr_isIP",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl3_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl3_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "tl3_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl2_two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl2_vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_uc_mc_bc",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl2_uc_mc_bc",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_hdr_type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl2_hdr_type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "tl2_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "hrec_next",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "hrec_next",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
- }
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "agg_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "agg_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "pkt_type_0",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "pkt_type_0",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "pkt_type_1",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "pkt_type_1",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- .field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- }
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam_cache.l3_l4_wr */
{
- .field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
- }
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
- }
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l3_l4 */
{
- .field_info_mask = {
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
- }
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
- }
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "lcos",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "lcos",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "meta",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "meta",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "rcyc_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "rcyc_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tuntype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tflags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_l2type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_l2type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tctxts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_dt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_dt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tctxt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_sa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_sa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tqos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_nvt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_nvt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "terr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "tl2_ovp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ovp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_ovd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ovd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_ovv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ovv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_ovt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ovt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_ivp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ivp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_ivd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ivd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_ivv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ivv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_ivt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ivt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.l3type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.l3type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.sip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.sip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "tl3.sip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.sip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.sip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.sip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.dip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.dip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.dip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.dip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "tl3.dip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.dip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.fid.ipv4",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.fid.ipv4",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.fid.ipv6",
- .field_bit_size = 20,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.fid.ipv6",
- .field_bit_size = 20,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.qos",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.qos",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_nonext",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_nonext",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_esp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_esp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_auth",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_auth",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.l3err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.l3err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "tl4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "tl4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_win.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tuntype",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tuntype",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tflags",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tflags",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tids",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tids",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tid",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tid",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 3, , table: profile_tcam.l3_l4.ip */
{
- .field_info_mask = {
- .description = "tctxts",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tctxts",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 & 0xff}
},
{
- .field_info_mask = {
- .description = "tctxt",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tctxt",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
},
{
- .field_info_mask = {
- .description = "tqos",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tqos",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "terr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "terr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_l2type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_l2type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_dt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_dt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 3, , table: profile_tcam.l3_l4.nonip */
{
- .field_info_mask = {
- .description = "l2_sa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_sa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 & 0xff}
},
{
- .field_info_mask = {
- .description = "l2_nvt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_nvt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
},
{
- .field_info_mask = {
- .description = "l2_ovp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ovp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "l2_ovd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ovd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ovv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ovv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ovt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ovt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ivp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ivp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ivd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ivd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 3, , table: profile_tcam_cache.wr */
{
- .field_info_mask = {
- .description = "l2_ivv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ivv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .field_info_mask = {
- .description = "l2_ivt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ivt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "l2_etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.l3type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.l3type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.sip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
- },
- .field_info_spec = {
- .description = "l3.sip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
- }
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.sip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.sip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.sip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.sip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
+ /* class_tid: 3, , table: wm.l3_l4.ipv4 */
{
- .field_info_mask = {
- .description = "l3.dip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
- },
- .field_info_spec = {
- .description = "l3.dip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
- }
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.dip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.dip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.dip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.dip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .field_info_mask = {
- .description = "l3.ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 3, , table: wm.l3.ipv4 */
{
- .field_info_mask = {
- .description = "l3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}
- }
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.fid.ipv4",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.fid.ipv4",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.fid.ipv6",
- .field_bit_size = 20,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.fid.ipv6",
- .field_bit_size = 20,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.qos",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.qos",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .field_info_mask = {
- .description = "l3.ieh_nonext",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_nonext",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 3, , table: wm.l2 */
{
- .field_info_mask = {
- .description = "l3.ieh_esp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_esp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_auth",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_auth",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .field_info_mask = {
- .description = "l3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 4, , table: int_full_act_record.0 */
{
- .field_info_mask = {
- .description = "l3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.l3err.ipv4",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.l3err.ipv4",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.l3err.ipv6",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.l3err.ipv6",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
- },
- .field_info_spec = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
- }
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
- },
- .field_info_spec = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
- }
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}
},
{
- .field_info_mask = {
- .description = "l4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.ack",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.ack",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.win",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.win",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.tsval",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.tsval",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
- {
- .field_info_mask = {
- .description = "l4.txecr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.txecr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ /* class_tid: 4, , table: port_table.ing_wr_0 */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "drv_func.mac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: port_table.wr_0 */
{
- .field_info_mask = {
- .description = "dev.port_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "dev.port_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
- }
+ .description = "drv_func.parent.mac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
- }
+ .description = "phy_port",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "default_arec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
/* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
- .field_info_mask = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
},
{
- .field_info_mask = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
{
- .field_info_mask = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
},
{
- .field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
},
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
{
- .field_info_mask = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
{
- .field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
+ /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
{
- .field_info_mask = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
+ /* class_tid: 4, , table: int_full_act_record.egr_0 */
{
- .field_info_mask = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
- }
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- .field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- }
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
- }
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
- }
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
- .field_info_mask = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 4, , table: port_table.egr_wr_0 */
{
- .field_info_mask = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "drv_func.mac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "drv_func.parent.mac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "phy_port",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "default_arec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
+ /* class_tid: 4, , table: ilt_tbl.egr_vfr */
{
- .field_info_mask = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "ilt_destination",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "fwd_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_FWD_OP_BYPASS_LKUP}
},
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
- }
+ .description = "en_ilt_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "en_bd_action",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "en_bd_meta",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "reserved",
+ .field_bit_size = 23,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
{
- .field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .field_info_mask = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- .field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- }
- }
-};
-
-struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
- /* class_tid: 1, , table: l2_cntxt_tcam.0 */
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
.description = "prof_func_id",
.field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
},
@@ -4304,8 +40108,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
.description = "ctxt_opcode",
@@ -4330,10 +40134,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
},
- /* class_tid: 1, , table: mac_addr_cache.wr */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -4347,7 +40151,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_cntxt_tcam_index",
.field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
},
{
.description = "l2_cntxt_id",
@@ -4364,461 +40171,494 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: fkb_select.l3_l4_wm */
+ /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
{
- .description = "l2_cntxt_id.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- 1}
- },
- {
- .description = "parif.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spif.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "svif.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "lcos.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "meta.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "rcyc_cnt.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
+ /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
{
- .description = "loopback.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
+ /* class_tid: 5, , table: int_full_act_record.loopback */
{
- .description = "tl2_l2type.en",
- .field_bit_size = 1,
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_dmac.en",
- .field_bit_size = 1,
+ .description = "encap_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_smac.en",
- .field_bit_size = 1,
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_dt.en",
- .field_bit_size = 1,
+ .description = "rsvd1",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_sa.en",
- .field_bit_size = 1,
+ .description = "rsvd0",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_nvt.en",
- .field_bit_size = 1,
+ .description = "decap_func",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovp.en",
- .field_bit_size = 1,
+ .description = "meter",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovd.en",
+ .description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovv.en",
- .field_bit_size = 1,
+ .description = "stats_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovt.en",
- .field_bit_size = 1,
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff,
+ ULP_THOR_SYM_LOOPBACK_PORT & 0xff}
},
{
- .description = "tl2_ivp.en",
+ .description = "use_default",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivd.en",
- .field_bit_size = 1,
+ .description = "mirror",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivv.en",
+ .description = "cond_copy",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivt.en",
- .field_bit_size = 1,
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_etype.en",
+ .description = "drop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_l3type.en",
+ .description = "hit",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_sip.en",
- .field_bit_size = 1,
+ .description = "type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
{
- .description = "tl3_sip_selcmp.en",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
},
{
- .description = "tl3_dip.en",
- .field_bit_size = 1,
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_dip_selcmp.en",
- .field_bit_size = 1,
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
{
- .description = "tl3_ttl.en",
- .field_bit_size = 1,
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
},
{
- .description = "tl3_prot.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .description = "tl3_fid.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_LOOPBACK_PARIF}
},
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
{
- .description = "tl3_qos.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "tl3_ieh_nonext.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
},
{
- .description = "tl3_ieh_esp.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .description = "tl3_ieh_auth.en",
- .field_bit_size = 1,
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
{
- .description = "tl3_ieh_dest.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
+ /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
{
- .description = "tl3_ieh_frag.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
+ /* class_tid: 5, , table: int_full_act_record.vf_ing */
{
- .description = "tl3_ieh_rthdr.en",
- .field_bit_size = 1,
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_hop.en",
- .field_bit_size = 1,
+ .description = "encap_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_1frag.en",
- .field_bit_size = 1,
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_df.en",
- .field_bit_size = 1,
+ .description = "rsvd1",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_l3err.en",
- .field_bit_size = 1,
+ .description = "rsvd0",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_l4type.en",
- .field_bit_size = 1,
+ .description = "decap_func",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_src.en",
- .field_bit_size = 1,
+ .description = "meter",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_dst.en",
+ .description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_flags.en",
- .field_bit_size = 1,
+ .description = "stats_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_seq.en",
- .field_bit_size = 1,
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}
},
{
- .description = "tl4_pa.en",
+ .description = "use_default",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_opt.en",
- .field_bit_size = 1,
+ .description = "mirror",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_tcpts.en",
+ .description = "cond_copy",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_err.en",
- .field_bit_size = 1,
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tuntype.en",
+ .description = "drop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tflags.en",
+ .description = "hit",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tids.en",
- .field_bit_size = 1,
+ .description = "type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 5, , table: ilt_tbl.vf_ing */
{
- .description = "tid.en",
- .field_bit_size = 1,
+ .description = "ilt_destination",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tctxts.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tctxt.en",
- .field_bit_size = 1,
+ .description = "fwd_op",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_FWD_OP_BYPASS_LKUP}
},
{
- .description = "tqos.en",
+ .description = "en_ilt_dest",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "terr.en",
+ .description = "en_bd_action",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_l2type.en",
+ .description = "en_bd_meta",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_dmac.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_smac.en",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 23,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: ilt_tbl.vfr_egr */
{
- .description = "l2_dt.en",
- .field_bit_size = 1,
+ .description = "ilt_destination",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_sa.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_nvt.en",
- .field_bit_size = 1,
+ .description = "fwd_op",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_FWD_OP_BYPASS_LKUP}
},
{
- .description = "l2_ovp.en",
+ .description = "en_ilt_dest",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovd.en",
+ .description = "en_bd_action",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "l2_ovv.en",
+ .description = "en_bd_meta",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovt.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivp.en",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 23,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
{
- .description = "l2_ivd.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "l2_ivv.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivt.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_etype.en",
- .field_bit_size = 1,
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: metadata_record.vfr_egr */
{
- .description = "l3_l3type.en",
- .field_bit_size = 1,
+ .description = "prof_meta_mask",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
+ /* class_tid: 5, , table: mod_record.vfr_egr */
{
- .description = "l3_sip.en",
+ .description = "metadata_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -4826,1078 +40666,1113 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
1}
},
{
- .description = "l3_sip_selcmp.en",
+ .description = "rem_ovlan",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- {
- .description = "l3_dip_selcmp.en",
+ .description = "rem_ivlan",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ttl.en",
+ .description = "rep_add_ivlan",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_prot.en",
+ .description = "rep_add_ovlan",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_fid.en",
+ .description = "ttl_update",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_qos.en",
+ .description = "tun_md_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_nonext.en",
+ .description = "reserved_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_esp.en",
+ .description = "l2_dmac_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_auth.en",
+ .description = "l2_smac_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_dest.en",
+ .description = "l3_sip_ipv6_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_frag.en",
+ .description = "l3_dip_ipv6_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_rthdr.en",
+ .description = "l3_sip_ipv4_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_hop.en",
+ .description = "l3_dip_ipv4_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_1frag.en",
+ .description = "l4_sport_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_df.en",
+ .description = "l4_dport_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_l3err.en",
- .field_bit_size = 1,
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_l4type.en",
- .field_bit_size = 1,
+ .description = "metadata_op",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_src.en",
- .field_bit_size = 1,
+ .description = "metadata_prof",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0 & 0xff}
},
{
- .description = "l4_dst.en",
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_flags.en",
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_seq.en",
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_dec",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_ack.en",
+ .description = "ttl_il3_dec",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_win.en",
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_rdir",
.field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ /* class_tid: 5, , table: int_full_act_record.vfr_egr */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_pa.en",
- .field_bit_size = 1,
+ .description = "encap_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_opt.en",
- .field_bit_size = 1,
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_tcpts.en",
- .field_bit_size = 1,
+ .description = "rsvd0",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_tsval.en",
- .field_bit_size = 1,
+ .description = "decap_func",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_txecr.en",
- .field_bit_size = 1,
+ .description = "meter",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_err.en",
+ .description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam.l3_l4 */
{
- .description = "wc_key_id",
- .field_bit_size = 6,
+ .description = "stats_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff,
+ ULP_THOR_SYM_LOOPBACK_PORT & 0xff}
},
{
- .description = "wc_search_en",
+ .description = "use_default",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_type",
- .field_bit_size = 2,
+ .description = "mirror",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 6,
+ .description = "cond_copy",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_search_en",
+ .description = "drop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "pl_byp_lkup_en",
+ .description = "hit",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam_cache.l3_l4_wr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ 1}
},
+ /* class_tid: 5, , table: l2_cntxt_tcam.vfr_ing0 */
{
- .description = "profile_tcam_index",
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 & 0xff}
+ },
+ {
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ },
+ {
+ .description = "l2_cntxt_id",
.field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
+ },
+ /* class_tid: 5, , table: fkb_select.vfr_em */
+ {
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 8,
+ .description = "parif.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "spif.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_key_id",
- .field_bit_size = 8,
+ .description = "svif.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "flow_sig_id",
- .field_bit_size = 64,
+ .description = "lcos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l3_l4 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "meta.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "loopback.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: int_full_act_record.0 */
{
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "encap_ptr",
- .field_bit_size = 16,
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd1",
- .field_bit_size = 16,
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd0",
- .field_bit_size = 8,
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "decap_func",
- .field_bit_size = 5,
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meter",
- .field_bit_size = 10,
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_op",
+ .description = "tl2_ovt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_ptr",
- .field_bit_size = 16,
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 11,
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "use_default",
+ .description = "tl2_ivv.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mirror",
- .field_bit_size = 4,
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "cond_copy",
+ .description = "tl2_etype.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drop",
+ .description = "tl3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "hit",
+ .description = "tl3_sip_selcmp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "type",
- .field_bit_size = 3,
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: port_table.wr_0 */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drv_func.mac",
- .field_bit_size = 48,
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drv_func.parent.mac",
- .field_bit_size = 48,
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "phy_port",
- .field_bit_size = 8,
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "default_arec_ptr",
- .field_bit_size = 16,
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_tcam_index",
- .field_bit_size = 10,
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: int_full_act_record.egr_0 */
{
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "encap_ptr",
- .field_bit_size = 16,
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd1",
- .field_bit_size = 16,
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd0",
- .field_bit_size = 8,
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "decap_func",
- .field_bit_size = 5,
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meter",
- .field_bit_size = 10,
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_op",
+ .description = "tuntype.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_ptr",
- .field_bit_size = 16,
+ .description = "tflags.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 11,
+ .description = "tids.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "use_default",
+ .description = "tid.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mirror",
- .field_bit_size = 4,
+ .description = "tctxts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "cond_copy",
+ .description = "tctxt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
+ .description = "tqos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drop",
+ .description = "terr.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "hit",
+ .description = "l2_l2type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "type",
- .field_bit_size = 3,
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: int_full_act_record.loopback */
{
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "encap_ptr",
- .field_bit_size = 16,
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd1",
- .field_bit_size = 16,
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd0",
- .field_bit_size = 8,
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "decap_func",
- .field_bit_size = 5,
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meter",
- .field_bit_size = 10,
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_op",
+ .description = "l3_sip_selcmp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_ptr",
- .field_bit_size = 16,
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 11,
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff,
- ULP_THOR_SYM_LOOPBACK_PORT & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "use_default",
+ .description = "l3_ttl.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mirror",
- .field_bit_size = 4,
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "cond_copy",
+ .description = "l3_fid.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drop",
+ .description = "l3_ieh_nonext.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "hit",
+ .description = "l3_ieh_esp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "type",
- .field_bit_size = 3,
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: int_full_act_record.vf_ing */
{
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "encap_ptr",
- .field_bit_size = 16,
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd1",
- .field_bit_size = 16,
+ .description = "l3_df.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd0",
- .field_bit_size = 8,
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "decap_func",
- .field_bit_size = 5,
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meter",
- .field_bit_size = 10,
+ .description = "l4_src.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_op",
+ .description = "l4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_ptr",
- .field_bit_size = 16,
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 11,
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "use_default",
+ .description = "l4_ack.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mirror",
- .field_bit_size = 4,
+ .description = "l4_win.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "cond_copy",
+ .description = "l4_pa.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drop",
+ .description = "l4_tcpts.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "hit",
+ .description = "l4_tsval.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "type",
- .field_bit_size = 3,
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: vtag_encap_record.vfr_egr0 */
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "l4_err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: profile_tcam.vfr_ing0 */
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "wc_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l2_en",
+ .description = "wc_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
- },
- {
- .description = "rsrvd",
- .field_bit_size = 1,
+ .description = "em_key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "em_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 & 0xff}
},
{
- .description = "vtag_tpid",
- .field_bit_size = 16,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- 0x81,
- 0x00}
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 & 0xff}
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "em_search_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ 1}
},
{
- .description = "vtag_de",
+ .description = "pl_byp_lkup_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- {
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
- },
- /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
+ /* class_tid: 5, , table: int_full_act_record.vfr_ing0 */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -5908,10 +41783,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "encap_ptr",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "mod_rec_ptr",
@@ -5959,10 +41831,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "vnic_or_vport",
.field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff,
- ULP_THOR_SYM_LOOPBACK_PORT & 0xff}
+ (BNXT_ULP_CF_IDX_VF_FUNC_VNIC >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_VNIC & 0xff}
},
{
.description = "use_default",
@@ -6007,6 +41879,50 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
+ },
+ /* class_tid: 5, , table: em.vfr.0 */
+ {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
};
@@ -6053,6 +41969,203 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 29
},
+ /* class_tid: 1, , table: profile_tcam_cache.ipv6_rd */
+ {
+ .description = "em_key_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_KEY_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 50
+ },
+ {
+ .description = "em_profile_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 42
+ },
+ {
+ .description = "flow_sig_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .ident_bit_size = 64,
+ .ident_bit_pos = 74
+ },
+ {
+ .description = "profile_tcam_index",
+ .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
+ },
+ /* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */
+ {
+ .description = "em_profile_id",
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_EM_PROF,
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 23
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.rd */
+ {
+ .description = "flow_sig_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .ident_bit_size = 64,
+ .ident_bit_pos = 74
+ },
+ {
+ .description = "profile_tcam_index",
+ .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
+ },
+ /* class_tid: 2, , table: port_table.rd */
+ {
+ .description = "default_arec_ptr",
+ .regfile_idx = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
+ .ident_bit_size = 16,
+ .ident_bit_pos = 136
+ },
+ {
+ .description = "drv_func.parent.mac",
+ .regfile_idx = BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC,
+ .ident_bit_size = 48,
+ .ident_bit_pos = 80
+ },
+ {
+ .description = "phy_port",
+ .regfile_idx = BNXT_ULP_RF_IDX_PHY_PORT,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 128
+ },
+ /* class_tid: 2, , table: tunnel_cache.rd */
+ {
+ .description = "l2_cntxt_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 42
+ },
+ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
+ {
+ .description = "l2_cntxt_id",
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 29
+ },
+ /* class_tid: 2, , table: mac_addr_cache.rd */
+ {
+ .description = "l2_cntxt_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 42
+ },
+ /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
+ {
+ .description = "em_profile_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 42
+ },
+ {
+ .description = "flow_sig_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .ident_bit_size = 64,
+ .ident_bit_pos = 74
+ },
+ {
+ .description = "profile_tcam_index",
+ .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ {
+ .description = "l2_cntxt_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 42
+ },
+ /* class_tid: 3, , table: mac_addr_cache.rd */
+ {
+ .description = "l2_cntxt_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 42
+ },
+ /* class_tid: 3, , table: port_table.egr.rd */
+ {
+ .description = "default_arec_ptr",
+ .regfile_idx = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
+ .ident_bit_size = 16,
+ .ident_bit_pos = 136
+ },
+ {
+ .description = "drv_func.parent.mac",
+ .regfile_idx = BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC,
+ .ident_bit_size = 48,
+ .ident_bit_pos = 80
+ },
+ {
+ .description = "phy_port",
+ .regfile_idx = BNXT_ULP_RF_IDX_PHY_PORT,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 128
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam.0 */
+ {
+ .description = "l2_cntxt_id",
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 29
+ },
+ /* class_tid: 3, , table: profile_tcam_cache.ipv6_rd */
+ {
+ .description = "em_key_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_KEY_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 50
+ },
+ {
+ .description = "em_profile_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 42
+ },
+ {
+ .description = "flow_sig_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .ident_bit_size = 64,
+ .ident_bit_pos = 74
+ },
+ {
+ .description = "profile_tcam_index",
+ .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
+ },
+ /* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */
+ {
+ .description = "em_profile_id",
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_EM_PROF,
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 23
+ },
+ /* class_tid: 3, , table: profile_tcam_cache.rd */
+ {
+ .description = "flow_sig_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .ident_bit_size = 64,
+ .ident_bit_pos = 74
+ },
+ {
+ .description = "profile_tcam_index",
+ .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
+ },
/* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
.description = "l2_cntxt_id",
@@ -6070,5 +42183,21 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 29
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
+ {
+ .description = "l2_cntxt_id",
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 29
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_wr_vfr */
+ {
+ .description = "rid",
+ .regfile_idx = BNXT_ULP_RF_IDX_RID,
+ .ident_bit_size = 32,
+ .ident_bit_pos = 0
}
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
index 7203dcf1fb..2870a0615a 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Fri May 28 16:46:46 2021 */
+/* date: Wed Jun 30 14:36:16 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -1488,7 +1488,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 47,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE,
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index bcc089b3e1..234f7ea2fa 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -2212,6 +2212,7 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
int32_t trc;
int32_t rc = 0;
int32_t pad = 0;
+ enum bnxt_ulp_byte_order key_order, res_order;
tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session);
rc = bnxt_ulp_cntxt_mem_type_get(parms->ulp_ctx, &mtype);
@@ -2226,11 +2227,12 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
+ key_order = dparms->em_byte_order;
+ res_order = dparms->em_byte_order;
+
/* Initialize the key/result blobs */
- if (!ulp_blob_init(&key, tbl->blob_key_bit_size,
- dparms->key_byte_order) ||
- !ulp_blob_init(&data, tbl->result_bit_size,
- dparms->result_byte_order)) {
+ if (!ulp_blob_init(&key, tbl->blob_key_bit_size, key_order) ||
+ !ulp_blob_init(&data, tbl->result_bit_size, res_order)) {
BNXT_TF_DBG(ERR, "blob inits failed.\n");
return -EINVAL;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index 4e9968e5fa..dce95de05c 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -826,12 +826,12 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
*/
ulp_rte_prsr_fld_mask(params, &idx, size,
&priority,
- &priority_mask,
+ (vlan_mask) ? &priority_mask : NULL,
ULP_PRSR_ACT_MASK_IGNORE);
ulp_rte_prsr_fld_mask(params, &idx, size,
&vlan_tag,
- &vlan_tag_mask,
+ (vlan_mask) ? &vlan_tag_mask : NULL,
ULP_PRSR_ACT_DEFAULT);
size = sizeof(((struct rte_flow_item_vlan *)NULL)->inner_type);
@@ -859,6 +859,10 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_ONE_VTAG, 1);
ULP_BITMAP_SET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_OO_VLAN);
+ if (vlan_mask && vlan_tag_mask)
+ ULP_COMP_FLD_IDX_WR(params,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID, 1);
+
} else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) &&
!ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_I_ETH) &&
outer_vtag_num == 1) {
@@ -870,6 +874,10 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_ONE_VTAG, 0);
ULP_BITMAP_SET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_OI_VLAN);
+ if (vlan_mask && vlan_tag_mask)
+ ULP_COMP_FLD_IDX_WR(params,
+ BNXT_ULP_CF_IDX_OI_VLAN_FB_VID, 1);
+
} else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) &&
ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_I_ETH) &&
!inner_vtag_num) {
@@ -881,6 +889,9 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_ONE_VTAG, 1);
ULP_BITMAP_SET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_IO_VLAN);
+ if (vlan_mask && vlan_tag_mask)
+ ULP_COMP_FLD_IDX_WR(params,
+ BNXT_ULP_CF_IDX_IO_VLAN_FB_VID, 1);
inner_flag = 1;
} else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) &&
ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_I_ETH) &&
@@ -893,6 +904,9 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_ONE_VTAG, 0);
ULP_BITMAP_SET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_II_VLAN);
+ if (vlan_mask && vlan_tag_mask)
+ ULP_COMP_FLD_IDX_WR(params,
+ BNXT_ULP_CF_IDX_II_VLAN_FB_VID, 1);
inner_flag = 1;
} else {
BNXT_TF_DBG(ERR, "Error Parsing:Vlan hdr found without eth\n");
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index e2a4b81cec..1683cd7ec4 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -213,6 +213,7 @@ struct bnxt_ulp_device_params {
enum bnxt_ulp_byte_order result_byte_order;
enum bnxt_ulp_byte_order encap_byte_order;
enum bnxt_ulp_byte_order wc_key_byte_order;
+ enum bnxt_ulp_byte_order em_byte_order;
uint8_t encap_byte_swap;
uint8_t num_phy_ports;
uint32_t mark_db_lfid_entries;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c
index fc4f435c97..686b80e456 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c
@@ -964,8 +964,11 @@ ulp_blob_append(struct ulp_blob *dst, struct ulp_blob *src,
ulp_bs_put_msb(dst->data, dst->write_idx,
ULP_BLOB_BYTE, bluff);
dst->write_idx += remaining;
+ src_offset += remaining;
}
+ src_buf += ULP_BITS_2_BYTE_NR(src_offset);
+
/* Push the byte aligned pieces */
for (k = 0; k < ULP_BITS_2_BYTE_NR(src_len); k++) {
ulp_bs_put_msb(dst->data, dst->write_idx, ULP_BLOB_BYTE,
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v3 10/13] net/bnxt: tf core SRAM Manager
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 00/13] enhancements to host based flow table management Venkat Duvvuru
` (8 preceding siblings ...)
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 09/13] net/bnxt: add flow templates " Venkat Duvvuru
@ 2021-09-11 15:30 ` Venkat Duvvuru
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 11/13] net/bnxt: dynamically allocate space for EM defrag function Venkat Duvvuru
` (4 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-11 15:30 UTC (permalink / raw)
To: dev; +Cc: Farah Smith
From: Farah Smith <farah.smith@broadcom.com>
Adjust info message to debug level to prevent excessive
logging.
Signed-off-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
---
drivers/net/bnxt/tf_core/tf_tbl_sram.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.c b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
index ea10afecb6..d7727f7a11 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl_sram.c
+++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
@@ -130,7 +130,7 @@ static int tf_tbl_sram_get_info(struct tf_tbl_sram_get_info_parms *parms)
if (slices)
parms->slice_size = tf_tbl_sram_slices_2_size[slices];
- TFP_DRV_LOG(INFO,
+ TFP_DRV_LOG(DEBUG,
"(%s) bank(%s) slice_size(%s)\n",
tf_tbl_type_2_str(parms->tbl_type),
tf_sram_bank_2_str(parms->bank_id),
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v3 11/13] net/bnxt: dynamically allocate space for EM defrag function
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 00/13] enhancements to host based flow table management Venkat Duvvuru
` (9 preceding siblings ...)
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 10/13] net/bnxt: tf core SRAM Manager Venkat Duvvuru
@ 2021-09-11 15:30 ` Venkat Duvvuru
2021-09-16 13:53 ` Ferruh Yigit
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 12/13] net/bnxt: sram manager shared session Venkat Duvvuru
` (3 subsequent siblings)
14 siblings, 1 reply; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-11 15:30 UTC (permalink / raw)
To: dev; +Cc: Randy Schacher
From: Randy Schacher <stuart.schacher@broadcom.com>
Alter defrag function to dynamically allocate and delete
free_list and adj_list buffers.
Signed-off-by: Randy Schacher <stuart.schacher@broadcom.com>
Reviewed-by: Peter Spreadborough <peter.spreadborough@broadcom.com>
---
drivers/net/bnxt/tf_core/dpool.c | 38 +++++++++++++++++++++-----------
1 file changed, 25 insertions(+), 13 deletions(-)
diff --git a/drivers/net/bnxt/tf_core/dpool.c b/drivers/net/bnxt/tf_core/dpool.c
index 145efa486f..5c03f775a5 100644
--- a/drivers/net/bnxt/tf_core/dpool.c
+++ b/drivers/net/bnxt/tf_core/dpool.c
@@ -7,9 +7,6 @@
#include <stdbool.h>
#include <stdint.h>
#include <errno.h>
-
-#include <rte_malloc.h>
-
#include "tfp.h"
#include "dpool.h"
@@ -84,13 +81,13 @@ static int dpool_move(struct dpool *dpool,
return 0;
}
-
int dpool_defrag(struct dpool *dpool,
uint32_t entry_size,
uint8_t defrag)
{
struct dpool_free_list *free_list;
struct dpool_adj_list *adj_list;
+ struct tfp_calloc_parms parms;
uint32_t count;
uint32_t index;
uint32_t used;
@@ -103,15 +100,31 @@ int dpool_defrag(struct dpool *dpool,
uint32_t max_size = 0;
int rc;
- free_list = rte_zmalloc("dpool_free_list",
- sizeof(struct dpool_free_list), 0);
+ parms.nitems = 1;
+ parms.size = sizeof(struct dpool_free_list);
+ parms.alignment = 0;
+
+ rc = tfp_calloc(&parms);
+
+ if (rc)
+ return rc;
+
+ free_list = (struct dpool_free_list *)parms.mem_va;
if (free_list == NULL) {
TFP_DRV_LOG(ERR, "dpool free list allocation failed\n");
return -ENOMEM;
}
- adj_list = rte_zmalloc("dpool_adjacent_list",
- sizeof(struct dpool_adj_list), 0);
+ parms.nitems = 1;
+ parms.size = sizeof(struct dpool_adj_list);
+ parms.alignment = 0;
+
+ rc = tfp_calloc(&parms);
+
+ if (rc)
+ return rc;
+
+ adj_list = (struct dpool_adj_list *)parms.mem_va;
if (adj_list == NULL) {
TFP_DRV_LOG(ERR, "dpool adjacent list allocation failed\n");
return -ENOMEM;
@@ -239,8 +252,8 @@ int dpool_defrag(struct dpool *dpool,
free_list->entry[largest_free_index].index,
max_index);
if (rc) {
- rte_free(free_list);
- rte_free(adj_list);
+ tfp_free(free_list);
+ tfp_free(adj_list);
return rc;
}
} else {
@@ -249,12 +262,11 @@ int dpool_defrag(struct dpool *dpool,
}
done:
- rte_free(free_list);
- rte_free(adj_list);
+ tfp_free(free_list);
+ tfp_free(adj_list);
return largest_free_size;
}
-
uint32_t dpool_alloc(struct dpool *dpool,
uint32_t size,
uint8_t defrag)
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* Re: [dpdk-dev] [PATCH v3 11/13] net/bnxt: dynamically allocate space for EM defrag function
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 11/13] net/bnxt: dynamically allocate space for EM defrag function Venkat Duvvuru
@ 2021-09-16 13:53 ` Ferruh Yigit
0 siblings, 0 replies; 83+ messages in thread
From: Ferruh Yigit @ 2021-09-16 13:53 UTC (permalink / raw)
To: Ajit Khaparde; +Cc: Randy Schacher, Venkat Duvvuru, dev
On 9/11/2021 4:30 PM, Venkat Duvvuru wrote:
> From: Randy Schacher <stuart.schacher@broadcom.com>
>
> Alter defrag function to dynamically allocate and delete
> free_list and adj_list buffers.
>
Can you explain a little more the reasoning/motivation/impact of the change,
why buffers are dynamically allocated, is there any impact the user application
will observe after this?
> Signed-off-by: Randy Schacher <stuart.schacher@broadcom.com>
> Reviewed-by: Peter Spreadborough <peter.spreadborough@broadcom.com>
<...>
^ permalink raw reply [flat|nested] 83+ messages in thread
* [dpdk-dev] [PATCH v3 12/13] net/bnxt: sram manager shared session
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 00/13] enhancements to host based flow table management Venkat Duvvuru
` (10 preceding siblings ...)
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 11/13] net/bnxt: dynamically allocate space for EM defrag function Venkat Duvvuru
@ 2021-09-11 15:30 ` Venkat Duvvuru
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 13/13] net/bnxt: add enhancements to TF ULP Venkat Duvvuru
` (2 subsequent siblings)
14 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-11 15:30 UTC (permalink / raw)
To: dev; +Cc: Farah Smith
From: Farah Smith <farah.smith@broadcom.com>
Fix shared session support issues due to SRAM manager
additions. Shared session does not support slices within
RM blocks. Calculate resources required without slices
and determine base addresses using old methods for the
shared session.
Signed-off-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com>
---
drivers/net/bnxt/tf_core/tf_em_internal.c | 5 +-
drivers/net/bnxt/tf_core/tf_rm.c | 134 +++++++++++++++++++---
drivers/net/bnxt/tf_core/tf_tbl_sram.c | 73 +++++++++---
3 files changed, 176 insertions(+), 36 deletions(-)
diff --git a/drivers/net/bnxt/tf_core/tf_em_internal.c b/drivers/net/bnxt/tf_core/tf_em_internal.c
index 2d57595f17..67ba011eae 100644
--- a/drivers/net/bnxt/tf_core/tf_em_internal.c
+++ b/drivers/net/bnxt/tf_core/tf_em_internal.c
@@ -326,8 +326,11 @@ tf_em_int_unbind(struct tf *tfp)
return rc;
if (!tf_session_is_shared_session(tfs)) {
- for (i = 0; i < TF_DIR_MAX; i++)
+ for (i = 0; i < TF_DIR_MAX; i++) {
+ if (tfs->em_pool[i] == NULL)
+ continue;
dpool_free_all(tfs->em_pool[i]);
+ }
}
rc = tf_session_get_db(tfp, TF_MODULE_TYPE_EM, &em_db_ptr);
diff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c
index 03c958a7d6..dd537aaece 100644
--- a/drivers/net/bnxt/tf_core/tf_rm.c
+++ b/drivers/net/bnxt/tf_core/tf_rm.c
@@ -18,6 +18,9 @@
#include "tfp.h"
#include "tf_msg.h"
+/* Logging defines */
+#define TF_RM_DEBUG 0
+
/**
* Generic RM Element data type that an RM DB is build upon.
*/
@@ -207,6 +210,45 @@ tf_rm_adjust_index(struct tf_rm_element *db,
return rc;
}
+/**
+ * Logs an array of found residual entries to the console.
+ *
+ * [in] dir
+ * Receive or transmit direction
+ *
+ * [in] module
+ * Type of Device Module
+ *
+ * [in] count
+ * Number of entries in the residual array
+ *
+ * [in] residuals
+ * Pointer to an array of residual entries. Array is index same as
+ * the DB in which this function is used. Each entry holds residual
+ * value for that entry.
+ */
+#if (TF_RM_DEBUG == 1)
+static void
+tf_rm_log_residuals(enum tf_dir dir,
+ enum tf_module_type module,
+ uint16_t count,
+ uint16_t *residuals)
+{
+ int i;
+
+ /* Walk the residual array and log the types that wasn't
+ * cleaned up to the console.
+ */
+ for (i = 0; i < count; i++) {
+ if (residuals[i] != 0)
+ TFP_DRV_LOG(INFO,
+ "%s, %s was not cleaned up, %d outstanding\n",
+ tf_dir_2_str(dir),
+ tf_module_subtype_2_str(module, i),
+ residuals[i]);
+ }
+}
+#endif /* TF_RM_DEBUG == 1 */
/**
* Performs a check of the passed in DB for any lingering elements. If
* a resource type was found to not have been cleaned up by the caller
@@ -322,6 +364,12 @@ tf_rm_check_residuals(struct tf_rm_new_db *rm_db,
*resv_size = found;
}
+#if (TF_RM_DEBUG == 1)
+ tf_rm_log_residuals(rm_db->dir,
+ rm_db->module,
+ rm_db->num_entries,
+ residuals);
+#endif
tfp_free((void *)residuals);
*resv = local_resv;
@@ -367,7 +415,8 @@ tf_rm_update_parent_reservations(struct tf *tfp,
struct tf_rm_element_cfg *cfg,
uint16_t *alloc_cnt,
uint16_t num_elements,
- uint16_t *req_cnt)
+ uint16_t *req_cnt,
+ bool shared_session)
{
int parent, child;
const char *type_str;
@@ -378,18 +427,28 @@ tf_rm_update_parent_reservations(struct tf *tfp,
/* If I am a parent */
if (cfg[parent].cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_PARENT) {
- /* start with my own count */
- RTE_ASSERT(cfg[parent].slices);
- combined_cnt =
- alloc_cnt[parent] / cfg[parent].slices;
+ uint8_t p_slices = 1;
+
+ /* Shared session doesn't support slices */
+ if (!shared_session)
+ p_slices = cfg[parent].slices;
+
+ RTE_ASSERT(p_slices);
- if (alloc_cnt[parent] % cfg[parent].slices)
+ combined_cnt = alloc_cnt[parent] / p_slices;
+
+ if (alloc_cnt[parent] % p_slices)
combined_cnt++;
if (alloc_cnt[parent]) {
dev->ops->tf_dev_get_resource_str(tfp,
cfg[parent].hcapi_type,
&type_str);
+#if (TF_RM_DEBUG == 1)
+ printf("%s:%s cnt(%d) slices(%d)\n",
+ type_str, tf_tbl_type_2_str(parent),
+ alloc_cnt[parent], p_slices);
+#endif /* (TF_RM_DEBUG == 1) */
}
/* Search again through all the elements */
@@ -399,20 +458,31 @@ tf_rm_update_parent_reservations(struct tf *tfp,
TF_RM_ELEM_CFG_HCAPI_BA_CHILD &&
cfg[child].parent_subtype == parent &&
alloc_cnt[child]) {
+ uint8_t c_slices = 1;
uint16_t cnt = 0;
- RTE_ASSERT(cfg[child].slices);
+
+ if (!shared_session)
+ c_slices = cfg[child].slices;
+
+ RTE_ASSERT(c_slices);
dev->ops->tf_dev_get_resource_str(tfp,
cfg[child].hcapi_type,
&type_str);
+#if (TF_RM_DEBUG == 1)
+ printf("%s:%s cnt(%d) slices(%d)\n",
+ type_str,
+ tf_tbl_type_2_str(child),
+ alloc_cnt[child],
+ c_slices);
+#endif /* (TF_RM_DEBUG == 1) */
/* Increment the parents combined count
* with each child's count adjusted for
- * number of slices per RM allocated item.
+ * number of slices per RM alloc item.
*/
- cnt =
- alloc_cnt[child] / cfg[child].slices;
+ cnt = alloc_cnt[child] / c_slices;
- if (alloc_cnt[child] % cfg[child].slices)
+ if (alloc_cnt[child] % c_slices)
cnt++;
combined_cnt += cnt;
@@ -422,6 +492,10 @@ tf_rm_update_parent_reservations(struct tf *tfp,
}
/* Save the parent count to be requested */
req_cnt[parent] = combined_cnt;
+#if (TF_RM_DEBUG == 1)
+ printf("%s calculated total:%d\n\n",
+ type_str, req_cnt[parent]);
+#endif /* (TF_RM_DEBUG == 1) */
}
}
return 0;
@@ -444,6 +518,7 @@ tf_rm_create_db(struct tf *tfp,
struct tf_rm_new_db *rm_db;
struct tf_rm_element *db;
uint32_t pool_size;
+ bool shared_session = 0;
TF_CHECK_PARMS2(tfp, parms);
@@ -460,7 +535,6 @@ tf_rm_create_db(struct tf *tfp,
/* Need device max number of elements for the RM QCAPS */
rc = dev->ops->tf_dev_get_max_types(tfp, &max_types);
-
/* Allocate memory for RM QCAPS request */
cparms.nitems = max_types;
cparms.size = sizeof(struct tf_rm_resc_req_entry);
@@ -496,12 +570,15 @@ tf_rm_create_db(struct tf *tfp,
tfp_memcpy(req_cnt, parms->alloc_cnt,
parms->num_elements * sizeof(uint16_t));
+ shared_session = tf_session_is_shared_session(tfs);
+
/* Update the req_cnt based upon the element configuration
*/
tf_rm_update_parent_reservations(tfp, dev, parms->cfg,
parms->alloc_cnt,
parms->num_elements,
- req_cnt);
+ req_cnt,
+ shared_session);
/* Process capabilities against DB requirements. However, as a
* DB can hold elements that are not HCAPI we can reduce the
@@ -517,6 +594,12 @@ tf_rm_create_db(struct tf *tfp,
&hcapi_items);
if (hcapi_items == 0) {
+#if (TF_RM_DEBUG == 1)
+ TFP_DRV_LOG(INFO,
+ "%s: module: %s Empty RM DB create request\n",
+ tf_dir_2_str(parms->dir),
+ tf_module_2_str(parms->module));
+#endif
parms->rm_db = NULL;
return -ENOMEM;
}
@@ -565,11 +648,11 @@ tf_rm_create_db(struct tf *tfp,
hcapi_type,
&type_str);
TFP_DRV_LOG(ERR,
- "Failure, %s:%d:%s req:%d avail:%d\n",
- tf_dir_2_str(parms->dir),
- hcapi_type, type_str,
- req_cnt[i],
- query[hcapi_type].max);
+ "Failure, %s:%d:%s req:%d avail:%d\n",
+ tf_dir_2_str(parms->dir),
+ hcapi_type, type_str,
+ req_cnt[i],
+ query[hcapi_type].max);
return -EINVAL;
}
}
@@ -689,6 +772,13 @@ tf_rm_create_db(struct tf *tfp,
rm_db->module = parms->module;
*parms->rm_db = (void *)rm_db;
+#if (TF_RM_DEBUG == 1)
+
+ printf("%s: module:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_module_2_str(parms->module));
+#endif /* (TF_RM_DEBUG == 1) */
+
tfp_free((void *)req);
tfp_free((void *)resv);
tfp_free((void *)req_cnt);
@@ -922,6 +1012,13 @@ tf_rm_create_db_no_reservation(struct tf *tfp,
rm_db->module = parms->module;
*parms->rm_db = (void *)rm_db;
+#if (TF_RM_DEBUG == 1)
+
+ printf("%s: module:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_module_2_str(parms->module));
+#endif /* (TF_RM_DEBUG == 1) */
+
tfp_free((void *)req);
tfp_free((void *)resv);
tfp_free((void *)req_cnt);
@@ -1185,7 +1282,6 @@ tf_rm_is_allocated(struct tf_rm_is_allocated_parms *parms)
cfg_type = rm_db->db[parms->subtype].cfg_type;
-
/* Bail out if not controlled by RM */
if (cfg_type != TF_RM_ELEM_CFG_HCAPI_BA &&
cfg_type != TF_RM_ELEM_CFG_HCAPI_BA_PARENT &&
diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.c b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
index d7727f7a11..167078a8c6 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl_sram.c
+++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
@@ -21,6 +21,10 @@
#define DBG_SRAM 0
+#define TF_TBL_PTR_TO_RM(new_idx, idx, base, shift) { \
+ *(new_idx) = (((idx) >> (shift)) - (base)); \
+}
+
/**
* tf_sram_tbl_get_info_parms parameter definition
*/
@@ -394,6 +398,7 @@ tf_tbl_sram_set(struct tf *tfp,
{
int rc;
bool allocated = 0;
+ int rallocated = 0;
uint16_t hcapi_type;
struct tf_rm_get_hcapi_parms hparms = { 0 };
struct tf_session *tfs;
@@ -402,7 +407,9 @@ tf_tbl_sram_set(struct tf *tfp,
void *tbl_db_ptr = NULL;
struct tf_tbl_sram_get_info_parms iparms = { 0 };
struct tf_sram_mgr_is_allocated_parms aparms = { 0 };
+ struct tf_rm_is_allocated_parms raparms = { 0 };
void *sram_handle = NULL;
+ uint16_t base = 0, shift = 0;
TF_CHECK_PARMS3(tfp, parms, parms->data);
@@ -442,23 +449,57 @@ tf_tbl_sram_set(struct tf *tfp,
return rc;
}
- aparms.sram_offset = parms->idx;
- aparms.slice_size = iparms.slice_size;
- aparms.bank_id = iparms.bank_id;
- aparms.dir = parms->dir;
- aparms.is_allocated = &allocated;
- rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
- if (rc || !allocated) {
- TFP_DRV_LOG(ERR,
- "%s: Entry not allocated:%s idx(%d):(%s)\n",
- tf_dir_2_str(parms->dir),
- tf_tbl_type_2_str(parms->type),
- parms->idx,
- strerror(-rc));
- rc = -ENOMEM;
- return rc;
+ if (tf_session_is_shared_session(tfs)) {
+ /* Only get table info if required for the device */
+ if (dev->ops->tf_dev_get_tbl_info) {
+ rc = dev->ops->tf_dev_get_tbl_info(tfp,
+ tbl_db->tbl_db[parms->dir],
+ parms->type,
+ &base,
+ &shift);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get table info:%d\n",
+ tf_dir_2_str(parms->dir),
+ parms->type);
+ return rc;
+ }
+ }
+ TF_TBL_PTR_TO_RM(&raparms.index, parms->idx, base, shift);
+
+ raparms.rm_db = tbl_db->tbl_db[parms->dir];
+ raparms.subtype = parms->type;
+ raparms.allocated = &rallocated;
+ rc = tf_rm_is_allocated(&raparms);
+ if (rc)
+ return rc;
+
+ if (rallocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
+ TFP_DRV_LOG(ERR,
+ "%s, Invalid or not allocated index, type:%s, idx:%d\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->idx);
+ return -EINVAL;
+ }
+ } else {
+ aparms.sram_offset = parms->idx;
+ aparms.slice_size = iparms.slice_size;
+ aparms.bank_id = iparms.bank_id;
+ aparms.dir = parms->dir;
+ aparms.is_allocated = &allocated;
+ rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
+ if (rc || !allocated) {
+ TFP_DRV_LOG(ERR,
+ "%s: Entry not allocated:%s idx(%d):(%s)\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->idx,
+ strerror(-rc));
+ rc = -ENOMEM;
+ return rc;
+ }
}
-
/* Set the entry */
hparms.rm_db = tbl_db->tbl_db[parms->dir];
hparms.subtype = parms->type;
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v3 13/13] net/bnxt: add enhancements to TF ULP
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 00/13] enhancements to host based flow table management Venkat Duvvuru
` (11 preceding siblings ...)
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 12/13] net/bnxt: sram manager shared session Venkat Duvvuru
@ 2021-09-11 15:30 ` Venkat Duvvuru
2021-09-16 14:06 ` Ferruh Yigit
2021-09-16 3:25 ` [dpdk-dev] [PATCH v3 00/13] enhancements to host based flow table management Ajit Khaparde
2021-09-16 13:26 ` Ferruh Yigit
14 siblings, 1 reply; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-11 15:30 UTC (permalink / raw)
To: dev; +Cc: Kishore Padmanabha, Mike Baucom, Venkat Duvvuru
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
1. Added support to specify l4 port masks in the template. Also enabled
source mac in the wild card key for ingress flows.
2. Added support to enable offload for ipv6 traffic within the vxlan
tunnel connection.
3. The flow counters is reduced from 7168 to 6912 for Whitney.
The stats operation is updated to reflect counts for packets
at egress from CFA instead of ingress to CFA
4. The miss path for the l2 context table is updated with correct
parif and default action handler to handle the miss path for
egress flows.
5. This support enables allocation of encapsulation, modification and
action records dynamically based on a given flow actions.
6. Reduce the l2context resource requests during open_session. Move the
SMAC from the L2Context to the EM/WM
7. Remap the parif in the bd action in order to eliminate incorrect
replication of broadcast packets. The layer 4 source port mask
was incorrectly updated in the outer layer 4 source port mask
instead of inner layer 4. Add the l3 proto to egress rules, switch
to using computed fields for l4 ports, add internal smac to f1/f2
flows, add l3 proto to ingress ipv6 flows
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Mike Baucom <michael.baucom@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
---
drivers/net/bnxt/tf_core/tf_tbl_sram.c | 7 -
.../generic_templates/ulp_template_db_class.c | 8102 ++++++++++++-----
.../generic_templates/ulp_template_db_enum.h | 675 +-
.../generic_templates/ulp_template_db_field.h | 195 +-
.../generic_templates/ulp_template_db_tbl.c | 2136 ++++-
.../ulp_template_db_thor_act.c | 996 +-
.../ulp_template_db_thor_class.c | 7495 ++++++++-------
.../ulp_template_db_wh_plus_class.c | 14 +-
drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c | 4 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 135 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 175 +-
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 10 +
drivers/net/bnxt/tf_ulp/ulp_utils.c | 3 +-
13 files changed, 13538 insertions(+), 6409 deletions(-)
diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.c b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
index 167078a8c6..636811bc2d 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl_sram.c
+++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
@@ -134,11 +134,6 @@ static int tf_tbl_sram_get_info(struct tf_tbl_sram_get_info_parms *parms)
if (slices)
parms->slice_size = tf_tbl_sram_slices_2_size[slices];
- TFP_DRV_LOG(DEBUG,
- "(%s) bank(%s) slice_size(%s)\n",
- tf_tbl_type_2_str(parms->tbl_type),
- tf_sram_bank_2_str(parms->bank_id),
- tf_sram_slice_2_str(parms->slice_size));
return rc;
}
@@ -373,7 +368,6 @@ tf_tbl_sram_free(struct tf *tfp __rte_unused,
return rc;
}
-
#if (DBG_SRAM == 1)
{
struct tf_sram_mgr_dump_parms dparms;
@@ -411,7 +405,6 @@ tf_tbl_sram_set(struct tf *tfp,
void *sram_handle = NULL;
uint16_t base = 0, shift = 0;
-
TF_CHECK_PARMS3(tfp, parms, parms->data);
/* Retrieve the session information */
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
index f74687acfa..ad3866243d 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 20 11:56:39 2021 */
+/* date: Fri Aug 6 11:15:47 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -362,508 +362,652 @@ uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {
[BNXT_ULP_CLASS_HID_315d] = 344,
[BNXT_ULP_CLASS_HID_3612] = 345,
[BNXT_ULP_CLASS_HID_66da] = 346,
- [BNXT_ULP_CLASS_HID_6165] = 347,
- [BNXT_ULP_CLASS_HID_2aa1] = 348,
- [BNXT_ULP_CLASS_HID_09cd] = 349,
- [BNXT_ULP_CLASS_HID_3845] = 350,
- [BNXT_ULP_CLASS_HID_11e9] = 351,
- [BNXT_ULP_CLASS_HID_4361] = 352,
- [BNXT_ULP_CLASS_HID_218d] = 353,
- [BNXT_ULP_CLASS_HID_5105] = 354,
- [BNXT_ULP_CLASS_HID_0c89] = 355,
- [BNXT_ULP_CLASS_HID_3e81] = 356,
- [BNXT_ULP_CLASS_HID_1dad] = 357,
- [BNXT_ULP_CLASS_HID_4ca5] = 358,
- [BNXT_ULP_CLASS_HID_25c9] = 359,
- [BNXT_ULP_CLASS_HID_57c1] = 360,
- [BNXT_ULP_CLASS_HID_33ed] = 361,
- [BNXT_ULP_CLASS_HID_65e5] = 362,
- [BNXT_ULP_CLASS_HID_6dd9] = 363,
- [BNXT_ULP_CLASS_HID_261d] = 364,
- [BNXT_ULP_CLASS_HID_0571] = 365,
- [BNXT_ULP_CLASS_HID_34f9] = 366,
- [BNXT_ULP_CLASS_HID_1d55] = 367,
- [BNXT_ULP_CLASS_HID_4fdd] = 368,
- [BNXT_ULP_CLASS_HID_2d31] = 369,
- [BNXT_ULP_CLASS_HID_5db9] = 370,
- [BNXT_ULP_CLASS_HID_0035] = 371,
- [BNXT_ULP_CLASS_HID_323d] = 372,
- [BNXT_ULP_CLASS_HID_1111] = 373,
- [BNXT_ULP_CLASS_HID_4019] = 374,
- [BNXT_ULP_CLASS_HID_2975] = 375,
- [BNXT_ULP_CLASS_HID_5b7d] = 376,
- [BNXT_ULP_CLASS_HID_3f51] = 377,
- [BNXT_ULP_CLASS_HID_6959] = 378,
- [BNXT_ULP_CLASS_HID_0e85] = 379,
- [BNXT_ULP_CLASS_HID_380d] = 380,
- [BNXT_ULP_CLASS_HID_1f21] = 381,
- [BNXT_ULP_CLASS_HID_4ea9] = 382,
- [BNXT_ULP_CLASS_HID_1705] = 383,
- [BNXT_ULP_CLASS_HID_418d] = 384,
- [BNXT_ULP_CLASS_HID_2721] = 385,
- [BNXT_ULP_CLASS_HID_57a9] = 386,
- [BNXT_ULP_CLASS_HID_1a25] = 387,
- [BNXT_ULP_CLASS_HID_342d] = 388,
- [BNXT_ULP_CLASS_HID_2b01] = 389,
- [BNXT_ULP_CLASS_HID_5a09] = 390,
- [BNXT_ULP_CLASS_HID_2325] = 391,
- [BNXT_ULP_CLASS_HID_5d2d] = 392,
- [BNXT_ULP_CLASS_HID_3101] = 393,
- [BNXT_ULP_CLASS_HID_6309] = 394,
- [BNXT_ULP_CLASS_HID_0bad] = 395,
- [BNXT_ULP_CLASS_HID_2535] = 396,
- [BNXT_ULP_CLASS_HID_1869] = 397,
- [BNXT_ULP_CLASS_HID_4bf1] = 398,
- [BNXT_ULP_CLASS_HID_136d] = 399,
- [BNXT_ULP_CLASS_HID_43f5] = 400,
- [BNXT_ULP_CLASS_HID_2129] = 401,
- [BNXT_ULP_CLASS_HID_53b1] = 402,
- [BNXT_ULP_CLASS_HID_072d] = 403,
- [BNXT_ULP_CLASS_HID_3135] = 404,
- [BNXT_ULP_CLASS_HID_1429] = 405,
- [BNXT_ULP_CLASS_HID_4731] = 406,
- [BNXT_ULP_CLASS_HID_2f6d] = 407,
- [BNXT_ULP_CLASS_HID_5f75] = 408,
- [BNXT_ULP_CLASS_HID_3d69] = 409,
- [BNXT_ULP_CLASS_HID_6f71] = 410,
- [BNXT_ULP_CLASS_HID_0dbd] = 411,
- [BNXT_ULP_CLASS_HID_3f25] = 412,
- [BNXT_ULP_CLASS_HID_1239] = 413,
- [BNXT_ULP_CLASS_HID_4da1] = 414,
- [BNXT_ULP_CLASS_HID_153d] = 415,
- [BNXT_ULP_CLASS_HID_45a5] = 416,
- [BNXT_ULP_CLASS_HID_3bb9] = 417,
- [BNXT_ULP_CLASS_HID_55a1] = 418,
- [BNXT_ULP_CLASS_HID_193d] = 419,
- [BNXT_ULP_CLASS_HID_4b25] = 420,
- [BNXT_ULP_CLASS_HID_2e39] = 421,
- [BNXT_ULP_CLASS_HID_5921] = 422,
- [BNXT_ULP_CLASS_HID_213d] = 423,
- [BNXT_ULP_CLASS_HID_5125] = 424,
- [BNXT_ULP_CLASS_HID_3739] = 425,
- [BNXT_ULP_CLASS_HID_093d] = 426,
- [BNXT_ULP_CLASS_HID_684d] = 427,
- [BNXT_ULP_CLASS_HID_2389] = 428,
- [BNXT_ULP_CLASS_HID_00e5] = 429,
- [BNXT_ULP_CLASS_HID_316d] = 430,
- [BNXT_ULP_CLASS_HID_18c1] = 431,
- [BNXT_ULP_CLASS_HID_4a49] = 432,
- [BNXT_ULP_CLASS_HID_28a5] = 433,
- [BNXT_ULP_CLASS_HID_582d] = 434,
- [BNXT_ULP_CLASS_HID_05a1] = 435,
- [BNXT_ULP_CLASS_HID_37a9] = 436,
- [BNXT_ULP_CLASS_HID_1485] = 437,
- [BNXT_ULP_CLASS_HID_458d] = 438,
- [BNXT_ULP_CLASS_HID_2ce1] = 439,
- [BNXT_ULP_CLASS_HID_5ee9] = 440,
- [BNXT_ULP_CLASS_HID_3ac5] = 441,
- [BNXT_ULP_CLASS_HID_6ccd] = 442,
- [BNXT_ULP_CLASS_HID_0b11] = 443,
- [BNXT_ULP_CLASS_HID_3d99] = 444,
- [BNXT_ULP_CLASS_HID_1ab5] = 445,
- [BNXT_ULP_CLASS_HID_4b3d] = 446,
- [BNXT_ULP_CLASS_HID_1291] = 447,
- [BNXT_ULP_CLASS_HID_4419] = 448,
- [BNXT_ULP_CLASS_HID_22b5] = 449,
- [BNXT_ULP_CLASS_HID_523d] = 450,
- [BNXT_ULP_CLASS_HID_1fb1] = 451,
- [BNXT_ULP_CLASS_HID_31b9] = 452,
- [BNXT_ULP_CLASS_HID_2e95] = 453,
- [BNXT_ULP_CLASS_HID_5f9d] = 454,
- [BNXT_ULP_CLASS_HID_26b1] = 455,
- [BNXT_ULP_CLASS_HID_58b9] = 456,
- [BNXT_ULP_CLASS_HID_3495] = 457,
- [BNXT_ULP_CLASS_HID_669d] = 458,
- [BNXT_ULP_CLASS_HID_0e39] = 459,
- [BNXT_ULP_CLASS_HID_20a1] = 460,
- [BNXT_ULP_CLASS_HID_1dfd] = 461,
- [BNXT_ULP_CLASS_HID_4e65] = 462,
- [BNXT_ULP_CLASS_HID_16f9] = 463,
- [BNXT_ULP_CLASS_HID_4661] = 464,
- [BNXT_ULP_CLASS_HID_24bd] = 465,
- [BNXT_ULP_CLASS_HID_5625] = 466,
- [BNXT_ULP_CLASS_HID_02b9] = 467,
- [BNXT_ULP_CLASS_HID_34a1] = 468,
- [BNXT_ULP_CLASS_HID_11bd] = 469,
- [BNXT_ULP_CLASS_HID_42a5] = 470,
- [BNXT_ULP_CLASS_HID_2af9] = 471,
- [BNXT_ULP_CLASS_HID_5ae1] = 472,
- [BNXT_ULP_CLASS_HID_38fd] = 473,
- [BNXT_ULP_CLASS_HID_6ae5] = 474,
- [BNXT_ULP_CLASS_HID_0829] = 475,
- [BNXT_ULP_CLASS_HID_3ab1] = 476,
- [BNXT_ULP_CLASS_HID_17ad] = 477,
- [BNXT_ULP_CLASS_HID_4835] = 478,
- [BNXT_ULP_CLASS_HID_10a9] = 479,
- [BNXT_ULP_CLASS_HID_4031] = 480,
- [BNXT_ULP_CLASS_HID_3e2d] = 481,
- [BNXT_ULP_CLASS_HID_5035] = 482,
- [BNXT_ULP_CLASS_HID_1ca9] = 483,
- [BNXT_ULP_CLASS_HID_4eb1] = 484,
- [BNXT_ULP_CLASS_HID_2bad] = 485,
- [BNXT_ULP_CLASS_HID_5cb5] = 486,
- [BNXT_ULP_CLASS_HID_24a9] = 487,
- [BNXT_ULP_CLASS_HID_54b1] = 488,
- [BNXT_ULP_CLASS_HID_32ad] = 489,
- [BNXT_ULP_CLASS_HID_0ca9] = 490,
- [BNXT_ULP_CLASS_HID_7f35] = 491,
- [BNXT_ULP_CLASS_HID_34f1] = 492,
- [BNXT_ULP_CLASS_HID_179d] = 493,
- [BNXT_ULP_CLASS_HID_2615] = 494,
- [BNXT_ULP_CLASS_HID_0fb9] = 495,
- [BNXT_ULP_CLASS_HID_5d31] = 496,
- [BNXT_ULP_CLASS_HID_3fdd] = 497,
- [BNXT_ULP_CLASS_HID_4f55] = 498,
- [BNXT_ULP_CLASS_HID_12d9] = 499,
- [BNXT_ULP_CLASS_HID_20d1] = 500,
- [BNXT_ULP_CLASS_HID_03fd] = 501,
- [BNXT_ULP_CLASS_HID_52f5] = 502,
- [BNXT_ULP_CLASS_HID_3b99] = 503,
- [BNXT_ULP_CLASS_HID_4991] = 504,
- [BNXT_ULP_CLASS_HID_2dbd] = 505,
- [BNXT_ULP_CLASS_HID_7bb5] = 506,
- [BNXT_ULP_CLASS_HID_34c6] = 507,
- [BNXT_ULP_CLASS_HID_0c22] = 508,
- [BNXT_ULP_CLASS_HID_1cbe] = 509,
- [BNXT_ULP_CLASS_HID_179a] = 510,
- [BNXT_ULP_CLASS_HID_59be] = 511,
- [BNXT_ULP_CLASS_HID_515a] = 512,
- [BNXT_ULP_CLASS_HID_1c72] = 513,
- [BNXT_ULP_CLASS_HID_171e] = 514,
- [BNXT_ULP_CLASS_HID_19c8] = 515,
- [BNXT_ULP_CLASS_HID_112c] = 516,
- [BNXT_ULP_CLASS_HID_4d68] = 517,
- [BNXT_ULP_CLASS_HID_444c] = 518,
- [BNXT_ULP_CLASS_HID_0e8c] = 519,
- [BNXT_ULP_CLASS_HID_09e0] = 520,
- [BNXT_ULP_CLASS_HID_1af0] = 521,
- [BNXT_ULP_CLASS_HID_15d4] = 522,
- [BNXT_ULP_CLASS_HID_1dd0] = 523,
- [BNXT_ULP_CLASS_HID_14f4] = 524,
- [BNXT_ULP_CLASS_HID_70b0] = 525,
- [BNXT_ULP_CLASS_HID_4854] = 526,
- [BNXT_ULP_CLASS_HID_3dd4] = 527,
- [BNXT_ULP_CLASS_HID_34f8] = 528,
- [BNXT_ULP_CLASS_HID_09e8] = 529,
- [BNXT_ULP_CLASS_HID_008c] = 530,
- [BNXT_ULP_CLASS_HID_34e6] = 531,
- [BNXT_ULP_CLASS_HID_0c02] = 532,
- [BNXT_ULP_CLASS_HID_1c9e] = 533,
- [BNXT_ULP_CLASS_HID_17ba] = 534,
- [BNXT_ULP_CLASS_HID_429e] = 535,
- [BNXT_ULP_CLASS_HID_5dba] = 536,
- [BNXT_ULP_CLASS_HID_2a16] = 537,
- [BNXT_ULP_CLASS_HID_2532] = 538,
- [BNXT_ULP_CLASS_HID_2da2] = 539,
- [BNXT_ULP_CLASS_HID_24fe] = 540,
- [BNXT_ULP_CLASS_HID_355a] = 541,
- [BNXT_ULP_CLASS_HID_0c76] = 542,
- [BNXT_ULP_CLASS_HID_13e6] = 543,
- [BNXT_ULP_CLASS_HID_7276] = 544,
- [BNXT_ULP_CLASS_HID_42d2] = 545,
- [BNXT_ULP_CLASS_HID_5dee] = 546,
- [BNXT_ULP_CLASS_HID_59de] = 547,
- [BNXT_ULP_CLASS_HID_513a] = 548,
- [BNXT_ULP_CLASS_HID_1c12] = 549,
- [BNXT_ULP_CLASS_HID_177e] = 550,
- [BNXT_ULP_CLASS_HID_0e92] = 551,
- [BNXT_ULP_CLASS_HID_09fe] = 552,
- [BNXT_ULP_CLASS_HID_5c1a] = 553,
- [BNXT_ULP_CLASS_HID_5746] = 554,
- [BNXT_ULP_CLASS_HID_79da] = 555,
- [BNXT_ULP_CLASS_HID_7106] = 556,
- [BNXT_ULP_CLASS_HID_3c1e] = 557,
- [BNXT_ULP_CLASS_HID_377a] = 558,
- [BNXT_ULP_CLASS_HID_2e9e] = 559,
- [BNXT_ULP_CLASS_HID_29fa] = 560,
- [BNXT_ULP_CLASS_HID_14d2] = 561,
- [BNXT_ULP_CLASS_HID_7742] = 562,
- [BNXT_ULP_CLASS_HID_3706] = 563,
- [BNXT_ULP_CLASS_HID_0fe2] = 564,
- [BNXT_ULP_CLASS_HID_1f7e] = 565,
- [BNXT_ULP_CLASS_HID_145a] = 566,
- [BNXT_ULP_CLASS_HID_417e] = 567,
- [BNXT_ULP_CLASS_HID_5e5a] = 568,
- [BNXT_ULP_CLASS_HID_29f6] = 569,
- [BNXT_ULP_CLASS_HID_26d2] = 570,
- [BNXT_ULP_CLASS_HID_2e42] = 571,
- [BNXT_ULP_CLASS_HID_271e] = 572,
- [BNXT_ULP_CLASS_HID_36ba] = 573,
- [BNXT_ULP_CLASS_HID_0f96] = 574,
- [BNXT_ULP_CLASS_HID_1006] = 575,
- [BNXT_ULP_CLASS_HID_7196] = 576,
- [BNXT_ULP_CLASS_HID_4132] = 577,
- [BNXT_ULP_CLASS_HID_5e0e] = 578,
- [BNXT_ULP_CLASS_HID_59fe] = 579,
- [BNXT_ULP_CLASS_HID_511a] = 580,
- [BNXT_ULP_CLASS_HID_1c32] = 581,
- [BNXT_ULP_CLASS_HID_175e] = 582,
- [BNXT_ULP_CLASS_HID_0eb2] = 583,
- [BNXT_ULP_CLASS_HID_09de] = 584,
- [BNXT_ULP_CLASS_HID_5c3a] = 585,
- [BNXT_ULP_CLASS_HID_5766] = 586,
- [BNXT_ULP_CLASS_HID_79fa] = 587,
- [BNXT_ULP_CLASS_HID_7126] = 588,
- [BNXT_ULP_CLASS_HID_3c3e] = 589,
- [BNXT_ULP_CLASS_HID_375a] = 590,
- [BNXT_ULP_CLASS_HID_2ebe] = 591,
- [BNXT_ULP_CLASS_HID_29da] = 592,
- [BNXT_ULP_CLASS_HID_14f2] = 593,
- [BNXT_ULP_CLASS_HID_7762] = 594,
- [BNXT_ULP_CLASS_HID_19e8] = 595,
- [BNXT_ULP_CLASS_HID_110c] = 596,
- [BNXT_ULP_CLASS_HID_4d48] = 597,
- [BNXT_ULP_CLASS_HID_446c] = 598,
- [BNXT_ULP_CLASS_HID_0eac] = 599,
- [BNXT_ULP_CLASS_HID_09c0] = 600,
- [BNXT_ULP_CLASS_HID_1ad0] = 601,
- [BNXT_ULP_CLASS_HID_15f4] = 602,
- [BNXT_ULP_CLASS_HID_39ec] = 603,
- [BNXT_ULP_CLASS_HID_3100] = 604,
- [BNXT_ULP_CLASS_HID_0210] = 605,
- [BNXT_ULP_CLASS_HID_1d34] = 606,
- [BNXT_ULP_CLASS_HID_2ea0] = 607,
- [BNXT_ULP_CLASS_HID_29c4] = 608,
- [BNXT_ULP_CLASS_HID_3ad4] = 609,
- [BNXT_ULP_CLASS_HID_35e8] = 610,
- [BNXT_ULP_CLASS_HID_5d80] = 611,
- [BNXT_ULP_CLASS_HID_54a4] = 612,
- [BNXT_ULP_CLASS_HID_29b4] = 613,
- [BNXT_ULP_CLASS_HID_20c8] = 614,
- [BNXT_ULP_CLASS_HID_7244] = 615,
- [BNXT_ULP_CLASS_HID_4d98] = 616,
- [BNXT_ULP_CLASS_HID_5e68] = 617,
- [BNXT_ULP_CLASS_HID_598c] = 618,
- [BNXT_ULP_CLASS_HID_1248] = 619,
- [BNXT_ULP_CLASS_HID_74d8] = 620,
- [BNXT_ULP_CLASS_HID_49a8] = 621,
- [BNXT_ULP_CLASS_HID_40cc] = 622,
- [BNXT_ULP_CLASS_HID_0b0c] = 623,
- [BNXT_ULP_CLASS_HID_0220] = 624,
- [BNXT_ULP_CLASS_HID_1730] = 625,
- [BNXT_ULP_CLASS_HID_7980] = 626,
- [BNXT_ULP_CLASS_HID_1db0] = 627,
- [BNXT_ULP_CLASS_HID_1494] = 628,
- [BNXT_ULP_CLASS_HID_70d0] = 629,
- [BNXT_ULP_CLASS_HID_4834] = 630,
- [BNXT_ULP_CLASS_HID_3db4] = 631,
- [BNXT_ULP_CLASS_HID_3498] = 632,
- [BNXT_ULP_CLASS_HID_0988] = 633,
- [BNXT_ULP_CLASS_HID_00ec] = 634,
- [BNXT_ULP_CLASS_HID_3f44] = 635,
- [BNXT_ULP_CLASS_HID_36a8] = 636,
- [BNXT_ULP_CLASS_HID_0b58] = 637,
- [BNXT_ULP_CLASS_HID_02bc] = 638,
- [BNXT_ULP_CLASS_HID_5f48] = 639,
- [BNXT_ULP_CLASS_HID_56ac] = 640,
- [BNXT_ULP_CLASS_HID_2b5c] = 641,
- [BNXT_ULP_CLASS_HID_2280] = 642,
- [BNXT_ULP_CLASS_HID_4000] = 643,
- [BNXT_ULP_CLASS_HID_5b64] = 644,
- [BNXT_ULP_CLASS_HID_2c14] = 645,
- [BNXT_ULP_CLASS_HID_2778] = 646,
- [BNXT_ULP_CLASS_HID_18f8] = 647,
- [BNXT_ULP_CLASS_HID_13dc] = 648,
- [BNXT_ULP_CLASS_HID_4c18] = 649,
- [BNXT_ULP_CLASS_HID_477c] = 650,
- [BNXT_ULP_CLASS_HID_1a88] = 651,
- [BNXT_ULP_CLASS_HID_15ec] = 652,
- [BNXT_ULP_CLASS_HID_4e28] = 653,
- [BNXT_ULP_CLASS_HID_490c] = 654,
- [BNXT_ULP_CLASS_HID_3a8c] = 655,
- [BNXT_ULP_CLASS_HID_35f0] = 656,
- [BNXT_ULP_CLASS_HID_06e0] = 657,
- [BNXT_ULP_CLASS_HID_01c4] = 658,
- [BNXT_ULP_CLASS_HID_1a08] = 659,
- [BNXT_ULP_CLASS_HID_12ec] = 660,
- [BNXT_ULP_CLASS_HID_4ea8] = 661,
- [BNXT_ULP_CLASS_HID_478c] = 662,
- [BNXT_ULP_CLASS_HID_0d4c] = 663,
- [BNXT_ULP_CLASS_HID_0a20] = 664,
- [BNXT_ULP_CLASS_HID_1930] = 665,
- [BNXT_ULP_CLASS_HID_1614] = 666,
- [BNXT_ULP_CLASS_HID_3a0c] = 667,
- [BNXT_ULP_CLASS_HID_32e0] = 668,
- [BNXT_ULP_CLASS_HID_01f0] = 669,
- [BNXT_ULP_CLASS_HID_1ed4] = 670,
- [BNXT_ULP_CLASS_HID_2d40] = 671,
- [BNXT_ULP_CLASS_HID_2a24] = 672,
- [BNXT_ULP_CLASS_HID_3934] = 673,
- [BNXT_ULP_CLASS_HID_3608] = 674,
- [BNXT_ULP_CLASS_HID_5e60] = 675,
- [BNXT_ULP_CLASS_HID_5744] = 676,
- [BNXT_ULP_CLASS_HID_2a54] = 677,
- [BNXT_ULP_CLASS_HID_2328] = 678,
- [BNXT_ULP_CLASS_HID_71a4] = 679,
- [BNXT_ULP_CLASS_HID_4e78] = 680,
- [BNXT_ULP_CLASS_HID_5d88] = 681,
- [BNXT_ULP_CLASS_HID_5a6c] = 682,
- [BNXT_ULP_CLASS_HID_11a8] = 683,
- [BNXT_ULP_CLASS_HID_7738] = 684,
- [BNXT_ULP_CLASS_HID_4a48] = 685,
- [BNXT_ULP_CLASS_HID_432c] = 686,
- [BNXT_ULP_CLASS_HID_08ec] = 687,
- [BNXT_ULP_CLASS_HID_01c0] = 688,
- [BNXT_ULP_CLASS_HID_14d0] = 689,
- [BNXT_ULP_CLASS_HID_7a60] = 690,
- [BNXT_ULP_CLASS_HID_1d90] = 691,
- [BNXT_ULP_CLASS_HID_14b4] = 692,
- [BNXT_ULP_CLASS_HID_70f0] = 693,
- [BNXT_ULP_CLASS_HID_4814] = 694,
- [BNXT_ULP_CLASS_HID_3d94] = 695,
- [BNXT_ULP_CLASS_HID_34b8] = 696,
- [BNXT_ULP_CLASS_HID_09a8] = 697,
- [BNXT_ULP_CLASS_HID_00cc] = 698,
- [BNXT_ULP_CLASS_HID_3f64] = 699,
- [BNXT_ULP_CLASS_HID_3688] = 700,
- [BNXT_ULP_CLASS_HID_0b78] = 701,
- [BNXT_ULP_CLASS_HID_029c] = 702,
- [BNXT_ULP_CLASS_HID_5f68] = 703,
- [BNXT_ULP_CLASS_HID_568c] = 704,
- [BNXT_ULP_CLASS_HID_2b7c] = 705,
- [BNXT_ULP_CLASS_HID_22a0] = 706,
- [BNXT_ULP_CLASS_HID_4020] = 707,
- [BNXT_ULP_CLASS_HID_5b44] = 708,
- [BNXT_ULP_CLASS_HID_2c34] = 709,
- [BNXT_ULP_CLASS_HID_2758] = 710,
- [BNXT_ULP_CLASS_HID_18d8] = 711,
- [BNXT_ULP_CLASS_HID_13fc] = 712,
- [BNXT_ULP_CLASS_HID_4c38] = 713,
- [BNXT_ULP_CLASS_HID_475c] = 714,
- [BNXT_ULP_CLASS_HID_1aa8] = 715,
- [BNXT_ULP_CLASS_HID_15cc] = 716,
- [BNXT_ULP_CLASS_HID_4e08] = 717,
- [BNXT_ULP_CLASS_HID_492c] = 718,
- [BNXT_ULP_CLASS_HID_3aac] = 719,
- [BNXT_ULP_CLASS_HID_35d0] = 720,
- [BNXT_ULP_CLASS_HID_06c0] = 721,
- [BNXT_ULP_CLASS_HID_01e4] = 722,
- [BNXT_ULP_CLASS_HID_4d32] = 723,
- [BNXT_ULP_CLASS_HID_54aa] = 724,
- [BNXT_ULP_CLASS_HID_0686] = 725,
- [BNXT_ULP_CLASS_HID_540e] = 726,
- [BNXT_ULP_CLASS_HID_2e3c] = 727,
- [BNXT_ULP_CLASS_HID_3a20] = 728,
- [BNXT_ULP_CLASS_HID_46f0] = 729,
- [BNXT_ULP_CLASS_HID_52e4] = 730,
- [BNXT_ULP_CLASS_HID_55e4] = 731,
- [BNXT_ULP_CLASS_HID_21f8] = 732,
- [BNXT_ULP_CLASS_HID_75e8] = 733,
- [BNXT_ULP_CLASS_HID_41fc] = 734,
- [BNXT_ULP_CLASS_HID_4d12] = 735,
- [BNXT_ULP_CLASS_HID_548a] = 736,
- [BNXT_ULP_CLASS_HID_3356] = 737,
- [BNXT_ULP_CLASS_HID_1ace] = 738,
- [BNXT_ULP_CLASS_HID_1a9a] = 739,
- [BNXT_ULP_CLASS_HID_4d46] = 740,
- [BNXT_ULP_CLASS_HID_2812] = 741,
- [BNXT_ULP_CLASS_HID_338a] = 742,
- [BNXT_ULP_CLASS_HID_06e6] = 743,
- [BNXT_ULP_CLASS_HID_546e] = 744,
- [BNXT_ULP_CLASS_HID_46ee] = 745,
- [BNXT_ULP_CLASS_HID_0d22] = 746,
- [BNXT_ULP_CLASS_HID_26e2] = 747,
- [BNXT_ULP_CLASS_HID_746a] = 748,
- [BNXT_ULP_CLASS_HID_1fa6] = 749,
- [BNXT_ULP_CLASS_HID_2d2e] = 750,
- [BNXT_ULP_CLASS_HID_4ef2] = 751,
- [BNXT_ULP_CLASS_HID_576a] = 752,
- [BNXT_ULP_CLASS_HID_30b6] = 753,
- [BNXT_ULP_CLASS_HID_192e] = 754,
- [BNXT_ULP_CLASS_HID_197a] = 755,
- [BNXT_ULP_CLASS_HID_4ea6] = 756,
- [BNXT_ULP_CLASS_HID_2bf2] = 757,
- [BNXT_ULP_CLASS_HID_306a] = 758,
- [BNXT_ULP_CLASS_HID_06c6] = 759,
- [BNXT_ULP_CLASS_HID_544e] = 760,
- [BNXT_ULP_CLASS_HID_46ce] = 761,
- [BNXT_ULP_CLASS_HID_0d02] = 762,
- [BNXT_ULP_CLASS_HID_26c2] = 763,
- [BNXT_ULP_CLASS_HID_744a] = 764,
- [BNXT_ULP_CLASS_HID_1f86] = 765,
- [BNXT_ULP_CLASS_HID_2d0e] = 766,
- [BNXT_ULP_CLASS_HID_2e1c] = 767,
- [BNXT_ULP_CLASS_HID_3a00] = 768,
- [BNXT_ULP_CLASS_HID_46d0] = 769,
- [BNXT_ULP_CLASS_HID_52c4] = 770,
- [BNXT_ULP_CLASS_HID_4e10] = 771,
- [BNXT_ULP_CLASS_HID_5a04] = 772,
- [BNXT_ULP_CLASS_HID_1f98] = 773,
- [BNXT_ULP_CLASS_HID_72f8] = 774,
- [BNXT_ULP_CLASS_HID_0a78] = 775,
- [BNXT_ULP_CLASS_HID_166c] = 776,
- [BNXT_ULP_CLASS_HID_233c] = 777,
- [BNXT_ULP_CLASS_HID_0f20] = 778,
- [BNXT_ULP_CLASS_HID_2a7c] = 779,
- [BNXT_ULP_CLASS_HID_3660] = 780,
- [BNXT_ULP_CLASS_HID_4330] = 781,
- [BNXT_ULP_CLASS_HID_2f24] = 782,
- [BNXT_ULP_CLASS_HID_5584] = 783,
- [BNXT_ULP_CLASS_HID_2198] = 784,
- [BNXT_ULP_CLASS_HID_7588] = 785,
- [BNXT_ULP_CLASS_HID_419c] = 786,
- [BNXT_ULP_CLASS_HID_7758] = 787,
- [BNXT_ULP_CLASS_HID_43ac] = 788,
- [BNXT_ULP_CLASS_HID_0c10] = 789,
- [BNXT_ULP_CLASS_HID_1864] = 790,
- [BNXT_ULP_CLASS_HID_30c8] = 791,
- [BNXT_ULP_CLASS_HID_1cdc] = 792,
- [BNXT_ULP_CLASS_HID_50cc] = 793,
- [BNXT_ULP_CLASS_HID_3d20] = 794,
- [BNXT_ULP_CLASS_HID_529c] = 795,
- [BNXT_ULP_CLASS_HID_3ef0] = 796,
- [BNXT_ULP_CLASS_HID_72e0] = 797,
- [BNXT_ULP_CLASS_HID_5ef4] = 798,
- [BNXT_ULP_CLASS_HID_2dfc] = 799,
- [BNXT_ULP_CLASS_HID_39e0] = 800,
- [BNXT_ULP_CLASS_HID_4530] = 801,
- [BNXT_ULP_CLASS_HID_5124] = 802,
- [BNXT_ULP_CLASS_HID_4df0] = 803,
- [BNXT_ULP_CLASS_HID_59e4] = 804,
- [BNXT_ULP_CLASS_HID_1c78] = 805,
- [BNXT_ULP_CLASS_HID_7118] = 806,
- [BNXT_ULP_CLASS_HID_0998] = 807,
- [BNXT_ULP_CLASS_HID_158c] = 808,
- [BNXT_ULP_CLASS_HID_20dc] = 809,
- [BNXT_ULP_CLASS_HID_0cc0] = 810,
- [BNXT_ULP_CLASS_HID_299c] = 811,
- [BNXT_ULP_CLASS_HID_3580] = 812,
- [BNXT_ULP_CLASS_HID_40d0] = 813,
- [BNXT_ULP_CLASS_HID_2cc4] = 814,
- [BNXT_ULP_CLASS_HID_55a4] = 815,
- [BNXT_ULP_CLASS_HID_21b8] = 816,
- [BNXT_ULP_CLASS_HID_75a8] = 817,
- [BNXT_ULP_CLASS_HID_41bc] = 818,
- [BNXT_ULP_CLASS_HID_7778] = 819,
- [BNXT_ULP_CLASS_HID_438c] = 820,
- [BNXT_ULP_CLASS_HID_0c30] = 821,
- [BNXT_ULP_CLASS_HID_1844] = 822,
- [BNXT_ULP_CLASS_HID_30e8] = 823,
- [BNXT_ULP_CLASS_HID_1cfc] = 824,
- [BNXT_ULP_CLASS_HID_50ec] = 825,
- [BNXT_ULP_CLASS_HID_3d00] = 826,
- [BNXT_ULP_CLASS_HID_52bc] = 827,
- [BNXT_ULP_CLASS_HID_3ed0] = 828,
- [BNXT_ULP_CLASS_HID_72c0] = 829,
- [BNXT_ULP_CLASS_HID_5ed4] = 830,
- [BNXT_ULP_CLASS_HID_3866] = 831,
- [BNXT_ULP_CLASS_HID_381e] = 832,
- [BNXT_ULP_CLASS_HID_3860] = 833,
- [BNXT_ULP_CLASS_HID_0454] = 834,
- [BNXT_ULP_CLASS_HID_3818] = 835,
- [BNXT_ULP_CLASS_HID_042c] = 836,
- [BNXT_ULP_CLASS_HID_3846] = 837,
- [BNXT_ULP_CLASS_HID_387e] = 838,
- [BNXT_ULP_CLASS_HID_3ba6] = 839,
- [BNXT_ULP_CLASS_HID_385e] = 840,
- [BNXT_ULP_CLASS_HID_3840] = 841,
- [BNXT_ULP_CLASS_HID_0474] = 842,
- [BNXT_ULP_CLASS_HID_3878] = 843,
- [BNXT_ULP_CLASS_HID_044c] = 844,
- [BNXT_ULP_CLASS_HID_3ba0] = 845,
- [BNXT_ULP_CLASS_HID_0794] = 846,
- [BNXT_ULP_CLASS_HID_3858] = 847,
- [BNXT_ULP_CLASS_HID_046c] = 848
+ [BNXT_ULP_CLASS_HID_e082] = 347,
+ [BNXT_ULP_CLASS_HID_ab46] = 348,
+ [BNXT_ULP_CLASS_HID_c82a] = 349,
+ [BNXT_ULP_CLASS_HID_f9a2] = 350,
+ [BNXT_ULP_CLASS_HID_d8ce] = 351,
+ [BNXT_ULP_CLASS_HID_a2d2] = 352,
+ [BNXT_ULP_CLASS_HID_c076] = 353,
+ [BNXT_ULP_CLASS_HID_f1ee] = 354,
+ [BNXT_ULP_CLASS_HID_a96e] = 355,
+ [BNXT_ULP_CLASS_HID_dae6] = 356,
+ [BNXT_ULP_CLASS_HID_c7aa] = 357,
+ [BNXT_ULP_CLASS_HID_c26e] = 358,
+ [BNXT_ULP_CLASS_HID_a0fa] = 359,
+ [BNXT_ULP_CLASS_HID_d272] = 360,
+ [BNXT_ULP_CLASS_HID_fff6] = 361,
+ [BNXT_ULP_CLASS_HID_e16e] = 362,
+ [BNXT_ULP_CLASS_HID_e165] = 363,
+ [BNXT_ULP_CLASS_HID_aaa1] = 364,
+ [BNXT_ULP_CLASS_HID_c9cd] = 365,
+ [BNXT_ULP_CLASS_HID_f845] = 366,
+ [BNXT_ULP_CLASS_HID_90f9] = 367,
+ [BNXT_ULP_CLASS_HID_c371] = 368,
+ [BNXT_ULP_CLASS_HID_e19d] = 369,
+ [BNXT_ULP_CLASS_HID_d015] = 370,
+ [BNXT_ULP_CLASS_HID_8c09] = 371,
+ [BNXT_ULP_CLASS_HID_be89] = 372,
+ [BNXT_ULP_CLASS_HID_ddad] = 373,
+ [BNXT_ULP_CLASS_HID_cc2d] = 374,
+ [BNXT_ULP_CLASS_HID_a4d9] = 375,
+ [BNXT_ULP_CLASS_HID_d759] = 376,
+ [BNXT_ULP_CLASS_HID_f27d] = 377,
+ [BNXT_ULP_CLASS_HID_e4fd] = 378,
+ [BNXT_ULP_CLASS_HID_ecf6] = 379,
+ [BNXT_ULP_CLASS_HID_a732] = 380,
+ [BNXT_ULP_CLASS_HID_c45e] = 381,
+ [BNXT_ULP_CLASS_HID_f5d6] = 382,
+ [BNXT_ULP_CLASS_HID_d4ba] = 383,
+ [BNXT_ULP_CLASS_HID_aea6] = 384,
+ [BNXT_ULP_CLASS_HID_cc02] = 385,
+ [BNXT_ULP_CLASS_HID_fd9a] = 386,
+ [BNXT_ULP_CLASS_HID_a51a] = 387,
+ [BNXT_ULP_CLASS_HID_d692] = 388,
+ [BNXT_ULP_CLASS_HID_cbde] = 389,
+ [BNXT_ULP_CLASS_HID_ce1a] = 390,
+ [BNXT_ULP_CLASS_HID_ac8e] = 391,
+ [BNXT_ULP_CLASS_HID_de06] = 392,
+ [BNXT_ULP_CLASS_HID_f382] = 393,
+ [BNXT_ULP_CLASS_HID_ed1a] = 394,
+ [BNXT_ULP_CLASS_HID_9d6a] = 395,
+ [BNXT_ULP_CLASS_HID_cee2] = 396,
+ [BNXT_ULP_CLASS_HID_ec0e] = 397,
+ [BNXT_ULP_CLASS_HID_dd86] = 398,
+ [BNXT_ULP_CLASS_HID_852e] = 399,
+ [BNXT_ULP_CLASS_HID_b6a6] = 400,
+ [BNXT_ULP_CLASS_HID_eb82] = 401,
+ [BNXT_ULP_CLASS_HID_c50a] = 402,
+ [BNXT_ULP_CLASS_HID_ccca] = 403,
+ [BNXT_ULP_CLASS_HID_8706] = 404,
+ [BNXT_ULP_CLASS_HID_d38e] = 405,
+ [BNXT_ULP_CLASS_HID_d5ca] = 406,
+ [BNXT_ULP_CLASS_HID_b48e] = 407,
+ [BNXT_ULP_CLASS_HID_8e8a] = 408,
+ [BNXT_ULP_CLASS_HID_db02] = 409,
+ [BNXT_ULP_CLASS_HID_dd8e] = 410,
+ [BNXT_ULP_CLASS_HID_819a] = 411,
+ [BNXT_ULP_CLASS_HID_b31a] = 412,
+ [BNXT_ULP_CLASS_HID_d03e] = 413,
+ [BNXT_ULP_CLASS_HID_c1be] = 414,
+ [BNXT_ULP_CLASS_HID_890e] = 415,
+ [BNXT_ULP_CLASS_HID_ba8e] = 416,
+ [BNXT_ULP_CLASS_HID_dfaa] = 417,
+ [BNXT_ULP_CLASS_HID_c93a] = 418,
+ [BNXT_ULP_CLASS_HID_b11a] = 419,
+ [BNXT_ULP_CLASS_HID_8b4e] = 420,
+ [BNXT_ULP_CLASS_HID_c79e] = 421,
+ [BNXT_ULP_CLASS_HID_d9da] = 422,
+ [BNXT_ULP_CLASS_HID_b88e] = 423,
+ [BNXT_ULP_CLASS_HID_ea0e] = 424,
+ [BNXT_ULP_CLASS_HID_cf0a] = 425,
+ [BNXT_ULP_CLASS_HID_c18e] = 426,
+ [BNXT_ULP_CLASS_HID_a94a] = 427,
+ [BNXT_ULP_CLASS_HID_daca] = 428,
+ [BNXT_ULP_CLASS_HID_ffee] = 429,
+ [BNXT_ULP_CLASS_HID_e96e] = 430,
+ [BNXT_ULP_CLASS_HID_910e] = 431,
+ [BNXT_ULP_CLASS_HID_c28e] = 432,
+ [BNXT_ULP_CLASS_HID_e7aa] = 433,
+ [BNXT_ULP_CLASS_HID_d12a] = 434,
+ [BNXT_ULP_CLASS_HID_d8ca] = 435,
+ [BNXT_ULP_CLASS_HID_930e] = 436,
+ [BNXT_ULP_CLASS_HID_ef4e] = 437,
+ [BNXT_ULP_CLASS_HID_e18a] = 438,
+ [BNXT_ULP_CLASS_HID_c08e] = 439,
+ [BNXT_ULP_CLASS_HID_9a8a] = 440,
+ [BNXT_ULP_CLASS_HID_d70a] = 441,
+ [BNXT_ULP_CLASS_HID_e90e] = 442,
+ [BNXT_ULP_CLASS_HID_edd9] = 443,
+ [BNXT_ULP_CLASS_HID_a61d] = 444,
+ [BNXT_ULP_CLASS_HID_c571] = 445,
+ [BNXT_ULP_CLASS_HID_f4f9] = 446,
+ [BNXT_ULP_CLASS_HID_9c45] = 447,
+ [BNXT_ULP_CLASS_HID_cfcd] = 448,
+ [BNXT_ULP_CLASS_HID_ed21] = 449,
+ [BNXT_ULP_CLASS_HID_dca9] = 450,
+ [BNXT_ULP_CLASS_HID_80b5] = 451,
+ [BNXT_ULP_CLASS_HID_b235] = 452,
+ [BNXT_ULP_CLASS_HID_d111] = 453,
+ [BNXT_ULP_CLASS_HID_c091] = 454,
+ [BNXT_ULP_CLASS_HID_a865] = 455,
+ [BNXT_ULP_CLASS_HID_dbe5] = 456,
+ [BNXT_ULP_CLASS_HID_fec1] = 457,
+ [BNXT_ULP_CLASS_HID_e841] = 458,
+ [BNXT_ULP_CLASS_HID_8e85] = 459,
+ [BNXT_ULP_CLASS_HID_b80d] = 460,
+ [BNXT_ULP_CLASS_HID_df65] = 461,
+ [BNXT_ULP_CLASS_HID_ceed] = 462,
+ [BNXT_ULP_CLASS_HID_9645] = 463,
+ [BNXT_ULP_CLASS_HID_c1cd] = 464,
+ [BNXT_ULP_CLASS_HID_e725] = 465,
+ [BNXT_ULP_CLASS_HID_d6ad] = 466,
+ [BNXT_ULP_CLASS_HID_9aa5] = 467,
+ [BNXT_ULP_CLASS_HID_b425] = 468,
+ [BNXT_ULP_CLASS_HID_eb05] = 469,
+ [BNXT_ULP_CLASS_HID_da85] = 470,
+ [BNXT_ULP_CLASS_HID_a265] = 471,
+ [BNXT_ULP_CLASS_HID_dde5] = 472,
+ [BNXT_ULP_CLASS_HID_f0c5] = 473,
+ [BNXT_ULP_CLASS_HID_e245] = 474,
+ [BNXT_ULP_CLASS_HID_8b8f] = 475,
+ [BNXT_ULP_CLASS_HID_a517] = 476,
+ [BNXT_ULP_CLASS_HID_d86b] = 477,
+ [BNXT_ULP_CLASS_HID_cbf3] = 478,
+ [BNXT_ULP_CLASS_HID_934f] = 479,
+ [BNXT_ULP_CLASS_HID_c2c7] = 480,
+ [BNXT_ULP_CLASS_HID_e02b] = 481,
+ [BNXT_ULP_CLASS_HID_d3a3] = 482,
+ [BNXT_ULP_CLASS_HID_87a7] = 483,
+ [BNXT_ULP_CLASS_HID_b137] = 484,
+ [BNXT_ULP_CLASS_HID_d403] = 485,
+ [BNXT_ULP_CLASS_HID_c793] = 486,
+ [BNXT_ULP_CLASS_HID_af67] = 487,
+ [BNXT_ULP_CLASS_HID_dee7] = 488,
+ [BNXT_ULP_CLASS_HID_fdc3] = 489,
+ [BNXT_ULP_CLASS_HID_ef43] = 490,
+ [BNXT_ULP_CLASS_HID_8dbf] = 491,
+ [BNXT_ULP_CLASS_HID_bf07] = 492,
+ [BNXT_ULP_CLASS_HID_d21f] = 493,
+ [BNXT_ULP_CLASS_HID_cde7] = 494,
+ [BNXT_ULP_CLASS_HID_956f] = 495,
+ [BNXT_ULP_CLASS_HID_c4c7] = 496,
+ [BNXT_ULP_CLASS_HID_fbcf] = 497,
+ [BNXT_ULP_CLASS_HID_d5a7] = 498,
+ [BNXT_ULP_CLASS_HID_9957] = 499,
+ [BNXT_ULP_CLASS_HID_cb27] = 500,
+ [BNXT_ULP_CLASS_HID_ee37] = 501,
+ [BNXT_ULP_CLASS_HID_d987] = 502,
+ [BNXT_ULP_CLASS_HID_a107] = 503,
+ [BNXT_ULP_CLASS_HID_d0e7] = 504,
+ [BNXT_ULP_CLASS_HID_f7e7] = 505,
+ [BNXT_ULP_CLASS_HID_c827] = 506,
+ [BNXT_ULP_CLASS_HID_f76a] = 507,
+ [BNXT_ULP_CLASS_HID_bcae] = 508,
+ [BNXT_ULP_CLASS_HID_dfc2] = 509,
+ [BNXT_ULP_CLASS_HID_ee4a] = 510,
+ [BNXT_ULP_CLASS_HID_cf26] = 511,
+ [BNXT_ULP_CLASS_HID_b53a] = 512,
+ [BNXT_ULP_CLASS_HID_d79e] = 513,
+ [BNXT_ULP_CLASS_HID_e606] = 514,
+ [BNXT_ULP_CLASS_HID_be86] = 515,
+ [BNXT_ULP_CLASS_HID_cd0e] = 516,
+ [BNXT_ULP_CLASS_HID_d042] = 517,
+ [BNXT_ULP_CLASS_HID_d586] = 518,
+ [BNXT_ULP_CLASS_HID_b712] = 519,
+ [BNXT_ULP_CLASS_HID_c59a] = 520,
+ [BNXT_ULP_CLASS_HID_e81e] = 521,
+ [BNXT_ULP_CLASS_HID_f686] = 522,
+ [BNXT_ULP_CLASS_HID_86f6] = 523,
+ [BNXT_ULP_CLASS_HID_d57e] = 524,
+ [BNXT_ULP_CLASS_HID_f792] = 525,
+ [BNXT_ULP_CLASS_HID_c61a] = 526,
+ [BNXT_ULP_CLASS_HID_9eb2] = 527,
+ [BNXT_ULP_CLASS_HID_ad3a] = 528,
+ [BNXT_ULP_CLASS_HID_f01e] = 529,
+ [BNXT_ULP_CLASS_HID_de96] = 530,
+ [BNXT_ULP_CLASS_HID_d756] = 531,
+ [BNXT_ULP_CLASS_HID_9c9a] = 532,
+ [BNXT_ULP_CLASS_HID_c812] = 533,
+ [BNXT_ULP_CLASS_HID_ce56] = 534,
+ [BNXT_ULP_CLASS_HID_af12] = 535,
+ [BNXT_ULP_CLASS_HID_9516] = 536,
+ [BNXT_ULP_CLASS_HID_c09e] = 537,
+ [BNXT_ULP_CLASS_HID_c612] = 538,
+ [BNXT_ULP_CLASS_HID_9a06] = 539,
+ [BNXT_ULP_CLASS_HID_a886] = 540,
+ [BNXT_ULP_CLASS_HID_cba2] = 541,
+ [BNXT_ULP_CLASS_HID_da22] = 542,
+ [BNXT_ULP_CLASS_HID_9292] = 543,
+ [BNXT_ULP_CLASS_HID_a112] = 544,
+ [BNXT_ULP_CLASS_HID_c436] = 545,
+ [BNXT_ULP_CLASS_HID_d2a6] = 546,
+ [BNXT_ULP_CLASS_HID_aa86] = 547,
+ [BNXT_ULP_CLASS_HID_90d2] = 548,
+ [BNXT_ULP_CLASS_HID_dc02] = 549,
+ [BNXT_ULP_CLASS_HID_c246] = 550,
+ [BNXT_ULP_CLASS_HID_a312] = 551,
+ [BNXT_ULP_CLASS_HID_f192] = 552,
+ [BNXT_ULP_CLASS_HID_d496] = 553,
+ [BNXT_ULP_CLASS_HID_da12] = 554,
+ [BNXT_ULP_CLASS_HID_b2d6] = 555,
+ [BNXT_ULP_CLASS_HID_c156] = 556,
+ [BNXT_ULP_CLASS_HID_e472] = 557,
+ [BNXT_ULP_CLASS_HID_f2f2] = 558,
+ [BNXT_ULP_CLASS_HID_8a92] = 559,
+ [BNXT_ULP_CLASS_HID_d912] = 560,
+ [BNXT_ULP_CLASS_HID_fc36] = 561,
+ [BNXT_ULP_CLASS_HID_cab6] = 562,
+ [BNXT_ULP_CLASS_HID_c356] = 563,
+ [BNXT_ULP_CLASS_HID_8892] = 564,
+ [BNXT_ULP_CLASS_HID_f4d2] = 565,
+ [BNXT_ULP_CLASS_HID_fa16] = 566,
+ [BNXT_ULP_CLASS_HID_db12] = 567,
+ [BNXT_ULP_CLASS_HID_8116] = 568,
+ [BNXT_ULP_CLASS_HID_cc96] = 569,
+ [BNXT_ULP_CLASS_HID_f292] = 570,
+ [BNXT_ULP_CLASS_HID_e84d] = 571,
+ [BNXT_ULP_CLASS_HID_a389] = 572,
+ [BNXT_ULP_CLASS_HID_c0e5] = 573,
+ [BNXT_ULP_CLASS_HID_f16d] = 574,
+ [BNXT_ULP_CLASS_HID_99d1] = 575,
+ [BNXT_ULP_CLASS_HID_ca59] = 576,
+ [BNXT_ULP_CLASS_HID_e8b5] = 577,
+ [BNXT_ULP_CLASS_HID_d93d] = 578,
+ [BNXT_ULP_CLASS_HID_8521] = 579,
+ [BNXT_ULP_CLASS_HID_b7a1] = 580,
+ [BNXT_ULP_CLASS_HID_d485] = 581,
+ [BNXT_ULP_CLASS_HID_c505] = 582,
+ [BNXT_ULP_CLASS_HID_adf1] = 583,
+ [BNXT_ULP_CLASS_HID_de71] = 584,
+ [BNXT_ULP_CLASS_HID_fb55] = 585,
+ [BNXT_ULP_CLASS_HID_edd5] = 586,
+ [BNXT_ULP_CLASS_HID_8b11] = 587,
+ [BNXT_ULP_CLASS_HID_bd99] = 588,
+ [BNXT_ULP_CLASS_HID_daf1] = 589,
+ [BNXT_ULP_CLASS_HID_cb79] = 590,
+ [BNXT_ULP_CLASS_HID_93d1] = 591,
+ [BNXT_ULP_CLASS_HID_c459] = 592,
+ [BNXT_ULP_CLASS_HID_e2b1] = 593,
+ [BNXT_ULP_CLASS_HID_d339] = 594,
+ [BNXT_ULP_CLASS_HID_9f31] = 595,
+ [BNXT_ULP_CLASS_HID_b1b1] = 596,
+ [BNXT_ULP_CLASS_HID_ee91] = 597,
+ [BNXT_ULP_CLASS_HID_df11] = 598,
+ [BNXT_ULP_CLASS_HID_a7f1] = 599,
+ [BNXT_ULP_CLASS_HID_d871] = 600,
+ [BNXT_ULP_CLASS_HID_f551] = 601,
+ [BNXT_ULP_CLASS_HID_e7d1] = 602,
+ [BNXT_ULP_CLASS_HID_8e1b] = 603,
+ [BNXT_ULP_CLASS_HID_a083] = 604,
+ [BNXT_ULP_CLASS_HID_ddff] = 605,
+ [BNXT_ULP_CLASS_HID_ce67] = 606,
+ [BNXT_ULP_CLASS_HID_96db] = 607,
+ [BNXT_ULP_CLASS_HID_c753] = 608,
+ [BNXT_ULP_CLASS_HID_e5bf] = 609,
+ [BNXT_ULP_CLASS_HID_d637] = 610,
+ [BNXT_ULP_CLASS_HID_8233] = 611,
+ [BNXT_ULP_CLASS_HID_b4a3] = 612,
+ [BNXT_ULP_CLASS_HID_d197] = 613,
+ [BNXT_ULP_CLASS_HID_c207] = 614,
+ [BNXT_ULP_CLASS_HID_aaf3] = 615,
+ [BNXT_ULP_CLASS_HID_db73] = 616,
+ [BNXT_ULP_CLASS_HID_f857] = 617,
+ [BNXT_ULP_CLASS_HID_ead7] = 618,
+ [BNXT_ULP_CLASS_HID_882b] = 619,
+ [BNXT_ULP_CLASS_HID_ba93] = 620,
+ [BNXT_ULP_CLASS_HID_d78b] = 621,
+ [BNXT_ULP_CLASS_HID_c873] = 622,
+ [BNXT_ULP_CLASS_HID_90fb] = 623,
+ [BNXT_ULP_CLASS_HID_c153] = 624,
+ [BNXT_ULP_CLASS_HID_fe5b] = 625,
+ [BNXT_ULP_CLASS_HID_d033] = 626,
+ [BNXT_ULP_CLASS_HID_9cc3] = 627,
+ [BNXT_ULP_CLASS_HID_ceb3] = 628,
+ [BNXT_ULP_CLASS_HID_eba3] = 629,
+ [BNXT_ULP_CLASS_HID_dc13] = 630,
+ [BNXT_ULP_CLASS_HID_a493] = 631,
+ [BNXT_ULP_CLASS_HID_d573] = 632,
+ [BNXT_ULP_CLASS_HID_f273] = 633,
+ [BNXT_ULP_CLASS_HID_cdb3] = 634,
+ [BNXT_ULP_CLASS_HID_ff35] = 635,
+ [BNXT_ULP_CLASS_HID_b4f1] = 636,
+ [BNXT_ULP_CLASS_HID_d79d] = 637,
+ [BNXT_ULP_CLASS_HID_e615] = 638,
+ [BNXT_ULP_CLASS_HID_8ea9] = 639,
+ [BNXT_ULP_CLASS_HID_dd21] = 640,
+ [BNXT_ULP_CLASS_HID_ffcd] = 641,
+ [BNXT_ULP_CLASS_HID_ce45] = 642,
+ [BNXT_ULP_CLASS_HID_9259] = 643,
+ [BNXT_ULP_CLASS_HID_a0d9] = 644,
+ [BNXT_ULP_CLASS_HID_c3fd] = 645,
+ [BNXT_ULP_CLASS_HID_d27d] = 646,
+ [BNXT_ULP_CLASS_HID_ba89] = 647,
+ [BNXT_ULP_CLASS_HID_c909] = 648,
+ [BNXT_ULP_CLASS_HID_ec2d] = 649,
+ [BNXT_ULP_CLASS_HID_faad] = 650,
+ [BNXT_ULP_CLASS_HID_34c6] = 651,
+ [BNXT_ULP_CLASS_HID_0c22] = 652,
+ [BNXT_ULP_CLASS_HID_1cbe] = 653,
+ [BNXT_ULP_CLASS_HID_179a] = 654,
+ [BNXT_ULP_CLASS_HID_59be] = 655,
+ [BNXT_ULP_CLASS_HID_515a] = 656,
+ [BNXT_ULP_CLASS_HID_1c72] = 657,
+ [BNXT_ULP_CLASS_HID_171e] = 658,
+ [BNXT_ULP_CLASS_HID_19c8] = 659,
+ [BNXT_ULP_CLASS_HID_112c] = 660,
+ [BNXT_ULP_CLASS_HID_4d68] = 661,
+ [BNXT_ULP_CLASS_HID_444c] = 662,
+ [BNXT_ULP_CLASS_HID_0e8c] = 663,
+ [BNXT_ULP_CLASS_HID_09e0] = 664,
+ [BNXT_ULP_CLASS_HID_1af0] = 665,
+ [BNXT_ULP_CLASS_HID_15d4] = 666,
+ [BNXT_ULP_CLASS_HID_1dd0] = 667,
+ [BNXT_ULP_CLASS_HID_14f4] = 668,
+ [BNXT_ULP_CLASS_HID_70b0] = 669,
+ [BNXT_ULP_CLASS_HID_4854] = 670,
+ [BNXT_ULP_CLASS_HID_3dd4] = 671,
+ [BNXT_ULP_CLASS_HID_34f8] = 672,
+ [BNXT_ULP_CLASS_HID_09e8] = 673,
+ [BNXT_ULP_CLASS_HID_008c] = 674,
+ [BNXT_ULP_CLASS_HID_34e6] = 675,
+ [BNXT_ULP_CLASS_HID_0c02] = 676,
+ [BNXT_ULP_CLASS_HID_1c9e] = 677,
+ [BNXT_ULP_CLASS_HID_17ba] = 678,
+ [BNXT_ULP_CLASS_HID_429e] = 679,
+ [BNXT_ULP_CLASS_HID_5dba] = 680,
+ [BNXT_ULP_CLASS_HID_2a16] = 681,
+ [BNXT_ULP_CLASS_HID_2532] = 682,
+ [BNXT_ULP_CLASS_HID_2da2] = 683,
+ [BNXT_ULP_CLASS_HID_24fe] = 684,
+ [BNXT_ULP_CLASS_HID_355a] = 685,
+ [BNXT_ULP_CLASS_HID_0c76] = 686,
+ [BNXT_ULP_CLASS_HID_13e6] = 687,
+ [BNXT_ULP_CLASS_HID_7276] = 688,
+ [BNXT_ULP_CLASS_HID_42d2] = 689,
+ [BNXT_ULP_CLASS_HID_5dee] = 690,
+ [BNXT_ULP_CLASS_HID_59de] = 691,
+ [BNXT_ULP_CLASS_HID_513a] = 692,
+ [BNXT_ULP_CLASS_HID_1c12] = 693,
+ [BNXT_ULP_CLASS_HID_177e] = 694,
+ [BNXT_ULP_CLASS_HID_0e92] = 695,
+ [BNXT_ULP_CLASS_HID_09fe] = 696,
+ [BNXT_ULP_CLASS_HID_5c1a] = 697,
+ [BNXT_ULP_CLASS_HID_5746] = 698,
+ [BNXT_ULP_CLASS_HID_79da] = 699,
+ [BNXT_ULP_CLASS_HID_7106] = 700,
+ [BNXT_ULP_CLASS_HID_3c1e] = 701,
+ [BNXT_ULP_CLASS_HID_377a] = 702,
+ [BNXT_ULP_CLASS_HID_2e9e] = 703,
+ [BNXT_ULP_CLASS_HID_29fa] = 704,
+ [BNXT_ULP_CLASS_HID_14d2] = 705,
+ [BNXT_ULP_CLASS_HID_7742] = 706,
+ [BNXT_ULP_CLASS_HID_3706] = 707,
+ [BNXT_ULP_CLASS_HID_0fe2] = 708,
+ [BNXT_ULP_CLASS_HID_1f7e] = 709,
+ [BNXT_ULP_CLASS_HID_145a] = 710,
+ [BNXT_ULP_CLASS_HID_417e] = 711,
+ [BNXT_ULP_CLASS_HID_5e5a] = 712,
+ [BNXT_ULP_CLASS_HID_29f6] = 713,
+ [BNXT_ULP_CLASS_HID_26d2] = 714,
+ [BNXT_ULP_CLASS_HID_2e42] = 715,
+ [BNXT_ULP_CLASS_HID_271e] = 716,
+ [BNXT_ULP_CLASS_HID_36ba] = 717,
+ [BNXT_ULP_CLASS_HID_0f96] = 718,
+ [BNXT_ULP_CLASS_HID_1006] = 719,
+ [BNXT_ULP_CLASS_HID_7196] = 720,
+ [BNXT_ULP_CLASS_HID_4132] = 721,
+ [BNXT_ULP_CLASS_HID_5e0e] = 722,
+ [BNXT_ULP_CLASS_HID_59fe] = 723,
+ [BNXT_ULP_CLASS_HID_511a] = 724,
+ [BNXT_ULP_CLASS_HID_1c32] = 725,
+ [BNXT_ULP_CLASS_HID_175e] = 726,
+ [BNXT_ULP_CLASS_HID_0eb2] = 727,
+ [BNXT_ULP_CLASS_HID_09de] = 728,
+ [BNXT_ULP_CLASS_HID_5c3a] = 729,
+ [BNXT_ULP_CLASS_HID_5766] = 730,
+ [BNXT_ULP_CLASS_HID_79fa] = 731,
+ [BNXT_ULP_CLASS_HID_7126] = 732,
+ [BNXT_ULP_CLASS_HID_3c3e] = 733,
+ [BNXT_ULP_CLASS_HID_375a] = 734,
+ [BNXT_ULP_CLASS_HID_2ebe] = 735,
+ [BNXT_ULP_CLASS_HID_29da] = 736,
+ [BNXT_ULP_CLASS_HID_14f2] = 737,
+ [BNXT_ULP_CLASS_HID_7762] = 738,
+ [BNXT_ULP_CLASS_HID_19e8] = 739,
+ [BNXT_ULP_CLASS_HID_110c] = 740,
+ [BNXT_ULP_CLASS_HID_4d48] = 741,
+ [BNXT_ULP_CLASS_HID_446c] = 742,
+ [BNXT_ULP_CLASS_HID_0eac] = 743,
+ [BNXT_ULP_CLASS_HID_09c0] = 744,
+ [BNXT_ULP_CLASS_HID_1ad0] = 745,
+ [BNXT_ULP_CLASS_HID_15f4] = 746,
+ [BNXT_ULP_CLASS_HID_39ec] = 747,
+ [BNXT_ULP_CLASS_HID_3100] = 748,
+ [BNXT_ULP_CLASS_HID_0210] = 749,
+ [BNXT_ULP_CLASS_HID_1d34] = 750,
+ [BNXT_ULP_CLASS_HID_2ea0] = 751,
+ [BNXT_ULP_CLASS_HID_29c4] = 752,
+ [BNXT_ULP_CLASS_HID_3ad4] = 753,
+ [BNXT_ULP_CLASS_HID_35e8] = 754,
+ [BNXT_ULP_CLASS_HID_5d80] = 755,
+ [BNXT_ULP_CLASS_HID_54a4] = 756,
+ [BNXT_ULP_CLASS_HID_29b4] = 757,
+ [BNXT_ULP_CLASS_HID_20c8] = 758,
+ [BNXT_ULP_CLASS_HID_7244] = 759,
+ [BNXT_ULP_CLASS_HID_4d98] = 760,
+ [BNXT_ULP_CLASS_HID_5e68] = 761,
+ [BNXT_ULP_CLASS_HID_598c] = 762,
+ [BNXT_ULP_CLASS_HID_1248] = 763,
+ [BNXT_ULP_CLASS_HID_74d8] = 764,
+ [BNXT_ULP_CLASS_HID_49a8] = 765,
+ [BNXT_ULP_CLASS_HID_40cc] = 766,
+ [BNXT_ULP_CLASS_HID_0b0c] = 767,
+ [BNXT_ULP_CLASS_HID_0220] = 768,
+ [BNXT_ULP_CLASS_HID_1730] = 769,
+ [BNXT_ULP_CLASS_HID_7980] = 770,
+ [BNXT_ULP_CLASS_HID_1db0] = 771,
+ [BNXT_ULP_CLASS_HID_1494] = 772,
+ [BNXT_ULP_CLASS_HID_70d0] = 773,
+ [BNXT_ULP_CLASS_HID_4834] = 774,
+ [BNXT_ULP_CLASS_HID_3db4] = 775,
+ [BNXT_ULP_CLASS_HID_3498] = 776,
+ [BNXT_ULP_CLASS_HID_0988] = 777,
+ [BNXT_ULP_CLASS_HID_00ec] = 778,
+ [BNXT_ULP_CLASS_HID_3f44] = 779,
+ [BNXT_ULP_CLASS_HID_36a8] = 780,
+ [BNXT_ULP_CLASS_HID_0b58] = 781,
+ [BNXT_ULP_CLASS_HID_02bc] = 782,
+ [BNXT_ULP_CLASS_HID_5f48] = 783,
+ [BNXT_ULP_CLASS_HID_56ac] = 784,
+ [BNXT_ULP_CLASS_HID_2b5c] = 785,
+ [BNXT_ULP_CLASS_HID_2280] = 786,
+ [BNXT_ULP_CLASS_HID_4000] = 787,
+ [BNXT_ULP_CLASS_HID_5b64] = 788,
+ [BNXT_ULP_CLASS_HID_2c14] = 789,
+ [BNXT_ULP_CLASS_HID_2778] = 790,
+ [BNXT_ULP_CLASS_HID_18f8] = 791,
+ [BNXT_ULP_CLASS_HID_13dc] = 792,
+ [BNXT_ULP_CLASS_HID_4c18] = 793,
+ [BNXT_ULP_CLASS_HID_477c] = 794,
+ [BNXT_ULP_CLASS_HID_1a88] = 795,
+ [BNXT_ULP_CLASS_HID_15ec] = 796,
+ [BNXT_ULP_CLASS_HID_4e28] = 797,
+ [BNXT_ULP_CLASS_HID_490c] = 798,
+ [BNXT_ULP_CLASS_HID_3a8c] = 799,
+ [BNXT_ULP_CLASS_HID_35f0] = 800,
+ [BNXT_ULP_CLASS_HID_06e0] = 801,
+ [BNXT_ULP_CLASS_HID_01c4] = 802,
+ [BNXT_ULP_CLASS_HID_1a08] = 803,
+ [BNXT_ULP_CLASS_HID_12ec] = 804,
+ [BNXT_ULP_CLASS_HID_4ea8] = 805,
+ [BNXT_ULP_CLASS_HID_478c] = 806,
+ [BNXT_ULP_CLASS_HID_0d4c] = 807,
+ [BNXT_ULP_CLASS_HID_0a20] = 808,
+ [BNXT_ULP_CLASS_HID_1930] = 809,
+ [BNXT_ULP_CLASS_HID_1614] = 810,
+ [BNXT_ULP_CLASS_HID_3a0c] = 811,
+ [BNXT_ULP_CLASS_HID_32e0] = 812,
+ [BNXT_ULP_CLASS_HID_01f0] = 813,
+ [BNXT_ULP_CLASS_HID_1ed4] = 814,
+ [BNXT_ULP_CLASS_HID_2d40] = 815,
+ [BNXT_ULP_CLASS_HID_2a24] = 816,
+ [BNXT_ULP_CLASS_HID_3934] = 817,
+ [BNXT_ULP_CLASS_HID_3608] = 818,
+ [BNXT_ULP_CLASS_HID_5e60] = 819,
+ [BNXT_ULP_CLASS_HID_5744] = 820,
+ [BNXT_ULP_CLASS_HID_2a54] = 821,
+ [BNXT_ULP_CLASS_HID_2328] = 822,
+ [BNXT_ULP_CLASS_HID_71a4] = 823,
+ [BNXT_ULP_CLASS_HID_4e78] = 824,
+ [BNXT_ULP_CLASS_HID_5d88] = 825,
+ [BNXT_ULP_CLASS_HID_5a6c] = 826,
+ [BNXT_ULP_CLASS_HID_11a8] = 827,
+ [BNXT_ULP_CLASS_HID_7738] = 828,
+ [BNXT_ULP_CLASS_HID_4a48] = 829,
+ [BNXT_ULP_CLASS_HID_432c] = 830,
+ [BNXT_ULP_CLASS_HID_08ec] = 831,
+ [BNXT_ULP_CLASS_HID_01c0] = 832,
+ [BNXT_ULP_CLASS_HID_14d0] = 833,
+ [BNXT_ULP_CLASS_HID_7a60] = 834,
+ [BNXT_ULP_CLASS_HID_1d90] = 835,
+ [BNXT_ULP_CLASS_HID_14b4] = 836,
+ [BNXT_ULP_CLASS_HID_70f0] = 837,
+ [BNXT_ULP_CLASS_HID_4814] = 838,
+ [BNXT_ULP_CLASS_HID_3d94] = 839,
+ [BNXT_ULP_CLASS_HID_34b8] = 840,
+ [BNXT_ULP_CLASS_HID_09a8] = 841,
+ [BNXT_ULP_CLASS_HID_00cc] = 842,
+ [BNXT_ULP_CLASS_HID_3f64] = 843,
+ [BNXT_ULP_CLASS_HID_3688] = 844,
+ [BNXT_ULP_CLASS_HID_0b78] = 845,
+ [BNXT_ULP_CLASS_HID_029c] = 846,
+ [BNXT_ULP_CLASS_HID_5f68] = 847,
+ [BNXT_ULP_CLASS_HID_568c] = 848,
+ [BNXT_ULP_CLASS_HID_2b7c] = 849,
+ [BNXT_ULP_CLASS_HID_22a0] = 850,
+ [BNXT_ULP_CLASS_HID_4020] = 851,
+ [BNXT_ULP_CLASS_HID_5b44] = 852,
+ [BNXT_ULP_CLASS_HID_2c34] = 853,
+ [BNXT_ULP_CLASS_HID_2758] = 854,
+ [BNXT_ULP_CLASS_HID_18d8] = 855,
+ [BNXT_ULP_CLASS_HID_13fc] = 856,
+ [BNXT_ULP_CLASS_HID_4c38] = 857,
+ [BNXT_ULP_CLASS_HID_475c] = 858,
+ [BNXT_ULP_CLASS_HID_1aa8] = 859,
+ [BNXT_ULP_CLASS_HID_15cc] = 860,
+ [BNXT_ULP_CLASS_HID_4e08] = 861,
+ [BNXT_ULP_CLASS_HID_492c] = 862,
+ [BNXT_ULP_CLASS_HID_3aac] = 863,
+ [BNXT_ULP_CLASS_HID_35d0] = 864,
+ [BNXT_ULP_CLASS_HID_06c0] = 865,
+ [BNXT_ULP_CLASS_HID_01e4] = 866,
+ [BNXT_ULP_CLASS_HID_4d32] = 867,
+ [BNXT_ULP_CLASS_HID_54aa] = 868,
+ [BNXT_ULP_CLASS_HID_0686] = 869,
+ [BNXT_ULP_CLASS_HID_540e] = 870,
+ [BNXT_ULP_CLASS_HID_2e3c] = 871,
+ [BNXT_ULP_CLASS_HID_3a20] = 872,
+ [BNXT_ULP_CLASS_HID_46f0] = 873,
+ [BNXT_ULP_CLASS_HID_52e4] = 874,
+ [BNXT_ULP_CLASS_HID_55e4] = 875,
+ [BNXT_ULP_CLASS_HID_21f8] = 876,
+ [BNXT_ULP_CLASS_HID_75e8] = 877,
+ [BNXT_ULP_CLASS_HID_41fc] = 878,
+ [BNXT_ULP_CLASS_HID_4d12] = 879,
+ [BNXT_ULP_CLASS_HID_548a] = 880,
+ [BNXT_ULP_CLASS_HID_3356] = 881,
+ [BNXT_ULP_CLASS_HID_1ace] = 882,
+ [BNXT_ULP_CLASS_HID_1a9a] = 883,
+ [BNXT_ULP_CLASS_HID_4d46] = 884,
+ [BNXT_ULP_CLASS_HID_2812] = 885,
+ [BNXT_ULP_CLASS_HID_338a] = 886,
+ [BNXT_ULP_CLASS_HID_06e6] = 887,
+ [BNXT_ULP_CLASS_HID_546e] = 888,
+ [BNXT_ULP_CLASS_HID_46ee] = 889,
+ [BNXT_ULP_CLASS_HID_0d22] = 890,
+ [BNXT_ULP_CLASS_HID_26e2] = 891,
+ [BNXT_ULP_CLASS_HID_746a] = 892,
+ [BNXT_ULP_CLASS_HID_1fa6] = 893,
+ [BNXT_ULP_CLASS_HID_2d2e] = 894,
+ [BNXT_ULP_CLASS_HID_4ef2] = 895,
+ [BNXT_ULP_CLASS_HID_576a] = 896,
+ [BNXT_ULP_CLASS_HID_30b6] = 897,
+ [BNXT_ULP_CLASS_HID_192e] = 898,
+ [BNXT_ULP_CLASS_HID_197a] = 899,
+ [BNXT_ULP_CLASS_HID_4ea6] = 900,
+ [BNXT_ULP_CLASS_HID_2bf2] = 901,
+ [BNXT_ULP_CLASS_HID_306a] = 902,
+ [BNXT_ULP_CLASS_HID_06c6] = 903,
+ [BNXT_ULP_CLASS_HID_544e] = 904,
+ [BNXT_ULP_CLASS_HID_46ce] = 905,
+ [BNXT_ULP_CLASS_HID_0d02] = 906,
+ [BNXT_ULP_CLASS_HID_26c2] = 907,
+ [BNXT_ULP_CLASS_HID_744a] = 908,
+ [BNXT_ULP_CLASS_HID_1f86] = 909,
+ [BNXT_ULP_CLASS_HID_2d0e] = 910,
+ [BNXT_ULP_CLASS_HID_2e1c] = 911,
+ [BNXT_ULP_CLASS_HID_3a00] = 912,
+ [BNXT_ULP_CLASS_HID_46d0] = 913,
+ [BNXT_ULP_CLASS_HID_52c4] = 914,
+ [BNXT_ULP_CLASS_HID_4e10] = 915,
+ [BNXT_ULP_CLASS_HID_5a04] = 916,
+ [BNXT_ULP_CLASS_HID_1f98] = 917,
+ [BNXT_ULP_CLASS_HID_72f8] = 918,
+ [BNXT_ULP_CLASS_HID_0a78] = 919,
+ [BNXT_ULP_CLASS_HID_166c] = 920,
+ [BNXT_ULP_CLASS_HID_233c] = 921,
+ [BNXT_ULP_CLASS_HID_0f20] = 922,
+ [BNXT_ULP_CLASS_HID_2a7c] = 923,
+ [BNXT_ULP_CLASS_HID_3660] = 924,
+ [BNXT_ULP_CLASS_HID_4330] = 925,
+ [BNXT_ULP_CLASS_HID_2f24] = 926,
+ [BNXT_ULP_CLASS_HID_5584] = 927,
+ [BNXT_ULP_CLASS_HID_2198] = 928,
+ [BNXT_ULP_CLASS_HID_7588] = 929,
+ [BNXT_ULP_CLASS_HID_419c] = 930,
+ [BNXT_ULP_CLASS_HID_7758] = 931,
+ [BNXT_ULP_CLASS_HID_43ac] = 932,
+ [BNXT_ULP_CLASS_HID_0c10] = 933,
+ [BNXT_ULP_CLASS_HID_1864] = 934,
+ [BNXT_ULP_CLASS_HID_30c8] = 935,
+ [BNXT_ULP_CLASS_HID_1cdc] = 936,
+ [BNXT_ULP_CLASS_HID_50cc] = 937,
+ [BNXT_ULP_CLASS_HID_3d20] = 938,
+ [BNXT_ULP_CLASS_HID_529c] = 939,
+ [BNXT_ULP_CLASS_HID_3ef0] = 940,
+ [BNXT_ULP_CLASS_HID_72e0] = 941,
+ [BNXT_ULP_CLASS_HID_5ef4] = 942,
+ [BNXT_ULP_CLASS_HID_2dfc] = 943,
+ [BNXT_ULP_CLASS_HID_39e0] = 944,
+ [BNXT_ULP_CLASS_HID_4530] = 945,
+ [BNXT_ULP_CLASS_HID_5124] = 946,
+ [BNXT_ULP_CLASS_HID_4df0] = 947,
+ [BNXT_ULP_CLASS_HID_59e4] = 948,
+ [BNXT_ULP_CLASS_HID_1c78] = 949,
+ [BNXT_ULP_CLASS_HID_7118] = 950,
+ [BNXT_ULP_CLASS_HID_0998] = 951,
+ [BNXT_ULP_CLASS_HID_158c] = 952,
+ [BNXT_ULP_CLASS_HID_20dc] = 953,
+ [BNXT_ULP_CLASS_HID_0cc0] = 954,
+ [BNXT_ULP_CLASS_HID_299c] = 955,
+ [BNXT_ULP_CLASS_HID_3580] = 956,
+ [BNXT_ULP_CLASS_HID_40d0] = 957,
+ [BNXT_ULP_CLASS_HID_2cc4] = 958,
+ [BNXT_ULP_CLASS_HID_55a4] = 959,
+ [BNXT_ULP_CLASS_HID_21b8] = 960,
+ [BNXT_ULP_CLASS_HID_75a8] = 961,
+ [BNXT_ULP_CLASS_HID_41bc] = 962,
+ [BNXT_ULP_CLASS_HID_7778] = 963,
+ [BNXT_ULP_CLASS_HID_438c] = 964,
+ [BNXT_ULP_CLASS_HID_0c30] = 965,
+ [BNXT_ULP_CLASS_HID_1844] = 966,
+ [BNXT_ULP_CLASS_HID_30e8] = 967,
+ [BNXT_ULP_CLASS_HID_1cfc] = 968,
+ [BNXT_ULP_CLASS_HID_50ec] = 969,
+ [BNXT_ULP_CLASS_HID_3d00] = 970,
+ [BNXT_ULP_CLASS_HID_52bc] = 971,
+ [BNXT_ULP_CLASS_HID_3ed0] = 972,
+ [BNXT_ULP_CLASS_HID_72c0] = 973,
+ [BNXT_ULP_CLASS_HID_5ed4] = 974,
+ [BNXT_ULP_CLASS_HID_3866] = 975,
+ [BNXT_ULP_CLASS_HID_381e] = 976,
+ [BNXT_ULP_CLASS_HID_3860] = 977,
+ [BNXT_ULP_CLASS_HID_0454] = 978,
+ [BNXT_ULP_CLASS_HID_3818] = 979,
+ [BNXT_ULP_CLASS_HID_042c] = 980,
+ [BNXT_ULP_CLASS_HID_3846] = 981,
+ [BNXT_ULP_CLASS_HID_387e] = 982,
+ [BNXT_ULP_CLASS_HID_3ba6] = 983,
+ [BNXT_ULP_CLASS_HID_385e] = 984,
+ [BNXT_ULP_CLASS_HID_3840] = 985,
+ [BNXT_ULP_CLASS_HID_0474] = 986,
+ [BNXT_ULP_CLASS_HID_3878] = 987,
+ [BNXT_ULP_CLASS_HID_044c] = 988,
+ [BNXT_ULP_CLASS_HID_3ba0] = 989,
+ [BNXT_ULP_CLASS_HID_0794] = 990,
+ [BNXT_ULP_CLASS_HID_3858] = 991,
+ [BNXT_ULP_CLASS_HID_046c] = 992
};
/* Array for the proto matcher list */
@@ -7165,7 +7309,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT }
},
[347] = {
- .class_hid = BNXT_ULP_CLASS_HID_6165,
+ .class_hid = BNXT_ULP_CLASS_HID_e082,
.class_tid = 2,
.hdr_sig_id = 1,
.flow_sig_id = 1313792,
@@ -7176,7 +7320,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7185,7 +7329,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC }
},
[348] = {
- .class_hid = BNXT_ULP_CLASS_HID_2aa1,
+ .class_hid = BNXT_ULP_CLASS_HID_ab46,
.class_tid = 2,
.hdr_sig_id = 1,
.flow_sig_id = 1321984,
@@ -7196,7 +7340,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7206,7 +7350,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC }
},
[349] = {
- .class_hid = BNXT_ULP_CLASS_HID_09cd,
+ .class_hid = BNXT_ULP_CLASS_HID_c82a,
.class_tid = 2,
.hdr_sig_id = 1,
.flow_sig_id = 3410944,
@@ -7217,7 +7361,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7227,7 +7371,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }
},
[350] = {
- .class_hid = BNXT_ULP_CLASS_HID_3845,
+ .class_hid = BNXT_ULP_CLASS_HID_f9a2,
.class_tid = 2,
.hdr_sig_id = 1,
.flow_sig_id = 3419136,
@@ -7238,7 +7382,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7249,10 +7393,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }
},
[351] = {
- .class_hid = BNXT_ULP_CLASS_HID_11e9,
+ .class_hid = BNXT_ULP_CLASS_HID_d8ce,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 2148797440,
+ .flow_sig_id = 538184704,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7260,20 +7404,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
},
[352] = {
- .class_hid = BNXT_ULP_CLASS_HID_4361,
+ .class_hid = BNXT_ULP_CLASS_HID_a2d2,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 2148805632,
+ .flow_sig_id = 538192896,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7281,7 +7425,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7289,13 +7433,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
},
[353] = {
- .class_hid = BNXT_ULP_CLASS_HID_218d,
+ .class_hid = BNXT_ULP_CLASS_HID_c076,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 2150894592,
+ .flow_sig_id = 540281856,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7303,7 +7447,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7311,13 +7455,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
},
[354] = {
- .class_hid = BNXT_ULP_CLASS_HID_5105,
+ .class_hid = BNXT_ULP_CLASS_HID_f1ee,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 2150902784,
+ .flow_sig_id = 540290048,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7325,7 +7469,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7334,13 +7478,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
},
[355] = {
- .class_hid = BNXT_ULP_CLASS_HID_0c89,
+ .class_hid = BNXT_ULP_CLASS_HID_a96e,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 4296281088,
+ .flow_sig_id = 1075055616,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7348,20 +7492,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[356] = {
- .class_hid = BNXT_ULP_CLASS_HID_3e81,
+ .class_hid = BNXT_ULP_CLASS_HID_dae6,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 4296289280,
+ .flow_sig_id = 1075063808,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7369,7 +7513,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7377,13 +7521,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[357] = {
- .class_hid = BNXT_ULP_CLASS_HID_1dad,
+ .class_hid = BNXT_ULP_CLASS_HID_c7aa,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 4298378240,
+ .flow_sig_id = 1077152768,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7391,7 +7535,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7399,13 +7543,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[358] = {
- .class_hid = BNXT_ULP_CLASS_HID_4ca5,
+ .class_hid = BNXT_ULP_CLASS_HID_c26e,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 4298386432,
+ .flow_sig_id = 1077160960,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7413,7 +7557,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7422,13 +7566,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[359] = {
- .class_hid = BNXT_ULP_CLASS_HID_25c9,
+ .class_hid = BNXT_ULP_CLASS_HID_a0fa,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 6443764736,
+ .flow_sig_id = 1611926528,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7436,21 +7580,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[360] = {
- .class_hid = BNXT_ULP_CLASS_HID_57c1,
+ .class_hid = BNXT_ULP_CLASS_HID_d272,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 6443772928,
+ .flow_sig_id = 1611934720,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7458,7 +7602,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7466,14 +7610,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[361] = {
- .class_hid = BNXT_ULP_CLASS_HID_33ed,
+ .class_hid = BNXT_ULP_CLASS_HID_fff6,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 6445861888,
+ .flow_sig_id = 1614023680,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7481,7 +7625,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7489,14 +7633,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[362] = {
- .class_hid = BNXT_ULP_CLASS_HID_65e5,
+ .class_hid = BNXT_ULP_CLASS_HID_e16e,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 6445870080,
+ .flow_sig_id = 1614031872,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7504,7 +7648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7513,11 +7657,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[363] = {
- .class_hid = BNXT_ULP_CLASS_HID_6dd9,
+ .class_hid = BNXT_ULP_CLASS_HID_e165,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 1313792,
@@ -7529,7 +7673,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7538,7 +7681,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }
},
[364] = {
- .class_hid = BNXT_ULP_CLASS_HID_261d,
+ .class_hid = BNXT_ULP_CLASS_HID_aaa1,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 1321984,
@@ -7550,7 +7693,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7560,7 +7702,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }
},
[365] = {
- .class_hid = BNXT_ULP_CLASS_HID_0571,
+ .class_hid = BNXT_ULP_CLASS_HID_c9cd,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 3410944,
@@ -7572,7 +7714,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7582,7 +7723,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
},
[366] = {
- .class_hid = BNXT_ULP_CLASS_HID_34f9,
+ .class_hid = BNXT_ULP_CLASS_HID_f845,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 3419136,
@@ -7594,7 +7735,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7605,7 +7745,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
},
[367] = {
- .class_hid = BNXT_ULP_CLASS_HID_1d55,
+ .class_hid = BNXT_ULP_CLASS_HID_90f9,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 2148797440,
@@ -7617,7 +7757,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7627,7 +7766,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
},
[368] = {
- .class_hid = BNXT_ULP_CLASS_HID_4fdd,
+ .class_hid = BNXT_ULP_CLASS_HID_c371,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 2148805632,
@@ -7639,7 +7778,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7650,7 +7788,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
},
[369] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d31,
+ .class_hid = BNXT_ULP_CLASS_HID_e19d,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 2150894592,
@@ -7662,7 +7800,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7673,7 +7810,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
},
[370] = {
- .class_hid = BNXT_ULP_CLASS_HID_5db9,
+ .class_hid = BNXT_ULP_CLASS_HID_d015,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 2150902784,
@@ -7685,7 +7822,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7697,7 +7833,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
},
[371] = {
- .class_hid = BNXT_ULP_CLASS_HID_0035,
+ .class_hid = BNXT_ULP_CLASS_HID_8c09,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 4296281088,
@@ -7709,7 +7845,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7719,7 +7854,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[372] = {
- .class_hid = BNXT_ULP_CLASS_HID_323d,
+ .class_hid = BNXT_ULP_CLASS_HID_be89,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 4296289280,
@@ -7731,7 +7866,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7742,7 +7876,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[373] = {
- .class_hid = BNXT_ULP_CLASS_HID_1111,
+ .class_hid = BNXT_ULP_CLASS_HID_ddad,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 4298378240,
@@ -7754,7 +7888,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7765,7 +7898,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[374] = {
- .class_hid = BNXT_ULP_CLASS_HID_4019,
+ .class_hid = BNXT_ULP_CLASS_HID_cc2d,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 4298386432,
@@ -7777,7 +7910,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7789,7 +7921,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[375] = {
- .class_hid = BNXT_ULP_CLASS_HID_2975,
+ .class_hid = BNXT_ULP_CLASS_HID_a4d9,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 6443764736,
@@ -7801,7 +7933,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7812,7 +7943,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[376] = {
- .class_hid = BNXT_ULP_CLASS_HID_5b7d,
+ .class_hid = BNXT_ULP_CLASS_HID_d759,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 6443772928,
@@ -7824,7 +7955,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7836,7 +7966,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[377] = {
- .class_hid = BNXT_ULP_CLASS_HID_3f51,
+ .class_hid = BNXT_ULP_CLASS_HID_f27d,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 6445861888,
@@ -7848,7 +7978,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7860,7 +7989,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[378] = {
- .class_hid = BNXT_ULP_CLASS_HID_6959,
+ .class_hid = BNXT_ULP_CLASS_HID_e4fd,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 6445870080,
@@ -7872,7 +8001,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7885,10 +8013,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[379] = {
- .class_hid = BNXT_ULP_CLASS_HID_0e85,
+ .class_hid = BNXT_ULP_CLASS_HID_ecf6,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 8591248384,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1313792,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7896,21 +8024,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
},
[380] = {
- .class_hid = BNXT_ULP_CLASS_HID_380d,
+ .class_hid = BNXT_ULP_CLASS_HID_a732,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 8591256576,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1321984,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7918,22 +8045,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
},
[381] = {
- .class_hid = BNXT_ULP_CLASS_HID_1f21,
+ .class_hid = BNXT_ULP_CLASS_HID_c45e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 8593345536,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3410944,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7941,22 +8067,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
},
[382] = {
- .class_hid = BNXT_ULP_CLASS_HID_4ea9,
+ .class_hid = BNXT_ULP_CLASS_HID_f5d6,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 8593353728,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3419136,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7964,23 +8089,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
},
[383] = {
- .class_hid = BNXT_ULP_CLASS_HID_1705,
+ .class_hid = BNXT_ULP_CLASS_HID_d4ba,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 10738732032,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 538184704,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7988,22 +8112,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[384] = {
- .class_hid = BNXT_ULP_CLASS_HID_418d,
+ .class_hid = BNXT_ULP_CLASS_HID_aea6,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 10738740224,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 538192896,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8011,23 +8134,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[385] = {
- .class_hid = BNXT_ULP_CLASS_HID_2721,
+ .class_hid = BNXT_ULP_CLASS_HID_cc02,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 10740829184,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 540281856,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8035,23 +8157,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[386] = {
- .class_hid = BNXT_ULP_CLASS_HID_57a9,
+ .class_hid = BNXT_ULP_CLASS_HID_fd9a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 10740837376,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 540290048,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8059,24 +8180,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[387] = {
- .class_hid = BNXT_ULP_CLASS_HID_1a25,
+ .class_hid = BNXT_ULP_CLASS_HID_a51a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 12886215680,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1075055616,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8084,22 +8204,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[388] = {
- .class_hid = BNXT_ULP_CLASS_HID_342d,
+ .class_hid = BNXT_ULP_CLASS_HID_d692,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 12886223872,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1075063808,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8107,23 +8226,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[389] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b01,
+ .class_hid = BNXT_ULP_CLASS_HID_cbde,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 12888312832,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1077152768,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8131,23 +8249,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[390] = {
- .class_hid = BNXT_ULP_CLASS_HID_5a09,
+ .class_hid = BNXT_ULP_CLASS_HID_ce1a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 12888321024,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1077160960,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8155,24 +8272,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[391] = {
- .class_hid = BNXT_ULP_CLASS_HID_2325,
+ .class_hid = BNXT_ULP_CLASS_HID_ac8e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 15033699328,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1611926528,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8180,23 +8296,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[392] = {
- .class_hid = BNXT_ULP_CLASS_HID_5d2d,
+ .class_hid = BNXT_ULP_CLASS_HID_de06,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 15033707520,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1611934720,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8204,24 +8319,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[393] = {
- .class_hid = BNXT_ULP_CLASS_HID_3101,
+ .class_hid = BNXT_ULP_CLASS_HID_f382,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 15035796480,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1614023680,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8229,24 +8343,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[394] = {
- .class_hid = BNXT_ULP_CLASS_HID_6309,
+ .class_hid = BNXT_ULP_CLASS_HID_ed1a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 15035804672,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1614031872,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8254,25 +8367,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[395] = {
- .class_hid = BNXT_ULP_CLASS_HID_0bad,
+ .class_hid = BNXT_ULP_CLASS_HID_9d6a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 17181182976,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2148797440,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8280,21 +8392,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[396] = {
- .class_hid = BNXT_ULP_CLASS_HID_2535,
+ .class_hid = BNXT_ULP_CLASS_HID_cee2,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 17181191168,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2148805632,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8302,22 +8414,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[397] = {
- .class_hid = BNXT_ULP_CLASS_HID_1869,
+ .class_hid = BNXT_ULP_CLASS_HID_ec0e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 17183280128,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2150894592,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8325,22 +8437,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[398] = {
- .class_hid = BNXT_ULP_CLASS_HID_4bf1,
+ .class_hid = BNXT_ULP_CLASS_HID_dd86,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 17183288320,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2150902784,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8348,23 +8460,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[399] = {
- .class_hid = BNXT_ULP_CLASS_HID_136d,
+ .class_hid = BNXT_ULP_CLASS_HID_852e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 19328666624,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2685668352,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8372,22 +8484,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[400] = {
- .class_hid = BNXT_ULP_CLASS_HID_43f5,
+ .class_hid = BNXT_ULP_CLASS_HID_b6a6,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 19328674816,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2685676544,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8395,23 +8507,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[401] = {
- .class_hid = BNXT_ULP_CLASS_HID_2129,
+ .class_hid = BNXT_ULP_CLASS_HID_eb82,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 19330763776,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2687765504,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8419,23 +8531,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[402] = {
- .class_hid = BNXT_ULP_CLASS_HID_53b1,
+ .class_hid = BNXT_ULP_CLASS_HID_c50a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 19330771968,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2687773696,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8443,24 +8555,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[403] = {
- .class_hid = BNXT_ULP_CLASS_HID_072d,
+ .class_hid = BNXT_ULP_CLASS_HID_ccca,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 21476150272,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3222539264,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8468,22 +8580,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[404] = {
- .class_hid = BNXT_ULP_CLASS_HID_3135,
+ .class_hid = BNXT_ULP_CLASS_HID_8706,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 21476158464,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3222547456,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8491,23 +8603,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[405] = {
- .class_hid = BNXT_ULP_CLASS_HID_1429,
+ .class_hid = BNXT_ULP_CLASS_HID_d38e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 21478247424,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3224636416,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8515,23 +8627,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[406] = {
- .class_hid = BNXT_ULP_CLASS_HID_4731,
+ .class_hid = BNXT_ULP_CLASS_HID_d5ca,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 21478255616,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3224644608,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8539,24 +8651,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[407] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f6d,
+ .class_hid = BNXT_ULP_CLASS_HID_b48e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 23623633920,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3759410176,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8564,23 +8676,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[408] = {
- .class_hid = BNXT_ULP_CLASS_HID_5f75,
+ .class_hid = BNXT_ULP_CLASS_HID_8e8a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 23623642112,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3759418368,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8588,24 +8700,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[409] = {
- .class_hid = BNXT_ULP_CLASS_HID_3d69,
+ .class_hid = BNXT_ULP_CLASS_HID_db02,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 23625731072,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3761507328,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8613,24 +8725,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[410] = {
- .class_hid = BNXT_ULP_CLASS_HID_6f71,
+ .class_hid = BNXT_ULP_CLASS_HID_dd8e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 23625739264,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3761515520,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8638,25 +8750,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
- },
- [411] = {
- .class_hid = BNXT_ULP_CLASS_HID_0dbd,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ },
+ [411] = {
+ .class_hid = BNXT_ULP_CLASS_HID_819a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 25771117568,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4296281088,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8664,22 +8776,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[412] = {
- .class_hid = BNXT_ULP_CLASS_HID_3f25,
+ .class_hid = BNXT_ULP_CLASS_HID_b31a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 25771125760,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4296289280,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8687,23 +8798,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[413] = {
- .class_hid = BNXT_ULP_CLASS_HID_1239,
+ .class_hid = BNXT_ULP_CLASS_HID_d03e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 25773214720,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4298378240,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8711,23 +8821,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[414] = {
- .class_hid = BNXT_ULP_CLASS_HID_4da1,
+ .class_hid = BNXT_ULP_CLASS_HID_c1be,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 25773222912,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4298386432,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8735,24 +8844,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[415] = {
- .class_hid = BNXT_ULP_CLASS_HID_153d,
+ .class_hid = BNXT_ULP_CLASS_HID_890e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 27918601216,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4833152000,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8760,23 +8868,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[416] = {
- .class_hid = BNXT_ULP_CLASS_HID_45a5,
+ .class_hid = BNXT_ULP_CLASS_HID_ba8e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 27918609408,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4833160192,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8784,24 +8891,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[417] = {
- .class_hid = BNXT_ULP_CLASS_HID_3bb9,
+ .class_hid = BNXT_ULP_CLASS_HID_dfaa,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 27920698368,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4835249152,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8809,24 +8915,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[418] = {
- .class_hid = BNXT_ULP_CLASS_HID_55a1,
+ .class_hid = BNXT_ULP_CLASS_HID_c93a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 27920706560,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4835257344,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8834,25 +8939,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[419] = {
- .class_hid = BNXT_ULP_CLASS_HID_193d,
+ .class_hid = BNXT_ULP_CLASS_HID_b11a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 30066084864,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5370022912,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8860,23 +8964,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[420] = {
- .class_hid = BNXT_ULP_CLASS_HID_4b25,
+ .class_hid = BNXT_ULP_CLASS_HID_8b4e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 30066093056,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5370031104,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8884,24 +8987,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[421] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e39,
+ .class_hid = BNXT_ULP_CLASS_HID_c79e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 30068182016,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5372120064,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8909,24 +9011,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[422] = {
- .class_hid = BNXT_ULP_CLASS_HID_5921,
+ .class_hid = BNXT_ULP_CLASS_HID_d9da,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 30068190208,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5372128256,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8934,25 +9035,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[423] = {
- .class_hid = BNXT_ULP_CLASS_HID_213d,
+ .class_hid = BNXT_ULP_CLASS_HID_b88e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 32213568512,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5906893824,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8960,24 +9060,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[424] = {
- .class_hid = BNXT_ULP_CLASS_HID_5125,
+ .class_hid = BNXT_ULP_CLASS_HID_ea0e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 32213576704,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5906902016,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8985,25 +9084,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[425] = {
- .class_hid = BNXT_ULP_CLASS_HID_3739,
+ .class_hid = BNXT_ULP_CLASS_HID_cf0a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 32215665664,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5908990976,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -9011,25 +9109,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[426] = {
- .class_hid = BNXT_ULP_CLASS_HID_093d,
+ .class_hid = BNXT_ULP_CLASS_HID_c18e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 32215673856,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5908999168,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -9037,25 +9134,3496 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [427] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a94a,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6443764736,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [428] = {
+ .class_hid = BNXT_ULP_CLASS_HID_daca,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6443772928,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [429] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ffee,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6445861888,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [430] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e96e,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6445870080,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [431] = {
+ .class_hid = BNXT_ULP_CLASS_HID_910e,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6980635648,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [432] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c28e,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6980643840,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [433] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e7aa,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6982732800,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [434] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d12a,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6982740992,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [435] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d8ca,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 7517506560,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [436] = {
+ .class_hid = BNXT_ULP_CLASS_HID_930e,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 7517514752,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [437] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ef4e,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 7519603712,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [438] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e18a,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 7519611904,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [439] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c08e,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8054377472,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [440] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9a8a,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8054385664,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [441] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d70a,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8056474624,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [442] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e90e,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8056482816,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [443] = {
+ .class_hid = BNXT_ULP_CLASS_HID_edd9,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1313792,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ },
+ [444] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a61d,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1321984,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ },
+ [445] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c571,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 3410944,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ },
+ [446] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f4f9,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 3419136,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ },
+ [447] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9c45,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2148797440,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [448] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cfcd,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2148805632,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [449] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ed21,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2150894592,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [450] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dca9,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2150902784,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [451] = {
+ .class_hid = BNXT_ULP_CLASS_HID_80b5,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4296281088,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [452] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b235,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4296289280,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [453] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d111,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4298378240,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [454] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c091,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4298386432,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [455] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a865,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6443764736,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [456] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dbe5,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6443772928,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [457] = {
+ .class_hid = BNXT_ULP_CLASS_HID_fec1,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6445861888,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [458] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e841,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6445870080,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [459] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8e85,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 8591248384,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [460] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b80d,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 8591256576,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [461] = {
+ .class_hid = BNXT_ULP_CLASS_HID_df65,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 8593345536,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [462] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ceed,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 8593353728,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [463] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9645,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 10738732032,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [464] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1cd,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 10738740224,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [465] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e725,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 10740829184,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [466] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d6ad,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 10740837376,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [467] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9aa5,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 12886215680,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [468] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b425,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 12886223872,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [469] = {
+ .class_hid = BNXT_ULP_CLASS_HID_eb05,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 12888312832,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [470] = {
+ .class_hid = BNXT_ULP_CLASS_HID_da85,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 12888321024,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [471] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a265,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 15033699328,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [472] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dde5,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 15033707520,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [473] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f0c5,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 15035796480,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [474] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e245,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 15035804672,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [475] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8b8f,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 17181182976,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [476] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a517,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 17181191168,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [477] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d86b,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 17183280128,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [478] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cbf3,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 17183288320,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [479] = {
+ .class_hid = BNXT_ULP_CLASS_HID_934f,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 19328666624,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [480] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c2c7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 19328674816,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [481] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e02b,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 19330763776,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [482] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d3a3,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 19330771968,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [483] = {
+ .class_hid = BNXT_ULP_CLASS_HID_87a7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 21476150272,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [484] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b137,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 21476158464,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [485] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d403,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 21478247424,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [486] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c793,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 21478255616,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [487] = {
+ .class_hid = BNXT_ULP_CLASS_HID_af67,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 23623633920,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [488] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dee7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 23623642112,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [489] = {
+ .class_hid = BNXT_ULP_CLASS_HID_fdc3,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 23625731072,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [490] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ef43,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 23625739264,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [491] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8dbf,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 25771117568,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [492] = {
+ .class_hid = BNXT_ULP_CLASS_HID_bf07,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 25771125760,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [493] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d21f,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 25773214720,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [494] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cde7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 25773222912,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [495] = {
+ .class_hid = BNXT_ULP_CLASS_HID_956f,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 27918601216,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [496] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c4c7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 27918609408,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [497] = {
+ .class_hid = BNXT_ULP_CLASS_HID_fbcf,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 27920698368,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [498] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d5a7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 27920706560,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [499] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9957,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 30066084864,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [500] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cb27,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 30066093056,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [501] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ee37,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 30068182016,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [502] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d987,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 30068190208,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [503] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a107,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 32213568512,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [504] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d0e7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 32213576704,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [505] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f7e7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 32215665664,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [506] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c827,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 32215673856,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [507] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f76a,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1313792,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC }
+ },
+ [508] = {
+ .class_hid = BNXT_ULP_CLASS_HID_bcae,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1321984,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC }
+ },
+ [509] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dfc2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3410944,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC }
+ },
+ [510] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ee4a,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3419136,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC }
+ },
+ [511] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cf26,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 538184704,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [512] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b53a,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 538192896,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [513] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d79e,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 540281856,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [514] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e606,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 540290048,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [515] = {
+ .class_hid = BNXT_ULP_CLASS_HID_be86,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1075055616,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [516] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cd0e,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1075063808,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [517] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d042,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1077152768,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [518] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d586,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1077160960,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [519] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b712,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1611926528,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [520] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c59a,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1611934720,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [521] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e81e,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1614023680,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [522] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f686,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1614031872,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [523] = {
+ .class_hid = BNXT_ULP_CLASS_HID_86f6,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2148797440,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [524] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d57e,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2148805632,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [525] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f792,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2150894592,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [526] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c61a,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2150902784,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [527] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9eb2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2685668352,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [528] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ad3a,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2685676544,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [529] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f01e,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2687765504,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [530] = {
+ .class_hid = BNXT_ULP_CLASS_HID_de96,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2687773696,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [531] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d756,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3222539264,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [532] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9c9a,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3222547456,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [533] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c812,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3224636416,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [534] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ce56,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3224644608,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [535] = {
+ .class_hid = BNXT_ULP_CLASS_HID_af12,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3759410176,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [536] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9516,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3759418368,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [537] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c09e,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3761507328,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [538] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c612,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3761515520,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [539] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9a06,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4296281088,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [540] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a886,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4296289280,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [541] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cba2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4298378240,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [542] = {
+ .class_hid = BNXT_ULP_CLASS_HID_da22,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4298386432,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [543] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9292,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4833152000,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [544] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a112,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4833160192,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [545] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c436,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4835249152,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [546] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d2a6,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4835257344,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [547] = {
+ .class_hid = BNXT_ULP_CLASS_HID_aa86,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5370022912,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [548] = {
+ .class_hid = BNXT_ULP_CLASS_HID_90d2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5370031104,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [549] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dc02,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5372120064,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [550] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c246,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5372128256,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [551] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a312,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5906893824,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [552] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f192,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5906902016,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [553] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d496,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5908990976,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [554] = {
+ .class_hid = BNXT_ULP_CLASS_HID_da12,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5908999168,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [555] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b2d6,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6443764736,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [556] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c156,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6443772928,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [557] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e472,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6445861888,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [558] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f2f2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6445870080,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [559] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8a92,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6980635648,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [560] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d912,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6980643840,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [561] = {
+ .class_hid = BNXT_ULP_CLASS_HID_fc36,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6982732800,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [562] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cab6,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6982740992,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [563] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c356,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 7517506560,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [564] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8892,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 7517514752,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [565] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f4d2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 7519603712,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [566] = {
+ .class_hid = BNXT_ULP_CLASS_HID_fa16,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 7519611904,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [567] = {
+ .class_hid = BNXT_ULP_CLASS_HID_db12,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 8054377472,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [568] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8116,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 8054385664,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [569] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cc96,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 8056474624,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [570] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f292,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 8056482816,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
},
- [427] = {
- .class_hid = BNXT_ULP_CLASS_HID_684d,
+ [571] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e84d,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 1313792,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9068,15 +12636,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC }
},
- [428] = {
- .class_hid = BNXT_ULP_CLASS_HID_2389,
+ [572] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a389,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 1321984,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9089,16 +12657,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC }
},
- [429] = {
- .class_hid = BNXT_ULP_CLASS_HID_00e5,
+ [573] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c0e5,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 3410944,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9111,16 +12679,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC }
},
- [430] = {
- .class_hid = BNXT_ULP_CLASS_HID_316d,
+ [574] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f16d,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 3419136,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9133,17 +12701,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC }
},
- [431] = {
- .class_hid = BNXT_ULP_CLASS_HID_18c1,
+ [575] = {
+ .class_hid = BNXT_ULP_CLASS_HID_99d1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 2148797440,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9156,16 +12724,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
},
- [432] = {
- .class_hid = BNXT_ULP_CLASS_HID_4a49,
+ [576] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ca59,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 2148805632,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9178,17 +12746,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
},
- [433] = {
- .class_hid = BNXT_ULP_CLASS_HID_28a5,
+ [577] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e8b5,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 2150894592,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9201,17 +12769,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
},
- [434] = {
- .class_hid = BNXT_ULP_CLASS_HID_582d,
+ [578] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d93d,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 2150902784,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9224,18 +12792,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
},
- [435] = {
- .class_hid = BNXT_ULP_CLASS_HID_05a1,
+ [579] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8521,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 4296281088,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9248,16 +12816,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [436] = {
- .class_hid = BNXT_ULP_CLASS_HID_37a9,
+ [580] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b7a1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 4296289280,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9270,17 +12838,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [437] = {
- .class_hid = BNXT_ULP_CLASS_HID_1485,
+ [581] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d485,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 4298378240,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9293,17 +12861,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [438] = {
- .class_hid = BNXT_ULP_CLASS_HID_458d,
+ [582] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c505,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 4298386432,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9316,18 +12884,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [439] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ce1,
+ [583] = {
+ .class_hid = BNXT_ULP_CLASS_HID_adf1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 6443764736,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9340,17 +12908,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [440] = {
- .class_hid = BNXT_ULP_CLASS_HID_5ee9,
+ [584] = {
+ .class_hid = BNXT_ULP_CLASS_HID_de71,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 6443772928,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9363,18 +12931,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [441] = {
- .class_hid = BNXT_ULP_CLASS_HID_3ac5,
+ [585] = {
+ .class_hid = BNXT_ULP_CLASS_HID_fb55,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 6445861888,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9387,18 +12955,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [442] = {
- .class_hid = BNXT_ULP_CLASS_HID_6ccd,
+ [586] = {
+ .class_hid = BNXT_ULP_CLASS_HID_edd5,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 6445870080,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9411,19 +12979,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [443] = {
- .class_hid = BNXT_ULP_CLASS_HID_0b11,
+ [587] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8b11,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 8591248384,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9436,16 +13004,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [444] = {
- .class_hid = BNXT_ULP_CLASS_HID_3d99,
+ [588] = {
+ .class_hid = BNXT_ULP_CLASS_HID_bd99,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 8591256576,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9458,17 +13026,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [445] = {
- .class_hid = BNXT_ULP_CLASS_HID_1ab5,
+ [589] = {
+ .class_hid = BNXT_ULP_CLASS_HID_daf1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 8593345536,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9481,17 +13049,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [446] = {
- .class_hid = BNXT_ULP_CLASS_HID_4b3d,
+ [590] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cb79,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 8593353728,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9504,18 +13072,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [447] = {
- .class_hid = BNXT_ULP_CLASS_HID_1291,
+ [591] = {
+ .class_hid = BNXT_ULP_CLASS_HID_93d1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 10738732032,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9528,17 +13096,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [448] = {
- .class_hid = BNXT_ULP_CLASS_HID_4419,
+ [592] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c459,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 10738740224,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9551,18 +13119,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [449] = {
- .class_hid = BNXT_ULP_CLASS_HID_22b5,
+ [593] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e2b1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 10740829184,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9575,18 +13143,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [450] = {
- .class_hid = BNXT_ULP_CLASS_HID_523d,
+ [594] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d339,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 10740837376,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9599,19 +13167,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [451] = {
- .class_hid = BNXT_ULP_CLASS_HID_1fb1,
+ [595] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9f31,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 12886215680,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9624,17 +13192,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [452] = {
- .class_hid = BNXT_ULP_CLASS_HID_31b9,
+ [596] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b1b1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 12886223872,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9647,18 +13215,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [453] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e95,
+ [597] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ee91,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 12888312832,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9671,18 +13239,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [454] = {
- .class_hid = BNXT_ULP_CLASS_HID_5f9d,
+ [598] = {
+ .class_hid = BNXT_ULP_CLASS_HID_df11,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 12888321024,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9695,19 +13263,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [455] = {
- .class_hid = BNXT_ULP_CLASS_HID_26b1,
+ [599] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a7f1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 15033699328,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9720,18 +13288,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [456] = {
- .class_hid = BNXT_ULP_CLASS_HID_58b9,
+ [600] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d871,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 15033707520,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9744,19 +13312,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [457] = {
- .class_hid = BNXT_ULP_CLASS_HID_3495,
+ [601] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f551,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 15035796480,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9769,19 +13337,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [458] = {
- .class_hid = BNXT_ULP_CLASS_HID_669d,
+ [602] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e7d1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 15035804672,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9794,20 +13362,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [459] = {
- .class_hid = BNXT_ULP_CLASS_HID_0e39,
+ [603] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8e1b,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 17181182976,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9820,16 +13388,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [460] = {
- .class_hid = BNXT_ULP_CLASS_HID_20a1,
+ [604] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a083,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 17181191168,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9842,17 +13410,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [461] = {
- .class_hid = BNXT_ULP_CLASS_HID_1dfd,
+ [605] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ddff,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 17183280128,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9865,17 +13433,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [462] = {
- .class_hid = BNXT_ULP_CLASS_HID_4e65,
+ [606] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ce67,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 17183288320,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9888,18 +13456,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [463] = {
- .class_hid = BNXT_ULP_CLASS_HID_16f9,
+ [607] = {
+ .class_hid = BNXT_ULP_CLASS_HID_96db,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 19328666624,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9912,17 +13480,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [464] = {
- .class_hid = BNXT_ULP_CLASS_HID_4661,
+ [608] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c753,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 19328674816,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9935,18 +13503,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [465] = {
- .class_hid = BNXT_ULP_CLASS_HID_24bd,
+ [609] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e5bf,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 19330763776,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9959,18 +13527,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [466] = {
- .class_hid = BNXT_ULP_CLASS_HID_5625,
+ [610] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d637,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 19330771968,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9983,19 +13551,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [467] = {
- .class_hid = BNXT_ULP_CLASS_HID_02b9,
+ [611] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8233,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 21476150272,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10008,17 +13576,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [468] = {
- .class_hid = BNXT_ULP_CLASS_HID_34a1,
+ [612] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b4a3,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 21476158464,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10031,18 +13599,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [469] = {
- .class_hid = BNXT_ULP_CLASS_HID_11bd,
+ [613] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d197,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 21478247424,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10055,18 +13623,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [470] = {
- .class_hid = BNXT_ULP_CLASS_HID_42a5,
+ [614] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c207,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 21478255616,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10079,19 +13647,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [471] = {
- .class_hid = BNXT_ULP_CLASS_HID_2af9,
+ [615] = {
+ .class_hid = BNXT_ULP_CLASS_HID_aaf3,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 23623633920,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10104,18 +13672,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [472] = {
- .class_hid = BNXT_ULP_CLASS_HID_5ae1,
+ [616] = {
+ .class_hid = BNXT_ULP_CLASS_HID_db73,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 23623642112,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10128,19 +13696,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [473] = {
- .class_hid = BNXT_ULP_CLASS_HID_38fd,
+ [617] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f857,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 23625731072,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10153,19 +13721,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [474] = {
- .class_hid = BNXT_ULP_CLASS_HID_6ae5,
+ [618] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ead7,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 23625739264,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10178,20 +13746,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [475] = {
- .class_hid = BNXT_ULP_CLASS_HID_0829,
+ [619] = {
+ .class_hid = BNXT_ULP_CLASS_HID_882b,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 25771117568,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10204,17 +13772,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [476] = {
- .class_hid = BNXT_ULP_CLASS_HID_3ab1,
+ [620] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ba93,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 25771125760,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10227,18 +13795,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [477] = {
- .class_hid = BNXT_ULP_CLASS_HID_17ad,
+ [621] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d78b,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 25773214720,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10251,18 +13819,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [478] = {
- .class_hid = BNXT_ULP_CLASS_HID_4835,
+ [622] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c873,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 25773222912,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10275,19 +13843,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [479] = {
- .class_hid = BNXT_ULP_CLASS_HID_10a9,
+ [623] = {
+ .class_hid = BNXT_ULP_CLASS_HID_90fb,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 27918601216,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10300,18 +13868,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [480] = {
- .class_hid = BNXT_ULP_CLASS_HID_4031,
+ [624] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c153,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 27918609408,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10324,19 +13892,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [481] = {
- .class_hid = BNXT_ULP_CLASS_HID_3e2d,
+ [625] = {
+ .class_hid = BNXT_ULP_CLASS_HID_fe5b,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 27920698368,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10349,19 +13917,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [482] = {
- .class_hid = BNXT_ULP_CLASS_HID_5035,
+ [626] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d033,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 27920706560,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10374,20 +13942,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [483] = {
- .class_hid = BNXT_ULP_CLASS_HID_1ca9,
+ [627] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9cc3,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 30066084864,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10400,18 +13968,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [484] = {
- .class_hid = BNXT_ULP_CLASS_HID_4eb1,
+ [628] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ceb3,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 30066093056,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10424,19 +13992,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [485] = {
- .class_hid = BNXT_ULP_CLASS_HID_2bad,
+ [629] = {
+ .class_hid = BNXT_ULP_CLASS_HID_eba3,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 30068182016,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10449,19 +14017,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [486] = {
- .class_hid = BNXT_ULP_CLASS_HID_5cb5,
+ [630] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dc13,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 30068190208,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10474,20 +14042,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [487] = {
- .class_hid = BNXT_ULP_CLASS_HID_24a9,
+ [631] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a493,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 32213568512,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10500,19 +14068,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [488] = {
- .class_hid = BNXT_ULP_CLASS_HID_54b1,
+ [632] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d573,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 32213576704,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10525,20 +14093,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [489] = {
- .class_hid = BNXT_ULP_CLASS_HID_32ad,
+ [633] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f273,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 32215665664,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10551,20 +14119,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [490] = {
- .class_hid = BNXT_ULP_CLASS_HID_0ca9,
+ [634] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cdb3,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 32215673856,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10577,21 +14145,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [491] = {
- .class_hid = BNXT_ULP_CLASS_HID_7f35,
+ [635] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ff35,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 1313792,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10604,15 +14172,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC }
},
- [492] = {
- .class_hid = BNXT_ULP_CLASS_HID_34f1,
+ [636] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b4f1,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 1321984,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10625,16 +14193,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC }
},
- [493] = {
- .class_hid = BNXT_ULP_CLASS_HID_179d,
+ [637] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d79d,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 3410944,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10647,16 +14215,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC }
},
- [494] = {
- .class_hid = BNXT_ULP_CLASS_HID_2615,
+ [638] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e615,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 3419136,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10669,17 +14237,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC }
},
- [495] = {
- .class_hid = BNXT_ULP_CLASS_HID_0fb9,
+ [639] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8ea9,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 2148797440,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10692,16 +14260,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
},
- [496] = {
- .class_hid = BNXT_ULP_CLASS_HID_5d31,
+ [640] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dd21,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 2148805632,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10714,17 +14282,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
},
- [497] = {
- .class_hid = BNXT_ULP_CLASS_HID_3fdd,
+ [641] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ffcd,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 2150894592,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10737,17 +14305,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
},
- [498] = {
- .class_hid = BNXT_ULP_CLASS_HID_4f55,
+ [642] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ce45,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 2150902784,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10760,18 +14328,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
},
- [499] = {
- .class_hid = BNXT_ULP_CLASS_HID_12d9,
+ [643] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9259,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 4296281088,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10784,16 +14352,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [500] = {
- .class_hid = BNXT_ULP_CLASS_HID_20d1,
+ [644] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a0d9,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 4296289280,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10806,17 +14374,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [501] = {
- .class_hid = BNXT_ULP_CLASS_HID_03fd,
+ [645] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c3fd,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 4298378240,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10829,17 +14397,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [502] = {
- .class_hid = BNXT_ULP_CLASS_HID_52f5,
+ [646] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d27d,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 4298386432,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10852,18 +14420,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [503] = {
- .class_hid = BNXT_ULP_CLASS_HID_3b99,
+ [647] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ba89,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 6443764736,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10876,17 +14444,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [504] = {
- .class_hid = BNXT_ULP_CLASS_HID_4991,
+ [648] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c909,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 6443772928,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10899,18 +14467,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [505] = {
- .class_hid = BNXT_ULP_CLASS_HID_2dbd,
+ [649] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ec2d,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 6445861888,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10923,18 +14491,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [506] = {
- .class_hid = BNXT_ULP_CLASS_HID_7bb5,
+ [650] = {
+ .class_hid = BNXT_ULP_CLASS_HID_faad,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 6445870080,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10947,16 +14515,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [507] = {
+ [651] = {
.class_hid = BNXT_ULP_CLASS_HID_34c6,
.class_tid = 3,
.hdr_sig_id = 0,
@@ -10971,7 +14539,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [508] = {
+ [652] = {
.class_hid = BNXT_ULP_CLASS_HID_0c22,
.class_tid = 3,
.hdr_sig_id = 0,
@@ -10987,7 +14555,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [509] = {
+ [653] = {
.class_hid = BNXT_ULP_CLASS_HID_1cbe,
.class_tid = 3,
.hdr_sig_id = 0,
@@ -11003,7 +14571,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [510] = {
+ [654] = {
.class_hid = BNXT_ULP_CLASS_HID_179a,
.class_tid = 3,
.hdr_sig_id = 0,
@@ -11020,7 +14588,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [511] = {
+ [655] = {
.class_hid = BNXT_ULP_CLASS_HID_59be,
.class_tid = 3,
.hdr_sig_id = 1,
@@ -11035,7 +14603,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [512] = {
+ [656] = {
.class_hid = BNXT_ULP_CLASS_HID_515a,
.class_tid = 3,
.hdr_sig_id = 1,
@@ -11051,7 +14619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [513] = {
+ [657] = {
.class_hid = BNXT_ULP_CLASS_HID_1c72,
.class_tid = 3,
.hdr_sig_id = 1,
@@ -11067,7 +14635,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [514] = {
+ [658] = {
.class_hid = BNXT_ULP_CLASS_HID_171e,
.class_tid = 3,
.hdr_sig_id = 1,
@@ -11084,7 +14652,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [515] = {
+ [659] = {
.class_hid = BNXT_ULP_CLASS_HID_19c8,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11100,7 +14668,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [516] = {
+ [660] = {
.class_hid = BNXT_ULP_CLASS_HID_112c,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11117,7 +14685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [517] = {
+ [661] = {
.class_hid = BNXT_ULP_CLASS_HID_4d68,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11134,7 +14702,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [518] = {
+ [662] = {
.class_hid = BNXT_ULP_CLASS_HID_444c,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11152,7 +14720,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [519] = {
+ [663] = {
.class_hid = BNXT_ULP_CLASS_HID_0e8c,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11169,7 +14737,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [520] = {
+ [664] = {
.class_hid = BNXT_ULP_CLASS_HID_09e0,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11187,7 +14755,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [521] = {
+ [665] = {
.class_hid = BNXT_ULP_CLASS_HID_1af0,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11205,7 +14773,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [522] = {
+ [666] = {
.class_hid = BNXT_ULP_CLASS_HID_15d4,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11224,7 +14792,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [523] = {
+ [667] = {
.class_hid = BNXT_ULP_CLASS_HID_1dd0,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11240,7 +14808,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [524] = {
+ [668] = {
.class_hid = BNXT_ULP_CLASS_HID_14f4,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11257,7 +14825,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [525] = {
+ [669] = {
.class_hid = BNXT_ULP_CLASS_HID_70b0,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11274,7 +14842,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [526] = {
+ [670] = {
.class_hid = BNXT_ULP_CLASS_HID_4854,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11292,7 +14860,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [527] = {
+ [671] = {
.class_hid = BNXT_ULP_CLASS_HID_3dd4,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11309,7 +14877,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [528] = {
+ [672] = {
.class_hid = BNXT_ULP_CLASS_HID_34f8,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11327,7 +14895,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [529] = {
+ [673] = {
.class_hid = BNXT_ULP_CLASS_HID_09e8,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11345,7 +14913,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [530] = {
+ [674] = {
.class_hid = BNXT_ULP_CLASS_HID_008c,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11364,7 +14932,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [531] = {
+ [675] = {
.class_hid = BNXT_ULP_CLASS_HID_34e6,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11380,7 +14948,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [532] = {
+ [676] = {
.class_hid = BNXT_ULP_CLASS_HID_0c02,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11397,7 +14965,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [533] = {
+ [677] = {
.class_hid = BNXT_ULP_CLASS_HID_1c9e,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11414,7 +14982,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [534] = {
+ [678] = {
.class_hid = BNXT_ULP_CLASS_HID_17ba,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11432,7 +15000,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [535] = {
+ [679] = {
.class_hid = BNXT_ULP_CLASS_HID_429e,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11449,7 +15017,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [536] = {
+ [680] = {
.class_hid = BNXT_ULP_CLASS_HID_5dba,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11467,7 +15035,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [537] = {
+ [681] = {
.class_hid = BNXT_ULP_CLASS_HID_2a16,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11485,7 +15053,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [538] = {
+ [682] = {
.class_hid = BNXT_ULP_CLASS_HID_2532,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11504,7 +15072,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [539] = {
+ [683] = {
.class_hid = BNXT_ULP_CLASS_HID_2da2,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11521,7 +15089,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [540] = {
+ [684] = {
.class_hid = BNXT_ULP_CLASS_HID_24fe,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11539,7 +15107,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [541] = {
+ [685] = {
.class_hid = BNXT_ULP_CLASS_HID_355a,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11557,7 +15125,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [542] = {
+ [686] = {
.class_hid = BNXT_ULP_CLASS_HID_0c76,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11576,7 +15144,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [543] = {
+ [687] = {
.class_hid = BNXT_ULP_CLASS_HID_13e6,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11594,7 +15162,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [544] = {
+ [688] = {
.class_hid = BNXT_ULP_CLASS_HID_7276,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11613,7 +15181,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [545] = {
+ [689] = {
.class_hid = BNXT_ULP_CLASS_HID_42d2,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11632,7 +15200,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [546] = {
+ [690] = {
.class_hid = BNXT_ULP_CLASS_HID_5dee,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11652,7 +15220,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [547] = {
+ [691] = {
.class_hid = BNXT_ULP_CLASS_HID_59de,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11668,7 +15236,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [548] = {
+ [692] = {
.class_hid = BNXT_ULP_CLASS_HID_513a,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11685,7 +15253,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [549] = {
+ [693] = {
.class_hid = BNXT_ULP_CLASS_HID_1c12,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11702,7 +15270,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [550] = {
+ [694] = {
.class_hid = BNXT_ULP_CLASS_HID_177e,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11720,7 +15288,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [551] = {
+ [695] = {
.class_hid = BNXT_ULP_CLASS_HID_0e92,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11737,7 +15305,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [552] = {
+ [696] = {
.class_hid = BNXT_ULP_CLASS_HID_09fe,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11755,7 +15323,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [553] = {
+ [697] = {
.class_hid = BNXT_ULP_CLASS_HID_5c1a,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11773,7 +15341,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [554] = {
+ [698] = {
.class_hid = BNXT_ULP_CLASS_HID_5746,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11792,7 +15360,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [555] = {
+ [699] = {
.class_hid = BNXT_ULP_CLASS_HID_79da,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11809,7 +15377,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [556] = {
+ [700] = {
.class_hid = BNXT_ULP_CLASS_HID_7106,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11827,7 +15395,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [557] = {
+ [701] = {
.class_hid = BNXT_ULP_CLASS_HID_3c1e,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11845,7 +15413,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [558] = {
+ [702] = {
.class_hid = BNXT_ULP_CLASS_HID_377a,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11864,7 +15432,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [559] = {
+ [703] = {
.class_hid = BNXT_ULP_CLASS_HID_2e9e,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11882,7 +15450,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [560] = {
+ [704] = {
.class_hid = BNXT_ULP_CLASS_HID_29fa,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11901,7 +15469,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [561] = {
+ [705] = {
.class_hid = BNXT_ULP_CLASS_HID_14d2,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11920,7 +15488,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [562] = {
+ [706] = {
.class_hid = BNXT_ULP_CLASS_HID_7742,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11940,7 +15508,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [563] = {
+ [707] = {
.class_hid = BNXT_ULP_CLASS_HID_3706,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -11956,7 +15524,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [564] = {
+ [708] = {
.class_hid = BNXT_ULP_CLASS_HID_0fe2,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -11973,7 +15541,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [565] = {
+ [709] = {
.class_hid = BNXT_ULP_CLASS_HID_1f7e,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -11990,7 +15558,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [566] = {
+ [710] = {
.class_hid = BNXT_ULP_CLASS_HID_145a,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12008,7 +15576,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [567] = {
+ [711] = {
.class_hid = BNXT_ULP_CLASS_HID_417e,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12025,7 +15593,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [568] = {
+ [712] = {
.class_hid = BNXT_ULP_CLASS_HID_5e5a,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12043,7 +15611,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [569] = {
+ [713] = {
.class_hid = BNXT_ULP_CLASS_HID_29f6,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12061,7 +15629,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [570] = {
+ [714] = {
.class_hid = BNXT_ULP_CLASS_HID_26d2,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12080,7 +15648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [571] = {
+ [715] = {
.class_hid = BNXT_ULP_CLASS_HID_2e42,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12097,7 +15665,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [572] = {
+ [716] = {
.class_hid = BNXT_ULP_CLASS_HID_271e,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12115,7 +15683,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [573] = {
+ [717] = {
.class_hid = BNXT_ULP_CLASS_HID_36ba,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12133,7 +15701,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [574] = {
+ [718] = {
.class_hid = BNXT_ULP_CLASS_HID_0f96,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12152,7 +15720,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [575] = {
+ [719] = {
.class_hid = BNXT_ULP_CLASS_HID_1006,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12170,7 +15738,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [576] = {
+ [720] = {
.class_hid = BNXT_ULP_CLASS_HID_7196,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12189,7 +15757,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [577] = {
+ [721] = {
.class_hid = BNXT_ULP_CLASS_HID_4132,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12208,7 +15776,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [578] = {
+ [722] = {
.class_hid = BNXT_ULP_CLASS_HID_5e0e,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12228,7 +15796,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [579] = {
+ [723] = {
.class_hid = BNXT_ULP_CLASS_HID_59fe,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12244,7 +15812,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [580] = {
+ [724] = {
.class_hid = BNXT_ULP_CLASS_HID_511a,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12261,7 +15829,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [581] = {
+ [725] = {
.class_hid = BNXT_ULP_CLASS_HID_1c32,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12278,7 +15846,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [582] = {
+ [726] = {
.class_hid = BNXT_ULP_CLASS_HID_175e,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12296,7 +15864,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [583] = {
+ [727] = {
.class_hid = BNXT_ULP_CLASS_HID_0eb2,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12313,7 +15881,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [584] = {
+ [728] = {
.class_hid = BNXT_ULP_CLASS_HID_09de,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12331,7 +15899,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [585] = {
+ [729] = {
.class_hid = BNXT_ULP_CLASS_HID_5c3a,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12349,7 +15917,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [586] = {
+ [730] = {
.class_hid = BNXT_ULP_CLASS_HID_5766,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12368,7 +15936,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [587] = {
+ [731] = {
.class_hid = BNXT_ULP_CLASS_HID_79fa,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12385,7 +15953,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [588] = {
+ [732] = {
.class_hid = BNXT_ULP_CLASS_HID_7126,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12403,7 +15971,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [589] = {
+ [733] = {
.class_hid = BNXT_ULP_CLASS_HID_3c3e,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12421,7 +15989,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [590] = {
+ [734] = {
.class_hid = BNXT_ULP_CLASS_HID_375a,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12440,7 +16008,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [591] = {
+ [735] = {
.class_hid = BNXT_ULP_CLASS_HID_2ebe,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12458,7 +16026,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [592] = {
+ [736] = {
.class_hid = BNXT_ULP_CLASS_HID_29da,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12477,7 +16045,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [593] = {
+ [737] = {
.class_hid = BNXT_ULP_CLASS_HID_14f2,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12496,7 +16064,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [594] = {
+ [738] = {
.class_hid = BNXT_ULP_CLASS_HID_7762,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12516,7 +16084,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [595] = {
+ [739] = {
.class_hid = BNXT_ULP_CLASS_HID_19e8,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12533,7 +16101,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [596] = {
+ [740] = {
.class_hid = BNXT_ULP_CLASS_HID_110c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12551,7 +16119,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [597] = {
+ [741] = {
.class_hid = BNXT_ULP_CLASS_HID_4d48,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12569,7 +16137,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [598] = {
+ [742] = {
.class_hid = BNXT_ULP_CLASS_HID_446c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12588,7 +16156,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [599] = {
+ [743] = {
.class_hid = BNXT_ULP_CLASS_HID_0eac,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12606,7 +16174,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [600] = {
+ [744] = {
.class_hid = BNXT_ULP_CLASS_HID_09c0,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12625,7 +16193,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [601] = {
+ [745] = {
.class_hid = BNXT_ULP_CLASS_HID_1ad0,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12644,7 +16212,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [602] = {
+ [746] = {
.class_hid = BNXT_ULP_CLASS_HID_15f4,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12664,7 +16232,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [603] = {
+ [747] = {
.class_hid = BNXT_ULP_CLASS_HID_39ec,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12682,7 +16250,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [604] = {
+ [748] = {
.class_hid = BNXT_ULP_CLASS_HID_3100,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12701,7 +16269,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [605] = {
+ [749] = {
.class_hid = BNXT_ULP_CLASS_HID_0210,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12720,7 +16288,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [606] = {
+ [750] = {
.class_hid = BNXT_ULP_CLASS_HID_1d34,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12740,7 +16308,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [607] = {
+ [751] = {
.class_hid = BNXT_ULP_CLASS_HID_2ea0,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12759,7 +16327,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [608] = {
+ [752] = {
.class_hid = BNXT_ULP_CLASS_HID_29c4,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12779,7 +16347,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [609] = {
+ [753] = {
.class_hid = BNXT_ULP_CLASS_HID_3ad4,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12799,7 +16367,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [610] = {
+ [754] = {
.class_hid = BNXT_ULP_CLASS_HID_35e8,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12820,7 +16388,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [611] = {
+ [755] = {
.class_hid = BNXT_ULP_CLASS_HID_5d80,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12838,7 +16406,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [612] = {
+ [756] = {
.class_hid = BNXT_ULP_CLASS_HID_54a4,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12857,7 +16425,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [613] = {
+ [757] = {
.class_hid = BNXT_ULP_CLASS_HID_29b4,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12876,7 +16444,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [614] = {
+ [758] = {
.class_hid = BNXT_ULP_CLASS_HID_20c8,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12896,7 +16464,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [615] = {
+ [759] = {
.class_hid = BNXT_ULP_CLASS_HID_7244,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12915,7 +16483,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [616] = {
+ [760] = {
.class_hid = BNXT_ULP_CLASS_HID_4d98,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12935,7 +16503,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [617] = {
+ [761] = {
.class_hid = BNXT_ULP_CLASS_HID_5e68,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12955,7 +16523,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [618] = {
+ [762] = {
.class_hid = BNXT_ULP_CLASS_HID_598c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12976,7 +16544,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [619] = {
+ [763] = {
.class_hid = BNXT_ULP_CLASS_HID_1248,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12995,7 +16563,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [620] = {
+ [764] = {
.class_hid = BNXT_ULP_CLASS_HID_74d8,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -13015,7 +16583,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [621] = {
+ [765] = {
.class_hid = BNXT_ULP_CLASS_HID_49a8,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -13035,7 +16603,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [622] = {
+ [766] = {
.class_hid = BNXT_ULP_CLASS_HID_40cc,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -13056,7 +16624,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [623] = {
+ [767] = {
.class_hid = BNXT_ULP_CLASS_HID_0b0c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -13076,7 +16644,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [624] = {
+ [768] = {
.class_hid = BNXT_ULP_CLASS_HID_0220,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -13097,7 +16665,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [625] = {
+ [769] = {
.class_hid = BNXT_ULP_CLASS_HID_1730,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -13118,7 +16686,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [626] = {
+ [770] = {
.class_hid = BNXT_ULP_CLASS_HID_7980,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -13140,7 +16708,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [627] = {
+ [771] = {
.class_hid = BNXT_ULP_CLASS_HID_1db0,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13157,7 +16725,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [628] = {
+ [772] = {
.class_hid = BNXT_ULP_CLASS_HID_1494,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13175,7 +16743,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [629] = {
+ [773] = {
.class_hid = BNXT_ULP_CLASS_HID_70d0,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13193,7 +16761,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [630] = {
+ [774] = {
.class_hid = BNXT_ULP_CLASS_HID_4834,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13212,7 +16780,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [631] = {
+ [775] = {
.class_hid = BNXT_ULP_CLASS_HID_3db4,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13230,7 +16798,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [632] = {
+ [776] = {
.class_hid = BNXT_ULP_CLASS_HID_3498,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13249,7 +16817,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [633] = {
+ [777] = {
.class_hid = BNXT_ULP_CLASS_HID_0988,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13268,7 +16836,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [634] = {
+ [778] = {
.class_hid = BNXT_ULP_CLASS_HID_00ec,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13288,7 +16856,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [635] = {
+ [779] = {
.class_hid = BNXT_ULP_CLASS_HID_3f44,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13306,7 +16874,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [636] = {
+ [780] = {
.class_hid = BNXT_ULP_CLASS_HID_36a8,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13325,7 +16893,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [637] = {
+ [781] = {
.class_hid = BNXT_ULP_CLASS_HID_0b58,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13344,7 +16912,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [638] = {
+ [782] = {
.class_hid = BNXT_ULP_CLASS_HID_02bc,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13364,7 +16932,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [639] = {
+ [783] = {
.class_hid = BNXT_ULP_CLASS_HID_5f48,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13383,7 +16951,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [640] = {
+ [784] = {
.class_hid = BNXT_ULP_CLASS_HID_56ac,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13403,7 +16971,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [641] = {
+ [785] = {
.class_hid = BNXT_ULP_CLASS_HID_2b5c,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13423,7 +16991,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [642] = {
+ [786] = {
.class_hid = BNXT_ULP_CLASS_HID_2280,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13444,7 +17012,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [643] = {
+ [787] = {
.class_hid = BNXT_ULP_CLASS_HID_4000,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13462,7 +17030,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [644] = {
+ [788] = {
.class_hid = BNXT_ULP_CLASS_HID_5b64,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13481,7 +17049,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [645] = {
+ [789] = {
.class_hid = BNXT_ULP_CLASS_HID_2c14,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13500,7 +17068,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [646] = {
+ [790] = {
.class_hid = BNXT_ULP_CLASS_HID_2778,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13520,7 +17088,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [647] = {
+ [791] = {
.class_hid = BNXT_ULP_CLASS_HID_18f8,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13539,7 +17107,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [648] = {
+ [792] = {
.class_hid = BNXT_ULP_CLASS_HID_13dc,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13559,7 +17127,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [649] = {
+ [793] = {
.class_hid = BNXT_ULP_CLASS_HID_4c18,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13579,7 +17147,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [650] = {
+ [794] = {
.class_hid = BNXT_ULP_CLASS_HID_477c,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13600,7 +17168,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [651] = {
+ [795] = {
.class_hid = BNXT_ULP_CLASS_HID_1a88,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13619,7 +17187,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [652] = {
+ [796] = {
.class_hid = BNXT_ULP_CLASS_HID_15ec,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13639,7 +17207,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [653] = {
+ [797] = {
.class_hid = BNXT_ULP_CLASS_HID_4e28,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13659,7 +17227,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [654] = {
+ [798] = {
.class_hid = BNXT_ULP_CLASS_HID_490c,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13680,7 +17248,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [655] = {
+ [799] = {
.class_hid = BNXT_ULP_CLASS_HID_3a8c,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13700,7 +17268,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [656] = {
+ [800] = {
.class_hid = BNXT_ULP_CLASS_HID_35f0,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13721,7 +17289,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [657] = {
+ [801] = {
.class_hid = BNXT_ULP_CLASS_HID_06e0,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13742,7 +17310,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [658] = {
+ [802] = {
.class_hid = BNXT_ULP_CLASS_HID_01c4,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13764,7 +17332,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [659] = {
+ [803] = {
.class_hid = BNXT_ULP_CLASS_HID_1a08,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13781,7 +17349,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [660] = {
+ [804] = {
.class_hid = BNXT_ULP_CLASS_HID_12ec,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13799,7 +17367,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [661] = {
+ [805] = {
.class_hid = BNXT_ULP_CLASS_HID_4ea8,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13817,7 +17385,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [662] = {
+ [806] = {
.class_hid = BNXT_ULP_CLASS_HID_478c,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13836,7 +17404,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [663] = {
+ [807] = {
.class_hid = BNXT_ULP_CLASS_HID_0d4c,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13854,7 +17422,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [664] = {
+ [808] = {
.class_hid = BNXT_ULP_CLASS_HID_0a20,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13873,7 +17441,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [665] = {
+ [809] = {
.class_hid = BNXT_ULP_CLASS_HID_1930,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13892,7 +17460,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [666] = {
+ [810] = {
.class_hid = BNXT_ULP_CLASS_HID_1614,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13912,7 +17480,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [667] = {
+ [811] = {
.class_hid = BNXT_ULP_CLASS_HID_3a0c,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13930,7 +17498,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [668] = {
+ [812] = {
.class_hid = BNXT_ULP_CLASS_HID_32e0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13949,7 +17517,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [669] = {
+ [813] = {
.class_hid = BNXT_ULP_CLASS_HID_01f0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13968,7 +17536,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [670] = {
+ [814] = {
.class_hid = BNXT_ULP_CLASS_HID_1ed4,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13988,7 +17556,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [671] = {
+ [815] = {
.class_hid = BNXT_ULP_CLASS_HID_2d40,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14007,7 +17575,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [672] = {
+ [816] = {
.class_hid = BNXT_ULP_CLASS_HID_2a24,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14027,7 +17595,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [673] = {
+ [817] = {
.class_hid = BNXT_ULP_CLASS_HID_3934,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14047,7 +17615,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [674] = {
+ [818] = {
.class_hid = BNXT_ULP_CLASS_HID_3608,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14068,7 +17636,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [675] = {
+ [819] = {
.class_hid = BNXT_ULP_CLASS_HID_5e60,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14086,7 +17654,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [676] = {
+ [820] = {
.class_hid = BNXT_ULP_CLASS_HID_5744,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14105,7 +17673,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [677] = {
+ [821] = {
.class_hid = BNXT_ULP_CLASS_HID_2a54,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14124,7 +17692,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [678] = {
+ [822] = {
.class_hid = BNXT_ULP_CLASS_HID_2328,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14144,7 +17712,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [679] = {
+ [823] = {
.class_hid = BNXT_ULP_CLASS_HID_71a4,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14163,7 +17731,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [680] = {
+ [824] = {
.class_hid = BNXT_ULP_CLASS_HID_4e78,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14183,7 +17751,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [681] = {
+ [825] = {
.class_hid = BNXT_ULP_CLASS_HID_5d88,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14203,7 +17771,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [682] = {
+ [826] = {
.class_hid = BNXT_ULP_CLASS_HID_5a6c,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14224,7 +17792,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [683] = {
+ [827] = {
.class_hid = BNXT_ULP_CLASS_HID_11a8,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14243,7 +17811,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [684] = {
+ [828] = {
.class_hid = BNXT_ULP_CLASS_HID_7738,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14263,7 +17831,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [685] = {
+ [829] = {
.class_hid = BNXT_ULP_CLASS_HID_4a48,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14283,7 +17851,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [686] = {
+ [830] = {
.class_hid = BNXT_ULP_CLASS_HID_432c,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14304,7 +17872,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [687] = {
+ [831] = {
.class_hid = BNXT_ULP_CLASS_HID_08ec,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14324,7 +17892,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [688] = {
+ [832] = {
.class_hid = BNXT_ULP_CLASS_HID_01c0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14345,7 +17913,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [689] = {
+ [833] = {
.class_hid = BNXT_ULP_CLASS_HID_14d0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14366,7 +17934,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [690] = {
+ [834] = {
.class_hid = BNXT_ULP_CLASS_HID_7a60,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14388,7 +17956,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [691] = {
+ [835] = {
.class_hid = BNXT_ULP_CLASS_HID_1d90,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14405,7 +17973,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [692] = {
+ [836] = {
.class_hid = BNXT_ULP_CLASS_HID_14b4,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14423,7 +17991,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [693] = {
+ [837] = {
.class_hid = BNXT_ULP_CLASS_HID_70f0,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14441,7 +18009,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [694] = {
+ [838] = {
.class_hid = BNXT_ULP_CLASS_HID_4814,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14460,7 +18028,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [695] = {
+ [839] = {
.class_hid = BNXT_ULP_CLASS_HID_3d94,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14478,7 +18046,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [696] = {
+ [840] = {
.class_hid = BNXT_ULP_CLASS_HID_34b8,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14497,7 +18065,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [697] = {
+ [841] = {
.class_hid = BNXT_ULP_CLASS_HID_09a8,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14516,7 +18084,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [698] = {
+ [842] = {
.class_hid = BNXT_ULP_CLASS_HID_00cc,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14536,7 +18104,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [699] = {
+ [843] = {
.class_hid = BNXT_ULP_CLASS_HID_3f64,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14554,7 +18122,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [700] = {
+ [844] = {
.class_hid = BNXT_ULP_CLASS_HID_3688,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14573,7 +18141,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [701] = {
+ [845] = {
.class_hid = BNXT_ULP_CLASS_HID_0b78,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14592,7 +18160,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [702] = {
+ [846] = {
.class_hid = BNXT_ULP_CLASS_HID_029c,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14612,7 +18180,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [703] = {
+ [847] = {
.class_hid = BNXT_ULP_CLASS_HID_5f68,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14631,7 +18199,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [704] = {
+ [848] = {
.class_hid = BNXT_ULP_CLASS_HID_568c,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14651,7 +18219,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [705] = {
+ [849] = {
.class_hid = BNXT_ULP_CLASS_HID_2b7c,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14671,7 +18239,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [706] = {
+ [850] = {
.class_hid = BNXT_ULP_CLASS_HID_22a0,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14692,7 +18260,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [707] = {
+ [851] = {
.class_hid = BNXT_ULP_CLASS_HID_4020,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14710,7 +18278,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [708] = {
+ [852] = {
.class_hid = BNXT_ULP_CLASS_HID_5b44,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14729,7 +18297,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [709] = {
+ [853] = {
.class_hid = BNXT_ULP_CLASS_HID_2c34,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14748,7 +18316,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [710] = {
+ [854] = {
.class_hid = BNXT_ULP_CLASS_HID_2758,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14768,7 +18336,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [711] = {
+ [855] = {
.class_hid = BNXT_ULP_CLASS_HID_18d8,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14787,7 +18355,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [712] = {
+ [856] = {
.class_hid = BNXT_ULP_CLASS_HID_13fc,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14807,7 +18375,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [713] = {
+ [857] = {
.class_hid = BNXT_ULP_CLASS_HID_4c38,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14827,7 +18395,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [714] = {
+ [858] = {
.class_hid = BNXT_ULP_CLASS_HID_475c,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14848,7 +18416,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [715] = {
+ [859] = {
.class_hid = BNXT_ULP_CLASS_HID_1aa8,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14867,7 +18435,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [716] = {
+ [860] = {
.class_hid = BNXT_ULP_CLASS_HID_15cc,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14887,7 +18455,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [717] = {
+ [861] = {
.class_hid = BNXT_ULP_CLASS_HID_4e08,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14907,7 +18475,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [718] = {
+ [862] = {
.class_hid = BNXT_ULP_CLASS_HID_492c,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14928,7 +18496,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [719] = {
+ [863] = {
.class_hid = BNXT_ULP_CLASS_HID_3aac,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14948,7 +18516,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [720] = {
+ [864] = {
.class_hid = BNXT_ULP_CLASS_HID_35d0,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14969,7 +18537,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [721] = {
+ [865] = {
.class_hid = BNXT_ULP_CLASS_HID_06c0,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14990,7 +18558,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [722] = {
+ [866] = {
.class_hid = BNXT_ULP_CLASS_HID_01e4,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -15012,7 +18580,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [723] = {
+ [867] = {
.class_hid = BNXT_ULP_CLASS_HID_4d32,
.class_tid = 3,
.hdr_sig_id = 0,
@@ -15026,7 +18594,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [724] = {
+ [868] = {
.class_hid = BNXT_ULP_CLASS_HID_54aa,
.class_tid = 3,
.hdr_sig_id = 0,
@@ -15041,7 +18609,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [725] = {
+ [869] = {
.class_hid = BNXT_ULP_CLASS_HID_0686,
.class_tid = 3,
.hdr_sig_id = 1,
@@ -15055,7 +18623,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [726] = {
+ [870] = {
.class_hid = BNXT_ULP_CLASS_HID_540e,
.class_tid = 3,
.hdr_sig_id = 1,
@@ -15070,7 +18638,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [727] = {
+ [871] = {
.class_hid = BNXT_ULP_CLASS_HID_2e3c,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -15085,7 +18653,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [728] = {
+ [872] = {
.class_hid = BNXT_ULP_CLASS_HID_3a20,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -15101,7 +18669,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [729] = {
+ [873] = {
.class_hid = BNXT_ULP_CLASS_HID_46f0,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -15117,7 +18685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [730] = {
+ [874] = {
.class_hid = BNXT_ULP_CLASS_HID_52e4,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -15134,7 +18702,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [731] = {
+ [875] = {
.class_hid = BNXT_ULP_CLASS_HID_55e4,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -15149,7 +18717,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [732] = {
+ [876] = {
.class_hid = BNXT_ULP_CLASS_HID_21f8,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -15165,7 +18733,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [733] = {
+ [877] = {
.class_hid = BNXT_ULP_CLASS_HID_75e8,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -15181,7 +18749,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [734] = {
+ [878] = {
.class_hid = BNXT_ULP_CLASS_HID_41fc,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -15198,7 +18766,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [735] = {
+ [879] = {
.class_hid = BNXT_ULP_CLASS_HID_4d12,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15213,7 +18781,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [736] = {
+ [880] = {
.class_hid = BNXT_ULP_CLASS_HID_548a,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15229,7 +18797,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [737] = {
+ [881] = {
.class_hid = BNXT_ULP_CLASS_HID_3356,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15245,7 +18813,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [738] = {
+ [882] = {
.class_hid = BNXT_ULP_CLASS_HID_1ace,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15262,7 +18830,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [739] = {
+ [883] = {
.class_hid = BNXT_ULP_CLASS_HID_1a9a,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15278,7 +18846,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [740] = {
+ [884] = {
.class_hid = BNXT_ULP_CLASS_HID_4d46,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15295,7 +18863,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [741] = {
+ [885] = {
.class_hid = BNXT_ULP_CLASS_HID_2812,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15312,7 +18880,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [742] = {
+ [886] = {
.class_hid = BNXT_ULP_CLASS_HID_338a,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15330,7 +18898,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [743] = {
+ [887] = {
.class_hid = BNXT_ULP_CLASS_HID_06e6,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15345,7 +18913,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [744] = {
+ [888] = {
.class_hid = BNXT_ULP_CLASS_HID_546e,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15361,7 +18929,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [745] = {
+ [889] = {
.class_hid = BNXT_ULP_CLASS_HID_46ee,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15377,7 +18945,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [746] = {
+ [890] = {
.class_hid = BNXT_ULP_CLASS_HID_0d22,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15394,7 +18962,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [747] = {
+ [891] = {
.class_hid = BNXT_ULP_CLASS_HID_26e2,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15410,7 +18978,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [748] = {
+ [892] = {
.class_hid = BNXT_ULP_CLASS_HID_746a,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15427,7 +18995,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [749] = {
+ [893] = {
.class_hid = BNXT_ULP_CLASS_HID_1fa6,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15444,7 +19012,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [750] = {
+ [894] = {
.class_hid = BNXT_ULP_CLASS_HID_2d2e,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15462,7 +19030,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [751] = {
+ [895] = {
.class_hid = BNXT_ULP_CLASS_HID_4ef2,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15477,7 +19045,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [752] = {
+ [896] = {
.class_hid = BNXT_ULP_CLASS_HID_576a,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15493,7 +19061,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [753] = {
+ [897] = {
.class_hid = BNXT_ULP_CLASS_HID_30b6,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15509,7 +19077,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [754] = {
+ [898] = {
.class_hid = BNXT_ULP_CLASS_HID_192e,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15526,7 +19094,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [755] = {
+ [899] = {
.class_hid = BNXT_ULP_CLASS_HID_197a,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15542,7 +19110,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [756] = {
+ [900] = {
.class_hid = BNXT_ULP_CLASS_HID_4ea6,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15559,7 +19127,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [757] = {
+ [901] = {
.class_hid = BNXT_ULP_CLASS_HID_2bf2,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15576,7 +19144,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [758] = {
+ [902] = {
.class_hid = BNXT_ULP_CLASS_HID_306a,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15594,7 +19162,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [759] = {
+ [903] = {
.class_hid = BNXT_ULP_CLASS_HID_06c6,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15609,7 +19177,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [760] = {
+ [904] = {
.class_hid = BNXT_ULP_CLASS_HID_544e,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15625,7 +19193,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [761] = {
+ [905] = {
.class_hid = BNXT_ULP_CLASS_HID_46ce,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15641,7 +19209,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [762] = {
+ [906] = {
.class_hid = BNXT_ULP_CLASS_HID_0d02,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15658,7 +19226,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [763] = {
+ [907] = {
.class_hid = BNXT_ULP_CLASS_HID_26c2,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15674,7 +19242,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [764] = {
+ [908] = {
.class_hid = BNXT_ULP_CLASS_HID_744a,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15691,7 +19259,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [765] = {
+ [909] = {
.class_hid = BNXT_ULP_CLASS_HID_1f86,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15708,7 +19276,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [766] = {
+ [910] = {
.class_hid = BNXT_ULP_CLASS_HID_2d0e,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15726,7 +19294,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [767] = {
+ [911] = {
.class_hid = BNXT_ULP_CLASS_HID_2e1c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15742,7 +19310,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [768] = {
+ [912] = {
.class_hid = BNXT_ULP_CLASS_HID_3a00,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15759,7 +19327,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [769] = {
+ [913] = {
.class_hid = BNXT_ULP_CLASS_HID_46d0,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15776,7 +19344,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [770] = {
+ [914] = {
.class_hid = BNXT_ULP_CLASS_HID_52c4,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15794,7 +19362,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [771] = {
+ [915] = {
.class_hid = BNXT_ULP_CLASS_HID_4e10,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15811,7 +19379,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [772] = {
+ [916] = {
.class_hid = BNXT_ULP_CLASS_HID_5a04,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15829,7 +19397,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [773] = {
+ [917] = {
.class_hid = BNXT_ULP_CLASS_HID_1f98,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15847,7 +19415,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [774] = {
+ [918] = {
.class_hid = BNXT_ULP_CLASS_HID_72f8,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15866,7 +19434,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [775] = {
+ [919] = {
.class_hid = BNXT_ULP_CLASS_HID_0a78,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15883,7 +19451,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [776] = {
+ [920] = {
.class_hid = BNXT_ULP_CLASS_HID_166c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15901,7 +19469,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [777] = {
+ [921] = {
.class_hid = BNXT_ULP_CLASS_HID_233c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15919,7 +19487,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [778] = {
+ [922] = {
.class_hid = BNXT_ULP_CLASS_HID_0f20,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15938,7 +19506,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [779] = {
+ [923] = {
.class_hid = BNXT_ULP_CLASS_HID_2a7c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15956,7 +19524,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [780] = {
+ [924] = {
.class_hid = BNXT_ULP_CLASS_HID_3660,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15975,7 +19543,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [781] = {
+ [925] = {
.class_hid = BNXT_ULP_CLASS_HID_4330,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15994,7 +19562,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [782] = {
+ [926] = {
.class_hid = BNXT_ULP_CLASS_HID_2f24,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -16014,7 +19582,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [783] = {
+ [927] = {
.class_hid = BNXT_ULP_CLASS_HID_5584,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16030,7 +19598,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [784] = {
+ [928] = {
.class_hid = BNXT_ULP_CLASS_HID_2198,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16047,7 +19615,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [785] = {
+ [929] = {
.class_hid = BNXT_ULP_CLASS_HID_7588,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16064,7 +19632,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [786] = {
+ [930] = {
.class_hid = BNXT_ULP_CLASS_HID_419c,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16082,7 +19650,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [787] = {
+ [931] = {
.class_hid = BNXT_ULP_CLASS_HID_7758,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16099,7 +19667,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [788] = {
+ [932] = {
.class_hid = BNXT_ULP_CLASS_HID_43ac,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16117,7 +19685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [789] = {
+ [933] = {
.class_hid = BNXT_ULP_CLASS_HID_0c10,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16135,7 +19703,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [790] = {
+ [934] = {
.class_hid = BNXT_ULP_CLASS_HID_1864,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16154,7 +19722,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [791] = {
+ [935] = {
.class_hid = BNXT_ULP_CLASS_HID_30c8,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16171,7 +19739,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [792] = {
+ [936] = {
.class_hid = BNXT_ULP_CLASS_HID_1cdc,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16189,7 +19757,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [793] = {
+ [937] = {
.class_hid = BNXT_ULP_CLASS_HID_50cc,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16207,7 +19775,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [794] = {
+ [938] = {
.class_hid = BNXT_ULP_CLASS_HID_3d20,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16226,7 +19794,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [795] = {
+ [939] = {
.class_hid = BNXT_ULP_CLASS_HID_529c,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16244,7 +19812,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [796] = {
+ [940] = {
.class_hid = BNXT_ULP_CLASS_HID_3ef0,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16263,7 +19831,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [797] = {
+ [941] = {
.class_hid = BNXT_ULP_CLASS_HID_72e0,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16282,7 +19850,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [798] = {
+ [942] = {
.class_hid = BNXT_ULP_CLASS_HID_5ef4,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16302,7 +19870,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [799] = {
+ [943] = {
.class_hid = BNXT_ULP_CLASS_HID_2dfc,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16318,7 +19886,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [800] = {
+ [944] = {
.class_hid = BNXT_ULP_CLASS_HID_39e0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16335,7 +19903,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [801] = {
+ [945] = {
.class_hid = BNXT_ULP_CLASS_HID_4530,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16352,7 +19920,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [802] = {
+ [946] = {
.class_hid = BNXT_ULP_CLASS_HID_5124,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16370,7 +19938,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [803] = {
+ [947] = {
.class_hid = BNXT_ULP_CLASS_HID_4df0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16387,7 +19955,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [804] = {
+ [948] = {
.class_hid = BNXT_ULP_CLASS_HID_59e4,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16405,7 +19973,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [805] = {
+ [949] = {
.class_hid = BNXT_ULP_CLASS_HID_1c78,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16423,7 +19991,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [806] = {
+ [950] = {
.class_hid = BNXT_ULP_CLASS_HID_7118,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16442,7 +20010,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [807] = {
+ [951] = {
.class_hid = BNXT_ULP_CLASS_HID_0998,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16459,7 +20027,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [808] = {
+ [952] = {
.class_hid = BNXT_ULP_CLASS_HID_158c,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16477,7 +20045,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [809] = {
+ [953] = {
.class_hid = BNXT_ULP_CLASS_HID_20dc,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16495,7 +20063,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [810] = {
+ [954] = {
.class_hid = BNXT_ULP_CLASS_HID_0cc0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16514,7 +20082,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [811] = {
+ [955] = {
.class_hid = BNXT_ULP_CLASS_HID_299c,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16532,7 +20100,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [812] = {
+ [956] = {
.class_hid = BNXT_ULP_CLASS_HID_3580,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16551,7 +20119,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [813] = {
+ [957] = {
.class_hid = BNXT_ULP_CLASS_HID_40d0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16570,7 +20138,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [814] = {
+ [958] = {
.class_hid = BNXT_ULP_CLASS_HID_2cc4,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16590,7 +20158,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [815] = {
+ [959] = {
.class_hid = BNXT_ULP_CLASS_HID_55a4,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16606,7 +20174,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [816] = {
+ [960] = {
.class_hid = BNXT_ULP_CLASS_HID_21b8,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16623,7 +20191,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [817] = {
+ [961] = {
.class_hid = BNXT_ULP_CLASS_HID_75a8,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16640,7 +20208,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [818] = {
+ [962] = {
.class_hid = BNXT_ULP_CLASS_HID_41bc,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16658,7 +20226,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [819] = {
+ [963] = {
.class_hid = BNXT_ULP_CLASS_HID_7778,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16675,7 +20243,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [820] = {
+ [964] = {
.class_hid = BNXT_ULP_CLASS_HID_438c,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16693,7 +20261,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [821] = {
+ [965] = {
.class_hid = BNXT_ULP_CLASS_HID_0c30,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16711,7 +20279,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [822] = {
+ [966] = {
.class_hid = BNXT_ULP_CLASS_HID_1844,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16730,7 +20298,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [823] = {
+ [967] = {
.class_hid = BNXT_ULP_CLASS_HID_30e8,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16747,7 +20315,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [824] = {
+ [968] = {
.class_hid = BNXT_ULP_CLASS_HID_1cfc,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16765,7 +20333,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [825] = {
+ [969] = {
.class_hid = BNXT_ULP_CLASS_HID_50ec,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16783,7 +20351,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [826] = {
+ [970] = {
.class_hid = BNXT_ULP_CLASS_HID_3d00,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16802,7 +20370,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [827] = {
+ [971] = {
.class_hid = BNXT_ULP_CLASS_HID_52bc,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16820,7 +20388,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [828] = {
+ [972] = {
.class_hid = BNXT_ULP_CLASS_HID_3ed0,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16839,7 +20407,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [829] = {
+ [973] = {
.class_hid = BNXT_ULP_CLASS_HID_72c0,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16858,7 +20426,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [830] = {
+ [974] = {
.class_hid = BNXT_ULP_CLASS_HID_5ed4,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16878,7 +20446,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [831] = {
+ [975] = {
.class_hid = BNXT_ULP_CLASS_HID_3866,
.class_tid = 3,
.hdr_sig_id = 0,
@@ -16893,7 +20461,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC }
},
- [832] = {
+ [976] = {
.class_hid = BNXT_ULP_CLASS_HID_381e,
.class_tid = 3,
.hdr_sig_id = 1,
@@ -16908,7 +20476,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC }
},
- [833] = {
+ [977] = {
.class_hid = BNXT_ULP_CLASS_HID_3860,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -16924,7 +20492,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC }
},
- [834] = {
+ [978] = {
.class_hid = BNXT_ULP_CLASS_HID_0454,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -16941,7 +20509,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID }
},
- [835] = {
+ [979] = {
.class_hid = BNXT_ULP_CLASS_HID_3818,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -16957,7 +20525,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC }
},
- [836] = {
+ [980] = {
.class_hid = BNXT_ULP_CLASS_HID_042c,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -16974,7 +20542,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID }
},
- [837] = {
+ [981] = {
.class_hid = BNXT_ULP_CLASS_HID_3846,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -16990,7 +20558,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC }
},
- [838] = {
+ [982] = {
.class_hid = BNXT_ULP_CLASS_HID_387e,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -17006,7 +20574,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC }
},
- [839] = {
+ [983] = {
.class_hid = BNXT_ULP_CLASS_HID_3ba6,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -17022,7 +20590,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC }
},
- [840] = {
+ [984] = {
.class_hid = BNXT_ULP_CLASS_HID_385e,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -17038,7 +20606,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC }
},
- [841] = {
+ [985] = {
.class_hid = BNXT_ULP_CLASS_HID_3840,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -17055,7 +20623,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC }
},
- [842] = {
+ [986] = {
.class_hid = BNXT_ULP_CLASS_HID_0474,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -17073,7 +20641,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID }
},
- [843] = {
+ [987] = {
.class_hid = BNXT_ULP_CLASS_HID_3878,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -17090,7 +20658,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC }
},
- [844] = {
+ [988] = {
.class_hid = BNXT_ULP_CLASS_HID_044c,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -17108,7 +20676,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID }
},
- [845] = {
+ [989] = {
.class_hid = BNXT_ULP_CLASS_HID_3ba0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -17125,7 +20693,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC }
},
- [846] = {
+ [990] = {
.class_hid = BNXT_ULP_CLASS_HID_0794,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -17143,7 +20711,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID }
},
- [847] = {
+ [991] = {
.class_hid = BNXT_ULP_CLASS_HID_3858,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -17160,7 +20728,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC }
},
- [848] = {
+ [992] = {
.class_hid = BNXT_ULP_CLASS_HID_046c,
.class_tid = 3,
.hdr_sig_id = 11,
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
index 84e3d92f41..c016e1940a 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Tue Jul 13 12:36:40 2021 */
+/* date: Fri Aug 20 17:59:14 2021 */
#ifndef ULP_TEMPLATE_DB_H_
#define ULP_TEMPLATE_DB_H_
@@ -11,14 +11,14 @@
#define BNXT_ULP_REGFILE_MAX_SZ 42
#define BNXT_ULP_MAX_NUM_DEVICES 4
#define BNXT_ULP_LOG2_MAX_NUM_DEV 2
-#define BNXT_ULP_GEN_TBL_MAX_SZ 12
-#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 32768
-#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 849
+#define BNXT_ULP_GEN_TBL_MAX_SZ 16
+#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 65536
+#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 993
#define BNXT_ULP_CLASS_HID_LOW_PRIME 6701
#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907
-#define BNXT_ULP_CLASS_HID_SHFTR 24
-#define BNXT_ULP_CLASS_HID_SHFTL 24
-#define BNXT_ULP_CLASS_HID_MASK 32767
+#define BNXT_ULP_CLASS_HID_SHFTR 28
+#define BNXT_ULP_CLASS_HID_SHFTL 28
+#define BNXT_ULP_CLASS_HID_MASK 65535
#define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048
#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 86
#define BNXT_ULP_ACT_HID_LOW_PRIME 7919
@@ -27,10 +27,10 @@
#define BNXT_ULP_ACT_HID_SHFTL 26
#define BNXT_ULP_ACT_HID_MASK 2047
#define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 8
-#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 62
+#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 110
#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 50
-#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 206
-#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 6
+#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 278
+#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 8
#define BNXT_ULP_COND_GOTO_REJECT 1023
#define BNXT_ULP_COND_GOTO_RF 0x10000
#define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7
@@ -44,10 +44,10 @@
#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 618
#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 49
#define ULP_THOR_CLASS_TMPL_LIST_SIZE 6
-#define ULP_THOR_CLASS_TBL_LIST_SIZE 114
-#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 2305
-#define ULP_THOR_CLASS_IDENT_LIST_SIZE 39
-#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1192
+#define ULP_THOR_CLASS_TBL_LIST_SIZE 116
+#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 2323
+#define ULP_THOR_CLASS_IDENT_LIST_SIZE 38
+#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1313
#define ULP_THOR_CLASS_COND_LIST_SIZE 55
#define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7
#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 35
@@ -56,11 +56,11 @@
#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 536
#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 39
#define ULP_THOR_ACT_TMPL_LIST_SIZE 7
-#define ULP_THOR_ACT_TBL_LIST_SIZE 28
-#define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 2
-#define ULP_THOR_ACT_IDENT_LIST_SIZE 1
-#define ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE 479
-#define ULP_THOR_ACT_COND_LIST_SIZE 20
+#define ULP_THOR_ACT_TBL_LIST_SIZE 36
+#define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 16
+#define ULP_THOR_ACT_IDENT_LIST_SIZE 3
+#define ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE 505
+#define ULP_THOR_ACT_COND_LIST_SIZE 27
enum bnxt_ulp_act_bit {
BNXT_ULP_ACT_BIT_MARK = 0x0000000000000001,
@@ -158,56 +158,60 @@ enum bnxt_ulp_cf_idx {
BNXT_ULP_CF_IDX_O_L4_DST_PORT = 18,
BNXT_ULP_CF_IDX_I_L4_SRC_PORT = 19,
BNXT_ULP_CF_IDX_I_L4_DST_PORT = 20,
- BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT = 21,
- BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT = 22,
- BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT = 23,
- BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT = 24,
- BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID = 25,
- BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID = 26,
- BNXT_ULP_CF_IDX_O_L3_PROTO_ID = 27,
- BNXT_ULP_CF_IDX_I_L3_PROTO_ID = 28,
- BNXT_ULP_CF_IDX_DEV_PORT_ID = 29,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 30,
- BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 31,
- BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 32,
- BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 33,
- BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 34,
- BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 35,
- BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 36,
- BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 37,
- BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 38,
- BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 39,
- BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 40,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 41,
- BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 42,
- BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG = 43,
- BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG = 44,
- BNXT_ULP_CF_IDX_ACT_DEC_TTL = 45,
- BNXT_ULP_CF_IDX_ACT_T_DEC_TTL = 46,
- BNXT_ULP_CF_IDX_ACT_PORT_IS_SET = 47,
- BNXT_ULP_CF_IDX_ACT_PORT_TYPE = 48,
- BNXT_ULP_CF_IDX_MATCH_PORT_TYPE = 49,
- BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP = 50,
- BNXT_ULP_CF_IDX_MATCH_PORT_IS_PF = 51,
- BNXT_ULP_CF_IDX_VF_TO_VF = 52,
- BNXT_ULP_CF_IDX_L3_HDR_CNT = 53,
- BNXT_ULP_CF_IDX_L4_HDR_CNT = 54,
- BNXT_ULP_CF_IDX_VFR_MODE = 55,
- BNXT_ULP_CF_IDX_L3_TUN = 56,
- BNXT_ULP_CF_IDX_L3_TUN_DECAP = 57,
- BNXT_ULP_CF_IDX_FID = 58,
- BNXT_ULP_CF_IDX_HDR_SIG_ID = 59,
- BNXT_ULP_CF_IDX_FLOW_SIG_ID = 60,
- BNXT_ULP_CF_IDX_WC_MATCH = 61,
- BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG = 62,
- BNXT_ULP_CF_IDX_TUNNEL_ID = 63,
- BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID = 64,
- BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID = 65,
- BNXT_ULP_CF_IDX_OO_VLAN_FB_VID = 66,
- BNXT_ULP_CF_IDX_OI_VLAN_FB_VID = 67,
- BNXT_ULP_CF_IDX_IO_VLAN_FB_VID = 68,
- BNXT_ULP_CF_IDX_II_VLAN_FB_VID = 69,
- BNXT_ULP_CF_IDX_LAST = 70
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK = 21,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK = 22,
+ BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK = 23,
+ BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK = 24,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT = 25,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT = 26,
+ BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT = 27,
+ BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT = 28,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID = 29,
+ BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID = 30,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID = 31,
+ BNXT_ULP_CF_IDX_I_L3_PROTO_ID = 32,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID = 33,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 34,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 35,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 36,
+ BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 37,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 38,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 39,
+ BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 40,
+ BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 41,
+ BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 42,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 43,
+ BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 44,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 45,
+ BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 46,
+ BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG = 47,
+ BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG = 48,
+ BNXT_ULP_CF_IDX_ACT_DEC_TTL = 49,
+ BNXT_ULP_CF_IDX_ACT_T_DEC_TTL = 50,
+ BNXT_ULP_CF_IDX_ACT_PORT_IS_SET = 51,
+ BNXT_ULP_CF_IDX_ACT_PORT_TYPE = 52,
+ BNXT_ULP_CF_IDX_MATCH_PORT_TYPE = 53,
+ BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP = 54,
+ BNXT_ULP_CF_IDX_MATCH_PORT_IS_PF = 55,
+ BNXT_ULP_CF_IDX_VF_TO_VF = 56,
+ BNXT_ULP_CF_IDX_L3_HDR_CNT = 57,
+ BNXT_ULP_CF_IDX_L4_HDR_CNT = 58,
+ BNXT_ULP_CF_IDX_VFR_MODE = 59,
+ BNXT_ULP_CF_IDX_L3_TUN = 60,
+ BNXT_ULP_CF_IDX_L3_TUN_DECAP = 61,
+ BNXT_ULP_CF_IDX_FID = 62,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID = 63,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID = 64,
+ BNXT_ULP_CF_IDX_WC_MATCH = 65,
+ BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG = 66,
+ BNXT_ULP_CF_IDX_TUNNEL_ID = 67,
+ BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID = 68,
+ BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID = 69,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID = 70,
+ BNXT_ULP_CF_IDX_OI_VLAN_FB_VID = 71,
+ BNXT_ULP_CF_IDX_IO_VLAN_FB_VID = 72,
+ BNXT_ULP_CF_IDX_II_VLAN_FB_VID = 73,
+ BNXT_ULP_CF_IDX_LAST = 74
};
enum bnxt_ulp_cond_list_opc {
@@ -394,38 +398,49 @@ enum bnxt_ulp_glb_rf_idx {
BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 = 9,
BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 = 10,
BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 = 11,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0 = 12,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1 = 13,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_6 = 12,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_7 = 13,
BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 = 14,
BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 = 15,
BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 = 16,
BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3 = 17,
BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4 = 18,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0 = 19,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1 = 20,
- BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0 = 21,
- BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_1 = 22,
- BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 = 23,
- BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 = 24,
- BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 = 25,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 26,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 = 27,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2 = 28,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 29,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 30,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 31,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 32,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 33,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 34,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 35,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 36,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 37,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 38,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 39,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 40,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 41,
- BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID = 42,
- BNXT_ULP_GLB_RF_IDX_LAST = 43
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0 = 19,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1 = 20,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2 = 21,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3 = 22,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_4 = 23,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_5 = 24,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_6 = 25,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_7 = 26,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0 = 27,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1 = 28,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2 = 29,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3 = 30,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_4 = 31,
+ BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0 = 32,
+ BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_1 = 33,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 = 34,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 = 35,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 = 36,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 37,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 = 38,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2 = 39,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 40,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 41,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 42,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 43,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 44,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 45,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 46,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 47,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 48,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 49,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 50,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 51,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 52,
+ BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID = 53,
+ BNXT_ULP_GLB_RF_IDX_LAST = 54
};
enum bnxt_ulp_hdr_type {
@@ -608,7 +623,9 @@ enum bnxt_ulp_resource_sub_type {
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR = 2,
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE = 3,
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE = 4,
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE = 5
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE = 5,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE = 6,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE = 7
};
enum bnxt_ulp_act_prop_sz {
@@ -1526,166 +1543,310 @@ enum bnxt_ulp_class_hid {
BNXT_ULP_CLASS_HID_315d = 0x315d,
BNXT_ULP_CLASS_HID_3612 = 0x3612,
BNXT_ULP_CLASS_HID_66da = 0x66da,
- BNXT_ULP_CLASS_HID_6165 = 0x6165,
- BNXT_ULP_CLASS_HID_2aa1 = 0x2aa1,
- BNXT_ULP_CLASS_HID_09cd = 0x09cd,
- BNXT_ULP_CLASS_HID_3845 = 0x3845,
- BNXT_ULP_CLASS_HID_11e9 = 0x11e9,
- BNXT_ULP_CLASS_HID_4361 = 0x4361,
- BNXT_ULP_CLASS_HID_218d = 0x218d,
- BNXT_ULP_CLASS_HID_5105 = 0x5105,
- BNXT_ULP_CLASS_HID_0c89 = 0x0c89,
- BNXT_ULP_CLASS_HID_3e81 = 0x3e81,
- BNXT_ULP_CLASS_HID_1dad = 0x1dad,
- BNXT_ULP_CLASS_HID_4ca5 = 0x4ca5,
- BNXT_ULP_CLASS_HID_25c9 = 0x25c9,
- BNXT_ULP_CLASS_HID_57c1 = 0x57c1,
- BNXT_ULP_CLASS_HID_33ed = 0x33ed,
- BNXT_ULP_CLASS_HID_65e5 = 0x65e5,
- BNXT_ULP_CLASS_HID_6dd9 = 0x6dd9,
- BNXT_ULP_CLASS_HID_261d = 0x261d,
- BNXT_ULP_CLASS_HID_0571 = 0x0571,
- BNXT_ULP_CLASS_HID_34f9 = 0x34f9,
- BNXT_ULP_CLASS_HID_1d55 = 0x1d55,
- BNXT_ULP_CLASS_HID_4fdd = 0x4fdd,
- BNXT_ULP_CLASS_HID_2d31 = 0x2d31,
- BNXT_ULP_CLASS_HID_5db9 = 0x5db9,
- BNXT_ULP_CLASS_HID_0035 = 0x0035,
- BNXT_ULP_CLASS_HID_323d = 0x323d,
- BNXT_ULP_CLASS_HID_1111 = 0x1111,
- BNXT_ULP_CLASS_HID_4019 = 0x4019,
- BNXT_ULP_CLASS_HID_2975 = 0x2975,
- BNXT_ULP_CLASS_HID_5b7d = 0x5b7d,
- BNXT_ULP_CLASS_HID_3f51 = 0x3f51,
- BNXT_ULP_CLASS_HID_6959 = 0x6959,
- BNXT_ULP_CLASS_HID_0e85 = 0x0e85,
- BNXT_ULP_CLASS_HID_380d = 0x380d,
- BNXT_ULP_CLASS_HID_1f21 = 0x1f21,
- BNXT_ULP_CLASS_HID_4ea9 = 0x4ea9,
- BNXT_ULP_CLASS_HID_1705 = 0x1705,
- BNXT_ULP_CLASS_HID_418d = 0x418d,
- BNXT_ULP_CLASS_HID_2721 = 0x2721,
- BNXT_ULP_CLASS_HID_57a9 = 0x57a9,
- BNXT_ULP_CLASS_HID_1a25 = 0x1a25,
- BNXT_ULP_CLASS_HID_342d = 0x342d,
- BNXT_ULP_CLASS_HID_2b01 = 0x2b01,
- BNXT_ULP_CLASS_HID_5a09 = 0x5a09,
- BNXT_ULP_CLASS_HID_2325 = 0x2325,
- BNXT_ULP_CLASS_HID_5d2d = 0x5d2d,
- BNXT_ULP_CLASS_HID_3101 = 0x3101,
- BNXT_ULP_CLASS_HID_6309 = 0x6309,
- BNXT_ULP_CLASS_HID_0bad = 0x0bad,
- BNXT_ULP_CLASS_HID_2535 = 0x2535,
- BNXT_ULP_CLASS_HID_1869 = 0x1869,
- BNXT_ULP_CLASS_HID_4bf1 = 0x4bf1,
- BNXT_ULP_CLASS_HID_136d = 0x136d,
- BNXT_ULP_CLASS_HID_43f5 = 0x43f5,
- BNXT_ULP_CLASS_HID_2129 = 0x2129,
- BNXT_ULP_CLASS_HID_53b1 = 0x53b1,
- BNXT_ULP_CLASS_HID_072d = 0x072d,
- BNXT_ULP_CLASS_HID_3135 = 0x3135,
- BNXT_ULP_CLASS_HID_1429 = 0x1429,
- BNXT_ULP_CLASS_HID_4731 = 0x4731,
- BNXT_ULP_CLASS_HID_2f6d = 0x2f6d,
- BNXT_ULP_CLASS_HID_5f75 = 0x5f75,
- BNXT_ULP_CLASS_HID_3d69 = 0x3d69,
- BNXT_ULP_CLASS_HID_6f71 = 0x6f71,
- BNXT_ULP_CLASS_HID_0dbd = 0x0dbd,
- BNXT_ULP_CLASS_HID_3f25 = 0x3f25,
- BNXT_ULP_CLASS_HID_1239 = 0x1239,
- BNXT_ULP_CLASS_HID_4da1 = 0x4da1,
- BNXT_ULP_CLASS_HID_153d = 0x153d,
- BNXT_ULP_CLASS_HID_45a5 = 0x45a5,
- BNXT_ULP_CLASS_HID_3bb9 = 0x3bb9,
- BNXT_ULP_CLASS_HID_55a1 = 0x55a1,
- BNXT_ULP_CLASS_HID_193d = 0x193d,
- BNXT_ULP_CLASS_HID_4b25 = 0x4b25,
- BNXT_ULP_CLASS_HID_2e39 = 0x2e39,
- BNXT_ULP_CLASS_HID_5921 = 0x5921,
- BNXT_ULP_CLASS_HID_213d = 0x213d,
- BNXT_ULP_CLASS_HID_5125 = 0x5125,
- BNXT_ULP_CLASS_HID_3739 = 0x3739,
- BNXT_ULP_CLASS_HID_093d = 0x093d,
- BNXT_ULP_CLASS_HID_684d = 0x684d,
- BNXT_ULP_CLASS_HID_2389 = 0x2389,
- BNXT_ULP_CLASS_HID_00e5 = 0x00e5,
- BNXT_ULP_CLASS_HID_316d = 0x316d,
- BNXT_ULP_CLASS_HID_18c1 = 0x18c1,
- BNXT_ULP_CLASS_HID_4a49 = 0x4a49,
- BNXT_ULP_CLASS_HID_28a5 = 0x28a5,
- BNXT_ULP_CLASS_HID_582d = 0x582d,
- BNXT_ULP_CLASS_HID_05a1 = 0x05a1,
- BNXT_ULP_CLASS_HID_37a9 = 0x37a9,
- BNXT_ULP_CLASS_HID_1485 = 0x1485,
- BNXT_ULP_CLASS_HID_458d = 0x458d,
- BNXT_ULP_CLASS_HID_2ce1 = 0x2ce1,
- BNXT_ULP_CLASS_HID_5ee9 = 0x5ee9,
- BNXT_ULP_CLASS_HID_3ac5 = 0x3ac5,
- BNXT_ULP_CLASS_HID_6ccd = 0x6ccd,
- BNXT_ULP_CLASS_HID_0b11 = 0x0b11,
- BNXT_ULP_CLASS_HID_3d99 = 0x3d99,
- BNXT_ULP_CLASS_HID_1ab5 = 0x1ab5,
- BNXT_ULP_CLASS_HID_4b3d = 0x4b3d,
- BNXT_ULP_CLASS_HID_1291 = 0x1291,
- BNXT_ULP_CLASS_HID_4419 = 0x4419,
- BNXT_ULP_CLASS_HID_22b5 = 0x22b5,
- BNXT_ULP_CLASS_HID_523d = 0x523d,
- BNXT_ULP_CLASS_HID_1fb1 = 0x1fb1,
- BNXT_ULP_CLASS_HID_31b9 = 0x31b9,
- BNXT_ULP_CLASS_HID_2e95 = 0x2e95,
- BNXT_ULP_CLASS_HID_5f9d = 0x5f9d,
- BNXT_ULP_CLASS_HID_26b1 = 0x26b1,
- BNXT_ULP_CLASS_HID_58b9 = 0x58b9,
- BNXT_ULP_CLASS_HID_3495 = 0x3495,
- BNXT_ULP_CLASS_HID_669d = 0x669d,
- BNXT_ULP_CLASS_HID_0e39 = 0x0e39,
- BNXT_ULP_CLASS_HID_20a1 = 0x20a1,
- BNXT_ULP_CLASS_HID_1dfd = 0x1dfd,
- BNXT_ULP_CLASS_HID_4e65 = 0x4e65,
- BNXT_ULP_CLASS_HID_16f9 = 0x16f9,
- BNXT_ULP_CLASS_HID_4661 = 0x4661,
- BNXT_ULP_CLASS_HID_24bd = 0x24bd,
- BNXT_ULP_CLASS_HID_5625 = 0x5625,
- BNXT_ULP_CLASS_HID_02b9 = 0x02b9,
- BNXT_ULP_CLASS_HID_34a1 = 0x34a1,
- BNXT_ULP_CLASS_HID_11bd = 0x11bd,
- BNXT_ULP_CLASS_HID_42a5 = 0x42a5,
- BNXT_ULP_CLASS_HID_2af9 = 0x2af9,
- BNXT_ULP_CLASS_HID_5ae1 = 0x5ae1,
- BNXT_ULP_CLASS_HID_38fd = 0x38fd,
- BNXT_ULP_CLASS_HID_6ae5 = 0x6ae5,
- BNXT_ULP_CLASS_HID_0829 = 0x0829,
- BNXT_ULP_CLASS_HID_3ab1 = 0x3ab1,
- BNXT_ULP_CLASS_HID_17ad = 0x17ad,
- BNXT_ULP_CLASS_HID_4835 = 0x4835,
- BNXT_ULP_CLASS_HID_10a9 = 0x10a9,
- BNXT_ULP_CLASS_HID_4031 = 0x4031,
- BNXT_ULP_CLASS_HID_3e2d = 0x3e2d,
- BNXT_ULP_CLASS_HID_5035 = 0x5035,
- BNXT_ULP_CLASS_HID_1ca9 = 0x1ca9,
- BNXT_ULP_CLASS_HID_4eb1 = 0x4eb1,
- BNXT_ULP_CLASS_HID_2bad = 0x2bad,
- BNXT_ULP_CLASS_HID_5cb5 = 0x5cb5,
- BNXT_ULP_CLASS_HID_24a9 = 0x24a9,
- BNXT_ULP_CLASS_HID_54b1 = 0x54b1,
- BNXT_ULP_CLASS_HID_32ad = 0x32ad,
- BNXT_ULP_CLASS_HID_0ca9 = 0x0ca9,
- BNXT_ULP_CLASS_HID_7f35 = 0x7f35,
- BNXT_ULP_CLASS_HID_34f1 = 0x34f1,
- BNXT_ULP_CLASS_HID_179d = 0x179d,
- BNXT_ULP_CLASS_HID_2615 = 0x2615,
- BNXT_ULP_CLASS_HID_0fb9 = 0x0fb9,
- BNXT_ULP_CLASS_HID_5d31 = 0x5d31,
- BNXT_ULP_CLASS_HID_3fdd = 0x3fdd,
- BNXT_ULP_CLASS_HID_4f55 = 0x4f55,
- BNXT_ULP_CLASS_HID_12d9 = 0x12d9,
- BNXT_ULP_CLASS_HID_20d1 = 0x20d1,
- BNXT_ULP_CLASS_HID_03fd = 0x03fd,
- BNXT_ULP_CLASS_HID_52f5 = 0x52f5,
- BNXT_ULP_CLASS_HID_3b99 = 0x3b99,
- BNXT_ULP_CLASS_HID_4991 = 0x4991,
- BNXT_ULP_CLASS_HID_2dbd = 0x2dbd,
- BNXT_ULP_CLASS_HID_7bb5 = 0x7bb5,
+ BNXT_ULP_CLASS_HID_e082 = 0xe082,
+ BNXT_ULP_CLASS_HID_ab46 = 0xab46,
+ BNXT_ULP_CLASS_HID_c82a = 0xc82a,
+ BNXT_ULP_CLASS_HID_f9a2 = 0xf9a2,
+ BNXT_ULP_CLASS_HID_d8ce = 0xd8ce,
+ BNXT_ULP_CLASS_HID_a2d2 = 0xa2d2,
+ BNXT_ULP_CLASS_HID_c076 = 0xc076,
+ BNXT_ULP_CLASS_HID_f1ee = 0xf1ee,
+ BNXT_ULP_CLASS_HID_a96e = 0xa96e,
+ BNXT_ULP_CLASS_HID_dae6 = 0xdae6,
+ BNXT_ULP_CLASS_HID_c7aa = 0xc7aa,
+ BNXT_ULP_CLASS_HID_c26e = 0xc26e,
+ BNXT_ULP_CLASS_HID_a0fa = 0xa0fa,
+ BNXT_ULP_CLASS_HID_d272 = 0xd272,
+ BNXT_ULP_CLASS_HID_fff6 = 0xfff6,
+ BNXT_ULP_CLASS_HID_e16e = 0xe16e,
+ BNXT_ULP_CLASS_HID_e165 = 0xe165,
+ BNXT_ULP_CLASS_HID_aaa1 = 0xaaa1,
+ BNXT_ULP_CLASS_HID_c9cd = 0xc9cd,
+ BNXT_ULP_CLASS_HID_f845 = 0xf845,
+ BNXT_ULP_CLASS_HID_90f9 = 0x90f9,
+ BNXT_ULP_CLASS_HID_c371 = 0xc371,
+ BNXT_ULP_CLASS_HID_e19d = 0xe19d,
+ BNXT_ULP_CLASS_HID_d015 = 0xd015,
+ BNXT_ULP_CLASS_HID_8c09 = 0x8c09,
+ BNXT_ULP_CLASS_HID_be89 = 0xbe89,
+ BNXT_ULP_CLASS_HID_ddad = 0xddad,
+ BNXT_ULP_CLASS_HID_cc2d = 0xcc2d,
+ BNXT_ULP_CLASS_HID_a4d9 = 0xa4d9,
+ BNXT_ULP_CLASS_HID_d759 = 0xd759,
+ BNXT_ULP_CLASS_HID_f27d = 0xf27d,
+ BNXT_ULP_CLASS_HID_e4fd = 0xe4fd,
+ BNXT_ULP_CLASS_HID_ecf6 = 0xecf6,
+ BNXT_ULP_CLASS_HID_a732 = 0xa732,
+ BNXT_ULP_CLASS_HID_c45e = 0xc45e,
+ BNXT_ULP_CLASS_HID_f5d6 = 0xf5d6,
+ BNXT_ULP_CLASS_HID_d4ba = 0xd4ba,
+ BNXT_ULP_CLASS_HID_aea6 = 0xaea6,
+ BNXT_ULP_CLASS_HID_cc02 = 0xcc02,
+ BNXT_ULP_CLASS_HID_fd9a = 0xfd9a,
+ BNXT_ULP_CLASS_HID_a51a = 0xa51a,
+ BNXT_ULP_CLASS_HID_d692 = 0xd692,
+ BNXT_ULP_CLASS_HID_cbde = 0xcbde,
+ BNXT_ULP_CLASS_HID_ce1a = 0xce1a,
+ BNXT_ULP_CLASS_HID_ac8e = 0xac8e,
+ BNXT_ULP_CLASS_HID_de06 = 0xde06,
+ BNXT_ULP_CLASS_HID_f382 = 0xf382,
+ BNXT_ULP_CLASS_HID_ed1a = 0xed1a,
+ BNXT_ULP_CLASS_HID_9d6a = 0x9d6a,
+ BNXT_ULP_CLASS_HID_cee2 = 0xcee2,
+ BNXT_ULP_CLASS_HID_ec0e = 0xec0e,
+ BNXT_ULP_CLASS_HID_dd86 = 0xdd86,
+ BNXT_ULP_CLASS_HID_852e = 0x852e,
+ BNXT_ULP_CLASS_HID_b6a6 = 0xb6a6,
+ BNXT_ULP_CLASS_HID_eb82 = 0xeb82,
+ BNXT_ULP_CLASS_HID_c50a = 0xc50a,
+ BNXT_ULP_CLASS_HID_ccca = 0xccca,
+ BNXT_ULP_CLASS_HID_8706 = 0x8706,
+ BNXT_ULP_CLASS_HID_d38e = 0xd38e,
+ BNXT_ULP_CLASS_HID_d5ca = 0xd5ca,
+ BNXT_ULP_CLASS_HID_b48e = 0xb48e,
+ BNXT_ULP_CLASS_HID_8e8a = 0x8e8a,
+ BNXT_ULP_CLASS_HID_db02 = 0xdb02,
+ BNXT_ULP_CLASS_HID_dd8e = 0xdd8e,
+ BNXT_ULP_CLASS_HID_819a = 0x819a,
+ BNXT_ULP_CLASS_HID_b31a = 0xb31a,
+ BNXT_ULP_CLASS_HID_d03e = 0xd03e,
+ BNXT_ULP_CLASS_HID_c1be = 0xc1be,
+ BNXT_ULP_CLASS_HID_890e = 0x890e,
+ BNXT_ULP_CLASS_HID_ba8e = 0xba8e,
+ BNXT_ULP_CLASS_HID_dfaa = 0xdfaa,
+ BNXT_ULP_CLASS_HID_c93a = 0xc93a,
+ BNXT_ULP_CLASS_HID_b11a = 0xb11a,
+ BNXT_ULP_CLASS_HID_8b4e = 0x8b4e,
+ BNXT_ULP_CLASS_HID_c79e = 0xc79e,
+ BNXT_ULP_CLASS_HID_d9da = 0xd9da,
+ BNXT_ULP_CLASS_HID_b88e = 0xb88e,
+ BNXT_ULP_CLASS_HID_ea0e = 0xea0e,
+ BNXT_ULP_CLASS_HID_cf0a = 0xcf0a,
+ BNXT_ULP_CLASS_HID_c18e = 0xc18e,
+ BNXT_ULP_CLASS_HID_a94a = 0xa94a,
+ BNXT_ULP_CLASS_HID_daca = 0xdaca,
+ BNXT_ULP_CLASS_HID_ffee = 0xffee,
+ BNXT_ULP_CLASS_HID_e96e = 0xe96e,
+ BNXT_ULP_CLASS_HID_910e = 0x910e,
+ BNXT_ULP_CLASS_HID_c28e = 0xc28e,
+ BNXT_ULP_CLASS_HID_e7aa = 0xe7aa,
+ BNXT_ULP_CLASS_HID_d12a = 0xd12a,
+ BNXT_ULP_CLASS_HID_d8ca = 0xd8ca,
+ BNXT_ULP_CLASS_HID_930e = 0x930e,
+ BNXT_ULP_CLASS_HID_ef4e = 0xef4e,
+ BNXT_ULP_CLASS_HID_e18a = 0xe18a,
+ BNXT_ULP_CLASS_HID_c08e = 0xc08e,
+ BNXT_ULP_CLASS_HID_9a8a = 0x9a8a,
+ BNXT_ULP_CLASS_HID_d70a = 0xd70a,
+ BNXT_ULP_CLASS_HID_e90e = 0xe90e,
+ BNXT_ULP_CLASS_HID_edd9 = 0xedd9,
+ BNXT_ULP_CLASS_HID_a61d = 0xa61d,
+ BNXT_ULP_CLASS_HID_c571 = 0xc571,
+ BNXT_ULP_CLASS_HID_f4f9 = 0xf4f9,
+ BNXT_ULP_CLASS_HID_9c45 = 0x9c45,
+ BNXT_ULP_CLASS_HID_cfcd = 0xcfcd,
+ BNXT_ULP_CLASS_HID_ed21 = 0xed21,
+ BNXT_ULP_CLASS_HID_dca9 = 0xdca9,
+ BNXT_ULP_CLASS_HID_80b5 = 0x80b5,
+ BNXT_ULP_CLASS_HID_b235 = 0xb235,
+ BNXT_ULP_CLASS_HID_d111 = 0xd111,
+ BNXT_ULP_CLASS_HID_c091 = 0xc091,
+ BNXT_ULP_CLASS_HID_a865 = 0xa865,
+ BNXT_ULP_CLASS_HID_dbe5 = 0xdbe5,
+ BNXT_ULP_CLASS_HID_fec1 = 0xfec1,
+ BNXT_ULP_CLASS_HID_e841 = 0xe841,
+ BNXT_ULP_CLASS_HID_8e85 = 0x8e85,
+ BNXT_ULP_CLASS_HID_b80d = 0xb80d,
+ BNXT_ULP_CLASS_HID_df65 = 0xdf65,
+ BNXT_ULP_CLASS_HID_ceed = 0xceed,
+ BNXT_ULP_CLASS_HID_9645 = 0x9645,
+ BNXT_ULP_CLASS_HID_c1cd = 0xc1cd,
+ BNXT_ULP_CLASS_HID_e725 = 0xe725,
+ BNXT_ULP_CLASS_HID_d6ad = 0xd6ad,
+ BNXT_ULP_CLASS_HID_9aa5 = 0x9aa5,
+ BNXT_ULP_CLASS_HID_b425 = 0xb425,
+ BNXT_ULP_CLASS_HID_eb05 = 0xeb05,
+ BNXT_ULP_CLASS_HID_da85 = 0xda85,
+ BNXT_ULP_CLASS_HID_a265 = 0xa265,
+ BNXT_ULP_CLASS_HID_dde5 = 0xdde5,
+ BNXT_ULP_CLASS_HID_f0c5 = 0xf0c5,
+ BNXT_ULP_CLASS_HID_e245 = 0xe245,
+ BNXT_ULP_CLASS_HID_8b8f = 0x8b8f,
+ BNXT_ULP_CLASS_HID_a517 = 0xa517,
+ BNXT_ULP_CLASS_HID_d86b = 0xd86b,
+ BNXT_ULP_CLASS_HID_cbf3 = 0xcbf3,
+ BNXT_ULP_CLASS_HID_934f = 0x934f,
+ BNXT_ULP_CLASS_HID_c2c7 = 0xc2c7,
+ BNXT_ULP_CLASS_HID_e02b = 0xe02b,
+ BNXT_ULP_CLASS_HID_d3a3 = 0xd3a3,
+ BNXT_ULP_CLASS_HID_87a7 = 0x87a7,
+ BNXT_ULP_CLASS_HID_b137 = 0xb137,
+ BNXT_ULP_CLASS_HID_d403 = 0xd403,
+ BNXT_ULP_CLASS_HID_c793 = 0xc793,
+ BNXT_ULP_CLASS_HID_af67 = 0xaf67,
+ BNXT_ULP_CLASS_HID_dee7 = 0xdee7,
+ BNXT_ULP_CLASS_HID_fdc3 = 0xfdc3,
+ BNXT_ULP_CLASS_HID_ef43 = 0xef43,
+ BNXT_ULP_CLASS_HID_8dbf = 0x8dbf,
+ BNXT_ULP_CLASS_HID_bf07 = 0xbf07,
+ BNXT_ULP_CLASS_HID_d21f = 0xd21f,
+ BNXT_ULP_CLASS_HID_cde7 = 0xcde7,
+ BNXT_ULP_CLASS_HID_956f = 0x956f,
+ BNXT_ULP_CLASS_HID_c4c7 = 0xc4c7,
+ BNXT_ULP_CLASS_HID_fbcf = 0xfbcf,
+ BNXT_ULP_CLASS_HID_d5a7 = 0xd5a7,
+ BNXT_ULP_CLASS_HID_9957 = 0x9957,
+ BNXT_ULP_CLASS_HID_cb27 = 0xcb27,
+ BNXT_ULP_CLASS_HID_ee37 = 0xee37,
+ BNXT_ULP_CLASS_HID_d987 = 0xd987,
+ BNXT_ULP_CLASS_HID_a107 = 0xa107,
+ BNXT_ULP_CLASS_HID_d0e7 = 0xd0e7,
+ BNXT_ULP_CLASS_HID_f7e7 = 0xf7e7,
+ BNXT_ULP_CLASS_HID_c827 = 0xc827,
+ BNXT_ULP_CLASS_HID_f76a = 0xf76a,
+ BNXT_ULP_CLASS_HID_bcae = 0xbcae,
+ BNXT_ULP_CLASS_HID_dfc2 = 0xdfc2,
+ BNXT_ULP_CLASS_HID_ee4a = 0xee4a,
+ BNXT_ULP_CLASS_HID_cf26 = 0xcf26,
+ BNXT_ULP_CLASS_HID_b53a = 0xb53a,
+ BNXT_ULP_CLASS_HID_d79e = 0xd79e,
+ BNXT_ULP_CLASS_HID_e606 = 0xe606,
+ BNXT_ULP_CLASS_HID_be86 = 0xbe86,
+ BNXT_ULP_CLASS_HID_cd0e = 0xcd0e,
+ BNXT_ULP_CLASS_HID_d042 = 0xd042,
+ BNXT_ULP_CLASS_HID_d586 = 0xd586,
+ BNXT_ULP_CLASS_HID_b712 = 0xb712,
+ BNXT_ULP_CLASS_HID_c59a = 0xc59a,
+ BNXT_ULP_CLASS_HID_e81e = 0xe81e,
+ BNXT_ULP_CLASS_HID_f686 = 0xf686,
+ BNXT_ULP_CLASS_HID_86f6 = 0x86f6,
+ BNXT_ULP_CLASS_HID_d57e = 0xd57e,
+ BNXT_ULP_CLASS_HID_f792 = 0xf792,
+ BNXT_ULP_CLASS_HID_c61a = 0xc61a,
+ BNXT_ULP_CLASS_HID_9eb2 = 0x9eb2,
+ BNXT_ULP_CLASS_HID_ad3a = 0xad3a,
+ BNXT_ULP_CLASS_HID_f01e = 0xf01e,
+ BNXT_ULP_CLASS_HID_de96 = 0xde96,
+ BNXT_ULP_CLASS_HID_d756 = 0xd756,
+ BNXT_ULP_CLASS_HID_9c9a = 0x9c9a,
+ BNXT_ULP_CLASS_HID_c812 = 0xc812,
+ BNXT_ULP_CLASS_HID_ce56 = 0xce56,
+ BNXT_ULP_CLASS_HID_af12 = 0xaf12,
+ BNXT_ULP_CLASS_HID_9516 = 0x9516,
+ BNXT_ULP_CLASS_HID_c09e = 0xc09e,
+ BNXT_ULP_CLASS_HID_c612 = 0xc612,
+ BNXT_ULP_CLASS_HID_9a06 = 0x9a06,
+ BNXT_ULP_CLASS_HID_a886 = 0xa886,
+ BNXT_ULP_CLASS_HID_cba2 = 0xcba2,
+ BNXT_ULP_CLASS_HID_da22 = 0xda22,
+ BNXT_ULP_CLASS_HID_9292 = 0x9292,
+ BNXT_ULP_CLASS_HID_a112 = 0xa112,
+ BNXT_ULP_CLASS_HID_c436 = 0xc436,
+ BNXT_ULP_CLASS_HID_d2a6 = 0xd2a6,
+ BNXT_ULP_CLASS_HID_aa86 = 0xaa86,
+ BNXT_ULP_CLASS_HID_90d2 = 0x90d2,
+ BNXT_ULP_CLASS_HID_dc02 = 0xdc02,
+ BNXT_ULP_CLASS_HID_c246 = 0xc246,
+ BNXT_ULP_CLASS_HID_a312 = 0xa312,
+ BNXT_ULP_CLASS_HID_f192 = 0xf192,
+ BNXT_ULP_CLASS_HID_d496 = 0xd496,
+ BNXT_ULP_CLASS_HID_da12 = 0xda12,
+ BNXT_ULP_CLASS_HID_b2d6 = 0xb2d6,
+ BNXT_ULP_CLASS_HID_c156 = 0xc156,
+ BNXT_ULP_CLASS_HID_e472 = 0xe472,
+ BNXT_ULP_CLASS_HID_f2f2 = 0xf2f2,
+ BNXT_ULP_CLASS_HID_8a92 = 0x8a92,
+ BNXT_ULP_CLASS_HID_d912 = 0xd912,
+ BNXT_ULP_CLASS_HID_fc36 = 0xfc36,
+ BNXT_ULP_CLASS_HID_cab6 = 0xcab6,
+ BNXT_ULP_CLASS_HID_c356 = 0xc356,
+ BNXT_ULP_CLASS_HID_8892 = 0x8892,
+ BNXT_ULP_CLASS_HID_f4d2 = 0xf4d2,
+ BNXT_ULP_CLASS_HID_fa16 = 0xfa16,
+ BNXT_ULP_CLASS_HID_db12 = 0xdb12,
+ BNXT_ULP_CLASS_HID_8116 = 0x8116,
+ BNXT_ULP_CLASS_HID_cc96 = 0xcc96,
+ BNXT_ULP_CLASS_HID_f292 = 0xf292,
+ BNXT_ULP_CLASS_HID_e84d = 0xe84d,
+ BNXT_ULP_CLASS_HID_a389 = 0xa389,
+ BNXT_ULP_CLASS_HID_c0e5 = 0xc0e5,
+ BNXT_ULP_CLASS_HID_f16d = 0xf16d,
+ BNXT_ULP_CLASS_HID_99d1 = 0x99d1,
+ BNXT_ULP_CLASS_HID_ca59 = 0xca59,
+ BNXT_ULP_CLASS_HID_e8b5 = 0xe8b5,
+ BNXT_ULP_CLASS_HID_d93d = 0xd93d,
+ BNXT_ULP_CLASS_HID_8521 = 0x8521,
+ BNXT_ULP_CLASS_HID_b7a1 = 0xb7a1,
+ BNXT_ULP_CLASS_HID_d485 = 0xd485,
+ BNXT_ULP_CLASS_HID_c505 = 0xc505,
+ BNXT_ULP_CLASS_HID_adf1 = 0xadf1,
+ BNXT_ULP_CLASS_HID_de71 = 0xde71,
+ BNXT_ULP_CLASS_HID_fb55 = 0xfb55,
+ BNXT_ULP_CLASS_HID_edd5 = 0xedd5,
+ BNXT_ULP_CLASS_HID_8b11 = 0x8b11,
+ BNXT_ULP_CLASS_HID_bd99 = 0xbd99,
+ BNXT_ULP_CLASS_HID_daf1 = 0xdaf1,
+ BNXT_ULP_CLASS_HID_cb79 = 0xcb79,
+ BNXT_ULP_CLASS_HID_93d1 = 0x93d1,
+ BNXT_ULP_CLASS_HID_c459 = 0xc459,
+ BNXT_ULP_CLASS_HID_e2b1 = 0xe2b1,
+ BNXT_ULP_CLASS_HID_d339 = 0xd339,
+ BNXT_ULP_CLASS_HID_9f31 = 0x9f31,
+ BNXT_ULP_CLASS_HID_b1b1 = 0xb1b1,
+ BNXT_ULP_CLASS_HID_ee91 = 0xee91,
+ BNXT_ULP_CLASS_HID_df11 = 0xdf11,
+ BNXT_ULP_CLASS_HID_a7f1 = 0xa7f1,
+ BNXT_ULP_CLASS_HID_d871 = 0xd871,
+ BNXT_ULP_CLASS_HID_f551 = 0xf551,
+ BNXT_ULP_CLASS_HID_e7d1 = 0xe7d1,
+ BNXT_ULP_CLASS_HID_8e1b = 0x8e1b,
+ BNXT_ULP_CLASS_HID_a083 = 0xa083,
+ BNXT_ULP_CLASS_HID_ddff = 0xddff,
+ BNXT_ULP_CLASS_HID_ce67 = 0xce67,
+ BNXT_ULP_CLASS_HID_96db = 0x96db,
+ BNXT_ULP_CLASS_HID_c753 = 0xc753,
+ BNXT_ULP_CLASS_HID_e5bf = 0xe5bf,
+ BNXT_ULP_CLASS_HID_d637 = 0xd637,
+ BNXT_ULP_CLASS_HID_8233 = 0x8233,
+ BNXT_ULP_CLASS_HID_b4a3 = 0xb4a3,
+ BNXT_ULP_CLASS_HID_d197 = 0xd197,
+ BNXT_ULP_CLASS_HID_c207 = 0xc207,
+ BNXT_ULP_CLASS_HID_aaf3 = 0xaaf3,
+ BNXT_ULP_CLASS_HID_db73 = 0xdb73,
+ BNXT_ULP_CLASS_HID_f857 = 0xf857,
+ BNXT_ULP_CLASS_HID_ead7 = 0xead7,
+ BNXT_ULP_CLASS_HID_882b = 0x882b,
+ BNXT_ULP_CLASS_HID_ba93 = 0xba93,
+ BNXT_ULP_CLASS_HID_d78b = 0xd78b,
+ BNXT_ULP_CLASS_HID_c873 = 0xc873,
+ BNXT_ULP_CLASS_HID_90fb = 0x90fb,
+ BNXT_ULP_CLASS_HID_c153 = 0xc153,
+ BNXT_ULP_CLASS_HID_fe5b = 0xfe5b,
+ BNXT_ULP_CLASS_HID_d033 = 0xd033,
+ BNXT_ULP_CLASS_HID_9cc3 = 0x9cc3,
+ BNXT_ULP_CLASS_HID_ceb3 = 0xceb3,
+ BNXT_ULP_CLASS_HID_eba3 = 0xeba3,
+ BNXT_ULP_CLASS_HID_dc13 = 0xdc13,
+ BNXT_ULP_CLASS_HID_a493 = 0xa493,
+ BNXT_ULP_CLASS_HID_d573 = 0xd573,
+ BNXT_ULP_CLASS_HID_f273 = 0xf273,
+ BNXT_ULP_CLASS_HID_cdb3 = 0xcdb3,
+ BNXT_ULP_CLASS_HID_ff35 = 0xff35,
+ BNXT_ULP_CLASS_HID_b4f1 = 0xb4f1,
+ BNXT_ULP_CLASS_HID_d79d = 0xd79d,
+ BNXT_ULP_CLASS_HID_e615 = 0xe615,
+ BNXT_ULP_CLASS_HID_8ea9 = 0x8ea9,
+ BNXT_ULP_CLASS_HID_dd21 = 0xdd21,
+ BNXT_ULP_CLASS_HID_ffcd = 0xffcd,
+ BNXT_ULP_CLASS_HID_ce45 = 0xce45,
+ BNXT_ULP_CLASS_HID_9259 = 0x9259,
+ BNXT_ULP_CLASS_HID_a0d9 = 0xa0d9,
+ BNXT_ULP_CLASS_HID_c3fd = 0xc3fd,
+ BNXT_ULP_CLASS_HID_d27d = 0xd27d,
+ BNXT_ULP_CLASS_HID_ba89 = 0xba89,
+ BNXT_ULP_CLASS_HID_c909 = 0xc909,
+ BNXT_ULP_CLASS_HID_ec2d = 0xec2d,
+ BNXT_ULP_CLASS_HID_faad = 0xfaad,
BNXT_ULP_CLASS_HID_34c6 = 0x34c6,
BNXT_ULP_CLASS_HID_0c22 = 0x0c22,
BNXT_ULP_CLASS_HID_1cbe = 0x1cbe,
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h
index 1d7bbfe2cc..0a5c7e3d6e 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 20 11:56:39 2021 */
+/* date: Fri Aug 6 11:15:47 2021 */
#ifndef ULP_HDR_FIELD_ENUMS_H_
#define ULP_HDR_FIELD_ENUMS_H_
@@ -459,16 +459,14 @@ enum bnxt_ulp_hf_0_2_1_bitmask {
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC = 0x0000080000000000,
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC = 0x0000040000000000,
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_TYPE = 0x0000020000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_VER = 0x0000010000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_TOS = 0x0000008000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_LEN = 0x0000004000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_TTL = 0x0000000800000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_TC = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_FLOW_LABEL = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_PROTO_ID = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR = 0x0000000200000000
};
enum bnxt_ulp_hf_0_2_2_bitmask {
@@ -504,16 +502,7 @@ enum bnxt_ulp_hf_0_2_2_bitmask {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT = 0x0000000040000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT = 0x0000000020000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SENT_SEQ = 0x0000000010000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_RECV_ACK = 0x0000000008000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DATA_OFF = 0x0000000004000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_TCP_FLAGS = 0x0000000002000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_RX_WIN = 0x0000000001000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_CSUM = 0x0000000000800000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_URP = 0x0000000000400000
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000
};
enum bnxt_ulp_hf_0_2_3_bitmask {
@@ -540,20 +529,23 @@ enum bnxt_ulp_hf_0_2_3_bitmask {
BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC = 0x0000080000000000,
BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC = 0x0000040000000000,
BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_TYPE = 0x0000020000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_VER = 0x0000010000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_TOS = 0x0000008000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_LEN = 0x0000004000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_TTL = 0x0000000800000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT = 0x0000000040000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT = 0x0000000020000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_LENGTH = 0x0000000010000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_CSUM = 0x0000000008000000
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_TC = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_FLOW_LABEL = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_PROTO_ID = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SENT_SEQ = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_RECV_ACK = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DATA_OFF = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_TCP_FLAGS = 0x0000000008000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_RX_WIN = 0x0000000004000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_CSUM = 0x0000000002000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_URP = 0x0000000001000000
};
enum bnxt_ulp_hf_0_2_4_bitmask {
@@ -590,11 +582,134 @@ enum bnxt_ulp_hf_0_2_4_bitmask {
BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_TYPE = 0x0000000040000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_CODE = 0x0000000020000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_CSUM = 0x0000000010000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_IDENT = 0x0000000008000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_SEQ_NUM = 0x0000000004000000
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SENT_SEQ = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_RECV_ACK = 0x0000000008000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DATA_OFF = 0x0000000004000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_TCP_FLAGS = 0x0000000002000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_RX_WIN = 0x0000000001000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_CSUM = 0x0000000000800000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_URP = 0x0000000000400000
+};
+
+enum bnxt_ulp_hf_0_2_5_bitmask {
+ BNXT_ULP_HF_0_2_5_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_TC = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_FLOW_LABEL = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_PROTO_ID = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_LENGTH = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_CSUM = 0x0000000020000000
+};
+
+enum bnxt_ulp_hf_0_2_6_bitmask {
+ BNXT_ULP_HF_0_2_6_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_LENGTH = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_CSUM = 0x0000000008000000
+};
+
+enum bnxt_ulp_hf_0_2_7_bitmask {
+ BNXT_ULP_HF_0_2_7_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_TYPE = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_CODE = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_CSUM = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_IDENT = 0x0000000008000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_SEQ_NUM = 0x0000000004000000
};
enum bnxt_ulp_hf_0_3_0_bitmask {
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
index 3d1e95d18c..684fa66f48 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu Jul 8 08:44:00 2021 */
+/* date: Tue Aug 17 12:16:42 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -131,6 +131,46 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = {
.num_buckets = 8,
.hash_tbl_entries = 1024,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE << 1 |
+ BNXT_ULP_DIRECTION_INGRESS] = {
+ .name = "INGRESS GEN_TABLE_SOURCE_PROPERTY_CACHE",
+ .result_num_entries = 0,
+ .result_num_bytes = 6,
+ .key_num_bytes = 10,
+ .num_buckets = 4,
+ .hash_tbl_entries = 0,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE << 1 |
+ BNXT_ULP_DIRECTION_EGRESS] = {
+ .name = "INGRESS GEN_TABLE_SOURCE_PROPERTY_CACHE",
+ .result_num_entries = 128,
+ .result_num_bytes = 6,
+ .key_num_bytes = 10,
+ .num_buckets = 4,
+ .hash_tbl_entries = 512,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE << 1 |
+ BNXT_ULP_DIRECTION_INGRESS] = {
+ .name = "INGRESS GEN_TABLE_VXLAN_ENCAP_REC_CACHE",
+ .result_num_entries = 0,
+ .result_num_bytes = 6,
+ .key_num_bytes = 17,
+ .num_buckets = 8,
+ .hash_tbl_entries = 0,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE << 1 |
+ BNXT_ULP_DIRECTION_EGRESS] = {
+ .name = "INGRESS GEN_TABLE_VXLAN_ENCAP_REC_CACHE",
+ .result_num_entries = 256,
+ .result_num_bytes = 6,
+ .key_num_bytes = 17,
+ .num_buckets = 8,
+ .hash_tbl_entries = 1024,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
}
};
@@ -222,6 +262,7 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
.byte_count_shift = 0,
.packet_count_shift = 36,
.dynamic_pad_en = 0,
+ .dynamic_sram_en = 0,
.dev_tbls = ulp_template_wh_plus_tbls
},
[BNXT_ULP_DEVICE_ID_THOR] = {
@@ -246,12 +287,24 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
.byte_count_shift = 0,
.packet_count_shift = 35,
.dynamic_pad_en = 1,
+ .dynamic_sram_en = 1,
+ .dyn_encap_list_size = 4,
+ .dyn_encap_sizes = {{64, TF_TBL_TYPE_ACT_ENCAP_8B},
+ {128, TF_TBL_TYPE_ACT_ENCAP_16B},
+ {256, TF_TBL_TYPE_ACT_ENCAP_32B},
+ {512, TF_TBL_TYPE_ACT_ENCAP_64B}},
+ .dyn_modify_list_size = 4,
+ .dyn_modify_sizes = {{64, TF_TBL_TYPE_ACT_MODIFY_8B},
+ {128, TF_TBL_TYPE_ACT_MODIFY_16B},
+ {256, TF_TBL_TYPE_ACT_MODIFY_32B},
+ {512, TF_TBL_TYPE_ACT_MODIFY_64B}},
.em_blk_size_bits = 100,
.em_blk_align_bits = 128,
.em_key_align_bytes = 80,
.wc_slice_width = 160,
.wc_max_slices = 4,
- .wc_mode_list = {0x0000000c, 0x0000000e, 0x0000000f, 0x0000000f},
+ .wc_mode_list = {0x0000000c, 0x0000000e,
+ 0x0000000f, 0x0000000f},
.wc_mod_list_max_size = 4,
.wc_ctl_size_bits = 32,
.dev_tbls = ulp_template_thor_tbls
@@ -307,6 +360,16 @@ struct bnxt_ulp_app_capabilities_info ulp_app_cap_info_list[] = {
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.flags = BNXT_ULP_APP_CAP_SHARED_EN |
BNXT_ULP_APP_CAP_UNICAST_ONLY
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY
}
};
@@ -1279,333 +1342,1261 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = {
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
.direction = TF_DIR_TX
- }
-};
-
-/* List of tf resources required to be reserved per app/device */
-struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
+ },
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 422
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 6
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 191
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 63
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 192
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 8192
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 6912
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 1023
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 511
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 15
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
- .count = 255
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
- .count = 1
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 422
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 6
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 960
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 88
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
- .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 13168
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
- .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
- .count = 1
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 292
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 148
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 191
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 63
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 192
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 8192
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_6,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_7,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_6,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_7,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3,
+ .direction = TF_DIR_RX
+ }
+};
+
+/* List of tf resources required to be reserved per app/device */
+struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 422
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 191
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 6912
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 511
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 15
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
+ .count = 255
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 422
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 960
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 88
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 13168
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 292
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 148
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 191
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 6912
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 511
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 223
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 255
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 488
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
+ .count = 511
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 292
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 144
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 960
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 928
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 15232
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 272
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 31
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 64
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 64
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 272
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 128
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4096
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 16384
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 272
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 64
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 100
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 272
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 128
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4096
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 16384
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .count = 1
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 32
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 2
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 128
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 128
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 32
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 2
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 32
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 1024
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 32
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 2
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 128
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 6912
+ .count = 128
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 1023
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 511
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 223
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 255
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 488
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
- .count = 511
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
- .count = 1
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 292
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 144
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 960
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 928
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 15232
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
- .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
- .count = 1
+ .count = 1024
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 422
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 6
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1613,15 +2604,15 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 32
+ .count = 16
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1629,255 +2620,223 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 2048
- },
- {
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 512
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 528
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
- .count = 5
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 256
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 32
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 31
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 64
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 64
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 300
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 6
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 128
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 2048
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 13200
+ .count = 1024
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 26
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 26
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 32
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 63
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 32
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 1023
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_STATS_64,
.count = 512
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
- .count = 5
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 256
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 32
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 32
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 64
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 100
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
- .count = 32
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 200
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 110
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 128
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 2048
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 15232
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_METADATA,
- .count = 1
+ .count = 1024
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1885,7 +2844,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1893,7 +2852,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1901,7 +2860,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1909,7 +2868,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1917,7 +2876,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1925,7 +2884,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 128
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1933,7 +2892,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 128
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1941,7 +2900,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1949,7 +2908,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1957,7 +2916,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1965,7 +2924,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1973,7 +2932,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1981,7 +2940,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1989,15 +2948,15 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 64
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
@@ -2005,7 +2964,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 1024
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2013,7 +2972,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2021,7 +2980,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2029,7 +2988,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2037,7 +2996,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2045,7 +3004,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2053,7 +3012,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 128
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2061,7 +3020,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 128
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2069,7 +3028,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2077,7 +3036,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2085,7 +3044,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2093,7 +3052,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2101,7 +3060,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2109,7 +3068,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2117,7 +3076,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2125,7 +3084,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2133,7 +3092,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2141,7 +3100,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
@@ -2149,7 +3108,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 1024
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2157,7 +3116,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2165,7 +3124,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2173,7 +3132,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2181,7 +3140,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 16
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2189,7 +3148,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2197,7 +3156,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 528
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2205,7 +3164,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 256
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2213,7 +3172,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2221,7 +3180,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2229,7 +3188,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2237,7 +3196,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2245,7 +3204,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2253,7 +3212,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2261,15 +3220,15 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 512
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
@@ -2277,7 +3236,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 1024
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2285,7 +3244,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2293,7 +3252,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2301,7 +3260,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2309,7 +3268,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2317,7 +3276,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2325,7 +3284,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 512
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2333,7 +3292,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 256
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2341,7 +3300,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2349,7 +3308,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2357,7 +3316,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2365,7 +3324,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2373,7 +3332,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2381,7 +3340,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2389,7 +3348,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2397,7 +3356,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
@@ -2405,532 +3364,596 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 1024
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 422
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 191
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 63
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 192
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 128
+ .count = 8192
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 128
+ .count = 7168
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 4
+ .count = 1023
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 4
+ .count = 511
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 4
+ .count = 15
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
- .count = 4
+ .count = 255
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 422
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 960
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 64
+ .count = 88
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 13168
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 292
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 148
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 191
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 63
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 192
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 128
+ .count = 8192
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 128
+ .count = 7168
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 4
+ .count = 1023
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .count = 511
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 4
+ .count = 223
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 4
+ .count = 255
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .count = 488
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
- .count = 4
+ .count = 511
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 292
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 144
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 960
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 928
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 15232
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 16
+ .count = 63
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 528
+ .count = 4096
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 256
+ .count = 1024
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 4
+ .count = 32
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 4
+ .count = 32
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .count = 1024
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .count = 1024
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 1024
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 512
+ .count = 2048
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 6144
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 63
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 512
+ .count = 4096
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 256
+ .count = 1024
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 4
+ .count = 32
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 4
+ .count = 32
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .count = 1024
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .count = 1024
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 1024
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 2048
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 6144
}
};
@@ -3322,25 +4345,23 @@ uint8_t ulp_glb_field_tbl[] = {
[4229] = 21,
[4231] = 22,
[4244] = 2,
- [4245] = 23,
[4246] = 3,
- [4247] = 24,
[4248] = 4,
- [4249] = 25,
[4250] = 5,
- [4251] = 26,
[4252] = 6,
- [4253] = 27,
[4254] = 7,
- [4255] = 28,
[4256] = 8,
- [4257] = 29,
[4258] = 9,
- [4259] = 30,
[4260] = 10,
- [4261] = 31,
[4262] = 11,
- [4263] = 32,
+ [4265] = 23,
+ [4267] = 24,
+ [4269] = 25,
+ [4271] = 26,
+ [4273] = 27,
+ [4275] = 28,
+ [4277] = 29,
+ [4279] = 30,
[4298] = 12,
[4300] = 13,
[4302] = 14,
@@ -3374,15 +4395,6 @@ uint8_t ulp_glb_field_tbl[] = {
[4389] = 31,
[4390] = 11,
[4391] = 32,
- [4409] = 33,
- [4411] = 34,
- [4413] = 35,
- [4415] = 36,
- [4417] = 37,
- [4419] = 38,
- [4421] = 39,
- [4423] = 40,
- [4425] = 41,
[4426] = 12,
[4428] = 13,
[4430] = 14,
@@ -3397,33 +4409,36 @@ uint8_t ulp_glb_field_tbl[] = {
[4485] = 21,
[4487] = 22,
[4500] = 2,
- [4501] = 23,
[4502] = 3,
- [4503] = 24,
[4504] = 4,
- [4505] = 25,
[4506] = 5,
- [4507] = 26,
[4508] = 6,
- [4509] = 27,
[4510] = 7,
- [4511] = 28,
[4512] = 8,
- [4513] = 29,
[4514] = 9,
- [4515] = 30,
[4516] = 10,
- [4517] = 31,
[4518] = 11,
- [4519] = 32,
+ [4521] = 23,
+ [4523] = 24,
+ [4525] = 25,
+ [4527] = 26,
+ [4529] = 27,
+ [4531] = 28,
+ [4533] = 29,
+ [4535] = 30,
+ [4537] = 31,
+ [4539] = 32,
+ [4541] = 33,
+ [4543] = 34,
+ [4545] = 35,
+ [4547] = 36,
+ [4549] = 37,
+ [4551] = 38,
+ [4553] = 39,
[4554] = 12,
- [4555] = 33,
[4556] = 13,
- [4557] = 34,
[4558] = 14,
- [4559] = 35,
[4560] = 15,
- [4561] = 36,
[4574] = 16,
[4575] = 17,
[4576] = 18,
@@ -3433,11 +4448,6 @@ uint8_t ulp_glb_field_tbl[] = {
[4611] = 20,
[4613] = 21,
[4615] = 22,
- [4619] = 33,
- [4621] = 34,
- [4623] = 35,
- [4625] = 36,
- [4627] = 37,
[4628] = 2,
[4629] = 23,
[4630] = 3,
@@ -3458,6 +4468,15 @@ uint8_t ulp_glb_field_tbl[] = {
[4645] = 31,
[4646] = 11,
[4647] = 32,
+ [4665] = 33,
+ [4667] = 34,
+ [4669] = 35,
+ [4671] = 36,
+ [4673] = 37,
+ [4675] = 38,
+ [4677] = 39,
+ [4679] = 40,
+ [4681] = 41,
[4682] = 12,
[4684] = 13,
[4686] = 14,
@@ -3466,6 +4485,116 @@ uint8_t ulp_glb_field_tbl[] = {
[4703] = 17,
[4704] = 18,
[4705] = 19,
+ [4736] = 0,
+ [4737] = 1,
+ [4739] = 20,
+ [4741] = 21,
+ [4743] = 22,
+ [4756] = 2,
+ [4758] = 3,
+ [4760] = 4,
+ [4762] = 5,
+ [4764] = 6,
+ [4766] = 7,
+ [4768] = 8,
+ [4770] = 9,
+ [4772] = 10,
+ [4774] = 11,
+ [4777] = 23,
+ [4779] = 24,
+ [4781] = 25,
+ [4783] = 26,
+ [4785] = 27,
+ [4787] = 28,
+ [4789] = 29,
+ [4791] = 30,
+ [4810] = 12,
+ [4811] = 31,
+ [4812] = 13,
+ [4813] = 32,
+ [4814] = 14,
+ [4815] = 33,
+ [4816] = 15,
+ [4817] = 34,
+ [4830] = 16,
+ [4831] = 17,
+ [4832] = 18,
+ [4833] = 19,
+ [4864] = 0,
+ [4865] = 1,
+ [4867] = 20,
+ [4869] = 21,
+ [4871] = 22,
+ [4884] = 2,
+ [4885] = 23,
+ [4886] = 3,
+ [4887] = 24,
+ [4888] = 4,
+ [4889] = 25,
+ [4890] = 5,
+ [4891] = 26,
+ [4892] = 6,
+ [4893] = 27,
+ [4894] = 7,
+ [4895] = 28,
+ [4896] = 8,
+ [4897] = 29,
+ [4898] = 9,
+ [4899] = 30,
+ [4900] = 10,
+ [4901] = 31,
+ [4902] = 11,
+ [4903] = 32,
+ [4938] = 12,
+ [4939] = 33,
+ [4940] = 13,
+ [4941] = 34,
+ [4942] = 14,
+ [4943] = 35,
+ [4944] = 15,
+ [4945] = 36,
+ [4958] = 16,
+ [4959] = 17,
+ [4960] = 18,
+ [4961] = 19,
+ [4992] = 0,
+ [4993] = 1,
+ [4995] = 20,
+ [4997] = 21,
+ [4999] = 22,
+ [5003] = 33,
+ [5005] = 34,
+ [5007] = 35,
+ [5009] = 36,
+ [5011] = 37,
+ [5012] = 2,
+ [5013] = 23,
+ [5014] = 3,
+ [5015] = 24,
+ [5016] = 4,
+ [5017] = 25,
+ [5018] = 5,
+ [5019] = 26,
+ [5020] = 6,
+ [5021] = 27,
+ [5022] = 7,
+ [5023] = 28,
+ [5024] = 8,
+ [5025] = 29,
+ [5026] = 9,
+ [5027] = 30,
+ [5028] = 10,
+ [5029] = 31,
+ [5030] = 11,
+ [5031] = 32,
+ [5066] = 12,
+ [5068] = 13,
+ [5070] = 14,
+ [5072] = 15,
+ [5086] = 16,
+ [5087] = 17,
+ [5088] = 18,
+ [5089] = 19,
[6144] = 0,
[6145] = 1,
[6146] = 2,
@@ -3705,4 +4834,3 @@ uint8_t ulp_glb_field_tbl[] = {
[7638] = 6,
[7642] = 7
};
-
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
index 223ecbf843..e49c1151d3 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu Jul 8 08:44:00 2021 */
+/* date: Tue Aug 17 12:16:42 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -15,7 +15,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {
/* act_tid: 1, ingress */
[1] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 4,
+ .num_tbls = 5,
.start_tbl_idx = 0,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
@@ -26,7 +26,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {
[2] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
.num_tbls = 6,
- .start_tbl_idx = 4,
+ .start_tbl_idx = 5,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
.cond_start_idx = 3,
@@ -36,7 +36,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {
[3] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
.num_tbls = 4,
- .start_tbl_idx = 10,
+ .start_tbl_idx = 11,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
.cond_start_idx = 4,
@@ -45,8 +45,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {
/* act_tid: 4, egress */
[4] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 4,
- .start_tbl_idx = 14,
+ .num_tbls = 5,
+ .start_tbl_idx = 15,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
.cond_start_idx = 7,
@@ -56,20 +56,20 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {
[5] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
.num_tbls = 4,
- .start_tbl_idx = 18,
+ .start_tbl_idx = 20,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 10,
+ .cond_start_idx = 12,
.cond_nums = 0 }
},
/* act_tid: 6, egress */
[6] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 6,
- .start_tbl_idx = 22,
+ .num_tbls = 12,
+ .start_tbl_idx = 24,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 13,
+ .cond_start_idx = 15,
.cond_nums = 0 }
}
};
@@ -125,14 +125,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
+ .cond_false_goto = 2,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 2,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
.result_start_idx = 1,
.result_bit_size = 0,
.result_num_fields = 0,
@@ -146,7 +145,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 0,
- .cond_false_goto = 0,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 3,
.cond_nums = 0 },
@@ -158,6 +157,26 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.result_bit_size = 128,
.result_num_fields = 17
},
+ { /* act_tid: 1, , table: int_compact_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_COMPACT_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 3,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 65,
+ .result_bit_size = 64,
+ .result_num_fields = 13
+ },
{ /* act_tid: 2, , table: control.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
@@ -187,7 +206,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 65,
+ .result_start_idx = 78,
.result_bit_size = 32,
.result_num_fields = 5
},
@@ -208,13 +227,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 70,
+ .result_start_idx = 83,
.result_bit_size = 64,
.result_num_fields = 1
},
- { /* act_tid: 2, , table: int_full_act_record.0 */
+ { /* act_tid: 2, , table: int_compact_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_type = TF_TBL_TYPE_COMPACT_ACT_RECORD,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
.direction = TF_DIR_RX,
@@ -229,9 +248,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 71,
- .result_bit_size = 128,
- .result_num_fields = 17,
+ .result_start_idx = 84,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
.encap_num_fields = 0
},
{ /* act_tid: 2, , table: mirror_tbl.wr */
@@ -250,7 +269,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 88,
+ .result_start_idx = 97,
.result_bit_size = 32,
.result_num_fields = 5
},
@@ -273,7 +292,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.blob_key_bit_size = 1,
.key_bit_size = 1,
.key_num_fields = 1,
- .result_start_idx = 93,
+ .result_start_idx = 102,
.result_bit_size = 36,
.result_num_fields = 2
},
@@ -292,7 +311,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 95,
+ .result_start_idx = 104,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -311,8 +330,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 96,
+ .result_start_idx = 105,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 47
@@ -332,8 +350,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 143,
+ .result_start_idx = 152,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 47
@@ -353,7 +370,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 190,
+ .result_start_idx = 199,
.result_bit_size = 128,
.result_num_fields = 17
},
@@ -372,7 +389,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 207,
+ .result_start_idx = 216,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -391,8 +408,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 8,
- .result_start_idx = 208,
+ .result_start_idx = 217,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 11
@@ -412,8 +428,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 219,
+ .result_start_idx = 228,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 47
@@ -426,17 +441,36 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 0,
- .cond_false_goto = 0,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
.cond_start_idx = 10,
- .cond_nums = 0 },
+ .cond_nums = 2 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 266,
+ .result_start_idx = 275,
.result_bit_size = 128,
.result_num_fields = 17
},
+ { /* act_tid: 4, , table: int_compact_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_COMPACT_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 12,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 292,
+ .result_bit_size = 64,
+ .result_num_fields = 13
+ },
{ /* act_tid: 5, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
@@ -447,12 +481,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 10,
+ .cond_start_idx = 12,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 283,
+ .result_start_idx = 305,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -466,13 +500,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 2,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 11,
+ .cond_start_idx = 13,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 284,
+ .result_start_idx = 306,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 47
@@ -487,13 +520,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 12,
+ .cond_start_idx = 14,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 331,
+ .result_start_idx = 353,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 47
@@ -508,12 +540,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 13,
+ .cond_start_idx = 15,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 378,
+ .result_start_idx = 400,
.result_bit_size = 128,
.result_num_fields = 17
},
@@ -527,15 +559,48 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 13,
+ .cond_start_idx = 15,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 395,
+ .result_start_idx = 417,
.result_bit_size = 64,
.result_num_fields = 1
},
+ { /* act_tid: 6, , table: source_property_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 16,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2,
+ .blob_key_bit_size = 80,
+ .key_bit_size = 80,
+ .key_num_fields = 2,
+ .ident_start_idx = 1,
+ .ident_nums = 1
+ },
+ { /* act_tid: 6, , table: control.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 17,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
{ /* act_tid: 6, , table: sp_smac_ipv4.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
@@ -546,17 +611,40 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 14,
+ .cond_start_idx = 18,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
.record_size = 16,
- .result_start_idx = 396,
+ .result_start_idx = 418,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 3
},
+ { /* act_tid: 6, , table: source_property_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 19,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 4,
+ .blob_key_bit_size = 80,
+ .key_bit_size = 80,
+ .key_num_fields = 2,
+ .result_start_idx = 421,
+ .result_bit_size = 48,
+ .result_num_fields = 2
+ },
{ /* act_tid: 6, , table: sp_smac_ipv6.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
@@ -567,17 +655,50 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 15,
+ .cond_start_idx = 19,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.record_size = 32,
- .result_start_idx = 399,
+ .result_start_idx = 423,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 3
},
+ { /* act_tid: 6, , table: vxlan_encap_rec_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 20,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 6,
+ .blob_key_bit_size = 136,
+ .key_bit_size = 136,
+ .key_num_fields = 5,
+ .ident_start_idx = 2,
+ .ident_nums = 1
+ },
+ { /* act_tid: 6, , table: control.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 22,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
{ /* act_tid: 6, , table: int_tun_encap_record.ipv4_vxlan */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
@@ -588,17 +709,39 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 16,
+ .cond_start_idx = 23,
.cond_nums = 2 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 402,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .result_start_idx = 426,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 30
},
+ { /* act_tid: 6, , table: vxlan_encap_rec_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 25,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 11,
+ .blob_key_bit_size = 136,
+ .key_bit_size = 136,
+ .key_num_fields = 5,
+ .result_start_idx = 456,
+ .result_bit_size = 48,
+ .result_num_fields = 2
+ },
{ /* act_tid: 6, , table: int_tun_encap_record.ipv6_vxlan */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
@@ -609,13 +752,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 18,
+ .cond_start_idx = 25,
.cond_nums = 2 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 432,
+ .result_start_idx = 458,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 30
@@ -630,13 +772,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 20,
+ .cond_start_idx = 27,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 462,
+ .result_start_idx = 488,
.result_bit_size = 128,
.result_num_fields = 17
}
@@ -693,6 +835,15 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
.cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
},
+ /* cond_execute: act_tid: 4, int_full_act_record.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
+ },
/* cond_execute: act_tid: 5, int_flow_counter_tbl.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
@@ -713,6 +864,16 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
.cond_operand = BNXT_ULP_ACT_BIT_COUNT
},
+ /* cond_execute: act_tid: 6, source_property_cache.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG
+ },
+ /* cond_execute: act_tid: 6, control.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
/* cond_execute: act_tid: 6, sp_smac_ipv4.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
@@ -723,6 +884,20 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
.cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG
},
+ /* cond_execute: act_tid: 6, vxlan_encap_rec_cache.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: act_tid: 6, control.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
/* cond_execute: act_tid: 6, int_tun_encap_record.ipv4_vxlan */
{
.cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
@@ -783,6 +958,316 @@ struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = {
(BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
}
+ },
+ /* act_tid: 6, , table: source_property_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ipv4_src_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "ipv4_src_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}
+ }
+ },
+ /* act_tid: 6, , table: source_property_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ipv4_src_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "ipv4_src_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}
+ }
+ },
+ /* act_tid: 6, , table: vxlan_encap_rec_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ipv4_dst_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "ipv4_dst_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
+ }
+ },
+ /* act_tid: 6, , table: vxlan_encap_rec_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ipv4_dst_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "ipv4_dst_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
+ }
}
};
@@ -1069,38 +1554,178 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "encap_ptr",
- .field_bit_size = 16,
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr2 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_DECAP_FUNC_THRU_TUN},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_DECAP_FUNC_NONE}
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr2 = {
+ (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_RF,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr2 = {
- (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff},
+ ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER},
.field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd1",
- .field_bit_size = 16,
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 1, , table: int_compact_act_record.0 */
+ {
.description = "rsvd0",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
@@ -1137,7 +1762,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -1233,9 +1860,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "type",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
/* act_tid: 2, , table: mirror_tbl.alloc */
{
@@ -1277,31 +1902,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 2, , table: int_full_act_record.0 */
- {
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "encap_ptr",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "rsvd1",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
+ /* act_tid: 2, , table: int_compact_act_record.0 */
{
.description = "rsvd0",
.field_bit_size = 8,
@@ -1324,7 +1925,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -1387,9 +1990,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "type",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
/* act_tid: 2, , table: mirror_tbl.wr */
{
@@ -2250,7 +2851,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -2721,16 +3324,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
+ 1}
},
{
.description = "stats_ptr",
@@ -2803,6 +3399,102 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_opr1 = {
1}
},
+ /* act_tid: 4, , table: int_compact_act_record.0 */
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
/* act_tid: 5, , table: int_flow_counter_tbl.0 */
{
.description = "count",
@@ -3708,6 +4400,25 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* act_tid: 6, , table: source_property_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_SP_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_SP_PTR & 0xff}
+ },
/* act_tid: 6, , table: sp_smac_ipv6.0 */
{
.description = "smac",
@@ -4021,6 +4732,25 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
(BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff,
BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}
},
+ /* act_tid: 6, , table: vxlan_encap_rec_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "enc_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
+ },
/* act_tid: 6, , table: int_tun_encap_record.ipv6_vxlan */
{
.description = "ecv_valid",
@@ -4351,7 +5081,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -4424,5 +5156,19 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_act_ident_list[] = {
.regfile_idx = BNXT_ULP_RF_IDX_MIRROR_ID_0,
.ident_bit_size = 4,
.ident_bit_pos = 32
+ },
+ /* act_tid: 6, , table: source_property_cache.rd */
+ {
+ .description = "sp_rec_ptr",
+ .regfile_idx = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
+ .ident_bit_size = 16,
+ .ident_bit_pos = 32
+ },
+ /* act_tid: 6, , table: vxlan_encap_rec_cache.rd */
+ {
+ .description = "enc_rec_ptr",
+ .regfile_idx = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .ident_bit_size = 16,
+ .ident_bit_pos = 32
}
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
index bcb204ae13..68c1e292b2 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Fri Jul 30 09:57:44 2021 */
+/* date: Fri Aug 20 18:05:25 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -25,7 +25,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {
/* class_tid: 2, ingress */
[2] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 17,
+ .num_tbls = 24,
.start_tbl_idx = 28,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
@@ -35,18 +35,18 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {
/* class_tid: 3, egress */
[3] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 24,
- .start_tbl_idx = 45,
+ .num_tbls = 18,
+ .start_tbl_idx = 52,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 36,
+ .cond_start_idx = 39,
.cond_nums = 0 }
},
/* class_tid: 4, ingress */
[4] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
.num_tbls = 21,
- .start_tbl_idx = 69,
+ .start_tbl_idx = 70,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
.cond_start_idx = 48,
@@ -55,8 +55,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {
/* class_tid: 5, egress */
[5] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 24,
- .start_tbl_idx = 90,
+ .num_tbls = 25,
+ .start_tbl_idx = 91,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
.cond_start_idx = 52,
@@ -855,18 +855,28 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
+ { /* class_tid: 2, , table: control.ipv6_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 8,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 32,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_ipv6_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 32,
- .cond_nums = 0 },
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 33,
+ .cond_nums = 1 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
@@ -875,38 +885,57 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.key_bit_size = 14,
.key_num_fields = 3,
.ident_start_idx = 19,
- .ident_nums = 3
+ .ident_nums = 4
},
- { /* class_tid: 2, , table: control.profile_tcam_cache.f2_check */
+ { /* class_tid: 2, , table: control.f2_ipv6_prof_cache_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 4,
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 32,
+ .cond_start_idx = 34,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 2, , table: fkb_select.f2_wm */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
+ { /* class_tid: 2, , table: control.f2_v6_conflict_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
+ .cond_true_goto = 4,
+ .cond_false_goto = 1023,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 33,
+ .cond_start_idx = 35,
.cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
- .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .func_info = {
+ .func_opc = BNXT_ULP_FUNC_OPC_EQ,
+ .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
+ .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
+ .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
+ },
+ { /* class_tid: 2, , table: fkb_select.f2_l2_l3_l4_v6_em */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 36,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
.result_start_idx = 426,
.result_bit_size = 106,
.result_num_fields = 106
},
- { /* class_tid: 2, , table: profile_tcam.f2 */
+ { /* class_tid: 2, , table: profile_tcam.f2_l2_l3_l4_v6_em */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.direction = TF_DIR_RX,
@@ -914,14 +943,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 34,
+ .cond_start_idx = 36,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
- .pri_operand = 1,
+ .pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.key_start_idx = 1146,
@@ -930,9 +959,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.key_num_fields = 43,
.result_start_idx = 532,
.result_bit_size = 33,
- .result_num_fields = 8
+ .result_num_fields = 8,
+ .ident_start_idx = 23,
+ .ident_nums = 1
},
- { /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_l2_l3_l4_v6_wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
@@ -942,7 +973,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 34,
+ .cond_start_idx = 36,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
@@ -955,135 +986,81 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 138,
.result_num_fields = 7
},
- { /* class_tid: 2, , table: wm.l3_l4.ipv4 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ { /* class_tid: 2, , table: em.f2_l2_l3_l4_v6.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_INTERNAL,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 0,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 34,
- .cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 36,
+ .cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
- .pri_operand = 0,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.key_start_idx = 1192,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
.result_start_idx = 547,
- .result_bit_size = 38,
- .result_num_fields = 5
- },
- { /* class_tid: 2, , table: wm.l3_l4.ipv6 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 0,
- .cond_false_goto = 0,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 35,
- .cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
- .pri_operand = 0,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1306,
- .blob_key_bit_size = 0,
- .key_bit_size = 0,
- .key_num_fields = 114,
- .result_start_idx = 552,
- .result_bit_size = 38,
- .result_num_fields = 5
- },
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 6,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 36,
- .cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1420,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .ident_start_idx = 22,
- .ident_nums = 1
+ .result_bit_size = 0,
+ .result_num_fields = 6
},
- { /* class_tid: 3, , table: mac_addr_cache.rd */
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 37,
+ .cond_start_idx = 36,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1421,
- .blob_key_bit_size = 73,
- .key_bit_size = 73,
- .key_num_fields = 5,
- .ident_start_idx = 23,
- .ident_nums = 1
+ .key_start_idx = 1306,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .ident_start_idx = 24,
+ .ident_nums = 3
},
- { /* class_tid: 3, , table: control.0 */
+ { /* class_tid: 2, , table: control.profile_tcam_cache.f2_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 4,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 37,
+ .cond_start_idx = 36,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 3, , table: port_table.egr.rd */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
- .direction = TF_DIR_TX,
+ { /* class_tid: 2, , table: fkb_select.f2_wm */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 38,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 37,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .key_start_idx = 1426,
- .blob_key_bit_size = 10,
- .key_bit_size = 10,
- .key_num_fields = 1,
- .ident_start_idx = 24,
- .ident_nums = 3
+ .result_start_idx = 553,
+ .result_bit_size = 106,
+ .result_num_fields = 106
},
- { /* class_tid: 3, , table: l2_cntxt_tcam.0 */
+ { /* class_tid: 2, , table: profile_tcam.f2 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .direction = TF_DIR_TX,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
@@ -1091,26 +1068,27 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_start_idx = 38,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
- .pri_operand = 0,
- .key_start_idx = 1427,
- .blob_key_bit_size = 213,
- .key_bit_size = 213,
- .key_num_fields = 21,
- .result_start_idx = 557,
- .result_bit_size = 43,
- .result_num_fields = 6,
- .ident_start_idx = 27,
- .ident_nums = 1
+ .pri_operand = 1,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 1309,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 659,
+ .result_bit_size = 33,
+ .result_num_fields = 8
},
- { /* class_tid: 3, , table: mac_addr_cache.wr */
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
@@ -1118,15 +1096,61 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_start_idx = 38,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1448,
- .blob_key_bit_size = 73,
- .key_bit_size = 73,
- .key_num_fields = 5,
- .result_start_idx = 563,
- .result_bit_size = 62,
- .result_num_fields = 4
+ .key_start_idx = 1352,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .result_start_idx = 667,
+ .result_bit_size = 138,
+ .result_num_fields = 7
+ },
+ { /* class_tid: 2, , table: wm.l3_l4.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 38,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 1355,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 674,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 39,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1469,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 27,
+ .ident_nums = 1
},
{ /* class_tid: 3, , table: control.ipv6_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
@@ -1135,7 +1159,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 8,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 38,
+ .cond_start_idx = 39,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
@@ -1148,12 +1172,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1023,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 39,
+ .cond_start_idx = 40,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1453,
+ .key_start_idx = 1470,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -1167,7 +1191,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 2,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 40,
+ .cond_start_idx = 41,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
@@ -1179,7 +1203,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 4,
.cond_false_goto = 1023,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 41,
+ .cond_start_idx = 42,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.func_info = {
@@ -1198,13 +1222,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .result_start_idx = 567,
+ .result_start_idx = 679,
.result_bit_size = 106,
.result_num_fields = 106
},
@@ -1216,7 +1240,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
@@ -1226,11 +1250,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 1456,
+ .key_start_idx = 1473,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
- .result_start_idx = 673,
+ .result_start_idx = 785,
.result_bit_size = 33,
.result_num_fields = 8,
.ident_start_idx = 32,
@@ -1246,16 +1270,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1499,
+ .key_start_idx = 1516,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
- .result_start_idx = 681,
+ .result_start_idx = 793,
.result_bit_size = 138,
.result_num_fields = 7
},
@@ -1267,15 +1291,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1502,
+ .key_start_idx = 1519,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
- .result_start_idx = 688,
+ .result_start_idx = 800,
.result_bit_size = 0,
.result_num_fields = 6
},
@@ -1288,12 +1312,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1616,
+ .key_start_idx = 1633,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -1304,32 +1328,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 2,
- .cond_false_goto = 1,
+ .cond_true_goto = 1,
+ .cond_false_goto = 5,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 3, , table: control.conflict_check */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 5,
- .cond_false_goto = 1023,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 43,
- .cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .func_info = {
- .func_opc = BNXT_ULP_FUNC_OPC_EQ,
- .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
- .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
- .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
- .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
- .func_dst_opr = BNXT_ULP_RF_IDX_CC }
- },
{ /* class_tid: 3, , table: fkb_select.l3_l4_wc */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
@@ -1343,7 +1349,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 694,
+ .result_start_idx = 806,
.result_bit_size = 106,
.result_num_fields = 106
},
@@ -1365,11 +1371,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 1619,
+ .key_start_idx = 1636,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
- .result_start_idx = 800,
+ .result_start_idx = 912,
.result_bit_size = 33,
.result_num_fields = 8,
.ident_start_idx = 35,
@@ -1393,11 +1399,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 1662,
+ .key_start_idx = 1679,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
- .result_start_idx = 808,
+ .result_start_idx = 920,
.result_bit_size = 33,
.result_num_fields = 8,
.ident_start_idx = 35,
@@ -1418,11 +1424,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1705,
+ .key_start_idx = 1722,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
- .result_start_idx = 816,
+ .result_start_idx = 928,
.result_bit_size = 138,
.result_num_fields = 7
},
@@ -1443,11 +1449,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1708,
+ .key_start_idx = 1725,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
- .result_start_idx = 823,
+ .result_start_idx = 935,
.result_bit_size = 38,
.result_num_fields = 5
},
@@ -1468,11 +1474,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1822,
+ .key_start_idx = 1839,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
- .result_start_idx = 828,
+ .result_start_idx = 940,
.result_bit_size = 38,
.result_num_fields = 5
},
@@ -1493,11 +1499,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1936,
+ .key_start_idx = 1953,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
- .result_start_idx = 833,
+ .result_start_idx = 945,
.result_bit_size = 38,
.result_num_fields = 5
},
@@ -1517,7 +1523,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 838,
+ .result_start_idx = 950,
.result_bit_size = 128,
.result_num_fields = 17
},
@@ -1535,11 +1541,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2050,
+ .key_start_idx = 2067,
.blob_key_bit_size = 10,
.key_bit_size = 10,
.key_num_fields = 1,
- .result_start_idx = 855,
+ .result_start_idx = 967,
.result_bit_size = 152,
.result_num_fields = 5
},
@@ -1557,7 +1563,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2051,
+ .key_start_idx = 2068,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1594,11 +1600,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 2052,
+ .key_start_idx = 2069,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
- .result_start_idx = 860,
+ .result_start_idx = 972,
.result_bit_size = 43,
.result_num_fields = 6,
.ident_start_idx = 35,
@@ -1618,11 +1624,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2073,
+ .key_start_idx = 2090,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .result_start_idx = 866,
+ .result_start_idx = 978,
.result_bit_size = 62,
.result_num_fields = 4
},
@@ -1639,7 +1645,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 870,
+ .result_start_idx = 982,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -1656,7 +1662,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 871,
+ .result_start_idx = 983,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -1676,7 +1682,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 872,
+ .result_start_idx = 984,
.result_bit_size = 128,
.result_num_fields = 17,
.encap_num_fields = 0
@@ -1695,11 +1701,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2074,
+ .key_start_idx = 2091,
.blob_key_bit_size = 10,
.key_bit_size = 10,
.key_num_fields = 1,
- .result_start_idx = 889,
+ .result_start_idx = 1001,
.result_bit_size = 152,
.result_num_fields = 5
},
@@ -1728,7 +1734,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2075,
+ .key_start_idx = 2092,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1761,7 +1767,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .result_start_idx = 894,
+ .result_start_idx = 1006,
.result_bit_size = 64,
.result_num_fields = 8
},
@@ -1779,11 +1785,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2076,
+ .key_start_idx = 2093,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .result_start_idx = 902,
+ .result_start_idx = 1014,
.result_bit_size = 62,
.result_num_fields = 4
},
@@ -1801,7 +1807,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2077,
+ .key_start_idx = 2094,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1836,11 +1842,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 2078,
+ .key_start_idx = 2095,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
- .result_start_idx = 906,
+ .result_start_idx = 1018,
.result_bit_size = 43,
.result_num_fields = 6,
.ident_start_idx = 36,
@@ -1860,11 +1866,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2099,
+ .key_start_idx = 2116,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .result_start_idx = 912,
+ .result_start_idx = 1024,
.result_bit_size = 62,
.result_num_fields = 4
},
@@ -1881,7 +1887,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 916,
+ .result_start_idx = 1028,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -1898,7 +1904,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 917,
+ .result_start_idx = 1029,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -1918,11 +1924,33 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 918,
+ .result_start_idx = 1030,
.result_bit_size = 128,
.result_num_fields = 17,
.encap_num_fields = 0
},
+ { /* class_tid: 5, , table: port_table.egr_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2117,
+ .blob_key_bit_size = 10,
+ .key_bit_size = 10,
+ .key_num_fields = 1,
+ .result_start_idx = 1047,
+ .result_bit_size = 152,
+ .result_num_fields = 5
+ },
{ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
@@ -1937,7 +1965,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2100,
+ .key_start_idx = 2118,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1972,11 +2000,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .key_start_idx = 2101,
+ .key_start_idx = 2119,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
- .result_start_idx = 935,
+ .result_start_idx = 1052,
.result_bit_size = 43,
.result_num_fields = 6,
.ident_start_idx = 37,
@@ -1996,11 +2024,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2122,
+ .key_start_idx = 2140,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .result_start_idx = 941,
+ .result_start_idx = 1058,
.result_bit_size = 62,
.result_num_fields = 4
},
@@ -2017,7 +2045,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 945,
+ .result_start_idx = 1062,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -2034,7 +2062,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 946,
+ .result_start_idx = 1063,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -2054,7 +2082,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
- .result_start_idx = 947,
+ .result_start_idx = 1064,
.result_bit_size = 128,
.result_num_fields = 17,
.encap_num_fields = 0
@@ -2072,7 +2100,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_SVIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 964,
+ .result_start_idx = 1081,
.result_bit_size = 64,
.result_num_fields = 8
},
@@ -2091,7 +2119,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2123,
+ .key_start_idx = 2141,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -2124,7 +2152,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .result_start_idx = 972,
+ .result_start_idx = 1089,
.result_bit_size = 64,
.result_num_fields = 8
},
@@ -2142,11 +2170,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2124,
+ .key_start_idx = 2142,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .result_start_idx = 980,
+ .result_start_idx = 1097,
.result_bit_size = 62,
.result_num_fields = 4
},
@@ -2165,7 +2193,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 984,
+ .result_start_idx = 1101,
.result_bit_size = 16,
.result_num_fields = 1
},
@@ -2184,8 +2212,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 985,
+ .result_start_idx = 1102,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 47
@@ -2206,7 +2233,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 1032,
+ .result_start_idx = 1149,
.result_bit_size = 128,
.result_num_fields = 17
},
@@ -2224,7 +2251,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2125,
+ .key_start_idx = 2143,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -2261,11 +2288,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 2126,
+ .key_start_idx = 2144,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
- .result_start_idx = 1049,
+ .result_start_idx = 1166,
.result_bit_size = 43,
.result_num_fields = 6,
.ident_start_idx = 38,
@@ -2284,7 +2311,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 1055,
+ .result_start_idx = 1172,
.result_bit_size = 106,
.result_num_fields = 106
},
@@ -2306,11 +2333,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 2147,
+ .key_start_idx = 2165,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
- .result_start_idx = 1161,
+ .result_start_idx = 1278,
.result_bit_size = 33,
.result_num_fields = 8
},
@@ -2325,15 +2352,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 55,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2190,
+ .key_start_idx = 2208,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .ident_start_idx = 38,
- .ident_nums = 1
+ .result_start_idx = 1286,
+ .result_bit_size = 62,
+ .result_num_fields = 4
},
{ /* class_tid: 5, , table: int_full_act_record.vfr_ing0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2351,7 +2379,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 1169,
+ .result_start_idx = 1290,
.result_bit_size = 128,
.result_num_fields = 17
},
@@ -2367,11 +2395,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 2191,
+ .key_start_idx = 2209,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
- .result_start_idx = 1186,
+ .result_start_idx = 1307,
.result_bit_size = 0,
.result_num_fields = 6
}
@@ -2529,6 +2557,26 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
+ /* cond_execute: class_tid: 2, control.ipv6_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6
+ },
+ /* cond_execute: class_tid: 2, profile_tcam_cache.f2_ipv6_rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH
+ },
+ /* cond_execute: class_tid: 2, control.f2_ipv6_prof_cache_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 2, control.f2_v6_conflict_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_CC
+ },
/* cond_execute: class_tid: 2, control.profile_tcam_cache.f2_check */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
@@ -2544,21 +2592,6 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
},
- /* cond_execute: class_tid: 2, wm.l3_l4.ipv6 */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
- .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
- },
- /* cond_execute: class_tid: 3, l2_cntxt_tcam_cache.rd */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET,
- .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC
- },
- /* cond_execute: class_tid: 3, control.0 */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
- .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
- },
/* cond_execute: class_tid: 3, control.ipv6_check */
{
.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
@@ -2584,11 +2617,6 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 3, control.conflict_check */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
- .cond_operand = BNXT_ULP_RF_IDX_CC
- },
/* cond_execute: class_tid: 3, profile_tcam.l3_l4.ip */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
@@ -5115,12 +5143,24 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -8346,7 +8386,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr1 = {
(BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
@@ -8373,7 +8416,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr1 = {
(BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
@@ -15050,7 +15096,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr1 = {
(BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
@@ -15077,7 +15126,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr1 = {
(BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
@@ -16551,7 +16603,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr1 = {
(BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
@@ -16578,7 +16633,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr1 = {
(BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
@@ -18283,7 +18341,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
- /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_ipv6_rd */
{
.field_info_mask = {
.description = "recycle_cnt",
@@ -18338,7 +18396,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
}
},
- /* class_tid: 2, , table: profile_tcam.f2 */
+ /* class_tid: 2, , table: profile_tcam.f2_l2_l3_l4_v6_em */
{
.field_info_mask = {
.description = "l4_hdr_is_udp_tcp",
@@ -18357,14 +18415,34 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l4_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l4_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_I_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_UDP}
}
},
{
@@ -18372,7 +18450,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l4_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4 & 0xff}
},
.field_info_spec = {
.description = "l4_hdr_error",
@@ -18386,13 +18467,19 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l4_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4 & 0xff}
},
.field_info_spec = {
.description = "l4_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4 & 0xff}
}
},
{
@@ -18456,13 +18543,17 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l3_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
.description = "l3_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
}
},
{
@@ -18470,7 +18561,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l3_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
.description = "l3_hdr_error",
@@ -18484,13 +18577,17 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
.description = "l3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
}
},
{
@@ -18526,7 +18623,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l2_uc_mc_bc",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
.description = "l2_uc_mc_bc",
@@ -18990,15 +19089,13 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
1}
}
},
- /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_l2_l3_l4_v6_wr */
{
.field_info_mask = {
.description = "recycle_cnt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "recycle_cnt",
@@ -19045,10 +19142,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
}
},
- /* class_tid: 2, , table: wm.l3_l4.ipv4 */
+ /* class_tid: 2, , table: em.f2_l2_l3_l4_v6.0 */
{
.field_info_mask = {
- .description = "wc_profile_id",
+ .description = "em_profile_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
@@ -19056,13 +19153,13 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "wc_profile_id",
+ .description = "em_profile_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 & 0xff}
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
}
},
{
@@ -19401,20 +19498,12 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "tl3.dip.ipv4",
.field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
.description = "tl3.dip.ipv4",
.field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
@@ -19766,7 +19855,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr2 = {
(BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
.field_info_spec = {
.description = "tids",
@@ -19780,7 +19869,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr2 = {
(BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -19879,12 +19968,30 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
.field_info_spec = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -20059,12 +20166,30 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.sip.ipv6",
.field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
.field_info_spec = {
.description = "l3.sip.ipv6",
.field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -20083,42 +20208,42 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.dip.ipv4",
.field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
.description = "l3.dip.ipv4",
.field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
.description = "l3.dip.ipv6",
.field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
.field_info_spec = {
.description = "l3.dip.ipv6",
.field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -20149,12 +20274,24 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -20341,24 +20478,50 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l4.src",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
.description = "l4.src",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
.field_info_mask = {
.description = "l4.dst",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
.description = "l4.dst",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -20481,2254 +20644,2585 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
- /* class_tid: 2, , table: wm.l3_l4.ipv6 */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
{
.field_info_mask = {
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 & 0xff}
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
}
},
+ /* class_tid: 2, , table: profile_tcam.f2 */
{
.field_info_mask = {
- .description = "parif",
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "parif",
+ .description = "l4_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "lcos",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "lcos",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "meta",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "meta",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "rcyc_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "rcyc_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "loopback",
+ .description = "l3_hdr_isIP",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "loopback",
+ .description = "l3_hdr_isIP",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_l2type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_l2type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl2_dt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_dt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_sa",
+ .description = "l2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_sa",
+ .description = "l2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_nvt",
+ .description = "l2_uc_mc_bc",
.field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_nvt",
+ .description = "l2_uc_mc_bc",
.field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ovp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovd",
+ .description = "l2_hdr_error",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ovd",
+ .description = "l2_hdr_error",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ovv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L2_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl2_ovt",
+ .description = "tun_hdr_flags",
.field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovt",
+ .description = "tun_hdr_flags",
.field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ivp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivd",
+ .description = "tun_hdr_err",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ivd",
+ .description = "tun_hdr_err",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl2_ivv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ivv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ivt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl2_etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.l3type",
+ .description = "tl4_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.l3type",
+ .description = "tl4_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL4_HDR_TYPE_UDP}
}
},
{
.field_info_mask = {
- .description = "tl3.sip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.sip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.sip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.sip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL4_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl3.sip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.sip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.dip.ipv4",
- .field_bit_size = 32,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.dip.ipv4",
- .field_bit_size = 32,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.dip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.dip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.dip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.dip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl3.fid.ipv4",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.fid.ipv4",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl3.fid.ipv6",
- .field_bit_size = 20,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.fid.ipv6",
- .field_bit_size = 20,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl3.qos",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.qos",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl3.ieh_nonext",
+ .description = "tl3_hdr_error",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.ieh_nonext",
+ .description = "tl3_hdr_error",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_esp",
+ .description = "tl3_hdr_valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.ieh_esp",
+ .description = "tl3_hdr_valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL3_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_auth",
+ .description = "tl2_two_vtags",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.ieh_auth",
+ .description = "tl2_two_vtags",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_dest",
+ .description = "tl2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.ieh_dest",
+ .description = "tl2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_hop",
+ .description = "tl2_hdr_valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.ieh_hop",
+ .description = "tl2_hdr_valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL2_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_1frag",
+ .description = "hrec_next",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.ieh_1frag",
+ .description = "hrec_next",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl3.l3err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.l3err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
.field_info_spec = {
- .description = "tl4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
}
},
+ /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
{
.field_info_mask = {
- .description = "tl4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
}
},
+ /* class_tid: 2, , table: wm.l3_l4.ipv4 */
{
.field_info_mask = {
- .description = "tl4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "tl4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
}
},
{
.field_info_mask = {
- .description = "tuntype",
+ .description = "parif",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tuntype",
+ .description = "parif",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tflags",
- .field_bit_size = 3,
+ .description = "spif",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tflags",
- .field_bit_size = 3,
+ .description = "spif",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tids",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tids",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "tid",
- .field_bit_size = 32,
+ .description = "svif",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tid",
- .field_bit_size = 32,
+ .description = "svif",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tctxts",
- .field_bit_size = 24,
+ .description = "lcos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tctxts",
- .field_bit_size = 24,
+ .description = "lcos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tctxt",
- .field_bit_size = 32,
+ .description = "meta",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tctxt",
- .field_bit_size = 32,
+ .description = "meta",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tqos",
- .field_bit_size = 3,
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tqos",
- .field_bit_size = 3,
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "terr",
- .field_bit_size = 4,
+ .description = "loopback",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "terr",
- .field_bit_size = 4,
+ .description = "loopback",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_l2type",
+ .description = "tl2_l2type",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_l2type",
+ .description = "tl2_l2type",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_dmac",
+ .description = "tl2_dmac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_dmac",
+ .description = "tl2_dmac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_smac",
+ .description = "tl2_smac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_smac",
+ .description = "tl2_smac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_dt",
+ .description = "tl2_dt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_dt",
+ .description = "tl2_dt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_sa",
+ .description = "tl2_sa",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_sa",
+ .description = "tl2_sa",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_nvt",
+ .description = "tl2_nvt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_nvt",
+ .description = "tl2_nvt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovp",
+ .description = "tl2_ovp",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovp",
+ .description = "tl2_ovp",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovd",
+ .description = "tl2_ovd",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovd",
+ .description = "tl2_ovd",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovv",
+ .description = "tl2_ovv",
.field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovv",
+ .description = "tl2_ovv",
.field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovt",
+ .description = "tl2_ovt",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovt",
+ .description = "tl2_ovt",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivp",
+ .description = "tl2_ivp",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivp",
+ .description = "tl2_ivp",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivd",
+ .description = "tl2_ivd",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivd",
+ .description = "tl2_ivd",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivv",
+ .description = "tl2_ivv",
.field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivv",
+ .description = "tl2_ivv",
.field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivt",
+ .description = "tl2_ivt",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivt",
+ .description = "tl2_ivt",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_etype",
+ .description = "tl2_etype",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_etype",
+ .description = "tl2_etype",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.l3type",
+ .description = "tl3.l3type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.l3type",
+ .description = "tl3.l3type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.sip.ipv4",
+ .description = "tl3.sip.ipv4",
.field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.sip.ipv4",
+ .description = "tl3.sip.ipv4",
.field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.sip.ipv6",
+ .description = "tl3.sip.ipv6",
.field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.sip.ipv6",
+ .description = "tl3.sip.ipv6",
.field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.sip_selcmp.ipv6",
+ .description = "tl3.sip_selcmp.ipv6",
.field_bit_size = 72,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.sip_selcmp.ipv6",
+ .description = "tl3.sip_selcmp.ipv6",
.field_bit_size = 72,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.dip.ipv4",
+ .description = "tl3.dip.ipv4",
.field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.dip.ipv4",
+ .description = "tl3.dip.ipv4",
.field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.dip.ipv6",
+ .description = "tl3.dip.ipv6",
.field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.dip.ipv6",
+ .description = "tl3.dip.ipv6",
.field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.dip_selcmp.ipv6",
+ .description = "tl3.dip_selcmp.ipv6",
.field_bit_size = 72,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.dip_selcmp.ipv6",
+ .description = "tl3.dip_selcmp.ipv6",
.field_bit_size = 72,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ttl",
+ .description = "tl3.ttl",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ttl",
+ .description = "tl3.ttl",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.prot",
+ .description = "tl3.prot",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.prot",
+ .description = "tl3.prot",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.fid.ipv4",
+ .description = "tl3.fid.ipv4",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.fid.ipv4",
+ .description = "tl3.fid.ipv4",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.fid.ipv6",
+ .description = "tl3.fid.ipv6",
.field_bit_size = 20,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.fid.ipv6",
+ .description = "tl3.fid.ipv6",
.field_bit_size = 20,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.qos",
+ .description = "tl3.qos",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.qos",
+ .description = "tl3.qos",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_nonext",
+ .description = "tl3.ieh_nonext",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_nonext",
+ .description = "tl3.ieh_nonext",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_esp",
+ .description = "tl3.ieh_esp",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_esp",
+ .description = "tl3.ieh_esp",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_auth",
+ .description = "tl3.ieh_auth",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_auth",
+ .description = "tl3.ieh_auth",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_dest",
+ .description = "tl3.ieh_dest",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_dest",
+ .description = "tl3.ieh_dest",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_frag",
+ .description = "tl3.ieh_frag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_frag",
+ .description = "tl3.ieh_frag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_rthdr",
+ .description = "tl3.ieh_rthdr",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_rthdr",
+ .description = "tl3.ieh_rthdr",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_hop",
+ .description = "tl3.ieh_hop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_hop",
+ .description = "tl3.ieh_hop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_1frag",
+ .description = "tl3.ieh_1frag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_1frag",
+ .description = "tl3.ieh_1frag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.df",
+ .description = "tl3.df",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.df",
+ .description = "tl3.df",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.l3err.ipv4",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.l3err.ipv4",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "l3.l3err.ipv6",
+ .description = "tl3.l3err",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.l3err.ipv6",
+ .description = "tl3.l3err",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.l4type",
+ .description = "tl4.l4type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.l4type",
+ .description = "tl4.l4type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.src",
+ .description = "tl4.src",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.src",
+ .description = "tl4.src",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.dst",
+ .description = "tl4.dst",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.dst",
+ .description = "tl4.dst",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.flags",
+ .description = "tl4.flags",
.field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.flags",
+ .description = "tl4.flags",
.field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.seq",
+ .description = "tl4.seq",
.field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.seq",
+ .description = "tl4.seq",
.field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.ack",
- .field_bit_size = 32,
+ .description = "tl4.pa",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.ack",
- .field_bit_size = 32,
+ .description = "tl4.pa",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.win",
- .field_bit_size = 16,
+ .description = "tl4.opt",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.win",
- .field_bit_size = 16,
+ .description = "tl4.opt",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.pa",
+ .description = "tl4.tcpts",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.pa",
+ .description = "tl4.tcpts",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.opt",
- .field_bit_size = 1,
+ .description = "tl4.err",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.opt",
- .field_bit_size = 1,
+ .description = "tl4.err",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.tcpts",
- .field_bit_size = 1,
+ .description = "tuntype",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.tcpts",
- .field_bit_size = 1,
+ .description = "tuntype",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.tsval",
- .field_bit_size = 32,
+ .description = "tflags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.tsval",
- .field_bit_size = 32,
+ .description = "tflags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.txecr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l4.txecr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4.err",
- .field_bit_size = 4,
+ .description = "tid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.err",
- .field_bit_size = 4,
+ .description = "tid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
- /* class_tid: 3, , table: mac_addr_cache.rd */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "mac_addr",
+ .description = "l2_dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "mac_addr",
+ .description = "l2_dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
}
},
- /* class_tid: 3, , table: port_table.egr.rd */
{
.field_info_mask = {
- .description = "dev.port_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- 0xff,
- 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "dev.port_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam.0 */
{
.field_info_mask = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_tpid_sel",
+ .description = "l2_ovp",
.field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovlan_tpid_sel",
+ .description = "l2_ovp",
.field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- }
- },
- {
- .field_info_mask = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
- /* class_tid: 3, , table: mac_addr_cache.wr */
{
.field_info_mask = {
- .description = "svif",
+ .description = "l3.ttl",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "svif",
+ .description = "l3.ttl",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ (BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ (BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
- /* class_tid: 3, , table: profile_tcam_cache.ipv6_rd */
{
.field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
- /* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */
{
.field_info_mask = {
- .description = "l4_hdr_is_udp_tcp",
+ .description = "l3.ieh_dest",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4_hdr_is_udp_tcp",
+ .description = "l3.ieh_dest",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_THOR_SYM_L4_HDR_TYPE_TCP},
- .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr3 = {
- ULP_THOR_SYM_L4_HDR_TYPE_UDP}
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4_hdr_error",
+ .description = "l3.ieh_rthdr",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4_hdr_error",
+ .description = "l3.ieh_rthdr",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4_hdr_valid",
+ .description = "l3.ieh_hop",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4_hdr_valid",
+ .description = "l3.ieh_hop",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "ieh",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "ieh",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3_ipv6_cmp_dst",
+ .description = "l3.df",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3_ipv6_cmp_dst",
+ .description = "l3.df",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3_hdr_type",
+ .description = "l4.l4type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3_hdr_type",
+ .description = "l4.l4type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 0xff}
+ (BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 0xff}
+ (BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ULP_THOR_SYM_L3_HDR_VALID_YES}
+ (BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_vtag_present",
- .field_bit_size = 1,
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam_cache.ipv6_rd */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_UDP}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
.field_opr1 = {
@@ -23114,17 +23608,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_spec = {
.description = "prof_func_id",
.field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
@@ -23230,17 +23716,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_spec = {
.description = "prof_func_id",
.field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
@@ -24082,12 +24560,30 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
.field_info_spec = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -24388,12 +24884,24 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -24773,17 +25281,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_spec = {
.description = "prof_func_id",
.field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
@@ -25425,17 +25925,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_spec = {
.description = "prof_func_id",
.field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
@@ -26095,17 +26587,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_spec = {
.description = "prof_func_id",
.field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
@@ -26211,17 +26695,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_spec = {
.description = "prof_func_id",
.field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
@@ -27063,12 +27539,30 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -27349,12 +27843,27 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -27542,47 +28051,29 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l4.src",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
.field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l4.src",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
.field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -27590,47 +28081,29 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l4.dst",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
.field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l4.dst",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
.field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -28571,12 +29044,30 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -28857,12 +29348,27 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -30011,12 +30517,30 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -30285,12 +30809,14 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -31393,227 +31919,11 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
}
},
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
- {
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
- }
- },
- /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
- {
- .field_info_mask = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
+ /* class_tid: 5, , table: port_table.egr_wr */
{
.field_info_mask = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
+ .description = "dev.port_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
@@ -31621,104 +31931,16 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
+ .description = "dev.port_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
- }
- },
- {
- .field_info_mask = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- .field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
}
},
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
{
.field_info_mask = {
.description = "svif",
@@ -31738,67 +31960,392 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
}
},
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.rd_egr0 */
- {
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
- }
- },
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
- {
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
- }
- },
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_rd_vfr */
- {
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
- }
- },
- /* class_tid: 5, , table: l2_cntxt_tcam.vfr_ing0 */
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.rd_egr0 */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_rd_vfr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam.vfr_ing0 */
{
.field_info_mask = {
.description = "etype",
@@ -33860,332 +34407,1091 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
}
},
{
- .field_info_mask = {
- .description = "l3.ieh_auth",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_auth",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ }
+};
+
+struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
+ /* class_tid: 1, , table: l2_cntxt_tcam.0 */
+ {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ },
+ {
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ },
+ {
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ },
+ /* class_tid: 1, , table: mac_addr_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: fkb_select.l2_l3_l4_v6_em */
+ {
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "parif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "spif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "lcos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "loopback.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tuntype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tflags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tqos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "terr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ },
+ {
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ },
+ {
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ },
+ {
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}
+ },
+ {
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.l3err.ipv4",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.l3err.ipv4",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}
},
{
- .field_info_mask = {
- .description = "l3.l3err.ipv6",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.l3err.ipv6",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}
},
{
- .field_info_mask = {
- .description = "l4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_win.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.ack",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.ack",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.win",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.win",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */
{
- .field_info_mask = {
- .description = "l4.tsval",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.tsval",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.txecr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.txecr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- }
-};
-
-struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
- /* class_tid: 1, , table: l2_cntxt_tcam.0 */
- {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "em_key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "em_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "em_search_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ 1}
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: mac_addr_cache.wr */
+ /* class_tid: 1, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -34196,27 +35502,98 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "l2_cntxt_tcam_index",
+ .description = "profile_tcam_index",
.field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "wc_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ },
+ /* class_tid: 1, , table: em.l2_l3_l4_v6.0 */
+ {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: fkb_select.l2_l3_l4_v6_em */
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: fkb_select.l3_l4_wm */
{
.description = "l2_cntxt_id.en",
.field_bit_size = 1,
@@ -34589,10 +35966,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ 1}
},
{
.description = "l2_dt.en",
@@ -34651,22 +36027,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
{
.description = "l2_ivv.en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ 1}
},
{
.description = "l2_ivt.en",
@@ -34690,10 +36054,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ 1}
},
{
.description = "l3_sip_selcmp.en",
@@ -34705,10 +36068,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ 1}
},
{
.description = "l3_dip_selcmp.en",
@@ -34726,7 +36088,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l3_fid.en",
@@ -34810,19 +36174,17 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}
+ 1}
},
{
.description = "l4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}
+ 1}
},
{
.description = "l4_flags.en",
@@ -34884,166 +36246,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */
- {
- .description = "wc_key_id",
- .field_bit_size = 6,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "wc_search_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "em_key_type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "em_key_id",
- .field_bit_size = 6,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
- },
- {
- .description = "em_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
- },
- {
- .description = "em_search_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- {
- .description = "pl_byp_lkup_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- /* class_tid: 1, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
- {
- .description = "rid",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
- },
- {
- .description = "profile_tcam_index",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
- },
- {
- .description = "em_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
- },
- {
- .description = "em_key_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
- },
- {
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "wc_key_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "flow_sig_id",
- .field_bit_size = 64,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
- },
- /* class_tid: 1, , table: em.l2_l3_l4_v6.0 */
- {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- {
- .description = "strength",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 3}
- },
- {
- .description = "data",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
- },
- {
- .description = "opcode",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "meta_prof",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "ctxt_data",
- .field_bit_size = 14,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- /* class_tid: 1, , table: fkb_select.l3_l4_wm */
+ /* class_tid: 1, , table: fkb_select.l3_l4_wm_vxlan */
{
.description = "l2_cntxt_id.en",
.field_bit_size = 1,
@@ -35170,7 +36373,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl2_ivv.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl2_ivt.en",
@@ -35194,7 +36399,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl3_sip_selcmp.en",
@@ -35206,7 +36413,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl3_dip_selcmp.en",
@@ -35224,7 +36433,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl3_fid.en",
@@ -35308,13 +36519,17 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl4_flags.en",
@@ -35478,9 +36693,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_ivv.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l2_ivt.en",
@@ -35504,9 +36717,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l3_sip_selcmp.en",
@@ -35518,9 +36729,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l3_dip_selcmp.en",
@@ -35538,9 +36747,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l3_fid.en",
@@ -35624,17 +36831,13 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l4_flags.en",
@@ -35696,9 +36899,112 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: fkb_select.l3_l4_wm_vxlan */
+ /* class_tid: 1, , table: profile_tcam.l3_l4.ip */
{
- .description = "l2_cntxt_id.en",
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.l3_l4.vxlan */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 & 0xff}
+ },
+ {
+ .description = "wc_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -35706,1131 +37012,1203 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
1}
},
{
- .description = "parif.en",
- .field_bit_size = 1,
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "spif.en",
- .field_bit_size = 1,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "svif.en",
+ .description = "em_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "lcos.en",
+ .description = "pl_byp_lkup_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 1, , table: profile_tcam_cache.wr */
{
- .description = "meta.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "rcyc_cnt.en",
- .field_bit_size = 1,
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
},
{
- .description = "loopback.en",
- .field_bit_size = 1,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_l2type.en",
- .field_bit_size = 1,
+ .description = "em_key_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_dmac.en",
- .field_bit_size = 1,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_smac.en",
- .field_bit_size = 1,
+ .description = "wc_key_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_dt.en",
- .field_bit_size = 1,
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
+ /* class_tid: 1, , table: wm.l3_l4.ipv4 */
{
- .description = "tl2_sa.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_nvt.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovp.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovd.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl2_ovv.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 1, , table: wm.l3_l4.ipv6 */
{
- .description = "tl2_ovt.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivp.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivd.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivv.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 1, , table: wm.l3.ipv4 */
{
- .description = "tl2_ivt.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_etype.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_l3type.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_sip.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 1, , table: wm.l3.ipv6 */
{
- .description = "tl3_sip_selcmp.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_dip.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_dip_selcmp.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ttl.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl3_prot.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 1, , table: wm.l2 */
{
- .description = "tl3_fid.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_qos.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_nonext.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_esp.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl3_ieh_auth.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv4 */
{
- .description = "tl3_ieh_dest.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_frag.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_rthdr.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_hop.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl3_ieh_1frag.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv6 */
{
- .description = "tl3_df.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_l3err.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_l4type.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_src.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl4_dst.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
{
- .description = "tl4_flags.en",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_seq.en",
- .field_bit_size = 1,
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_pa.en",
- .field_bit_size = 1,
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_opt.en",
- .field_bit_size = 1,
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_tcpts.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_err.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 2, , table: tunnel_cache.wr */
{
- .description = "tuntype.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "tflags.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tids.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
+ /* class_tid: 2, , table: l2_cntxt_tcam.0 */
{
- .description = "tid.en",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
},
{
- .description = "tctxts.en",
- .field_bit_size = 1,
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tctxt.en",
- .field_bit_size = 1,
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
{
- .description = "tqos.en",
- .field_bit_size = 1,
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
},
{
- .description = "terr.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .description = "l2_l2type.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
},
+ /* class_tid: 2, , table: mac_addr_cache.wr */
{
- .description = "l2_dmac.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_smac.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 2, , table: fkb_select.f2_l2_l3_l4_v6_em */
{
- .description = "l2_dt.en",
+ .description = "l2_cntxt_id.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "l2_sa.en",
+ .description = "parif.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_nvt.en",
+ .description = "spif.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovp.en",
+ .description = "svif.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovd.en",
+ .description = "lcos.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovv.en",
+ .description = "meta.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovt.en",
+ .description = "rcyc_cnt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivp.en",
+ .description = "loopback.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivd.en",
+ .description = "tl2_l2type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivv.en",
+ .description = "tl2_dmac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivt.en",
+ .description = "tl2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_etype.en",
+ .description = "tl2_dt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_l3type.en",
+ .description = "tl2_sa.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_sip.en",
+ .description = "tl2_nvt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_sip_selcmp.en",
+ .description = "tl2_ovp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip.en",
+ .description = "tl2_ovd.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip_selcmp.en",
+ .description = "tl2_ovv.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ttl.en",
+ .description = "tl2_ovt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_prot.en",
+ .description = "tl2_ivp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_fid.en",
+ .description = "tl2_ivd.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_qos.en",
+ .description = "tl2_ivv.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_nonext.en",
+ .description = "tl2_ivt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_esp.en",
+ .description = "tl2_etype.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_auth.en",
+ .description = "tl3_l3type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_dest.en",
+ .description = "tl3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_frag.en",
+ .description = "tl3_sip_selcmp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_rthdr.en",
+ .description = "tl3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_hop.en",
+ .description = "tl3_dip_selcmp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_1frag.en",
+ .description = "tl3_ttl.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_df.en",
+ .description = "tl3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_l3err.en",
+ .description = "tl3_fid.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_l4type.en",
+ .description = "tl3_qos.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_src.en",
+ .description = "tl3_ieh_nonext.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_dst.en",
+ .description = "tl3_ieh_esp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_flags.en",
+ .description = "tl3_ieh_auth.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_seq.en",
+ .description = "tl3_ieh_dest.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_ack.en",
+ .description = "tl3_ieh_frag.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_win.en",
+ .description = "tl3_ieh_rthdr.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_pa.en",
+ .description = "tl3_ieh_hop.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_opt.en",
+ .description = "tl3_ieh_1frag.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_tcpts.en",
+ .description = "tl3_df.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_tsval.en",
+ .description = "tl3_l3err.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_txecr.en",
+ .description = "tl4_l4type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_err.en",
+ .description = "tl4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam.l3_l4.ip */
{
- .description = "wc_key_id",
- .field_bit_size = 6,
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_search_en",
+ .description = "tl4_seq.en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_type",
- .field_bit_size = 2,
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 6,
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_search_en",
+ .description = "tl4_err.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "pl_byp_lkup_en",
+ .description = "tuntype.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam.l3_l4.vxlan */
{
- .description = "wc_key_id",
- .field_bit_size = 6,
+ .description = "tflags.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 & 0xff}
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}
},
{
- .description = "wc_search_en",
+ .description = "tid.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_type",
- .field_bit_size = 2,
+ .description = "tctxts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 6,
+ .description = "tctxt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "tqos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_search_en",
+ .description = "terr.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "pl_byp_lkup_en",
+ .description = "l2_l2type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam_cache.wr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ 1}
},
{
- .description = "profile_tcam_index",
- .field_bit_size = 10,
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 8,
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_key_id",
- .field_bit_size = 8,
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "flow_sig_id",
- .field_bit_size = 64,
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l3_l4.ipv4 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l3_l4.ipv6 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}
},
- /* class_tid: 1, , table: wm.l3.ipv4 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff}
+ },
+ {
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l3.ipv6 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l2 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l3_df.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ (BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff}
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff}
},
- /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv4 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l4_win.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv6 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l4_err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: l2_cntxt_tcam.1 */
+ /* class_tid: 2, , table: profile_tcam.f2_l2_l3_l4_v6_em */
{
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "wc_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "wc_search_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "em_key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "em_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: tunnel_cache.wr */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_l2_l3_l4_v6_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -36841,99 +38219,94 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "l2_cntxt_tcam_index",
+ .description = "profile_tcam_index",
.field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
},
- /* class_tid: 2, , table: l2_cntxt_tcam.0 */
{
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "em_key_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "wc_key_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
+ /* class_tid: 2, , table: em.f2_l2_l3_l4_v6.0 */
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ 1}
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ 3}
},
- /* class_tid: 2, , table: mac_addr_cache.wr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "l2_cntxt_tcam_index",
- .field_bit_size = 10,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -37100,9 +38473,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "tl3_dip_selcmp.en",
@@ -37316,7 +38687,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l2_dt.en",
@@ -37400,7 +38773,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l3_sip_selcmp.en",
@@ -37432,7 +38807,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l3_fid.en",
@@ -37516,13 +38893,17 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l4_flags.en",
@@ -37743,127 +39124,6 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 2, , table: wm.l3_l4.ipv6 */
- {
- .description = "ctxt_data",
- .field_bit_size = 14,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "meta_prof",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "opcode",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "data",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
- },
- {
- .description = "strength",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- /* class_tid: 3, , table: l2_cntxt_tcam.0 */
- {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}
- },
- {
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "def_ctxt_data",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
- },
- {
- .description = "ctxt_opcode",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
- },
- {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
- },
- {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
- },
- /* class_tid: 3, , table: mac_addr_cache.wr */
- {
- .description = "rid",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
- },
- {
- .description = "l2_cntxt_tcam_index",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
- },
- {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
- },
- {
- .description = "src_property_ptr",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
/* class_tid: 3, , table: fkb_select.l2_l3_l4_v6_em */
{
.description = "l2_cntxt_id.en",
@@ -38240,7 +39500,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
},
{
.description = "l2_dt.en",
@@ -38374,7 +39637,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}
},
{
.description = "l3_fid.en",
@@ -39066,7 +40332,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l2_dt.en",
@@ -39186,7 +40454,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l3_fid.en",
@@ -39663,7 +40933,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -39910,7 +41182,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -40050,7 +41324,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "parif",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
},
{
.description = "reserved",
@@ -40238,7 +41515,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -40299,6 +41578,43 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
+ /* class_tid: 5, , table: port_table.egr_wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drv_func.mac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drv_func.parent.mac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff}
+ },
+ {
+ .description = "phy_port",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "default_arec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
+ },
/* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
{
.description = "prof_func_id",
@@ -40450,7 +41766,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -40610,7 +41928,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "parif",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
},
{
.description = "reserved",
@@ -40970,7 +42291,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -41772,6 +43095,34 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_wr_vfr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
/* class_tid: 5, , table: int_full_act_record.vfr_ing0 */
{
.description = "sp_rec_ptr",
@@ -41819,7 +43170,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -42058,7 +43411,13 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 42
},
- /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_ipv6_rd */
+ {
+ .description = "em_key_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_KEY_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 50
+ },
{
.description = "em_profile_id",
.regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
@@ -42077,47 +43436,40 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 32
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ /* class_tid: 2, , table: profile_tcam.f2_l2_l3_l4_v6_em */
{
- .description = "l2_cntxt_id",
- .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
- .ident_bit_size = 10,
- .ident_bit_pos = 42
+ .description = "em_profile_id",
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_EM_PROF,
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 23
},
- /* class_tid: 3, , table: mac_addr_cache.rd */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
{
- .description = "l2_cntxt_id",
- .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
- .ident_bit_size = 10,
+ .description = "em_profile_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
.ident_bit_pos = 42
},
- /* class_tid: 3, , table: port_table.egr.rd */
- {
- .description = "default_arec_ptr",
- .regfile_idx = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
- .ident_bit_size = 16,
- .ident_bit_pos = 136
- },
{
- .description = "drv_func.parent.mac",
- .regfile_idx = BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC,
- .ident_bit_size = 48,
- .ident_bit_pos = 80
+ .description = "flow_sig_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .ident_bit_size = 64,
+ .ident_bit_pos = 74
},
{
- .description = "phy_port",
- .regfile_idx = BNXT_ULP_RF_IDX_PHY_PORT,
- .ident_bit_size = 8,
- .ident_bit_pos = 128
+ .description = "profile_tcam_index",
+ .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
},
- /* class_tid: 3, , table: l2_cntxt_tcam.0 */
+ /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
{
.description = "l2_cntxt_id",
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
- .ident_bit_pos = 29
+ .ident_bit_pos = 42
},
/* class_tid: 3, , table: profile_tcam_cache.ipv6_rd */
{
@@ -42168,36 +43520,29 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
},
/* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
- .description = "l2_cntxt_id",
+ .description = "l2_cntxt_id_low",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 29
},
/* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
- .description = "l2_cntxt_id",
+ .description = "l2_cntxt_id_low",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 29
},
/* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
{
- .description = "l2_cntxt_id",
+ .description = "l2_cntxt_id_low",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 29
- },
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_wr_vfr */
- {
- .description = "rid",
- .regfile_idx = BNXT_ULP_RF_IDX_RID,
- .ident_bit_size = 32,
- .ident_bit_pos = 0
}
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
index 2870a0615a..4b9cb7fd5b 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Wed Jun 30 14:36:16 2021 */
+/* date: Wed Aug 11 16:00:16 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -16741,27 +16741,27 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
},
/* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
- .description = "l2_cntxt_id",
+ .description = "l2_cntxt_id_low",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 0
},
/* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
- .description = "l2_cntxt_id",
+ .description = "l2_cntxt_id_low",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 0
},
/* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
{
- .description = "l2_cntxt_id",
+ .description = "l2_cntxt_id_low",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 0
diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
index c6b2b1675d..7b6db7a0f8 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
@@ -75,9 +75,9 @@ ulp_mapper_generic_tbl_list_init(struct bnxt_ulp_mapper_data *mapper_data)
entry->container.byte_data = &entry->mem_data[size];
entry->container.byte_order = tbl->result_byte_order;
} else {
- BNXT_TF_DBG(ERR, "%s:Invalid gen table num of ent %d\n",
+ BNXT_TF_DBG(DEBUG, "%s: Unused Gen tbl entry is %d\n",
tbl->name, idx);
- return -EINVAL;
+ /* return -EINVAL; */
}
if (tbl->hash_tbl_entries) {
cparams.key_size = tbl->key_num_bytes;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 234f7ea2fa..059ee99837 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -438,6 +438,77 @@ ulp_mapper_ident_fields_get(struct bnxt_ulp_mapper_parms *mparms,
return &dev_tbls->ident_list[idx];
}
+static enum tf_tbl_type
+ulp_mapper_dyn_tbl_type_get(struct bnxt_ulp_mapper_parms *mparms,
+ struct bnxt_ulp_mapper_tbl_info *tbl,
+ struct ulp_blob *bdata,
+ uint16_t *out_len)
+{
+ struct bnxt_ulp_device_params *d_params = mparms->device_params;
+ uint16_t blob_len = ulp_blob_data_len_get(bdata);
+ struct bnxt_ulp_dyn_size_map *size_map;
+ uint32_t i;
+
+ if (d_params->dynamic_sram_en) {
+ switch (tbl->resource_type) {
+ case TF_TBL_TYPE_ACT_ENCAP_8B:
+ case TF_TBL_TYPE_ACT_ENCAP_16B:
+ case TF_TBL_TYPE_ACT_ENCAP_32B:
+ case TF_TBL_TYPE_ACT_ENCAP_64B:
+ size_map = d_params->dyn_encap_sizes;
+ for (i = 0; i < d_params->dyn_encap_list_size; i++) {
+ if (blob_len <= size_map[i].slab_size) {
+ *out_len = size_map[i].slab_size;
+ return size_map[i].tbl_type;
+ }
+ }
+ break;
+ case TF_TBL_TYPE_ACT_MODIFY_8B:
+ case TF_TBL_TYPE_ACT_MODIFY_16B:
+ case TF_TBL_TYPE_ACT_MODIFY_32B:
+ case TF_TBL_TYPE_ACT_MODIFY_64B:
+ size_map = d_params->dyn_modify_sizes;
+ for (i = 0; i < d_params->dyn_modify_list_size; i++) {
+ if (blob_len <= size_map[i].slab_size) {
+ *out_len = size_map[i].slab_size;
+ return size_map[i].tbl_type;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ }
+ return tbl->resource_type;
+}
+
+static uint16_t
+ulp_mapper_dyn_blob_size_get(struct bnxt_ulp_mapper_parms *mparms,
+ struct bnxt_ulp_mapper_tbl_info *tbl)
+{
+ struct bnxt_ulp_device_params *d_params = mparms->device_params;
+
+ if (d_params->dynamic_sram_en) {
+ switch (tbl->resource_type) {
+ case TF_TBL_TYPE_ACT_ENCAP_8B:
+ case TF_TBL_TYPE_ACT_ENCAP_16B:
+ case TF_TBL_TYPE_ACT_ENCAP_32B:
+ case TF_TBL_TYPE_ACT_ENCAP_64B:
+ case TF_TBL_TYPE_ACT_MODIFY_8B:
+ case TF_TBL_TYPE_ACT_MODIFY_16B:
+ case TF_TBL_TYPE_ACT_MODIFY_32B:
+ case TF_TBL_TYPE_ACT_MODIFY_64B:
+ /* return max size */
+ return BNXT_ULP_FLMP_BLOB_SIZE_IN_BITS;
+ default:
+ break;
+ }
+ } else if (tbl->encap_num_fields) {
+ return BNXT_ULP_FLMP_BLOB_SIZE_IN_BITS;
+ }
+ return tbl->result_bit_size;
+}
+
static inline int32_t
ulp_mapper_tcam_entry_free(struct bnxt_ulp_context *ulp,
struct tf *tfp,
@@ -1562,7 +1633,8 @@ ulp_mapper_tbl_result_build(struct bnxt_ulp_mapper_parms *parms,
if (encap_flds) {
uint32_t pad = 0;
/* Initialize the encap blob */
- if (!tbl->record_size) {
+ if (!tbl->record_size &&
+ !parms->device_params->dynamic_sram_en) {
BNXT_TF_DBG(ERR, "Encap tbl record size incorrect\n");
return -EINVAL;
}
@@ -1583,9 +1655,21 @@ ulp_mapper_tbl_result_build(struct bnxt_ulp_mapper_parms *parms,
}
}
/* add the dynamic pad push */
- pad = ULP_BYTE_2_BITS(tbl->record_size) -
- ulp_blob_data_len_get(&encap_blob);
- ulp_blob_pad_push(&encap_blob, pad);
+ if (parms->device_params->dynamic_sram_en) {
+ uint16_t rec_s = ULP_BYTE_2_BITS(tbl->record_size);
+
+ (void)ulp_mapper_dyn_tbl_type_get(parms, tbl,
+ &encap_blob, &rec_s);
+ pad = rec_s - ulp_blob_data_len_get(&encap_blob);
+ } else {
+ pad = ULP_BYTE_2_BITS(tbl->record_size) -
+ ulp_blob_data_len_get(&encap_blob);
+ }
+ if (ulp_blob_pad_push(&encap_blob, pad) < 0) {
+ BNXT_TF_DBG(ERR, "encap buffer padding failed\n");
+ return -EINVAL;
+ }
+
/* perform the 64 bit byte swap */
ulp_blob_perform_64B_byte_swap(&encap_blob);
@@ -2411,13 +2495,11 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
bool global = false;
uint64_t act_rec_size;
bool shared = false;
+ enum tf_tbl_type tbl_type = tbl->resource_type;
tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session);
- /* use the max size if encap is enabled */
- if (tbl->encap_num_fields)
- bit_size = BNXT_ULP_FLMP_BLOB_SIZE_IN_BITS;
- else
- bit_size = tbl->result_bit_size;
+ /* compute the blob size */
+ bit_size = ulp_mapper_dyn_blob_size_get(parms, tbl);
/* Initialize the blob data */
if (!ulp_blob_init(&data, bit_size,
@@ -2526,7 +2608,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
gparms.dir = tbl->direction;
gparms.type = tbl->resource_type;
gparms.data = ulp_blob_data_get(&data, &tmplen);
- gparms.data_sz_in_bytes = ULP_BITS_2_BYTE(tbl->result_bit_size);
+ gparms.data_sz_in_bytes = ULP_BITS_2_BYTE(tmplen);
gparms.idx = index;
rc = tf_get_tbl_entry(tfp, &gparms);
if (rc) {
@@ -2568,14 +2650,16 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
if (alloc) {
aparms.dir = tbl->direction;
- aparms.type = tbl->resource_type;
+ tbl_type = ulp_mapper_dyn_tbl_type_get(parms, tbl,
+ &data, &tmplen);
+ aparms.type = tbl_type;
aparms.tbl_scope_id = tbl_scope_id;
/* All failures after the alloc succeeds require a free */
rc = tf_alloc_tbl_entry(tfp, &aparms);
if (rc) {
BNXT_TF_DBG(ERR, "Alloc table[%s][%s] failed rc=%d\n",
- tf_tbl_type_2_str(tbl->resource_type),
+ tf_tbl_type_2_str(aparms.type),
tf_dir_2_str(tbl->direction), rc);
return rc;
}
@@ -2619,8 +2703,10 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
if (write) {
sparms.dir = tbl->direction;
- sparms.type = tbl->resource_type;
sparms.data = ulp_blob_data_get(&data, &tmplen);
+ tbl_type = ulp_mapper_dyn_tbl_type_get(parms, tbl, &data,
+ &tmplen);
+ sparms.type = tbl_type;
sparms.data_sz_in_bytes = ULP_BITS_2_BYTE(tmplen);
sparms.idx = index;
sparms.tbl_scope_id = tbl_scope_id;
@@ -2655,7 +2741,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
memset(&fid_parms, 0, sizeof(fid_parms));
fid_parms.direction = tbl->direction;
fid_parms.resource_func = tbl->resource_func;
- fid_parms.resource_type = tbl->resource_type;
+ fid_parms.resource_type = tbl_type;
fid_parms.resource_sub_type = tbl->resource_sub_type;
fid_parms.resource_hndl = index;
fid_parms.critical_resource = tbl->critical_resource;
@@ -2684,7 +2770,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
* write to the entry or link the flow
*/
free_parms.dir = tbl->direction;
- free_parms.type = tbl->resource_type;
+ free_parms.type = tbl_type;
free_parms.idx = index;
free_parms.tbl_scope_id = tbl_scope_id;
@@ -2862,8 +2948,7 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms,
cache_key = ulp_blob_data_get(&key, &tmplen);
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
- BNXT_TF_DBG(DEBUG, "The gen_tbl[%u] key\n", tbl_idx);
- ulp_mapper_blob_dump(&key);
+ ulp_mapper_gen_tbl_dump(tbl->resource_sub_type, tbl->direction, &key);
#endif
#endif
/* get the generic table */
@@ -3310,18 +3395,10 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms,
*res = regval == 0;
break;
case BNXT_ULP_COND_OPC_FLOW_PAT_MATCH:
- if (parms->flow_pattern_id == operand) {
- BNXT_TF_DBG(ERR, "field pattern match failed %x\n",
- parms->flow_pattern_id);
- return -EINVAL;
- }
+ *res = parms->flow_pattern_id == operand;
break;
case BNXT_ULP_COND_OPC_ACT_PAT_MATCH:
- if (parms->act_pattern_id == operand) {
- BNXT_TF_DBG(ERR, "act pattern match failed %x\n",
- parms->act_pattern_id);
- return -EINVAL;
- }
+ *res = parms->act_pattern_id == operand;
break;
case BNXT_ULP_COND_OPC_EXT_MEM_IS_SET:
if (bnxt_ulp_cntxt_mem_type_get(parms->ulp_ctx, &mtype)) {
@@ -3507,7 +3584,6 @@ ulp_mapper_func_info_process(struct bnxt_ulp_mapper_parms *parms,
return rc;
}
-
/*
* Processes a list of conditions and returns both a status and result of the
* list. The status must be checked prior to verifying the result.
@@ -3863,8 +3939,7 @@ ulp_mapper_resources_free(struct bnxt_ulp_context *ulp_ctx,
* Set the critical resource on the first resource del, then iterate
* while status is good
*/
- if (flow_type != BNXT_ULP_FDB_TYPE_RID)
- res_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES;
+ res_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES;
rc = ulp_flow_db_resource_del(ulp_ctx, flow_type, fid, &res_parms);
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index dce95de05c..3a9c9bba27 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -1226,20 +1226,66 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
/* Function to handle the update of proto header based on field values */
static void
-ulp_rte_l4_proto_type_update(struct ulp_rte_parser_params *param,
- uint16_t dst_port)
-{
- if (dst_port == tfp_cpu_to_be_16(ULP_UDP_PORT_VXLAN)) {
- ULP_BITMAP_SET(param->hdr_fp_bit.bits,
- BNXT_ULP_HDR_BIT_T_VXLAN);
- ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_L3_TUN, 1);
+ulp_rte_l4_proto_type_update(struct ulp_rte_parser_params *params,
+ uint16_t src_port, uint16_t src_mask,
+ uint16_t dst_port, uint16_t dst_mask,
+ enum bnxt_ulp_hdr_bit hdr_bit)
+{
+ switch (hdr_bit) {
+ case BNXT_ULP_HDR_BIT_I_UDP:
+ case BNXT_ULP_HDR_BIT_I_TCP:
+ ULP_BITMAP_SET(params->hdr_bitmap.bits, hdr_bit);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4, 1);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_SRC_PORT,
+ (uint64_t)rte_be_to_cpu_16(src_port));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_DST_PORT,
+ (uint64_t)rte_be_to_cpu_16(dst_port));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK,
+ (uint64_t)rte_be_to_cpu_16(src_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK,
+ (uint64_t)rte_be_to_cpu_16(dst_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID,
+ 1);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT,
+ !!(src_port & src_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT,
+ !!(dst_port & dst_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_PROTO_ID,
+ (hdr_bit == BNXT_ULP_HDR_BIT_I_UDP) ?
+ IPPROTO_UDP : IPPROTO_TCP);
+ break;
+ case BNXT_ULP_HDR_BIT_O_UDP:
+ case BNXT_ULP_HDR_BIT_O_TCP:
+ ULP_BITMAP_SET(params->hdr_bitmap.bits, hdr_bit);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4, 1);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_SRC_PORT,
+ (uint64_t)rte_be_to_cpu_16(src_port));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DST_PORT,
+ (uint64_t)rte_be_to_cpu_16(dst_port));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK,
+ (uint64_t)rte_be_to_cpu_16(src_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK,
+ (uint64_t)rte_be_to_cpu_16(dst_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID,
+ 1);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT,
+ !!(src_port & src_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT,
+ !!(dst_port & dst_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_PROTO_ID,
+ (hdr_bit == BNXT_ULP_HDR_BIT_O_UDP) ?
+ IPPROTO_UDP : IPPROTO_TCP);
+ break;
+ default:
+ break;
}
- if (ULP_BITMAP_ISSET(param->hdr_bitmap.bits,
- BNXT_ULP_HDR_BIT_T_VXLAN) ||
- ULP_BITMAP_ISSET(param->hdr_bitmap.bits,
- BNXT_ULP_HDR_BIT_T_GRE))
- ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_L3_TUN, 1);
+ if (hdr_bit == BNXT_ULP_HDR_BIT_O_UDP && dst_port ==
+ tfp_cpu_to_be_16(ULP_UDP_PORT_VXLAN)) {
+ ULP_BITMAP_SET(params->hdr_fp_bit.bits,
+ BNXT_ULP_HDR_BIT_T_VXLAN);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN, 1);
+ }
}
/* Function to handle the parsing of RTE Flow item UDP Header. */
@@ -1253,7 +1299,9 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item,
uint32_t idx = 0;
uint32_t size;
uint16_t dport = 0, sport = 0;
+ uint16_t dport_mask = 0, sport_mask = 0;
uint32_t cnt;
+ enum bnxt_ulp_hdr_bit out_l4 = BNXT_ULP_HDR_BIT_O_UDP;
cnt = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L4_HDR_CNT);
if (cnt == 2) {
@@ -1265,6 +1313,10 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item,
sport = udp_spec->hdr.src_port;
dport = udp_spec->hdr.dst_port;
}
+ if (udp_mask) {
+ sport_mask = udp_mask->hdr.src_port;
+ dport_mask = udp_mask->hdr.dst_port;
+ }
if (ulp_rte_prsr_fld_size_validate(params, &idx,
BNXT_ULP_PROTO_HDR_UDP_NUM)) {
@@ -1302,48 +1354,11 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item,
/* Set the udp header bitmap and computed l4 header bitmaps */
if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP) ||
- ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP)) {
- ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_UDP);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4, 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_SRC_PORT,
- (uint32_t)rte_be_to_cpu_16(sport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_DST_PORT,
- (uint32_t)rte_be_to_cpu_16(dport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID,
- 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_PROTO_ID,
- IPPROTO_UDP);
- if (udp_mask && udp_mask->hdr.src_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT,
- 1);
- if (udp_mask && udp_mask->hdr.dst_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT,
- 1);
- } else {
- ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4, 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_SRC_PORT,
- (uint32_t)rte_be_to_cpu_16(sport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DST_PORT,
- (uint32_t)rte_be_to_cpu_16(dport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID,
- 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_PROTO_ID,
- IPPROTO_UDP);
- if (udp_mask && udp_mask->hdr.src_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT,
- 1);
- if (udp_mask && udp_mask->hdr.dst_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT,
- 1);
+ ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP))
+ out_l4 = BNXT_ULP_HDR_BIT_I_UDP;
- /* Update the field protocol hdr bitmap */
- ulp_rte_l4_proto_type_update(params, dport);
- }
+ ulp_rte_l4_proto_type_update(params, sport, sport_mask, dport,
+ dport_mask, out_l4);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L4_HDR_CNT, ++cnt);
return BNXT_TF_RC_SUCCESS;
}
@@ -1358,8 +1373,10 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item,
struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap;
uint32_t idx = 0;
uint16_t dport = 0, sport = 0;
+ uint16_t dport_mask = 0, sport_mask = 0;
uint32_t size;
uint32_t cnt;
+ enum bnxt_ulp_hdr_bit out_l4 = BNXT_ULP_HDR_BIT_O_TCP;
cnt = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L4_HDR_CNT);
if (cnt == 2) {
@@ -1371,6 +1388,10 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item,
sport = tcp_spec->hdr.src_port;
dport = tcp_spec->hdr.dst_port;
}
+ if (tcp_mask) {
+ sport_mask = tcp_mask->hdr.src_port;
+ dport_mask = tcp_mask->hdr.dst_port;
+ }
if (ulp_rte_prsr_fld_size_validate(params, &idx,
BNXT_ULP_PROTO_HDR_TCP_NUM)) {
@@ -1438,45 +1459,11 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item,
/* Set the udp header bitmap and computed l4 header bitmaps */
if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP) ||
- ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP)) {
- ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_TCP);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4, 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_SRC_PORT,
- (uint32_t)rte_be_to_cpu_16(sport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_DST_PORT,
- (uint32_t)rte_be_to_cpu_16(dport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID,
- 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_PROTO_ID,
- IPPROTO_TCP);
- if (tcp_mask && tcp_mask->hdr.src_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT,
- 1);
- if (tcp_mask && tcp_mask->hdr.dst_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT,
- 1);
- } else {
- ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4, 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_SRC_PORT,
- (uint32_t)rte_be_to_cpu_16(sport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DST_PORT,
- (uint32_t)rte_be_to_cpu_16(dport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID,
- 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_PROTO_ID,
- IPPROTO_TCP);
- if (tcp_mask && tcp_mask->hdr.src_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT,
- 1);
- if (tcp_mask && tcp_mask->hdr.dst_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT,
- 1);
- }
+ ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP))
+ out_l4 = BNXT_ULP_HDR_BIT_I_TCP;
+
+ ulp_rte_l4_proto_type_update(params, sport, sport_mask, dport,
+ dport_mask, out_l4);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L4_HDR_CNT, ++cnt);
return BNXT_TF_RC_SUCCESS;
}
@@ -1528,7 +1515,7 @@ ulp_rte_vxlan_hdr_handler(const struct rte_flow_item *item,
/* Update the hdr_bitmap with vxlan */
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_T_VXLAN);
- ulp_rte_l4_proto_type_update(params, 0);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN, 1);
return BNXT_TF_RC_SUCCESS;
}
@@ -1563,7 +1550,7 @@ ulp_rte_gre_hdr_handler(const struct rte_flow_item *item,
/* Update the hdr_bitmap with GRE */
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_T_GRE);
- ulp_rte_l4_proto_type_update(params, 0);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN, 1);
return BNXT_TF_RC_SUCCESS;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index 1683cd7ec4..d3bfb8c12d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -206,6 +206,11 @@ struct bnxt_ulp_template_device_tbls {
uint32_t cond_list_size;
};
+struct bnxt_ulp_dyn_size_map {
+ uint32_t slab_size;
+ enum tf_tbl_type tbl_type;
+};
+
/* Device specific parameters */
struct bnxt_ulp_device_params {
uint8_t description[16];
@@ -229,6 +234,11 @@ struct bnxt_ulp_device_params {
uint32_t byte_count_shift;
uint32_t packet_count_shift;
uint32_t dynamic_pad_en;
+ uint32_t dynamic_sram_en;
+ uint32_t dyn_encap_list_size;
+ struct bnxt_ulp_dyn_size_map dyn_encap_sizes[4];
+ uint32_t dyn_modify_list_size;
+ struct bnxt_ulp_dyn_size_map dyn_modify_sizes[4];
uint16_t em_blk_size_bits;
uint16_t em_blk_align_bits;
uint16_t em_key_align_bytes;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c
index 686b80e456..df3afaa6fd 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c
@@ -882,7 +882,8 @@ ulp_blob_msb_block_merge(struct ulp_blob *dst, struct ulp_blob *src,
for (i = 0; i < num;) {
if (((dst->write_idx % block_size) + (num - i)) > block_size)
- write_bytes = block_size - dst->write_idx;
+ write_bytes = block_size -
+ (dst->write_idx % block_size);
else
write_bytes = num - i;
for (k = 0; k < ULP_BITS_2_BYTE_NR(write_bytes); k++) {
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* Re: [dpdk-dev] [PATCH v3 13/13] net/bnxt: add enhancements to TF ULP
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 13/13] net/bnxt: add enhancements to TF ULP Venkat Duvvuru
@ 2021-09-16 14:06 ` Ferruh Yigit
0 siblings, 0 replies; 83+ messages in thread
From: Ferruh Yigit @ 2021-09-16 14:06 UTC (permalink / raw)
To: Ajit Khaparde, Thomas Monjalon, David Marchand
Cc: Kishore Padmanabha, Mike Baucom, Venkat Duvvuru, dev, Qi Zhang,
Raslan Darawsheh, Maxime Coquelin, jerinj, Chenbo Xia
On 9/11/2021 4:30 PM, Venkat Duvvuru wrote:
> From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
>
> 1. Added support to specify l4 port masks in the template. Also enabled
> source mac in the wild card key for ingress flows.
>
> 2. Added support to enable offload for ipv6 traffic within the vxlan
> tunnel connection.
>
> 3. The flow counters is reduced from 7168 to 6912 for Whitney.
> The stats operation is updated to reflect counts for packets
> at egress from CFA instead of ingress to CFA
>
> 4. The miss path for the l2 context table is updated with correct
> parif and default action handler to handle the miss path for
> egress flows.
>
> 5. This support enables allocation of encapsulation, modification and
> action records dynamically based on a given flow actions.
>
> 6. Reduce the l2context resource requests during open_session. Move the
> SMAC from the L2Context to the EM/WM
>
> 7. Remap the parif in the bd action in order to eliminate incorrect
> replication of broadcast packets. The layer 4 source port mask
> was incorrectly updated in the outer layer 4 source port mask
> instead of inner layer 4. Add the l3 proto to egress rules, switch
> to using computed fields for l4 ports, add internal smac to f1/f2
> flows, add l3 proto to ingress ipv6 flows
>
> Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
> Signed-off-by: Mike Baucom <michael.baucom@broadcom.com>
> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
> ---
> drivers/net/bnxt/tf_core/tf_tbl_sram.c | 7 -
> .../generic_templates/ulp_template_db_class.c | 8102 ++++++++++++-----
> .../generic_templates/ulp_template_db_enum.h | 675 +-
> .../generic_templates/ulp_template_db_field.h | 195 +-
> .../generic_templates/ulp_template_db_tbl.c | 2136 ++++-
> .../ulp_template_db_thor_act.c | 996 +-
> .../ulp_template_db_thor_class.c | 7495 ++++++++-------
> .../ulp_template_db_wh_plus_class.c | 14 +-
> drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c | 4 +-
> drivers/net/bnxt/tf_ulp/ulp_mapper.c | 135 +-
> drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 175 +-
> drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 10 +
> drivers/net/bnxt/tf_ulp/ulp_utils.c | 3 +-
> 13 files changed, 13538 insertions(+), 6409 deletions(-)
Hi Ajit,
I can see release notes ('release_21_11.rst') updated in the commit in net-brcm
tree [1], but that change doesn't exist in the original patchset.
I think it is crucial to be in sync on this, that content of the patches
shouldn't be changed in our sub-trees. cc'ed other subtree maintainers too, to
be sure we are all in same page.
Time to time we are doing simple changes/fixes in the repos, to help to the
developer, but changes shouldn't go beyond it, and I believe even those changes
should be communicated in the mail list for the record.
If the content of the patches needs to be changed, I think that should be done
by sending a new version of the set. I am aware it is additional overhead, but
still doing otherwise can cause more trouble in long term.
Thanks,
ferruh
[1]
https://git.dpdk.org/next/dpdk-next-net-brcm/commit/?id=840e8bd01b6493940ac6130e1280713ec708d000
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [dpdk-dev] [PATCH v3 00/13] enhancements to host based flow table management
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 00/13] enhancements to host based flow table management Venkat Duvvuru
` (12 preceding siblings ...)
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 13/13] net/bnxt: add enhancements to TF ULP Venkat Duvvuru
@ 2021-09-16 3:25 ` Ajit Khaparde
2021-09-16 13:26 ` Ferruh Yigit
14 siblings, 0 replies; 83+ messages in thread
From: Ajit Khaparde @ 2021-09-16 3:25 UTC (permalink / raw)
To: Venkat Duvvuru, Ferruh Yigit; +Cc: dpdk-dev
[-- Attachment #1: Type: text/plain, Size: 5248 bytes --]
On Sat, Sep 11, 2021 at 8:30 AM Venkat Duvvuru
<venkatkumar.duvvuru@broadcom.com> wrote:
>
> This patch set adds support for new offload features/enhancments for
> Thor adapters like VF representor support, new flow matches/actions
> & dynamic SRAM manager support.
>
> v2 ==> v3
> =========
> * Fixed compilation issue.
Patchset applied to dpdk-next-net-brcm. Thanks
>
> Farah Smith (4):
> net/bnxt: tf core index table updates
> net/bnxt: add Thor SRAM mgr model
> net/bnxt: tf core SRAM Manager
> net/bnxt: sram manager shared session
>
> Jay Ding (1):
> net/bnxt: add flow meter drop counter support
>
> Kishore Padmanabha (6):
> net/bnxt: add flow templates support for Thor
> net/bnxt: add support for tunnel offloads
> net/bnxt: add support for dynamic encap action
> net/bnxt: add wild card TCAM byte order for Thor
> net/bnxt: add flow templates for Thor
> net/bnxt: add enhancements to TF ULP
>
> Peter Spreadborough (1):
> net/bnxt: enable dpool allocator
>
> Randy Schacher (1):
> net/bnxt: dynamically allocate space for EM defrag function
>
> drivers/net/bnxt/tf_core/cfa_resource_types.h | 5 +-
> drivers/net/bnxt/tf_core/dpool.c | 38 +-
> drivers/net/bnxt/tf_core/ll.c | 3 +
> drivers/net/bnxt/tf_core/ll.h | 50 +-
> drivers/net/bnxt/tf_core/meson.build | 2 +
> drivers/net/bnxt/tf_core/tf_core.c | 169 +-
> drivers/net/bnxt/tf_core/tf_core.h | 159 +-
> drivers/net/bnxt/tf_core/tf_device.c | 40 +-
> drivers/net/bnxt/tf_core/tf_device.h | 137 +-
> drivers/net/bnxt/tf_core/tf_device_p4.c | 77 +-
> drivers/net/bnxt/tf_core/tf_device_p4.h | 50 +-
> drivers/net/bnxt/tf_core/tf_device_p58.c | 112 +-
> drivers/net/bnxt/tf_core/tf_device_p58.h | 70 +-
> drivers/net/bnxt/tf_core/tf_em.h | 10 -
> drivers/net/bnxt/tf_core/tf_em_common.c | 4 +
> .../net/bnxt/tf_core/tf_em_hash_internal.c | 34 -
> drivers/net/bnxt/tf_core/tf_em_internal.c | 185 +-
> drivers/net/bnxt/tf_core/tf_msg.c | 2 +-
> drivers/net/bnxt/tf_core/tf_rm.c | 180 +-
> drivers/net/bnxt/tf_core/tf_rm.h | 62 +-
> drivers/net/bnxt/tf_core/tf_session.c | 56 +
> drivers/net/bnxt/tf_core/tf_session.h | 58 +-
> drivers/net/bnxt/tf_core/tf_sram_mgr.c | 971 +
> drivers/net/bnxt/tf_core/tf_sram_mgr.h | 317 +
> drivers/net/bnxt/tf_core/tf_tbl.c | 259 +-
> drivers/net/bnxt/tf_core/tf_tbl.h | 87 +-
> drivers/net/bnxt/tf_core/tf_tbl_sram.c | 747 +
> drivers/net/bnxt/tf_core/tf_tbl_sram.h | 154 +
> drivers/net/bnxt/tf_core/tf_tcam.c | 16 +-
> drivers/net/bnxt/tf_core/tf_tcam.h | 7 +
> drivers/net/bnxt/tf_core/tf_tcam_shared.c | 28 +-
> drivers/net/bnxt/tf_core/tf_util.c | 12 +
> drivers/net/bnxt/tf_ulp/bnxt_tf_common.h | 10 +-
> drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 52 +-
> drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 20 +-
> drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 226 +-
> .../bnxt/tf_ulp/generic_templates/meson.build | 17 +-
> .../generic_templates/ulp_template_db_act.c | 2 +-
> .../generic_templates/ulp_template_db_class.c | 12109 +++-
> .../generic_templates/ulp_template_db_enum.h | 618 +-
> .../generic_templates/ulp_template_db_field.h | 767 +-
> .../generic_templates/ulp_template_db_tbl.c | 2757 +-
> .../ulp_template_db_thor_act.c | 5079 +-
> .../ulp_template_db_thor_class.c | 45573 ++++++++++++++--
> .../ulp_template_db_wh_plus_act.c | 1700 +-
> .../ulp_template_db_wh_plus_class.c | 8329 ++-
> drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 48 +-
> drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h | 8 +-
> drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 678 +-
> drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 68 +-
> drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c | 9 +-
> drivers/net/bnxt/tf_ulp/ulp_mapper.c | 448 +-
> drivers/net/bnxt/tf_ulp/ulp_mapper.h | 10 +-
> drivers/net/bnxt/tf_ulp/ulp_matcher.c | 13 +
> drivers/net/bnxt/tf_ulp/ulp_port_db.c | 15 +-
> drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c | 31 +
> drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 663 +-
> drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 12 +-
> drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 32 +-
> drivers/net/bnxt/tf_ulp/ulp_tun.c | 521 +-
> drivers/net/bnxt/tf_ulp/ulp_tun.h | 89 +-
> drivers/net/bnxt/tf_ulp/ulp_utils.c | 71 +-
> drivers/net/bnxt/tf_ulp/ulp_utils.h | 27 +-
> meson_options.txt | 2 +
> 64 files changed, 71149 insertions(+), 12956 deletions(-)
> create mode 100644 drivers/net/bnxt/tf_core/tf_sram_mgr.c
> create mode 100644 drivers/net/bnxt/tf_core/tf_sram_mgr.h
> create mode 100644 drivers/net/bnxt/tf_core/tf_tbl_sram.c
> create mode 100644 drivers/net/bnxt/tf_core/tf_tbl_sram.h
>
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 83+ messages in thread* Re: [dpdk-dev] [PATCH v3 00/13] enhancements to host based flow table management
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 00/13] enhancements to host based flow table management Venkat Duvvuru
` (13 preceding siblings ...)
2021-09-16 3:25 ` [dpdk-dev] [PATCH v3 00/13] enhancements to host based flow table management Ajit Khaparde
@ 2021-09-16 13:26 ` Ferruh Yigit
2021-09-16 14:17 ` Brandon Lo
2021-09-16 16:18 ` Ajit Khaparde
14 siblings, 2 replies; 83+ messages in thread
From: Ferruh Yigit @ 2021-09-16 13:26 UTC (permalink / raw)
To: Ajit Khaparde, Aaron Conole, dpdklab
Cc: Venkat Duvvuru, dev, Thomas Monjalon, David Marchand, Ali Alnubani
On 9/11/2021 4:30 PM, Venkat Duvvuru wrote:
> This patch set adds support for new offload features/enhancments for
> Thor adapters like VF representor support, new flow matches/actions
> & dynamic SRAM manager support.
>
> v2 ==> v3
> =========
> * Fixed compilation issue.
>
> Farah Smith (4):
> net/bnxt: tf core index table updates
> net/bnxt: add Thor SRAM mgr model
> net/bnxt: tf core SRAM Manager
> net/bnxt: sram manager shared session
>
> Jay Ding (1):
> net/bnxt: add flow meter drop counter support
>
> Kishore Padmanabha (6):
> net/bnxt: add flow templates support for Thor
> net/bnxt: add support for tunnel offloads
> net/bnxt: add support for dynamic encap action
> net/bnxt: add wild card TCAM byte order for Thor
> net/bnxt: add flow templates for Thor
> net/bnxt: add enhancements to TF ULP
>
> Peter Spreadborough (1):
> net/bnxt: enable dpool allocator
>
> Randy Schacher (1):
> net/bnxt: dynamically allocate space for EM defrag function
>
Hi Ajit,
There are a few checkpatch errors reported, can you please check them?
Also CI seems failed to apply the patch and not run, indeed patch is merged in
the correct tree, but seems on top of wrong commit [1].
Aaron, Lab,
Can you please check if there is an issue with the tree synchronization. (This
is previously reported for eventdev too, perhaps there may be a generic problem.)
Can you please trigger the testing of this set after repo updated?
[1]
dpdk-next-net-brcm (175af25734f295874e31b33ccd0879e69fd152a9)
^ permalink raw reply [flat|nested] 83+ messages in thread* Re: [dpdk-dev] [PATCH v3 00/13] enhancements to host based flow table management
2021-09-16 13:26 ` Ferruh Yigit
@ 2021-09-16 14:17 ` Brandon Lo
2021-09-16 16:18 ` Ajit Khaparde
1 sibling, 0 replies; 83+ messages in thread
From: Brandon Lo @ 2021-09-16 14:17 UTC (permalink / raw)
To: Ferruh Yigit
Cc: Ajit Khaparde, Aaron Conole, dpdklab, Venkat Duvvuru, dev,
Thomas Monjalon, David Marchand, Ali Alnubani
On Thu, Sep 16, 2021 at 9:26 AM Ferruh Yigit <ferruh.yigit@intel.com> wrote:
>
> On 9/11/2021 4:30 PM, Venkat Duvvuru wrote:
> > This patch set adds support for new offload features/enhancments for
> > Thor adapters like VF representor support, new flow matches/actions
> > & dynamic SRAM manager support.
> >
> > v2 ==> v3
> > =========
> > * Fixed compilation issue.
> >
> > Farah Smith (4):
> > net/bnxt: tf core index table updates
> > net/bnxt: add Thor SRAM mgr model
> > net/bnxt: tf core SRAM Manager
> > net/bnxt: sram manager shared session
> >
> > Jay Ding (1):
> > net/bnxt: add flow meter drop counter support
> >
> > Kishore Padmanabha (6):
> > net/bnxt: add flow templates support for Thor
> > net/bnxt: add support for tunnel offloads
> > net/bnxt: add support for dynamic encap action
> > net/bnxt: add wild card TCAM byte order for Thor
> > net/bnxt: add flow templates for Thor
> > net/bnxt: add enhancements to TF ULP
> >
> > Peter Spreadborough (1):
> > net/bnxt: enable dpool allocator
> >
> > Randy Schacher (1):
> > net/bnxt: dynamically allocate space for EM defrag function
> >
>
> Hi Ajit,
>
> There are a few checkpatch errors reported, can you please check them?
>
> Also CI seems failed to apply the patch and not run, indeed patch is merged in
> the correct tree, but seems on top of wrong commit [1].
>
>
> Aaron, Lab,
>
> Can you please check if there is an issue with the tree synchronization. (This
> is previously reported for eventdev too, perhaps there may be a generic problem.)
>
> Can you please trigger the testing of this set after repo updated?
>
>
> [1]
> dpdk-next-net-brcm (175af25734f295874e31b33ccd0879e69fd152a9)
Hi all,
This is related to a current migration that is in process within the
lab. I have found the root cause for this issue, and I am working on a
solution to fix this tree synchronization issue. Once I have a stable
solution, I will rerun the patches that failed to apply.
Thanks,
Brandon
--
Brandon Lo
UNH InterOperability Laboratory
21 Madbury Rd, Suite 100, Durham, NH 03824
blo@iol.unh.edu
www.iol.unh.edu
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [dpdk-dev] [PATCH v3 00/13] enhancements to host based flow table management
2021-09-16 13:26 ` Ferruh Yigit
2021-09-16 14:17 ` Brandon Lo
@ 2021-09-16 16:18 ` Ajit Khaparde
1 sibling, 0 replies; 83+ messages in thread
From: Ajit Khaparde @ 2021-09-16 16:18 UTC (permalink / raw)
To: Ferruh Yigit
Cc: Aaron Conole, dpdklab, Venkat Duvvuru, dpdk-dev, Thomas Monjalon,
David Marchand, Ali Alnubani
[-- Attachment #1: Type: text/plain, Size: 1875 bytes --]
On Thu, Sep 16, 2021 at 6:26 AM Ferruh Yigit <ferruh.yigit@intel.com> wrote:
>
> On 9/11/2021 4:30 PM, Venkat Duvvuru wrote:
> > This patch set adds support for new offload features/enhancments for
> > Thor adapters like VF representor support, new flow matches/actions
> > & dynamic SRAM manager support.
> >
> > v2 ==> v3
> > =========
> > * Fixed compilation issue.
> >
> > Farah Smith (4):
> > net/bnxt: tf core index table updates
> > net/bnxt: add Thor SRAM mgr model
> > net/bnxt: tf core SRAM Manager
> > net/bnxt: sram manager shared session
> >
> > Jay Ding (1):
> > net/bnxt: add flow meter drop counter support
> >
> > Kishore Padmanabha (6):
> > net/bnxt: add flow templates support for Thor
> > net/bnxt: add support for tunnel offloads
> > net/bnxt: add support for dynamic encap action
> > net/bnxt: add wild card TCAM byte order for Thor
> > net/bnxt: add flow templates for Thor
> > net/bnxt: add enhancements to TF ULP
> >
> > Peter Spreadborough (1):
> > net/bnxt: enable dpool allocator
> >
> > Randy Schacher (1):
> > net/bnxt: dynamically allocate space for EM defrag function
> >
>
> Hi Ajit,
>
> There are a few checkpatch errors reported, can you please check them?
I had taken care of them, but I forgot to mention it in my merge mail.
So the next spin of the patches should have those addressed.
>
> Also CI seems failed to apply the patch and not run, indeed patch is merged in
> the correct tree, but seems on top of wrong commit [1].
Looks like Brandon has root caused it.
Thanks
Ajit
>
>
> Aaron, Lab,
>
> Can you please check if there is an issue with the tree synchronization. (This
> is previously reported for eventdev too, perhaps there may be a generic problem.)
>
> Can you please trigger the testing of this set after repo updated?
>
>
> [1]
> dpdk-next-net-brcm (175af25734f295874e31b33ccd0879e69fd152a9)
^ permalink raw reply [flat|nested] 83+ messages in thread
* [dpdk-dev] [PATCH v4 00/13] enhancements to host based flow table management
2021-09-08 5:06 ` [dpdk-dev] [PATCH v2 00/13] enhancements to host based flow table management Venkat Duvvuru
` (13 preceding siblings ...)
2021-09-11 15:30 ` [dpdk-dev] [PATCH v3 00/13] enhancements to host based flow table management Venkat Duvvuru
@ 2021-09-20 7:42 ` Venkat Duvvuru
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 01/13] net/bnxt: updates to TF core index table Venkat Duvvuru
` (13 more replies)
14 siblings, 14 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-20 7:42 UTC (permalink / raw)
To: dev; +Cc: Venkat Duvvuru
This patch set adds support for new offload features/enhancments for
Thor adapters like VF representor support, new flow matches/actions
& dynamic SRAM manager support.
Farah Smith (4):
net/bnxt: updates to TF core index table
net/bnxt: add SRAM manager model
net/bnxt: change log level to debug
net/bnxt: add SRAM manager shared session
Jay Ding (1):
net/bnxt: add flow meter drop counter support
Kishore Padmanabha (6):
net/bnxt: add flow template support for Thor
net/bnxt: add support for tunnel offload API
net/bnxt: add support for dynamic encap action
net/bnxt: add wild card TCAM byte order for Thor
net/bnxt: add flow templates for Thor
net/bnxt: add enhancements to TF ULP
Peter Spreadborough (1):
net/bnxt: enable dpool allocator
Randy Schacher (1):
net/bnxt: dynamically allocate space for EM defrag function
doc/guides/rel_notes/release_21_11.rst | 6 +
drivers/net/bnxt/tf_core/cfa_resource_types.h | 5 +-
drivers/net/bnxt/tf_core/dpool.c | 38 +-
drivers/net/bnxt/tf_core/ll.c | 3 +
drivers/net/bnxt/tf_core/ll.h | 50 +-
drivers/net/bnxt/tf_core/meson.build | 2 +
drivers/net/bnxt/tf_core/tf_core.c | 169 +-
drivers/net/bnxt/tf_core/tf_core.h | 159 +-
drivers/net/bnxt/tf_core/tf_device.c | 40 +-
drivers/net/bnxt/tf_core/tf_device.h | 137 +-
drivers/net/bnxt/tf_core/tf_device_p4.c | 77 +-
drivers/net/bnxt/tf_core/tf_device_p4.h | 50 +-
drivers/net/bnxt/tf_core/tf_device_p58.c | 112 +-
drivers/net/bnxt/tf_core/tf_device_p58.h | 70 +-
drivers/net/bnxt/tf_core/tf_em.h | 10 -
drivers/net/bnxt/tf_core/tf_em_common.c | 4 +
.../net/bnxt/tf_core/tf_em_hash_internal.c | 34 -
drivers/net/bnxt/tf_core/tf_em_internal.c | 185 +-
drivers/net/bnxt/tf_core/tf_msg.c | 2 +-
drivers/net/bnxt/tf_core/tf_rm.c | 180 +-
drivers/net/bnxt/tf_core/tf_rm.h | 62 +-
drivers/net/bnxt/tf_core/tf_session.c | 56 +
drivers/net/bnxt/tf_core/tf_session.h | 58 +-
drivers/net/bnxt/tf_core/tf_sram_mgr.c | 971 +
drivers/net/bnxt/tf_core/tf_sram_mgr.h | 317 +
drivers/net/bnxt/tf_core/tf_tbl.c | 259 +-
drivers/net/bnxt/tf_core/tf_tbl.h | 87 +-
drivers/net/bnxt/tf_core/tf_tbl_sram.c | 747 +
drivers/net/bnxt/tf_core/tf_tbl_sram.h | 154 +
drivers/net/bnxt/tf_core/tf_tcam.c | 16 +-
drivers/net/bnxt/tf_core/tf_tcam.h | 7 +
drivers/net/bnxt/tf_core/tf_tcam_shared.c | 28 +-
drivers/net/bnxt/tf_core/tf_util.c | 12 +
drivers/net/bnxt/tf_ulp/bnxt_tf_common.h | 10 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 52 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 20 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 226 +-
.../bnxt/tf_ulp/generic_templates/meson.build | 3 +
.../generic_templates/ulp_template_db_act.c | 2 +-
.../generic_templates/ulp_template_db_class.c | 12109 +++-
.../generic_templates/ulp_template_db_enum.h | 618 +-
.../generic_templates/ulp_template_db_field.h | 767 +-
.../generic_templates/ulp_template_db_tbl.c | 2757 +-
.../ulp_template_db_thor_act.c | 5079 +-
.../ulp_template_db_thor_class.c | 45573 ++++++++++++++--
.../ulp_template_db_wh_plus_act.c | 1700 +-
.../ulp_template_db_wh_plus_class.c | 8329 ++-
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 48 +-
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h | 8 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 678 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 68 +-
drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c | 9 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 448 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.h | 10 +-
drivers/net/bnxt/tf_ulp/ulp_matcher.c | 13 +
drivers/net/bnxt/tf_ulp/ulp_port_db.c | 15 +-
drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c | 31 +
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 663 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 12 +-
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 32 +-
drivers/net/bnxt/tf_ulp/ulp_tun.c | 521 +-
drivers/net/bnxt/tf_ulp/ulp_tun.h | 89 +-
drivers/net/bnxt/tf_ulp/ulp_utils.c | 71 +-
drivers/net/bnxt/tf_ulp/ulp_utils.h | 27 +-
64 files changed, 71146 insertions(+), 12949 deletions(-)
create mode 100644 drivers/net/bnxt/tf_core/tf_sram_mgr.c
create mode 100644 drivers/net/bnxt/tf_core/tf_sram_mgr.h
create mode 100644 drivers/net/bnxt/tf_core/tf_tbl_sram.c
create mode 100644 drivers/net/bnxt/tf_core/tf_tbl_sram.h
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v4 01/13] net/bnxt: updates to TF core index table
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 " Venkat Duvvuru
@ 2021-09-20 7:42 ` Venkat Duvvuru
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 02/13] net/bnxt: enable dpool allocator Venkat Duvvuru
` (12 subsequent siblings)
13 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-20 7:42 UTC (permalink / raw)
To: dev; +Cc: Farah Smith
From: Farah Smith <farah.smith@broadcom.com>
Update the TRUFLOW core index table and
remove unused shadow table functionality.
Signed-off-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Peter Spreadborough <peter.spreadborough@broadcom.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/tf_core/tf_core.c | 65 --------------
drivers/net/bnxt/tf_core/tf_core.h | 103 +----------------------
drivers/net/bnxt/tf_core/tf_device.h | 22 -----
drivers/net/bnxt/tf_core/tf_device_p4.c | 2 -
drivers/net/bnxt/tf_core/tf_device_p58.c | 2 -
drivers/net/bnxt/tf_core/tf_em_common.c | 4 +
drivers/net/bnxt/tf_core/tf_tbl.c | 21 -----
drivers/net/bnxt/tf_core/tf_tbl.h | 72 ----------------
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 3 +-
9 files changed, 7 insertions(+), 287 deletions(-)
diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c
index 97e6165e92..5458f76e2d 100644
--- a/drivers/net/bnxt/tf_core/tf_core.c
+++ b/drivers/net/bnxt/tf_core/tf_core.c
@@ -1105,71 +1105,6 @@ tf_alloc_tbl_entry(struct tf *tfp,
return 0;
}
-int
-tf_search_tbl_entry(struct tf *tfp,
- struct tf_search_tbl_entry_parms *parms)
-{
- int rc;
- struct tf_session *tfs;
- struct tf_dev_info *dev;
- struct tf_tbl_alloc_search_parms sparms;
-
- TF_CHECK_PARMS2(tfp, parms);
-
- /* Retrieve the session information */
- rc = tf_session_get_session(tfp, &tfs);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed to lookup session, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(-rc));
- return rc;
- }
-
- /* Retrieve the device information */
- rc = tf_session_get_device(tfs, &dev);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed to lookup device, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(-rc));
- return rc;
- }
-
- if (dev->ops->tf_dev_alloc_search_tbl == NULL) {
- rc = -EOPNOTSUPP;
- TFP_DRV_LOG(ERR,
- "%s: Operation not supported, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(-rc));
- return rc;
- }
-
- memset(&sparms, 0, sizeof(struct tf_tbl_alloc_search_parms));
- sparms.dir = parms->dir;
- sparms.type = parms->type;
- sparms.result = parms->result;
- sparms.result_sz_in_bytes = parms->result_sz_in_bytes;
- sparms.alloc = parms->alloc;
- sparms.tbl_scope_id = parms->tbl_scope_id;
- rc = dev->ops->tf_dev_alloc_search_tbl(tfp, &sparms);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: TBL allocation failed, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(-rc));
- return rc;
- }
-
- /* Return the outputs from the search */
- parms->hit = sparms.hit;
- parms->search_status = sparms.search_status;
- parms->ref_cnt = sparms.ref_cnt;
- parms->idx = sparms.idx;
-
- return 0;
-}
-
int
tf_free_tbl_entry(struct tf *tfp,
struct tf_free_tbl_entry_parms *parms)
diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h
index 84b234f0e3..7e0cdf7e0d 100644
--- a/drivers/net/bnxt/tf_core/tf_core.h
+++ b/drivers/net/bnxt/tf_core/tf_core.h
@@ -1622,79 +1622,6 @@ int tf_clear_tcam_shared_entries(struct tf *tfp,
* @ref tf_get_shared_tbl_increment
*/
-/**
- * tf_alloc_tbl_entry parameter definition
- */
-struct tf_search_tbl_entry_parms {
- /**
- * [in] Receive or transmit direction
- */
- enum tf_dir dir;
- /**
- * [in] Type of the allocation
- */
- enum tf_tbl_type type;
- /**
- * [in] Table scope identifier (ignored unless TF_TBL_TYPE_EXT)
- */
- uint32_t tbl_scope_id;
- /**
- * [in] Result data to search for
- */
- uint8_t *result;
- /**
- * [in] Result data size in bytes
- */
- uint16_t result_sz_in_bytes;
- /**
- * [in] Allocate on miss.
- */
- uint8_t alloc;
- /**
- * [out] Set if matching entry found
- */
- uint8_t hit;
- /**
- * [out] Search result status (hit, miss, reject)
- */
- enum tf_search_status search_status;
- /**
- * [out] Current ref count after allocation
- */
- uint16_t ref_cnt;
- /**
- * [out] Idx of allocated entry or found entry
- */
- uint32_t idx;
-};
-
-/**
- * search Table Entry (experimental)
- *
- * This function searches the shadow copy of an index table for a matching
- * entry. The result data must match for hit to be set. Only TruFlow core
- * data is accessed. If shadow_copy is not enabled, an error is returned.
- *
- * Implementation:
- *
- * A hash is performed on the result data and mapped to a shadow copy entry
- * where the result is populated. If the result matches the entry, hit is set,
- * ref_cnt is incremented (if alloc), and the search status indicates what
- * action the caller can take regarding setting the entry.
- *
- * search status should be used as follows:
- * - On MISS, the caller should set the result into the returned index.
- *
- * - On REJECT, the caller should reject the flow since there are no resources.
- *
- * - On Hit, the matching index is returned to the caller. Additionally, the
- * ref_cnt is updated.
- *
- * Also returns success or failure code.
- */
-int tf_search_tbl_entry(struct tf *tfp,
- struct tf_search_tbl_entry_parms *parms);
-
/**
* tf_alloc_tbl_entry parameter definition
*/
@@ -1711,30 +1638,9 @@ struct tf_alloc_tbl_entry_parms {
* [in] Table scope identifier (ignored unless TF_TBL_TYPE_EXT)
*/
uint32_t tbl_scope_id;
+
/**
- * [in] Enable search for matching entry. If the table type is
- * internal the shadow copy will be searched before
- * alloc. Session must be configured with shadow copy enabled.
- */
- uint8_t search_enable;
- /**
- * [in] Result data to search for (if search_enable)
- */
- uint8_t *result;
- /**
- * [in] Result data size in bytes (if search_enable)
- */
- uint16_t result_sz_in_bytes;
- /**
- * [out] If search_enable, set if matching entry found
- */
- uint8_t hit;
- /**
- * [out] Current ref count after allocation (if search_enable)
- */
- uint16_t ref_cnt;
- /**
- * [out] Idx of allocated entry or found entry (if search_enable)
+ * [out] Idx of allocated entry
*/
uint32_t idx;
};
@@ -1790,11 +1696,6 @@ struct tf_free_tbl_entry_parms {
* [in] Index to free
*/
uint32_t idx;
- /**
- * [out] Reference count after free, only valid if session has been
- * created with shadow_copy.
- */
- uint16_t ref_cnt;
};
/**
diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h
index da3f541685..b43cfc6925 100644
--- a/drivers/net/bnxt/tf_core/tf_device.h
+++ b/drivers/net/bnxt/tf_core/tf_device.h
@@ -347,28 +347,6 @@ struct tf_dev_ops {
int (*tf_dev_free_ext_tbl)(struct tf *tfp,
struct tf_tbl_free_parms *parms);
- /**
- * Searches for the specified table type element in a shadow DB.
- *
- * This API searches for the specified table type element in a
- * device specific shadow DB. If the element is found the
- * reference count for the element is updated. If the element
- * is not found a new element is allocated from the table type
- * DB and then inserted into the shadow DB.
- *
- * [in] tfp
- * Pointer to TF handle
- *
- * [in] parms
- * Pointer to table allocation and search parameters
- *
- * Returns
- * - (0) if successful.
- * - (-EINVAL) on failure.
- */
- int (*tf_dev_alloc_search_tbl)(struct tf *tfp,
- struct tf_tbl_alloc_search_parms *parms);
-
/**
* Sets the specified table type element.
*
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c
index 971fab7bda..2e7ccec123 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.c
@@ -236,7 +236,6 @@ const struct tf_dev_ops tf_dev_ops_p4_init = {
.tf_dev_alloc_tbl = NULL,
.tf_dev_free_ext_tbl = NULL,
.tf_dev_free_tbl = NULL,
- .tf_dev_alloc_search_tbl = NULL,
.tf_dev_set_tbl = NULL,
.tf_dev_set_ext_tbl = NULL,
.tf_dev_get_tbl = NULL,
@@ -282,7 +281,6 @@ const struct tf_dev_ops tf_dev_ops_p4 = {
.tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc,
.tf_dev_free_tbl = tf_tbl_free,
.tf_dev_free_ext_tbl = tf_tbl_ext_free,
- .tf_dev_alloc_search_tbl = tf_tbl_alloc_search,
.tf_dev_set_tbl = tf_tbl_set,
.tf_dev_set_ext_tbl = tf_tbl_ext_common_set,
.tf_dev_get_tbl = tf_tbl_get,
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c
index 6bbc5e21e9..ce4d8c661f 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.c
@@ -280,7 +280,6 @@ const struct tf_dev_ops tf_dev_ops_p58_init = {
.tf_dev_alloc_tbl = NULL,
.tf_dev_free_ext_tbl = NULL,
.tf_dev_free_tbl = NULL,
- .tf_dev_alloc_search_tbl = NULL,
.tf_dev_set_tbl = NULL,
.tf_dev_set_ext_tbl = NULL,
.tf_dev_get_tbl = NULL,
@@ -326,7 +325,6 @@ const struct tf_dev_ops tf_dev_ops_p58 = {
.tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc,
.tf_dev_free_tbl = tf_tbl_free,
.tf_dev_free_ext_tbl = tf_tbl_ext_free,
- .tf_dev_alloc_search_tbl = tf_tbl_alloc_search,
.tf_dev_set_tbl = tf_tbl_set,
.tf_dev_set_ext_tbl = tf_tbl_ext_common_set,
.tf_dev_get_tbl = tf_tbl_get,
diff --git a/drivers/net/bnxt/tf_core/tf_em_common.c b/drivers/net/bnxt/tf_core/tf_em_common.c
index 812ccb0d29..3bdfc14e05 100644
--- a/drivers/net/bnxt/tf_core/tf_em_common.c
+++ b/drivers/net/bnxt/tf_core/tf_em_common.c
@@ -23,6 +23,10 @@
#include "bnxt.h"
+
+/** Invalid table scope id */
+#define TF_TBL_SCOPE_INVALID 0xffffffff
+
/* Number of pointers per page_size */
#define MAX_PAGE_PTRS(page_size) ((page_size) / sizeof(void *))
diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c
index ced59130b2..e77399c6bd 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl.c
+++ b/drivers/net/bnxt/tf_core/tf_tbl.c
@@ -26,11 +26,6 @@
struct tf;
-/**
- * Table Shadow DBs
- */
-static void *shadow_tbl_db[TF_DIR_MAX];
-
/**
* Shadow init flag, set on bind and cleared on unbind
*/
@@ -327,22 +322,6 @@ tf_tbl_free(struct tf *tfp __rte_unused,
return 0;
}
-int
-tf_tbl_alloc_search(struct tf *tfp,
- struct tf_tbl_alloc_search_parms *parms)
-{
- int rc = 0;
- TF_CHECK_PARMS2(tfp, parms);
-
- if (!shadow_init || !shadow_tbl_db[parms->dir]) {
- TFP_DRV_LOG(ERR, "%s: Shadow TBL not initialized.\n",
- tf_dir_2_str(parms->dir));
- return -EINVAL;
- }
-
- return rc;
-}
-
int
tf_tbl_set(struct tf *tfp,
struct tf_tbl_set_parms *parms)
diff --git a/drivers/net/bnxt/tf_core/tf_tbl.h b/drivers/net/bnxt/tf_core/tf_tbl.h
index aba46fd161..7e1107ffe7 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl.h
+++ b/drivers/net/bnxt/tf_core/tf_tbl.h
@@ -15,8 +15,6 @@ struct tf;
* The Table module provides processing of Internal TF table types.
*/
-/** Invalid table scope id */
-#define TF_TBL_SCOPE_INVALID 0xffffffff
/**
* Table configuration parameters
@@ -86,57 +84,6 @@ struct tf_tbl_free_parms {
* [in] Index to free
*/
uint32_t idx;
- /**
- * [out] Reference count after free, only valid if session has been
- * created with shadow_copy.
- */
- uint16_t ref_cnt;
-};
-
-/**
- * Table allocate search parameters
- */
-struct tf_tbl_alloc_search_parms {
- /**
- * [in] Receive or transmit direction
- */
- enum tf_dir dir;
- /**
- * [in] Type of the allocation
- */
- enum tf_tbl_type type;
- /**
- * [in] Table scope identifier (ignored unless TF_TBL_TYPE_EXT)
- */
- uint32_t tbl_scope_id;
- /**
- * [in] Result data to search for
- */
- uint8_t *result;
- /**
- * [in] Result data size in bytes
- */
- uint16_t result_sz_in_bytes;
- /**
- * [in] Whether or not to allocate on MISS, 1 is allocate.
- */
- uint8_t alloc;
- /**
- * [out] If search_enable, set if matching entry found
- */
- uint8_t hit;
- /**
- * [out] The status of the search (REJECT, MISS, HIT)
- */
- enum tf_search_status search_status;
- /**
- * [out] Current ref count after allocation
- */
- uint16_t ref_cnt;
- /**
- * [out] Idx of allocated entry or found entry
- */
- uint32_t idx;
};
/**
@@ -326,25 +273,6 @@ int tf_tbl_alloc(struct tf *tfp,
int tf_tbl_free(struct tf *tfp,
struct tf_tbl_free_parms *parms);
-/**
- * Supported if Shadow DB is configured. Searches the Shadow DB for
- * any matching element. If found the refcount in the shadow DB is
- * updated accordingly. If not found a new element is allocated and
- * installed into the shadow DB.
- *
- * [in] tfp
- * Pointer to TF handle, used for HCAPI communication
- *
- * [in] parms
- * Pointer to parameters
- *
- * Returns
- * - (0) if successful.
- * - (-EINVAL) on failure.
- */
-int tf_tbl_alloc_search(struct tf *tfp,
- struct tf_tbl_alloc_search_parms *parms);
-
/**
* Configures the requested element by sending a firmware request which
* then installs it into the device internal structures.
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 871dbad0fe..f3a60cc880 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -189,13 +189,12 @@ ulp_mapper_resource_index_tbl_alloc(struct bnxt_ulp_context *ulp_ctx,
aparms.type = glb_res->resource_type;
aparms.dir = glb_res->direction;
- aparms.search_enable = 0;
aparms.tbl_scope_id = tbl_scope_id;
/* Allocate the index tbl using tf api */
rc = tf_alloc_tbl_entry(tfp, &aparms);
if (rc) {
- BNXT_TF_DBG(ERR, "Failed to alloc identifier [%s][%d]\n",
+ BNXT_TF_DBG(ERR, "Failed to alloc index table [%s][%d]\n",
tf_dir_2_str(aparms.dir), aparms.type);
return rc;
}
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v4 02/13] net/bnxt: enable dpool allocator
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 " Venkat Duvvuru
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 01/13] net/bnxt: updates to TF core index table Venkat Duvvuru
@ 2021-09-20 7:42 ` Venkat Duvvuru
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 03/13] net/bnxt: add flow meter drop counter support Venkat Duvvuru
` (11 subsequent siblings)
13 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-20 7:42 UTC (permalink / raw)
To: dev; +Cc: Peter Spreadborough
From: Peter Spreadborough <peter.spreadborough@broadcom.com>
Enable dynamic entry allocator for Exact Match SRAM entries.
Deprecate static entry allocator code.
Signed-off-by: Peter Spreadborough <peter.spreadborough@broadcom.com>
Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/tf_core/tf_device_p58.c | 4 -
drivers/net/bnxt/tf_core/tf_em.h | 10 -
.../net/bnxt/tf_core/tf_em_hash_internal.c | 34 ----
drivers/net/bnxt/tf_core/tf_em_internal.c | 180 +-----------------
4 files changed, 1 insertion(+), 227 deletions(-)
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c
index ce4d8c661f..808dcb1f77 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.c
@@ -348,11 +348,7 @@ const struct tf_dev_ops tf_dev_ops_p58 = {
.tf_dev_get_tcam_resc_info = tf_tcam_get_resc_info,
.tf_dev_insert_int_em_entry = tf_em_hash_insert_int_entry,
.tf_dev_delete_int_em_entry = tf_em_hash_delete_int_entry,
-#if (TF_EM_ALLOC == 1)
.tf_dev_move_int_em_entry = tf_em_move_int_entry,
-#else
- .tf_dev_move_int_em_entry = NULL,
-#endif
.tf_dev_insert_ext_em_entry = NULL,
.tf_dev_delete_ext_em_entry = NULL,
.tf_dev_get_em_resc_info = tf_em_get_resc_info,
diff --git a/drivers/net/bnxt/tf_core/tf_em.h b/drivers/net/bnxt/tf_core/tf_em.h
index 568071ad8c..074c128651 100644
--- a/drivers/net/bnxt/tf_core/tf_em.h
+++ b/drivers/net/bnxt/tf_core/tf_em.h
@@ -13,16 +13,6 @@
#include "hcapi_cfa_defs.h"
-/**
- * TF_EM_ALLOC
- *
- * 0: Use stack allocator with fixed sized entries
- * (default).
- * 1: Use dpool allocator with variable size
- * entries.
- */
-#define TF_EM_ALLOC 0
-
#define TF_EM_MIN_ENTRIES (1 << 15) /* 32K */
#define TF_EM_MAX_ENTRIES (1 << 27) /* 128M */
diff --git a/drivers/net/bnxt/tf_core/tf_em_hash_internal.c b/drivers/net/bnxt/tf_core/tf_em_hash_internal.c
index 098e8af07e..60273a798c 100644
--- a/drivers/net/bnxt/tf_core/tf_em_hash_internal.c
+++ b/drivers/net/bnxt/tf_core/tf_em_hash_internal.c
@@ -22,9 +22,7 @@
/**
* EM Pool
*/
-#if (TF_EM_ALLOC == 1)
#include "dpool.h"
-#endif
/**
* Insert EM internal entry API
@@ -41,11 +39,7 @@ tf_em_hash_insert_int_entry(struct tf *tfp,
uint16_t rptr_index = 0;
uint8_t rptr_entry = 0;
uint8_t num_of_entries = 0;
-#if (TF_EM_ALLOC == 1)
struct dpool *pool;
-#else
- struct stack *pool;
-#endif
uint32_t index;
uint32_t key0_hash;
uint32_t key1_hash;
@@ -62,7 +56,6 @@ tf_em_hash_insert_int_entry(struct tf *tfp,
rc = tf_session_get_device(tfs, &dev);
if (rc)
return rc;
-#if (TF_EM_ALLOC == 1)
pool = (struct dpool *)tfs->em_pool[parms->dir];
index = dpool_alloc(pool,
parms->em_record_sz_in_bits / 128,
@@ -74,16 +67,6 @@ tf_em_hash_insert_int_entry(struct tf *tfp,
tf_dir_2_str(parms->dir));
return -1;
}
-#else
- pool = (struct stack *)tfs->em_pool[parms->dir];
- rc = stack_pop(pool, &index);
- if (rc) {
- PMD_DRV_LOG(ERR,
- "%s, EM entry index allocation failed\n",
- tf_dir_2_str(parms->dir));
- return rc;
- }
-#endif
if (dev->ops->tf_dev_cfa_key_hash == NULL)
return -EINVAL;
@@ -103,11 +86,7 @@ tf_em_hash_insert_int_entry(struct tf *tfp,
&num_of_entries);
if (rc) {
/* Free the allocated index before returning */
-#if (TF_EM_ALLOC == 1)
dpool_free(pool, index);
-#else
- stack_push(pool, index);
-#endif
return -1;
}
@@ -128,9 +107,7 @@ tf_em_hash_insert_int_entry(struct tf *tfp,
rptr_index,
rptr_entry,
0);
-#if (TF_EM_ALLOC == 1)
dpool_set_entry_data(pool, index, parms->flow_handle);
-#endif
return 0;
}
@@ -146,11 +123,7 @@ tf_em_hash_delete_int_entry(struct tf *tfp,
{
int rc = 0;
struct tf_session *tfs;
-#if (TF_EM_ALLOC == 1)
struct dpool *pool;
-#else
- struct stack *pool;
-#endif
/* Retrieve the session information */
rc = tf_session_get_session(tfp, &tfs);
if (rc) {
@@ -165,19 +138,13 @@ tf_em_hash_delete_int_entry(struct tf *tfp,
/* Return resource to pool */
if (rc == 0) {
-#if (TF_EM_ALLOC == 1)
pool = (struct dpool *)tfs->em_pool[parms->dir];
dpool_free(pool, parms->index);
-#else
- pool = (struct stack *)tfs->em_pool[parms->dir];
- stack_push(pool, parms->index);
-#endif
}
return rc;
}
-#if (TF_EM_ALLOC == 1)
/** Move EM internal entry API
*
* returns:
@@ -212,4 +179,3 @@ tf_em_move_int_entry(struct tf *tfp,
return rc;
}
-#endif
diff --git a/drivers/net/bnxt/tf_core/tf_em_internal.c b/drivers/net/bnxt/tf_core/tf_em_internal.c
index 0720bb905d..2d57595f17 100644
--- a/drivers/net/bnxt/tf_core/tf_em_internal.c
+++ b/drivers/net/bnxt/tf_core/tf_em_internal.c
@@ -22,145 +22,7 @@
/**
* EM Pool
*/
-#if (TF_EM_ALLOC == 1)
#include "dpool.h"
-#else
-
-/**
- * Create EM Tbl pool of memory indexes.
- *
- * [in] dir
- * direction
- * [in] num_entries
- * number of entries to write
- * [in] start
- * starting offset
- *
- * Return:
- * 0 - Success, entry allocated - no search support
- * -ENOMEM -EINVAL -EOPNOTSUPP
- * - Failure, entry not allocated, out of resources
- */
-static int
-tf_create_em_pool(struct tf_session *tfs,
- enum tf_dir dir,
- uint32_t num_entries,
- uint32_t start)
-{
- struct tfp_calloc_parms parms;
- uint32_t i, j;
- int rc = 0;
- struct stack *pool;
-
- /*
- * Allocate stack pool
- */
- parms.nitems = 1;
- parms.size = sizeof(struct stack);
- parms.alignment = 0;
-
- rc = tfp_calloc(&parms);
-
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s, EM stack allocation failure %s\n",
- tf_dir_2_str(dir),
- strerror(-rc));
- return rc;
- }
-
- pool = (struct stack *)parms.mem_va;
- tfs->em_pool[dir] = (void *)pool;
-
- /* Assumes that num_entries has been checked before we get here */
- parms.nitems = num_entries / TF_SESSION_EM_ENTRY_SIZE;
- parms.size = sizeof(uint32_t);
- parms.alignment = 0;
-
- rc = tfp_calloc(&parms);
-
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s, EM pool allocation failure %s\n",
- tf_dir_2_str(dir),
- strerror(-rc));
- return rc;
- }
-
- /* Create empty stack
- */
- rc = stack_init(num_entries / TF_SESSION_EM_ENTRY_SIZE,
- (uint32_t *)parms.mem_va,
- pool);
-
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s, EM pool stack init failure %s\n",
- tf_dir_2_str(dir),
- strerror(-rc));
- goto cleanup;
- }
-
- /* Fill pool with indexes
- */
- j = start + num_entries - TF_SESSION_EM_ENTRY_SIZE;
-
- for (i = 0; i < (num_entries / TF_SESSION_EM_ENTRY_SIZE); i++) {
- rc = stack_push(pool, j);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s, EM pool stack push failure %s\n",
- tf_dir_2_str(dir),
- strerror(-rc));
- goto cleanup;
- }
-
- j -= TF_SESSION_EM_ENTRY_SIZE;
- }
-
- if (!stack_is_full(pool)) {
- rc = -EINVAL;
- TFP_DRV_LOG(ERR,
- "%s, EM pool stack failure %s\n",
- tf_dir_2_str(dir),
- strerror(-rc));
- goto cleanup;
- }
-
- return 0;
-cleanup:
- tfp_free((void *)parms.mem_va);
- tfp_free((void *)tfs->em_pool[dir]);
- tfs->em_pool[dir] = NULL;
- return rc;
-}
-
-/**
- * Create EM Tbl pool of memory indexes.
- *
- * [in] dir
- * direction
- *
- * Return:
- */
-static void
-tf_free_em_pool(struct tf_session *tfs,
- enum tf_dir dir)
-{
- struct stack *pool = (struct stack *)tfs->em_pool[dir];
- uint32_t *ptr;
-
- if (pool != NULL) {
- ptr = stack_items(pool);
-
- if (ptr != NULL)
- tfp_free(ptr);
-
- tfp_free(pool);
- tfs->em_pool[dir] = NULL;
- }
-}
-#endif /* TF_EM_ALLOC != 1 */
/**
* Insert EM internal entry API
@@ -178,11 +40,7 @@ tf_em_insert_int_entry(struct tf *tfp,
uint8_t rptr_entry = 0;
uint8_t num_of_entries = 0;
struct tf_session *tfs;
-#if (TF_EM_ALLOC == 1)
struct dpool *pool;
-#else
- struct stack *pool;
-#endif
uint32_t index;
/* Retrieve the session information */
@@ -195,7 +53,6 @@ tf_em_insert_int_entry(struct tf *tfp,
return rc;
}
-#if (TF_EM_ALLOC == 1)
pool = (struct dpool *)tfs->em_pool[parms->dir];
index = dpool_alloc(pool, TF_SESSION_EM_ENTRY_SIZE, 0);
if (index == DP_INVALID_INDEX) {
@@ -204,16 +61,6 @@ tf_em_insert_int_entry(struct tf *tfp,
tf_dir_2_str(parms->dir));
return -1;
}
-#else
- pool = (struct stack *)tfs->em_pool[parms->dir];
- rc = stack_pop(pool, &index);
- if (rc) {
- PMD_DRV_LOG(ERR,
- "%s, EM entry index allocation failed\n",
- tf_dir_2_str(parms->dir));
- return rc;
- }
-#endif
rptr_index = index;
@@ -224,11 +71,7 @@ tf_em_insert_int_entry(struct tf *tfp,
&num_of_entries);
if (rc) {
/* Free the allocated index before returning */
-#if (TF_EM_ALLOC == 1)
dpool_free(pool, index);
-#else
- stack_push(pool, index);
-#endif
return -1;
}
TF_SET_GFID(gfid,
@@ -264,11 +107,7 @@ tf_em_delete_int_entry(struct tf *tfp,
{
int rc = 0;
struct tf_session *tfs;
-#if (TF_EM_ALLOC == 1)
struct dpool *pool;
-#else
- struct stack *pool;
-#endif
/* Retrieve the session information */
rc = tf_session_get_session(tfp, &tfs);
if (rc) {
@@ -283,19 +122,13 @@ tf_em_delete_int_entry(struct tf *tfp,
/* Return resource to pool */
if (rc == 0) {
-#if (TF_EM_ALLOC == 1)
pool = (struct dpool *)tfs->em_pool[parms->dir];
dpool_free(pool, parms->index);
-#else
- pool = (struct stack *)tfs->em_pool[parms->dir];
- stack_push(pool, parms->index);
-#endif
}
return rc;
}
-#if (TF_EM_ALLOC == 1)
static int
tf_em_move_callback(void *user_data,
uint64_t entry_data,
@@ -342,7 +175,6 @@ tf_em_move_callback(void *user_data,
return rc;
}
-#endif
int
tf_em_int_bind(struct tf *tfp,
@@ -434,7 +266,7 @@ tf_em_int_bind(struct tf *tfp,
tf_dir_2_str(i));
return rc;
}
-#if (TF_EM_ALLOC == 1)
+
/*
* Allocate stack pool
*/
@@ -460,12 +292,6 @@ tf_em_int_bind(struct tf *tfp,
7,
(void *)tfp,
tf_em_move_callback);
-#else
- rc = tf_create_em_pool(tfs,
- i,
- iparms.info->entry.stride,
- iparms.info->entry.start);
-#endif
/* Logging handled in tf_create_em_pool */
if (rc)
return rc;
@@ -501,11 +327,7 @@ tf_em_int_unbind(struct tf *tfp)
if (!tf_session_is_shared_session(tfs)) {
for (i = 0; i < TF_DIR_MAX; i++)
-#if (TF_EM_ALLOC == 1)
dpool_free_all(tfs->em_pool[i]);
-#else
- tf_free_em_pool(tfs, i);
-#endif
}
rc = tf_session_get_db(tfp, TF_MODULE_TYPE_EM, &em_db_ptr);
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v4 03/13] net/bnxt: add flow meter drop counter support
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 " Venkat Duvvuru
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 01/13] net/bnxt: updates to TF core index table Venkat Duvvuru
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 02/13] net/bnxt: enable dpool allocator Venkat Duvvuru
@ 2021-09-20 7:42 ` Venkat Duvvuru
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 04/13] net/bnxt: add SRAM manager model Venkat Duvvuru
` (10 subsequent siblings)
13 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-20 7:42 UTC (permalink / raw)
To: dev; +Cc: Jay Ding
From: Jay Ding <jay.ding@broadcom.com>
This patch adds flow meter drop counter support for Thor.
Signed-off-by: Jay Ding <jay.ding@broadcom.com>
Reviewed-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/tf_core/cfa_resource_types.h | 5 +-
drivers/net/bnxt/tf_core/tf_core.h | 8 +-
drivers/net/bnxt/tf_core/tf_device_p58.c | 1 +
drivers/net/bnxt/tf_core/tf_device_p58.h | 14 ++++
drivers/net/bnxt/tf_core/tf_tbl.c | 74 +++++++++++--------
drivers/net/bnxt/tf_core/tf_util.c | 2 +
6 files changed, 68 insertions(+), 36 deletions(-)
diff --git a/drivers/net/bnxt/tf_core/cfa_resource_types.h b/drivers/net/bnxt/tf_core/cfa_resource_types.h
index cbab0d0078..36a55d4e17 100644
--- a/drivers/net/bnxt/tf_core/cfa_resource_types.h
+++ b/drivers/net/bnxt/tf_core/cfa_resource_types.h
@@ -104,10 +104,11 @@
#define CFA_RESOURCE_TYPE_P58_WC_FKB 0x12UL
/* VEB TCAM */
#define CFA_RESOURCE_TYPE_P58_VEB_TCAM 0x13UL
+/* Metadata */
+#define CFA_RESOURCE_TYPE_P58_METADATA 0x14UL
/* Meter drop counter */
#define CFA_RESOURCE_TYPE_P58_METER_DROP_CNT 0x15UL
-#define CFA_RESOURCE_TYPE_P58_LAST CFA_RESOURCE_TYPE_P58_METER_DROP_CNT
-
+#define CFA_RESOURCE_TYPE_P58_LAST CFA_RESOURCE_TYPE_P58_METER_DROP_CNT
/* Multicast Group */
#define CFA_RESOURCE_TYPE_P45_MCG 0x0UL
diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h
index 7e0cdf7e0d..af8d13bd7e 100644
--- a/drivers/net/bnxt/tf_core/tf_core.h
+++ b/drivers/net/bnxt/tf_core/tf_core.h
@@ -283,9 +283,9 @@ enum tf_tbl_type {
TF_TBL_TYPE_ACT_MODIFY_32B,
/** TH 64B Modify Record */
TF_TBL_TYPE_ACT_MODIFY_64B,
- /** (Future) Meter Profiles */
+ /** Meter Profiles */
TF_TBL_TYPE_METER_PROF,
- /** (Future) Meter Instance */
+ /** Meter Instance */
TF_TBL_TYPE_METER_INST,
/** Wh+/SR/Th Mirror Config */
TF_TBL_TYPE_MIRROR_CONFIG,
@@ -301,6 +301,8 @@ enum tf_tbl_type {
TF_TBL_TYPE_EM_FKB,
/** TH WC Flexible Key builder */
TF_TBL_TYPE_WC_FKB,
+ /** Meter Drop Counter */
+ TF_TBL_TYPE_METER_DROP_CNT,
/* External */
@@ -2194,6 +2196,8 @@ enum tf_global_config_type {
TF_TUNNEL_ENCAP, /**< Tunnel Encap Config(TECT) */
TF_ACTION_BLOCK, /**< Action Block Config(ABCR) */
TF_COUNTER_CFG, /**< Counter Configuration (CNTRS_CTRL) */
+ TF_METER_CFG, /**< Meter Config(ACTP4_FMTCR) */
+ TF_METER_INTERVAL_CFG, /**< Meter Interval Config(FMTCR_INTERVAL) */
TF_GLOBAL_CFG_TYPE_MAX
};
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c
index 808dcb1f77..a492c62bff 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.c
@@ -43,6 +43,7 @@ const char *tf_resource_str_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = {
[CFA_RESOURCE_TYPE_P58_EM_FKB] = "em_fkb ",
[CFA_RESOURCE_TYPE_P58_WC_FKB] = "wc_fkb ",
[CFA_RESOURCE_TYPE_P58_VEB_TCAM] = "veb ",
+ [CFA_RESOURCE_TYPE_P58_METADATA] = "metadata",
};
/**
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h
index 66b0f4e983..8c2e07aa34 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.h
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.h
@@ -75,10 +75,18 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER,
0, 0, 0
},
+ [TF_TBL_TYPE_METER_DROP_CNT] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT,
+ 0, 0, 0
+ },
[TF_TBL_TYPE_MIRROR_CONFIG] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR,
0, 0, 0
},
+ [TF_TBL_TYPE_METADATA] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA,
+ 0, 0, 0
+ },
/* Policy - ARs in bank 1 */
[TF_TBL_TYPE_FULL_ACT_RECORD] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
@@ -194,5 +202,11 @@ struct tf_global_cfg_cfg tf_global_cfg_p58[TF_GLOBAL_CFG_TYPE_MAX] = {
[TF_COUNTER_CFG] = {
TF_GLOBAL_CFG_CFG_HCAPI, TF_COUNTER_CFG
},
+ [TF_METER_CFG] = {
+ TF_GLOBAL_CFG_CFG_HCAPI, TF_METER_CFG
+ },
+ [TF_METER_INTERVAL_CFG] = {
+ TF_GLOBAL_CFG_CFG_HCAPI, TF_METER_INTERVAL_CFG
+ },
};
#endif /* _TF_DEVICE_P58_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c
index e77399c6bd..7011edcd78 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl.c
+++ b/drivers/net/bnxt/tf_core/tf_tbl.c
@@ -374,23 +374,28 @@ tf_tbl_set(struct tf *tfp,
}
}
- /* Verify that the entry has been previously allocated */
- aparms.rm_db = tbl_db->tbl_db[parms->dir];
- aparms.subtype = parms->type;
- TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift);
-
- aparms.allocated = &allocated;
- rc = tf_rm_is_allocated(&aparms);
- if (rc)
- return rc;
+ /* Do not check meter drop counter because it is not allocated
+ * resources
+ */
+ if (parms->type != TF_TBL_TYPE_METER_DROP_CNT) {
+ /* Verify that the entry has been previously allocated */
+ aparms.rm_db = tbl_db->tbl_db[parms->dir];
+ aparms.subtype = parms->type;
+ TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift);
+
+ aparms.allocated = &allocated;
+ rc = tf_rm_is_allocated(&aparms);
+ if (rc)
+ return rc;
- if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
- TFP_DRV_LOG(ERR,
- "%s, Invalid or not allocated index, type:%d, idx:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type,
- parms->idx);
- return -EINVAL;
+ if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
+ TFP_DRV_LOG(ERR,
+ "%s, Invalid or not allocated index, type:%d, idx:%d\n",
+ tf_dir_2_str(parms->dir),
+ parms->type,
+ parms->idx);
+ return -EINVAL;
+ }
}
/* Set the entry */
@@ -477,23 +482,28 @@ tf_tbl_get(struct tf *tfp,
}
}
- /* Verify that the entry has been previously allocated */
- aparms.rm_db = tbl_db->tbl_db[parms->dir];
- aparms.subtype = parms->type;
- TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift);
-
- aparms.allocated = &allocated;
- rc = tf_rm_is_allocated(&aparms);
- if (rc)
- return rc;
+ /* Do not check meter drop counter because it is not allocated
+ * resources.
+ */
+ if (parms->type != TF_TBL_TYPE_METER_DROP_CNT) {
+ /* Verify that the entry has been previously allocated */
+ aparms.rm_db = tbl_db->tbl_db[parms->dir];
+ aparms.subtype = parms->type;
+ TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift);
+
+ aparms.allocated = &allocated;
+ rc = tf_rm_is_allocated(&aparms);
+ if (rc)
+ return rc;
- if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
- TFP_DRV_LOG(ERR,
- "%s, Invalid or not allocated index, type:%d, idx:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type,
- parms->idx);
- return -EINVAL;
+ if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
+ TFP_DRV_LOG(ERR,
+ "%s, Invalid or not allocated index, type:%d, idx:%d\n",
+ tf_dir_2_str(parms->dir),
+ parms->type,
+ parms->idx);
+ return -EINVAL;
+ }
}
/* Set the entry */
diff --git a/drivers/net/bnxt/tf_core/tf_util.c b/drivers/net/bnxt/tf_core/tf_util.c
index e712816209..d100399d0a 100644
--- a/drivers/net/bnxt/tf_core/tf_util.c
+++ b/drivers/net/bnxt/tf_core/tf_util.c
@@ -112,6 +112,8 @@ tf_tbl_type_2_str(enum tf_tbl_type tbl_type)
return "WC Flexible Key Builder";
case TF_TBL_TYPE_EXT:
return "External";
+ case TF_TBL_TYPE_METER_DROP_CNT:
+ return "Meter drop counter";
default:
return "Invalid tbl type";
}
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v4 04/13] net/bnxt: add SRAM manager model
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 " Venkat Duvvuru
` (2 preceding siblings ...)
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 03/13] net/bnxt: add flow meter drop counter support Venkat Duvvuru
@ 2021-09-20 7:42 ` Venkat Duvvuru
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 05/13] net/bnxt: add flow template support for Thor Venkat Duvvuru
` (9 subsequent siblings)
13 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-20 7:42 UTC (permalink / raw)
To: dev; +Cc: Farah Smith
From: Farah Smith <farah.smith@broadcom.com>
The SRAM manager supports allocation and free of variable sized
records within SRAM memory. These record sizes are 8, 16, 32, or
64B. The SRAM manager algorithm will not fragment memory during
run time. Previous implementation only included fixed size 64B
records regardless of the size required.
Signed-off-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com>
Reviewed-by: Peter Spreadborough <peter.spreadborough@broadcom.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/tf_core/ll.c | 3 +
drivers/net/bnxt/tf_core/ll.h | 50 +-
drivers/net/bnxt/tf_core/meson.build | 2 +
drivers/net/bnxt/tf_core/tf_core.c | 104 ++-
drivers/net/bnxt/tf_core/tf_core.h | 48 +-
drivers/net/bnxt/tf_core/tf_device.c | 40 +-
drivers/net/bnxt/tf_core/tf_device.h | 133 ++-
drivers/net/bnxt/tf_core/tf_device_p4.c | 75 +-
drivers/net/bnxt/tf_core/tf_device_p4.h | 50 +-
drivers/net/bnxt/tf_core/tf_device_p58.c | 105 ++-
drivers/net/bnxt/tf_core/tf_device_p58.h | 60 +-
drivers/net/bnxt/tf_core/tf_msg.c | 2 +-
drivers/net/bnxt/tf_core/tf_rm.c | 46 +-
drivers/net/bnxt/tf_core/tf_rm.h | 62 +-
drivers/net/bnxt/tf_core/tf_session.c | 56 ++
drivers/net/bnxt/tf_core/tf_session.h | 58 +-
drivers/net/bnxt/tf_core/tf_sram_mgr.c | 971 ++++++++++++++++++++++
drivers/net/bnxt/tf_core/tf_sram_mgr.h | 317 +++++++
drivers/net/bnxt/tf_core/tf_tbl.c | 186 +----
drivers/net/bnxt/tf_core/tf_tbl.h | 15 +-
drivers/net/bnxt/tf_core/tf_tbl_sram.c | 713 ++++++++++++++++
drivers/net/bnxt/tf_core/tf_tbl_sram.h | 154 ++++
drivers/net/bnxt/tf_core/tf_tcam.c | 10 +-
drivers/net/bnxt/tf_core/tf_tcam.h | 7 +
drivers/net/bnxt/tf_core/tf_tcam_shared.c | 28 +-
drivers/net/bnxt/tf_core/tf_util.c | 10 +
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 23 +
27 files changed, 2976 insertions(+), 352 deletions(-)
create mode 100644 drivers/net/bnxt/tf_core/tf_sram_mgr.c
create mode 100644 drivers/net/bnxt/tf_core/tf_sram_mgr.h
create mode 100644 drivers/net/bnxt/tf_core/tf_tbl_sram.c
create mode 100644 drivers/net/bnxt/tf_core/tf_tbl_sram.h
diff --git a/drivers/net/bnxt/tf_core/ll.c b/drivers/net/bnxt/tf_core/ll.c
index cd168a7970..f2bdff6b9e 100644
--- a/drivers/net/bnxt/tf_core/ll.c
+++ b/drivers/net/bnxt/tf_core/ll.c
@@ -13,6 +13,7 @@ void ll_init(struct ll *ll)
{
ll->head = NULL;
ll->tail = NULL;
+ ll->cnt = 0;
}
/* insert entry in linked list */
@@ -30,6 +31,7 @@ void ll_insert(struct ll *ll,
entry->next->prev = entry;
ll->head = entry->next->prev;
}
+ ll->cnt++;
}
/* delete entry from linked list */
@@ -49,4 +51,5 @@ void ll_delete(struct ll *ll,
entry->prev->next = entry->next;
entry->next->prev = entry->prev;
}
+ ll->cnt--;
}
diff --git a/drivers/net/bnxt/tf_core/ll.h b/drivers/net/bnxt/tf_core/ll.h
index 239478b4f8..9cf8f64ec2 100644
--- a/drivers/net/bnxt/tf_core/ll.h
+++ b/drivers/net/bnxt/tf_core/ll.h
@@ -8,6 +8,8 @@
#ifndef _LL_H_
#define _LL_H_
+#include <stdint.h>
+
/* linked list entry */
struct ll_entry {
struct ll_entry *prev;
@@ -18,6 +20,7 @@ struct ll_entry {
struct ll {
struct ll_entry *head;
struct ll_entry *tail;
+ uint32_t cnt;
};
/**
@@ -28,7 +31,7 @@ struct ll {
void ll_init(struct ll *ll);
/**
- * Linked list insert
+ * Linked list insert head
*
* [in] ll, linked list where element is inserted
* [in] entry, entry to be added
@@ -43,4 +46,49 @@ void ll_insert(struct ll *ll, struct ll_entry *entry);
*/
void ll_delete(struct ll *ll, struct ll_entry *entry);
+/**
+ * Linked list return next entry without deleting it
+ *
+ * Useful in performing search
+ *
+ * [in] Entry in the list
+ */
+static inline struct ll_entry *ll_next(struct ll_entry *entry)
+{
+ return entry->next;
+}
+
+/**
+ * Linked list return the head of the list without removing it
+ *
+ * Useful in performing search
+ *
+ * [in] ll, linked list
+ */
+static inline struct ll_entry *ll_head(struct ll *ll)
+{
+ return ll->head;
+}
+
+/**
+ * Linked list return the tail of the list without removing it
+ *
+ * Useful in performing search
+ *
+ * [in] ll, linked list
+ */
+static inline struct ll_entry *ll_tail(struct ll *ll)
+{
+ return ll->tail;
+}
+
+/**
+ * Linked list return the number of entries in the list
+ *
+ * [in] ll, linked list
+ */
+static inline uint32_t ll_cnt(struct ll *ll)
+{
+ return ll->cnt;
+}
#endif /* _LL_H_ */
diff --git a/drivers/net/bnxt/tf_core/meson.build b/drivers/net/bnxt/tf_core/meson.build
index f28e77ec2e..206935d18a 100644
--- a/drivers/net/bnxt/tf_core/meson.build
+++ b/drivers/net/bnxt/tf_core/meson.build
@@ -16,6 +16,8 @@ sources += files(
'stack.c',
'tf_rm.c',
'tf_tbl.c',
+ 'tf_tbl_sram.c',
+ 'tf_sram_mgr.c',
'tf_em_common.c',
'tf_em_host.c',
'tf_em_internal.c',
diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c
index 5458f76e2d..936102c804 100644
--- a/drivers/net/bnxt/tf_core/tf_core.c
+++ b/drivers/net/bnxt/tf_core/tf_core.c
@@ -1079,17 +1079,16 @@ tf_alloc_tbl_entry(struct tf *tfp,
strerror(-rc));
return rc;
}
-
- } else {
- if (dev->ops->tf_dev_alloc_tbl == NULL) {
- rc = -EOPNOTSUPP;
+ } else if (dev->ops->tf_dev_is_sram_managed(tfp, parms->type)) {
+ rc = dev->ops->tf_dev_alloc_sram_tbl(tfp, &aparms);
+ if (rc) {
TFP_DRV_LOG(ERR,
- "%s: Operation not supported, rc:%s\n",
+ "%s: SRAM table allocation failed, rc:%s\n",
tf_dir_2_str(parms->dir),
strerror(-rc));
- return -EOPNOTSUPP;
+ return rc;
}
-
+ } else {
rc = dev->ops->tf_dev_alloc_tbl(tfp, &aparms);
if (rc) {
TFP_DRV_LOG(ERR,
@@ -1162,15 +1161,16 @@ tf_free_tbl_entry(struct tf *tfp,
strerror(-rc));
return rc;
}
- } else {
- if (dev->ops->tf_dev_free_tbl == NULL) {
- rc = -EOPNOTSUPP;
+ } else if (dev->ops->tf_dev_is_sram_managed(tfp, parms->type)) {
+ rc = dev->ops->tf_dev_free_sram_tbl(tfp, &fparms);
+ if (rc) {
TFP_DRV_LOG(ERR,
- "%s: Operation not supported, rc:%s\n",
+ "%s: SRAM table free failed, rc:%s\n",
tf_dir_2_str(parms->dir),
strerror(-rc));
- return -EOPNOTSUPP;
+ return rc;
}
+ } else {
rc = dev->ops->tf_dev_free_tbl(tfp, &fparms);
if (rc) {
@@ -1181,7 +1181,6 @@ tf_free_tbl_entry(struct tf *tfp,
return rc;
}
}
-
return 0;
}
@@ -1244,6 +1243,15 @@ tf_set_tbl_entry(struct tf *tfp,
strerror(-rc));
return rc;
}
+ } else if (dev->ops->tf_dev_is_sram_managed(tfp, parms->type)) {
+ rc = dev->ops->tf_dev_set_sram_tbl(tfp, &sparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: SRAM table set failed, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ strerror(-rc));
+ return rc;
+ }
} else {
if (dev->ops->tf_dev_set_tbl == NULL) {
rc = -EOPNOTSUPP;
@@ -1300,28 +1308,39 @@ tf_get_tbl_entry(struct tf *tfp,
strerror(-rc));
return rc;
}
-
- if (dev->ops->tf_dev_get_tbl == NULL) {
- rc = -EOPNOTSUPP;
- TFP_DRV_LOG(ERR,
- "%s: Operation not supported, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(-rc));
- return -EOPNOTSUPP;
- }
-
gparms.dir = parms->dir;
gparms.type = parms->type;
gparms.data = parms->data;
gparms.data_sz_in_bytes = parms->data_sz_in_bytes;
gparms.idx = parms->idx;
- rc = dev->ops->tf_dev_get_tbl(tfp, &gparms);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Table get failed, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(-rc));
- return rc;
+
+ if (dev->ops->tf_dev_is_sram_managed(tfp, parms->type)) {
+ rc = dev->ops->tf_dev_get_sram_tbl(tfp, &gparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: SRAM table get failed, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ strerror(-rc));
+ return rc;
+ }
+ } else {
+ if (dev->ops->tf_dev_get_tbl == NULL) {
+ rc = -EOPNOTSUPP;
+ TFP_DRV_LOG(ERR,
+ "%s: Operation not supported, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ strerror(-rc));
+ return -EOPNOTSUPP;
+ }
+
+ rc = dev->ops->tf_dev_get_tbl(tfp, &gparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Table get failed, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ strerror(-rc));
+ return rc;
+ }
}
return rc;
@@ -1361,6 +1380,13 @@ tf_bulk_get_tbl_entry(struct tf *tfp,
return rc;
}
+ bparms.dir = parms->dir;
+ bparms.type = parms->type;
+ bparms.starting_idx = parms->starting_idx;
+ bparms.num_entries = parms->num_entries;
+ bparms.entry_sz_in_bytes = parms->entry_sz_in_bytes;
+ bparms.physical_mem_addr = parms->physical_mem_addr;
+
if (parms->type == TF_TBL_TYPE_EXT) {
/* Not supported, yet */
rc = -EOPNOTSUPP;
@@ -1370,10 +1396,17 @@ tf_bulk_get_tbl_entry(struct tf *tfp,
strerror(-rc));
return rc;
+ } else if (dev->ops->tf_dev_is_sram_managed(tfp, parms->type)) {
+ rc = dev->ops->tf_dev_get_bulk_sram_tbl(tfp, &bparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: SRAM table bulk get failed, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ strerror(-rc));
+ }
+ return rc;
}
- /* Internal table type processing */
-
if (dev->ops->tf_dev_get_bulk_tbl == NULL) {
rc = -EOPNOTSUPP;
TFP_DRV_LOG(ERR,
@@ -1383,12 +1416,6 @@ tf_bulk_get_tbl_entry(struct tf *tfp,
return -EOPNOTSUPP;
}
- bparms.dir = parms->dir;
- bparms.type = parms->type;
- bparms.starting_idx = parms->starting_idx;
- bparms.num_entries = parms->num_entries;
- bparms.entry_sz_in_bytes = parms->entry_sz_in_bytes;
- bparms.physical_mem_addr = parms->physical_mem_addr;
rc = dev->ops->tf_dev_get_bulk_tbl(tfp, &bparms);
if (rc) {
TFP_DRV_LOG(ERR,
@@ -1397,7 +1424,6 @@ tf_bulk_get_tbl_entry(struct tf *tfp,
strerror(-rc));
return rc;
}
-
return rc;
}
diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h
index af8d13bd7e..fb02c2b161 100644
--- a/drivers/net/bnxt/tf_core/tf_core.h
+++ b/drivers/net/bnxt/tf_core/tf_core.h
@@ -65,6 +65,16 @@ enum tf_ext_mem_chan_type {
TF_EXT_MEM_CHAN_TYPE_MAX
};
+/**
+ * WC TCAM number of slice per row that devices supported
+ */
+enum tf_wc_num_slice {
+ TF_WC_TCAM_1_SLICE_PER_ROW = 1,
+ TF_WC_TCAM_2_SLICE_PER_ROW = 2,
+ TF_WC_TCAM_4_SLICE_PER_ROW = 4,
+ TF_WC_TCAM_8_SLICE_PER_ROW = 8,
+};
+
/**
* EEM record AR helper
*
@@ -670,6 +680,13 @@ struct tf_open_session_parms {
*/
void *bp;
+ /**
+ * [in]
+ *
+ * The number of slices per row for WC TCAM entry.
+ */
+ enum tf_wc_num_slice wc_num_slices;
+
/**
* [out] shared_session_creator
*
@@ -734,8 +751,6 @@ int tf_open_session(struct tf *tfp,
/**
* General internal resource info
*
- * TODO: remove tf_rm_new_entry structure and use this structure
- * internally.
*/
struct tf_resource_info {
uint16_t start;
@@ -1656,12 +1671,7 @@ struct tf_alloc_tbl_entry_parms {
* entry of the indicated type for this TruFlow session.
*
* Allocates an index table record. This function will attempt to
- * allocate an entry or search an index table for a matching entry if
- * search is enabled (only the shadow copy of the table is accessed).
- *
- * If search is not enabled, the first available free entry is
- * returned. If search is enabled and a matching entry to entry_data
- * is found hit is set to TRUE and success is returned.
+ * allocate an index table entry.
*
* External types:
*
@@ -1670,8 +1680,8 @@ struct tf_alloc_tbl_entry_parms {
* Allocates an external index table action record.
*
* NOTE:
- * Implementation of the internals of this function will be a stack with push
- * and pop.
+ * Implementation of the internals of the external function will be a stack with
+ * push and pop.
*
* Returns success or failure code.
*/
@@ -1707,20 +1717,15 @@ struct tf_free_tbl_entry_parms {
*
* Internal types:
*
- * If session has shadow_copy enabled the shadow DB is searched and if
- * found the element ref_cnt is decremented. If ref_cnt goes to
- * zero then the element is returned to the session pool.
- *
- * If the session does not have a shadow DB the element is free'ed and
- * given back to the session pool.
+ * The element is freed and given back to the session pool.
*
* External types:
*
- * Free's an external index table action record.
+ * Frees an external index table action record.
*
* NOTE:
- * Implementation of the internals of this function will be a stack with push
- * and pop.
+ * Implementation of the internals of the external table will be a stack with
+ * push and pop.
*
* Returns success or failure code.
*/
@@ -1764,9 +1769,8 @@ struct tf_set_tbl_entry_parms {
/**
* set index table entry
*
- * Used to insert an application programmed index table entry into a
- * previous allocated table location. A shadow copy of the table
- * is maintained (if enabled) (only for internal objects)
+ * Used to set an application programmed index table entry into a
+ * previous allocated table location.
*
* Returns success or failure code.
*/
diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c
index 498e668b16..25a7166bbb 100644
--- a/drivers/net/bnxt/tf_core/tf_device.c
+++ b/drivers/net/bnxt/tf_core/tf_device.c
@@ -11,10 +11,14 @@
#include "tf_rm.h"
#ifdef TF_TCAM_SHARED
#include "tf_tcam_shared.h"
+#include "tf_tbl_sram.h"
#endif /* TF_TCAM_SHARED */
struct tf;
+/* Number of slices per row for WC TCAM */
+uint16_t g_wc_num_slices_per_row = TF_WC_TCAM_1_SLICE_PER_ROW;
+
/* Forward declarations */
static int tf_dev_unbind_p4(struct tf *tfp);
static int tf_dev_unbind_p58(struct tf *tfp);
@@ -83,7 +87,8 @@ static int
tf_dev_bind_p4(struct tf *tfp,
bool shadow_copy,
struct tf_session_resources *resources,
- struct tf_dev_info *dev_handle)
+ struct tf_dev_info *dev_handle,
+ enum tf_wc_num_slice wc_num_slices)
{
int rc;
int frc;
@@ -131,7 +136,6 @@ tf_dev_bind_p4(struct tf *tfp,
if (rsv_cnt) {
tbl_cfg.num_elements = TF_TBL_TYPE_MAX;
tbl_cfg.cfg = tf_tbl_p4;
- tbl_cfg.shadow_copy = shadow_copy;
tbl_cfg.resources = resources;
rc = tf_tbl_bind(tfp, &tbl_cfg);
if (rc) {
@@ -151,6 +155,7 @@ tf_dev_bind_p4(struct tf *tfp,
tcam_cfg.cfg = tf_tcam_p4;
tcam_cfg.shadow_copy = shadow_copy;
tcam_cfg.resources = resources;
+ tcam_cfg.wc_num_slices = wc_num_slices;
#ifdef TF_TCAM_SHARED
rc = tf_tcam_shared_bind(tfp, &tcam_cfg);
#else /* !TF_TCAM_SHARED */
@@ -369,7 +374,8 @@ static int
tf_dev_bind_p58(struct tf *tfp,
bool shadow_copy,
struct tf_session_resources *resources,
- struct tf_dev_info *dev_handle)
+ struct tf_dev_info *dev_handle,
+ enum tf_wc_num_slice wc_num_slices)
{
int rc;
int frc;
@@ -414,7 +420,6 @@ tf_dev_bind_p58(struct tf *tfp,
if (rsv_cnt) {
tbl_cfg.num_elements = TF_TBL_TYPE_MAX;
tbl_cfg.cfg = tf_tbl_p58;
- tbl_cfg.shadow_copy = shadow_copy;
tbl_cfg.resources = resources;
rc = tf_tbl_bind(tfp, &tbl_cfg);
if (rc) {
@@ -423,6 +428,13 @@ tf_dev_bind_p58(struct tf *tfp,
goto fail;
}
no_rsv_flag = false;
+
+ rc = tf_tbl_sram_bind(tfp);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "SRAM table initialization failure\n");
+ goto fail;
+ }
}
rsv_cnt = tf_dev_reservation_check(TF_TCAM_TBL_TYPE_MAX,
@@ -433,6 +445,7 @@ tf_dev_bind_p58(struct tf *tfp,
tcam_cfg.cfg = tf_tcam_p58;
tcam_cfg.shadow_copy = shadow_copy;
tcam_cfg.resources = resources;
+ tcam_cfg.wc_num_slices = wc_num_slices;
#ifdef TF_TCAM_SHARED
rc = tf_tcam_shared_bind(tfp, &tcam_cfg);
#else /* !TF_TCAM_SHARED */
@@ -565,6 +578,18 @@ tf_dev_unbind_p58(struct tf *tfp)
fail = true;
}
+ /* Unbind the SRAM table prior to table as the table manager
+ * owns and frees the table DB while the SRAM table manager owns
+ * and manages it's internal data structures. SRAM table manager
+ * relies on the table rm_db to exist.
+ */
+ rc = tf_tbl_sram_unbind(tfp);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Device unbind failed, SRAM table\n");
+ fail = true;
+ }
+
rc = tf_tbl_unbind(tfp);
if (rc) {
TFP_DRV_LOG(INFO,
@@ -606,6 +631,7 @@ tf_dev_bind(struct tf *tfp __rte_unused,
enum tf_device_type type,
bool shadow_copy,
struct tf_session_resources *resources,
+ uint16_t wc_num_slices,
struct tf_dev_info *dev_handle)
{
switch (type) {
@@ -615,13 +641,15 @@ tf_dev_bind(struct tf *tfp __rte_unused,
return tf_dev_bind_p4(tfp,
shadow_copy,
resources,
- dev_handle);
+ dev_handle,
+ wc_num_slices);
case TF_DEVICE_TYPE_THOR:
dev_handle->type = type;
return tf_dev_bind_p58(tfp,
shadow_copy,
resources,
- dev_handle);
+ dev_handle,
+ wc_num_slices);
default:
TFP_DRV_LOG(ERR,
"No such device\n");
diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h
index b43cfc6925..9b0c037db0 100644
--- a/drivers/net/bnxt/tf_core/tf_device.h
+++ b/drivers/net/bnxt/tf_core/tf_device.h
@@ -57,6 +57,9 @@ struct tf_dev_info {
* [in] resources
* Pointer to resource allocation information
*
+ * [in] wc_num_slices
+ * Number of slices per row for WC
+ *
* [out] dev_handle
* Device handle
*
@@ -69,6 +72,7 @@ int tf_dev_bind(struct tf *tfp,
enum tf_device_type type,
bool shadow_copy,
struct tf_session_resources *resources,
+ uint16_t wc_num_slices,
struct tf_dev_info *dev_handle);
/**
@@ -139,6 +143,23 @@ struct tf_dev_ops {
uint16_t resource_id,
const char **resource_str);
+ /**
+ * Set the WC TCAM slice information that the device
+ * supports.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] num_slices_per_row
+ * Number of slices per row the device supports
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+ int (*tf_dev_set_tcam_slice_info)(struct tf *tfp,
+ enum tf_wc_num_slice num_slices_per_row);
+
/**
* Retrieves the WC TCAM slice information that the device
* supports.
@@ -241,6 +262,22 @@ struct tf_dev_ops {
int (*tf_dev_get_ident_resc_info)(struct tf *tfp,
struct tf_identifier_resource_info *parms);
+ /**
+ * Indicates whether the index table type is SRAM managed
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] type
+ * Truflow index table type, e.g. TF_TYPE_FULL_ACT_RECORD
+ *
+ * Returns
+ * - (0) if the table is not managed by the SRAM manager
+ * - (1) if the table is managed by the SRAM manager
+ */
+ bool (*tf_dev_is_sram_managed)(struct tf *tfp,
+ enum tf_tbl_type tbl_type);
+
/**
* Get SRAM table information.
*
@@ -289,6 +326,25 @@ struct tf_dev_ops {
int (*tf_dev_alloc_tbl)(struct tf *tfp,
struct tf_tbl_alloc_parms *parms);
+ /**
+ * Allocation of an SRAM index table type element.
+ *
+ * This API allocates the specified table type element from a
+ * device specific table type DB. The allocated element is
+ * returned.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] parms
+ * Pointer to table allocation parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+ int (*tf_dev_alloc_sram_tbl)(struct tf *tfp,
+ struct tf_tbl_alloc_parms *parms);
/**
* Allocation of a external table type element.
*
@@ -327,7 +383,24 @@ struct tf_dev_ops {
*/
int (*tf_dev_free_tbl)(struct tf *tfp,
struct tf_tbl_free_parms *parms);
-
+ /**
+ * Free of an SRAM table type element.
+ *
+ * This API free's a previous allocated table type element from a
+ * device specific table type DB.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] parms
+ * Pointer to table free parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+ int (*tf_dev_free_sram_tbl)(struct tf *tfp,
+ struct tf_tbl_free_parms *parms);
/**
* Free of a external table type element.
*
@@ -385,6 +458,25 @@ struct tf_dev_ops {
int (*tf_dev_set_ext_tbl)(struct tf *tfp,
struct tf_tbl_set_parms *parms);
+ /**
+ * Sets the specified SRAM table type element.
+ *
+ * This API sets the specified element data by invoking the
+ * firmware.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] parms
+ * Pointer to table set parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+ int (*tf_dev_set_sram_tbl)(struct tf *tfp,
+ struct tf_tbl_set_parms *parms);
+
/**
* Retrieves the specified table type element.
*
@@ -404,6 +496,25 @@ struct tf_dev_ops {
int (*tf_dev_get_tbl)(struct tf *tfp,
struct tf_tbl_get_parms *parms);
+ /**
+ * Retrieves the specified SRAM table type element.
+ *
+ * This API retrieves the specified element data by invoking the
+ * firmware.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] parms
+ * Pointer to table get parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+ int (*tf_dev_get_sram_tbl)(struct tf *tfp,
+ struct tf_tbl_get_parms *parms);
+
/**
* Retrieves the specified table type element using 'bulk'
* mechanism.
@@ -424,6 +535,26 @@ struct tf_dev_ops {
int (*tf_dev_get_bulk_tbl)(struct tf *tfp,
struct tf_tbl_get_bulk_parms *parms);
+ /**
+ * Retrieves the specified SRAM table type element using 'bulk'
+ * mechanism.
+ *
+ * This API retrieves the specified element data by invoking the
+ * firmware.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] parms
+ * Pointer to table get bulk parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+ int (*tf_dev_get_bulk_sram_tbl)(struct tf *tfp,
+ struct tf_tbl_get_bulk_parms *parms);
+
/**
* Gets the increment value to add to the shared session resource
* start offset by for each count in the "stride"
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c
index 2e7ccec123..826cd0cdbc 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.c
@@ -118,14 +118,48 @@ tf_dev_p4_get_resource_str(struct tf *tfp __rte_unused,
}
/**
- * Device specific function that retrieves the WC TCAM slices the
+ * Device specific function that set the WC TCAM slices the
* device supports.
*
* [in] tfp
* Pointer to TF handle
*
- * [out] slice_size
- * Pointer to the WC TCAM slice size
+ * [in] num_slices_per_row
+ * The WC TCAM row slice configuration
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+static int
+tf_dev_p4_set_tcam_slice_info(struct tf *tfp __rte_unused,
+ enum tf_wc_num_slice num_slices_per_row)
+{
+ switch (num_slices_per_row) {
+ case TF_WC_TCAM_1_SLICE_PER_ROW:
+ case TF_WC_TCAM_2_SLICE_PER_ROW:
+ case TF_WC_TCAM_4_SLICE_PER_ROW:
+ g_wc_num_slices_per_row = num_slices_per_row;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/**
+ * Device specific function that retrieves the TCAM slices the
+ * device supports.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] type
+ * TF TCAM type
+ *
+ * [in] key_sz
+ * The key size
*
* [out] num_slices_per_row
* Pointer to the WC TCAM row slice configuration
@@ -141,11 +175,10 @@ tf_dev_p4_get_tcam_slice_info(struct tf *tfp __rte_unused,
uint16_t *num_slices_per_row)
{
/* Single slice support */
-#define CFA_P4_WC_TCAM_SLICES_PER_ROW 1
#define CFA_P4_WC_TCAM_SLICE_SIZE 12
if (type == TF_TCAM_TBL_TYPE_WC_TCAM) {
- *num_slices_per_row = CFA_P4_WC_TCAM_SLICES_PER_ROW;
+ *num_slices_per_row = g_wc_num_slices_per_row;
if (key_sz > *num_slices_per_row * CFA_P4_WC_TCAM_SLICE_SIZE)
return -ENOTSUP;
} else { /* for other type of tcam */
@@ -220,26 +253,51 @@ static int tf_dev_p4_word_align(uint16_t size)
return ((((size) + 31) >> 5) * 4);
}
+/**
+ * Indicates whether the index table type is SRAM managed
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] type
+ * Truflow index table type, e.g. TF_TYPE_FULL_ACT_RECORD
+ *
+ * Returns
+ * - (0) if the table is not managed by the SRAM manager
+ * - (1) if the table is managed by the SRAM manager
+ */
+static bool tf_dev_p4_is_sram_managed(struct tf *tfp __rte_unused,
+ enum tf_tbl_type type __rte_unused)
+{
+ return false;
+}
/**
* Truflow P4 device specific functions
*/
const struct tf_dev_ops tf_dev_ops_p4_init = {
.tf_dev_get_max_types = tf_dev_p4_get_max_types,
.tf_dev_get_resource_str = tf_dev_p4_get_resource_str,
+ .tf_dev_set_tcam_slice_info = tf_dev_p4_set_tcam_slice_info,
.tf_dev_get_tcam_slice_info = tf_dev_p4_get_tcam_slice_info,
.tf_dev_alloc_ident = NULL,
.tf_dev_free_ident = NULL,
.tf_dev_search_ident = NULL,
.tf_dev_get_ident_resc_info = NULL,
.tf_dev_get_tbl_info = NULL,
+ .tf_dev_is_sram_managed = tf_dev_p4_is_sram_managed,
.tf_dev_alloc_ext_tbl = NULL,
.tf_dev_alloc_tbl = NULL,
+ .tf_dev_alloc_sram_tbl = NULL,
.tf_dev_free_ext_tbl = NULL,
.tf_dev_free_tbl = NULL,
+ .tf_dev_free_sram_tbl = NULL,
.tf_dev_set_tbl = NULL,
.tf_dev_set_ext_tbl = NULL,
+ .tf_dev_set_sram_tbl = NULL,
.tf_dev_get_tbl = NULL,
+ .tf_dev_get_sram_tbl = NULL,
.tf_dev_get_bulk_tbl = NULL,
+ .tf_dev_get_bulk_sram_tbl = NULL,
.tf_dev_get_shared_tbl_increment = tf_dev_p4_get_shared_tbl_increment,
.tf_dev_get_tbl_resc_info = NULL,
.tf_dev_alloc_tcam = NULL,
@@ -271,20 +329,27 @@ const struct tf_dev_ops tf_dev_ops_p4_init = {
const struct tf_dev_ops tf_dev_ops_p4 = {
.tf_dev_get_max_types = tf_dev_p4_get_max_types,
.tf_dev_get_resource_str = tf_dev_p4_get_resource_str,
+ .tf_dev_set_tcam_slice_info = tf_dev_p4_set_tcam_slice_info,
.tf_dev_get_tcam_slice_info = tf_dev_p4_get_tcam_slice_info,
.tf_dev_alloc_ident = tf_ident_alloc,
.tf_dev_free_ident = tf_ident_free,
.tf_dev_search_ident = tf_ident_search,
.tf_dev_get_ident_resc_info = tf_ident_get_resc_info,
.tf_dev_get_tbl_info = NULL,
+ .tf_dev_is_sram_managed = tf_dev_p4_is_sram_managed,
.tf_dev_alloc_tbl = tf_tbl_alloc,
.tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc,
+ .tf_dev_alloc_sram_tbl = tf_tbl_alloc,
.tf_dev_free_tbl = tf_tbl_free,
.tf_dev_free_ext_tbl = tf_tbl_ext_free,
+ .tf_dev_free_sram_tbl = tf_tbl_free,
.tf_dev_set_tbl = tf_tbl_set,
.tf_dev_set_ext_tbl = tf_tbl_ext_common_set,
+ .tf_dev_set_sram_tbl = NULL,
.tf_dev_get_tbl = tf_tbl_get,
+ .tf_dev_get_sram_tbl = NULL,
.tf_dev_get_bulk_tbl = tf_tbl_bulk_get,
+ .tf_dev_get_bulk_sram_tbl = NULL,
.tf_dev_get_shared_tbl_increment = tf_dev_p4_get_shared_tbl_increment,
.tf_dev_get_tbl_resc_info = tf_tbl_get_resc_info,
#ifdef TF_TCAM_SHARED
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h
index a73ba3cd70..c1357913f1 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.h
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.h
@@ -15,101 +15,101 @@
struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = {
[TF_IDENT_TYPE_L2_CTXT_HIGH] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_L2_CTXT_LOW] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_PROF_FUNC] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_FUNC,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_WC_PROF] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_EM_PROF] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_EM_PROF_ID,
- 0, 0, 0
+ 0, 0
},
};
struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = {
[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_PROF_TCAM] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_TCAM,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_WC_TCAM] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_SP_TCAM] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_TCAM,
- 0, 0, 0
+ 0, 0
},
};
struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = {
[TF_TBL_TYPE_FULL_ACT_RECORD] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_MCAST_GROUPS] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_ENCAP_8B] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_ENCAP_16B] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_ENCAP_64B] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_SP_SMAC] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_STATS_64] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_ACT_MODIFY_IPV4] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_METER_PROF] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_METER_INST] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_MIRROR_CONFIG] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR,
- 0, 0, 0
+ 0, 0
},
};
@@ -117,14 +117,14 @@ struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = {
struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = {
[TF_EM_TBL_TYPE_TBL_SCOPE] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_TBL_SCOPE,
- 0, 0, 0
+ 0, 0
},
};
struct tf_rm_element_cfg tf_em_int_p4[TF_EM_TBL_TYPE_MAX] = {
[TF_EM_TBL_TYPE_EM_RECORD] = {
TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_EM_REC,
- 0, 0, 0
+ 0, 0
},
};
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c
index a492c62bff..47d7836a58 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.c
@@ -17,6 +17,7 @@
#include "tf_if_tbl.h"
#include "tfp.h"
#include "tf_msg_common.h"
+#include "tf_tbl_sram.h"
#define TF_DEV_P58_PARIF_MAX 16
#define TF_DEV_P58_PF_MASK 0xfUL
@@ -105,14 +106,48 @@ tf_dev_p58_get_resource_str(struct tf *tfp __rte_unused,
}
/**
- * Device specific function that retrieves the WC TCAM slices the
+ * Device specific function that set the WC TCAM slices the
* device supports.
*
* [in] tfp
* Pointer to TF handle
*
- * [out] slice_size
- * Pointer to the WC TCAM slice size
+ * [in] num_slices_per_row
+ * The WC TCAM row slice configuration
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+static int
+tf_dev_p58_set_tcam_slice_info(struct tf *tfp __rte_unused,
+ enum tf_wc_num_slice num_slices_per_row)
+{
+ switch (num_slices_per_row) {
+ case TF_WC_TCAM_1_SLICE_PER_ROW:
+ case TF_WC_TCAM_2_SLICE_PER_ROW:
+ case TF_WC_TCAM_4_SLICE_PER_ROW:
+ g_wc_num_slices_per_row = num_slices_per_row;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/**
+ * Device specific function that retrieves the TCAM slices the
+ * device supports.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] type
+ * TF TCAM type
+ *
+ * [in] key_sz
+ * The key size
*
* [out] num_slices_per_row
* Pointer to the WC TCAM row slice configuration
@@ -123,16 +158,13 @@ tf_dev_p58_get_resource_str(struct tf *tfp __rte_unused,
*/
static int
tf_dev_p58_get_tcam_slice_info(struct tf *tfp __rte_unused,
- enum tf_tcam_tbl_type type,
- uint16_t key_sz,
- uint16_t *num_slices_per_row)
+ enum tf_tcam_tbl_type type,
+ uint16_t key_sz,
+ uint16_t *num_slices_per_row)
{
-#define CFA_P58_WC_TCAM_SLICES_PER_ROW 1
#define CFA_P58_WC_TCAM_SLICE_SIZE 24
-
if (type == TF_TCAM_TBL_TYPE_WC_TCAM) {
- /* only support single slice key size now */
- *num_slices_per_row = CFA_P58_WC_TCAM_SLICES_PER_ROW;
+ *num_slices_per_row = g_wc_num_slices_per_row;
if (key_sz > *num_slices_per_row * CFA_P58_WC_TCAM_SLICE_SIZE)
return -ENOTSUP;
} else { /* for other type of tcam */
@@ -194,6 +226,44 @@ static int tf_dev_p58_get_shared_tbl_increment(struct tf *tfp __rte_unused,
return 0;
}
+/**
+ * Indicates whether the index table type is SRAM managed
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] type
+ * Truflow index table type, e.g. TF_TYPE_FULL_ACT_RECORD
+ *
+ * Returns
+ * - (0) if the table is not managed by the SRAM manager
+ * - (1) if the table is managed by the SRAM manager
+ */
+static bool tf_dev_p58_is_sram_managed(struct tf *tfp __rte_unused,
+ enum tf_tbl_type type)
+{
+ switch (type) {
+ case TF_TBL_TYPE_FULL_ACT_RECORD:
+ case TF_TBL_TYPE_COMPACT_ACT_RECORD:
+ case TF_TBL_TYPE_ACT_ENCAP_8B:
+ case TF_TBL_TYPE_ACT_ENCAP_16B:
+ case TF_TBL_TYPE_ACT_ENCAP_32B:
+ case TF_TBL_TYPE_ACT_ENCAP_64B:
+ case TF_TBL_TYPE_ACT_SP_SMAC:
+ case TF_TBL_TYPE_ACT_SP_SMAC_IPV4:
+ case TF_TBL_TYPE_ACT_SP_SMAC_IPV6:
+ case TF_TBL_TYPE_ACT_STATS_64:
+ case TF_TBL_TYPE_ACT_MODIFY_IPV4:
+ case TF_TBL_TYPE_ACT_MODIFY_8B:
+ case TF_TBL_TYPE_ACT_MODIFY_16B:
+ case TF_TBL_TYPE_ACT_MODIFY_32B:
+ case TF_TBL_TYPE_ACT_MODIFY_64B:
+ return true;
+ default:
+ return false;
+ }
+}
+
#define TF_DEV_P58_BANK_SZ_64B 2048
/**
* Get SRAM table information.
@@ -265,26 +335,34 @@ static int tf_dev_p58_get_sram_tbl_info(struct tf *tfp __rte_unused,
}
return 0;
}
+
/**
* Truflow P58 device specific functions
*/
const struct tf_dev_ops tf_dev_ops_p58_init = {
.tf_dev_get_max_types = tf_dev_p58_get_max_types,
.tf_dev_get_resource_str = tf_dev_p58_get_resource_str,
+ .tf_dev_set_tcam_slice_info = tf_dev_p58_set_tcam_slice_info,
.tf_dev_get_tcam_slice_info = tf_dev_p58_get_tcam_slice_info,
.tf_dev_alloc_ident = NULL,
.tf_dev_free_ident = NULL,
.tf_dev_search_ident = NULL,
.tf_dev_get_ident_resc_info = NULL,
.tf_dev_get_tbl_info = NULL,
+ .tf_dev_is_sram_managed = tf_dev_p58_is_sram_managed,
.tf_dev_alloc_ext_tbl = NULL,
.tf_dev_alloc_tbl = NULL,
+ .tf_dev_alloc_sram_tbl = NULL,
.tf_dev_free_ext_tbl = NULL,
.tf_dev_free_tbl = NULL,
+ .tf_dev_free_sram_tbl = NULL,
.tf_dev_set_tbl = NULL,
.tf_dev_set_ext_tbl = NULL,
+ .tf_dev_set_sram_tbl = NULL,
.tf_dev_get_tbl = NULL,
+ .tf_dev_get_sram_tbl = NULL,
.tf_dev_get_bulk_tbl = NULL,
+ .tf_dev_get_bulk_sram_tbl = NULL,
.tf_dev_get_shared_tbl_increment = tf_dev_p58_get_shared_tbl_increment,
.tf_dev_get_tbl_resc_info = NULL,
.tf_dev_alloc_tcam = NULL,
@@ -316,20 +394,27 @@ const struct tf_dev_ops tf_dev_ops_p58_init = {
const struct tf_dev_ops tf_dev_ops_p58 = {
.tf_dev_get_max_types = tf_dev_p58_get_max_types,
.tf_dev_get_resource_str = tf_dev_p58_get_resource_str,
+ .tf_dev_set_tcam_slice_info = tf_dev_p58_set_tcam_slice_info,
.tf_dev_get_tcam_slice_info = tf_dev_p58_get_tcam_slice_info,
.tf_dev_alloc_ident = tf_ident_alloc,
.tf_dev_free_ident = tf_ident_free,
.tf_dev_search_ident = tf_ident_search,
.tf_dev_get_ident_resc_info = tf_ident_get_resc_info,
+ .tf_dev_is_sram_managed = tf_dev_p58_is_sram_managed,
.tf_dev_get_tbl_info = tf_dev_p58_get_sram_tbl_info,
.tf_dev_alloc_tbl = tf_tbl_alloc,
+ .tf_dev_alloc_sram_tbl = tf_tbl_sram_alloc,
.tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc,
.tf_dev_free_tbl = tf_tbl_free,
.tf_dev_free_ext_tbl = tf_tbl_ext_free,
+ .tf_dev_free_sram_tbl = tf_tbl_sram_free,
.tf_dev_set_tbl = tf_tbl_set,
.tf_dev_set_ext_tbl = tf_tbl_ext_common_set,
+ .tf_dev_set_sram_tbl = tf_tbl_sram_set,
.tf_dev_get_tbl = tf_tbl_get,
+ .tf_dev_get_sram_tbl = tf_tbl_sram_get,
.tf_dev_get_bulk_tbl = tf_tbl_bulk_get,
+ .tf_dev_get_bulk_sram_tbl = tf_tbl_sram_bulk_get,
.tf_dev_get_shared_tbl_increment = tf_dev_p58_get_shared_tbl_increment,
.tf_dev_get_tbl_resc_info = tf_tbl_get_resc_info,
#ifdef TF_TCAM_SHARED
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h
index 8c2e07aa34..3e8759f2df 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.h
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.h
@@ -15,107 +15,107 @@
struct tf_rm_element_cfg tf_ident_p58[TF_IDENT_TYPE_MAX] = {
[TF_IDENT_TYPE_L2_CTXT_HIGH] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_L2_CTXT_LOW] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_PROF_FUNC] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_PROF_FUNC,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_WC_PROF] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID,
- 0, 0, 0
+ 0, 0
},
[TF_IDENT_TYPE_EM_PROF] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_PROF_ID,
- 0, 0, 0
+ 0, 0
},
};
struct tf_rm_element_cfg tf_tcam_p58[TF_TCAM_TBL_TYPE_MAX] = {
[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_PROF_TCAM] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_PROF_TCAM,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_WC_TCAM] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_TCAM,
- 0, 0, 0
+ 0, 0
},
[TF_TCAM_TBL_TYPE_VEB_TCAM] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_VEB_TCAM,
- 0, 0, 0
+ 0, 0
},
};
struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = {
[TF_TBL_TYPE_EM_FKB] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_WC_FKB] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_METER_PROF] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_METER_INST] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_METER_DROP_CNT] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_MIRROR_CONFIG] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR,
- 0, 0, 0
+ 0, 0
},
[TF_TBL_TYPE_METADATA] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA,
- 0, 0, 0
+ 0, 0
},
/* Policy - ARs in bank 1 */
[TF_TBL_TYPE_FULL_ACT_RECORD] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
- .slices = 1,
+ .slices = 4,
},
[TF_TBL_TYPE_COMPACT_ACT_RECORD] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
- .slices = 1,
+ .slices = 8,
},
/* Policy - Encaps in bank 2 */
[TF_TBL_TYPE_ACT_ENCAP_8B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 1,
+ .slices = 8,
},
[TF_TBL_TYPE_ACT_ENCAP_16B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 1,
+ .slices = 4,
},
[TF_TBL_TYPE_ACT_ENCAP_32B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 1,
+ .slices = 2,
},
[TF_TBL_TYPE_ACT_ENCAP_64B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
@@ -128,19 +128,19 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 1,
+ .slices = 8,
},
[TF_TBL_TYPE_ACT_MODIFY_16B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 1,
+ .slices = 4,
},
[TF_TBL_TYPE_ACT_MODIFY_32B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 1,
+ .slices = 2,
},
[TF_TBL_TYPE_ACT_MODIFY_64B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
@@ -152,32 +152,32 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = {
[TF_TBL_TYPE_ACT_SP_SMAC] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
- .slices = 1,
+ .slices = 8,
},
[TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
- .slices = 1,
+ .slices = 4,
},
[TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
- .slices = 1,
+ .slices = 2,
},
/* Policy - Stats in bank 3 */
[TF_TBL_TYPE_ACT_STATS_64] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3,
- .slices = 1,
+ .slices = 8,
},
};
struct tf_rm_element_cfg tf_em_int_p58[TF_EM_TBL_TYPE_MAX] = {
[TF_EM_TBL_TYPE_EM_RECORD] = {
TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P58_EM_REC,
- 0, 0, 0
+ 0, 0
},
};
diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c
index e07d9168be..0fbb2fe837 100644
--- a/drivers/net/bnxt/tf_core/tf_msg.c
+++ b/drivers/net/bnxt/tf_core/tf_msg.c
@@ -2231,7 +2231,7 @@ tf_msg_get_if_tbl_entry(struct tf *tfp,
if (rc != 0)
return rc;
- tfp_memcpy(params->data, resp.data, req.size);
+ tfp_memcpy(¶ms->data[0], resp.data, req.size);
return 0;
}
diff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c
index 0a46e2a343..03c958a7d6 100644
--- a/drivers/net/bnxt/tf_core/tf_rm.c
+++ b/drivers/net/bnxt/tf_core/tf_rm.c
@@ -34,6 +34,12 @@ struct tf_rm_element {
*/
uint16_t hcapi_type;
+ /**
+ * Resource slices. How many slices will fit in the
+ * resource pool chunk size.
+ */
+ uint8_t slices;
+
/**
* HCAPI RM allocated range information for the element.
*/
@@ -356,12 +362,15 @@ tf_rm_check_residuals(struct tf_rm_new_db *rm_db,
* - - Failure if negative
*/
static int
-tf_rm_update_parent_reservations(struct tf_rm_element_cfg *cfg,
+tf_rm_update_parent_reservations(struct tf *tfp,
+ struct tf_dev_info *dev,
+ struct tf_rm_element_cfg *cfg,
uint16_t *alloc_cnt,
uint16_t num_elements,
uint16_t *req_cnt)
{
int parent, child;
+ const char *type_str;
/* Search through all the elements */
for (parent = 0; parent < num_elements; parent++) {
@@ -377,15 +386,25 @@ tf_rm_update_parent_reservations(struct tf_rm_element_cfg *cfg,
if (alloc_cnt[parent] % cfg[parent].slices)
combined_cnt++;
+ if (alloc_cnt[parent]) {
+ dev->ops->tf_dev_get_resource_str(tfp,
+ cfg[parent].hcapi_type,
+ &type_str);
+ }
+
/* Search again through all the elements */
for (child = 0; child < num_elements; child++) {
/* If this is one of my children */
if (cfg[child].cfg_type ==
TF_RM_ELEM_CFG_HCAPI_BA_CHILD &&
- cfg[child].parent_subtype == parent) {
+ cfg[child].parent_subtype == parent &&
+ alloc_cnt[child]) {
uint16_t cnt = 0;
RTE_ASSERT(cfg[child].slices);
+ dev->ops->tf_dev_get_resource_str(tfp,
+ cfg[child].hcapi_type,
+ &type_str);
/* Increment the parents combined count
* with each child's count adjusted for
* number of slices per RM allocated item.
@@ -479,7 +498,7 @@ tf_rm_create_db(struct tf *tfp,
/* Update the req_cnt based upon the element configuration
*/
- tf_rm_update_parent_reservations(parms->cfg,
+ tf_rm_update_parent_reservations(tfp, dev, parms->cfg,
parms->alloc_cnt,
parms->num_elements,
req_cnt);
@@ -594,6 +613,7 @@ tf_rm_create_db(struct tf *tfp,
db[i].cfg_type = cfg->cfg_type;
db[i].hcapi_type = cfg->hcapi_type;
+ db[i].slices = cfg->slices;
/* Save the parent subtype for later use to find the pool
*/
@@ -1271,6 +1291,26 @@ tf_rm_get_hcapi_type(struct tf_rm_get_hcapi_parms *parms)
return 0;
}
+int
+tf_rm_get_slices(struct tf_rm_get_slices_parms *parms)
+{
+ struct tf_rm_new_db *rm_db;
+ enum tf_rm_elem_cfg_type cfg_type;
+
+ TF_CHECK_PARMS2(parms, parms->rm_db);
+ rm_db = (struct tf_rm_new_db *)parms->rm_db;
+ TF_CHECK_PARMS1(rm_db->db);
+
+ cfg_type = rm_db->db[parms->subtype].cfg_type;
+
+ /* Bail out if not controlled by HCAPI */
+ if (cfg_type == TF_RM_ELEM_CFG_NULL)
+ return -ENOTSUP;
+
+ *parms->slices = rm_db->db[parms->subtype].slices;
+
+ return 0;
+}
int
tf_rm_get_inuse_count(struct tf_rm_get_inuse_count_parms *parms)
diff --git a/drivers/net/bnxt/tf_core/tf_rm.h b/drivers/net/bnxt/tf_core/tf_rm.h
index 8b984112e8..da7d0c7211 100644
--- a/drivers/net/bnxt/tf_core/tf_rm.h
+++ b/drivers/net/bnxt/tf_core/tf_rm.h
@@ -43,16 +43,6 @@ struct tf;
* support module, not called directly.
*/
-/**
- * Resource reservation single entry result. Used when accessing HCAPI
- * RM on the firmware.
- */
-struct tf_rm_new_entry {
- /** Starting index of the allocated resource */
- uint16_t start;
- /** Number of allocated elements */
- uint16_t stride;
-};
/**
* RM Element configuration enumeration. Used by the Device to
@@ -114,10 +104,6 @@ struct tf_rm_element_cfg {
*/
enum tf_rm_elem_cfg_type cfg_type;
- /* If a HCAPI to TF type conversion is required then TF type
- * can be added here.
- */
-
/**
* HCAPI RM Type for the element. Used for TF to HCAPI type
* conversion.
@@ -125,28 +111,19 @@ struct tf_rm_element_cfg {
uint16_t hcapi_type;
/**
- * if cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_CHILD
+ * if cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_CHILD/PARENT
*
* Parent Truflow module subtype associated with this resource type.
*/
uint16_t parent_subtype;
/**
- * if cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_CHILD
+ * if cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_CHILD/PARENT
*
* Resource slices. How many slices will fit in the
* resource pool chunk size.
*/
uint8_t slices;
-
- /**
- * Pool element divider count
- * If 0 or 1, there is 1:1 correspondence between the RM
- * BA pool resource element and the HCAPI RM firmware
- * resource. If > 1, the RM BA pool element has a 1:n
- * correspondence to the HCAPI RM firmware resource.
- */
- uint8_t divider;
};
/**
@@ -160,7 +137,7 @@ struct tf_rm_alloc_info {
* In case of dynamic allocation support this would have
* to be changed to linked list of tf_rm_entry instead.
*/
- struct tf_rm_new_entry entry;
+ struct tf_resource_info entry;
};
/**
@@ -331,6 +308,25 @@ struct tf_rm_get_hcapi_parms {
*/
uint16_t *hcapi_type;
};
+/**
+ * Get Slices parameters for a single element
+ */
+struct tf_rm_get_slices_parms {
+ /**
+ * [in] RM DB Handle
+ */
+ void *rm_db;
+ /**
+ * [in] TF subtype indicates which DB entry to perform the
+ * action on. (e.g. TF_TBL_TYPE_FULL_ACTION subtype of module
+ * TF_MODULE_TYPE_TABLE)
+ */
+ uint16_t subtype;
+ /**
+ * [in/out] Pointer to number of slices for the given type
+ */
+ uint16_t *slices;
+};
/**
* Get InUse count parameters for single element
@@ -394,6 +390,8 @@ struct tf_rm_check_indexes_in_range_parms {
* @ref tf_rm_get_hcapi_type
*
* @ref tf_rm_get_inuse_count
+ *
+ * @ref tf_rm_get_slice_size
*/
/**
@@ -571,5 +569,17 @@ int tf_rm_get_inuse_count(struct tf_rm_get_inuse_count_parms *parms);
int
tf_rm_check_indexes_in_range(struct tf_rm_check_indexes_in_range_parms *parms);
+/**
+ * Get the number of slices per resource bit allocator for the resource type
+ *
+ * [in] parms
+ * Pointer to get inuse parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int
+tf_rm_get_slices(struct tf_rm_get_slices_parms *parms);
#endif /* TF_RM_NEW_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_session.c b/drivers/net/bnxt/tf_core/tf_session.c
index 90b65c59e6..3e6664e9f2 100644
--- a/drivers/net/bnxt/tf_core/tf_session.c
+++ b/drivers/net/bnxt/tf_core/tf_session.c
@@ -202,6 +202,7 @@ tf_session_create(struct tf *tfp,
parms->open_cfg->device_type,
session->shadow_copy,
&parms->open_cfg->resources,
+ parms->open_cfg->wc_num_slices,
&session->dev);
/* Logging handled by dev_bind */
@@ -705,6 +706,22 @@ tf_session_get_session(struct tf *tfp,
return rc;
}
+int tf_session_get(struct tf *tfp,
+ struct tf_session **tfs,
+ struct tf_dev_info **tfd)
+{
+ int rc;
+ rc = tf_session_get_session_internal(tfp, tfs);
+
+ /* Logging done by tf_session_get_session_internal */
+ if (rc)
+ return rc;
+
+ rc = tf_session_get_device(*tfs, tfd);
+
+ return rc;
+}
+
struct tf_session_client *
tf_session_get_session_client(struct tf_session *tfs,
union tf_session_client_id session_client_id)
@@ -1012,4 +1029,43 @@ tf_session_set_tcam_shared_db(struct tf *tfp,
tfs->tcam_shared_db_handle = tcam_shared_db_handle;
return rc;
}
+
+int
+tf_session_get_sram_db(struct tf *tfp,
+ void **sram_handle)
+{
+ struct tf_session *tfs = NULL;
+ int rc = 0;
+
+ *sram_handle = NULL;
+
+ if (tfp == NULL)
+ return (-EINVAL);
+
+ rc = tf_session_get_session_internal(tfp, &tfs);
+ if (rc)
+ return rc;
+
+ *sram_handle = tfs->sram_handle;
+ return rc;
+}
+
+int
+tf_session_set_sram_db(struct tf *tfp,
+ void *sram_handle)
+{
+ struct tf_session *tfs = NULL;
+ int rc = 0;
+
+ if (tfp == NULL)
+ return (-EINVAL);
+
+ rc = tf_session_get_session_internal(tfp, &tfs);
+ if (rc)
+ return rc;
+
+ tfs->sram_handle = sram_handle;
+ return rc;
+}
+
#endif /* TF_TCAM_SHARED */
diff --git a/drivers/net/bnxt/tf_core/tf_session.h b/drivers/net/bnxt/tf_core/tf_session.h
index d68421cd13..c1d7f70060 100644
--- a/drivers/net/bnxt/tf_core/tf_session.h
+++ b/drivers/net/bnxt/tf_core/tf_session.h
@@ -166,6 +166,10 @@ struct tf_session {
*/
void *tcam_shared_db_handle;
#endif /* TF_TCAM_SHARED */
+ /**
+ * SRAM db reference for the session
+ */
+ void *sram_handle;
};
/**
@@ -278,6 +282,10 @@ struct tf_session_close_session_parms {
*
* @ref tf_session_set_tcam_shared_db
* #endif
+ *
+ * @ref tf_session_get_sram_db
+ *
+ * @ref tf_session_set_sram_db
*/
/**
@@ -435,11 +443,11 @@ tf_session_find_session_client_by_fid(struct tf_session *tfs,
/**
* Looks up the device information from the TF Session.
*
- * [in] tfp
- * Pointer to TF handle
+ * [in] tfs
+ * Pointer to session handle
*
* [out] tfd
- * Pointer pointer to the device
+ * Pointer to the device
*
* Returns
* - (0) if successful.
@@ -448,6 +456,26 @@ tf_session_find_session_client_by_fid(struct tf_session *tfs,
int tf_session_get_device(struct tf_session *tfs,
struct tf_dev_info **tfd);
+/**
+ * Returns the session and the device from the tfp.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [out] tfs
+ * Pointer to the session
+ *
+ * [out] tfd
+ * Pointer to the device
+
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_session_get(struct tf *tfp,
+ struct tf_session **tfs,
+ struct tf_dev_info **tfd);
+
/**
* Looks up the FW Session id the requested TF handle.
*
@@ -614,4 +642,28 @@ int
tf_session_get_tcam_shared_db(struct tf *tfp,
void **tcam_shared_db_handle);
+/**
+ * Set the pointer to the SRAM database
+ *
+ * [in] session, pointer to the session
+ *
+ * Returns:
+ * - the pointer to the parent bnxt struct
+ */
+int
+tf_session_set_sram_db(struct tf *tfp,
+ void *sram_handle);
+
+/**
+ * Get the pointer to the SRAM database
+ *
+ * [in] session, pointer to the session
+ *
+ * Returns:
+ * - the pointer to the parent bnxt struct
+ */
+int
+tf_session_get_sram_db(struct tf *tfp,
+ void **sram_handle);
+
#endif /* _TF_SESSION_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_sram_mgr.c b/drivers/net/bnxt/tf_core/tf_sram_mgr.c
new file mode 100644
index 0000000000..f633a78b25
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/tf_sram_mgr.c
@@ -0,0 +1,971 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019-2021 Broadcom
+ * All rights reserved.
+ */
+#include <stdlib.h>
+#include <stdio.h>
+#include "tf_sram_mgr.h"
+#include "tf_core.h"
+#include "tf_rm.h"
+#include "tf_common.h"
+#include "assert.h"
+#include "tf_util.h"
+#include "tfp.h"
+#if (STATS_CLEAR_ON_READ_SUPPORT == 0)
+#include "tf_msg.h"
+#endif
+/***************************
+ * Internal Data Structures
+ ***************************/
+
+/**
+ * TF SRAM block info
+ *
+ * Contains all the information about a particular 64B SRAM
+ * block and the slices within it.
+ */
+struct tf_sram_block {
+ /* Previous block
+ */
+ struct tf_sram_block *prev;
+ /* Next block
+ */
+ struct tf_sram_block *next;
+
+ /** Bitmap indicating which slices are in use
+ * If a bit is set, it indicates the slice
+ * in the row is in use.
+ */
+ uint8_t in_use_mask;
+
+ /** Block id - this is a 64B offset
+ */
+ uint16_t block_id;
+};
+
+/**
+ * TF SRAM block list
+ *
+ * List of 64B SRAM blocks used for fixed size slices (8, 16, 32, 64B)
+ */
+struct tf_sram_slice_list {
+ /** Pointer to head of linked list of blocks.
+ */
+ struct tf_sram_block *head;
+
+ /** Pointer to tail of linked list of blocks.
+ */
+ struct tf_sram_block *tail;
+
+ /** Total count of blocks
+ */
+ uint32_t cnt;
+
+ /** First non-full block in the list
+ */
+ struct tf_sram_block *first_not_full_block;
+
+ /** Entry slice size for this list
+ */
+ enum tf_sram_slice_size size;
+};
+
+
+/**
+ * TF SRAM bank info consists of lists of different slice sizes per bank
+ */
+struct tf_sram_bank_info {
+ struct tf_sram_slice_list slice[TF_SRAM_SLICE_SIZE_MAX];
+};
+
+/**
+ * SRAM banks consist of SRAM bank information
+ */
+struct tf_sram_bank {
+ struct tf_sram_bank_info bank[TF_SRAM_BANK_ID_MAX];
+};
+
+/**
+ * SRAM banks consist of SRAM bank information
+ */
+struct tf_sram {
+ struct tf_sram_bank dir[TF_DIR_MAX];
+};
+
+/**********************
+ * Internal functions
+ **********************/
+
+/**
+ * Get slice size in string format
+ */
+const char
+*tf_sram_slice_2_str(enum tf_sram_slice_size slice_size)
+{
+ switch (slice_size) {
+ case TF_SRAM_SLICE_SIZE_8B:
+ return "8B slice";
+ case TF_SRAM_SLICE_SIZE_16B:
+ return "16B slice";
+ case TF_SRAM_SLICE_SIZE_32B:
+ return "32B slice";
+ case TF_SRAM_SLICE_SIZE_64B:
+ return "64B slice";
+ default:
+ return "Invalid slice size";
+ }
+}
+
+/**
+ * Get bank in string format
+ */
+const char
+*tf_sram_bank_2_str(enum tf_sram_bank_id bank_id)
+{
+ switch (bank_id) {
+ case TF_SRAM_BANK_ID_0:
+ return "bank_0";
+ case TF_SRAM_BANK_ID_1:
+ return "bank_1";
+ case TF_SRAM_BANK_ID_2:
+ return "bank_2";
+ case TF_SRAM_BANK_ID_3:
+ return "bank_3";
+ default:
+ return "Invalid bank_id";
+ }
+}
+
+/**
+ * TF SRAM get slice list
+ */
+static int
+tf_sram_get_slice_list(struct tf_sram *sram,
+ struct tf_sram_slice_list **slice_list,
+ enum tf_sram_slice_size slice_size,
+ enum tf_dir dir,
+ enum tf_sram_bank_id bank_id)
+{
+ int rc = 0;
+
+ TF_CHECK_PARMS2(sram, slice_list);
+
+ *slice_list = &sram->dir[dir].bank[bank_id].slice[slice_size];
+
+ return rc;
+}
+
+uint16_t tf_sram_bank_2_base_offset[TF_SRAM_BANK_ID_MAX] = {
+ 0,
+ 2048,
+ 4096,
+ 6144
+};
+
+/**
+ * Translate a block id and bank_id to an 8B offset
+ */
+static void
+tf_sram_block_id_2_offset(enum tf_sram_bank_id bank_id, uint16_t block_id,
+ uint16_t *offset)
+{
+ *offset = (block_id + tf_sram_bank_2_base_offset[bank_id]) << 3;
+}
+
+/**
+ * Translates an 8B offset and bank_id to a block_id
+ */
+static void
+tf_sram_offset_2_block_id(enum tf_sram_bank_id bank_id, uint16_t offset,
+ uint16_t *block_id, uint16_t *slice_offset)
+{
+ *slice_offset = offset & 0x7;
+ *block_id = ((offset & ~0x7) >> 3) -
+ tf_sram_bank_2_base_offset[bank_id];
+}
+
+/**
+ * Find a matching block_id within the slice list
+ */
+static struct tf_sram_block
+*tf_sram_find_block(uint16_t block_id, struct tf_sram_slice_list *slice_list)
+{
+ uint32_t cnt;
+ struct tf_sram_block *block;
+
+ cnt = slice_list->cnt;
+ block = slice_list->head;
+
+ while (cnt > 0 && block) {
+ if (block->block_id == block_id)
+ return block;
+ block = block->next;
+ cnt--;
+ }
+ return NULL;
+}
+
+/**
+ * Given the current block get the next block within the slice list
+ *
+ * List is not changed.
+ */
+static struct tf_sram_block
+*tf_sram_get_next_block(struct tf_sram_block *block)
+{
+ struct tf_sram_block *nblock;
+
+ if (block != NULL)
+ nblock = block->next;
+ else
+ nblock = NULL;
+ return nblock;
+}
+
+/**
+ * Free an allocated slice from a block and if the block is empty,
+ * return an indication so that the block can be freed.
+ */
+static int
+tf_sram_free_slice(enum tf_sram_slice_size slice_size,
+ uint16_t slice_offset, struct tf_sram_block *block,
+ bool *block_is_empty)
+{
+ int rc = 0;
+ uint8_t shift;
+ uint8_t slice_mask = 0;
+
+ TF_CHECK_PARMS2(block, block_is_empty);
+
+ switch (slice_size) {
+ case TF_SRAM_SLICE_SIZE_8B:
+ shift = slice_offset >> 0;
+ assert(shift < 8);
+ slice_mask = 1 << shift;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_16B:
+ shift = slice_offset >> 1;
+ assert(shift < 4);
+ slice_mask = 1 << shift;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_32B:
+ shift = slice_offset >> 2;
+ assert(shift < 2);
+ slice_mask = 1 << shift;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_64B:
+ default:
+ shift = slice_offset >> 0;
+ assert(shift < 1);
+ slice_mask = 1 << shift;
+ break;
+ }
+
+ if ((block->in_use_mask & slice_mask) == 0) {
+ rc = -EINVAL;
+ TFP_DRV_LOG(ERR, "block_id(0x%x) slice(%d) was not allocated\n",
+ block->block_id, slice_offset);
+ return rc;
+ }
+
+ block->in_use_mask &= ~slice_mask;
+
+ if (block->in_use_mask == 0)
+ *block_is_empty = true;
+ else
+ *block_is_empty = false;
+
+ return rc;
+}
+
+/**
+ * TF SRAM get next slice
+ *
+ * Gets the next slice_offset available in the block
+ * and updates the in_use_mask.
+ */
+static int
+tf_sram_get_next_slice_in_block(struct tf_sram_block *block,
+ enum tf_sram_slice_size slice_size,
+ uint16_t *slice_offset,
+ bool *block_is_full)
+{
+ int rc, free_id = -1;
+ uint8_t shift, max_slices, mask, i, full_mask;
+
+ TF_CHECK_PARMS3(block, slice_offset, block_is_full);
+
+ switch (slice_size) {
+ case TF_SRAM_SLICE_SIZE_8B:
+ shift = 0;
+ max_slices = 8;
+ full_mask = 0xff;
+ break;
+ case TF_SRAM_SLICE_SIZE_16B:
+ shift = 1;
+ max_slices = 4;
+ full_mask = 0xf;
+ break;
+ case TF_SRAM_SLICE_SIZE_32B:
+ shift = 2;
+ max_slices = 2;
+ full_mask = 0x3;
+ break;
+ case TF_SRAM_SLICE_SIZE_64B:
+ default:
+ shift = 0;
+ max_slices = 1;
+ full_mask = 1;
+ break;
+ }
+
+ mask = block->in_use_mask;
+
+ for (i = 0; i < max_slices; i++) {
+ if ((mask & 1) == 0) {
+ free_id = i;
+ block->in_use_mask |= 1 << free_id;
+ break;
+ }
+ mask = mask >> 1;
+ }
+
+ if (block->in_use_mask == full_mask)
+ *block_is_full = true;
+ else
+ *block_is_full = false;
+
+
+ if (free_id >= 0) {
+ *slice_offset = free_id << shift;
+ rc = 0;
+ } else {
+ *slice_offset = 0;
+ rc = -ENOMEM;
+ }
+
+ return rc;
+}
+
+/**
+ * TF SRAM get indication as to whether the slice offset is
+ * allocated in the block.
+ *
+ */
+static int
+tf_sram_is_slice_allocated_in_block(struct tf_sram_block *block,
+ enum tf_sram_slice_size slice_size,
+ uint16_t slice_offset,
+ bool *is_allocated)
+{
+ int rc = 0;
+ uint8_t shift;
+ uint8_t slice_mask = 0;
+
+ TF_CHECK_PARMS2(block, is_allocated);
+
+ *is_allocated = false;
+
+ switch (slice_size) {
+ case TF_SRAM_SLICE_SIZE_8B:
+ shift = slice_offset >> 0;
+ assert(shift < 8);
+ slice_mask = 1 << shift;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_16B:
+ shift = slice_offset >> 1;
+ assert(shift < 4);
+ slice_mask = 1 << shift;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_32B:
+ shift = slice_offset >> 2;
+ assert(shift < 2);
+ slice_mask = 1 << shift;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_64B:
+ default:
+ shift = slice_offset >> 0;
+ assert(shift < 1);
+ slice_mask = 1 << shift;
+ break;
+ }
+
+ if ((block->in_use_mask & slice_mask) == 0) {
+ TFP_DRV_LOG(ERR, "block_id(0x%x) slice(%d) was not allocated\n",
+ block->block_id, slice_offset);
+ *is_allocated = false;
+ } else {
+ *is_allocated = true;
+ }
+
+ return rc;
+}
+
+/**
+ * Initialize slice list
+ */
+static void
+tf_sram_init_slice_list(struct tf_sram_slice_list *slice_list,
+ enum tf_sram_slice_size slice_size)
+{
+ slice_list->head = NULL;
+ slice_list->tail = NULL;
+ slice_list->cnt = 0;
+ slice_list->size = slice_size;
+}
+
+/**
+ * Get the block count
+ */
+static uint32_t
+tf_sram_get_block_cnt(struct tf_sram_slice_list *slice_list)
+{
+ return slice_list->cnt;
+}
+
+
+/**
+ * Free a block data structure - does not free to the RM
+ */
+static void
+tf_sram_free_block(struct tf_sram_slice_list *slice_list,
+ struct tf_sram_block *block)
+{
+ if (slice_list->head == block && slice_list->tail == block) {
+ slice_list->head = NULL;
+ slice_list->tail = NULL;
+ } else if (slice_list->head == block) {
+ slice_list->head = block->next;
+ slice_list->head->prev = NULL;
+ } else if (slice_list->tail == block) {
+ slice_list->tail = block->prev;
+ slice_list->tail->next = NULL;
+ } else {
+ block->prev->next = block->next;
+ block->next->prev = block->prev;
+ }
+ tfp_free(block);
+ slice_list->cnt--;
+}
+/**
+ * Free the entire slice_list
+ */
+static void
+tf_sram_free_slice_list(struct tf_sram_slice_list *slice_list)
+{
+ uint32_t i, block_cnt;
+ struct tf_sram_block *nblock, *block;
+
+ block_cnt = tf_sram_get_block_cnt(slice_list);
+ block = slice_list->head;
+
+ for (i = 0; i < block_cnt; i++) {
+ nblock = block->next;
+ tf_sram_free_block(slice_list, block);
+ block = nblock;
+ }
+}
+
+/**
+ * Allocate a single SRAM block from memory and add it to the slice list
+ */
+static struct tf_sram_block
+*tf_sram_alloc_block(struct tf_sram_slice_list *slice_list,
+ uint16_t block_id)
+{
+ struct tf_sram_block *block;
+ struct tfp_calloc_parms cparms;
+ int rc;
+
+ cparms.nitems = 1;
+ cparms.size = sizeof(struct tf_sram_block);
+ cparms.alignment = 0;
+ rc = tfp_calloc(&cparms);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "Failed to allocate block, rc:%s\n",
+ strerror(-rc));
+ return NULL;
+ }
+ block = (struct tf_sram_block *)cparms.mem_va;
+ block->block_id = block_id;
+
+ if (slice_list->head == NULL) {
+ slice_list->head = block;
+ slice_list->tail = block;
+ block->next = NULL;
+ block->prev = NULL;
+ } else {
+ block->next = slice_list->head;
+ block->prev = NULL;
+ block->next->prev = block;
+ slice_list->head = block->next->prev;
+ }
+ slice_list->cnt++;
+ return block;
+}
+
+/**
+ * Find the first not full block in the slice list
+ */
+static void
+tf_sram_find_first_not_full_block(struct tf_sram_slice_list *slice_list,
+ enum tf_sram_slice_size slice_size,
+ struct tf_sram_block **first_not_full_block)
+{
+ struct tf_sram_block *block = slice_list->head;
+ uint8_t slice_mask, mask;
+
+ switch (slice_size) {
+ case TF_SRAM_SLICE_SIZE_8B:
+ slice_mask = 0xff;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_16B:
+ slice_mask = 0xf;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_32B:
+ slice_mask = 0x3;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_64B:
+ default:
+ slice_mask = 0x1;
+ break;
+ }
+
+ *first_not_full_block = NULL;
+
+ while (block) {
+ mask = block->in_use_mask & slice_mask;
+ if (mask != slice_mask) {
+ *first_not_full_block = block;
+ break;
+ }
+ block = block->next;
+ }
+}
+static void
+tf_sram_dump_block(struct tf_sram_block *block)
+{
+ TFP_DRV_LOG(INFO, "block_id(0x%x) in_use_mask(0x%02x)\n",
+ block->block_id,
+ block->in_use_mask);
+}
+
+/**********************
+ * External functions
+ **********************/
+int
+tf_sram_mgr_bind(void **sram_handle)
+{
+ int rc = 0;
+ enum tf_sram_bank_id bank_id;
+ enum tf_sram_slice_size slice_size;
+ struct tf_sram *sram;
+ struct tf_sram_slice_list *slice_list;
+ enum tf_dir dir;
+ struct tfp_calloc_parms cparms;
+
+ TF_CHECK_PARMS1(sram_handle);
+
+ cparms.nitems = 1;
+ cparms.size = sizeof(struct tf_sram);
+ cparms.alignment = 0;
+ rc = tfp_calloc(&cparms);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "Failed to allocate SRAM mgmt data, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ sram = (struct tf_sram *)cparms.mem_va;
+
+ /* For each direction
+ */
+ for (dir = 0; dir < TF_DIR_MAX; dir++) {
+ /* For each bank
+ */
+ for (bank_id = TF_SRAM_BANK_ID_0;
+ bank_id < TF_SRAM_BANK_ID_MAX;
+ bank_id++) {
+ /* Create each sized slice empty list
+ */
+ for (slice_size = TF_SRAM_SLICE_SIZE_8B;
+ slice_size < TF_SRAM_SLICE_SIZE_MAX;
+ slice_size++) {
+ rc = tf_sram_get_slice_list(sram, &slice_list,
+ slice_size, dir,
+ bank_id);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "No SRAM slice list, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ tf_sram_init_slice_list(slice_list, slice_size);
+ }
+ }
+ }
+
+ *sram_handle = sram;
+
+ return rc;
+}
+
+int
+tf_sram_mgr_unbind(void *sram_handle)
+{
+ int rc = 0;
+ struct tf_sram *sram;
+ enum tf_sram_bank_id bank_id;
+ enum tf_sram_slice_size slice_size;
+ enum tf_dir dir;
+ struct tf_sram_slice_list *slice_list;
+
+ TF_CHECK_PARMS1(sram_handle);
+
+ sram = (struct tf_sram *)sram_handle;
+
+ for (dir = 0; dir < TF_DIR_MAX; dir++) {
+ /* For each bank
+ */
+ for (bank_id = TF_SRAM_BANK_ID_0;
+ bank_id < TF_SRAM_BANK_ID_MAX;
+ bank_id++) {
+ /* For each slice size
+ */
+ for (slice_size = TF_SRAM_SLICE_SIZE_8B;
+ slice_size < TF_SRAM_SLICE_SIZE_MAX;
+ slice_size++) {
+ rc = tf_sram_get_slice_list(sram, &slice_list,
+ slice_size, dir,
+ bank_id);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "No SRAM slice list, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ if (tf_sram_get_block_cnt(slice_list))
+ tf_sram_free_slice_list(slice_list);
+ }
+ }
+ }
+
+ tfp_free(sram);
+ sram_handle = NULL;
+
+ /* Freeing of the RM resources is handled by the table manager */
+ return rc;
+}
+
+int tf_sram_mgr_alloc(void *sram_handle,
+ struct tf_sram_mgr_alloc_parms *parms)
+{
+ int rc = 0;
+ struct tf_sram *sram;
+ struct tf_sram_slice_list *slice_list;
+ uint16_t block_id, slice_offset = 0;
+ uint32_t index;
+ struct tf_sram_block *block;
+ struct tf_rm_allocate_parms aparms = { 0 };
+ bool block_is_full;
+ uint16_t block_offset;
+
+ TF_CHECK_PARMS3(sram_handle, parms, parms->sram_offset);
+
+ sram = (struct tf_sram *)sram_handle;
+
+ /* Check the current slice list
+ */
+ rc = tf_sram_get_slice_list(sram, &slice_list, parms->slice_size,
+ parms->dir, parms->bank_id);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "No SRAM slice list, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ /* If the list is empty or all entries are full allocate a new block
+ */
+ if (!slice_list->first_not_full_block) {
+ /* Allocate and insert a new block
+ */
+ aparms.index = &index;
+ aparms.subtype = parms->tbl_type;
+ aparms.rm_db = parms->rm_db;
+ rc = tf_rm_allocate(&aparms);
+ if (rc)
+ return rc;
+
+ block_id = index;
+ block = tf_sram_alloc_block(slice_list, block_id);
+ } else {
+ /* Block exists
+ */
+ block =
+ (struct tf_sram_block *)(slice_list->first_not_full_block);
+ }
+ rc = tf_sram_get_next_slice_in_block(block,
+ parms->slice_size,
+ &slice_offset,
+ &block_is_full);
+
+ /* Find the new first non-full block in the list
+ */
+ tf_sram_find_first_not_full_block(slice_list,
+ parms->slice_size,
+ &slice_list->first_not_full_block);
+
+ tf_sram_block_id_2_offset(parms->bank_id, block->block_id,
+ &block_offset);
+
+ *parms->sram_offset = block_offset + slice_offset;
+ return rc;
+}
+
+int
+tf_sram_mgr_free(void *sram_handle,
+ struct tf_sram_mgr_free_parms *parms)
+{
+ int rc = 0;
+ struct tf_sram *sram;
+ struct tf_sram_slice_list *slice_list;
+ uint16_t block_id, slice_offset;
+ struct tf_sram_block *block;
+ bool block_is_empty;
+ struct tf_rm_free_parms fparms = { 0 };
+
+ TF_CHECK_PARMS2(sram_handle, parms);
+
+ sram = (struct tf_sram *)sram_handle;
+
+ /* Check the current slice list
+ */
+ rc = tf_sram_get_slice_list(sram, &slice_list, parms->slice_size,
+ parms->dir, parms->bank_id);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "No SRAM slice list, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ /* Determine the block id and slice offset from the SRAM offset
+ */
+ tf_sram_offset_2_block_id(parms->bank_id, parms->sram_offset, &block_id,
+ &slice_offset);
+
+ /* Search the list of blocks for the matching block id
+ */
+ block = tf_sram_find_block(block_id, slice_list);
+ if (block == NULL) {
+ TFP_DRV_LOG(ERR, "block not found 0x%x\n", block_id);
+ return rc;
+ }
+
+ /* If found, search for the matching SRAM slice in use.
+ */
+ rc = tf_sram_free_slice(parms->slice_size, slice_offset,
+ block, &block_is_empty);
+ if (rc) {
+ TFP_DRV_LOG(ERR, "Error freeing slice (%s)\n", strerror(-rc));
+ return rc;
+ }
+#if (STATS_CLEAR_ON_READ_SUPPORT == 0)
+ /* If this is a counter, clear it. In the future we need to switch to
+ * using the special access registers on Thor to automatically clear on
+ * read.
+ */
+ /* If this is counter table, clear the entry on free */
+ if (parms->tbl_type == TF_TBL_TYPE_ACT_STATS_64) {
+ uint8_t data[8] = { 0 };
+ uint16_t hcapi_type = 0;
+ struct tf_rm_get_hcapi_parms hparms = { 0 };
+
+ /* Get the hcapi type */
+ hparms.rm_db = parms->rm_db;
+ hparms.subtype = parms->tbl_type;
+ hparms.hcapi_type = &hcapi_type;
+ rc = tf_rm_get_hcapi_type(&hparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Failed type lookup, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->tbl_type),
+ strerror(-rc));
+ return rc;
+ }
+ /* Clear the counter
+ */
+ rc = tf_msg_set_tbl_entry(parms->tfp,
+ parms->dir,
+ hcapi_type,
+ sizeof(data),
+ data,
+ parms->sram_offset);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Set failed, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->tbl_type),
+ strerror(-rc));
+ return rc;
+ }
+ }
+#endif
+ /* If the block is empty, free the block to the RM
+ */
+ if (block_is_empty) {
+ fparms.rm_db = parms->rm_db;
+ fparms.subtype = parms->tbl_type;
+ fparms.index = block_id;
+ rc = tf_rm_free(&fparms);
+
+ if (rc) {
+ TFP_DRV_LOG(ERR, "Free block_id(%d) failed error(%s)\n",
+ block_id, strerror(-rc));
+ }
+ /* Free local entry regardless
+ */
+ tf_sram_free_block(slice_list, block);
+
+ /* Find the next non-full block in the list
+ */
+ tf_sram_find_first_not_full_block(slice_list,
+ parms->slice_size,
+ &slice_list->first_not_full_block);
+ }
+
+ return rc;
+}
+
+int
+tf_sram_mgr_dump(void *sram_handle,
+ struct tf_sram_mgr_dump_parms *parms)
+{
+ int rc = 0;
+ struct tf_sram *sram;
+ struct tf_sram_slice_list *slice_list;
+ uint32_t block_cnt, i;
+ struct tf_sram_block *block;
+
+ TF_CHECK_PARMS2(sram_handle, parms);
+
+ sram = (struct tf_sram *)sram_handle;
+
+ rc = tf_sram_get_slice_list(sram, &slice_list, parms->slice_size,
+ parms->dir, parms->bank_id);
+ if (rc)
+ return rc;
+
+ if (slice_list->cnt || slice_list->first_not_full_block) {
+ TFP_DRV_LOG(INFO, "\n********** %s: %s: %s ***********\n",
+ tf_sram_bank_2_str(parms->bank_id),
+ tf_dir_2_str(parms->dir),
+ tf_sram_slice_2_str(parms->slice_size));
+
+ block_cnt = tf_sram_get_block_cnt(slice_list);
+ TFP_DRV_LOG(INFO, "block_cnt(%d)\n", block_cnt);
+ if (slice_list->first_not_full_block)
+ TFP_DRV_LOG(INFO, "first_not_full_block(0x%x)\n",
+ slice_list->first_not_full_block->block_id);
+ block = slice_list->head;
+ for (i = 0; i < block_cnt; i++) {
+ tf_sram_dump_block(block);
+ block = tf_sram_get_next_block(block);
+ }
+ TFP_DRV_LOG(INFO, "*********************************\n");
+ }
+ return rc;
+}
+/**
+ * Validate an SRAM Slice is allocated
+ *
+ * Validate whether the SRAM slice is allocated
+ *
+ * [in] sram_handle
+ * Pointer to SRAM handle
+ *
+ * [in] parms
+ * Pointer to the SRAM alloc parameters
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ *
+ */
+int tf_sram_mgr_is_allocated(void *sram_handle,
+ struct tf_sram_mgr_is_allocated_parms *parms)
+{
+ int rc = 0;
+ struct tf_sram *sram;
+ struct tf_sram_slice_list *slice_list;
+ uint16_t block_id, slice_offset;
+ struct tf_sram_block *block;
+
+ TF_CHECK_PARMS3(sram_handle, parms, parms->is_allocated);
+
+ sram = (struct tf_sram *)sram_handle;
+
+ /* Check the current slice list
+ */
+ rc = tf_sram_get_slice_list(sram, &slice_list, parms->slice_size,
+ parms->dir, parms->bank_id);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "No SRAM slice list, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ /* If the list is empty, then it cannot be allocated
+ */
+ if (!slice_list->cnt) {
+ TFP_DRV_LOG(ERR, "List is empty for %s:%s:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_sram_slice_2_str(parms->slice_size),
+ tf_sram_bank_2_str(parms->bank_id));
+
+ parms->is_allocated = false;
+ goto done;
+ }
+
+ /* Determine the block id and slice offset from the SRAM offset
+ */
+ tf_sram_offset_2_block_id(parms->bank_id, parms->sram_offset, &block_id,
+ &slice_offset);
+
+ /* Search the list of blocks for the matching block id
+ */
+ block = tf_sram_find_block(block_id, slice_list);
+ if (block == NULL) {
+ TFP_DRV_LOG(ERR, "block not found in list 0x%x\n",
+ parms->sram_offset);
+ parms->is_allocated = false;
+ goto done;
+ }
+
+ rc = tf_sram_is_slice_allocated_in_block(block,
+ parms->slice_size,
+ slice_offset,
+ parms->is_allocated);
+done:
+ return rc;
+}
diff --git a/drivers/net/bnxt/tf_core/tf_sram_mgr.h b/drivers/net/bnxt/tf_core/tf_sram_mgr.h
new file mode 100644
index 0000000000..4abe3fb468
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/tf_sram_mgr.h
@@ -0,0 +1,317 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019-2021 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef _TF_SRAM_MGR_H_
+#define _TF_SRAM_MGR_H_
+
+#include <string.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <ctype.h>
+#include <limits.h>
+#include <errno.h>
+#include "tf_core.h"
+#include "tf_rm.h"
+
+/* When special access registers are used to access the SRAM, stats can be
+ * automatically cleared on read by the hardware. This requires additional
+ * support to be added in the firmware to use these registers for statistics.
+ * The support entails using the special access registers to read the stats.
+ * These are stored in bank 3 currently but may move depending upon the
+ * policy defined in tf_device_p58.h
+ */
+#define STATS_CLEAR_ON_READ_SUPPORT 0
+
+#define TF_SRAM_MGR_BLOCK_SZ_BYTES 64
+#define TF_SRAM_MGR_MIN_SLICE_BYTES 8
+/**
+ * Bank identifier
+ */
+enum tf_sram_bank_id {
+ TF_SRAM_BANK_ID_0, /**< SRAM Bank 0 id */
+ TF_SRAM_BANK_ID_1, /**< SRAM Bank 1 id */
+ TF_SRAM_BANK_ID_2, /**< SRAM Bank 2 id */
+ TF_SRAM_BANK_ID_3, /**< SRAM Bank 3 id */
+ TF_SRAM_BANK_ID_MAX /**< SRAM Bank index limit */
+};
+
+/**
+ * TF slice size.
+ *
+ * A slice is part of a 64B row
+ *
+ * Each slice is a multiple of 8B
+ */
+enum tf_sram_slice_size {
+ TF_SRAM_SLICE_SIZE_8B, /**< 8 byte SRAM slice */
+ TF_SRAM_SLICE_SIZE_16B, /**< 16 byte SRAM slice */
+ TF_SRAM_SLICE_SIZE_32B, /**< 32 byte SRAM slice */
+ TF_SRAM_SLICE_SIZE_64B, /**< 64 byte SRAM slice */
+ TF_SRAM_SLICE_SIZE_MAX /**< slice limit */
+};
+
+
+/** Initialize the SRAM slice manager
+ *
+ * The SRAM slice manager manages slices within 64B rows. Slices are of size
+ * tf_sram_slice_size. This function provides a handle to the SRAM manager
+ * data.
+ *
+ * SRAM manager data may dynamically allocate data upon initialization if
+ * running on the host.
+ *
+ * [in/out] sram_handle
+ * Pointer to SRAM handle
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ *
+ * Returns the handle for the SRAM slice manager
+ */
+int tf_sram_mgr_bind(void **sram_handle);
+
+/** Uninitialize the SRAM slice manager
+ *
+ * Frees any dynamically allocated data structures for SRAM slice management.
+ *
+ * [in] sram_handle
+ * Pointer to SRAM handle
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ */
+int tf_sram_mgr_unbind(void *sram_handle);
+
+/**
+ * tf_sram_mgr_alloc_parms parameter definition
+ */
+struct tf_sram_mgr_alloc_parms {
+ /**
+ * [in] dir
+ */
+ enum tf_dir dir;
+ /**
+ * [in] bank
+ *
+ * the SRAM bank to allocate from
+ */
+ enum tf_sram_bank_id bank_id;
+ /**
+ * [in] slice_size
+ *
+ * the slice size to allocate
+ */
+ enum tf_sram_slice_size slice_size;
+ /**
+ * [in/out] sram_slice
+ *
+ * A pointer to be filled with an 8B sram slice offset
+ */
+ uint16_t *sram_offset;
+ /**
+ * [in] RM DB Handle required for RM allocation
+ */
+ void *rm_db;
+ /**
+ * [in] tf table type
+ */
+ enum tf_tbl_type tbl_type;
+};
+
+/**
+ * Allocate an SRAM Slice
+ *
+ * Allocate an SRAM slice from the indicated bank. If successful an 8B SRAM
+ * offset will be returned. Slices are variable sized. This may result in
+ * a row being allocated from the RM SRAM bank pool if required.
+ *
+ * [in] sram_handle
+ * Pointer to SRAM handle
+ *
+ * [in] parms
+ * Pointer to the SRAM alloc parameters
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ *
+ */
+int tf_sram_mgr_alloc(void *sram_handle,
+ struct tf_sram_mgr_alloc_parms *parms);
+/**
+ * tf_sram_mgr_free_parms parameter definition
+ */
+struct tf_sram_mgr_free_parms {
+ /**
+ * [in] dir
+ */
+ enum tf_dir dir;
+ /**
+ * [in] bank
+ *
+ * the SRAM bank to free to
+ */
+ enum tf_sram_bank_id bank_id;
+ /**
+ * [in] slice_size
+ *
+ * the slice size to be returned
+ */
+ enum tf_sram_slice_size slice_size;
+ /**
+ * [in] sram_offset
+ *
+ * the SRAM slice offset (8B) to be returned
+ */
+ uint16_t sram_offset;
+ /**
+ * [in] RM DB Handle required for RM free
+ */
+ void *rm_db;
+ /**
+ * [in] tf table type
+ */
+ enum tf_tbl_type tbl_type;
+#if (STATS_CLEAR_ON_READ_SUPPORT == 0)
+ /**
+ * [in] tfp
+ *
+ * A pointer to the tf handle
+ */
+ void *tfp;
+#endif
+};
+
+/**
+ * Free an SRAM Slice
+ *
+ * Free an SRAM slice to the indicated bank. This may result in a 64B row
+ * being returned to the RM SRAM bank pool.
+ *
+ * [in] sram_handle
+ * Pointer to SRAM handle
+ *
+ * [in] parms
+ * Pointer to the SRAM free parameters
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ *
+ */
+int tf_sram_mgr_free(void *sram_handle,
+ struct tf_sram_mgr_free_parms *parms);
+
+/**
+ * tf_sram_mgr_dump_parms parameter definition
+ */
+struct tf_sram_mgr_dump_parms {
+ /**
+ * [in] dir
+ */
+ enum tf_dir dir;
+ /**
+ * [in] bank
+ *
+ * the SRAM bank to dump
+ */
+ enum tf_sram_bank_id bank_id;
+ /**
+ * [in] slice_size
+ *
+ * the slice size list to be dumped
+ */
+ enum tf_sram_slice_size slice_size;
+};
+
+/**
+ * Dump a slice list
+ *
+ * Dump the slice list given the SRAM bank and the slice size
+ *
+ * [in] sram_handle
+ * Pointer to SRAM handle
+ *
+ * [in] parms
+ * Pointer to the SRAM free parameters
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ *
+ */
+int tf_sram_mgr_dump(void *sram_handle,
+ struct tf_sram_mgr_dump_parms *parms);
+
+/**
+ * tf_sram_mgr_is_allocated_parms parameter definition
+ */
+struct tf_sram_mgr_is_allocated_parms {
+ /**
+ * [in] dir
+ */
+ enum tf_dir dir;
+ /**
+ * [in] bank
+ *
+ * the SRAM bank to allocate from
+ */
+ enum tf_sram_bank_id bank_id;
+ /**
+ * [in] slice_size
+ *
+ * the slice size which was allocated
+ */
+ enum tf_sram_slice_size slice_size;
+ /**
+ * [in] sram_offset
+ *
+ * The sram slice offset to validate
+ */
+ uint16_t sram_offset;
+ /**
+ * [in/out] is_allocated
+ *
+ * Pointer passed in to be filled with indication of allocation
+ */
+ bool *is_allocated;
+};
+
+/**
+ * Validate an SRAM Slice is allocated
+ *
+ * Validate whether the SRAM slice is allocated
+ *
+ * [in] sram_handle
+ * Pointer to SRAM handle
+ *
+ * [in] parms
+ * Pointer to the SRAM alloc parameters
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ *
+ */
+int tf_sram_mgr_is_allocated(void *sram_handle,
+ struct tf_sram_mgr_is_allocated_parms *parms);
+
+/**
+ * Given the slice size, return a char string
+ */
+const char
+*tf_sram_slice_2_str(enum tf_sram_slice_size slice_size);
+
+/**
+ * Given the bank_id, return a char string
+ */
+const char
+*tf_sram_bank_2_str(enum tf_sram_bank_id bank_id);
+
+#endif /* _TF_SRAM_MGR_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c
index 7011edcd78..0a8720e7b6 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl.c
+++ b/drivers/net/bnxt/tf_core/tf_tbl.c
@@ -16,20 +16,11 @@
#include "tf_session.h"
#include "tf_device.h"
-#define TF_TBL_RM_TO_PTR(new_idx, idx, base, shift) { \
- *(new_idx) = (((idx) + (base)) << (shift)); \
-}
-
-#define TF_TBL_PTR_TO_RM(new_idx, idx, base, shift) { \
- *(new_idx) = (((idx) >> (shift)) - (base)); \
-}
-
struct tf;
-/**
- * Shadow init flag, set on bind and cleared on unbind
- */
-static uint8_t shadow_init;
+#define TF_TBL_RM_TO_PTR(new_idx, idx, base, shift) { \
+ *(new_idx) = (((idx) + (base)) << (shift)); \
+}
int
tf_tbl_bind(struct tf *tfp,
@@ -121,8 +112,6 @@ tf_tbl_unbind(struct tf *tfp)
tbl_db->tbl_db[i] = NULL;
}
- shadow_init = 0;
-
return 0;
}
@@ -135,7 +124,6 @@ tf_tbl_alloc(struct tf *tfp __rte_unused,
struct tf_rm_allocate_parms aparms = { 0 };
struct tf_session *tfs;
struct tf_dev_info *dev;
- uint16_t base = 0, shift = 0;
struct tbl_rm_db *tbl_db;
void *tbl_db_ptr = NULL;
@@ -154,28 +142,12 @@ tf_tbl_alloc(struct tf *tfp __rte_unused,
rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr);
if (rc) {
TFP_DRV_LOG(ERR,
- "Failed to get em_ext_db from session, rc:%s\n",
+ "Failed to get tbl_db from session, rc:%s\n",
strerror(-rc));
return rc;
}
tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
- /* Only get table info if required for the device */
- if (dev->ops->tf_dev_get_tbl_info) {
- rc = dev->ops->tf_dev_get_tbl_info(tfp,
- tbl_db->tbl_db[parms->dir],
- parms->type,
- &base,
- &shift);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed to get table info:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type);
- return rc;
- }
- }
-
/* Allocate requested element */
aparms.rm_db = tbl_db->tbl_db[parms->dir];
aparms.subtype = parms->type;
@@ -183,13 +155,12 @@ tf_tbl_alloc(struct tf *tfp __rte_unused,
rc = tf_rm_allocate(&aparms);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s: Failed allocate, type:%d\n",
+ "%s: Failed allocate, type:%s\n",
tf_dir_2_str(parms->dir),
- parms->type);
+ tf_tbl_type_2_str(parms->type));
return rc;
}
- TF_TBL_RM_TO_PTR(&idx, idx, base, shift);
*parms->idx = idx;
return 0;
@@ -205,7 +176,6 @@ tf_tbl_free(struct tf *tfp __rte_unused,
int allocated = 0;
struct tf_session *tfs;
struct tf_dev_info *dev;
- uint16_t base = 0, shift = 0;
struct tbl_rm_db *tbl_db;
void *tbl_db_ptr = NULL;
@@ -230,28 +200,10 @@ tf_tbl_free(struct tf *tfp __rte_unused,
}
tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
- /* Only get table info if required for the device */
- if (dev->ops->tf_dev_get_tbl_info) {
- rc = dev->ops->tf_dev_get_tbl_info(tfp,
- tbl_db->tbl_db[parms->dir],
- parms->type,
- &base,
- &shift);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed to get table info:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type);
- return rc;
- }
- }
-
/* Check if element is in use */
aparms.rm_db = tbl_db->tbl_db[parms->dir];
aparms.subtype = parms->type;
-
- TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift);
-
+ aparms.index = parms->idx;
aparms.allocated = &allocated;
rc = tf_rm_is_allocated(&aparms);
if (rc)
@@ -259,9 +211,9 @@ tf_tbl_free(struct tf *tfp __rte_unused,
if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
TFP_DRV_LOG(ERR,
- "%s: Entry already free, type:%d, index:%d\n",
+ "%s: Entry already free, type:%s, index:%d\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
parms->idx);
return -EINVAL;
}
@@ -279,9 +231,9 @@ tf_tbl_free(struct tf *tfp __rte_unused,
rc = tf_rm_get_hcapi_type(&hparms);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Failed type lookup, type:%d, rc:%s\n",
+ "%s, Failed type lookup, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
return rc;
}
@@ -295,9 +247,9 @@ tf_tbl_free(struct tf *tfp __rte_unused,
parms->idx);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Set failed, type:%d, rc:%s\n",
+ "%s, Set failed, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
return rc;
}
@@ -306,15 +258,13 @@ tf_tbl_free(struct tf *tfp __rte_unused,
/* Free requested element */
fparms.rm_db = tbl_db->tbl_db[parms->dir];
fparms.subtype = parms->type;
-
- TF_TBL_PTR_TO_RM(&fparms.index, parms->idx, base, shift);
-
+ fparms.index = parms->idx;
rc = tf_rm_free(&fparms);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s: Free failed, type:%d, index:%d\n",
+ "%s: Free failed, type:%s, index:%d\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
parms->idx);
return rc;
}
@@ -333,7 +283,6 @@ tf_tbl_set(struct tf *tfp,
struct tf_rm_get_hcapi_parms hparms = { 0 };
struct tf_session *tfs;
struct tf_dev_info *dev;
- uint16_t base = 0, shift = 0;
struct tbl_rm_db *tbl_db;
void *tbl_db_ptr = NULL;
@@ -358,21 +307,6 @@ tf_tbl_set(struct tf *tfp,
}
tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
- /* Only get table info if required for the device */
- if (dev->ops->tf_dev_get_tbl_info) {
- rc = dev->ops->tf_dev_get_tbl_info(tfp,
- tbl_db->tbl_db[parms->dir],
- parms->type,
- &base,
- &shift);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed to get table info:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type);
- return rc;
- }
- }
/* Do not check meter drop counter because it is not allocated
* resources
@@ -381,19 +315,18 @@ tf_tbl_set(struct tf *tfp,
/* Verify that the entry has been previously allocated */
aparms.rm_db = tbl_db->tbl_db[parms->dir];
aparms.subtype = parms->type;
- TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift);
-
aparms.allocated = &allocated;
+ aparms.index = parms->idx;
rc = tf_rm_is_allocated(&aparms);
if (rc)
return rc;
if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
TFP_DRV_LOG(ERR,
- "%s, Invalid or not allocated index, type:%d, idx:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type,
- parms->idx);
+ "%s, Invalid or not allocated, type:%s, idx:%d\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->idx);
return -EINVAL;
}
}
@@ -405,9 +338,9 @@ tf_tbl_set(struct tf *tfp,
rc = tf_rm_get_hcapi_type(&hparms);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Failed type lookup, type:%d, rc:%s\n",
+ "%s, Failed type lookup, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
return rc;
}
@@ -420,9 +353,9 @@ tf_tbl_set(struct tf *tfp,
parms->idx);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Set failed, type:%d, rc:%s\n",
+ "%s, Set failed, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
return rc;
}
@@ -441,7 +374,6 @@ tf_tbl_get(struct tf *tfp,
struct tf_rm_get_hcapi_parms hparms = { 0 };
struct tf_session *tfs;
struct tf_dev_info *dev;
- uint16_t base = 0, shift = 0;
struct tbl_rm_db *tbl_db;
void *tbl_db_ptr = NULL;
@@ -466,22 +398,6 @@ tf_tbl_get(struct tf *tfp,
}
tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
- /* Only get table info if required for the device */
- if (dev->ops->tf_dev_get_tbl_info) {
- rc = dev->ops->tf_dev_get_tbl_info(tfp,
- tbl_db->tbl_db[parms->dir],
- parms->type,
- &base,
- &shift);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed to get table info:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type);
- return rc;
- }
- }
-
/* Do not check meter drop counter because it is not allocated
* resources.
*/
@@ -489,8 +405,7 @@ tf_tbl_get(struct tf *tfp,
/* Verify that the entry has been previously allocated */
aparms.rm_db = tbl_db->tbl_db[parms->dir];
aparms.subtype = parms->type;
- TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift);
-
+ aparms.index = parms->idx;
aparms.allocated = &allocated;
rc = tf_rm_is_allocated(&aparms);
if (rc)
@@ -498,9 +413,9 @@ tf_tbl_get(struct tf *tfp,
if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
TFP_DRV_LOG(ERR,
- "%s, Invalid or not allocated index, type:%d, idx:%d\n",
+ "%s, Invalid or not allocated index, type:%s, idx:%d\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
parms->idx);
return -EINVAL;
}
@@ -513,9 +428,9 @@ tf_tbl_get(struct tf *tfp,
rc = tf_rm_get_hcapi_type(&hparms);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Failed type lookup, type:%d, rc:%s\n",
+ "%s, Failed type lookup, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
return rc;
}
@@ -529,9 +444,9 @@ tf_tbl_get(struct tf *tfp,
parms->idx);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Get failed, type:%d, rc:%s\n",
+ "%s, Get failed, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
return rc;
}
@@ -549,7 +464,6 @@ tf_tbl_bulk_get(struct tf *tfp,
struct tf_rm_check_indexes_in_range_parms cparms = { 0 };
struct tf_session *tfs;
struct tf_dev_info *dev;
- uint16_t base = 0, shift = 0;
struct tbl_rm_db *tbl_db;
void *tbl_db_ptr = NULL;
@@ -574,40 +488,21 @@ tf_tbl_bulk_get(struct tf *tfp,
}
tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
- /* Only get table info if required for the device */
- if (dev->ops->tf_dev_get_tbl_info) {
- rc = dev->ops->tf_dev_get_tbl_info(tfp,
- tbl_db->tbl_db[parms->dir],
- parms->type,
- &base,
- &shift);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed to get table info:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type);
- return rc;
- }
- }
-
/* Verify that the entries are in the range of reserved resources. */
cparms.rm_db = tbl_db->tbl_db[parms->dir];
cparms.subtype = parms->type;
-
- TF_TBL_PTR_TO_RM(&cparms.starting_index, parms->starting_idx,
- base, shift);
-
cparms.num_entries = parms->num_entries;
+ cparms.starting_index = parms->starting_idx;
rc = tf_rm_check_indexes_in_range(&cparms);
if (rc) {
TFP_DRV_LOG(ERR,
"%s, Invalid or %d index starting from %d"
- " not in range, type:%d",
+ " not in range, type:%s",
tf_dir_2_str(parms->dir),
parms->starting_idx,
parms->num_entries,
- parms->type);
+ tf_tbl_type_2_str(parms->type));
return rc;
}
@@ -617,9 +512,9 @@ tf_tbl_bulk_get(struct tf *tfp,
rc = tf_rm_get_hcapi_type(&hparms);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Failed type lookup, type:%d, rc:%s\n",
+ "%s, Failed type lookup, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
return rc;
}
@@ -634,9 +529,9 @@ tf_tbl_bulk_get(struct tf *tfp,
parms->physical_mem_addr);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s, Bulk get failed, type:%d, rc:%s\n",
+ "%s, Bulk get failed, type:%s, rc:%s\n",
tf_dir_2_str(parms->dir),
- parms->type,
+ tf_tbl_type_2_str(parms->type),
strerror(-rc));
}
@@ -653,9 +548,9 @@ tf_tbl_get_resc_info(struct tf *tfp,
struct tf_rm_get_alloc_info_parms ainfo;
void *tbl_db_ptr = NULL;
struct tbl_rm_db *tbl_db;
- uint16_t base = 0, shift = 0;
struct tf_dev_info *dev;
struct tf_session *tfs;
+ uint16_t base = 0, shift = 0;
TF_CHECK_PARMS2(tfp, tbl);
@@ -677,7 +572,6 @@ tf_tbl_get_resc_info(struct tf *tfp,
tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
- /* check if reserved resource for WC is multiple of num_slices */
for (d = 0; d < TF_DIR_MAX; d++) {
ainfo.rm_db = tbl_db->tbl_db[d];
dinfo = tbl[d].info;
diff --git a/drivers/net/bnxt/tf_core/tf_tbl.h b/drivers/net/bnxt/tf_core/tf_tbl.h
index 7e1107ffe7..2483718e5d 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl.h
+++ b/drivers/net/bnxt/tf_core/tf_tbl.h
@@ -28,14 +28,6 @@ struct tf_tbl_cfg_parms {
* Table Type element configuration array
*/
struct tf_rm_element_cfg *cfg;
- /**
- * Shadow table type configuration array
- */
- struct tf_shadow_tbl_cfg *shadow_cfg;
- /**
- * Boolean controlling the request shadow copy.
- */
- bool shadow_copy;
/**
* Session resource allocations
*/
@@ -197,8 +189,6 @@ struct tbl_rm_db {
*
* @ref tf_tbl_free
*
- * @ref tf_tbl_alloc_search
- *
* @ref tf_tbl_set
*
* @ref tf_tbl_get
@@ -255,10 +245,7 @@ int tf_tbl_alloc(struct tf *tfp,
struct tf_tbl_alloc_parms *parms);
/**
- * Free's the requested table type and returns it to the DB. If shadow
- * DB is enabled its searched first and if found the element refcount
- * is decremented. If refcount goes to 0 then its returned to the
- * table type DB.
+ * Frees the requested table type and returns it to the DB.
*
* [in] tfp
* Pointer to TF handle, used for HCAPI communication
diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.c b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
new file mode 100644
index 0000000000..ea10afecb6
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
@@ -0,0 +1,713 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019-2021 Broadcom
+ * All rights reserved.
+ */
+
+/* Truflow Table APIs and supporting code */
+
+#include <rte_common.h>
+
+#include "tf_tbl.h"
+#include "tf_tbl_sram.h"
+#include "tf_sram_mgr.h"
+#include "tf_common.h"
+#include "tf_rm.h"
+#include "tf_util.h"
+#include "tf_msg.h"
+#include "tfp.h"
+#include "tf_session.h"
+#include "tf_device.h"
+#include "cfa_resource_types.h"
+
+#define DBG_SRAM 0
+
+/**
+ * tf_sram_tbl_get_info_parms parameter definition
+ */
+struct tf_tbl_sram_get_info_parms {
+ /**
+ * [in] table RM database
+ */
+ void *rm_db;
+ /**
+ * [in] Receive or transmit direction
+ */
+ enum tf_dir dir;
+ /**
+ * [in] table_type
+ *
+ * the TF index table type
+ */
+ enum tf_tbl_type tbl_type;
+ /**
+ * [out] bank
+ *
+ * The SRAM bank associated with the type
+ */
+ enum tf_sram_bank_id bank_id;
+ /**
+ * [out] slice_size
+ *
+ * the slice size for the indicated table type
+ */
+ enum tf_sram_slice_size slice_size;
+};
+
+/**
+ * Translate HCAPI type to SRAM Manager bank
+ */
+const uint16_t tf_tbl_sram_hcapi_2_bank[CFA_RESOURCE_TYPE_P58_LAST] = {
+ [CFA_RESOURCE_TYPE_P58_SRAM_BANK_0] = TF_SRAM_BANK_ID_0,
+ [CFA_RESOURCE_TYPE_P58_SRAM_BANK_1] = TF_SRAM_BANK_ID_1,
+ [CFA_RESOURCE_TYPE_P58_SRAM_BANK_2] = TF_SRAM_BANK_ID_2,
+ [CFA_RESOURCE_TYPE_P58_SRAM_BANK_3] = TF_SRAM_BANK_ID_3
+};
+
+#define TF_TBL_SRAM_SLICES_MAX \
+ (TF_SRAM_MGR_BLOCK_SZ_BYTES / TF_SRAM_MGR_MIN_SLICE_BYTES)
+/**
+ * Translate HCAPI type to SRAM Manager bank
+ */
+const uint8_t tf_tbl_sram_slices_2_size[TF_TBL_SRAM_SLICES_MAX + 1] = {
+ [0] = TF_SRAM_SLICE_SIZE_64B, /* if 0 slices assume 1 64B block */
+ [1] = TF_SRAM_SLICE_SIZE_64B, /* 1 slice per 64B block */
+ [2] = TF_SRAM_SLICE_SIZE_32B, /* 2 slices per 64B block */
+ [4] = TF_SRAM_SLICE_SIZE_16B, /* 4 slices per 64B block */
+ [8] = TF_SRAM_SLICE_SIZE_8B /* 8 slices per 64B block */
+};
+
+/**
+ * Get SRAM Table Information for a given index table type
+ *
+ *
+ * [in] sram_handle
+ * Pointer to SRAM handle
+ *
+ * [in] parms
+ * Pointer to the SRAM get info parameters
+ *
+ * Returns
+ * - (0) if successful
+ * - (-EINVAL) on failure
+ *
+ */
+static int tf_tbl_sram_get_info(struct tf_tbl_sram_get_info_parms *parms)
+{
+ int rc = 0;
+ uint16_t hcapi_type;
+ uint16_t slices;
+ struct tf_rm_get_hcapi_parms hparms;
+ struct tf_rm_get_slices_parms sparms;
+
+ hparms.rm_db = parms->rm_db;
+ hparms.subtype = parms->tbl_type;
+ hparms.hcapi_type = &hcapi_type;
+
+ rc = tf_rm_get_hcapi_type(&hparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get hcapi_type %s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->tbl_type),
+ strerror(-rc));
+ return rc;
+ }
+ parms->bank_id = tf_tbl_sram_hcapi_2_bank[hcapi_type];
+
+ sparms.rm_db = parms->rm_db;
+ sparms.subtype = parms->tbl_type;
+ sparms.slices = &slices;
+
+ rc = tf_rm_get_slices(&sparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get slice cnt %s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->tbl_type),
+ strerror(-rc));
+ return rc;
+ }
+ if (slices)
+ parms->slice_size = tf_tbl_sram_slices_2_size[slices];
+
+ TFP_DRV_LOG(INFO,
+ "(%s) bank(%s) slice_size(%s)\n",
+ tf_tbl_type_2_str(parms->tbl_type),
+ tf_sram_bank_2_str(parms->bank_id),
+ tf_sram_slice_2_str(parms->slice_size));
+ return rc;
+}
+
+int
+tf_tbl_sram_bind(struct tf *tfp __rte_unused)
+{
+ int rc = 0;
+ void *sram_handle = NULL;
+
+ TF_CHECK_PARMS1(tfp);
+
+ rc = tf_sram_mgr_bind(&sram_handle);
+
+ tf_session_set_sram_db(tfp, sram_handle);
+
+ TFP_DRV_LOG(INFO,
+ "SRAM Table - initialized\n");
+
+ return rc;
+}
+
+int
+tf_tbl_sram_unbind(struct tf *tfp __rte_unused)
+{
+ int rc = 0;
+ void *sram_handle = NULL;
+
+ TF_CHECK_PARMS1(tfp);
+
+ rc = tf_session_get_sram_db(tfp, &sram_handle);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get sram_handle from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ if (sram_handle)
+ rc = tf_sram_mgr_unbind(sram_handle);
+
+ TFP_DRV_LOG(INFO,
+ "SRAM Table - deinitialized\n");
+ return rc;
+}
+
+int
+tf_tbl_sram_alloc(struct tf *tfp,
+ struct tf_tbl_alloc_parms *parms)
+{
+ int rc;
+ uint16_t idx;
+ struct tf_session *tfs;
+ struct tf_dev_info *dev;
+ struct tf_tbl_sram_get_info_parms iparms = { 0 };
+ struct tf_sram_mgr_alloc_parms aparms = { 0 };
+ struct tbl_rm_db *tbl_db;
+ void *tbl_db_ptr = NULL;
+ void *sram_handle = NULL;
+
+ TF_CHECK_PARMS2(tfp, parms);
+
+ /* Retrieve the session information */
+ rc = tf_session_get(tfp, &tfs, &dev);
+ if (rc)
+ return rc;
+
+ rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get tbl_db from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
+
+ rc = tf_session_get_sram_db(tfp, &sram_handle);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get sram_handle from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ iparms.rm_db = tbl_db->tbl_db[parms->dir];
+ iparms.dir = parms->dir;
+ iparms.tbl_type = parms->type;
+
+ rc = tf_tbl_sram_get_info(&iparms);
+
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get SRAM info %s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type));
+ return rc;
+ }
+
+ aparms.dir = parms->dir;
+ aparms.bank_id = iparms.bank_id;
+ aparms.slice_size = iparms.slice_size;
+ aparms.sram_offset = &idx;
+ aparms.tbl_type = parms->type;
+ aparms.rm_db = tbl_db->tbl_db[parms->dir];
+
+ rc = tf_sram_mgr_alloc(sram_handle, &aparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to allocate SRAM table:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type));
+ return rc;
+ }
+ *parms->idx = idx;
+
+#if (DBG_SRAM == 1)
+ {
+ struct tf_sram_mgr_dump_parms dparms;
+
+ dparms.dir = parms->dir;
+ dparms.bank_id = iparms.bank_id;
+ dparms.slice_size = iparms.slice_size;
+
+ rc = tf_sram_mgr_dump(sram_handle, &dparms);
+ }
+#endif
+
+ return rc;
+}
+
+int
+tf_tbl_sram_free(struct tf *tfp __rte_unused,
+ struct tf_tbl_free_parms *parms)
+{
+ int rc;
+ struct tf_session *tfs;
+ struct tf_dev_info *dev;
+ struct tbl_rm_db *tbl_db;
+ void *tbl_db_ptr = NULL;
+ struct tf_tbl_sram_get_info_parms iparms = { 0 };
+ struct tf_sram_mgr_free_parms fparms = { 0 };
+ struct tf_sram_mgr_is_allocated_parms aparms = { 0 };
+ bool allocated = false;
+ void *sram_handle = NULL;
+
+ TF_CHECK_PARMS2(tfp, parms);
+
+ /* Retrieve the session information */
+ rc = tf_session_get(tfp, &tfs, &dev);
+ if (rc)
+ return rc;
+
+ rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get em_ext_db from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
+
+ rc = tf_session_get_sram_db(tfp, &sram_handle);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get sram_handle from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ iparms.rm_db = tbl_db->tbl_db[parms->dir];
+ iparms.dir = parms->dir;
+ iparms.tbl_type = parms->type;
+
+ rc = tf_tbl_sram_get_info(&iparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get table info:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type));
+ return rc;
+ }
+
+#if (DBG_SRAM == 1)
+ {
+ struct tf_sram_mgr_dump_parms dparms;
+
+ printf("%s: %s: %s\n", tf_dir_2_str(parms->dir),
+ tf_sram_slice_2_str(iparms.slice_size),
+ tf_sram_bank_2_str(iparms.bank_id));
+
+ dparms.dir = parms->dir;
+ dparms.bank_id = iparms.bank_id;
+ dparms.slice_size = iparms.slice_size;
+
+ rc = tf_sram_mgr_dump(sram_handle, &dparms);
+ }
+#endif
+
+ aparms.sram_offset = parms->idx;
+ aparms.slice_size = iparms.slice_size;
+ aparms.bank_id = iparms.bank_id;
+ aparms.dir = parms->dir;
+ aparms.is_allocated = &allocated;
+
+ rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
+ if (rc || !allocated) {
+ TFP_DRV_LOG(ERR,
+ "%s: Free of invalid entry:%s idx(%d):(%s)\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->idx,
+ strerror(-rc));
+ rc = -ENOMEM;
+ return rc;
+ }
+
+ fparms.rm_db = tbl_db->tbl_db[parms->dir];
+ fparms.tbl_type = parms->type;
+ fparms.sram_offset = parms->idx;
+ fparms.slice_size = iparms.slice_size;
+ fparms.bank_id = iparms.bank_id;
+ fparms.dir = parms->dir;
+#if (STATS_CLEAR_ON_READ_SUPPORT == 0)
+ fparms.tfp = tfp;
+#endif
+ rc = tf_sram_mgr_free(sram_handle, &fparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to free entry:%s idx(%d)\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->idx);
+ return rc;
+ }
+
+
+#if (DBG_SRAM == 1)
+ {
+ struct tf_sram_mgr_dump_parms dparms;
+
+ printf("%s: %s: %s\n", tf_dir_2_str(parms->dir),
+ tf_sram_slice_2_str(iparms.slice_size),
+ tf_sram_bank_2_str(iparms.bank_id));
+
+ dparms.dir = parms->dir;
+ dparms.bank_id = iparms.bank_id;
+ dparms.slice_size = iparms.slice_size;
+
+ rc = tf_sram_mgr_dump(sram_handle, &dparms);
+ }
+#endif
+ return rc;
+}
+
+int
+tf_tbl_sram_set(struct tf *tfp,
+ struct tf_tbl_set_parms *parms)
+{
+ int rc;
+ bool allocated = 0;
+ uint16_t hcapi_type;
+ struct tf_rm_get_hcapi_parms hparms = { 0 };
+ struct tf_session *tfs;
+ struct tf_dev_info *dev;
+ struct tbl_rm_db *tbl_db;
+ void *tbl_db_ptr = NULL;
+ struct tf_tbl_sram_get_info_parms iparms = { 0 };
+ struct tf_sram_mgr_is_allocated_parms aparms = { 0 };
+ void *sram_handle = NULL;
+
+
+ TF_CHECK_PARMS3(tfp, parms, parms->data);
+
+ /* Retrieve the session information */
+ rc = tf_session_get(tfp, &tfs, &dev);
+ if (rc)
+ return rc;
+
+ rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get em_ext_db from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
+
+ rc = tf_session_get_sram_db(tfp, &sram_handle);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get sram_handle from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ iparms.rm_db = tbl_db->tbl_db[parms->dir];
+ iparms.dir = parms->dir;
+ iparms.tbl_type = parms->type;
+
+ rc = tf_tbl_sram_get_info(&iparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get table info:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type));
+ return rc;
+ }
+
+ aparms.sram_offset = parms->idx;
+ aparms.slice_size = iparms.slice_size;
+ aparms.bank_id = iparms.bank_id;
+ aparms.dir = parms->dir;
+ aparms.is_allocated = &allocated;
+ rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
+ if (rc || !allocated) {
+ TFP_DRV_LOG(ERR,
+ "%s: Entry not allocated:%s idx(%d):(%s)\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->idx,
+ strerror(-rc));
+ rc = -ENOMEM;
+ return rc;
+ }
+
+ /* Set the entry */
+ hparms.rm_db = tbl_db->tbl_db[parms->dir];
+ hparms.subtype = parms->type;
+ hparms.hcapi_type = &hcapi_type;
+ rc = tf_rm_get_hcapi_type(&hparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Failed type lookup, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ strerror(-rc));
+ return rc;
+ }
+
+ rc = tf_msg_set_tbl_entry(tfp,
+ parms->dir,
+ hcapi_type,
+ parms->data_sz_in_bytes,
+ parms->data,
+ parms->idx);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Set failed, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ strerror(-rc));
+ return rc;
+ }
+ return rc;
+}
+
+int
+tf_tbl_sram_get(struct tf *tfp,
+ struct tf_tbl_get_parms *parms)
+{
+ int rc;
+ uint16_t hcapi_type;
+ bool allocated = 0;
+ struct tf_rm_get_hcapi_parms hparms = { 0 };
+ struct tf_session *tfs;
+ struct tf_dev_info *dev;
+ struct tbl_rm_db *tbl_db;
+ void *tbl_db_ptr = NULL;
+ struct tf_tbl_sram_get_info_parms iparms = { 0 };
+ struct tf_sram_mgr_is_allocated_parms aparms = { 0 };
+ void *sram_handle = NULL;
+
+ TF_CHECK_PARMS3(tfp, parms, parms->data);
+
+ /* Retrieve the session information */
+ rc = tf_session_get(tfp, &tfs, &dev);
+ if (rc)
+ return rc;
+
+ rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get em_ext_db from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
+
+ rc = tf_session_get_sram_db(tfp, &sram_handle);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get sram_handle from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ iparms.rm_db = tbl_db->tbl_db[parms->dir];
+ iparms.dir = parms->dir;
+ iparms.tbl_type = parms->type;
+
+ rc = tf_tbl_sram_get_info(&iparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get table info:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type));
+ return rc;
+ }
+
+ aparms.sram_offset = parms->idx;
+ aparms.slice_size = iparms.slice_size;
+ aparms.bank_id = iparms.bank_id;
+ aparms.dir = parms->dir;
+ aparms.is_allocated = &allocated;
+
+ rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
+ if (rc || !allocated) {
+ TFP_DRV_LOG(ERR,
+ "%s: Entry not allocated:%s idx(%d):(%s)\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->idx,
+ strerror(-rc));
+ rc = -ENOMEM;
+ return rc;
+ }
+
+ /* Get the entry */
+ hparms.rm_db = tbl_db->tbl_db[parms->dir];
+ hparms.subtype = parms->type;
+ hparms.hcapi_type = &hcapi_type;
+ rc = tf_rm_get_hcapi_type(&hparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Failed type lookup, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ strerror(-rc));
+ return rc;
+ }
+
+ /* Get the entry */
+ rc = tf_msg_get_tbl_entry(tfp,
+ parms->dir,
+ hcapi_type,
+ parms->data_sz_in_bytes,
+ parms->data,
+ parms->idx);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Get failed, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ strerror(-rc));
+ return rc;
+ }
+ return rc;
+}
+
+int
+tf_tbl_sram_bulk_get(struct tf *tfp,
+ struct tf_tbl_get_bulk_parms *parms)
+{
+ int rc;
+ uint16_t hcapi_type;
+ struct tf_rm_get_hcapi_parms hparms = { 0 };
+ struct tf_tbl_sram_get_info_parms iparms = { 0 };
+ struct tf_session *tfs;
+ struct tf_dev_info *dev;
+ struct tbl_rm_db *tbl_db;
+ void *tbl_db_ptr = NULL;
+ uint16_t idx;
+ struct tf_sram_mgr_is_allocated_parms aparms = { 0 };
+ bool allocated = false;
+ void *sram_handle = NULL;
+
+ TF_CHECK_PARMS2(tfp, parms);
+
+ /* Retrieve the session information */
+ rc = tf_session_get(tfp, &tfs, &dev);
+ if (rc)
+ return rc;
+
+ rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get em_ext_db from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+ tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
+
+ rc = tf_session_get_sram_db(tfp, &sram_handle);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to get sram_handle from session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ iparms.rm_db = tbl_db->tbl_db[parms->dir];
+ iparms.dir = parms->dir;
+ iparms.tbl_type = parms->type;
+
+ rc = tf_tbl_sram_get_info(&iparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get table info:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type));
+ return rc;
+ }
+
+ /* Validate the start offset and the end offset is allocated
+ * This API is only used for statistics. 8 Byte entry allocation
+ * is used to verify
+ */
+ aparms.sram_offset = parms->starting_idx;
+ aparms.slice_size = iparms.slice_size;
+ aparms.bank_id = iparms.bank_id;
+ aparms.dir = parms->dir;
+ aparms.is_allocated = &allocated;
+ rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
+ if (rc || !allocated) {
+ TFP_DRV_LOG(ERR,
+ "%s: Entry not allocated:%s starting_idx(%d):(%s)\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->starting_idx,
+ strerror(-rc));
+ rc = -ENOMEM;
+ return rc;
+ }
+ idx = parms->starting_idx + parms->num_entries - 1;
+ aparms.sram_offset = idx;
+ rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
+ if (rc || !allocated) {
+ TFP_DRV_LOG(ERR,
+ "%s: Entry not allocated:%s last_idx(%d):(%s)\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ idx,
+ strerror(-rc));
+ rc = -ENOMEM;
+ return rc;
+ }
+
+ hparms.rm_db = tbl_db->tbl_db[parms->dir];
+ hparms.subtype = parms->type;
+ hparms.hcapi_type = &hcapi_type;
+ rc = tf_rm_get_hcapi_type(&hparms);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Failed type lookup, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ strerror(-rc));
+ return rc;
+ }
+
+ /* Get the entries */
+ rc = tf_msg_bulk_get_tbl_entry(tfp,
+ parms->dir,
+ hcapi_type,
+ parms->starting_idx,
+ parms->num_entries,
+ parms->entry_sz_in_bytes,
+ parms->physical_mem_addr);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s, Bulk get failed, type:%s, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ strerror(-rc));
+ }
+ return rc;
+}
diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.h b/drivers/net/bnxt/tf_core/tf_tbl_sram.h
new file mode 100644
index 0000000000..32001e34a9
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.h
@@ -0,0 +1,154 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019-2021 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef TF_TBL_SRAM_H_
+#define TF_TBL_SRAM_H_
+
+#include "tf_core.h"
+#include "stack.h"
+
+
+/**
+ * The SRAM Table module provides processing of managed SRAM types.
+ */
+
+
+/**
+ * @page tblsram SRAM Table
+ *
+ * @ref tf_tbl_sram_bind
+ *
+ * @ref tf_tbl_sram_unbind
+ *
+ * @ref tf_tbl_sram_alloc
+ *
+ * @ref tf_tbl_sram_free
+ *
+ * @ref tf_tbl_sram_set
+ *
+ * @ref tf_tbl_sram_get
+ *
+ * @ref tf_tbl_sram_bulk_get
+ */
+
+/**
+ * Initializes the Table module with the requested DBs. Must be
+ * invoked as the first thing before any of the access functions.
+ *
+ * [in] tfp
+ * Pointer to TF handle, used for HCAPI communication
+ *
+ * [in] parms
+ * Pointer to Table configuration parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_tbl_sram_bind(struct tf *tfp);
+
+/**
+ * Cleans up the private DBs and releases all the data.
+ *
+ * [in] tfp
+ * Pointer to TF handle, used for HCAPI communication
+ *
+ * [in] parms
+ * Pointer to parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_tbl_sram_unbind(struct tf *tfp);
+
+/**
+ * Allocates the requested table type from the internal RM DB.
+ *
+ * [in] tfp
+ * Pointer to TF handle, used for HCAPI communication
+ *
+ * [in] parms
+ * Pointer to Table allocation parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_tbl_sram_alloc(struct tf *tfp,
+ struct tf_tbl_alloc_parms *parms);
+
+/**
+ * Free's the requested table type and returns it to the DB. If shadow
+ * DB is enabled its searched first and if found the element refcount
+ * is decremented. If refcount goes to 0 then its returned to the
+ * table type DB.
+ *
+ * [in] tfp
+ * Pointer to TF handle, used for HCAPI communication
+ *
+ * [in] parms
+ * Pointer to Table free parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_tbl_sram_free(struct tf *tfp,
+ struct tf_tbl_free_parms *parms);
+
+
+/**
+ * Configures the requested element by sending a firmware request which
+ * then installs it into the device internal structures.
+ *
+ * [in] tfp
+ * Pointer to TF handle, used for HCAPI communication
+ *
+ * [in] parms
+ * Pointer to Table set parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_tbl_sram_set(struct tf *tfp,
+ struct tf_tbl_set_parms *parms);
+
+/**
+ * Retrieves the requested element by sending a firmware request to get
+ * the element.
+ *
+ * [in] tfp
+ * Pointer to TF handle, used for HCAPI communication
+ *
+ * [in] parms
+ * Pointer to Table get parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_tbl_sram_get(struct tf *tfp,
+ struct tf_tbl_get_parms *parms);
+
+/**
+ * Retrieves bulk block of elements by sending a firmware request to
+ * get the elements.
+ *
+ * [in] tfp
+ * Pointer to TF handle, used for HCAPI communication
+ *
+ * [in] parms
+ * Pointer to Table get bulk parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_tbl_sram_bulk_get(struct tf *tfp,
+ struct tf_tbl_get_bulk_parms *parms);
+
+#endif /* TF_TBL_SRAM_H */
diff --git a/drivers/net/bnxt/tf_core/tf_tcam.c b/drivers/net/bnxt/tf_core/tf_tcam.c
index 45206c5992..806af3070a 100644
--- a/drivers/net/bnxt/tf_core/tf_tcam.c
+++ b/drivers/net/bnxt/tf_core/tf_tcam.c
@@ -43,7 +43,7 @@ tf_tcam_bind(struct tf *tfp,
struct tf_shadow_tcam_free_db_parms fshadow;
struct tf_shadow_tcam_cfg_parms shadow_cfg;
struct tf_shadow_tcam_create_db_parms shadow_cdb;
- uint16_t num_slices = 1;
+ uint16_t num_slices = parms->wc_num_slices;
struct tf_session *tfs;
struct tf_dev_info *dev;
struct tcam_rm_db *tcam_db;
@@ -61,7 +61,7 @@ tf_tcam_bind(struct tf *tfp,
if (rc)
return rc;
- if (dev->ops->tf_dev_get_tcam_slice_info == NULL) {
+ if (dev->ops->tf_dev_set_tcam_slice_info == NULL) {
rc = -EOPNOTSUPP;
TFP_DRV_LOG(ERR,
"Operation not supported, rc:%s\n",
@@ -69,10 +69,8 @@ tf_tcam_bind(struct tf *tfp,
return rc;
}
- rc = dev->ops->tf_dev_get_tcam_slice_info(tfp,
- TF_TCAM_TBL_TYPE_WC_TCAM,
- 0,
- &num_slices);
+ rc = dev->ops->tf_dev_set_tcam_slice_info(tfp,
+ num_slices);
if (rc)
return rc;
diff --git a/drivers/net/bnxt/tf_core/tf_tcam.h b/drivers/net/bnxt/tf_core/tf_tcam.h
index bed17af6ae..b1e7a92b0b 100644
--- a/drivers/net/bnxt/tf_core/tf_tcam.h
+++ b/drivers/net/bnxt/tf_core/tf_tcam.h
@@ -12,6 +12,9 @@
* The TCAM module provides processing of Internal TCAM types.
*/
+/* Number of slices per row for WC TCAM */
+extern uint16_t g_wc_num_slices_per_row;
+
/**
* TCAM configuration parameters
*/
@@ -36,6 +39,10 @@ struct tf_tcam_cfg_parms {
* Session resource allocations
*/
struct tf_session_resources *resources;
+ /**
+ * WC number of slices per row.
+ */
+ enum tf_wc_num_slice wc_num_slices;
};
/**
diff --git a/drivers/net/bnxt/tf_core/tf_tcam_shared.c b/drivers/net/bnxt/tf_core/tf_tcam_shared.c
index 83b6fbd5fb..c120c6f577 100644
--- a/drivers/net/bnxt/tf_core/tf_tcam_shared.c
+++ b/drivers/net/bnxt/tf_core/tf_tcam_shared.c
@@ -279,18 +279,6 @@ tf_tcam_shared_bind(struct tf *tfp,
if (rc)
return rc;
- rc = tf_tcam_shared_get_slices(tfp,
- dev,
- &num_slices);
- if (rc)
- return rc;
-
- if (num_slices > 1) {
- TFP_DRV_LOG(ERR,
- "Only single slice supported\n");
- return -EOPNOTSUPP;
- }
-
tf_tcam_shared_create_db(&tcam_shared_wc);
@@ -330,6 +318,18 @@ tf_tcam_shared_bind(struct tf *tfp,
tf_session_set_tcam_shared_db(tfp, (void *)tcam_shared_wc);
}
+
+ rc = tf_tcam_shared_get_slices(tfp,
+ dev,
+ &num_slices);
+ if (rc)
+ return rc;
+
+ if (num_slices > 1) {
+ TFP_DRV_LOG(ERR,
+ "Only single slice supported\n");
+ return -EOPNOTSUPP;
+ }
}
done:
return rc;
@@ -972,9 +972,9 @@ tf_tcam_shared_move_entry(struct tf *tfp,
sparms.idx = dphy_idx;
sparms.key = gparms.key;
sparms.mask = gparms.mask;
- sparms.key_size = gparms.key_size;
+ sparms.key_size = key_sz_bytes;
sparms.result = gparms.result;
- sparms.result_size = gparms.result_size;
+ sparms.result_size = remap_sz_bytes;
rc = tf_msg_tcam_entry_set(tfp, dev, &sparms);
if (rc) {
diff --git a/drivers/net/bnxt/tf_core/tf_util.c b/drivers/net/bnxt/tf_core/tf_util.c
index d100399d0a..c1b9be0755 100644
--- a/drivers/net/bnxt/tf_core/tf_util.c
+++ b/drivers/net/bnxt/tf_core/tf_util.c
@@ -76,6 +76,8 @@ tf_tbl_type_2_str(enum tf_tbl_type tbl_type)
switch (tbl_type) {
case TF_TBL_TYPE_FULL_ACT_RECORD:
return "Full Action record";
+ case TF_TBL_TYPE_COMPACT_ACT_RECORD:
+ return "Compact Action record";
case TF_TBL_TYPE_MCAST_GROUPS:
return "Multicast Groups";
case TF_TBL_TYPE_ACT_ENCAP_8B:
@@ -96,6 +98,14 @@ tf_tbl_type_2_str(enum tf_tbl_type tbl_type)
return "Stats 64B";
case TF_TBL_TYPE_ACT_MODIFY_IPV4:
return "Modify IPv4";
+ case TF_TBL_TYPE_ACT_MODIFY_8B:
+ return "Modify 8B";
+ case TF_TBL_TYPE_ACT_MODIFY_16B:
+ return "Modify 16B";
+ case TF_TBL_TYPE_ACT_MODIFY_32B:
+ return "Modify 32B";
+ case TF_TBL_TYPE_ACT_MODIFY_64B:
+ return "Modify 64B";
case TF_TBL_TYPE_METER_PROF:
return "Meter Profile";
case TF_TBL_TYPE_METER_INST:
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index dbf85e4eda..183bae66c5 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -384,6 +384,7 @@ ulp_ctx_shared_session_open(struct bnxt *bp,
size_t copy_nbytes;
uint32_t ulp_dev_id = BNXT_ULP_DEVICE_ID_LAST;
int32_t rc = 0;
+ uint8_t app_id;
/* only perform this if shared session is enabled. */
if (!bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx))
@@ -422,6 +423,12 @@ ulp_ctx_shared_session_open(struct bnxt *bp,
if (rc)
return rc;
+ rc = bnxt_ulp_cntxt_app_id_get(bp->ulp_ctx, &app_id);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Unable to get the app id from ulp.\n");
+ return -EINVAL;
+ }
+
rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &ulp_dev_id);
if (rc) {
BNXT_TF_DBG(ERR, "Unable to get device id from ulp.\n");
@@ -445,6 +452,10 @@ ulp_ctx_shared_session_open(struct bnxt *bp,
parms.shadow_copy = true;
parms.bp = bp;
+ if (app_id == 0 || app_id == 3)
+ parms.wc_num_slices = TF_WC_TCAM_2_SLICE_PER_ROW;
+ else
+ parms.wc_num_slices = TF_WC_TCAM_1_SLICE_PER_ROW;
/*
* Open the session here, but the collect the resources during the
@@ -516,6 +527,7 @@ ulp_ctx_session_open(struct bnxt *bp,
struct tf_open_session_parms params;
struct tf_session_resources *resources;
uint32_t ulp_dev_id = BNXT_ULP_DEVICE_ID_LAST;
+ uint8_t app_id;
memset(¶ms, 0, sizeof(params));
@@ -529,6 +541,12 @@ ulp_ctx_session_open(struct bnxt *bp,
params.shadow_copy = true;
+ rc = bnxt_ulp_cntxt_app_id_get(bp->ulp_ctx, &app_id);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Unable to get the app id from ulp.\n");
+ return -EINVAL;
+ }
+
rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &ulp_dev_id);
if (rc) {
BNXT_TF_DBG(ERR, "Unable to get device id from ulp.\n");
@@ -556,6 +574,11 @@ ulp_ctx_session_open(struct bnxt *bp,
return rc;
params.bp = bp;
+ if (app_id == 0 || app_id == 3)
+ params.wc_num_slices = TF_WC_TCAM_2_SLICE_PER_ROW;
+ else
+ params.wc_num_slices = TF_WC_TCAM_1_SLICE_PER_ROW;
+
rc = tf_open_session(&bp->tfp, ¶ms);
if (rc) {
BNXT_TF_DBG(ERR, "Failed to open TF session - %s, rc = %d\n",
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v4 05/13] net/bnxt: add flow template support for Thor
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 " Venkat Duvvuru
` (3 preceding siblings ...)
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 04/13] net/bnxt: add SRAM manager model Venkat Duvvuru
@ 2021-09-20 7:42 ` Venkat Duvvuru
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 06/13] net/bnxt: add support for tunnel offload API Venkat Duvvuru
` (8 subsequent siblings)
13 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-20 7:42 UTC (permalink / raw)
To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Template adds non-VFR based support for testpmd with:
matches to include
- DMAC, SIP, DIP, Proto, Sport, Dport
- SIP, DIP, Proto, Sport, Dport
actions:
- count, drop
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/tf_ulp/bnxt_tf_common.h | 6 +
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 36 +++---
drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 12 ++
.../bnxt/tf_ulp/generic_templates/meson.build | 3 +
.../ulp_template_db_thor_class.c | 1 -
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 120 +++++++++++++++++-
drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 26 +++-
drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c | 5 +
drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 111 +++++++++++++++-
drivers/net/bnxt/tf_ulp/ulp_matcher.c | 13 ++
drivers/net/bnxt/tf_ulp/ulp_port_db.c | 15 ++-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 9 +-
drivers/net/bnxt/tf_ulp/ulp_tun.c | 20 +++
drivers/net/bnxt/tf_ulp/ulp_utils.c | 8 +-
16 files changed, 348 insertions(+), 41 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
index f59da41e54..e0ebed3fed 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
@@ -13,6 +13,12 @@
#define BNXT_TF_DBG(lvl, fmt, args...) PMD_DRV_LOG(lvl, fmt, ## args)
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#define BNXT_TF_INF(fmt, args...) PMD_DRV_LOG(INFO, fmt, ## args)
+#else
+#define BNXT_TF_INF(fmt, args...)
+#endif
+
#define BNXT_ULP_EM_FLOWS 8192
#define BNXT_ULP_1M_FLOWS 1000000
#define BNXT_EEM_RX_GLOBAL_ID_MASK (BNXT_ULP_1M_FLOWS - 1)
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 183bae66c5..475c7a6cdf 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -698,6 +698,11 @@ ulp_eem_tbl_scope_init(struct bnxt *bp)
rc);
return rc;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+ BNXT_TF_DBG(DEBUG, "TableScope=0x%0x %d\n",
+ params.tbl_scope_id,
+ params.tbl_scope_id);
+#endif
rc = bnxt_ulp_cntxt_tbl_scope_id_set(bp->ulp_ctx, params.tbl_scope_id);
if (rc) {
BNXT_TF_DBG(ERR, "Unable to set table scope id\n");
@@ -825,6 +830,8 @@ ulp_ctx_init(struct bnxt *bp,
goto error_deinit;
}
+ /* TODO: For now we are overriding to APP:1 on this branch*/
+ bp->app_id = 1;
rc = bnxt_ulp_cntxt_app_id_set(bp->ulp_ctx, bp->app_id);
if (rc) {
BNXT_TF_DBG(ERR, "Unable to set app_id for ULP init.\n");
@@ -838,11 +845,6 @@ ulp_ctx_init(struct bnxt *bp,
goto error_deinit;
}
- if (devid == BNXT_ULP_DEVICE_ID_THOR) {
- ulp_data->ulp_flags &= ~BNXT_ULP_VF_REP_ENABLED;
- BNXT_TF_DBG(ERR, "Enabled non-VFR mode\n");
- }
-
/*
* Shared session must be created before first regular session but after
* the ulp_ctx is valid.
@@ -902,7 +904,7 @@ ulp_dparms_init(struct bnxt *bp, struct bnxt_ulp_context *ulp_ctx)
dparms->ext_flow_db_num_entries = bp->max_num_kflows * 1024;
/* GFID = 2 * num_flows */
dparms->mark_db_gfid_entries = dparms->ext_flow_db_num_entries * 2;
- BNXT_TF_DBG(DEBUG, "Set the number of flows = %"PRIu64"\n",
+ BNXT_TF_DBG(DEBUG, "Set the number of flows = %" PRIu64 "\n",
dparms->ext_flow_db_num_entries);
return 0;
@@ -1393,17 +1395,13 @@ bnxt_ulp_port_init(struct bnxt *bp)
uint32_t ulp_flags;
int32_t rc = 0;
+ if (!bp || !BNXT_TRUFLOW_EN(bp))
+ return rc;
+
if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
BNXT_TF_DBG(ERR,
"Skip ulp init for port: %d, not a TVF or PF\n",
- bp->eth_dev->data->port_id);
- return rc;
- }
-
- if (!BNXT_TRUFLOW_EN(bp)) {
- BNXT_TF_DBG(DEBUG,
- "Skip ulp init for port: %d, truflow is not enabled\n",
- bp->eth_dev->data->port_id);
+ bp->eth_dev->data->port_id);
return rc;
}
@@ -1524,6 +1522,9 @@ bnxt_ulp_port_deinit(struct bnxt *bp)
struct rte_pci_device *pci_dev;
struct rte_pci_addr *pci_addr;
+ if (!BNXT_TRUFLOW_EN(bp))
+ return;
+
if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
BNXT_TF_DBG(ERR,
"Skip ULP deinit port:%d, not a TVF or PF\n",
@@ -1531,13 +1532,6 @@ bnxt_ulp_port_deinit(struct bnxt *bp)
return;
}
- if (!BNXT_TRUFLOW_EN(bp)) {
- BNXT_TF_DBG(DEBUG,
- "Skip ULP deinit for port:%d, truflow is not enabled\n",
- bp->eth_dev->data->port_id);
- return;
- }
-
if (!bp->ulp_ctx) {
BNXT_TF_DBG(DEBUG, "ulp ctx already de-allocated\n");
return;
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
index 19e9dba356..238b1d9657 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
@@ -13,6 +13,9 @@
#include "ulp_port_db.h"
#include "ulp_ha_mgr.h"
#include <rte_malloc.h>
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#include "ulp_template_debug_proto.h"
+#endif
static int32_t
bnxt_ulp_flow_validate_args(const struct rte_flow_attr *attr,
@@ -222,6 +225,15 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
else if (ret == BNXT_TF_RC_FID)
goto return_fid;
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER
+ /* Dump the rte flow pattern */
+ ulp_parser_hdr_info_dump(¶ms);
+ /* Dump the rte flow action */
+ ulp_parser_act_info_dump(¶ms);
+#endif
+#endif
+
ret = ulp_matcher_pattern_match(¶ms, ¶ms.class_id);
if (ret != BNXT_TF_RC_SUCCESS)
goto free_fid;
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/meson.build b/drivers/net/bnxt/tf_ulp/generic_templates/meson.build
index b1e7b8cc32..4ace838a3c 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/meson.build
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/meson.build
@@ -2,7 +2,10 @@
# Copyright(c) 2018 Intel Corporation
# Copyright(c) 2020 Broadcom
+#Include the folder for headers
includes += include_directories('.')
+
+#Add the source files
sources += files(
'ulp_template_db_class.c',
'ulp_template_db_act.c',
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
index 83f6152700..e342f340d9 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
@@ -6104,4 +6104,3 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.ident_bit_pos = 29
}
};
-
diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
index 13f71ed83b..22c51976ac 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
@@ -35,7 +35,7 @@ ulp_fc_mgr_shadow_mem_alloc(struct hw_fc_mem_info *parms, int size)
rte_mem_lock_page(parms->mem_va);
parms->mem_pa = (void *)(uintptr_t)rte_mem_virt2phy(parms->mem_va);
- if (parms->mem_pa == (void *)(uintptr_t)RTE_BAD_IOVA) {
+ if (parms->mem_pa == (void *)RTE_BAD_IOVA) {
BNXT_TF_DBG(ERR, "Allocate failed mem_pa\n");
return -ENOMEM;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
index ab6013f0e3..016c86fb6e 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
@@ -116,7 +116,7 @@ ulp_flow_db_resource_func_get(struct ulp_fdb_resource_info *res_info)
func = (((res_info->nxt_resource_idx & ULP_FLOW_DB_RES_FUNC_MASK) >>
ULP_FLOW_DB_RES_FUNC_BITS) << ULP_FLOW_DB_RES_FUNC_UPPER);
- /* The resource func is split into upper and lower */
+ /* The reource func is split into upper and lower */
if (func & ULP_FLOW_DB_RES_FUNC_NEED_LOWER)
return (func | res_info->resource_func_lower);
return func;
@@ -654,6 +654,9 @@ ulp_flow_db_fid_alloc(struct bnxt_ulp_context *ulp_ctxt,
if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR)
ulp_flow_db_func_id_set(flow_db, *fid, func_id);
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+ BNXT_TF_DBG(ERR, "flow_id = %u:%u allocated\n", flow_type, *fid);
+#endif
/* return success */
return 0;
}
@@ -766,7 +769,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt,
* flow_type [in] Specify it is regular or default flow
* fid [in] The index to the flow entry
* params [in/out] The contents to be copied into params.
- * Only the critical_resource needs to be set by the caller.
+ * Onlythe critical_resource needs to be set by the caller.
*
* Returns 0 on success and negative on failure.
*/
@@ -937,6 +940,9 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt,
ulp_clear_tun_inner_entry(tun_tbl, fid);
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+ BNXT_TF_DBG(ERR, "flow_id = %u:%u freed\n", flow_type, fid);
+#endif
/* all good, return success */
return 0;
}
@@ -1921,3 +1927,113 @@ void ulp_flow_db_shared_session_set(struct ulp_flow_db_res_params *res,
if (res && (shared & BNXT_ULP_SHARED_SESSION_YES))
res->fdb_flags |= ULP_FDB_FLAG_SHARED_SESSION;
}
+
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+/*
+ * Dump the entry details
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ *
+ * returns none
+ */
+static void ulp_flow_db_res_dump(struct ulp_fdb_resource_info *r,
+ uint32_t *nxt_res)
+{
+ uint8_t res_func = ulp_flow_db_resource_func_get(r);
+
+ BNXT_TF_DBG(DEBUG, "Resource func = %x, nxt_resource_idx = %x\n",
+ res_func, (ULP_FLOW_DB_RES_NXT_MASK & r->nxt_resource_idx));
+ if (res_func == BNXT_ULP_RESOURCE_FUNC_EM_TABLE)
+ BNXT_TF_DBG(DEBUG, "EM Handle = 0x%016" PRIX64 "\n",
+ r->resource_em_handle);
+ else
+ BNXT_TF_DBG(DEBUG, "Handle = 0x%08x\n", r->resource_hndl);
+
+ *nxt_res = 0;
+ ULP_FLOW_DB_RES_NXT_SET(*nxt_res,
+ r->nxt_resource_idx);
+}
+
+/*
+ * Dump the flow entry details
+ *
+ * flow_db [in] Ptr to flow db
+ * fid [in] flow id
+ *
+ * returns none
+ */
+void
+ulp_flow_db_debug_fid_dump(struct bnxt_ulp_flow_db *flow_db, uint32_t fid)
+{
+ struct ulp_fdb_resource_info *r;
+ struct bnxt_ulp_flow_tbl *flow_tbl;
+ uint32_t nxt_res = 0;
+ uint32_t def_flag = 0, reg_flag = 0;
+
+ flow_tbl = &flow_db->flow_tbl;
+ if (ulp_flow_db_active_flows_bit_is_set(flow_db,
+ BNXT_ULP_FDB_TYPE_REGULAR, fid))
+ reg_flag = 1;
+ if (ulp_flow_db_active_flows_bit_is_set(flow_db,
+ BNXT_ULP_FDB_TYPE_DEFAULT, fid))
+ def_flag = 1;
+
+ if (reg_flag && def_flag)
+ BNXT_TF_DBG(DEBUG, "RID = %u\n", fid);
+ else if (reg_flag)
+ BNXT_TF_DBG(DEBUG, "Regular fid = %u and func id = %u\n",
+ fid, flow_db->func_id_tbl[fid]);
+ else if (def_flag)
+ BNXT_TF_DBG(DEBUG, "Default fid = %u\n", fid);
+ else
+ return;
+ /* iterate the resource */
+ nxt_res = fid;
+ do {
+ r = &flow_tbl->flow_resources[nxt_res];
+ ulp_flow_db_res_dump(r, &nxt_res);
+ } while (nxt_res);
+}
+
+/*
+ * Dump the flow database entry details
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ * flow_id [in] if zero then all fids are dumped.
+ *
+ * returns none
+ */
+int32_t ulp_flow_db_debug_dump(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t flow_id)
+{
+ struct bnxt_ulp_flow_db *flow_db;
+ struct bnxt_ulp_flow_tbl *flow_tbl;
+ uint32_t fid;
+
+ if (!ulp_ctxt || !ulp_ctxt->cfg_data) {
+ BNXT_TF_DBG(ERR, "Invalid Arguments\n");
+ return -EINVAL;
+ }
+ flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
+ if (!flow_db) {
+ BNXT_TF_DBG(ERR, "Invalid Arguments\n");
+ return -EINVAL;
+ }
+
+ flow_tbl = &flow_db->flow_tbl;
+ if (flow_id) {
+ ulp_flow_db_debug_fid_dump(flow_db, flow_id);
+ return 0;
+ }
+
+ BNXT_TF_DBG(DEBUG, "Dump flows = %u:%u\n",
+ flow_tbl->num_flows,
+ flow_tbl->num_resources);
+ BNXT_TF_DBG(DEBUG, "Head_index = %u, Tail_index = %u\n",
+ flow_tbl->head_index, flow_tbl->tail_index);
+ for (fid = 1; fid < flow_tbl->num_flows; fid++)
+ ulp_flow_db_debug_fid_dump(flow_db, fid);
+ BNXT_TF_DBG(DEBUG, "Done.\n");
+ return 0;
+}
+#endif
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
index 67afca8872..0ddfa6f66d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
@@ -18,7 +18,7 @@
/*
* Structure for the flow database resource information
- * The below structure is based on the below partitions
+ * The below structure is based on the below paritions
* nxt_resource_idx = dir[31],resource_func_upper[30:28],nxt_resource_idx[27:0]
* If resource_func is EM_TBL then use resource_em_handle.
* Else the other part of the union is used and
@@ -417,4 +417,28 @@ ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt);
void ulp_flow_db_shared_session_set(struct ulp_flow_db_res_params *res,
enum bnxt_ulp_shared_session shared);
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+/*
+ * Dump the flow entry details
+ *
+ * flow_db [in] Ptr to flow db
+ * fid [in] flow id
+ *
+ * returns none
+ */
+void
+ulp_flow_db_debug_fid_dump(struct bnxt_ulp_flow_db *flow_db, uint32_t fid);
+
+/*
+ * Dump the flow database entry details
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ * flow_id [in] if zero then all fids are dumped.
+ *
+ * returns none
+ */
+int32_t ulp_flow_db_debug_dump(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t flow_id);
+#endif
+
#endif /* _ULP_FLOW_DB_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
index 3c1af0b007..c6b2b1675d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
@@ -10,6 +10,11 @@
#include "ulp_mapper.h"
#include "ulp_flow_db.h"
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#include "ulp_template_debug_proto.h"
+#include "ulp_tf_debug.h"
+#endif
+
/* Retrieve the generic table initialization parameters for the tbl_idx */
static struct bnxt_ulp_generic_tbl_params*
ulp_mapper_gen_tbl_params_get(uint32_t tbl_idx)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
index 5f5b5d639e..bc5627ec5b 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
@@ -185,7 +185,7 @@ ulp_ha_mgr_timer_cb(void *arg __rte_unused)
rc = ulp_ha_mgr_state_get(ulp_ctx, &curr_state);
if (rc) {
/*
- * This shouldn't happen, if it does, reset the timer
+ * This shouldn't happen, if it does, resetart the timer
* and try again next time.
*/
BNXT_TF_DBG(ERR, "Failed(%d) to get state.\n",
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index f3a60cc880..7fc3767b33 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -22,6 +22,11 @@
#include "ulp_ha_mgr.h"
#include "bnxt_tf_pmd_shim.h"
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#include "ulp_template_debug_proto.h"
+#include "ulp_tf_debug.h"
+#endif
+
static uint8_t mapper_fld_zeros[16] = { 0 };
static uint8_t mapper_fld_ones[16] = {
@@ -156,6 +161,13 @@ ulp_mapper_resource_ident_allocate(struct bnxt_ulp_context *ulp_ctx,
tf_free_identifier(tfp, &fparms);
return rc;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ BNXT_TF_DBG(DEBUG, "Allocated Glb Res Ident [%s][%d][%d] = 0x%04x\n",
+ tf_dir_2_str(iparms.dir),
+ glb_res->glb_regfile_index, iparms.ident_type, iparms.id);
+#endif
+#endif
return rc;
}
@@ -216,6 +228,13 @@ ulp_mapper_resource_index_tbl_alloc(struct bnxt_ulp_context *ulp_ctx,
tf_free_tbl_entry(tfp, &free_parms);
return rc;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ BNXT_TF_DBG(DEBUG, "Allocated Glb Res Index [%s][%d][%d] = 0x%04x\n",
+ tf_dir_2_str(aparms.dir),
+ glb_res->glb_regfile_index, aparms.type, aparms.idx);
+#endif
+#endif
return rc;
}
@@ -784,6 +803,9 @@ ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms,
tf_ident_2_str(iparms.ident_type));
return rc;
}
+ BNXT_TF_INF("Alloc ident %s:%s.success.\n",
+ tf_dir_2_str(iparms.dir),
+ tf_ident_2_str(iparms.ident_type));
id = (uint64_t)tfp_cpu_to_be_64(iparms.id);
if (ulp_regfile_write(parms->regfile, idx, id)) {
@@ -813,6 +835,11 @@ ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms,
} else {
*val = iparms.id;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_ident_field_dump("Ident", ident, tbl, iparms.id);
+#endif
+#endif
return 0;
error:
@@ -877,6 +904,10 @@ ulp_mapper_ident_extract(struct bnxt_ulp_mapper_parms *parms,
sparms.search_id);
return rc;
}
+ BNXT_TF_INF("Search ident %s:%s:%x.success.\n",
+ tf_dir_2_str(sparms.dir),
+ tf_tbl_type_2_str(sparms.ident_type),
+ sparms.search_id);
/* Write it to the regfile */
id = (uint64_t)tfp_cpu_to_be_64(sparms.search_id);
@@ -904,6 +935,11 @@ ulp_mapper_ident_extract(struct bnxt_ulp_mapper_parms *parms,
goto error;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_ident_field_dump("Ident", ident, tbl, sparms.search_id);
+#endif
+#endif
return 0;
error:
@@ -996,7 +1032,7 @@ ulp_mapper_field_src_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
idx = tfp_be_to_cpu_16(idx);
- if (idx >= BNXT_ULP_CF_IDX_LAST || bytelen > sizeof(uint64_t)) {
+ if (idx >= BNXT_ULP_CF_IDX_LAST || bytelen > sizeof(uint32_t)) {
BNXT_TF_DBG(ERR, "comp field [%d] read oob %d\n", idx,
bytelen);
return -EINVAL;
@@ -1448,7 +1484,16 @@ ulp_mapper_field_opc_process(struct bnxt_ulp_mapper_parms *parms,
break;
}
- return rc;
+ if (!rc) {
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ if (fld->field_src1 != BNXT_ULP_FIELD_SRC_ZERO)
+ ulp_mapper_field_dump(name, fld, blob, write_idx, val,
+ val_len);
+#endif
+#endif
+ return rc;
+ }
error:
BNXT_TF_DBG(ERR, "Error in %s:%s process %u:%u\n", name,
fld->description, (val) ? write_idx : 0, val_len);
@@ -1500,8 +1545,15 @@ ulp_mapper_tbl_result_build(struct bnxt_ulp_mapper_parms *parms,
}
/* if encap bit swap is enabled perform the bit swap */
- if (parms->device_params->encap_byte_swap && encap_flds)
+ if (parms->device_params->encap_byte_swap && encap_flds) {
ulp_blob_perform_encap_swap(data);
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ BNXT_TF_DBG(INFO, "Dump after encap swap\n");
+ ulp_mapper_blob_dump(data);
+#endif
+#endif
+ }
return rc;
}
@@ -1725,6 +1777,9 @@ ulp_mapper_tcam_tbl_entry_write(struct bnxt_ulp_mapper_parms *parms,
tf_dir_2_str(sparms.dir), sparms.idx);
return -EIO;
}
+ BNXT_TF_INF("tcam[%s][%s][%x] write success.\n",
+ tf_tcam_tbl_2_str(sparms.tcam_tbl_type),
+ tf_dir_2_str(sparms.dir), sparms.idx);
/* Mark action */
rc = ulp_mapper_mark_act_ptr_process(parms, tbl);
@@ -1733,6 +1788,11 @@ ulp_mapper_tcam_tbl_entry_write(struct bnxt_ulp_mapper_parms *parms,
return rc;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_tcam_entry_dump("TCAM", idx, tbl, key, mask, data);
+#endif
+#endif
return rc;
}
@@ -1838,6 +1898,12 @@ static void ulp_mapper_wc_tcam_tbl_post_process(struct ulp_blob *blob)
{
ulp_blob_perform_64B_word_swap(blob);
ulp_blob_perform_64B_byte_swap(blob);
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ BNXT_TF_DBG(INFO, "Dump after wc tcam post process\n");
+ ulp_mapper_blob_dump(blob);
+#endif
+#endif
}
static int32_t
@@ -2134,6 +2200,11 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
BNXT_TF_DBG(ERR, "Failed to build the result blob\n");
return rc;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_result_dump("EM Result", tbl, &data);
+#endif
+#endif
if (dparms->dynamic_pad_en) {
uint32_t abits = dparms->em_blk_align_bits;
@@ -2148,6 +2219,11 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
ulp_blob_pad_align(&data, abits);
ulp_blob_perform_byte_reverse(&data, ULP_BITS_2_BYTE(abits));
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_result_dump("EM Merged Result", tbl, &data);
+#endif
+#endif
}
/* do the transpose for the internal EM keys */
@@ -2160,6 +2236,11 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
}
tmplen = ulp_blob_data_len_get(&key);
ulp_blob_perform_byte_reverse(&key, ULP_BITS_2_BYTE(tmplen));
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_result_dump("EM Key Transpose", tbl, &key);
+#endif
+#endif
}
rc = bnxt_ulp_cntxt_tbl_scope_id_get(parms->ulp_ctx,
@@ -2190,6 +2271,12 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return rc;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_em_dump("EM", &key, &data, &iparms);
+ /* tf_dump_tables(tfp, iparms.tbl_scope_id); */
+#endif
+#endif
/* Mark action process */
if (mtype == BNXT_ULP_FLOW_MEM_TYPE_EXT &&
tbl->resource_type == TF_MEM_EXTERNAL)
@@ -2479,6 +2566,9 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
sparms.idx, rc);
goto error;
}
+ BNXT_TF_INF("Index table[%s][%s][%x] write successful.\n",
+ tf_tbl_type_2_str(sparms.type),
+ tf_dir_2_str(sparms.dir), sparms.idx);
/* Calculate action record size */
if (tbl->resource_type == TF_TBL_TYPE_EXT) {
@@ -2635,6 +2725,10 @@ ulp_mapper_if_tbl_process(struct bnxt_ulp_mapper_parms *parms,
iftbl_params.idx, rc);
return rc;
}
+ BNXT_TF_INF("Set table[%s][%s][%x] success.\n",
+ tf_if_tbl_2_str(iftbl_params.type),
+ tf_dir_2_str(iftbl_params.dir),
+ iftbl_params.idx);
/*
* TBD: Need to look at the need to store idx in flow db for restore
@@ -2697,6 +2791,12 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms,
/* The_key is a byte array convert it to a search index */
cache_key = ulp_blob_data_get(&key, &tmplen);
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ BNXT_TF_DBG(DEBUG, "The gen_tbl[%u] key\n", tbl_idx);
+ ulp_mapper_blob_dump(&key);
+#endif
+#endif
/* get the generic table */
gen_tbl_list = &parms->mapper_data->gen_tbl_list[tbl_idx];
@@ -3495,6 +3595,11 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid)
for (tbl_idx = 0; tbl_idx < num_tbls && cond_goto;) {
tbl = &tbls[tbl_idx];
cond_goto = tbl->execute_info.cond_true_goto;
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
+ ulp_mapper_table_dump(tbl, tbl_idx);
+#endif
+#endif
/* Process the conditional func code opcodes */
if (ulp_mapper_func_info_process(parms, tbl)) {
BNXT_TF_DBG(ERR, "Failed to process cond update\n");
diff --git a/drivers/net/bnxt/tf_ulp/ulp_matcher.c b/drivers/net/bnxt/tf_ulp/ulp_matcher.c
index 67fa61fc7c..e06d8f6287 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_matcher.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_matcher.c
@@ -6,6 +6,10 @@
#include "ulp_matcher.h"
#include "ulp_utils.h"
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#include "ulp_template_debug_proto.h"
+#endif
+
/* Utility function to calculate the class matcher hash */
static uint32_t
ulp_matcher_class_hash_calculate(uint64_t hi_sig, uint64_t lo_sig)
@@ -95,6 +99,11 @@ ulp_matcher_pattern_match(struct ulp_rte_parser_params *params,
error:
BNXT_TF_DBG(DEBUG, "Did not find any matching template\n");
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+ BNXT_TF_DBG(DEBUG, "class_hid:0x%x, Hdr:%" PRIX64 " Fld:%" PRIX64 "\n",
+ class_hid, params->hdr_bitmap.bits,
+ params->fld_bitmap.bits);
+#endif
*class_id = 0;
return BNXT_TF_RC_ERROR;
}
@@ -142,6 +151,10 @@ ulp_matcher_action_match(struct ulp_rte_parser_params *params,
error:
BNXT_TF_DBG(DEBUG, "Did not find any matching action template\n");
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+ BNXT_TF_DBG(DEBUG, "act_hid:0x%x, Hdr:%" PRIX64 "\n",
+ act_hid, params->act_bitmap.bits);
+#endif
*act_id = 0;
return BNXT_TF_RC_ERROR;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.c b/drivers/net/bnxt/tf_ulp/ulp_port_db.c
index 4045473097..7d9865b3e3 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_port_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.c
@@ -7,9 +7,13 @@
#include "bnxt.h"
#include "bnxt_vnic.h"
#include "bnxt_tf_common.h"
+#include "bnxt_tf_pmd_shim.h"
#include "ulp_port_db.h"
#include "tfp.h"
-#include "bnxt_tf_pmd_shim.h"
+
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#include "ulp_tf_debug.h"
+#endif
static uint32_t
ulp_port_db_allocate_ifindex(struct bnxt_ulp_port_db *port_db)
@@ -151,12 +155,12 @@ int32_t ulp_port_db_dev_port_intf_update(struct bnxt_ulp_context *ulp_ctxt,
intf->type = bnxt_pmd_get_interface_type(port_id);
intf->drv_func_id = bnxt_pmd_get_fw_func_id(port_id,
- BNXT_ULP_INTF_TYPE_INVALID);
+ BNXT_ULP_INTF_TYPE_INVALID);
func = &port_db->ulp_func_id_tbl[intf->drv_func_id];
if (!func->func_valid) {
func->func_svif = bnxt_pmd_get_svif(port_id, true,
- BNXT_ULP_INTF_TYPE_INVALID);
+ BNXT_ULP_INTF_TYPE_INVALID);
func->func_spif = bnxt_pmd_get_phy_port_id(port_id);
func->func_parif =
bnxt_pmd_get_parif(port_id, BNXT_ULP_INTF_TYPE_INVALID);
@@ -202,6 +206,11 @@ int32_t ulp_port_db_dev_port_intf_update(struct bnxt_ulp_context *ulp_ctxt,
port_data->port_vport = bnxt_pmd_get_vport(port_id);
port_data->port_valid = true;
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PORT
+ ulp_port_db_dump(port_db, intf, port_id);
+#endif
+#endif
return 0;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index 5fd52b8f36..79b9957781 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -8,6 +8,7 @@
#include "ulp_template_struct.h"
#include "bnxt_ulp.h"
#include "bnxt_tf_common.h"
+#include "bnxt_tf_pmd_shim.h"
#include "ulp_rte_parser.h"
#include "ulp_matcher.h"
#include "ulp_utils.h"
@@ -855,7 +856,7 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
BNXT_ULP_HDR_BIT_II_VLAN);
inner_flag = 1;
} else {
- BNXT_TF_DBG(ERR, "Error Parsing:Vlan hdr found without eth\n");
+ BNXT_TF_DBG(ERR, "Error Parsing:Vlan hdr found withtout eth\n");
return BNXT_TF_RC_ERROR;
}
/* Update the field protocol hdr bitmap */
@@ -1135,8 +1136,8 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
ulp_rte_prsr_fld_mask(params, &idx, size, &ver_spec, &ver_mask,
ULP_PRSR_ACT_DEFAULT);
/*
- * The TC and flow label field are ignored since OVS is setting
- * it for match and it is not supported.
+ * The TC and flow label field are ignored since OVS is
+ * setting it for match and it is not supported.
* This is a work around and
* shall be addressed in the future.
*/
@@ -2138,7 +2139,7 @@ ulp_rte_vf_act_handler(const struct rte_flow_action *action_item,
return BNXT_TF_RC_PARSE_ERR;
}
- bp = bnxt_get_bp(params->port_id);
+ bp = bnxt_pmd_get_bp(params->port_id);
if (bp == NULL) {
BNXT_TF_DBG(ERR, "Invalid bp\n");
return BNXT_TF_RC_ERROR;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.c b/drivers/net/bnxt/tf_ulp/ulp_tun.c
index cb8530d791..a1dd5b902c 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_tun.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_tun.c
@@ -3,6 +3,8 @@
* All rights reserved.
*/
+#include <sys/queue.h>
+
#include <rte_malloc.h>
#include "ulp_tun.h"
@@ -29,6 +31,15 @@ ulp_install_outer_tun_flow(struct ulp_rte_parser_params *params,
ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F1);
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER
+ /* Dump the rte flow pattern */
+ ulp_parser_hdr_info_dump(params);
+ /* Dump the rte flow action */
+ ulp_parser_act_info_dump(params);
+#endif
+#endif
+
ret = ulp_matcher_pattern_match(params, ¶ms->class_id);
if (ret != BNXT_TF_RC_SUCCESS)
goto err;
@@ -146,6 +157,15 @@ ulp_post_process_cache_inner_tun_flow(struct ulp_rte_parser_params *params,
struct ulp_per_port_flow_info *flow_info;
int ret;
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER
+ /* Dump the rte flow pattern */
+ ulp_parser_hdr_info_dump(params);
+ /* Dump the rte flow action */
+ ulp_parser_act_info_dump(params);
+#endif
+#endif
+
ret = ulp_matcher_pattern_match(params, ¶ms->class_id);
if (ret != BNXT_TF_RC_SUCCESS)
return BNXT_TF_RC_ERROR;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c
index bafb539c8d..1649e157f2 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c
@@ -62,7 +62,7 @@ ulp_regfile_read(struct ulp_regfile *regfile,
* data [in] The value is written into this variable. It is going to be in the
* same byte order as it was written.
*
- * size [in] The size in bytes of the value being written into this
+ * size [in] The size in bytes of the value beingritten into this
* variable.
*
* returns 0 on success
@@ -295,7 +295,7 @@ ulp_blob_push(struct ulp_blob *blob,
datalen,
data);
if (!rc) {
- BNXT_TF_DBG(ERR, "Failed to write blob\n");
+ BNXT_TF_DBG(ERR, "Failed ro write blob\n");
return 0;
}
blob->write_idx += datalen;
@@ -355,7 +355,7 @@ ulp_blob_insert(struct ulp_blob *blob, uint32_t offset,
datalen,
data);
if (!rc) {
- BNXT_TF_DBG(ERR, "Failed to write blob\n");
+ BNXT_TF_DBG(ERR, "Failed ro write blob\n");
return 0;
}
/* copy the previously stored data */
@@ -409,7 +409,7 @@ ulp_blob_push_64(struct ulp_blob *blob,
*
* data [in] 32-bit value to be added to the blob.
*
- * datalen [in] The number of bits to be added to the blob.
+ * datalen [in] The number of bits to be added ot the blob.
*
* The offset of the data is updated after each push of data.
* NULL returned on error, pointer pushed value otherwise.
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v4 06/13] net/bnxt: add support for tunnel offload API
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 " Venkat Duvvuru
` (4 preceding siblings ...)
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 05/13] net/bnxt: add flow template support for Thor Venkat Duvvuru
@ 2021-09-20 7:42 ` Venkat Duvvuru
2021-09-28 12:43 ` Ferruh Yigit
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 07/13] net/bnxt: add support for dynamic encap action Venkat Duvvuru
` (7 subsequent siblings)
13 siblings, 1 reply; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-20 7:42 UTC (permalink / raw)
To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Add support for tunnel offload APIs. Specifically the following
are supported.
tunnel_decap_set, tunnel_match, tunnel_action_decap_release,
tunnel_item_release.
This provides support for VXLAN decap action where two flows
can indicate tunnel offload rule. The first flow indicates the
tunnel properties and second flow indicates the inner packet
structure. The templates are updated to support this
feature.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/tf_ulp/bnxt_tf_common.h | 4 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 12 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 20 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 212 +-
.../generic_templates/ulp_template_db_act.c | 2 +-
.../generic_templates/ulp_template_db_class.c | 8541 +++++++++++-----
.../generic_templates/ulp_template_db_enum.h | 210 +-
.../generic_templates/ulp_template_db_field.h | 654 +-
.../generic_templates/ulp_template_db_tbl.c | 645 +-
.../ulp_template_db_thor_class.c | 110 +-
.../ulp_template_db_wh_plus_act.c | 2 +-
.../ulp_template_db_wh_plus_class.c | 8577 +++++++++++------
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 46 +-
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h | 8 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 562 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 44 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 52 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.h | 6 +-
drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c | 31 +
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 134 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 10 +-
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 10 +-
drivers/net/bnxt/tf_ulp/ulp_tun.c | 541 +-
drivers/net/bnxt/tf_ulp/ulp_tun.h | 89 +-
24 files changed, 13810 insertions(+), 6712 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
index e0ebed3fed..6c4bcd2d90 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
@@ -37,9 +37,7 @@
enum bnxt_tf_rc {
BNXT_TF_RC_PARSE_ERR = -2,
BNXT_TF_RC_ERROR = -1,
- BNXT_TF_RC_SUCCESS = 0,
- BNXT_TF_RC_NORMAL = 1,
- BNXT_TF_RC_FID = 2,
+ BNXT_TF_RC_SUCCESS = 0
};
/* eth IPv4 Type */
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 475c7a6cdf..dfafd9ff5b 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -860,8 +860,6 @@ ulp_ctx_init(struct bnxt *bp,
if (rc)
goto error_deinit;
- ulp_tun_tbl_init(ulp_data->tun_tbl);
-
bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, &bp->tfp);
return rc;
@@ -2064,3 +2062,13 @@ bnxt_ulp_cntxt_entry_release(void)
{
rte_spinlock_unlock(&bnxt_ulp_ctxt_lock);
}
+
+/* Function to get the app tunnel details from the ulp context. */
+struct bnxt_flow_app_tun_ent *
+bnxt_ulp_cntxt_ptr2_app_tun_list_get(struct bnxt_ulp_context *ulp)
+{
+ if (!ulp || !ulp->cfg_data)
+ return NULL;
+
+ return ulp->cfg_data->app_tun;
+}
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
index 082ca501b6..006df9cbc5 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
@@ -47,6 +47,18 @@ enum bnxt_ulp_flow_mem_type {
BNXT_ULP_FLOW_MEM_TYPE_LAST = 3
};
+enum bnxt_rte_flow_item_type {
+ BNXT_RTE_FLOW_ITEM_TYPE_END = (uint32_t)INT_MIN,
+ BNXT_RTE_FLOW_ITEM_TYPE_VXLAN_DECAP,
+ BNXT_RTE_FLOW_ITEM_TYPE_LAST
+};
+
+enum bnxt_rte_flow_action_type {
+ BNXT_RTE_FLOW_ACTION_TYPE_END = (uint32_t)INT_MIN,
+ BNXT_RTE_FLOW_ACTION_TYPE_VXLAN_DECAP,
+ BNXT_RTE_FLOW_ACTION_TYPE_LAST
+};
+
struct bnxt_ulp_df_rule_info {
uint32_t def_port_flow_id;
uint8_t valid;
@@ -79,6 +91,7 @@ struct bnxt_ulp_data {
bool accum_stats;
uint8_t app_id;
uint8_t num_shared_clients;
+ struct bnxt_flow_app_tun_ent app_tun[BNXT_ULP_MAX_TUN_CACHE_ENTRIES];
};
struct bnxt_ulp_context {
@@ -258,9 +271,6 @@ bnxt_ulp_cntxt_acquire_fdb_lock(struct bnxt_ulp_context *ulp_ctx);
void
bnxt_ulp_cntxt_release_fdb_lock(struct bnxt_ulp_context *ulp_ctx);
-int32_t
-ulp_post_process_tun_flow(struct ulp_rte_parser_params *params);
-
struct bnxt_ulp_glb_resource_info *
bnxt_ulp_app_glb_resource_info_list_get(uint32_t *num_entries);
@@ -301,4 +311,8 @@ bnxt_ulp_cntxt_entry_release(void);
uint8_t
bnxt_ulp_cntxt_num_shared_clients_get(struct bnxt_ulp_context *ulp_ctx);
+
+struct bnxt_flow_app_tun_ent *
+bnxt_ulp_cntxt_ptr2_app_tun_list_get(struct bnxt_ulp_context *ulp);
+
#endif /* _BNXT_ULP_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
index 238b1d9657..3daf5942e8 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
@@ -12,6 +12,7 @@
#include "ulp_fc_mgr.h"
#include "ulp_port_db.h"
#include "ulp_ha_mgr.h"
+#include "ulp_tun.h"
#include <rte_malloc.h>
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
#include "ulp_template_debug_proto.h"
@@ -101,12 +102,13 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms,
mapper_cparms->act_prop = ¶ms->act_prop;
mapper_cparms->flow_id = params->fid;
mapper_cparms->parent_flow = params->parent_flow;
- mapper_cparms->parent_fid = params->parent_fid;
+ mapper_cparms->child_flow = params->child_flow;
mapper_cparms->fld_bitmap = ¶ms->fld_bitmap;
mapper_cparms->flow_pattern_id = params->flow_pattern_id;
mapper_cparms->act_pattern_id = params->act_pattern_id;
mapper_cparms->app_id = params->app_id;
mapper_cparms->port_id = params->port_id;
+ mapper_cparms->tun_idx = params->tun_idx;
/* update the signature fields into the computed field list */
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_HDR_SIG_ID,
@@ -218,12 +220,14 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
params.func_id = func_id;
params.priority = attr->priority;
params.port_id = dev->data->port_id;
+
/* Perform the rte flow post process */
- ret = bnxt_ulp_rte_parser_post_process(¶ms);
+ bnxt_ulp_rte_parser_post_process(¶ms);
+
+ /* do the tunnel offload process if any */
+ ret = ulp_tunnel_offload_process(¶ms);
if (ret == BNXT_TF_RC_ERROR)
goto free_fid;
- else if (ret == BNXT_TF_RC_FID)
- goto return_fid;
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER
@@ -249,7 +253,6 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
if (ret)
goto free_fid;
-return_fid:
bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
flow_id = (struct rte_flow *)((uintptr_t)fid);
@@ -314,11 +317,12 @@ bnxt_ulp_flow_validate(struct rte_eth_dev *dev,
goto parse_error;
/* Perform the rte flow post process */
- ret = bnxt_ulp_rte_parser_post_process(¶ms);
+ bnxt_ulp_rte_parser_post_process(¶ms);
+
+ /* do the tunnel offload process if any */
+ ret = ulp_tunnel_offload_process(¶ms);
if (ret == BNXT_TF_RC_ERROR)
goto parse_error;
- else if (ret == BNXT_TF_RC_FID)
- return 0;
ret = ulp_matcher_pattern_match(¶ms, &class_id);
@@ -475,11 +479,201 @@ bnxt_ulp_flow_query(struct rte_eth_dev *eth_dev,
return rc;
}
+/* Tunnel offload Apis */
+#define BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS 1
+
+static int
+bnxt_ulp_tunnel_decap_set(struct rte_eth_dev *eth_dev,
+ struct rte_flow_tunnel *tunnel,
+ struct rte_flow_action **pmd_actions,
+ uint32_t *num_of_actions,
+ struct rte_flow_error *error)
+{
+ struct bnxt_ulp_context *ulp_ctx;
+ struct bnxt_flow_app_tun_ent *tun_entry;
+ int32_t rc = 0;
+
+ ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev);
+ if (ulp_ctx == NULL) {
+ BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
+ "ULP context uninitialized");
+ return -EINVAL;
+ }
+
+ if (tunnel == NULL) {
+ BNXT_TF_DBG(ERR, "No tunnel specified\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "no tunnel specified");
+ return -EINVAL;
+ }
+
+ if (tunnel->type != RTE_FLOW_ITEM_TYPE_VXLAN) {
+ BNXT_TF_DBG(ERR, "Tunnel type unsupported\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "tunnel type unsupported");
+ return -EINVAL;
+ }
+
+ rc = ulp_app_tun_search_entry(ulp_ctx, tunnel, &tun_entry);
+ if (rc < 0) {
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "tunnel decap set failed");
+ return -EINVAL;
+ }
+
+ rc = ulp_app_tun_entry_set_decap_action(tun_entry);
+ if (rc < 0) {
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "tunnel decap set failed");
+ return -EINVAL;
+ }
+
+ *pmd_actions = &tun_entry->action;
+ *num_of_actions = BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS;
+ return 0;
+}
+
+static int
+bnxt_ulp_tunnel_match(struct rte_eth_dev *eth_dev,
+ struct rte_flow_tunnel *tunnel,
+ struct rte_flow_item **pmd_items,
+ uint32_t *num_of_items,
+ struct rte_flow_error *error)
+{
+ struct bnxt_ulp_context *ulp_ctx;
+ struct bnxt_flow_app_tun_ent *tun_entry;
+ int32_t rc = 0;
+
+ ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev);
+ if (ulp_ctx == NULL) {
+ BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
+ "ULP context uninitialized");
+ return -EINVAL;
+ }
+
+ if (tunnel == NULL) {
+ BNXT_TF_DBG(ERR, "No tunnel specified\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
+ "no tunnel specified");
+ return -EINVAL;
+ }
+
+ if (tunnel->type != RTE_FLOW_ITEM_TYPE_VXLAN) {
+ BNXT_TF_DBG(ERR, "Tunnel type unsupported\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
+ "tunnel type unsupported");
+ return -EINVAL;
+ }
+
+ rc = ulp_app_tun_search_entry(ulp_ctx, tunnel, &tun_entry);
+ if (rc < 0) {
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "tunnel match set failed");
+ return -EINVAL;
+ }
+
+ rc = ulp_app_tun_entry_set_decap_item(tun_entry);
+ if (rc < 0) {
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "tunnel match set failed");
+ return -EINVAL;
+ }
+
+ *pmd_items = &tun_entry->item;
+ *num_of_items = BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS;
+ return 0;
+}
+
+static int
+bnxt_ulp_tunnel_decap_release(struct rte_eth_dev *eth_dev,
+ struct rte_flow_action *pmd_actions,
+ uint32_t num_actions,
+ struct rte_flow_error *error)
+{
+ struct bnxt_ulp_context *ulp_ctx;
+ struct bnxt_flow_app_tun_ent *tun_entry;
+ const struct rte_flow_action *action_item = pmd_actions;
+
+ ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev);
+ if (ulp_ctx == NULL) {
+ BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
+ "ULP context uninitialized");
+ return -EINVAL;
+ }
+ if (num_actions != BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS) {
+ BNXT_TF_DBG(ERR, "num actions is invalid\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "num actions is invalid");
+ return -EINVAL;
+ }
+ while (action_item && action_item->type != RTE_FLOW_ACTION_TYPE_END) {
+ if (action_item->type == (typeof(tun_entry->action.type))
+ BNXT_RTE_FLOW_ACTION_TYPE_VXLAN_DECAP) {
+ tun_entry = ulp_app_tun_match_entry(ulp_ctx,
+ action_item->conf);
+ ulp_app_tun_entry_delete(tun_entry);
+ }
+ action_item++;
+ }
+ return 0;
+}
+
+static int
+bnxt_ulp_tunnel_item_release(struct rte_eth_dev *eth_dev,
+ struct rte_flow_item *pmd_items,
+ uint32_t num_items,
+ struct rte_flow_error *error)
+{
+ struct bnxt_ulp_context *ulp_ctx;
+ struct bnxt_flow_app_tun_ent *tun_entry;
+
+ ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev);
+ if (ulp_ctx == NULL) {
+ BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
+ "ULP context uninitialized");
+ return -EINVAL;
+ }
+ if (num_items != BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS) {
+ BNXT_TF_DBG(ERR, "num items is invalid\n");
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR, NULL,
+ "num items is invalid");
+ return -EINVAL;
+ }
+
+ tun_entry = ulp_app_tun_match_entry(ulp_ctx, pmd_items->spec);
+ ulp_app_tun_entry_delete(tun_entry);
+ return 0;
+}
+
const struct rte_flow_ops bnxt_ulp_rte_flow_ops = {
.validate = bnxt_ulp_flow_validate,
.create = bnxt_ulp_flow_create,
.destroy = bnxt_ulp_flow_destroy,
.flush = bnxt_ulp_flow_flush,
.query = bnxt_ulp_flow_query,
- .isolate = NULL
+ .isolate = NULL,
+ /* Tunnel offload callbacks */
+ .tunnel_decap_set = bnxt_ulp_tunnel_decap_set,
+ .tunnel_match = bnxt_ulp_tunnel_match,
+ .tunnel_action_decap_release = bnxt_ulp_tunnel_decap_release,
+ .tunnel_item_release = bnxt_ulp_tunnel_item_release,
+ .get_restore_info = NULL
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c
index e18f314856..0da6070d7d 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Wed Mar 17 11:31:19 2021 */
+/* date: Mon May 17 15:30:41 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
index 9c419f6a15..f74687acfa 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Wed Mar 17 11:31:19 2021 */
+/* date: Thu May 20 11:56:39 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -360,348 +360,510 @@ uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {
[BNXT_ULP_CLASS_HID_15db] = 342,
[BNXT_ULP_CLASS_HID_1151] = 343,
[BNXT_ULP_CLASS_HID_315d] = 344,
- [BNXT_ULP_CLASS_HID_34c6] = 345,
- [BNXT_ULP_CLASS_HID_0c22] = 346,
- [BNXT_ULP_CLASS_HID_1cbe] = 347,
- [BNXT_ULP_CLASS_HID_179a] = 348,
- [BNXT_ULP_CLASS_HID_59be] = 349,
- [BNXT_ULP_CLASS_HID_515a] = 350,
- [BNXT_ULP_CLASS_HID_1c72] = 351,
- [BNXT_ULP_CLASS_HID_171e] = 352,
- [BNXT_ULP_CLASS_HID_19c8] = 353,
- [BNXT_ULP_CLASS_HID_112c] = 354,
- [BNXT_ULP_CLASS_HID_4d68] = 355,
- [BNXT_ULP_CLASS_HID_444c] = 356,
- [BNXT_ULP_CLASS_HID_0e8c] = 357,
- [BNXT_ULP_CLASS_HID_09e0] = 358,
- [BNXT_ULP_CLASS_HID_1af0] = 359,
- [BNXT_ULP_CLASS_HID_15d4] = 360,
- [BNXT_ULP_CLASS_HID_1dd0] = 361,
- [BNXT_ULP_CLASS_HID_14f4] = 362,
- [BNXT_ULP_CLASS_HID_70b0] = 363,
- [BNXT_ULP_CLASS_HID_4854] = 364,
- [BNXT_ULP_CLASS_HID_3dd4] = 365,
- [BNXT_ULP_CLASS_HID_34f8] = 366,
- [BNXT_ULP_CLASS_HID_09e8] = 367,
- [BNXT_ULP_CLASS_HID_008c] = 368,
- [BNXT_ULP_CLASS_HID_34e6] = 369,
- [BNXT_ULP_CLASS_HID_0c02] = 370,
- [BNXT_ULP_CLASS_HID_1c9e] = 371,
- [BNXT_ULP_CLASS_HID_17ba] = 372,
- [BNXT_ULP_CLASS_HID_429e] = 373,
- [BNXT_ULP_CLASS_HID_5dba] = 374,
- [BNXT_ULP_CLASS_HID_2a16] = 375,
- [BNXT_ULP_CLASS_HID_2532] = 376,
- [BNXT_ULP_CLASS_HID_2da2] = 377,
- [BNXT_ULP_CLASS_HID_24fe] = 378,
- [BNXT_ULP_CLASS_HID_355a] = 379,
- [BNXT_ULP_CLASS_HID_0c76] = 380,
- [BNXT_ULP_CLASS_HID_13e6] = 381,
- [BNXT_ULP_CLASS_HID_7276] = 382,
- [BNXT_ULP_CLASS_HID_42d2] = 383,
- [BNXT_ULP_CLASS_HID_5dee] = 384,
- [BNXT_ULP_CLASS_HID_59de] = 385,
- [BNXT_ULP_CLASS_HID_513a] = 386,
- [BNXT_ULP_CLASS_HID_1c12] = 387,
- [BNXT_ULP_CLASS_HID_177e] = 388,
- [BNXT_ULP_CLASS_HID_0e92] = 389,
- [BNXT_ULP_CLASS_HID_09fe] = 390,
- [BNXT_ULP_CLASS_HID_5c1a] = 391,
- [BNXT_ULP_CLASS_HID_5746] = 392,
- [BNXT_ULP_CLASS_HID_79da] = 393,
- [BNXT_ULP_CLASS_HID_7106] = 394,
- [BNXT_ULP_CLASS_HID_3c1e] = 395,
- [BNXT_ULP_CLASS_HID_377a] = 396,
- [BNXT_ULP_CLASS_HID_2e9e] = 397,
- [BNXT_ULP_CLASS_HID_29fa] = 398,
- [BNXT_ULP_CLASS_HID_14d2] = 399,
- [BNXT_ULP_CLASS_HID_7742] = 400,
- [BNXT_ULP_CLASS_HID_3706] = 401,
- [BNXT_ULP_CLASS_HID_0fe2] = 402,
- [BNXT_ULP_CLASS_HID_1f7e] = 403,
- [BNXT_ULP_CLASS_HID_145a] = 404,
- [BNXT_ULP_CLASS_HID_417e] = 405,
- [BNXT_ULP_CLASS_HID_5e5a] = 406,
- [BNXT_ULP_CLASS_HID_29f6] = 407,
- [BNXT_ULP_CLASS_HID_26d2] = 408,
- [BNXT_ULP_CLASS_HID_2e42] = 409,
- [BNXT_ULP_CLASS_HID_271e] = 410,
- [BNXT_ULP_CLASS_HID_36ba] = 411,
- [BNXT_ULP_CLASS_HID_0f96] = 412,
- [BNXT_ULP_CLASS_HID_1006] = 413,
- [BNXT_ULP_CLASS_HID_7196] = 414,
- [BNXT_ULP_CLASS_HID_4132] = 415,
- [BNXT_ULP_CLASS_HID_5e0e] = 416,
- [BNXT_ULP_CLASS_HID_59fe] = 417,
- [BNXT_ULP_CLASS_HID_511a] = 418,
- [BNXT_ULP_CLASS_HID_1c32] = 419,
- [BNXT_ULP_CLASS_HID_175e] = 420,
- [BNXT_ULP_CLASS_HID_0eb2] = 421,
- [BNXT_ULP_CLASS_HID_09de] = 422,
- [BNXT_ULP_CLASS_HID_5c3a] = 423,
- [BNXT_ULP_CLASS_HID_5766] = 424,
- [BNXT_ULP_CLASS_HID_79fa] = 425,
- [BNXT_ULP_CLASS_HID_7126] = 426,
- [BNXT_ULP_CLASS_HID_3c3e] = 427,
- [BNXT_ULP_CLASS_HID_375a] = 428,
- [BNXT_ULP_CLASS_HID_2ebe] = 429,
- [BNXT_ULP_CLASS_HID_29da] = 430,
- [BNXT_ULP_CLASS_HID_14f2] = 431,
- [BNXT_ULP_CLASS_HID_7762] = 432,
- [BNXT_ULP_CLASS_HID_19e8] = 433,
- [BNXT_ULP_CLASS_HID_110c] = 434,
- [BNXT_ULP_CLASS_HID_4d48] = 435,
- [BNXT_ULP_CLASS_HID_446c] = 436,
- [BNXT_ULP_CLASS_HID_0eac] = 437,
- [BNXT_ULP_CLASS_HID_09c0] = 438,
- [BNXT_ULP_CLASS_HID_1ad0] = 439,
- [BNXT_ULP_CLASS_HID_15f4] = 440,
- [BNXT_ULP_CLASS_HID_39ec] = 441,
- [BNXT_ULP_CLASS_HID_3100] = 442,
- [BNXT_ULP_CLASS_HID_0210] = 443,
- [BNXT_ULP_CLASS_HID_1d34] = 444,
- [BNXT_ULP_CLASS_HID_2ea0] = 445,
- [BNXT_ULP_CLASS_HID_29c4] = 446,
- [BNXT_ULP_CLASS_HID_3ad4] = 447,
- [BNXT_ULP_CLASS_HID_35e8] = 448,
- [BNXT_ULP_CLASS_HID_5d80] = 449,
- [BNXT_ULP_CLASS_HID_54a4] = 450,
- [BNXT_ULP_CLASS_HID_29b4] = 451,
- [BNXT_ULP_CLASS_HID_20c8] = 452,
- [BNXT_ULP_CLASS_HID_7244] = 453,
- [BNXT_ULP_CLASS_HID_4d98] = 454,
- [BNXT_ULP_CLASS_HID_5e68] = 455,
- [BNXT_ULP_CLASS_HID_598c] = 456,
- [BNXT_ULP_CLASS_HID_1248] = 457,
- [BNXT_ULP_CLASS_HID_74d8] = 458,
- [BNXT_ULP_CLASS_HID_49a8] = 459,
- [BNXT_ULP_CLASS_HID_40cc] = 460,
- [BNXT_ULP_CLASS_HID_0b0c] = 461,
- [BNXT_ULP_CLASS_HID_0220] = 462,
- [BNXT_ULP_CLASS_HID_1730] = 463,
- [BNXT_ULP_CLASS_HID_7980] = 464,
- [BNXT_ULP_CLASS_HID_1db0] = 465,
- [BNXT_ULP_CLASS_HID_1494] = 466,
- [BNXT_ULP_CLASS_HID_70d0] = 467,
- [BNXT_ULP_CLASS_HID_4834] = 468,
- [BNXT_ULP_CLASS_HID_3db4] = 469,
- [BNXT_ULP_CLASS_HID_3498] = 470,
- [BNXT_ULP_CLASS_HID_0988] = 471,
- [BNXT_ULP_CLASS_HID_00ec] = 472,
- [BNXT_ULP_CLASS_HID_3f44] = 473,
- [BNXT_ULP_CLASS_HID_36a8] = 474,
- [BNXT_ULP_CLASS_HID_0b58] = 475,
- [BNXT_ULP_CLASS_HID_02bc] = 476,
- [BNXT_ULP_CLASS_HID_5f48] = 477,
- [BNXT_ULP_CLASS_HID_56ac] = 478,
- [BNXT_ULP_CLASS_HID_2b5c] = 479,
- [BNXT_ULP_CLASS_HID_2280] = 480,
- [BNXT_ULP_CLASS_HID_4000] = 481,
- [BNXT_ULP_CLASS_HID_5b64] = 482,
- [BNXT_ULP_CLASS_HID_2c14] = 483,
- [BNXT_ULP_CLASS_HID_2778] = 484,
- [BNXT_ULP_CLASS_HID_18f8] = 485,
- [BNXT_ULP_CLASS_HID_13dc] = 486,
- [BNXT_ULP_CLASS_HID_4c18] = 487,
- [BNXT_ULP_CLASS_HID_477c] = 488,
- [BNXT_ULP_CLASS_HID_1a88] = 489,
- [BNXT_ULP_CLASS_HID_15ec] = 490,
- [BNXT_ULP_CLASS_HID_4e28] = 491,
- [BNXT_ULP_CLASS_HID_490c] = 492,
- [BNXT_ULP_CLASS_HID_3a8c] = 493,
- [BNXT_ULP_CLASS_HID_35f0] = 494,
- [BNXT_ULP_CLASS_HID_06e0] = 495,
- [BNXT_ULP_CLASS_HID_01c4] = 496,
- [BNXT_ULP_CLASS_HID_1a08] = 497,
- [BNXT_ULP_CLASS_HID_12ec] = 498,
- [BNXT_ULP_CLASS_HID_4ea8] = 499,
- [BNXT_ULP_CLASS_HID_478c] = 500,
- [BNXT_ULP_CLASS_HID_0d4c] = 501,
- [BNXT_ULP_CLASS_HID_0a20] = 502,
- [BNXT_ULP_CLASS_HID_1930] = 503,
- [BNXT_ULP_CLASS_HID_1614] = 504,
- [BNXT_ULP_CLASS_HID_3a0c] = 505,
- [BNXT_ULP_CLASS_HID_32e0] = 506,
- [BNXT_ULP_CLASS_HID_01f0] = 507,
- [BNXT_ULP_CLASS_HID_1ed4] = 508,
- [BNXT_ULP_CLASS_HID_2d40] = 509,
- [BNXT_ULP_CLASS_HID_2a24] = 510,
- [BNXT_ULP_CLASS_HID_3934] = 511,
- [BNXT_ULP_CLASS_HID_3608] = 512,
- [BNXT_ULP_CLASS_HID_5e60] = 513,
- [BNXT_ULP_CLASS_HID_5744] = 514,
- [BNXT_ULP_CLASS_HID_2a54] = 515,
- [BNXT_ULP_CLASS_HID_2328] = 516,
- [BNXT_ULP_CLASS_HID_71a4] = 517,
- [BNXT_ULP_CLASS_HID_4e78] = 518,
- [BNXT_ULP_CLASS_HID_5d88] = 519,
- [BNXT_ULP_CLASS_HID_5a6c] = 520,
- [BNXT_ULP_CLASS_HID_11a8] = 521,
- [BNXT_ULP_CLASS_HID_7738] = 522,
- [BNXT_ULP_CLASS_HID_4a48] = 523,
- [BNXT_ULP_CLASS_HID_432c] = 524,
- [BNXT_ULP_CLASS_HID_08ec] = 525,
- [BNXT_ULP_CLASS_HID_01c0] = 526,
- [BNXT_ULP_CLASS_HID_14d0] = 527,
- [BNXT_ULP_CLASS_HID_7a60] = 528,
- [BNXT_ULP_CLASS_HID_1d90] = 529,
- [BNXT_ULP_CLASS_HID_14b4] = 530,
- [BNXT_ULP_CLASS_HID_70f0] = 531,
- [BNXT_ULP_CLASS_HID_4814] = 532,
- [BNXT_ULP_CLASS_HID_3d94] = 533,
- [BNXT_ULP_CLASS_HID_34b8] = 534,
- [BNXT_ULP_CLASS_HID_09a8] = 535,
- [BNXT_ULP_CLASS_HID_00cc] = 536,
- [BNXT_ULP_CLASS_HID_3f64] = 537,
- [BNXT_ULP_CLASS_HID_3688] = 538,
- [BNXT_ULP_CLASS_HID_0b78] = 539,
- [BNXT_ULP_CLASS_HID_029c] = 540,
- [BNXT_ULP_CLASS_HID_5f68] = 541,
- [BNXT_ULP_CLASS_HID_568c] = 542,
- [BNXT_ULP_CLASS_HID_2b7c] = 543,
- [BNXT_ULP_CLASS_HID_22a0] = 544,
- [BNXT_ULP_CLASS_HID_4020] = 545,
- [BNXT_ULP_CLASS_HID_5b44] = 546,
- [BNXT_ULP_CLASS_HID_2c34] = 547,
- [BNXT_ULP_CLASS_HID_2758] = 548,
- [BNXT_ULP_CLASS_HID_18d8] = 549,
- [BNXT_ULP_CLASS_HID_13fc] = 550,
- [BNXT_ULP_CLASS_HID_4c38] = 551,
- [BNXT_ULP_CLASS_HID_475c] = 552,
- [BNXT_ULP_CLASS_HID_1aa8] = 553,
- [BNXT_ULP_CLASS_HID_15cc] = 554,
- [BNXT_ULP_CLASS_HID_4e08] = 555,
- [BNXT_ULP_CLASS_HID_492c] = 556,
- [BNXT_ULP_CLASS_HID_3aac] = 557,
- [BNXT_ULP_CLASS_HID_35d0] = 558,
- [BNXT_ULP_CLASS_HID_06c0] = 559,
- [BNXT_ULP_CLASS_HID_01e4] = 560,
- [BNXT_ULP_CLASS_HID_4d32] = 561,
- [BNXT_ULP_CLASS_HID_54aa] = 562,
- [BNXT_ULP_CLASS_HID_0686] = 563,
- [BNXT_ULP_CLASS_HID_540e] = 564,
- [BNXT_ULP_CLASS_HID_2e3c] = 565,
- [BNXT_ULP_CLASS_HID_3a20] = 566,
- [BNXT_ULP_CLASS_HID_46f0] = 567,
- [BNXT_ULP_CLASS_HID_52e4] = 568,
- [BNXT_ULP_CLASS_HID_55e4] = 569,
- [BNXT_ULP_CLASS_HID_21f8] = 570,
- [BNXT_ULP_CLASS_HID_75e8] = 571,
- [BNXT_ULP_CLASS_HID_41fc] = 572,
- [BNXT_ULP_CLASS_HID_4d12] = 573,
- [BNXT_ULP_CLASS_HID_548a] = 574,
- [BNXT_ULP_CLASS_HID_3356] = 575,
- [BNXT_ULP_CLASS_HID_1ace] = 576,
- [BNXT_ULP_CLASS_HID_1a9a] = 577,
- [BNXT_ULP_CLASS_HID_4d46] = 578,
- [BNXT_ULP_CLASS_HID_2812] = 579,
- [BNXT_ULP_CLASS_HID_338a] = 580,
- [BNXT_ULP_CLASS_HID_06e6] = 581,
- [BNXT_ULP_CLASS_HID_546e] = 582,
- [BNXT_ULP_CLASS_HID_46ee] = 583,
- [BNXT_ULP_CLASS_HID_0d22] = 584,
- [BNXT_ULP_CLASS_HID_26e2] = 585,
- [BNXT_ULP_CLASS_HID_746a] = 586,
- [BNXT_ULP_CLASS_HID_1fa6] = 587,
- [BNXT_ULP_CLASS_HID_2d2e] = 588,
- [BNXT_ULP_CLASS_HID_4ef2] = 589,
- [BNXT_ULP_CLASS_HID_576a] = 590,
- [BNXT_ULP_CLASS_HID_30b6] = 591,
- [BNXT_ULP_CLASS_HID_192e] = 592,
- [BNXT_ULP_CLASS_HID_197a] = 593,
- [BNXT_ULP_CLASS_HID_4ea6] = 594,
- [BNXT_ULP_CLASS_HID_2bf2] = 595,
- [BNXT_ULP_CLASS_HID_306a] = 596,
- [BNXT_ULP_CLASS_HID_06c6] = 597,
- [BNXT_ULP_CLASS_HID_544e] = 598,
- [BNXT_ULP_CLASS_HID_46ce] = 599,
- [BNXT_ULP_CLASS_HID_0d02] = 600,
- [BNXT_ULP_CLASS_HID_26c2] = 601,
- [BNXT_ULP_CLASS_HID_744a] = 602,
- [BNXT_ULP_CLASS_HID_1f86] = 603,
- [BNXT_ULP_CLASS_HID_2d0e] = 604,
- [BNXT_ULP_CLASS_HID_2e1c] = 605,
- [BNXT_ULP_CLASS_HID_3a00] = 606,
- [BNXT_ULP_CLASS_HID_46d0] = 607,
- [BNXT_ULP_CLASS_HID_52c4] = 608,
- [BNXT_ULP_CLASS_HID_4e10] = 609,
- [BNXT_ULP_CLASS_HID_5a04] = 610,
- [BNXT_ULP_CLASS_HID_1f98] = 611,
- [BNXT_ULP_CLASS_HID_72f8] = 612,
- [BNXT_ULP_CLASS_HID_0a78] = 613,
- [BNXT_ULP_CLASS_HID_166c] = 614,
- [BNXT_ULP_CLASS_HID_233c] = 615,
- [BNXT_ULP_CLASS_HID_0f20] = 616,
- [BNXT_ULP_CLASS_HID_2a7c] = 617,
- [BNXT_ULP_CLASS_HID_3660] = 618,
- [BNXT_ULP_CLASS_HID_4330] = 619,
- [BNXT_ULP_CLASS_HID_2f24] = 620,
- [BNXT_ULP_CLASS_HID_5584] = 621,
- [BNXT_ULP_CLASS_HID_2198] = 622,
- [BNXT_ULP_CLASS_HID_7588] = 623,
- [BNXT_ULP_CLASS_HID_419c] = 624,
- [BNXT_ULP_CLASS_HID_7758] = 625,
- [BNXT_ULP_CLASS_HID_43ac] = 626,
- [BNXT_ULP_CLASS_HID_0c10] = 627,
- [BNXT_ULP_CLASS_HID_1864] = 628,
- [BNXT_ULP_CLASS_HID_30c8] = 629,
- [BNXT_ULP_CLASS_HID_1cdc] = 630,
- [BNXT_ULP_CLASS_HID_50cc] = 631,
- [BNXT_ULP_CLASS_HID_3d20] = 632,
- [BNXT_ULP_CLASS_HID_529c] = 633,
- [BNXT_ULP_CLASS_HID_3ef0] = 634,
- [BNXT_ULP_CLASS_HID_72e0] = 635,
- [BNXT_ULP_CLASS_HID_5ef4] = 636,
- [BNXT_ULP_CLASS_HID_2dfc] = 637,
- [BNXT_ULP_CLASS_HID_39e0] = 638,
- [BNXT_ULP_CLASS_HID_4530] = 639,
- [BNXT_ULP_CLASS_HID_5124] = 640,
- [BNXT_ULP_CLASS_HID_4df0] = 641,
- [BNXT_ULP_CLASS_HID_59e4] = 642,
- [BNXT_ULP_CLASS_HID_1c78] = 643,
- [BNXT_ULP_CLASS_HID_7118] = 644,
- [BNXT_ULP_CLASS_HID_0998] = 645,
- [BNXT_ULP_CLASS_HID_158c] = 646,
- [BNXT_ULP_CLASS_HID_20dc] = 647,
- [BNXT_ULP_CLASS_HID_0cc0] = 648,
- [BNXT_ULP_CLASS_HID_299c] = 649,
- [BNXT_ULP_CLASS_HID_3580] = 650,
- [BNXT_ULP_CLASS_HID_40d0] = 651,
- [BNXT_ULP_CLASS_HID_2cc4] = 652,
- [BNXT_ULP_CLASS_HID_55a4] = 653,
- [BNXT_ULP_CLASS_HID_21b8] = 654,
- [BNXT_ULP_CLASS_HID_75a8] = 655,
- [BNXT_ULP_CLASS_HID_41bc] = 656,
- [BNXT_ULP_CLASS_HID_7778] = 657,
- [BNXT_ULP_CLASS_HID_438c] = 658,
- [BNXT_ULP_CLASS_HID_0c30] = 659,
- [BNXT_ULP_CLASS_HID_1844] = 660,
- [BNXT_ULP_CLASS_HID_30e8] = 661,
- [BNXT_ULP_CLASS_HID_1cfc] = 662,
- [BNXT_ULP_CLASS_HID_50ec] = 663,
- [BNXT_ULP_CLASS_HID_3d00] = 664,
- [BNXT_ULP_CLASS_HID_52bc] = 665,
- [BNXT_ULP_CLASS_HID_3ed0] = 666,
- [BNXT_ULP_CLASS_HID_72c0] = 667,
- [BNXT_ULP_CLASS_HID_5ed4] = 668,
- [BNXT_ULP_CLASS_HID_3866] = 669,
- [BNXT_ULP_CLASS_HID_381e] = 670,
- [BNXT_ULP_CLASS_HID_3860] = 671,
- [BNXT_ULP_CLASS_HID_0454] = 672,
- [BNXT_ULP_CLASS_HID_3818] = 673,
- [BNXT_ULP_CLASS_HID_042c] = 674,
- [BNXT_ULP_CLASS_HID_3846] = 675,
- [BNXT_ULP_CLASS_HID_387e] = 676,
- [BNXT_ULP_CLASS_HID_3ba6] = 677,
- [BNXT_ULP_CLASS_HID_385e] = 678,
- [BNXT_ULP_CLASS_HID_3840] = 679,
- [BNXT_ULP_CLASS_HID_0474] = 680,
- [BNXT_ULP_CLASS_HID_3878] = 681,
- [BNXT_ULP_CLASS_HID_044c] = 682,
- [BNXT_ULP_CLASS_HID_3ba0] = 683,
- [BNXT_ULP_CLASS_HID_0794] = 684,
- [BNXT_ULP_CLASS_HID_3858] = 685,
- [BNXT_ULP_CLASS_HID_046c] = 686
+ [BNXT_ULP_CLASS_HID_3612] = 345,
+ [BNXT_ULP_CLASS_HID_66da] = 346,
+ [BNXT_ULP_CLASS_HID_6165] = 347,
+ [BNXT_ULP_CLASS_HID_2aa1] = 348,
+ [BNXT_ULP_CLASS_HID_09cd] = 349,
+ [BNXT_ULP_CLASS_HID_3845] = 350,
+ [BNXT_ULP_CLASS_HID_11e9] = 351,
+ [BNXT_ULP_CLASS_HID_4361] = 352,
+ [BNXT_ULP_CLASS_HID_218d] = 353,
+ [BNXT_ULP_CLASS_HID_5105] = 354,
+ [BNXT_ULP_CLASS_HID_0c89] = 355,
+ [BNXT_ULP_CLASS_HID_3e81] = 356,
+ [BNXT_ULP_CLASS_HID_1dad] = 357,
+ [BNXT_ULP_CLASS_HID_4ca5] = 358,
+ [BNXT_ULP_CLASS_HID_25c9] = 359,
+ [BNXT_ULP_CLASS_HID_57c1] = 360,
+ [BNXT_ULP_CLASS_HID_33ed] = 361,
+ [BNXT_ULP_CLASS_HID_65e5] = 362,
+ [BNXT_ULP_CLASS_HID_6dd9] = 363,
+ [BNXT_ULP_CLASS_HID_261d] = 364,
+ [BNXT_ULP_CLASS_HID_0571] = 365,
+ [BNXT_ULP_CLASS_HID_34f9] = 366,
+ [BNXT_ULP_CLASS_HID_1d55] = 367,
+ [BNXT_ULP_CLASS_HID_4fdd] = 368,
+ [BNXT_ULP_CLASS_HID_2d31] = 369,
+ [BNXT_ULP_CLASS_HID_5db9] = 370,
+ [BNXT_ULP_CLASS_HID_0035] = 371,
+ [BNXT_ULP_CLASS_HID_323d] = 372,
+ [BNXT_ULP_CLASS_HID_1111] = 373,
+ [BNXT_ULP_CLASS_HID_4019] = 374,
+ [BNXT_ULP_CLASS_HID_2975] = 375,
+ [BNXT_ULP_CLASS_HID_5b7d] = 376,
+ [BNXT_ULP_CLASS_HID_3f51] = 377,
+ [BNXT_ULP_CLASS_HID_6959] = 378,
+ [BNXT_ULP_CLASS_HID_0e85] = 379,
+ [BNXT_ULP_CLASS_HID_380d] = 380,
+ [BNXT_ULP_CLASS_HID_1f21] = 381,
+ [BNXT_ULP_CLASS_HID_4ea9] = 382,
+ [BNXT_ULP_CLASS_HID_1705] = 383,
+ [BNXT_ULP_CLASS_HID_418d] = 384,
+ [BNXT_ULP_CLASS_HID_2721] = 385,
+ [BNXT_ULP_CLASS_HID_57a9] = 386,
+ [BNXT_ULP_CLASS_HID_1a25] = 387,
+ [BNXT_ULP_CLASS_HID_342d] = 388,
+ [BNXT_ULP_CLASS_HID_2b01] = 389,
+ [BNXT_ULP_CLASS_HID_5a09] = 390,
+ [BNXT_ULP_CLASS_HID_2325] = 391,
+ [BNXT_ULP_CLASS_HID_5d2d] = 392,
+ [BNXT_ULP_CLASS_HID_3101] = 393,
+ [BNXT_ULP_CLASS_HID_6309] = 394,
+ [BNXT_ULP_CLASS_HID_0bad] = 395,
+ [BNXT_ULP_CLASS_HID_2535] = 396,
+ [BNXT_ULP_CLASS_HID_1869] = 397,
+ [BNXT_ULP_CLASS_HID_4bf1] = 398,
+ [BNXT_ULP_CLASS_HID_136d] = 399,
+ [BNXT_ULP_CLASS_HID_43f5] = 400,
+ [BNXT_ULP_CLASS_HID_2129] = 401,
+ [BNXT_ULP_CLASS_HID_53b1] = 402,
+ [BNXT_ULP_CLASS_HID_072d] = 403,
+ [BNXT_ULP_CLASS_HID_3135] = 404,
+ [BNXT_ULP_CLASS_HID_1429] = 405,
+ [BNXT_ULP_CLASS_HID_4731] = 406,
+ [BNXT_ULP_CLASS_HID_2f6d] = 407,
+ [BNXT_ULP_CLASS_HID_5f75] = 408,
+ [BNXT_ULP_CLASS_HID_3d69] = 409,
+ [BNXT_ULP_CLASS_HID_6f71] = 410,
+ [BNXT_ULP_CLASS_HID_0dbd] = 411,
+ [BNXT_ULP_CLASS_HID_3f25] = 412,
+ [BNXT_ULP_CLASS_HID_1239] = 413,
+ [BNXT_ULP_CLASS_HID_4da1] = 414,
+ [BNXT_ULP_CLASS_HID_153d] = 415,
+ [BNXT_ULP_CLASS_HID_45a5] = 416,
+ [BNXT_ULP_CLASS_HID_3bb9] = 417,
+ [BNXT_ULP_CLASS_HID_55a1] = 418,
+ [BNXT_ULP_CLASS_HID_193d] = 419,
+ [BNXT_ULP_CLASS_HID_4b25] = 420,
+ [BNXT_ULP_CLASS_HID_2e39] = 421,
+ [BNXT_ULP_CLASS_HID_5921] = 422,
+ [BNXT_ULP_CLASS_HID_213d] = 423,
+ [BNXT_ULP_CLASS_HID_5125] = 424,
+ [BNXT_ULP_CLASS_HID_3739] = 425,
+ [BNXT_ULP_CLASS_HID_093d] = 426,
+ [BNXT_ULP_CLASS_HID_684d] = 427,
+ [BNXT_ULP_CLASS_HID_2389] = 428,
+ [BNXT_ULP_CLASS_HID_00e5] = 429,
+ [BNXT_ULP_CLASS_HID_316d] = 430,
+ [BNXT_ULP_CLASS_HID_18c1] = 431,
+ [BNXT_ULP_CLASS_HID_4a49] = 432,
+ [BNXT_ULP_CLASS_HID_28a5] = 433,
+ [BNXT_ULP_CLASS_HID_582d] = 434,
+ [BNXT_ULP_CLASS_HID_05a1] = 435,
+ [BNXT_ULP_CLASS_HID_37a9] = 436,
+ [BNXT_ULP_CLASS_HID_1485] = 437,
+ [BNXT_ULP_CLASS_HID_458d] = 438,
+ [BNXT_ULP_CLASS_HID_2ce1] = 439,
+ [BNXT_ULP_CLASS_HID_5ee9] = 440,
+ [BNXT_ULP_CLASS_HID_3ac5] = 441,
+ [BNXT_ULP_CLASS_HID_6ccd] = 442,
+ [BNXT_ULP_CLASS_HID_0b11] = 443,
+ [BNXT_ULP_CLASS_HID_3d99] = 444,
+ [BNXT_ULP_CLASS_HID_1ab5] = 445,
+ [BNXT_ULP_CLASS_HID_4b3d] = 446,
+ [BNXT_ULP_CLASS_HID_1291] = 447,
+ [BNXT_ULP_CLASS_HID_4419] = 448,
+ [BNXT_ULP_CLASS_HID_22b5] = 449,
+ [BNXT_ULP_CLASS_HID_523d] = 450,
+ [BNXT_ULP_CLASS_HID_1fb1] = 451,
+ [BNXT_ULP_CLASS_HID_31b9] = 452,
+ [BNXT_ULP_CLASS_HID_2e95] = 453,
+ [BNXT_ULP_CLASS_HID_5f9d] = 454,
+ [BNXT_ULP_CLASS_HID_26b1] = 455,
+ [BNXT_ULP_CLASS_HID_58b9] = 456,
+ [BNXT_ULP_CLASS_HID_3495] = 457,
+ [BNXT_ULP_CLASS_HID_669d] = 458,
+ [BNXT_ULP_CLASS_HID_0e39] = 459,
+ [BNXT_ULP_CLASS_HID_20a1] = 460,
+ [BNXT_ULP_CLASS_HID_1dfd] = 461,
+ [BNXT_ULP_CLASS_HID_4e65] = 462,
+ [BNXT_ULP_CLASS_HID_16f9] = 463,
+ [BNXT_ULP_CLASS_HID_4661] = 464,
+ [BNXT_ULP_CLASS_HID_24bd] = 465,
+ [BNXT_ULP_CLASS_HID_5625] = 466,
+ [BNXT_ULP_CLASS_HID_02b9] = 467,
+ [BNXT_ULP_CLASS_HID_34a1] = 468,
+ [BNXT_ULP_CLASS_HID_11bd] = 469,
+ [BNXT_ULP_CLASS_HID_42a5] = 470,
+ [BNXT_ULP_CLASS_HID_2af9] = 471,
+ [BNXT_ULP_CLASS_HID_5ae1] = 472,
+ [BNXT_ULP_CLASS_HID_38fd] = 473,
+ [BNXT_ULP_CLASS_HID_6ae5] = 474,
+ [BNXT_ULP_CLASS_HID_0829] = 475,
+ [BNXT_ULP_CLASS_HID_3ab1] = 476,
+ [BNXT_ULP_CLASS_HID_17ad] = 477,
+ [BNXT_ULP_CLASS_HID_4835] = 478,
+ [BNXT_ULP_CLASS_HID_10a9] = 479,
+ [BNXT_ULP_CLASS_HID_4031] = 480,
+ [BNXT_ULP_CLASS_HID_3e2d] = 481,
+ [BNXT_ULP_CLASS_HID_5035] = 482,
+ [BNXT_ULP_CLASS_HID_1ca9] = 483,
+ [BNXT_ULP_CLASS_HID_4eb1] = 484,
+ [BNXT_ULP_CLASS_HID_2bad] = 485,
+ [BNXT_ULP_CLASS_HID_5cb5] = 486,
+ [BNXT_ULP_CLASS_HID_24a9] = 487,
+ [BNXT_ULP_CLASS_HID_54b1] = 488,
+ [BNXT_ULP_CLASS_HID_32ad] = 489,
+ [BNXT_ULP_CLASS_HID_0ca9] = 490,
+ [BNXT_ULP_CLASS_HID_7f35] = 491,
+ [BNXT_ULP_CLASS_HID_34f1] = 492,
+ [BNXT_ULP_CLASS_HID_179d] = 493,
+ [BNXT_ULP_CLASS_HID_2615] = 494,
+ [BNXT_ULP_CLASS_HID_0fb9] = 495,
+ [BNXT_ULP_CLASS_HID_5d31] = 496,
+ [BNXT_ULP_CLASS_HID_3fdd] = 497,
+ [BNXT_ULP_CLASS_HID_4f55] = 498,
+ [BNXT_ULP_CLASS_HID_12d9] = 499,
+ [BNXT_ULP_CLASS_HID_20d1] = 500,
+ [BNXT_ULP_CLASS_HID_03fd] = 501,
+ [BNXT_ULP_CLASS_HID_52f5] = 502,
+ [BNXT_ULP_CLASS_HID_3b99] = 503,
+ [BNXT_ULP_CLASS_HID_4991] = 504,
+ [BNXT_ULP_CLASS_HID_2dbd] = 505,
+ [BNXT_ULP_CLASS_HID_7bb5] = 506,
+ [BNXT_ULP_CLASS_HID_34c6] = 507,
+ [BNXT_ULP_CLASS_HID_0c22] = 508,
+ [BNXT_ULP_CLASS_HID_1cbe] = 509,
+ [BNXT_ULP_CLASS_HID_179a] = 510,
+ [BNXT_ULP_CLASS_HID_59be] = 511,
+ [BNXT_ULP_CLASS_HID_515a] = 512,
+ [BNXT_ULP_CLASS_HID_1c72] = 513,
+ [BNXT_ULP_CLASS_HID_171e] = 514,
+ [BNXT_ULP_CLASS_HID_19c8] = 515,
+ [BNXT_ULP_CLASS_HID_112c] = 516,
+ [BNXT_ULP_CLASS_HID_4d68] = 517,
+ [BNXT_ULP_CLASS_HID_444c] = 518,
+ [BNXT_ULP_CLASS_HID_0e8c] = 519,
+ [BNXT_ULP_CLASS_HID_09e0] = 520,
+ [BNXT_ULP_CLASS_HID_1af0] = 521,
+ [BNXT_ULP_CLASS_HID_15d4] = 522,
+ [BNXT_ULP_CLASS_HID_1dd0] = 523,
+ [BNXT_ULP_CLASS_HID_14f4] = 524,
+ [BNXT_ULP_CLASS_HID_70b0] = 525,
+ [BNXT_ULP_CLASS_HID_4854] = 526,
+ [BNXT_ULP_CLASS_HID_3dd4] = 527,
+ [BNXT_ULP_CLASS_HID_34f8] = 528,
+ [BNXT_ULP_CLASS_HID_09e8] = 529,
+ [BNXT_ULP_CLASS_HID_008c] = 530,
+ [BNXT_ULP_CLASS_HID_34e6] = 531,
+ [BNXT_ULP_CLASS_HID_0c02] = 532,
+ [BNXT_ULP_CLASS_HID_1c9e] = 533,
+ [BNXT_ULP_CLASS_HID_17ba] = 534,
+ [BNXT_ULP_CLASS_HID_429e] = 535,
+ [BNXT_ULP_CLASS_HID_5dba] = 536,
+ [BNXT_ULP_CLASS_HID_2a16] = 537,
+ [BNXT_ULP_CLASS_HID_2532] = 538,
+ [BNXT_ULP_CLASS_HID_2da2] = 539,
+ [BNXT_ULP_CLASS_HID_24fe] = 540,
+ [BNXT_ULP_CLASS_HID_355a] = 541,
+ [BNXT_ULP_CLASS_HID_0c76] = 542,
+ [BNXT_ULP_CLASS_HID_13e6] = 543,
+ [BNXT_ULP_CLASS_HID_7276] = 544,
+ [BNXT_ULP_CLASS_HID_42d2] = 545,
+ [BNXT_ULP_CLASS_HID_5dee] = 546,
+ [BNXT_ULP_CLASS_HID_59de] = 547,
+ [BNXT_ULP_CLASS_HID_513a] = 548,
+ [BNXT_ULP_CLASS_HID_1c12] = 549,
+ [BNXT_ULP_CLASS_HID_177e] = 550,
+ [BNXT_ULP_CLASS_HID_0e92] = 551,
+ [BNXT_ULP_CLASS_HID_09fe] = 552,
+ [BNXT_ULP_CLASS_HID_5c1a] = 553,
+ [BNXT_ULP_CLASS_HID_5746] = 554,
+ [BNXT_ULP_CLASS_HID_79da] = 555,
+ [BNXT_ULP_CLASS_HID_7106] = 556,
+ [BNXT_ULP_CLASS_HID_3c1e] = 557,
+ [BNXT_ULP_CLASS_HID_377a] = 558,
+ [BNXT_ULP_CLASS_HID_2e9e] = 559,
+ [BNXT_ULP_CLASS_HID_29fa] = 560,
+ [BNXT_ULP_CLASS_HID_14d2] = 561,
+ [BNXT_ULP_CLASS_HID_7742] = 562,
+ [BNXT_ULP_CLASS_HID_3706] = 563,
+ [BNXT_ULP_CLASS_HID_0fe2] = 564,
+ [BNXT_ULP_CLASS_HID_1f7e] = 565,
+ [BNXT_ULP_CLASS_HID_145a] = 566,
+ [BNXT_ULP_CLASS_HID_417e] = 567,
+ [BNXT_ULP_CLASS_HID_5e5a] = 568,
+ [BNXT_ULP_CLASS_HID_29f6] = 569,
+ [BNXT_ULP_CLASS_HID_26d2] = 570,
+ [BNXT_ULP_CLASS_HID_2e42] = 571,
+ [BNXT_ULP_CLASS_HID_271e] = 572,
+ [BNXT_ULP_CLASS_HID_36ba] = 573,
+ [BNXT_ULP_CLASS_HID_0f96] = 574,
+ [BNXT_ULP_CLASS_HID_1006] = 575,
+ [BNXT_ULP_CLASS_HID_7196] = 576,
+ [BNXT_ULP_CLASS_HID_4132] = 577,
+ [BNXT_ULP_CLASS_HID_5e0e] = 578,
+ [BNXT_ULP_CLASS_HID_59fe] = 579,
+ [BNXT_ULP_CLASS_HID_511a] = 580,
+ [BNXT_ULP_CLASS_HID_1c32] = 581,
+ [BNXT_ULP_CLASS_HID_175e] = 582,
+ [BNXT_ULP_CLASS_HID_0eb2] = 583,
+ [BNXT_ULP_CLASS_HID_09de] = 584,
+ [BNXT_ULP_CLASS_HID_5c3a] = 585,
+ [BNXT_ULP_CLASS_HID_5766] = 586,
+ [BNXT_ULP_CLASS_HID_79fa] = 587,
+ [BNXT_ULP_CLASS_HID_7126] = 588,
+ [BNXT_ULP_CLASS_HID_3c3e] = 589,
+ [BNXT_ULP_CLASS_HID_375a] = 590,
+ [BNXT_ULP_CLASS_HID_2ebe] = 591,
+ [BNXT_ULP_CLASS_HID_29da] = 592,
+ [BNXT_ULP_CLASS_HID_14f2] = 593,
+ [BNXT_ULP_CLASS_HID_7762] = 594,
+ [BNXT_ULP_CLASS_HID_19e8] = 595,
+ [BNXT_ULP_CLASS_HID_110c] = 596,
+ [BNXT_ULP_CLASS_HID_4d48] = 597,
+ [BNXT_ULP_CLASS_HID_446c] = 598,
+ [BNXT_ULP_CLASS_HID_0eac] = 599,
+ [BNXT_ULP_CLASS_HID_09c0] = 600,
+ [BNXT_ULP_CLASS_HID_1ad0] = 601,
+ [BNXT_ULP_CLASS_HID_15f4] = 602,
+ [BNXT_ULP_CLASS_HID_39ec] = 603,
+ [BNXT_ULP_CLASS_HID_3100] = 604,
+ [BNXT_ULP_CLASS_HID_0210] = 605,
+ [BNXT_ULP_CLASS_HID_1d34] = 606,
+ [BNXT_ULP_CLASS_HID_2ea0] = 607,
+ [BNXT_ULP_CLASS_HID_29c4] = 608,
+ [BNXT_ULP_CLASS_HID_3ad4] = 609,
+ [BNXT_ULP_CLASS_HID_35e8] = 610,
+ [BNXT_ULP_CLASS_HID_5d80] = 611,
+ [BNXT_ULP_CLASS_HID_54a4] = 612,
+ [BNXT_ULP_CLASS_HID_29b4] = 613,
+ [BNXT_ULP_CLASS_HID_20c8] = 614,
+ [BNXT_ULP_CLASS_HID_7244] = 615,
+ [BNXT_ULP_CLASS_HID_4d98] = 616,
+ [BNXT_ULP_CLASS_HID_5e68] = 617,
+ [BNXT_ULP_CLASS_HID_598c] = 618,
+ [BNXT_ULP_CLASS_HID_1248] = 619,
+ [BNXT_ULP_CLASS_HID_74d8] = 620,
+ [BNXT_ULP_CLASS_HID_49a8] = 621,
+ [BNXT_ULP_CLASS_HID_40cc] = 622,
+ [BNXT_ULP_CLASS_HID_0b0c] = 623,
+ [BNXT_ULP_CLASS_HID_0220] = 624,
+ [BNXT_ULP_CLASS_HID_1730] = 625,
+ [BNXT_ULP_CLASS_HID_7980] = 626,
+ [BNXT_ULP_CLASS_HID_1db0] = 627,
+ [BNXT_ULP_CLASS_HID_1494] = 628,
+ [BNXT_ULP_CLASS_HID_70d0] = 629,
+ [BNXT_ULP_CLASS_HID_4834] = 630,
+ [BNXT_ULP_CLASS_HID_3db4] = 631,
+ [BNXT_ULP_CLASS_HID_3498] = 632,
+ [BNXT_ULP_CLASS_HID_0988] = 633,
+ [BNXT_ULP_CLASS_HID_00ec] = 634,
+ [BNXT_ULP_CLASS_HID_3f44] = 635,
+ [BNXT_ULP_CLASS_HID_36a8] = 636,
+ [BNXT_ULP_CLASS_HID_0b58] = 637,
+ [BNXT_ULP_CLASS_HID_02bc] = 638,
+ [BNXT_ULP_CLASS_HID_5f48] = 639,
+ [BNXT_ULP_CLASS_HID_56ac] = 640,
+ [BNXT_ULP_CLASS_HID_2b5c] = 641,
+ [BNXT_ULP_CLASS_HID_2280] = 642,
+ [BNXT_ULP_CLASS_HID_4000] = 643,
+ [BNXT_ULP_CLASS_HID_5b64] = 644,
+ [BNXT_ULP_CLASS_HID_2c14] = 645,
+ [BNXT_ULP_CLASS_HID_2778] = 646,
+ [BNXT_ULP_CLASS_HID_18f8] = 647,
+ [BNXT_ULP_CLASS_HID_13dc] = 648,
+ [BNXT_ULP_CLASS_HID_4c18] = 649,
+ [BNXT_ULP_CLASS_HID_477c] = 650,
+ [BNXT_ULP_CLASS_HID_1a88] = 651,
+ [BNXT_ULP_CLASS_HID_15ec] = 652,
+ [BNXT_ULP_CLASS_HID_4e28] = 653,
+ [BNXT_ULP_CLASS_HID_490c] = 654,
+ [BNXT_ULP_CLASS_HID_3a8c] = 655,
+ [BNXT_ULP_CLASS_HID_35f0] = 656,
+ [BNXT_ULP_CLASS_HID_06e0] = 657,
+ [BNXT_ULP_CLASS_HID_01c4] = 658,
+ [BNXT_ULP_CLASS_HID_1a08] = 659,
+ [BNXT_ULP_CLASS_HID_12ec] = 660,
+ [BNXT_ULP_CLASS_HID_4ea8] = 661,
+ [BNXT_ULP_CLASS_HID_478c] = 662,
+ [BNXT_ULP_CLASS_HID_0d4c] = 663,
+ [BNXT_ULP_CLASS_HID_0a20] = 664,
+ [BNXT_ULP_CLASS_HID_1930] = 665,
+ [BNXT_ULP_CLASS_HID_1614] = 666,
+ [BNXT_ULP_CLASS_HID_3a0c] = 667,
+ [BNXT_ULP_CLASS_HID_32e0] = 668,
+ [BNXT_ULP_CLASS_HID_01f0] = 669,
+ [BNXT_ULP_CLASS_HID_1ed4] = 670,
+ [BNXT_ULP_CLASS_HID_2d40] = 671,
+ [BNXT_ULP_CLASS_HID_2a24] = 672,
+ [BNXT_ULP_CLASS_HID_3934] = 673,
+ [BNXT_ULP_CLASS_HID_3608] = 674,
+ [BNXT_ULP_CLASS_HID_5e60] = 675,
+ [BNXT_ULP_CLASS_HID_5744] = 676,
+ [BNXT_ULP_CLASS_HID_2a54] = 677,
+ [BNXT_ULP_CLASS_HID_2328] = 678,
+ [BNXT_ULP_CLASS_HID_71a4] = 679,
+ [BNXT_ULP_CLASS_HID_4e78] = 680,
+ [BNXT_ULP_CLASS_HID_5d88] = 681,
+ [BNXT_ULP_CLASS_HID_5a6c] = 682,
+ [BNXT_ULP_CLASS_HID_11a8] = 683,
+ [BNXT_ULP_CLASS_HID_7738] = 684,
+ [BNXT_ULP_CLASS_HID_4a48] = 685,
+ [BNXT_ULP_CLASS_HID_432c] = 686,
+ [BNXT_ULP_CLASS_HID_08ec] = 687,
+ [BNXT_ULP_CLASS_HID_01c0] = 688,
+ [BNXT_ULP_CLASS_HID_14d0] = 689,
+ [BNXT_ULP_CLASS_HID_7a60] = 690,
+ [BNXT_ULP_CLASS_HID_1d90] = 691,
+ [BNXT_ULP_CLASS_HID_14b4] = 692,
+ [BNXT_ULP_CLASS_HID_70f0] = 693,
+ [BNXT_ULP_CLASS_HID_4814] = 694,
+ [BNXT_ULP_CLASS_HID_3d94] = 695,
+ [BNXT_ULP_CLASS_HID_34b8] = 696,
+ [BNXT_ULP_CLASS_HID_09a8] = 697,
+ [BNXT_ULP_CLASS_HID_00cc] = 698,
+ [BNXT_ULP_CLASS_HID_3f64] = 699,
+ [BNXT_ULP_CLASS_HID_3688] = 700,
+ [BNXT_ULP_CLASS_HID_0b78] = 701,
+ [BNXT_ULP_CLASS_HID_029c] = 702,
+ [BNXT_ULP_CLASS_HID_5f68] = 703,
+ [BNXT_ULP_CLASS_HID_568c] = 704,
+ [BNXT_ULP_CLASS_HID_2b7c] = 705,
+ [BNXT_ULP_CLASS_HID_22a0] = 706,
+ [BNXT_ULP_CLASS_HID_4020] = 707,
+ [BNXT_ULP_CLASS_HID_5b44] = 708,
+ [BNXT_ULP_CLASS_HID_2c34] = 709,
+ [BNXT_ULP_CLASS_HID_2758] = 710,
+ [BNXT_ULP_CLASS_HID_18d8] = 711,
+ [BNXT_ULP_CLASS_HID_13fc] = 712,
+ [BNXT_ULP_CLASS_HID_4c38] = 713,
+ [BNXT_ULP_CLASS_HID_475c] = 714,
+ [BNXT_ULP_CLASS_HID_1aa8] = 715,
+ [BNXT_ULP_CLASS_HID_15cc] = 716,
+ [BNXT_ULP_CLASS_HID_4e08] = 717,
+ [BNXT_ULP_CLASS_HID_492c] = 718,
+ [BNXT_ULP_CLASS_HID_3aac] = 719,
+ [BNXT_ULP_CLASS_HID_35d0] = 720,
+ [BNXT_ULP_CLASS_HID_06c0] = 721,
+ [BNXT_ULP_CLASS_HID_01e4] = 722,
+ [BNXT_ULP_CLASS_HID_4d32] = 723,
+ [BNXT_ULP_CLASS_HID_54aa] = 724,
+ [BNXT_ULP_CLASS_HID_0686] = 725,
+ [BNXT_ULP_CLASS_HID_540e] = 726,
+ [BNXT_ULP_CLASS_HID_2e3c] = 727,
+ [BNXT_ULP_CLASS_HID_3a20] = 728,
+ [BNXT_ULP_CLASS_HID_46f0] = 729,
+ [BNXT_ULP_CLASS_HID_52e4] = 730,
+ [BNXT_ULP_CLASS_HID_55e4] = 731,
+ [BNXT_ULP_CLASS_HID_21f8] = 732,
+ [BNXT_ULP_CLASS_HID_75e8] = 733,
+ [BNXT_ULP_CLASS_HID_41fc] = 734,
+ [BNXT_ULP_CLASS_HID_4d12] = 735,
+ [BNXT_ULP_CLASS_HID_548a] = 736,
+ [BNXT_ULP_CLASS_HID_3356] = 737,
+ [BNXT_ULP_CLASS_HID_1ace] = 738,
+ [BNXT_ULP_CLASS_HID_1a9a] = 739,
+ [BNXT_ULP_CLASS_HID_4d46] = 740,
+ [BNXT_ULP_CLASS_HID_2812] = 741,
+ [BNXT_ULP_CLASS_HID_338a] = 742,
+ [BNXT_ULP_CLASS_HID_06e6] = 743,
+ [BNXT_ULP_CLASS_HID_546e] = 744,
+ [BNXT_ULP_CLASS_HID_46ee] = 745,
+ [BNXT_ULP_CLASS_HID_0d22] = 746,
+ [BNXT_ULP_CLASS_HID_26e2] = 747,
+ [BNXT_ULP_CLASS_HID_746a] = 748,
+ [BNXT_ULP_CLASS_HID_1fa6] = 749,
+ [BNXT_ULP_CLASS_HID_2d2e] = 750,
+ [BNXT_ULP_CLASS_HID_4ef2] = 751,
+ [BNXT_ULP_CLASS_HID_576a] = 752,
+ [BNXT_ULP_CLASS_HID_30b6] = 753,
+ [BNXT_ULP_CLASS_HID_192e] = 754,
+ [BNXT_ULP_CLASS_HID_197a] = 755,
+ [BNXT_ULP_CLASS_HID_4ea6] = 756,
+ [BNXT_ULP_CLASS_HID_2bf2] = 757,
+ [BNXT_ULP_CLASS_HID_306a] = 758,
+ [BNXT_ULP_CLASS_HID_06c6] = 759,
+ [BNXT_ULP_CLASS_HID_544e] = 760,
+ [BNXT_ULP_CLASS_HID_46ce] = 761,
+ [BNXT_ULP_CLASS_HID_0d02] = 762,
+ [BNXT_ULP_CLASS_HID_26c2] = 763,
+ [BNXT_ULP_CLASS_HID_744a] = 764,
+ [BNXT_ULP_CLASS_HID_1f86] = 765,
+ [BNXT_ULP_CLASS_HID_2d0e] = 766,
+ [BNXT_ULP_CLASS_HID_2e1c] = 767,
+ [BNXT_ULP_CLASS_HID_3a00] = 768,
+ [BNXT_ULP_CLASS_HID_46d0] = 769,
+ [BNXT_ULP_CLASS_HID_52c4] = 770,
+ [BNXT_ULP_CLASS_HID_4e10] = 771,
+ [BNXT_ULP_CLASS_HID_5a04] = 772,
+ [BNXT_ULP_CLASS_HID_1f98] = 773,
+ [BNXT_ULP_CLASS_HID_72f8] = 774,
+ [BNXT_ULP_CLASS_HID_0a78] = 775,
+ [BNXT_ULP_CLASS_HID_166c] = 776,
+ [BNXT_ULP_CLASS_HID_233c] = 777,
+ [BNXT_ULP_CLASS_HID_0f20] = 778,
+ [BNXT_ULP_CLASS_HID_2a7c] = 779,
+ [BNXT_ULP_CLASS_HID_3660] = 780,
+ [BNXT_ULP_CLASS_HID_4330] = 781,
+ [BNXT_ULP_CLASS_HID_2f24] = 782,
+ [BNXT_ULP_CLASS_HID_5584] = 783,
+ [BNXT_ULP_CLASS_HID_2198] = 784,
+ [BNXT_ULP_CLASS_HID_7588] = 785,
+ [BNXT_ULP_CLASS_HID_419c] = 786,
+ [BNXT_ULP_CLASS_HID_7758] = 787,
+ [BNXT_ULP_CLASS_HID_43ac] = 788,
+ [BNXT_ULP_CLASS_HID_0c10] = 789,
+ [BNXT_ULP_CLASS_HID_1864] = 790,
+ [BNXT_ULP_CLASS_HID_30c8] = 791,
+ [BNXT_ULP_CLASS_HID_1cdc] = 792,
+ [BNXT_ULP_CLASS_HID_50cc] = 793,
+ [BNXT_ULP_CLASS_HID_3d20] = 794,
+ [BNXT_ULP_CLASS_HID_529c] = 795,
+ [BNXT_ULP_CLASS_HID_3ef0] = 796,
+ [BNXT_ULP_CLASS_HID_72e0] = 797,
+ [BNXT_ULP_CLASS_HID_5ef4] = 798,
+ [BNXT_ULP_CLASS_HID_2dfc] = 799,
+ [BNXT_ULP_CLASS_HID_39e0] = 800,
+ [BNXT_ULP_CLASS_HID_4530] = 801,
+ [BNXT_ULP_CLASS_HID_5124] = 802,
+ [BNXT_ULP_CLASS_HID_4df0] = 803,
+ [BNXT_ULP_CLASS_HID_59e4] = 804,
+ [BNXT_ULP_CLASS_HID_1c78] = 805,
+ [BNXT_ULP_CLASS_HID_7118] = 806,
+ [BNXT_ULP_CLASS_HID_0998] = 807,
+ [BNXT_ULP_CLASS_HID_158c] = 808,
+ [BNXT_ULP_CLASS_HID_20dc] = 809,
+ [BNXT_ULP_CLASS_HID_0cc0] = 810,
+ [BNXT_ULP_CLASS_HID_299c] = 811,
+ [BNXT_ULP_CLASS_HID_3580] = 812,
+ [BNXT_ULP_CLASS_HID_40d0] = 813,
+ [BNXT_ULP_CLASS_HID_2cc4] = 814,
+ [BNXT_ULP_CLASS_HID_55a4] = 815,
+ [BNXT_ULP_CLASS_HID_21b8] = 816,
+ [BNXT_ULP_CLASS_HID_75a8] = 817,
+ [BNXT_ULP_CLASS_HID_41bc] = 818,
+ [BNXT_ULP_CLASS_HID_7778] = 819,
+ [BNXT_ULP_CLASS_HID_438c] = 820,
+ [BNXT_ULP_CLASS_HID_0c30] = 821,
+ [BNXT_ULP_CLASS_HID_1844] = 822,
+ [BNXT_ULP_CLASS_HID_30e8] = 823,
+ [BNXT_ULP_CLASS_HID_1cfc] = 824,
+ [BNXT_ULP_CLASS_HID_50ec] = 825,
+ [BNXT_ULP_CLASS_HID_3d00] = 826,
+ [BNXT_ULP_CLASS_HID_52bc] = 827,
+ [BNXT_ULP_CLASS_HID_3ed0] = 828,
+ [BNXT_ULP_CLASS_HID_72c0] = 829,
+ [BNXT_ULP_CLASS_HID_5ed4] = 830,
+ [BNXT_ULP_CLASS_HID_3866] = 831,
+ [BNXT_ULP_CLASS_HID_381e] = 832,
+ [BNXT_ULP_CLASS_HID_3860] = 833,
+ [BNXT_ULP_CLASS_HID_0454] = 834,
+ [BNXT_ULP_CLASS_HID_3818] = 835,
+ [BNXT_ULP_CLASS_HID_042c] = 836,
+ [BNXT_ULP_CLASS_HID_3846] = 837,
+ [BNXT_ULP_CLASS_HID_387e] = 838,
+ [BNXT_ULP_CLASS_HID_3ba6] = 839,
+ [BNXT_ULP_CLASS_HID_385e] = 840,
+ [BNXT_ULP_CLASS_HID_3840] = 841,
+ [BNXT_ULP_CLASS_HID_0474] = 842,
+ [BNXT_ULP_CLASS_HID_3878] = 843,
+ [BNXT_ULP_CLASS_HID_044c] = 844,
+ [BNXT_ULP_CLASS_HID_3ba0] = 845,
+ [BNXT_ULP_CLASS_HID_0794] = 846,
+ [BNXT_ULP_CLASS_HID_3858] = 847,
+ [BNXT_ULP_CLASS_HID_046c] = 848
};
/* Array for the proto matcher list */
@@ -6964,8 +7126,3839 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_12_BITMASK_O_UDP_DST_PORT }
},
[345] = {
- .class_hid = BNXT_ULP_CLASS_HID_34c6,
+ .class_hid = BNXT_ULP_CLASS_HID_3612,
+ .class_tid = 2,
+ .hdr_sig_id = 0,
+ .flow_sig_id = 81920,
+ .flow_pattern_id = 0,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_F1 |
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT }
+ },
+ [346] = {
+ .class_hid = BNXT_ULP_CLASS_HID_66da,
+ .class_tid = 2,
+ .hdr_sig_id = 0,
+ .flow_sig_id = 81928,
+ .flow_pattern_id = 0,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_F1 |
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT }
+ },
+ [347] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6165,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 1313792,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC }
+ },
+ [348] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2aa1,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 1321984,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC }
+ },
+ [349] = {
+ .class_hid = BNXT_ULP_CLASS_HID_09cd,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 3410944,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }
+ },
+ [350] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3845,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 3419136,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }
+ },
+ [351] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11e9,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 2148797440,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [352] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4361,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 2148805632,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [353] = {
+ .class_hid = BNXT_ULP_CLASS_HID_218d,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 2150894592,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [354] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5105,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 2150902784,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [355] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0c89,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 4296281088,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [356] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3e81,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 4296289280,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [357] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1dad,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 4298378240,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [358] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4ca5,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 4298386432,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [359] = {
+ .class_hid = BNXT_ULP_CLASS_HID_25c9,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 6443764736,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [360] = {
+ .class_hid = BNXT_ULP_CLASS_HID_57c1,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 6443772928,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [361] = {
+ .class_hid = BNXT_ULP_CLASS_HID_33ed,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 6445861888,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [362] = {
+ .class_hid = BNXT_ULP_CLASS_HID_65e5,
+ .class_tid = 2,
+ .hdr_sig_id = 1,
+ .flow_sig_id = 6445870080,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [363] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6dd9,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 1313792,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }
+ },
+ [364] = {
+ .class_hid = BNXT_ULP_CLASS_HID_261d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 1321984,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }
+ },
+ [365] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0571,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 3410944,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
+ },
+ [366] = {
+ .class_hid = BNXT_ULP_CLASS_HID_34f9,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 3419136,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
+ },
+ [367] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1d55,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 2148797440,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [368] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4fdd,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 2148805632,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [369] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2d31,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 2150894592,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [370] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5db9,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 2150902784,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [371] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0035,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 4296281088,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [372] = {
+ .class_hid = BNXT_ULP_CLASS_HID_323d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 4296289280,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [373] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1111,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 4298378240,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [374] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4019,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 4298386432,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [375] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2975,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 6443764736,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [376] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5b7d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 6443772928,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [377] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3f51,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 6445861888,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [378] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6959,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 6445870080,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [379] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0e85,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 8591248384,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [380] = {
+ .class_hid = BNXT_ULP_CLASS_HID_380d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 8591256576,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [381] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1f21,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 8593345536,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [382] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4ea9,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 8593353728,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [383] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1705,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 10738732032,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [384] = {
+ .class_hid = BNXT_ULP_CLASS_HID_418d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 10738740224,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [385] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2721,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 10740829184,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [386] = {
+ .class_hid = BNXT_ULP_CLASS_HID_57a9,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 10740837376,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [387] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1a25,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 12886215680,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [388] = {
+ .class_hid = BNXT_ULP_CLASS_HID_342d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 12886223872,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [389] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2b01,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 12888312832,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [390] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5a09,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 12888321024,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [391] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2325,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 15033699328,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [392] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5d2d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 15033707520,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [393] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3101,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 15035796480,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [394] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6309,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 15035804672,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ },
+ [395] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0bad,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 17181182976,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [396] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2535,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 17181191168,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [397] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1869,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 17183280128,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [398] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4bf1,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 17183288320,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [399] = {
+ .class_hid = BNXT_ULP_CLASS_HID_136d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 19328666624,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [400] = {
+ .class_hid = BNXT_ULP_CLASS_HID_43f5,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 19328674816,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [401] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2129,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 19330763776,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [402] = {
+ .class_hid = BNXT_ULP_CLASS_HID_53b1,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 19330771968,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [403] = {
+ .class_hid = BNXT_ULP_CLASS_HID_072d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 21476150272,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [404] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3135,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 21476158464,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [405] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1429,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 21478247424,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [406] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4731,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 21478255616,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [407] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2f6d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 23623633920,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [408] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5f75,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 23623642112,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [409] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3d69,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 23625731072,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [410] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6f71,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 23625739264,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [411] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0dbd,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 25771117568,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [412] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3f25,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 25771125760,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [413] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1239,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 25773214720,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [414] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4da1,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 25773222912,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [415] = {
+ .class_hid = BNXT_ULP_CLASS_HID_153d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 27918601216,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [416] = {
+ .class_hid = BNXT_ULP_CLASS_HID_45a5,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 27918609408,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [417] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3bb9,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 27920698368,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [418] = {
+ .class_hid = BNXT_ULP_CLASS_HID_55a1,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 27920706560,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [419] = {
+ .class_hid = BNXT_ULP_CLASS_HID_193d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 30066084864,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [420] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4b25,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 30066093056,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [421] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2e39,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 30068182016,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [422] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5921,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 30068190208,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [423] = {
+ .class_hid = BNXT_ULP_CLASS_HID_213d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 32213568512,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [424] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5125,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 32213576704,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [425] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3739,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 32215665664,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [426] = {
+ .class_hid = BNXT_ULP_CLASS_HID_093d,
+ .class_tid = 2,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 32215673856,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ },
+ [427] = {
+ .class_hid = BNXT_ULP_CLASS_HID_684d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1313792,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
+ },
+ [428] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2389,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1321984,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
+ },
+ [429] = {
+ .class_hid = BNXT_ULP_CLASS_HID_00e5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3410944,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
+ },
+ [430] = {
+ .class_hid = BNXT_ULP_CLASS_HID_316d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3419136,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
+ },
+ [431] = {
+ .class_hid = BNXT_ULP_CLASS_HID_18c1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2148797440,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [432] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4a49,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2148805632,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [433] = {
+ .class_hid = BNXT_ULP_CLASS_HID_28a5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2150894592,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [434] = {
+ .class_hid = BNXT_ULP_CLASS_HID_582d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2150902784,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [435] = {
+ .class_hid = BNXT_ULP_CLASS_HID_05a1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4296281088,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [436] = {
+ .class_hid = BNXT_ULP_CLASS_HID_37a9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4296289280,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [437] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1485,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4298378240,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [438] = {
+ .class_hid = BNXT_ULP_CLASS_HID_458d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4298386432,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [439] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2ce1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6443764736,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [440] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5ee9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6443772928,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [441] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3ac5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6445861888,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [442] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6ccd,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6445870080,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [443] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0b11,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8591248384,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [444] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3d99,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8591256576,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [445] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1ab5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8593345536,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [446] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4b3d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8593353728,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [447] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1291,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 10738732032,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [448] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4419,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 10738740224,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [449] = {
+ .class_hid = BNXT_ULP_CLASS_HID_22b5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 10740829184,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [450] = {
+ .class_hid = BNXT_ULP_CLASS_HID_523d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 10740837376,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [451] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1fb1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 12886215680,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [452] = {
+ .class_hid = BNXT_ULP_CLASS_HID_31b9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 12886223872,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [453] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2e95,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 12888312832,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [454] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5f9d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 12888321024,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [455] = {
+ .class_hid = BNXT_ULP_CLASS_HID_26b1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 15033699328,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [456] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58b9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 15033707520,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [457] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3495,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 15035796480,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [458] = {
+ .class_hid = BNXT_ULP_CLASS_HID_669d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 15035804672,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ },
+ [459] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0e39,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 17181182976,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [460] = {
+ .class_hid = BNXT_ULP_CLASS_HID_20a1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 17181191168,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [461] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1dfd,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 17183280128,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [462] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4e65,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 17183288320,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [463] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16f9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 19328666624,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [464] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4661,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 19328674816,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [465] = {
+ .class_hid = BNXT_ULP_CLASS_HID_24bd,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 19330763776,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [466] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5625,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 19330771968,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [467] = {
+ .class_hid = BNXT_ULP_CLASS_HID_02b9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 21476150272,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [468] = {
+ .class_hid = BNXT_ULP_CLASS_HID_34a1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 21476158464,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [469] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11bd,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 21478247424,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [470] = {
+ .class_hid = BNXT_ULP_CLASS_HID_42a5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 21478255616,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [471] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2af9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 23623633920,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [472] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5ae1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 23623642112,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [473] = {
+ .class_hid = BNXT_ULP_CLASS_HID_38fd,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 23625731072,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [474] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6ae5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 23625739264,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [475] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0829,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 25771117568,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [476] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3ab1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 25771125760,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [477] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17ad,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 25773214720,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [478] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4835,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 25773222912,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [479] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10a9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 27918601216,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [480] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4031,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 27918609408,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [481] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3e2d,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 27920698368,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [482] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5035,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 27920706560,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [483] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1ca9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 30066084864,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [484] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4eb1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 30066093056,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [485] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2bad,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 30068182016,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [486] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5cb5,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 30068190208,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [487] = {
+ .class_hid = BNXT_ULP_CLASS_HID_24a9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 32213568512,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [488] = {
+ .class_hid = BNXT_ULP_CLASS_HID_54b1,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 32213576704,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [489] = {
+ .class_hid = BNXT_ULP_CLASS_HID_32ad,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 32215665664,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [490] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0ca9,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 32215673856,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ },
+ [491] = {
+ .class_hid = BNXT_ULP_CLASS_HID_7f35,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1313792,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ },
+ [492] = {
+ .class_hid = BNXT_ULP_CLASS_HID_34f1,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1321984,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ },
+ [493] = {
+ .class_hid = BNXT_ULP_CLASS_HID_179d,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 3410944,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ },
+ [494] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2615,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 3419136,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ },
+ [495] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0fb9,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2148797440,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [496] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5d31,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2148805632,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [497] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3fdd,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2150894592,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [498] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4f55,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2150902784,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [499] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12d9,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4296281088,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [500] = {
+ .class_hid = BNXT_ULP_CLASS_HID_20d1,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4296289280,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [501] = {
+ .class_hid = BNXT_ULP_CLASS_HID_03fd,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4298378240,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [502] = {
+ .class_hid = BNXT_ULP_CLASS_HID_52f5,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4298386432,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [503] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3b99,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6443764736,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [504] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4991,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6443772928,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [505] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2dbd,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6445861888,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [506] = {
+ .class_hid = BNXT_ULP_CLASS_HID_7bb5,
.class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6445870080,
+ .flow_pattern_id = 2,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_ICMP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [507] = {
+ .class_hid = BNXT_ULP_CLASS_HID_34c6,
+ .class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 4096,
.flow_pattern_id = 0,
@@ -6975,12 +10968,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [346] = {
+ [508] = {
.class_hid = BNXT_ULP_CLASS_HID_0c22,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 4100,
.flow_pattern_id = 0,
@@ -6990,13 +10983,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [347] = {
+ [509] = {
.class_hid = BNXT_ULP_CLASS_HID_1cbe,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 6144,
.flow_pattern_id = 0,
@@ -7006,13 +10999,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [348] = {
+ [510] = {
.class_hid = BNXT_ULP_CLASS_HID_179a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 6148,
.flow_pattern_id = 0,
@@ -7022,14 +11015,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [349] = {
+ [511] = {
.class_hid = BNXT_ULP_CLASS_HID_59be,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 16384,
.flow_pattern_id = 0,
@@ -7039,12 +11032,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [350] = {
+ [512] = {
.class_hid = BNXT_ULP_CLASS_HID_515a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 16388,
.flow_pattern_id = 0,
@@ -7054,13 +11047,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [351] = {
+ [513] = {
.class_hid = BNXT_ULP_CLASS_HID_1c72,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 24576,
.flow_pattern_id = 0,
@@ -7070,13 +11063,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [352] = {
+ [514] = {
.class_hid = BNXT_ULP_CLASS_HID_171e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 24580,
.flow_pattern_id = 0,
@@ -7086,14 +11079,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [353] = {
+ [515] = {
.class_hid = BNXT_ULP_CLASS_HID_19c8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32768,
.flow_pattern_id = 0,
@@ -7104,12 +11097,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [354] = {
+ [516] = {
.class_hid = BNXT_ULP_CLASS_HID_112c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32772,
.flow_pattern_id = 0,
@@ -7120,13 +11113,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [355] = {
+ [517] = {
.class_hid = BNXT_ULP_CLASS_HID_4d68,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32832,
.flow_pattern_id = 0,
@@ -7137,13 +11130,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [356] = {
+ [518] = {
.class_hid = BNXT_ULP_CLASS_HID_444c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32836,
.flow_pattern_id = 0,
@@ -7154,14 +11147,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [357] = {
+ [519] = {
.class_hid = BNXT_ULP_CLASS_HID_0e8c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49152,
.flow_pattern_id = 0,
@@ -7172,13 +11165,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [358] = {
+ [520] = {
.class_hid = BNXT_ULP_CLASS_HID_09e0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49156,
.flow_pattern_id = 0,
@@ -7189,14 +11182,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [359] = {
+ [521] = {
.class_hid = BNXT_ULP_CLASS_HID_1af0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49216,
.flow_pattern_id = 0,
@@ -7207,14 +11200,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [360] = {
+ [522] = {
.class_hid = BNXT_ULP_CLASS_HID_15d4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49220,
.flow_pattern_id = 0,
@@ -7225,15 +11218,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [361] = {
+ [523] = {
.class_hid = BNXT_ULP_CLASS_HID_1dd0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131072,
.flow_pattern_id = 0,
@@ -7244,12 +11237,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [362] = {
+ [524] = {
.class_hid = BNXT_ULP_CLASS_HID_14f4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131076,
.flow_pattern_id = 0,
@@ -7260,13 +11253,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [363] = {
+ [525] = {
.class_hid = BNXT_ULP_CLASS_HID_70b0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131136,
.flow_pattern_id = 0,
@@ -7277,13 +11270,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [364] = {
+ [526] = {
.class_hid = BNXT_ULP_CLASS_HID_4854,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131140,
.flow_pattern_id = 0,
@@ -7294,14 +11287,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [365] = {
+ [527] = {
.class_hid = BNXT_ULP_CLASS_HID_3dd4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196608,
.flow_pattern_id = 0,
@@ -7312,13 +11305,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [366] = {
+ [528] = {
.class_hid = BNXT_ULP_CLASS_HID_34f8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196612,
.flow_pattern_id = 0,
@@ -7329,14 +11322,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [367] = {
+ [529] = {
.class_hid = BNXT_ULP_CLASS_HID_09e8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196672,
.flow_pattern_id = 0,
@@ -7347,14 +11340,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [368] = {
+ [530] = {
.class_hid = BNXT_ULP_CLASS_HID_008c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196676,
.flow_pattern_id = 0,
@@ -7365,15 +11358,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [369] = {
+ [531] = {
.class_hid = BNXT_ULP_CLASS_HID_34e6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 4096,
.flow_pattern_id = 0,
@@ -7384,12 +11377,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [370] = {
+ [532] = {
.class_hid = BNXT_ULP_CLASS_HID_0c02,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 4100,
.flow_pattern_id = 0,
@@ -7400,13 +11393,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [371] = {
+ [533] = {
.class_hid = BNXT_ULP_CLASS_HID_1c9e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 6144,
.flow_pattern_id = 0,
@@ -7417,13 +11410,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [372] = {
+ [534] = {
.class_hid = BNXT_ULP_CLASS_HID_17ba,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 6148,
.flow_pattern_id = 0,
@@ -7434,14 +11427,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [373] = {
+ [535] = {
.class_hid = BNXT_ULP_CLASS_HID_429e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 12288,
.flow_pattern_id = 0,
@@ -7452,13 +11445,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [374] = {
+ [536] = {
.class_hid = BNXT_ULP_CLASS_HID_5dba,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 12292,
.flow_pattern_id = 0,
@@ -7469,14 +11462,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [375] = {
+ [537] = {
.class_hid = BNXT_ULP_CLASS_HID_2a16,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 14336,
.flow_pattern_id = 0,
@@ -7487,14 +11480,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [376] = {
+ [538] = {
.class_hid = BNXT_ULP_CLASS_HID_2532,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 14340,
.flow_pattern_id = 0,
@@ -7505,15 +11498,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [377] = {
+ [539] = {
.class_hid = BNXT_ULP_CLASS_HID_2da2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 20480,
.flow_pattern_id = 0,
@@ -7524,13 +11517,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [378] = {
+ [540] = {
.class_hid = BNXT_ULP_CLASS_HID_24fe,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 20484,
.flow_pattern_id = 0,
@@ -7541,14 +11534,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [379] = {
+ [541] = {
.class_hid = BNXT_ULP_CLASS_HID_355a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 22528,
.flow_pattern_id = 0,
@@ -7559,14 +11552,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [380] = {
+ [542] = {
.class_hid = BNXT_ULP_CLASS_HID_0c76,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 22532,
.flow_pattern_id = 0,
@@ -7577,15 +11570,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [381] = {
+ [543] = {
.class_hid = BNXT_ULP_CLASS_HID_13e6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 28672,
.flow_pattern_id = 0,
@@ -7596,14 +11589,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [382] = {
+ [544] = {
.class_hid = BNXT_ULP_CLASS_HID_7276,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 28676,
.flow_pattern_id = 0,
@@ -7614,15 +11607,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [383] = {
+ [545] = {
.class_hid = BNXT_ULP_CLASS_HID_42d2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 30720,
.flow_pattern_id = 0,
@@ -7633,15 +11626,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [384] = {
+ [546] = {
.class_hid = BNXT_ULP_CLASS_HID_5dee,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 30724,
.flow_pattern_id = 0,
@@ -7652,16 +11645,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [385] = {
+ [547] = {
.class_hid = BNXT_ULP_CLASS_HID_59de,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 16384,
.flow_pattern_id = 0,
@@ -7672,12 +11665,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [386] = {
+ [548] = {
.class_hid = BNXT_ULP_CLASS_HID_513a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 16388,
.flow_pattern_id = 0,
@@ -7688,13 +11681,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [387] = {
+ [549] = {
.class_hid = BNXT_ULP_CLASS_HID_1c12,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 24576,
.flow_pattern_id = 0,
@@ -7705,13 +11698,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [388] = {
+ [550] = {
.class_hid = BNXT_ULP_CLASS_HID_177e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 24580,
.flow_pattern_id = 0,
@@ -7722,14 +11715,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [389] = {
+ [551] = {
.class_hid = BNXT_ULP_CLASS_HID_0e92,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 49152,
.flow_pattern_id = 0,
@@ -7740,13 +11733,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [390] = {
+ [552] = {
.class_hid = BNXT_ULP_CLASS_HID_09fe,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 49156,
.flow_pattern_id = 0,
@@ -7757,14 +11750,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [391] = {
+ [553] = {
.class_hid = BNXT_ULP_CLASS_HID_5c1a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 57344,
.flow_pattern_id = 0,
@@ -7775,14 +11768,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [392] = {
+ [554] = {
.class_hid = BNXT_ULP_CLASS_HID_5746,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 57348,
.flow_pattern_id = 0,
@@ -7793,15 +11786,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [393] = {
+ [555] = {
.class_hid = BNXT_ULP_CLASS_HID_79da,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 81920,
.flow_pattern_id = 0,
@@ -7812,13 +11805,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [394] = {
+ [556] = {
.class_hid = BNXT_ULP_CLASS_HID_7106,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 81924,
.flow_pattern_id = 0,
@@ -7829,14 +11822,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [395] = {
+ [557] = {
.class_hid = BNXT_ULP_CLASS_HID_3c1e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 90112,
.flow_pattern_id = 0,
@@ -7847,14 +11840,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [396] = {
+ [558] = {
.class_hid = BNXT_ULP_CLASS_HID_377a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 90116,
.flow_pattern_id = 0,
@@ -7865,15 +11858,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [397] = {
+ [559] = {
.class_hid = BNXT_ULP_CLASS_HID_2e9e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 114688,
.flow_pattern_id = 0,
@@ -7884,14 +11877,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [398] = {
+ [560] = {
.class_hid = BNXT_ULP_CLASS_HID_29fa,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 114692,
.flow_pattern_id = 0,
@@ -7902,15 +11895,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [399] = {
+ [561] = {
.class_hid = BNXT_ULP_CLASS_HID_14d2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 122880,
.flow_pattern_id = 0,
@@ -7921,15 +11914,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [400] = {
+ [562] = {
.class_hid = BNXT_ULP_CLASS_HID_7742,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 122884,
.flow_pattern_id = 0,
@@ -7940,16 +11933,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [401] = {
+ [563] = {
.class_hid = BNXT_ULP_CLASS_HID_3706,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 4096,
.flow_pattern_id = 0,
@@ -7960,12 +11953,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [402] = {
+ [564] = {
.class_hid = BNXT_ULP_CLASS_HID_0fe2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 4100,
.flow_pattern_id = 0,
@@ -7976,13 +11969,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [403] = {
+ [565] = {
.class_hid = BNXT_ULP_CLASS_HID_1f7e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 6144,
.flow_pattern_id = 0,
@@ -7993,13 +11986,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [404] = {
+ [566] = {
.class_hid = BNXT_ULP_CLASS_HID_145a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 6148,
.flow_pattern_id = 0,
@@ -8010,14 +12003,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [405] = {
+ [567] = {
.class_hid = BNXT_ULP_CLASS_HID_417e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 12288,
.flow_pattern_id = 0,
@@ -8028,13 +12021,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [406] = {
+ [568] = {
.class_hid = BNXT_ULP_CLASS_HID_5e5a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 12292,
.flow_pattern_id = 0,
@@ -8045,14 +12038,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [407] = {
+ [569] = {
.class_hid = BNXT_ULP_CLASS_HID_29f6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 14336,
.flow_pattern_id = 0,
@@ -8063,14 +12056,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [408] = {
+ [570] = {
.class_hid = BNXT_ULP_CLASS_HID_26d2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 14340,
.flow_pattern_id = 0,
@@ -8081,15 +12074,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [409] = {
+ [571] = {
.class_hid = BNXT_ULP_CLASS_HID_2e42,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 20480,
.flow_pattern_id = 0,
@@ -8100,13 +12093,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [410] = {
+ [572] = {
.class_hid = BNXT_ULP_CLASS_HID_271e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 20484,
.flow_pattern_id = 0,
@@ -8117,14 +12110,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [411] = {
+ [573] = {
.class_hid = BNXT_ULP_CLASS_HID_36ba,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 22528,
.flow_pattern_id = 0,
@@ -8135,14 +12128,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [412] = {
+ [574] = {
.class_hid = BNXT_ULP_CLASS_HID_0f96,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 22532,
.flow_pattern_id = 0,
@@ -8153,15 +12146,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [413] = {
+ [575] = {
.class_hid = BNXT_ULP_CLASS_HID_1006,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 28672,
.flow_pattern_id = 0,
@@ -8172,14 +12165,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [414] = {
+ [576] = {
.class_hid = BNXT_ULP_CLASS_HID_7196,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 28676,
.flow_pattern_id = 0,
@@ -8190,15 +12183,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [415] = {
+ [577] = {
.class_hid = BNXT_ULP_CLASS_HID_4132,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 30720,
.flow_pattern_id = 0,
@@ -8209,15 +12202,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [416] = {
+ [578] = {
.class_hid = BNXT_ULP_CLASS_HID_5e0e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 30724,
.flow_pattern_id = 0,
@@ -8228,16 +12221,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [417] = {
+ [579] = {
.class_hid = BNXT_ULP_CLASS_HID_59fe,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 16384,
.flow_pattern_id = 0,
@@ -8248,12 +12241,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [418] = {
+ [580] = {
.class_hid = BNXT_ULP_CLASS_HID_511a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 16388,
.flow_pattern_id = 0,
@@ -8264,13 +12257,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [419] = {
+ [581] = {
.class_hid = BNXT_ULP_CLASS_HID_1c32,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 24576,
.flow_pattern_id = 0,
@@ -8281,13 +12274,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [420] = {
+ [582] = {
.class_hid = BNXT_ULP_CLASS_HID_175e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 24580,
.flow_pattern_id = 0,
@@ -8298,14 +12291,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [421] = {
+ [583] = {
.class_hid = BNXT_ULP_CLASS_HID_0eb2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 49152,
.flow_pattern_id = 0,
@@ -8316,13 +12309,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [422] = {
+ [584] = {
.class_hid = BNXT_ULP_CLASS_HID_09de,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 49156,
.flow_pattern_id = 0,
@@ -8333,14 +12326,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [423] = {
+ [585] = {
.class_hid = BNXT_ULP_CLASS_HID_5c3a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 57344,
.flow_pattern_id = 0,
@@ -8351,14 +12344,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [424] = {
+ [586] = {
.class_hid = BNXT_ULP_CLASS_HID_5766,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 57348,
.flow_pattern_id = 0,
@@ -8369,15 +12362,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [425] = {
+ [587] = {
.class_hid = BNXT_ULP_CLASS_HID_79fa,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 81920,
.flow_pattern_id = 0,
@@ -8388,13 +12381,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [426] = {
+ [588] = {
.class_hid = BNXT_ULP_CLASS_HID_7126,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 81924,
.flow_pattern_id = 0,
@@ -8405,14 +12398,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [427] = {
+ [589] = {
.class_hid = BNXT_ULP_CLASS_HID_3c3e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 90112,
.flow_pattern_id = 0,
@@ -8423,14 +12416,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [428] = {
+ [590] = {
.class_hid = BNXT_ULP_CLASS_HID_375a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 90116,
.flow_pattern_id = 0,
@@ -8441,15 +12434,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [429] = {
+ [591] = {
.class_hid = BNXT_ULP_CLASS_HID_2ebe,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 114688,
.flow_pattern_id = 0,
@@ -8460,14 +12453,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [430] = {
+ [592] = {
.class_hid = BNXT_ULP_CLASS_HID_29da,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 114692,
.flow_pattern_id = 0,
@@ -8478,15 +12471,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [431] = {
+ [593] = {
.class_hid = BNXT_ULP_CLASS_HID_14f2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 122880,
.flow_pattern_id = 0,
@@ -8497,15 +12490,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [432] = {
+ [594] = {
.class_hid = BNXT_ULP_CLASS_HID_7762,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 122884,
.flow_pattern_id = 0,
@@ -8516,16 +12509,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [433] = {
+ [595] = {
.class_hid = BNXT_ULP_CLASS_HID_19e8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32768,
.flow_pattern_id = 0,
@@ -8537,12 +12530,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [434] = {
+ [596] = {
.class_hid = BNXT_ULP_CLASS_HID_110c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32772,
.flow_pattern_id = 0,
@@ -8554,13 +12547,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [435] = {
+ [597] = {
.class_hid = BNXT_ULP_CLASS_HID_4d48,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32832,
.flow_pattern_id = 0,
@@ -8572,13 +12565,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [436] = {
+ [598] = {
.class_hid = BNXT_ULP_CLASS_HID_446c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32836,
.flow_pattern_id = 0,
@@ -8590,14 +12583,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [437] = {
+ [599] = {
.class_hid = BNXT_ULP_CLASS_HID_0eac,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49152,
.flow_pattern_id = 0,
@@ -8609,13 +12602,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [438] = {
+ [600] = {
.class_hid = BNXT_ULP_CLASS_HID_09c0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49156,
.flow_pattern_id = 0,
@@ -8627,14 +12620,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [439] = {
+ [601] = {
.class_hid = BNXT_ULP_CLASS_HID_1ad0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49216,
.flow_pattern_id = 0,
@@ -8646,14 +12639,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [440] = {
+ [602] = {
.class_hid = BNXT_ULP_CLASS_HID_15f4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49220,
.flow_pattern_id = 0,
@@ -8665,15 +12658,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [441] = {
+ [603] = {
.class_hid = BNXT_ULP_CLASS_HID_39ec,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98304,
.flow_pattern_id = 0,
@@ -8685,13 +12678,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [442] = {
+ [604] = {
.class_hid = BNXT_ULP_CLASS_HID_3100,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98308,
.flow_pattern_id = 0,
@@ -8703,14 +12696,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [443] = {
+ [605] = {
.class_hid = BNXT_ULP_CLASS_HID_0210,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98368,
.flow_pattern_id = 0,
@@ -8722,14 +12715,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [444] = {
+ [606] = {
.class_hid = BNXT_ULP_CLASS_HID_1d34,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98372,
.flow_pattern_id = 0,
@@ -8741,15 +12734,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [445] = {
+ [607] = {
.class_hid = BNXT_ULP_CLASS_HID_2ea0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114688,
.flow_pattern_id = 0,
@@ -8761,14 +12754,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [446] = {
+ [608] = {
.class_hid = BNXT_ULP_CLASS_HID_29c4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114692,
.flow_pattern_id = 0,
@@ -8780,15 +12773,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [447] = {
+ [609] = {
.class_hid = BNXT_ULP_CLASS_HID_3ad4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114752,
.flow_pattern_id = 0,
@@ -8800,15 +12793,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [448] = {
+ [610] = {
.class_hid = BNXT_ULP_CLASS_HID_35e8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114756,
.flow_pattern_id = 0,
@@ -8820,16 +12813,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [449] = {
+ [611] = {
.class_hid = BNXT_ULP_CLASS_HID_5d80,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163840,
.flow_pattern_id = 0,
@@ -8841,13 +12834,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [450] = {
+ [612] = {
.class_hid = BNXT_ULP_CLASS_HID_54a4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163844,
.flow_pattern_id = 0,
@@ -8859,14 +12852,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [451] = {
+ [613] = {
.class_hid = BNXT_ULP_CLASS_HID_29b4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163904,
.flow_pattern_id = 0,
@@ -8878,14 +12871,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [452] = {
+ [614] = {
.class_hid = BNXT_ULP_CLASS_HID_20c8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163908,
.flow_pattern_id = 0,
@@ -8897,15 +12890,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [453] = {
+ [615] = {
.class_hid = BNXT_ULP_CLASS_HID_7244,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180224,
.flow_pattern_id = 0,
@@ -8917,14 +12910,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [454] = {
+ [616] = {
.class_hid = BNXT_ULP_CLASS_HID_4d98,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180228,
.flow_pattern_id = 0,
@@ -8936,15 +12929,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [455] = {
+ [617] = {
.class_hid = BNXT_ULP_CLASS_HID_5e68,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180288,
.flow_pattern_id = 0,
@@ -8956,15 +12949,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [456] = {
+ [618] = {
.class_hid = BNXT_ULP_CLASS_HID_598c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180292,
.flow_pattern_id = 0,
@@ -8976,16 +12969,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [457] = {
+ [619] = {
.class_hid = BNXT_ULP_CLASS_HID_1248,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229376,
.flow_pattern_id = 0,
@@ -8997,14 +12990,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [458] = {
+ [620] = {
.class_hid = BNXT_ULP_CLASS_HID_74d8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229380,
.flow_pattern_id = 0,
@@ -9016,15 +13009,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [459] = {
+ [621] = {
.class_hid = BNXT_ULP_CLASS_HID_49a8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229440,
.flow_pattern_id = 0,
@@ -9036,15 +13029,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [460] = {
+ [622] = {
.class_hid = BNXT_ULP_CLASS_HID_40cc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229444,
.flow_pattern_id = 0,
@@ -9056,16 +13049,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [461] = {
+ [623] = {
.class_hid = BNXT_ULP_CLASS_HID_0b0c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245760,
.flow_pattern_id = 0,
@@ -9077,15 +13070,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [462] = {
+ [624] = {
.class_hid = BNXT_ULP_CLASS_HID_0220,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245764,
.flow_pattern_id = 0,
@@ -9097,16 +13090,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [463] = {
+ [625] = {
.class_hid = BNXT_ULP_CLASS_HID_1730,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245824,
.flow_pattern_id = 0,
@@ -9118,16 +13111,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [464] = {
+ [626] = {
.class_hid = BNXT_ULP_CLASS_HID_7980,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245828,
.flow_pattern_id = 0,
@@ -9139,17 +13132,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [465] = {
+ [627] = {
.class_hid = BNXT_ULP_CLASS_HID_1db0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131072,
.flow_pattern_id = 0,
@@ -9161,12 +13154,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [466] = {
+ [628] = {
.class_hid = BNXT_ULP_CLASS_HID_1494,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131076,
.flow_pattern_id = 0,
@@ -9178,13 +13171,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [467] = {
+ [629] = {
.class_hid = BNXT_ULP_CLASS_HID_70d0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131136,
.flow_pattern_id = 0,
@@ -9196,13 +13189,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [468] = {
+ [630] = {
.class_hid = BNXT_ULP_CLASS_HID_4834,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131140,
.flow_pattern_id = 0,
@@ -9214,14 +13207,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [469] = {
+ [631] = {
.class_hid = BNXT_ULP_CLASS_HID_3db4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196608,
.flow_pattern_id = 0,
@@ -9233,13 +13226,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [470] = {
+ [632] = {
.class_hid = BNXT_ULP_CLASS_HID_3498,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196612,
.flow_pattern_id = 0,
@@ -9251,14 +13244,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [471] = {
+ [633] = {
.class_hid = BNXT_ULP_CLASS_HID_0988,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196672,
.flow_pattern_id = 0,
@@ -9270,14 +13263,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [472] = {
+ [634] = {
.class_hid = BNXT_ULP_CLASS_HID_00ec,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196676,
.flow_pattern_id = 0,
@@ -9289,15 +13282,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [473] = {
+ [635] = {
.class_hid = BNXT_ULP_CLASS_HID_3f44,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393216,
.flow_pattern_id = 0,
@@ -9309,13 +13302,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [474] = {
+ [636] = {
.class_hid = BNXT_ULP_CLASS_HID_36a8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393220,
.flow_pattern_id = 0,
@@ -9327,14 +13320,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [475] = {
+ [637] = {
.class_hid = BNXT_ULP_CLASS_HID_0b58,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393280,
.flow_pattern_id = 0,
@@ -9346,14 +13339,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [476] = {
+ [638] = {
.class_hid = BNXT_ULP_CLASS_HID_02bc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393284,
.flow_pattern_id = 0,
@@ -9365,15 +13358,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [477] = {
+ [639] = {
.class_hid = BNXT_ULP_CLASS_HID_5f48,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458752,
.flow_pattern_id = 0,
@@ -9385,14 +13378,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [478] = {
+ [640] = {
.class_hid = BNXT_ULP_CLASS_HID_56ac,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458756,
.flow_pattern_id = 0,
@@ -9404,15 +13397,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [479] = {
+ [641] = {
.class_hid = BNXT_ULP_CLASS_HID_2b5c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458816,
.flow_pattern_id = 0,
@@ -9424,15 +13417,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [480] = {
+ [642] = {
.class_hid = BNXT_ULP_CLASS_HID_2280,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458820,
.flow_pattern_id = 0,
@@ -9444,16 +13437,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [481] = {
+ [643] = {
.class_hid = BNXT_ULP_CLASS_HID_4000,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655360,
.flow_pattern_id = 0,
@@ -9465,13 +13458,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [482] = {
+ [644] = {
.class_hid = BNXT_ULP_CLASS_HID_5b64,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655364,
.flow_pattern_id = 0,
@@ -9483,14 +13476,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [483] = {
+ [645] = {
.class_hid = BNXT_ULP_CLASS_HID_2c14,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655424,
.flow_pattern_id = 0,
@@ -9502,14 +13495,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [484] = {
+ [646] = {
.class_hid = BNXT_ULP_CLASS_HID_2778,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655428,
.flow_pattern_id = 0,
@@ -9521,15 +13514,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [485] = {
+ [647] = {
.class_hid = BNXT_ULP_CLASS_HID_18f8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720896,
.flow_pattern_id = 0,
@@ -9541,14 +13534,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [486] = {
+ [648] = {
.class_hid = BNXT_ULP_CLASS_HID_13dc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720900,
.flow_pattern_id = 0,
@@ -9560,15 +13553,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [487] = {
+ [649] = {
.class_hid = BNXT_ULP_CLASS_HID_4c18,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720960,
.flow_pattern_id = 0,
@@ -9580,15 +13573,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [488] = {
+ [650] = {
.class_hid = BNXT_ULP_CLASS_HID_477c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720964,
.flow_pattern_id = 0,
@@ -9600,16 +13593,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [489] = {
+ [651] = {
.class_hid = BNXT_ULP_CLASS_HID_1a88,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917504,
.flow_pattern_id = 0,
@@ -9621,14 +13614,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [490] = {
+ [652] = {
.class_hid = BNXT_ULP_CLASS_HID_15ec,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917508,
.flow_pattern_id = 0,
@@ -9640,15 +13633,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [491] = {
+ [653] = {
.class_hid = BNXT_ULP_CLASS_HID_4e28,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917568,
.flow_pattern_id = 0,
@@ -9660,15 +13653,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [492] = {
+ [654] = {
.class_hid = BNXT_ULP_CLASS_HID_490c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917572,
.flow_pattern_id = 0,
@@ -9680,16 +13673,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [493] = {
+ [655] = {
.class_hid = BNXT_ULP_CLASS_HID_3a8c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983040,
.flow_pattern_id = 0,
@@ -9701,15 +13694,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [494] = {
+ [656] = {
.class_hid = BNXT_ULP_CLASS_HID_35f0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983044,
.flow_pattern_id = 0,
@@ -9721,16 +13714,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [495] = {
+ [657] = {
.class_hid = BNXT_ULP_CLASS_HID_06e0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983104,
.flow_pattern_id = 0,
@@ -9742,16 +13735,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [496] = {
+ [658] = {
.class_hid = BNXT_ULP_CLASS_HID_01c4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983108,
.flow_pattern_id = 0,
@@ -9763,17 +13756,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [497] = {
+ [659] = {
.class_hid = BNXT_ULP_CLASS_HID_1a08,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32768,
.flow_pattern_id = 0,
@@ -9785,12 +13778,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [498] = {
+ [660] = {
.class_hid = BNXT_ULP_CLASS_HID_12ec,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32772,
.flow_pattern_id = 0,
@@ -9802,13 +13795,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [499] = {
+ [661] = {
.class_hid = BNXT_ULP_CLASS_HID_4ea8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32832,
.flow_pattern_id = 0,
@@ -9820,13 +13813,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [500] = {
+ [662] = {
.class_hid = BNXT_ULP_CLASS_HID_478c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32836,
.flow_pattern_id = 0,
@@ -9838,14 +13831,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [501] = {
+ [663] = {
.class_hid = BNXT_ULP_CLASS_HID_0d4c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49152,
.flow_pattern_id = 0,
@@ -9857,13 +13850,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [502] = {
+ [664] = {
.class_hid = BNXT_ULP_CLASS_HID_0a20,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49156,
.flow_pattern_id = 0,
@@ -9875,14 +13868,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [503] = {
+ [665] = {
.class_hid = BNXT_ULP_CLASS_HID_1930,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49216,
.flow_pattern_id = 0,
@@ -9894,14 +13887,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [504] = {
+ [666] = {
.class_hid = BNXT_ULP_CLASS_HID_1614,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49220,
.flow_pattern_id = 0,
@@ -9913,15 +13906,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [505] = {
+ [667] = {
.class_hid = BNXT_ULP_CLASS_HID_3a0c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98304,
.flow_pattern_id = 0,
@@ -9933,13 +13926,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [506] = {
+ [668] = {
.class_hid = BNXT_ULP_CLASS_HID_32e0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98308,
.flow_pattern_id = 0,
@@ -9951,14 +13944,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [507] = {
+ [669] = {
.class_hid = BNXT_ULP_CLASS_HID_01f0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98368,
.flow_pattern_id = 0,
@@ -9970,14 +13963,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [508] = {
+ [670] = {
.class_hid = BNXT_ULP_CLASS_HID_1ed4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98372,
.flow_pattern_id = 0,
@@ -9989,15 +13982,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [509] = {
+ [671] = {
.class_hid = BNXT_ULP_CLASS_HID_2d40,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114688,
.flow_pattern_id = 0,
@@ -10009,14 +14002,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [510] = {
+ [672] = {
.class_hid = BNXT_ULP_CLASS_HID_2a24,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114692,
.flow_pattern_id = 0,
@@ -10028,15 +14021,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [511] = {
+ [673] = {
.class_hid = BNXT_ULP_CLASS_HID_3934,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114752,
.flow_pattern_id = 0,
@@ -10048,15 +14041,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [512] = {
+ [674] = {
.class_hid = BNXT_ULP_CLASS_HID_3608,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114756,
.flow_pattern_id = 0,
@@ -10068,16 +14061,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [513] = {
+ [675] = {
.class_hid = BNXT_ULP_CLASS_HID_5e60,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163840,
.flow_pattern_id = 0,
@@ -10089,13 +14082,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [514] = {
+ [676] = {
.class_hid = BNXT_ULP_CLASS_HID_5744,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163844,
.flow_pattern_id = 0,
@@ -10107,14 +14100,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [515] = {
+ [677] = {
.class_hid = BNXT_ULP_CLASS_HID_2a54,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163904,
.flow_pattern_id = 0,
@@ -10126,14 +14119,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [516] = {
+ [678] = {
.class_hid = BNXT_ULP_CLASS_HID_2328,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163908,
.flow_pattern_id = 0,
@@ -10145,15 +14138,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [517] = {
+ [679] = {
.class_hid = BNXT_ULP_CLASS_HID_71a4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180224,
.flow_pattern_id = 0,
@@ -10165,14 +14158,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [518] = {
+ [680] = {
.class_hid = BNXT_ULP_CLASS_HID_4e78,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180228,
.flow_pattern_id = 0,
@@ -10184,15 +14177,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [519] = {
+ [681] = {
.class_hid = BNXT_ULP_CLASS_HID_5d88,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180288,
.flow_pattern_id = 0,
@@ -10204,15 +14197,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [520] = {
+ [682] = {
.class_hid = BNXT_ULP_CLASS_HID_5a6c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180292,
.flow_pattern_id = 0,
@@ -10224,16 +14217,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [521] = {
+ [683] = {
.class_hid = BNXT_ULP_CLASS_HID_11a8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229376,
.flow_pattern_id = 0,
@@ -10245,14 +14238,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [522] = {
+ [684] = {
.class_hid = BNXT_ULP_CLASS_HID_7738,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229380,
.flow_pattern_id = 0,
@@ -10264,15 +14257,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [523] = {
+ [685] = {
.class_hid = BNXT_ULP_CLASS_HID_4a48,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229440,
.flow_pattern_id = 0,
@@ -10284,15 +14277,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [524] = {
+ [686] = {
.class_hid = BNXT_ULP_CLASS_HID_432c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229444,
.flow_pattern_id = 0,
@@ -10304,16 +14297,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [525] = {
+ [687] = {
.class_hid = BNXT_ULP_CLASS_HID_08ec,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245760,
.flow_pattern_id = 0,
@@ -10325,15 +14318,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [526] = {
+ [688] = {
.class_hid = BNXT_ULP_CLASS_HID_01c0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245764,
.flow_pattern_id = 0,
@@ -10345,16 +14338,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [527] = {
+ [689] = {
.class_hid = BNXT_ULP_CLASS_HID_14d0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245824,
.flow_pattern_id = 0,
@@ -10366,16 +14359,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [528] = {
+ [690] = {
.class_hid = BNXT_ULP_CLASS_HID_7a60,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245828,
.flow_pattern_id = 0,
@@ -10387,17 +14380,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [529] = {
+ [691] = {
.class_hid = BNXT_ULP_CLASS_HID_1d90,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131072,
.flow_pattern_id = 0,
@@ -10409,12 +14402,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [530] = {
+ [692] = {
.class_hid = BNXT_ULP_CLASS_HID_14b4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131076,
.flow_pattern_id = 0,
@@ -10426,13 +14419,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [531] = {
+ [693] = {
.class_hid = BNXT_ULP_CLASS_HID_70f0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131136,
.flow_pattern_id = 0,
@@ -10444,13 +14437,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [532] = {
+ [694] = {
.class_hid = BNXT_ULP_CLASS_HID_4814,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131140,
.flow_pattern_id = 0,
@@ -10462,14 +14455,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [533] = {
+ [695] = {
.class_hid = BNXT_ULP_CLASS_HID_3d94,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196608,
.flow_pattern_id = 0,
@@ -10481,13 +14474,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [534] = {
+ [696] = {
.class_hid = BNXT_ULP_CLASS_HID_34b8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196612,
.flow_pattern_id = 0,
@@ -10499,14 +14492,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [535] = {
+ [697] = {
.class_hid = BNXT_ULP_CLASS_HID_09a8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196672,
.flow_pattern_id = 0,
@@ -10518,14 +14511,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [536] = {
+ [698] = {
.class_hid = BNXT_ULP_CLASS_HID_00cc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196676,
.flow_pattern_id = 0,
@@ -10537,15 +14530,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [537] = {
+ [699] = {
.class_hid = BNXT_ULP_CLASS_HID_3f64,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393216,
.flow_pattern_id = 0,
@@ -10557,13 +14550,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [538] = {
+ [700] = {
.class_hid = BNXT_ULP_CLASS_HID_3688,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393220,
.flow_pattern_id = 0,
@@ -10575,14 +14568,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [539] = {
+ [701] = {
.class_hid = BNXT_ULP_CLASS_HID_0b78,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393280,
.flow_pattern_id = 0,
@@ -10594,14 +14587,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [540] = {
+ [702] = {
.class_hid = BNXT_ULP_CLASS_HID_029c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393284,
.flow_pattern_id = 0,
@@ -10613,15 +14606,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [541] = {
+ [703] = {
.class_hid = BNXT_ULP_CLASS_HID_5f68,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458752,
.flow_pattern_id = 0,
@@ -10633,14 +14626,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [542] = {
+ [704] = {
.class_hid = BNXT_ULP_CLASS_HID_568c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458756,
.flow_pattern_id = 0,
@@ -10652,15 +14645,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [543] = {
+ [705] = {
.class_hid = BNXT_ULP_CLASS_HID_2b7c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458816,
.flow_pattern_id = 0,
@@ -10672,15 +14665,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [544] = {
+ [706] = {
.class_hid = BNXT_ULP_CLASS_HID_22a0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458820,
.flow_pattern_id = 0,
@@ -10692,16 +14685,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [545] = {
+ [707] = {
.class_hid = BNXT_ULP_CLASS_HID_4020,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655360,
.flow_pattern_id = 0,
@@ -10713,13 +14706,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [546] = {
+ [708] = {
.class_hid = BNXT_ULP_CLASS_HID_5b44,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655364,
.flow_pattern_id = 0,
@@ -10731,14 +14724,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [547] = {
+ [709] = {
.class_hid = BNXT_ULP_CLASS_HID_2c34,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655424,
.flow_pattern_id = 0,
@@ -10750,14 +14743,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [548] = {
+ [710] = {
.class_hid = BNXT_ULP_CLASS_HID_2758,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655428,
.flow_pattern_id = 0,
@@ -10769,15 +14762,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [549] = {
+ [711] = {
.class_hid = BNXT_ULP_CLASS_HID_18d8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720896,
.flow_pattern_id = 0,
@@ -10789,14 +14782,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [550] = {
+ [712] = {
.class_hid = BNXT_ULP_CLASS_HID_13fc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720900,
.flow_pattern_id = 0,
@@ -10808,15 +14801,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [551] = {
+ [713] = {
.class_hid = BNXT_ULP_CLASS_HID_4c38,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720960,
.flow_pattern_id = 0,
@@ -10828,15 +14821,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [552] = {
+ [714] = {
.class_hid = BNXT_ULP_CLASS_HID_475c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720964,
.flow_pattern_id = 0,
@@ -10848,16 +14841,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [553] = {
+ [715] = {
.class_hid = BNXT_ULP_CLASS_HID_1aa8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917504,
.flow_pattern_id = 0,
@@ -10869,14 +14862,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [554] = {
+ [716] = {
.class_hid = BNXT_ULP_CLASS_HID_15cc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917508,
.flow_pattern_id = 0,
@@ -10888,15 +14881,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [555] = {
+ [717] = {
.class_hid = BNXT_ULP_CLASS_HID_4e08,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917568,
.flow_pattern_id = 0,
@@ -10908,15 +14901,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [556] = {
+ [718] = {
.class_hid = BNXT_ULP_CLASS_HID_492c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917572,
.flow_pattern_id = 0,
@@ -10928,16 +14921,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [557] = {
+ [719] = {
.class_hid = BNXT_ULP_CLASS_HID_3aac,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983040,
.flow_pattern_id = 0,
@@ -10949,15 +14942,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [558] = {
+ [720] = {
.class_hid = BNXT_ULP_CLASS_HID_35d0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983044,
.flow_pattern_id = 0,
@@ -10969,16 +14962,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [559] = {
+ [721] = {
.class_hid = BNXT_ULP_CLASS_HID_06c0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983104,
.flow_pattern_id = 0,
@@ -10990,16 +14983,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [560] = {
+ [722] = {
.class_hid = BNXT_ULP_CLASS_HID_01e4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983108,
.flow_pattern_id = 0,
@@ -11011,17 +15004,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [561] = {
+ [723] = {
.class_hid = BNXT_ULP_CLASS_HID_4d32,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 4096,
.flow_pattern_id = 1,
@@ -11031,11 +15024,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [562] = {
+ [724] = {
.class_hid = BNXT_ULP_CLASS_HID_54aa,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 6144,
.flow_pattern_id = 1,
@@ -11045,12 +15038,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [563] = {
+ [725] = {
.class_hid = BNXT_ULP_CLASS_HID_0686,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 16384,
.flow_pattern_id = 1,
@@ -11060,11 +15053,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [564] = {
+ [726] = {
.class_hid = BNXT_ULP_CLASS_HID_540e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 24576,
.flow_pattern_id = 1,
@@ -11074,12 +15067,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [565] = {
+ [727] = {
.class_hid = BNXT_ULP_CLASS_HID_2e3c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32768,
.flow_pattern_id = 1,
@@ -11090,11 +15083,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [566] = {
+ [728] = {
.class_hid = BNXT_ULP_CLASS_HID_3a20,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32832,
.flow_pattern_id = 1,
@@ -11105,12 +15098,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [567] = {
+ [729] = {
.class_hid = BNXT_ULP_CLASS_HID_46f0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49152,
.flow_pattern_id = 1,
@@ -11121,12 +15114,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [568] = {
+ [730] = {
.class_hid = BNXT_ULP_CLASS_HID_52e4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49216,
.flow_pattern_id = 1,
@@ -11137,13 +15130,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [569] = {
+ [731] = {
.class_hid = BNXT_ULP_CLASS_HID_55e4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131072,
.flow_pattern_id = 1,
@@ -11154,11 +15147,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [570] = {
+ [732] = {
.class_hid = BNXT_ULP_CLASS_HID_21f8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131136,
.flow_pattern_id = 1,
@@ -11169,12 +15162,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [571] = {
+ [733] = {
.class_hid = BNXT_ULP_CLASS_HID_75e8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196608,
.flow_pattern_id = 1,
@@ -11185,12 +15178,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [572] = {
+ [734] = {
.class_hid = BNXT_ULP_CLASS_HID_41fc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196672,
.flow_pattern_id = 1,
@@ -11201,13 +15194,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [573] = {
+ [735] = {
.class_hid = BNXT_ULP_CLASS_HID_4d12,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 4096,
.flow_pattern_id = 1,
@@ -11218,11 +15211,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [574] = {
+ [736] = {
.class_hid = BNXT_ULP_CLASS_HID_548a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 6144,
.flow_pattern_id = 1,
@@ -11233,12 +15226,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [575] = {
+ [737] = {
.class_hid = BNXT_ULP_CLASS_HID_3356,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 12288,
.flow_pattern_id = 1,
@@ -11249,12 +15242,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [576] = {
+ [738] = {
.class_hid = BNXT_ULP_CLASS_HID_1ace,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 14336,
.flow_pattern_id = 1,
@@ -11265,13 +15258,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [577] = {
+ [739] = {
.class_hid = BNXT_ULP_CLASS_HID_1a9a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 20480,
.flow_pattern_id = 1,
@@ -11282,12 +15275,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [578] = {
+ [740] = {
.class_hid = BNXT_ULP_CLASS_HID_4d46,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 22528,
.flow_pattern_id = 1,
@@ -11298,13 +15291,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [579] = {
+ [741] = {
.class_hid = BNXT_ULP_CLASS_HID_2812,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 28672,
.flow_pattern_id = 1,
@@ -11315,13 +15308,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [580] = {
+ [742] = {
.class_hid = BNXT_ULP_CLASS_HID_338a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 30720,
.flow_pattern_id = 1,
@@ -11332,14 +15325,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [581] = {
+ [743] = {
.class_hid = BNXT_ULP_CLASS_HID_06e6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 16384,
.flow_pattern_id = 1,
@@ -11350,11 +15343,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [582] = {
+ [744] = {
.class_hid = BNXT_ULP_CLASS_HID_546e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 24576,
.flow_pattern_id = 1,
@@ -11365,12 +15358,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [583] = {
+ [745] = {
.class_hid = BNXT_ULP_CLASS_HID_46ee,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 49152,
.flow_pattern_id = 1,
@@ -11381,12 +15374,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [584] = {
+ [746] = {
.class_hid = BNXT_ULP_CLASS_HID_0d22,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 57344,
.flow_pattern_id = 1,
@@ -11397,13 +15390,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [585] = {
+ [747] = {
.class_hid = BNXT_ULP_CLASS_HID_26e2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 81920,
.flow_pattern_id = 1,
@@ -11414,12 +15407,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [586] = {
+ [748] = {
.class_hid = BNXT_ULP_CLASS_HID_746a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 90112,
.flow_pattern_id = 1,
@@ -11430,13 +15423,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [587] = {
+ [749] = {
.class_hid = BNXT_ULP_CLASS_HID_1fa6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 114688,
.flow_pattern_id = 1,
@@ -11447,13 +15440,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [588] = {
+ [750] = {
.class_hid = BNXT_ULP_CLASS_HID_2d2e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 122880,
.flow_pattern_id = 1,
@@ -11464,14 +15457,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [589] = {
+ [751] = {
.class_hid = BNXT_ULP_CLASS_HID_4ef2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 4096,
.flow_pattern_id = 1,
@@ -11482,11 +15475,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [590] = {
+ [752] = {
.class_hid = BNXT_ULP_CLASS_HID_576a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 6144,
.flow_pattern_id = 1,
@@ -11497,12 +15490,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [591] = {
+ [753] = {
.class_hid = BNXT_ULP_CLASS_HID_30b6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 12288,
.flow_pattern_id = 1,
@@ -11513,12 +15506,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [592] = {
+ [754] = {
.class_hid = BNXT_ULP_CLASS_HID_192e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 14336,
.flow_pattern_id = 1,
@@ -11529,13 +15522,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [593] = {
+ [755] = {
.class_hid = BNXT_ULP_CLASS_HID_197a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 20480,
.flow_pattern_id = 1,
@@ -11546,12 +15539,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [594] = {
+ [756] = {
.class_hid = BNXT_ULP_CLASS_HID_4ea6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 22528,
.flow_pattern_id = 1,
@@ -11562,13 +15555,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [595] = {
+ [757] = {
.class_hid = BNXT_ULP_CLASS_HID_2bf2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 28672,
.flow_pattern_id = 1,
@@ -11579,13 +15572,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [596] = {
+ [758] = {
.class_hid = BNXT_ULP_CLASS_HID_306a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 30720,
.flow_pattern_id = 1,
@@ -11596,14 +15589,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [597] = {
+ [759] = {
.class_hid = BNXT_ULP_CLASS_HID_06c6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 16384,
.flow_pattern_id = 1,
@@ -11614,11 +15607,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [598] = {
+ [760] = {
.class_hid = BNXT_ULP_CLASS_HID_544e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 24576,
.flow_pattern_id = 1,
@@ -11629,12 +15622,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [599] = {
+ [761] = {
.class_hid = BNXT_ULP_CLASS_HID_46ce,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 49152,
.flow_pattern_id = 1,
@@ -11645,12 +15638,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [600] = {
+ [762] = {
.class_hid = BNXT_ULP_CLASS_HID_0d02,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 57344,
.flow_pattern_id = 1,
@@ -11661,13 +15654,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [601] = {
+ [763] = {
.class_hid = BNXT_ULP_CLASS_HID_26c2,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 81920,
.flow_pattern_id = 1,
@@ -11678,12 +15671,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [602] = {
+ [764] = {
.class_hid = BNXT_ULP_CLASS_HID_744a,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 90112,
.flow_pattern_id = 1,
@@ -11694,13 +15687,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [603] = {
+ [765] = {
.class_hid = BNXT_ULP_CLASS_HID_1f86,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 114688,
.flow_pattern_id = 1,
@@ -11711,13 +15704,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [604] = {
+ [766] = {
.class_hid = BNXT_ULP_CLASS_HID_2d0e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 122880,
.flow_pattern_id = 1,
@@ -11728,14 +15721,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [605] = {
+ [767] = {
.class_hid = BNXT_ULP_CLASS_HID_2e1c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32768,
.flow_pattern_id = 1,
@@ -11747,11 +15740,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [606] = {
+ [768] = {
.class_hid = BNXT_ULP_CLASS_HID_3a00,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32832,
.flow_pattern_id = 1,
@@ -11763,12 +15756,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [607] = {
+ [769] = {
.class_hid = BNXT_ULP_CLASS_HID_46d0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49152,
.flow_pattern_id = 1,
@@ -11780,12 +15773,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [608] = {
+ [770] = {
.class_hid = BNXT_ULP_CLASS_HID_52c4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49216,
.flow_pattern_id = 1,
@@ -11797,13 +15790,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [609] = {
+ [771] = {
.class_hid = BNXT_ULP_CLASS_HID_4e10,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98304,
.flow_pattern_id = 1,
@@ -11815,12 +15808,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [610] = {
+ [772] = {
.class_hid = BNXT_ULP_CLASS_HID_5a04,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98368,
.flow_pattern_id = 1,
@@ -11832,13 +15825,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [611] = {
+ [773] = {
.class_hid = BNXT_ULP_CLASS_HID_1f98,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114688,
.flow_pattern_id = 1,
@@ -11850,13 +15843,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [612] = {
+ [774] = {
.class_hid = BNXT_ULP_CLASS_HID_72f8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114752,
.flow_pattern_id = 1,
@@ -11868,14 +15861,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [613] = {
+ [775] = {
.class_hid = BNXT_ULP_CLASS_HID_0a78,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163840,
.flow_pattern_id = 1,
@@ -11887,12 +15880,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [614] = {
+ [776] = {
.class_hid = BNXT_ULP_CLASS_HID_166c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163904,
.flow_pattern_id = 1,
@@ -11904,13 +15897,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [615] = {
+ [777] = {
.class_hid = BNXT_ULP_CLASS_HID_233c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180224,
.flow_pattern_id = 1,
@@ -11922,13 +15915,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [616] = {
+ [778] = {
.class_hid = BNXT_ULP_CLASS_HID_0f20,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180288,
.flow_pattern_id = 1,
@@ -11940,14 +15933,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [617] = {
+ [779] = {
.class_hid = BNXT_ULP_CLASS_HID_2a7c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229376,
.flow_pattern_id = 1,
@@ -11959,13 +15952,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [618] = {
+ [780] = {
.class_hid = BNXT_ULP_CLASS_HID_3660,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229440,
.flow_pattern_id = 1,
@@ -11977,14 +15970,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [619] = {
+ [781] = {
.class_hid = BNXT_ULP_CLASS_HID_4330,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245760,
.flow_pattern_id = 1,
@@ -11996,14 +15989,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [620] = {
+ [782] = {
.class_hid = BNXT_ULP_CLASS_HID_2f24,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245824,
.flow_pattern_id = 1,
@@ -12015,15 +16008,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [621] = {
+ [783] = {
.class_hid = BNXT_ULP_CLASS_HID_5584,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131072,
.flow_pattern_id = 1,
@@ -12035,11 +16028,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [622] = {
+ [784] = {
.class_hid = BNXT_ULP_CLASS_HID_2198,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131136,
.flow_pattern_id = 1,
@@ -12051,12 +16044,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [623] = {
+ [785] = {
.class_hid = BNXT_ULP_CLASS_HID_7588,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196608,
.flow_pattern_id = 1,
@@ -12068,12 +16061,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [624] = {
+ [786] = {
.class_hid = BNXT_ULP_CLASS_HID_419c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196672,
.flow_pattern_id = 1,
@@ -12085,13 +16078,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [625] = {
+ [787] = {
.class_hid = BNXT_ULP_CLASS_HID_7758,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393216,
.flow_pattern_id = 1,
@@ -12103,12 +16096,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [626] = {
+ [788] = {
.class_hid = BNXT_ULP_CLASS_HID_43ac,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393280,
.flow_pattern_id = 1,
@@ -12120,13 +16113,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [627] = {
+ [789] = {
.class_hid = BNXT_ULP_CLASS_HID_0c10,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458752,
.flow_pattern_id = 1,
@@ -12138,13 +16131,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [628] = {
+ [790] = {
.class_hid = BNXT_ULP_CLASS_HID_1864,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458816,
.flow_pattern_id = 1,
@@ -12156,14 +16149,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [629] = {
+ [791] = {
.class_hid = BNXT_ULP_CLASS_HID_30c8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655360,
.flow_pattern_id = 1,
@@ -12175,12 +16168,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [630] = {
+ [792] = {
.class_hid = BNXT_ULP_CLASS_HID_1cdc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655424,
.flow_pattern_id = 1,
@@ -12192,13 +16185,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [631] = {
+ [793] = {
.class_hid = BNXT_ULP_CLASS_HID_50cc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720896,
.flow_pattern_id = 1,
@@ -12210,13 +16203,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [632] = {
+ [794] = {
.class_hid = BNXT_ULP_CLASS_HID_3d20,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720960,
.flow_pattern_id = 1,
@@ -12228,14 +16221,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [633] = {
+ [795] = {
.class_hid = BNXT_ULP_CLASS_HID_529c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917504,
.flow_pattern_id = 1,
@@ -12247,13 +16240,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [634] = {
+ [796] = {
.class_hid = BNXT_ULP_CLASS_HID_3ef0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917568,
.flow_pattern_id = 1,
@@ -12265,14 +16258,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [635] = {
+ [797] = {
.class_hid = BNXT_ULP_CLASS_HID_72e0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983040,
.flow_pattern_id = 1,
@@ -12284,14 +16277,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [636] = {
+ [798] = {
.class_hid = BNXT_ULP_CLASS_HID_5ef4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983104,
.flow_pattern_id = 1,
@@ -12303,15 +16296,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT }
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [637] = {
+ [799] = {
.class_hid = BNXT_ULP_CLASS_HID_2dfc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32768,
.flow_pattern_id = 1,
@@ -12323,11 +16316,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [638] = {
+ [800] = {
.class_hid = BNXT_ULP_CLASS_HID_39e0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32832,
.flow_pattern_id = 1,
@@ -12339,12 +16332,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [639] = {
+ [801] = {
.class_hid = BNXT_ULP_CLASS_HID_4530,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49152,
.flow_pattern_id = 1,
@@ -12356,12 +16349,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [640] = {
+ [802] = {
.class_hid = BNXT_ULP_CLASS_HID_5124,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49216,
.flow_pattern_id = 1,
@@ -12373,13 +16366,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [641] = {
+ [803] = {
.class_hid = BNXT_ULP_CLASS_HID_4df0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98304,
.flow_pattern_id = 1,
@@ -12391,12 +16384,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [642] = {
+ [804] = {
.class_hid = BNXT_ULP_CLASS_HID_59e4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98368,
.flow_pattern_id = 1,
@@ -12408,13 +16401,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [643] = {
+ [805] = {
.class_hid = BNXT_ULP_CLASS_HID_1c78,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114688,
.flow_pattern_id = 1,
@@ -12426,13 +16419,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [644] = {
+ [806] = {
.class_hid = BNXT_ULP_CLASS_HID_7118,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114752,
.flow_pattern_id = 1,
@@ -12444,14 +16437,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [645] = {
+ [807] = {
.class_hid = BNXT_ULP_CLASS_HID_0998,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163840,
.flow_pattern_id = 1,
@@ -12463,12 +16456,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [646] = {
+ [808] = {
.class_hid = BNXT_ULP_CLASS_HID_158c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163904,
.flow_pattern_id = 1,
@@ -12480,13 +16473,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [647] = {
+ [809] = {
.class_hid = BNXT_ULP_CLASS_HID_20dc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180224,
.flow_pattern_id = 1,
@@ -12498,13 +16491,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [648] = {
+ [810] = {
.class_hid = BNXT_ULP_CLASS_HID_0cc0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180288,
.flow_pattern_id = 1,
@@ -12516,14 +16509,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [649] = {
+ [811] = {
.class_hid = BNXT_ULP_CLASS_HID_299c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229376,
.flow_pattern_id = 1,
@@ -12535,13 +16528,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [650] = {
+ [812] = {
.class_hid = BNXT_ULP_CLASS_HID_3580,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229440,
.flow_pattern_id = 1,
@@ -12553,14 +16546,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [651] = {
+ [813] = {
.class_hid = BNXT_ULP_CLASS_HID_40d0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245760,
.flow_pattern_id = 1,
@@ -12572,14 +16565,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [652] = {
+ [814] = {
.class_hid = BNXT_ULP_CLASS_HID_2cc4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245824,
.flow_pattern_id = 1,
@@ -12591,15 +16584,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [653] = {
+ [815] = {
.class_hid = BNXT_ULP_CLASS_HID_55a4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131072,
.flow_pattern_id = 1,
@@ -12611,11 +16604,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [654] = {
+ [816] = {
.class_hid = BNXT_ULP_CLASS_HID_21b8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131136,
.flow_pattern_id = 1,
@@ -12627,12 +16620,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [655] = {
+ [817] = {
.class_hid = BNXT_ULP_CLASS_HID_75a8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196608,
.flow_pattern_id = 1,
@@ -12644,12 +16637,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [656] = {
+ [818] = {
.class_hid = BNXT_ULP_CLASS_HID_41bc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196672,
.flow_pattern_id = 1,
@@ -12661,13 +16654,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [657] = {
+ [819] = {
.class_hid = BNXT_ULP_CLASS_HID_7778,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393216,
.flow_pattern_id = 1,
@@ -12679,12 +16672,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [658] = {
+ [820] = {
.class_hid = BNXT_ULP_CLASS_HID_438c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393280,
.flow_pattern_id = 1,
@@ -12696,13 +16689,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [659] = {
+ [821] = {
.class_hid = BNXT_ULP_CLASS_HID_0c30,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458752,
.flow_pattern_id = 1,
@@ -12714,13 +16707,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [660] = {
+ [822] = {
.class_hid = BNXT_ULP_CLASS_HID_1844,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458816,
.flow_pattern_id = 1,
@@ -12732,14 +16725,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [661] = {
+ [823] = {
.class_hid = BNXT_ULP_CLASS_HID_30e8,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655360,
.flow_pattern_id = 1,
@@ -12751,12 +16744,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [662] = {
+ [824] = {
.class_hid = BNXT_ULP_CLASS_HID_1cfc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655424,
.flow_pattern_id = 1,
@@ -12768,13 +16761,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [663] = {
+ [825] = {
.class_hid = BNXT_ULP_CLASS_HID_50ec,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720896,
.flow_pattern_id = 1,
@@ -12786,13 +16779,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [664] = {
+ [826] = {
.class_hid = BNXT_ULP_CLASS_HID_3d00,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720960,
.flow_pattern_id = 1,
@@ -12804,14 +16797,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [665] = {
+ [827] = {
.class_hid = BNXT_ULP_CLASS_HID_52bc,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917504,
.flow_pattern_id = 1,
@@ -12823,13 +16816,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [666] = {
+ [828] = {
.class_hid = BNXT_ULP_CLASS_HID_3ed0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917568,
.flow_pattern_id = 1,
@@ -12841,14 +16834,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [667] = {
+ [829] = {
.class_hid = BNXT_ULP_CLASS_HID_72c0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983040,
.flow_pattern_id = 1,
@@ -12860,14 +16853,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [668] = {
+ [830] = {
.class_hid = BNXT_ULP_CLASS_HID_5ed4,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983104,
.flow_pattern_id = 1,
@@ -12879,15 +16872,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT }
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [669] = {
+ [831] = {
.class_hid = BNXT_ULP_CLASS_HID_3866,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -12897,12 +16890,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC }
},
- [670] = {
+ [832] = {
.class_hid = BNXT_ULP_CLASS_HID_381e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -12912,12 +16905,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC }
},
- [671] = {
+ [833] = {
.class_hid = BNXT_ULP_CLASS_HID_3860,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -12928,12 +16921,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC }
},
- [672] = {
+ [834] = {
.class_hid = BNXT_ULP_CLASS_HID_0454,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 68,
.flow_pattern_id = 2,
@@ -12944,13 +16937,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID }
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID }
},
- [673] = {
+ [835] = {
.class_hid = BNXT_ULP_CLASS_HID_3818,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -12961,12 +16954,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC }
},
- [674] = {
+ [836] = {
.class_hid = BNXT_ULP_CLASS_HID_042c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 68,
.flow_pattern_id = 2,
@@ -12977,13 +16970,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID }
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID }
},
- [675] = {
+ [837] = {
.class_hid = BNXT_ULP_CLASS_HID_3846,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -12994,12 +16987,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC }
},
- [676] = {
+ [838] = {
.class_hid = BNXT_ULP_CLASS_HID_387e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -13010,12 +17003,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC }
},
- [677] = {
+ [839] = {
.class_hid = BNXT_ULP_CLASS_HID_3ba6,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -13026,12 +17019,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC }
},
- [678] = {
+ [840] = {
.class_hid = BNXT_ULP_CLASS_HID_385e,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -13042,12 +17035,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC }
},
- [679] = {
+ [841] = {
.class_hid = BNXT_ULP_CLASS_HID_3840,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -13059,12 +17052,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC }
},
- [680] = {
+ [842] = {
.class_hid = BNXT_ULP_CLASS_HID_0474,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 68,
.flow_pattern_id = 2,
@@ -13076,13 +17069,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID }
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID }
},
- [681] = {
+ [843] = {
.class_hid = BNXT_ULP_CLASS_HID_3878,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -13094,12 +17087,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC }
},
- [682] = {
+ [844] = {
.class_hid = BNXT_ULP_CLASS_HID_044c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 68,
.flow_pattern_id = 2,
@@ -13111,13 +17104,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID }
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID }
},
- [683] = {
+ [845] = {
.class_hid = BNXT_ULP_CLASS_HID_3ba0,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -13129,12 +17122,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC }
},
- [684] = {
+ [846] = {
.class_hid = BNXT_ULP_CLASS_HID_0794,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 68,
.flow_pattern_id = 2,
@@ -13146,13 +17139,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID }
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID }
},
- [685] = {
+ [847] = {
.class_hid = BNXT_ULP_CLASS_HID_3858,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 4,
.flow_pattern_id = 2,
@@ -13164,12 +17157,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC }
},
- [686] = {
+ [848] = {
.class_hid = BNXT_ULP_CLASS_HID_046c,
- .class_tid = 2,
+ .class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 68,
.flow_pattern_id = 2,
@@ -13181,8 +17174,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID }
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID }
}
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
index b6db49cc5d..e55d0923a5 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 13 18:15:56 2021 */
+/* date: Thu May 20 11:56:39 2021 */
#ifndef ULP_TEMPLATE_DB_H_
#define ULP_TEMPLATE_DB_H_
@@ -11,13 +11,13 @@
#define BNXT_ULP_REGFILE_MAX_SZ 40
#define BNXT_ULP_MAX_NUM_DEVICES 4
#define BNXT_ULP_LOG2_MAX_NUM_DEV 2
-#define BNXT_ULP_GEN_TBL_MAX_SZ 10
+#define BNXT_ULP_GEN_TBL_MAX_SZ 12
#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 32768
-#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 687
+#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 849
#define BNXT_ULP_CLASS_HID_LOW_PRIME 6701
#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907
-#define BNXT_ULP_CLASS_HID_SHFTR 23
-#define BNXT_ULP_CLASS_HID_SHFTL 23
+#define BNXT_ULP_CLASS_HID_SHFTR 24
+#define BNXT_ULP_CLASS_HID_SHFTL 24
#define BNXT_ULP_CLASS_HID_MASK 32767
#define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048
#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 86
@@ -36,14 +36,14 @@
#define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7
#define BNXT_ULP_HDR_SIG_ID_SHIFT 4
#define BNXT_ULP_APP_ID_SHIFT 4
-#define BNXT_ULP_GLB_FIELD_TBL_SIZE 5595
-#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 5
-#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 74
-#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 495
-#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 20
-#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 546
-#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 43
-#define ULP_THOR_CLASS_TMPL_LIST_SIZE 5
+#define BNXT_ULP_GLB_FIELD_TBL_SIZE 7643
+#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 6
+#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 89
+#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 600
+#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 26
+#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 619
+#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 49
+#define ULP_THOR_CLASS_TMPL_LIST_SIZE 6
#define ULP_THOR_CLASS_TBL_LIST_SIZE 33
#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 242
#define ULP_THOR_CLASS_IDENT_LIST_SIZE 8
@@ -113,7 +113,8 @@ enum bnxt_ulp_hdr_bit {
BNXT_ULP_HDR_BIT_I_UDP = 0x0000000000010000,
BNXT_ULP_HDR_BIT_I_ICMP = 0x0000000000020000,
BNXT_ULP_HDR_BIT_F1 = 0x0000000000040000,
- BNXT_ULP_HDR_BIT_LAST = 0x0000000000080000
+ BNXT_ULP_HDR_BIT_F2 = 0x0000000000080000,
+ BNXT_ULP_HDR_BIT_LAST = 0x0000000000100000
};
enum bnxt_ulp_accept_opc {
@@ -199,8 +200,10 @@ enum bnxt_ulp_cf_idx {
BNXT_ULP_CF_IDX_FLOW_SIG_ID = 60,
BNXT_ULP_CF_IDX_WC_MATCH = 61,
BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG = 62,
- BNXT_ULP_CF_IDX_F1_DMAC = 63,
- BNXT_ULP_CF_IDX_LAST = 64
+ BNXT_ULP_CF_IDX_TUNNEL_ID = 63,
+ BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID = 64,
+ BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID = 65,
+ BNXT_ULP_CF_IDX_LAST = 66
};
enum bnxt_ulp_cond_list_opc {
@@ -315,7 +318,8 @@ enum bnxt_ulp_func_opc {
BNXT_ULP_FUNC_OPC_COPY_SRC1_TO_RF = 7,
BNXT_ULP_FUNC_OPC_RSS_CONFIG = 8,
BNXT_ULP_FUNC_OPC_GET_PARENT_MAC_ADDR = 9,
- BNXT_ULP_FUNC_OPC_LAST = 10
+ BNXT_ULP_FUNC_OPC_ALLOC_L2_CTX_ID = 10,
+ BNXT_ULP_FUNC_OPC_LAST = 11
};
enum bnxt_ulp_func_src {
@@ -497,7 +501,8 @@ enum bnxt_ulp_tcam_tbl_opc {
BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE = 2,
BNXT_ULP_TCAM_TBL_OPC_ALLOC_REGFILE = 3,
BNXT_ULP_TCAM_TBL_OPC_WR_REGFILE = 4,
- BNXT_ULP_TCAM_TBL_OPC_LAST = 5
+ BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT = 5,
+ BNXT_ULP_TCAM_TBL_OPC_LAST = 6
};
enum bnxt_ulp_template_type {
@@ -549,7 +554,8 @@ enum bnxt_ulp_resource_sub_type {
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM = 1,
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR = 2,
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE = 3,
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE = 4
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE = 4,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE = 5
};
enum bnxt_ulp_act_prop_sz {
@@ -1443,6 +1449,168 @@ enum bnxt_ulp_class_hid {
BNXT_ULP_CLASS_HID_15db = 0x15db,
BNXT_ULP_CLASS_HID_1151 = 0x1151,
BNXT_ULP_CLASS_HID_315d = 0x315d,
+ BNXT_ULP_CLASS_HID_3612 = 0x3612,
+ BNXT_ULP_CLASS_HID_66da = 0x66da,
+ BNXT_ULP_CLASS_HID_6165 = 0x6165,
+ BNXT_ULP_CLASS_HID_2aa1 = 0x2aa1,
+ BNXT_ULP_CLASS_HID_09cd = 0x09cd,
+ BNXT_ULP_CLASS_HID_3845 = 0x3845,
+ BNXT_ULP_CLASS_HID_11e9 = 0x11e9,
+ BNXT_ULP_CLASS_HID_4361 = 0x4361,
+ BNXT_ULP_CLASS_HID_218d = 0x218d,
+ BNXT_ULP_CLASS_HID_5105 = 0x5105,
+ BNXT_ULP_CLASS_HID_0c89 = 0x0c89,
+ BNXT_ULP_CLASS_HID_3e81 = 0x3e81,
+ BNXT_ULP_CLASS_HID_1dad = 0x1dad,
+ BNXT_ULP_CLASS_HID_4ca5 = 0x4ca5,
+ BNXT_ULP_CLASS_HID_25c9 = 0x25c9,
+ BNXT_ULP_CLASS_HID_57c1 = 0x57c1,
+ BNXT_ULP_CLASS_HID_33ed = 0x33ed,
+ BNXT_ULP_CLASS_HID_65e5 = 0x65e5,
+ BNXT_ULP_CLASS_HID_6dd9 = 0x6dd9,
+ BNXT_ULP_CLASS_HID_261d = 0x261d,
+ BNXT_ULP_CLASS_HID_0571 = 0x0571,
+ BNXT_ULP_CLASS_HID_34f9 = 0x34f9,
+ BNXT_ULP_CLASS_HID_1d55 = 0x1d55,
+ BNXT_ULP_CLASS_HID_4fdd = 0x4fdd,
+ BNXT_ULP_CLASS_HID_2d31 = 0x2d31,
+ BNXT_ULP_CLASS_HID_5db9 = 0x5db9,
+ BNXT_ULP_CLASS_HID_0035 = 0x0035,
+ BNXT_ULP_CLASS_HID_323d = 0x323d,
+ BNXT_ULP_CLASS_HID_1111 = 0x1111,
+ BNXT_ULP_CLASS_HID_4019 = 0x4019,
+ BNXT_ULP_CLASS_HID_2975 = 0x2975,
+ BNXT_ULP_CLASS_HID_5b7d = 0x5b7d,
+ BNXT_ULP_CLASS_HID_3f51 = 0x3f51,
+ BNXT_ULP_CLASS_HID_6959 = 0x6959,
+ BNXT_ULP_CLASS_HID_0e85 = 0x0e85,
+ BNXT_ULP_CLASS_HID_380d = 0x380d,
+ BNXT_ULP_CLASS_HID_1f21 = 0x1f21,
+ BNXT_ULP_CLASS_HID_4ea9 = 0x4ea9,
+ BNXT_ULP_CLASS_HID_1705 = 0x1705,
+ BNXT_ULP_CLASS_HID_418d = 0x418d,
+ BNXT_ULP_CLASS_HID_2721 = 0x2721,
+ BNXT_ULP_CLASS_HID_57a9 = 0x57a9,
+ BNXT_ULP_CLASS_HID_1a25 = 0x1a25,
+ BNXT_ULP_CLASS_HID_342d = 0x342d,
+ BNXT_ULP_CLASS_HID_2b01 = 0x2b01,
+ BNXT_ULP_CLASS_HID_5a09 = 0x5a09,
+ BNXT_ULP_CLASS_HID_2325 = 0x2325,
+ BNXT_ULP_CLASS_HID_5d2d = 0x5d2d,
+ BNXT_ULP_CLASS_HID_3101 = 0x3101,
+ BNXT_ULP_CLASS_HID_6309 = 0x6309,
+ BNXT_ULP_CLASS_HID_0bad = 0x0bad,
+ BNXT_ULP_CLASS_HID_2535 = 0x2535,
+ BNXT_ULP_CLASS_HID_1869 = 0x1869,
+ BNXT_ULP_CLASS_HID_4bf1 = 0x4bf1,
+ BNXT_ULP_CLASS_HID_136d = 0x136d,
+ BNXT_ULP_CLASS_HID_43f5 = 0x43f5,
+ BNXT_ULP_CLASS_HID_2129 = 0x2129,
+ BNXT_ULP_CLASS_HID_53b1 = 0x53b1,
+ BNXT_ULP_CLASS_HID_072d = 0x072d,
+ BNXT_ULP_CLASS_HID_3135 = 0x3135,
+ BNXT_ULP_CLASS_HID_1429 = 0x1429,
+ BNXT_ULP_CLASS_HID_4731 = 0x4731,
+ BNXT_ULP_CLASS_HID_2f6d = 0x2f6d,
+ BNXT_ULP_CLASS_HID_5f75 = 0x5f75,
+ BNXT_ULP_CLASS_HID_3d69 = 0x3d69,
+ BNXT_ULP_CLASS_HID_6f71 = 0x6f71,
+ BNXT_ULP_CLASS_HID_0dbd = 0x0dbd,
+ BNXT_ULP_CLASS_HID_3f25 = 0x3f25,
+ BNXT_ULP_CLASS_HID_1239 = 0x1239,
+ BNXT_ULP_CLASS_HID_4da1 = 0x4da1,
+ BNXT_ULP_CLASS_HID_153d = 0x153d,
+ BNXT_ULP_CLASS_HID_45a5 = 0x45a5,
+ BNXT_ULP_CLASS_HID_3bb9 = 0x3bb9,
+ BNXT_ULP_CLASS_HID_55a1 = 0x55a1,
+ BNXT_ULP_CLASS_HID_193d = 0x193d,
+ BNXT_ULP_CLASS_HID_4b25 = 0x4b25,
+ BNXT_ULP_CLASS_HID_2e39 = 0x2e39,
+ BNXT_ULP_CLASS_HID_5921 = 0x5921,
+ BNXT_ULP_CLASS_HID_213d = 0x213d,
+ BNXT_ULP_CLASS_HID_5125 = 0x5125,
+ BNXT_ULP_CLASS_HID_3739 = 0x3739,
+ BNXT_ULP_CLASS_HID_093d = 0x093d,
+ BNXT_ULP_CLASS_HID_684d = 0x684d,
+ BNXT_ULP_CLASS_HID_2389 = 0x2389,
+ BNXT_ULP_CLASS_HID_00e5 = 0x00e5,
+ BNXT_ULP_CLASS_HID_316d = 0x316d,
+ BNXT_ULP_CLASS_HID_18c1 = 0x18c1,
+ BNXT_ULP_CLASS_HID_4a49 = 0x4a49,
+ BNXT_ULP_CLASS_HID_28a5 = 0x28a5,
+ BNXT_ULP_CLASS_HID_582d = 0x582d,
+ BNXT_ULP_CLASS_HID_05a1 = 0x05a1,
+ BNXT_ULP_CLASS_HID_37a9 = 0x37a9,
+ BNXT_ULP_CLASS_HID_1485 = 0x1485,
+ BNXT_ULP_CLASS_HID_458d = 0x458d,
+ BNXT_ULP_CLASS_HID_2ce1 = 0x2ce1,
+ BNXT_ULP_CLASS_HID_5ee9 = 0x5ee9,
+ BNXT_ULP_CLASS_HID_3ac5 = 0x3ac5,
+ BNXT_ULP_CLASS_HID_6ccd = 0x6ccd,
+ BNXT_ULP_CLASS_HID_0b11 = 0x0b11,
+ BNXT_ULP_CLASS_HID_3d99 = 0x3d99,
+ BNXT_ULP_CLASS_HID_1ab5 = 0x1ab5,
+ BNXT_ULP_CLASS_HID_4b3d = 0x4b3d,
+ BNXT_ULP_CLASS_HID_1291 = 0x1291,
+ BNXT_ULP_CLASS_HID_4419 = 0x4419,
+ BNXT_ULP_CLASS_HID_22b5 = 0x22b5,
+ BNXT_ULP_CLASS_HID_523d = 0x523d,
+ BNXT_ULP_CLASS_HID_1fb1 = 0x1fb1,
+ BNXT_ULP_CLASS_HID_31b9 = 0x31b9,
+ BNXT_ULP_CLASS_HID_2e95 = 0x2e95,
+ BNXT_ULP_CLASS_HID_5f9d = 0x5f9d,
+ BNXT_ULP_CLASS_HID_26b1 = 0x26b1,
+ BNXT_ULP_CLASS_HID_58b9 = 0x58b9,
+ BNXT_ULP_CLASS_HID_3495 = 0x3495,
+ BNXT_ULP_CLASS_HID_669d = 0x669d,
+ BNXT_ULP_CLASS_HID_0e39 = 0x0e39,
+ BNXT_ULP_CLASS_HID_20a1 = 0x20a1,
+ BNXT_ULP_CLASS_HID_1dfd = 0x1dfd,
+ BNXT_ULP_CLASS_HID_4e65 = 0x4e65,
+ BNXT_ULP_CLASS_HID_16f9 = 0x16f9,
+ BNXT_ULP_CLASS_HID_4661 = 0x4661,
+ BNXT_ULP_CLASS_HID_24bd = 0x24bd,
+ BNXT_ULP_CLASS_HID_5625 = 0x5625,
+ BNXT_ULP_CLASS_HID_02b9 = 0x02b9,
+ BNXT_ULP_CLASS_HID_34a1 = 0x34a1,
+ BNXT_ULP_CLASS_HID_11bd = 0x11bd,
+ BNXT_ULP_CLASS_HID_42a5 = 0x42a5,
+ BNXT_ULP_CLASS_HID_2af9 = 0x2af9,
+ BNXT_ULP_CLASS_HID_5ae1 = 0x5ae1,
+ BNXT_ULP_CLASS_HID_38fd = 0x38fd,
+ BNXT_ULP_CLASS_HID_6ae5 = 0x6ae5,
+ BNXT_ULP_CLASS_HID_0829 = 0x0829,
+ BNXT_ULP_CLASS_HID_3ab1 = 0x3ab1,
+ BNXT_ULP_CLASS_HID_17ad = 0x17ad,
+ BNXT_ULP_CLASS_HID_4835 = 0x4835,
+ BNXT_ULP_CLASS_HID_10a9 = 0x10a9,
+ BNXT_ULP_CLASS_HID_4031 = 0x4031,
+ BNXT_ULP_CLASS_HID_3e2d = 0x3e2d,
+ BNXT_ULP_CLASS_HID_5035 = 0x5035,
+ BNXT_ULP_CLASS_HID_1ca9 = 0x1ca9,
+ BNXT_ULP_CLASS_HID_4eb1 = 0x4eb1,
+ BNXT_ULP_CLASS_HID_2bad = 0x2bad,
+ BNXT_ULP_CLASS_HID_5cb5 = 0x5cb5,
+ BNXT_ULP_CLASS_HID_24a9 = 0x24a9,
+ BNXT_ULP_CLASS_HID_54b1 = 0x54b1,
+ BNXT_ULP_CLASS_HID_32ad = 0x32ad,
+ BNXT_ULP_CLASS_HID_0ca9 = 0x0ca9,
+ BNXT_ULP_CLASS_HID_7f35 = 0x7f35,
+ BNXT_ULP_CLASS_HID_34f1 = 0x34f1,
+ BNXT_ULP_CLASS_HID_179d = 0x179d,
+ BNXT_ULP_CLASS_HID_2615 = 0x2615,
+ BNXT_ULP_CLASS_HID_0fb9 = 0x0fb9,
+ BNXT_ULP_CLASS_HID_5d31 = 0x5d31,
+ BNXT_ULP_CLASS_HID_3fdd = 0x3fdd,
+ BNXT_ULP_CLASS_HID_4f55 = 0x4f55,
+ BNXT_ULP_CLASS_HID_12d9 = 0x12d9,
+ BNXT_ULP_CLASS_HID_20d1 = 0x20d1,
+ BNXT_ULP_CLASS_HID_03fd = 0x03fd,
+ BNXT_ULP_CLASS_HID_52f5 = 0x52f5,
+ BNXT_ULP_CLASS_HID_3b99 = 0x3b99,
+ BNXT_ULP_CLASS_HID_4991 = 0x4991,
+ BNXT_ULP_CLASS_HID_2dbd = 0x2dbd,
+ BNXT_ULP_CLASS_HID_7bb5 = 0x7bb5,
BNXT_ULP_CLASS_HID_34c6 = 0x34c6,
BNXT_ULP_CLASS_HID_0c22 = 0x0c22,
BNXT_ULP_CLASS_HID_1cbe = 0x1cbe,
@@ -1876,8 +2044,8 @@ enum bnxt_ulp_act_hid {
};
enum bnxt_ulp_df_tpl {
- BNXT_ULP_DF_TPL_DEFAULT_UPLINK_PORT = 3,
- BNXT_ULP_DF_TPL_DEFAULT_VFR = 4
+ BNXT_ULP_DF_TPL_DEFAULT_UPLINK_PORT = 4,
+ BNXT_ULP_DF_TPL_DEFAULT_VFR = 5
};
#endif
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h
index 115bdc644c..1d7bbfe2cc 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Wed Mar 17 11:31:19 2021 */
+/* date: Thu May 20 11:56:39 2021 */
#ifndef ULP_HDR_FIELD_ENUMS_H_
#define ULP_HDR_FIELD_ENUMS_H_
@@ -415,272 +415,460 @@ enum bnxt_ulp_hf_0_2_0_bitmask {
BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_VER = 0x0400000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_TC = 0x0200000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_TTL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_TOS = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_LEN = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_LENGTH = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_CSUM = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_FLAGS = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_RSVD0 = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_VNI = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_RSVD1 = 0x0000020000000000
};
enum bnxt_ulp_hf_0_2_1_bitmask {
BNXT_ULP_HF_0_2_1_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_VER = 0x0400000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TOS = 0x0200000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_LEN = 0x0100000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TTL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000
};
enum bnxt_ulp_hf_0_2_2_bitmask {
BNXT_ULP_HF_0_2_2_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID = 0x0200000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_VER = 0x0080000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_TC = 0x0040000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_TTL = 0x0004000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SENT_SEQ = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_RECV_ACK = 0x0000000008000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DATA_OFF = 0x0000000004000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_TCP_FLAGS = 0x0000000002000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_RX_WIN = 0x0000000001000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_CSUM = 0x0000000000800000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_URP = 0x0000000000400000
};
enum bnxt_ulp_hf_0_2_3_bitmask {
BNXT_ULP_HF_0_2_3_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID = 0x0200000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_VER = 0x0080000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TOS = 0x0040000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_LEN = 0x0020000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TTL = 0x0004000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_LENGTH = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_CSUM = 0x0000000008000000
};
enum bnxt_ulp_hf_0_2_4_bitmask {
BNXT_ULP_HF_0_2_4_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_VER = 0x0400000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_TC = 0x0200000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_TTL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT = 0x0004000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT = 0x0002000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SENT_SEQ = 0x0001000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_RECV_ACK = 0x0000800000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DATA_OFF = 0x0000400000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_TCP_FLAGS = 0x0000200000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_RX_WIN = 0x0000100000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_CSUM = 0x0000080000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_URP = 0x0000040000000000
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_TYPE = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_CODE = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_CSUM = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_IDENT = 0x0000000008000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_SEQ_NUM = 0x0000000004000000
};
-enum bnxt_ulp_hf_0_2_5_bitmask {
- BNXT_ULP_HF_0_2_5_BITMASK_WM = 0x8000000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_VER = 0x0400000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_TOS = 0x0200000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_LEN = 0x0100000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_TTL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT = 0x0000800000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_RX_WIN = 0x0000040000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_CSUM = 0x0000020000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_URP = 0x0000010000000000
+enum bnxt_ulp_hf_0_3_0_bitmask {
+ BNXT_ULP_HF_0_3_0_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_TC = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000
};
-enum bnxt_ulp_hf_0_2_6_bitmask {
- BNXT_ULP_HF_0_2_6_BITMASK_WM = 0x8000000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_VER = 0x0400000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_TC = 0x0200000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_TTL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT = 0x0002000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_LENGTH = 0x0001000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_CSUM = 0x0000800000000000
+enum bnxt_ulp_hf_0_3_1_bitmask {
+ BNXT_ULP_HF_0_3_1_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_TOS = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_LEN = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000
};
-enum bnxt_ulp_hf_0_2_7_bitmask {
- BNXT_ULP_HF_0_2_7_BITMASK_WM = 0x8000000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_VER = 0x0400000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_TOS = 0x0200000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_LEN = 0x0100000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_TTL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT = 0x0000800000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_LENGTH = 0x0000400000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_CSUM = 0x0000200000000000
+enum bnxt_ulp_hf_0_3_2_bitmask {
+ BNXT_ULP_HF_0_3_2_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_VER = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_TC = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_TTL = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000
};
-enum bnxt_ulp_hf_0_2_8_bitmask {
- BNXT_ULP_HF_0_2_8_BITMASK_WM = 0x8000000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID = 0x0200000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_VER = 0x0080000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_TC = 0x0040000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_TTL = 0x0004000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT = 0x0000400000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_RX_WIN = 0x0000020000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_CSUM = 0x0000010000000000,
- BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_URP = 0x0000008000000000
+enum bnxt_ulp_hf_0_3_3_bitmask {
+ BNXT_ULP_HF_0_3_3_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_VER = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_TOS = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_LEN = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_TTL = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000
};
-enum bnxt_ulp_hf_0_2_9_bitmask {
- BNXT_ULP_HF_0_2_9_BITMASK_WM = 0x8000000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID = 0x0200000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_VER = 0x0080000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_TOS = 0x0040000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_LEN = 0x0020000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_TTL = 0x0004000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT = 0x0000100000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_RX_WIN = 0x0000008000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_CSUM = 0x0000004000000000,
- BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_URP = 0x0000002000000000
+enum bnxt_ulp_hf_0_3_4_bitmask {
+ BNXT_ULP_HF_0_3_4_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_TC = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SENT_SEQ = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_RECV_ACK = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DATA_OFF = 0x0000400000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_TCP_FLAGS = 0x0000200000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_RX_WIN = 0x0000100000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_CSUM = 0x0000080000000000,
+ BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_URP = 0x0000040000000000
};
-enum bnxt_ulp_hf_0_2_10_bitmask {
- BNXT_ULP_HF_0_2_10_BITMASK_WM = 0x8000000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID = 0x0200000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_VER = 0x0080000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_TC = 0x0040000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_TTL = 0x0004000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT = 0x0000400000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_LENGTH = 0x0000200000000000,
- BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_CSUM = 0x0000100000000000
+enum bnxt_ulp_hf_0_3_5_bitmask {
+ BNXT_ULP_HF_0_3_5_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_TOS = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_LEN = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_RX_WIN = 0x0000040000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_CSUM = 0x0000020000000000,
+ BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_URP = 0x0000010000000000
};
-enum bnxt_ulp_hf_0_2_11_bitmask {
- BNXT_ULP_HF_0_2_11_BITMASK_WM = 0x8000000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC = 0x2000000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC = 0x1000000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID = 0x0200000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_VER = 0x0080000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_TOS = 0x0040000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_LEN = 0x0020000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_TTL = 0x0004000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT = 0x0000100000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_LENGTH = 0x0000080000000000,
- BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_CSUM = 0x0000040000000000
+enum bnxt_ulp_hf_0_3_6_bitmask {
+ BNXT_ULP_HF_0_3_6_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_TC = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_LENGTH = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_CSUM = 0x0000800000000000
+};
+
+enum bnxt_ulp_hf_0_3_7_bitmask {
+ BNXT_ULP_HF_0_3_7_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_TOS = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_LEN = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_LENGTH = 0x0000400000000000,
+ BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_CSUM = 0x0000200000000000
+};
+
+enum bnxt_ulp_hf_0_3_8_bitmask {
+ BNXT_ULP_HF_0_3_8_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_VER = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_TC = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_TTL = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT = 0x0000400000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_RX_WIN = 0x0000020000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_CSUM = 0x0000010000000000,
+ BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_URP = 0x0000008000000000
+};
+
+enum bnxt_ulp_hf_0_3_9_bitmask {
+ BNXT_ULP_HF_0_3_9_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_VER = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_TOS = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_LEN = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_TTL = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT = 0x0000100000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_RX_WIN = 0x0000008000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_CSUM = 0x0000004000000000,
+ BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_URP = 0x0000002000000000
+};
+
+enum bnxt_ulp_hf_0_3_10_bitmask {
+ BNXT_ULP_HF_0_3_10_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_VER = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_TC = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_TTL = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT = 0x0000400000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_LENGTH = 0x0000200000000000,
+ BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_CSUM = 0x0000100000000000
+};
+
+enum bnxt_ulp_hf_0_3_11_bitmask {
+ BNXT_ULP_HF_0_3_11_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID = 0x0200000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_VER = 0x0080000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_TOS = 0x0040000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_LEN = 0x0020000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_TTL = 0x0004000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT = 0x0000100000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_LENGTH = 0x0000080000000000,
+ BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_CSUM = 0x0000040000000000
};
#endif
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
index 2debaea0ca..58b4dba63c 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 13 18:15:56 2021 */
+/* date: Thu May 20 11:56:39 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -111,6 +111,26 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = {
.num_buckets = 0,
.hash_tbl_entries = 0,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE << 1 |
+ BNXT_ULP_DIRECTION_INGRESS] = {
+ .name = "INGRESS GENERIC_TABLE_TUNNEL_CACHE",
+ .result_num_entries = 256,
+ .result_num_bytes = 7,
+ .key_num_bytes = 2,
+ .num_buckets = 8,
+ .hash_tbl_entries = 1024,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE << 1 |
+ BNXT_ULP_DIRECTION_EGRESS] = {
+ .name = "EGRESS GENERIC_TABLE_TUNNEL_CACHE",
+ .result_num_entries = 256,
+ .result_num_bytes = 7,
+ .key_num_bytes = 2,
+ .num_buckets = 8,
+ .hash_tbl_entries = 1024,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
}
};
@@ -3098,238 +3118,411 @@ uint8_t ulp_glb_field_tbl[] = {
[4098] = 2,
[4100] = 3,
[4102] = 4,
- [4136] = 5,
- [4138] = 6,
- [4140] = 7,
- [4142] = 8,
- [4144] = 9,
- [4146] = 10,
- [4148] = 11,
- [4150] = 12,
+ [4116] = 5,
+ [4118] = 6,
+ [4120] = 7,
+ [4122] = 8,
+ [4124] = 9,
+ [4126] = 10,
+ [4128] = 11,
+ [4130] = 12,
+ [4132] = 13,
+ [4134] = 14,
+ [4170] = 15,
+ [4172] = 16,
+ [4174] = 17,
+ [4176] = 18,
+ [4190] = 19,
+ [4191] = 20,
+ [4192] = 21,
+ [4193] = 22,
[4224] = 0,
[4225] = 1,
- [4226] = 2,
- [4228] = 3,
- [4230] = 4,
- [4244] = 5,
- [4246] = 6,
- [4248] = 7,
- [4250] = 8,
- [4252] = 9,
- [4254] = 10,
- [4256] = 11,
- [4258] = 12,
- [4260] = 13,
- [4262] = 14,
+ [4227] = 20,
+ [4229] = 21,
+ [4231] = 22,
+ [4244] = 2,
+ [4245] = 23,
+ [4246] = 3,
+ [4247] = 24,
+ [4248] = 4,
+ [4249] = 25,
+ [4250] = 5,
+ [4251] = 26,
+ [4252] = 6,
+ [4253] = 27,
+ [4254] = 7,
+ [4255] = 28,
+ [4256] = 8,
+ [4257] = 29,
+ [4258] = 9,
+ [4259] = 30,
+ [4260] = 10,
+ [4261] = 31,
+ [4262] = 11,
+ [4263] = 32,
+ [4298] = 12,
+ [4300] = 13,
+ [4302] = 14,
+ [4304] = 15,
+ [4318] = 16,
+ [4319] = 17,
+ [4320] = 18,
+ [4321] = 19,
[4352] = 0,
[4353] = 1,
- [4354] = 2,
- [4356] = 3,
- [4358] = 4,
- [4392] = 8,
- [4394] = 9,
- [4396] = 10,
- [4398] = 11,
- [4400] = 12,
- [4402] = 13,
- [4404] = 14,
- [4406] = 15,
- [4434] = 5,
- [4438] = 6,
- [4442] = 7,
+ [4355] = 20,
+ [4357] = 21,
+ [4359] = 22,
+ [4372] = 2,
+ [4373] = 23,
+ [4374] = 3,
+ [4375] = 24,
+ [4376] = 4,
+ [4377] = 25,
+ [4378] = 5,
+ [4379] = 26,
+ [4380] = 6,
+ [4381] = 27,
+ [4382] = 7,
+ [4383] = 28,
+ [4384] = 8,
+ [4385] = 29,
+ [4386] = 9,
+ [4387] = 30,
+ [4388] = 10,
+ [4389] = 31,
+ [4390] = 11,
+ [4391] = 32,
+ [4409] = 33,
+ [4411] = 34,
+ [4413] = 35,
+ [4415] = 36,
+ [4417] = 37,
+ [4419] = 38,
+ [4421] = 39,
+ [4423] = 40,
+ [4425] = 41,
+ [4426] = 12,
+ [4428] = 13,
+ [4430] = 14,
+ [4432] = 15,
+ [4446] = 16,
+ [4447] = 17,
+ [4448] = 18,
+ [4449] = 19,
[4480] = 0,
[4481] = 1,
- [4482] = 2,
- [4484] = 3,
- [4486] = 4,
- [4500] = 8,
- [4502] = 9,
- [4504] = 10,
- [4506] = 11,
- [4508] = 12,
- [4510] = 13,
- [4512] = 14,
- [4514] = 15,
- [4516] = 16,
- [4518] = 17,
- [4562] = 5,
- [4566] = 6,
- [4570] = 7,
+ [4483] = 20,
+ [4485] = 21,
+ [4487] = 22,
+ [4500] = 2,
+ [4501] = 23,
+ [4502] = 3,
+ [4503] = 24,
+ [4504] = 4,
+ [4505] = 25,
+ [4506] = 5,
+ [4507] = 26,
+ [4508] = 6,
+ [4509] = 27,
+ [4510] = 7,
+ [4511] = 28,
+ [4512] = 8,
+ [4513] = 29,
+ [4514] = 9,
+ [4515] = 30,
+ [4516] = 10,
+ [4517] = 31,
+ [4518] = 11,
+ [4519] = 32,
+ [4554] = 12,
+ [4555] = 33,
+ [4556] = 13,
+ [4557] = 34,
+ [4558] = 14,
+ [4559] = 35,
+ [4560] = 15,
+ [4561] = 36,
+ [4574] = 16,
+ [4575] = 17,
+ [4576] = 18,
+ [4577] = 19,
[4608] = 0,
[4609] = 1,
- [4610] = 2,
- [4612] = 3,
- [4614] = 4,
- [4648] = 5,
- [4650] = 6,
- [4652] = 7,
- [4654] = 8,
- [4656] = 9,
- [4658] = 10,
- [4660] = 11,
- [4662] = 12,
- [4664] = 13,
- [4666] = 14,
- [4668] = 15,
- [4670] = 16,
- [4672] = 17,
- [4674] = 18,
- [4676] = 19,
- [4678] = 20,
- [4680] = 21,
- [4736] = 0,
- [4737] = 1,
- [4738] = 2,
- [4740] = 3,
- [4742] = 4,
- [4756] = 5,
- [4758] = 6,
- [4760] = 7,
- [4762] = 8,
- [4764] = 9,
- [4766] = 10,
- [4768] = 11,
- [4770] = 12,
- [4772] = 13,
- [4774] = 14,
- [4792] = 15,
- [4794] = 16,
- [4796] = 17,
- [4798] = 18,
- [4800] = 19,
- [4802] = 20,
- [4804] = 21,
- [4806] = 22,
- [4808] = 23,
- [4864] = 0,
- [4865] = 1,
- [4866] = 2,
- [4868] = 3,
- [4870] = 4,
- [4904] = 5,
- [4906] = 6,
- [4908] = 7,
- [4910] = 8,
- [4912] = 9,
- [4914] = 10,
- [4916] = 11,
- [4918] = 12,
- [4938] = 13,
- [4940] = 14,
- [4942] = 15,
- [4944] = 16,
- [4992] = 0,
- [4993] = 1,
- [4994] = 2,
- [4996] = 3,
- [4998] = 4,
- [5012] = 5,
- [5014] = 6,
- [5016] = 7,
- [5018] = 8,
- [5020] = 9,
- [5022] = 10,
- [5024] = 11,
- [5026] = 12,
- [5028] = 13,
- [5030] = 14,
- [5066] = 15,
- [5068] = 16,
- [5070] = 17,
- [5072] = 18,
- [5120] = 0,
- [5121] = 1,
- [5122] = 2,
- [5124] = 3,
- [5126] = 4,
- [5160] = 8,
- [5162] = 9,
- [5164] = 10,
- [5166] = 11,
- [5168] = 12,
- [5170] = 13,
- [5172] = 14,
- [5174] = 15,
- [5176] = 16,
- [5178] = 17,
- [5180] = 18,
- [5182] = 19,
- [5184] = 20,
- [5186] = 21,
- [5188] = 22,
- [5190] = 23,
- [5192] = 24,
- [5202] = 5,
- [5206] = 6,
- [5210] = 7,
- [5248] = 0,
- [5249] = 1,
- [5250] = 2,
- [5252] = 3,
- [5254] = 4,
- [5268] = 8,
- [5270] = 9,
- [5272] = 10,
- [5274] = 11,
- [5276] = 12,
- [5278] = 13,
- [5280] = 14,
- [5282] = 15,
- [5284] = 16,
- [5286] = 17,
- [5304] = 18,
- [5306] = 19,
- [5308] = 20,
- [5310] = 21,
- [5312] = 22,
- [5314] = 23,
- [5316] = 24,
- [5318] = 25,
- [5320] = 26,
- [5330] = 5,
- [5334] = 6,
- [5338] = 7,
- [5376] = 0,
- [5377] = 1,
- [5378] = 2,
- [5380] = 3,
- [5382] = 4,
- [5416] = 8,
- [5418] = 9,
- [5420] = 10,
- [5422] = 11,
- [5424] = 12,
- [5426] = 13,
- [5428] = 14,
- [5430] = 15,
- [5450] = 16,
- [5452] = 17,
- [5454] = 18,
- [5456] = 19,
- [5458] = 5,
- [5462] = 6,
- [5466] = 7,
- [5504] = 0,
- [5505] = 1,
- [5506] = 2,
- [5508] = 3,
- [5510] = 4,
- [5524] = 8,
- [5526] = 9,
- [5528] = 10,
- [5530] = 11,
- [5532] = 12,
- [5534] = 13,
- [5536] = 14,
- [5538] = 15,
- [5540] = 16,
- [5542] = 17,
- [5578] = 18,
- [5580] = 19,
- [5582] = 20,
- [5584] = 21,
- [5586] = 5,
- [5590] = 6,
- [5594] = 7
+ [4611] = 20,
+ [4613] = 21,
+ [4615] = 22,
+ [4619] = 33,
+ [4621] = 34,
+ [4623] = 35,
+ [4625] = 36,
+ [4627] = 37,
+ [4628] = 2,
+ [4629] = 23,
+ [4630] = 3,
+ [4631] = 24,
+ [4632] = 4,
+ [4633] = 25,
+ [4634] = 5,
+ [4635] = 26,
+ [4636] = 6,
+ [4637] = 27,
+ [4638] = 7,
+ [4639] = 28,
+ [4640] = 8,
+ [4641] = 29,
+ [4642] = 9,
+ [4643] = 30,
+ [4644] = 10,
+ [4645] = 31,
+ [4646] = 11,
+ [4647] = 32,
+ [4682] = 12,
+ [4684] = 13,
+ [4686] = 14,
+ [4688] = 15,
+ [4702] = 16,
+ [4703] = 17,
+ [4704] = 18,
+ [4705] = 19,
+ [6144] = 0,
+ [6145] = 1,
+ [6146] = 2,
+ [6148] = 3,
+ [6150] = 4,
+ [6184] = 5,
+ [6186] = 6,
+ [6188] = 7,
+ [6190] = 8,
+ [6192] = 9,
+ [6194] = 10,
+ [6196] = 11,
+ [6198] = 12,
+ [6272] = 0,
+ [6273] = 1,
+ [6274] = 2,
+ [6276] = 3,
+ [6278] = 4,
+ [6292] = 5,
+ [6294] = 6,
+ [6296] = 7,
+ [6298] = 8,
+ [6300] = 9,
+ [6302] = 10,
+ [6304] = 11,
+ [6306] = 12,
+ [6308] = 13,
+ [6310] = 14,
+ [6400] = 0,
+ [6401] = 1,
+ [6402] = 2,
+ [6404] = 3,
+ [6406] = 4,
+ [6440] = 8,
+ [6442] = 9,
+ [6444] = 10,
+ [6446] = 11,
+ [6448] = 12,
+ [6450] = 13,
+ [6452] = 14,
+ [6454] = 15,
+ [6482] = 5,
+ [6486] = 6,
+ [6490] = 7,
+ [6528] = 0,
+ [6529] = 1,
+ [6530] = 2,
+ [6532] = 3,
+ [6534] = 4,
+ [6548] = 8,
+ [6550] = 9,
+ [6552] = 10,
+ [6554] = 11,
+ [6556] = 12,
+ [6558] = 13,
+ [6560] = 14,
+ [6562] = 15,
+ [6564] = 16,
+ [6566] = 17,
+ [6610] = 5,
+ [6614] = 6,
+ [6618] = 7,
+ [6656] = 0,
+ [6657] = 1,
+ [6658] = 2,
+ [6660] = 3,
+ [6662] = 4,
+ [6696] = 5,
+ [6698] = 6,
+ [6700] = 7,
+ [6702] = 8,
+ [6704] = 9,
+ [6706] = 10,
+ [6708] = 11,
+ [6710] = 12,
+ [6712] = 13,
+ [6714] = 14,
+ [6716] = 15,
+ [6718] = 16,
+ [6720] = 17,
+ [6722] = 18,
+ [6724] = 19,
+ [6726] = 20,
+ [6728] = 21,
+ [6784] = 0,
+ [6785] = 1,
+ [6786] = 2,
+ [6788] = 3,
+ [6790] = 4,
+ [6804] = 5,
+ [6806] = 6,
+ [6808] = 7,
+ [6810] = 8,
+ [6812] = 9,
+ [6814] = 10,
+ [6816] = 11,
+ [6818] = 12,
+ [6820] = 13,
+ [6822] = 14,
+ [6840] = 15,
+ [6842] = 16,
+ [6844] = 17,
+ [6846] = 18,
+ [6848] = 19,
+ [6850] = 20,
+ [6852] = 21,
+ [6854] = 22,
+ [6856] = 23,
+ [6912] = 0,
+ [6913] = 1,
+ [6914] = 2,
+ [6916] = 3,
+ [6918] = 4,
+ [6952] = 5,
+ [6954] = 6,
+ [6956] = 7,
+ [6958] = 8,
+ [6960] = 9,
+ [6962] = 10,
+ [6964] = 11,
+ [6966] = 12,
+ [6986] = 13,
+ [6988] = 14,
+ [6990] = 15,
+ [6992] = 16,
+ [7040] = 0,
+ [7041] = 1,
+ [7042] = 2,
+ [7044] = 3,
+ [7046] = 4,
+ [7060] = 5,
+ [7062] = 6,
+ [7064] = 7,
+ [7066] = 8,
+ [7068] = 9,
+ [7070] = 10,
+ [7072] = 11,
+ [7074] = 12,
+ [7076] = 13,
+ [7078] = 14,
+ [7114] = 15,
+ [7116] = 16,
+ [7118] = 17,
+ [7120] = 18,
+ [7168] = 0,
+ [7169] = 1,
+ [7170] = 2,
+ [7172] = 3,
+ [7174] = 4,
+ [7208] = 8,
+ [7210] = 9,
+ [7212] = 10,
+ [7214] = 11,
+ [7216] = 12,
+ [7218] = 13,
+ [7220] = 14,
+ [7222] = 15,
+ [7224] = 16,
+ [7226] = 17,
+ [7228] = 18,
+ [7230] = 19,
+ [7232] = 20,
+ [7234] = 21,
+ [7236] = 22,
+ [7238] = 23,
+ [7240] = 24,
+ [7250] = 5,
+ [7254] = 6,
+ [7258] = 7,
+ [7296] = 0,
+ [7297] = 1,
+ [7298] = 2,
+ [7300] = 3,
+ [7302] = 4,
+ [7316] = 8,
+ [7318] = 9,
+ [7320] = 10,
+ [7322] = 11,
+ [7324] = 12,
+ [7326] = 13,
+ [7328] = 14,
+ [7330] = 15,
+ [7332] = 16,
+ [7334] = 17,
+ [7352] = 18,
+ [7354] = 19,
+ [7356] = 20,
+ [7358] = 21,
+ [7360] = 22,
+ [7362] = 23,
+ [7364] = 24,
+ [7366] = 25,
+ [7368] = 26,
+ [7378] = 5,
+ [7382] = 6,
+ [7386] = 7,
+ [7424] = 0,
+ [7425] = 1,
+ [7426] = 2,
+ [7428] = 3,
+ [7430] = 4,
+ [7464] = 8,
+ [7466] = 9,
+ [7468] = 10,
+ [7470] = 11,
+ [7472] = 12,
+ [7474] = 13,
+ [7476] = 14,
+ [7478] = 15,
+ [7498] = 16,
+ [7500] = 17,
+ [7502] = 18,
+ [7504] = 19,
+ [7506] = 5,
+ [7510] = 6,
+ [7514] = 7,
+ [7552] = 0,
+ [7553] = 1,
+ [7554] = 2,
+ [7556] = 3,
+ [7558] = 4,
+ [7572] = 8,
+ [7574] = 9,
+ [7576] = 10,
+ [7578] = 11,
+ [7580] = 12,
+ [7582] = 13,
+ [7584] = 14,
+ [7586] = 15,
+ [7588] = 16,
+ [7590] = 17,
+ [7626] = 18,
+ [7628] = 19,
+ [7630] = 20,
+ [7632] = 21,
+ [7634] = 5,
+ [7638] = 6,
+ [7642] = 7
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
index e342f340d9..d20c4197fa 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 13 18:15:56 2021 */
+/* date: Thu May 20 11:56:39 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -22,8 +22,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {
.cond_start_idx = 0,
.cond_nums = 4 }
},
- /* class_tid: 3, ingress */
- [3] = {
+ /* class_tid: 4, ingress */
+ [4] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
.num_tbls = 15,
.start_tbl_idx = 12,
@@ -32,8 +32,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {
.cond_start_idx = 8,
.cond_nums = 1 }
},
- /* class_tid: 4, egress */
- [4] = {
+ /* class_tid: 5, egress */
+ [5] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
.num_tbls = 6,
.start_tbl_idx = 27,
@@ -306,7 +306,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 38,
.result_num_fields = 5
},
- { /* class_tid: 3, , table: int_full_act_record.0 */
+ { /* class_tid: 4, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@@ -327,7 +327,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 128,
.result_num_fields = 17
},
- { /* class_tid: 3, , table: port_table.wr_0 */
+ { /* class_tid: 4, , table: port_table.wr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
@@ -350,7 +350,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 152,
.result_num_fields = 5
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
@@ -372,7 +372,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.ident_start_idx = 6,
.ident_nums = 0
},
- { /* class_tid: 3, , table: control.ing_0 */
+ { /* class_tid: 4, , table: control.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
@@ -385,7 +385,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
+ { /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.direction = TF_DIR_RX,
@@ -414,7 +414,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.ident_start_idx = 6,
.ident_nums = 1
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
@@ -437,7 +437,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */
+ { /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
.direction = TF_DIR_RX,
@@ -455,7 +455,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */
+ { /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
.direction = TF_DIR_RX,
@@ -473,7 +473,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 3, , table: control.egr_0 */
+ { /* class_tid: 4, , table: control.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
@@ -485,7 +485,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 3, , table: int_full_act_record.egr_0 */
+ { /* class_tid: 4, , table: int_full_act_record.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@@ -507,7 +507,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_num_fields = 17,
.encap_num_fields = 0
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
@@ -529,7 +529,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.ident_start_idx = 7,
.ident_nums = 0
},
- { /* class_tid: 3, , table: control.egr_1 */
+ { /* class_tid: 4, , table: control.egr_1 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
@@ -542,7 +542,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
+ { /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.direction = TF_DIR_TX,
@@ -569,7 +569,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.ident_start_idx = 7,
.ident_nums = 1
},
- { /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */
+ { /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
.direction = TF_DIR_TX,
@@ -587,7 +587,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */
+ { /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
.direction = TF_DIR_TX,
@@ -605,7 +605,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 4, , table: int_full_act_record.loopback */
+ { /* class_tid: 5, , table: int_full_act_record.loopback */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@@ -627,7 +627,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_num_fields = 17,
.encap_num_fields = 0
},
- { /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */
+ { /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
.direction = TF_DIR_TX,
@@ -645,7 +645,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */
+ { /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
.direction = TF_DIR_TX,
@@ -663,7 +663,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 4, , table: int_full_act_record.vf_ing */
+ { /* class_tid: 5, , table: int_full_act_record.vf_ing */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@@ -685,7 +685,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_num_fields = 17,
.encap_num_fields = 0
},
- { /* class_tid: 4, , table: vtag_encap_record.vfr_egr0 */
+ { /* class_tid: 5, , table: vtag_encap_record.vfr_egr0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
.resource_sub_type =
@@ -707,7 +707,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_num_fields = 0,
.encap_num_fields = 11
},
- { /* class_tid: 4, , table: int_full_act_record.vfr_egr0 */
+ { /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@@ -768,27 +768,27 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
.cond_operand = BNXT_ULP_CF_IDX_O_L4
},
- /* cond_reject: thor, class_tid: 3 */
+ /* cond_reject: thor, class_tid: 4 */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
},
- /* cond_execute: class_tid: 3, control.ing_0 */
+ /* cond_execute: class_tid: 4, control.ing_0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 3, control.egr_0 */
+ /* cond_execute: class_tid: 4, control.egr_0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
},
- /* cond_execute: class_tid: 3, control.egr_1 */
+ /* cond_execute: class_tid: 4, control.egr_1 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_reject: thor, class_tid: 4 */
+ /* cond_reject: thor, class_tid: 5 */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
@@ -3612,7 +3612,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
- /* class_tid: 3, , table: port_table.wr_0 */
+ /* class_tid: 4, , table: port_table.wr_0 */
{
.field_info_mask = {
.description = "dev.port_id",
@@ -3633,7 +3633,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
{
.field_info_mask = {
.description = "svif",
@@ -3653,7 +3653,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
.field_info_mask = {
.description = "etype",
@@ -3958,7 +3958,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
1}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
{
.field_info_mask = {
.description = "svif",
@@ -3978,7 +3978,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */
{
.field_info_mask = {
.description = "svif",
@@ -3998,7 +3998,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
.field_info_mask = {
.description = "etype",
@@ -5187,7 +5187,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 3, , table: int_full_act_record.0 */
+ /* class_tid: 4, , table: int_full_act_record.0 */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -5295,7 +5295,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 3, , table: port_table.wr_0 */
+ /* class_tid: 4, , table: port_table.wr_0 */
{
.description = "rid",
.field_bit_size = 32,
@@ -5329,7 +5329,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
- /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
.description = "prof_func_id",
.field_bit_size = 7,
@@ -5380,7 +5380,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -5414,7 +5414,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */
+ /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -5424,7 +5424,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
- /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */
+ /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -5434,7 +5434,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
- /* class_tid: 3, , table: int_full_act_record.egr_0 */
+ /* class_tid: 4, , table: int_full_act_record.egr_0 */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -5542,7 +5542,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
.description = "prof_func_id",
.field_bit_size = 7,
@@ -5593,7 +5593,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
},
- /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */
+ /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -5603,7 +5603,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */
+ /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -5613,7 +5613,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 4, , table: int_full_act_record.loopback */
+ /* class_tid: 5, , table: int_full_act_record.loopback */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -5721,7 +5721,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */
+ /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -5731,7 +5731,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
- /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */
+ /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -5741,7 +5741,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
- /* class_tid: 4, , table: int_full_act_record.vf_ing */
+ /* class_tid: 5, , table: int_full_act_record.vf_ing */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -5849,7 +5849,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 4, , table: vtag_encap_record.vfr_egr0 */
+ /* class_tid: 5, , table: vtag_encap_record.vfr_egr0 */
{
.description = "ecv_tun_type",
.field_bit_size = 3,
@@ -5929,7 +5929,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
},
- /* class_tid: 4, , table: int_full_act_record.vfr_egr0 */
+ /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -6085,7 +6085,7 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 29
},
- /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
.description = "l2_cntxt_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -6094,7 +6094,7 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 29
},
- /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
.description = "l2_cntxt_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
index b6d2afd55b..de924fe81a 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 13 18:15:56 2021 */
+/* date: Mon May 17 15:54:03 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
index 85b8950e49..7b6ee03a4b 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Fri May 14 10:26:31 2021 */
+/* date: Mon May 17 15:54:03 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -22,7 +22,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = {
.cond_start_idx = 0,
.cond_nums = 1 }
},
- /* class_tid: 2, egress */
+ /* class_tid: 2, ingress */
[2] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
.num_tbls = 15,
@@ -32,24 +32,34 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = {
.cond_start_idx = 24,
.cond_nums = 1 }
},
- /* class_tid: 3, ingress */
+ /* class_tid: 3, egress */
[3] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .num_tbls = 22,
+ .num_tbls = 15,
.start_tbl_idx = 33,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 30,
+ .cond_nums = 1 }
+ },
+ /* class_tid: 4, ingress */
+ [4] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 22,
+ .start_tbl_idx = 48,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 35,
+ .cond_start_idx = 41,
.cond_nums = 0 }
},
- /* class_tid: 4, egress */
- [4] = {
+ /* class_tid: 5, egress */
+ [5] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
.num_tbls = 19,
- .start_tbl_idx = 55,
+ .start_tbl_idx = 70,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 41,
+ .cond_start_idx = 47,
.cond_nums = 0 }
}
};
@@ -455,58 +465,133 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.result_bit_size = 64,
.result_num_fields = 9
},
- { /* class_tid: 2, , table: l2_cntxt_tcam_cache.rd */
+ { /* class_tid: 2, , table: tunnel_cache.rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 5,
+ .cond_true_goto = 1,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 25,
- .cond_nums = 1 },
+ .cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 223,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
+ .blob_key_bit_size = 16,
+ .key_bit_size = 16,
+ .key_num_fields = 2,
.ident_start_idx = 9,
.ident_nums = 1
},
+ { /* class_tid: 2, , table: control.tunnel_cache_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 25,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ { /* class_tid: 2, , table: l2_cntxt_tcam.1 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 26,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 225,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 127,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .ident_start_idx = 10,
+ .ident_nums = 1
+ },
+ { /* class_tid: 2, , table: tunnel_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 26,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 238,
+ .blob_key_bit_size = 16,
+ .key_bit_size = 16,
+ .key_num_fields = 2,
+ .result_start_idx = 140,
+ .result_bit_size = 52,
+ .result_num_fields = 3
+ },
+ { /* class_tid: 2, , table: control.flow_type_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 5,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 26,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
{ /* class_tid: 2, , table: mac_addr_cache.rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 26,
+ .cond_start_idx = 27,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 224,
+ .key_start_idx = 240,
.blob_key_bit_size = 73,
.key_bit_size = 73,
.key_num_fields = 5,
- .ident_start_idx = 10,
+ .ident_start_idx = 11,
.ident_nums = 1
},
- { /* class_tid: 2, , table: control.0 */
+ { /* class_tid: 2, , table: control.mac_addr_cache_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 3,
+ .cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 26,
+ .cond_start_idx = 27,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
@@ -515,12 +600,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
{ /* class_tid: 2, , table: l2_cntxt_tcam.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 27,
+ .cond_start_idx = 28,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
@@ -529,323 +614,236 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 229,
+ .key_start_idx = 245,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 127,
+ .result_start_idx = 143,
.result_bit_size = 64,
.result_num_fields = 13,
- .ident_start_idx = 11,
- .ident_nums = 1
+ .ident_start_idx = 12,
+ .ident_nums = 0
},
{ /* class_tid: 2, , table: mac_addr_cache.wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 27,
+ .cond_start_idx = 28,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 242,
+ .key_start_idx = 258,
.blob_key_bit_size = 73,
.key_bit_size = 73,
.key_num_fields = 5,
- .result_start_idx = 140,
+ .result_start_idx = 156,
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 2, , table: profile_tcam_cache.rd */
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 27,
+ .cond_start_idx = 28,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 247,
+ .key_start_idx = 263,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
.ident_start_idx = 12,
.ident_nums = 3
},
- { /* class_tid: 2, , table: control.gen_tbl_miss */
+ { /* class_tid: 2, , table: control.profile_tcam_cache.f2_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 2,
- .cond_false_goto = 1,
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 27,
+ .cond_start_idx = 28,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 2, , table: control.conflict_check */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 4,
- .cond_false_goto = 1023,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 28,
- .cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .func_info = {
- .func_opc = BNXT_ULP_FUNC_OPC_EQ,
- .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
- .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
- .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
- .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
- .func_dst_opr = BNXT_ULP_RF_IDX_CC },
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
- },
- { /* class_tid: 2, , table: profile_tcam.ipv4 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 2,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 29,
- .cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 250,
- .blob_key_bit_size = 81,
- .key_bit_size = 81,
- .key_num_fields = 43,
- .result_start_idx = 144,
- .result_bit_size = 38,
- .result_num_fields = 17,
- .ident_start_idx = 15,
- .ident_nums = 1
- },
- { /* class_tid: 2, , table: profile_tcam.ipv6 */
+ { /* class_tid: 2, , table: profile_tcam.f2 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 30,
+ .cond_start_idx = 29,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 1,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 293,
+ .key_start_idx = 266,
.blob_key_bit_size = 81,
.key_bit_size = 81,
.key_num_fields = 43,
- .result_start_idx = 161,
+ .result_start_idx = 160,
.result_bit_size = 38,
- .result_num_fields = 17,
- .ident_start_idx = 16,
- .ident_nums = 1
+ .result_num_fields = 17
},
- { /* class_tid: 2, , table: profile_tcam_cache.wr */
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 30,
+ .cond_start_idx = 29,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 336,
+ .key_start_idx = 309,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
- .result_start_idx = 178,
+ .result_start_idx = 177,
.result_bit_size = 122,
.result_num_fields = 5
},
- { /* class_tid: 2, , table: em.ipv4 */
+ { /* class_tid: 2, , table: em.tun */
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_MEM_INTERNAL,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 0,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 30,
- .cond_nums = 2 },
+ .cond_start_idx = 29,
+ .cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 339,
- .blob_key_bit_size = 176,
- .key_bit_size = 176,
- .key_num_fields = 10,
- .result_start_idx = 183,
+ .key_start_idx = 312,
+ .blob_key_bit_size = 112,
+ .key_bit_size = 112,
+ .key_num_fields = 8,
+ .result_start_idx = 182,
.result_bit_size = 64,
.result_num_fields = 9
},
- { /* class_tid: 2, , table: eem.ipv4 */
+ { /* class_tid: 2, , table: eem.tun */
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_MEM_EXTERNAL,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 0,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 32,
- .cond_nums = 2 },
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 30,
+ .cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 349,
+ .key_start_idx = 320,
.blob_key_bit_size = 448,
.key_bit_size = 448,
- .key_num_fields = 10,
- .result_start_idx = 192,
+ .key_num_fields = 8,
+ .result_start_idx = 191,
.result_bit_size = 64,
.result_num_fields = 9
},
- { /* class_tid: 2, , table: em.ipv6 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
- .resource_type = TF_MEM_INTERNAL,
+ { /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 0,
+ .cond_true_goto = 5,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 34,
+ .cond_start_idx = 31,
.cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 359,
- .blob_key_bit_size = 416,
- .key_bit_size = 416,
- .key_num_fields = 11,
- .result_start_idx = 201,
- .result_bit_size = 64,
- .result_num_fields = 9
+ .key_start_idx = 328,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 15,
+ .ident_nums = 1
},
- { /* class_tid: 2, , table: eem.ipv6 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
- .resource_type = TF_MEM_EXTERNAL,
+ { /* class_tid: 3, , table: mac_addr_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 0,
- .cond_false_goto = 0,
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 35,
+ .cond_start_idx = 32,
.cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 370,
- .blob_key_bit_size = 448,
- .key_bit_size = 448,
- .key_num_fields = 11,
- .result_start_idx = 210,
- .result_bit_size = 64,
- .result_num_fields = 9
+ .key_start_idx = 329,
+ .blob_key_bit_size = 73,
+ .key_bit_size = 73,
+ .key_num_fields = 5,
+ .ident_start_idx = 16,
+ .ident_nums = 1
},
- { /* class_tid: 3, , table: int_full_act_record.ing_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 35,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 219,
- .result_bit_size = 128,
- .result_num_fields = 26
- },
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 35,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 381,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .ident_start_idx = 17,
- .ident_nums = 0
- },
- { /* class_tid: 3, , table: control.ing_0 */
+ { /* class_tid: 3, , table: control.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_RX,
+ .direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 3,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 35,
+ .cond_start_idx = 32,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
+ { /* class_tid: 3, , table: l2_cntxt_tcam.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .direction = TF_DIR_RX,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 36,
+ .cond_start_idx = 33,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
@@ -853,361 +851,240 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 382,
+ .key_start_idx = 334,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 245,
+ .result_start_idx = 200,
.result_bit_size = 64,
.result_num_fields = 13,
.ident_start_idx = 17,
.ident_nums = 1
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */
+ { /* class_tid: 3, , table: mac_addr_cache.wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
- .direction = TF_DIR_RX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
+ .direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 36,
+ .cond_start_idx = 33,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 395,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .result_start_idx = 258,
+ .key_start_idx = 347,
+ .blob_key_bit_size = 73,
+ .key_bit_size = 73,
+ .key_num_fields = 5,
+ .result_start_idx = 213,
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 3, , table: parif_def_lkup_arec_ptr.ing_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 36,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 262,
- .result_bit_size = 32,
- .result_num_fields = 1
- },
- { /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
- .direction = TF_DIR_RX,
+ { /* class_tid: 3, , table: profile_tcam_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 36,
+ .cond_start_idx = 33,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 263,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .key_start_idx = 352,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .ident_start_idx = 18,
+ .ident_nums = 3
},
- { /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
- .direction = TF_DIR_RX,
+ { /* class_tid: 3, , table: control.gen_tbl_miss */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 2,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 36,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 264,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 33,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 3, , table: control.egr_0 */
+ { /* class_tid: 3, , table: control.conflict_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_RX,
+ .direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 6,
+ .cond_true_goto = 4,
+ .cond_false_goto = 1023,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 36,
+ .cond_start_idx = 34,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .func_info = {
+ .func_opc = BNXT_ULP_FUNC_OPC_EQ,
+ .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
+ .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
+ .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC },
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 3, , table: int_full_act_record.egr_vfr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 37,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 265,
- .result_bit_size = 128,
- .result_num_fields = 26,
- .encap_num_fields = 0
- },
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd_vfr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ { /* class_tid: 3, , table: profile_tcam.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 2,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 37,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 396,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .ident_start_idx = 18,
- .ident_nums = 0
- },
- { /* class_tid: 3, , table: control.egr_1 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 37,
+ .cond_start_idx = 35,
.cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 355,
+ .blob_key_bit_size = 81,
+ .key_bit_size = 81,
+ .key_num_fields = 43,
+ .result_start_idx = 217,
+ .result_bit_size = 38,
+ .result_num_fields = 17,
+ .ident_start_idx = 21,
+ .ident_nums = 1
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_bypass.egr_vfr */
+ { /* class_tid: 3, , table: profile_tcam.ipv6 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 38,
+ .cond_start_idx = 36,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
- .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 397,
- .blob_key_bit_size = 167,
- .key_bit_size = 167,
- .key_num_fields = 13,
- .result_start_idx = 291,
- .result_bit_size = 64,
- .result_num_fields = 13,
- .ident_start_idx = 18,
- .ident_nums = 0
+ .key_start_idx = 398,
+ .blob_key_bit_size = 81,
+ .key_bit_size = 81,
+ .key_num_fields = 43,
+ .result_start_idx = 234,
+ .result_bit_size = 38,
+ .result_num_fields = 17,
+ .ident_start_idx = 22,
+ .ident_nums = 1
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
+ { /* class_tid: 3, , table: profile_tcam_cache.wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 0,
+ .cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 38,
+ .cond_start_idx = 36,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 410,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .result_start_idx = 304,
- .result_bit_size = 62,
- .result_num_fields = 4
+ .key_start_idx = 441,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .result_start_idx = 251,
+ .result_bit_size = 122,
+ .result_num_fields = 5
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ { /* class_tid: 3, , table: em.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_INTERNAL,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 38,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 36,
+ .cond_nums = 2 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 411,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .ident_start_idx = 18,
- .ident_nums = 0
- },
- { /* class_tid: 3, , table: control.egr_2 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 3,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 38,
- .cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
- },
- { /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 39,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 412,
- .blob_key_bit_size = 167,
- .key_bit_size = 167,
- .key_num_fields = 13,
- .result_start_idx = 308,
+ .key_start_idx = 444,
+ .blob_key_bit_size = 176,
+ .key_bit_size = 176,
+ .key_num_fields = 10,
+ .result_start_idx = 256,
.result_bit_size = 64,
- .result_num_fields = 13,
- .ident_start_idx = 18,
- .ident_nums = 1
+ .result_num_fields = 9
},
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ { /* class_tid: 3, , table: eem.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_EXTERNAL,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 39,
+ .cond_start_idx = 38,
.cond_nums = 2 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 425,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .result_start_idx = 321,
- .result_bit_size = 62,
- .result_num_fields = 4
- },
- { /* class_tid: 3, , table: int_full_act_record.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 41,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 325,
- .result_bit_size = 128,
- .result_num_fields = 26,
- .encap_num_fields = 0
- },
- { /* class_tid: 3, , table: parif_def_lkup_arec_ptr.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 41,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 351,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .key_start_idx = 454,
+ .blob_key_bit_size = 448,
+ .key_bit_size = 448,
+ .key_num_fields = 10,
+ .result_start_idx = 265,
+ .result_bit_size = 64,
+ .result_num_fields = 9
},
- { /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+ { /* class_tid: 3, , table: em.ipv6 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_INTERNAL,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 41,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 40,
+ .cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 352,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .key_start_idx = 464,
+ .blob_key_bit_size = 416,
+ .key_bit_size = 416,
+ .key_num_fields = 11,
+ .result_start_idx = 274,
+ .result_bit_size = 64,
+ .result_num_fields = 9
},
- { /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
+ { /* class_tid: 3, , table: eem.ipv6 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_EXTERNAL,
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 0,
@@ -1215,41 +1092,44 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 41,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 353,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .key_start_idx = 475,
+ .blob_key_bit_size = 448,
+ .key_bit_size = 448,
+ .key_num_fields = 11,
+ .result_start_idx = 283,
+ .result_bit_size = 64,
+ .result_num_fields = 9
},
- { /* class_tid: 4, , table: int_full_act_record.loopback */
+ { /* class_tid: 4, , table: int_full_act_record.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 41,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE,
- .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 354,
+ .result_start_idx = 292,
.result_bit_size = 128,
- .result_num_fields = 26,
- .encap_num_fields = 0
+ .result_num_fields = 26
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_rd_egr */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
@@ -1260,16 +1140,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 426,
+ .key_start_idx = 486,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .ident_start_idx = 19,
+ .ident_start_idx = 23,
.ident_nums = 0
},
- { /* class_tid: 4, , table: control.vf_0 */
+ { /* class_tid: 4, , table: control.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 3,
@@ -1280,10 +1160,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */
+ { /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
@@ -1296,22 +1176,24 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 427,
+ .key_start_idx = 487,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 380,
+ .result_start_idx = 318,
.result_bit_size = 64,
.result_num_fields = 13,
- .ident_start_idx = 19,
+ .ident_start_idx = 23,
.ident_nums = 1
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
@@ -1322,119 +1204,103 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 440,
+ .key_start_idx = 500,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .result_start_idx = 393,
+ .result_start_idx = 331,
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 4, , table: parif_def_lkup_arec_ptr.vf_egr */
+ { /* class_tid: 4, , table: parif_def_lkup_arec_ptr.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 42,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
- .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 397,
+ .result_start_idx = 335,
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */
+ { /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 42,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
- .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 398,
+ .result_start_idx = 336,
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */
+ { /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 42,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
- .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 399,
+ .result_start_idx = 337,
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 4, , table: int_full_act_record.vf_ing */
+ { /* class_tid: 4, , table: control.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 6,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 42,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ { /* class_tid: 4, , table: int_full_act_record.egr_vfr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_RX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 400,
+ .result_start_idx = 338,
.result_bit_size = 128,
.result_num_fields = 26,
.encap_num_fields = 0
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vf_ing */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
- .pri_operand = 0,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 441,
- .blob_key_bit_size = 167,
- .key_bit_size = 167,
- .key_num_fields = 13,
- .result_start_idx = 426,
- .result_bit_size = 64,
- .result_num_fields = 13,
- .ident_start_idx = 20,
- .ident_nums = 0
- },
- { /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_rd_egr0 */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd_vfr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
@@ -1443,33 +1309,33 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 454,
+ .key_start_idx = 501,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .ident_start_idx = 20,
+ .ident_start_idx = 24,
.ident_nums = 0
},
- { /* class_tid: 4, , table: control.vfr_0 */
+ { /* class_tid: 4, , table: control.egr_1 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 3,
+ .cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_egr0 */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.egr_vfr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.direction = TF_DIR_TX,
@@ -1477,7 +1343,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 43,
+ .cond_start_idx = 44,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
@@ -1486,140 +1352,392 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 455,
+ .key_start_idx = 502,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 439,
+ .result_start_idx = 364,
.result_bit_size = 64,
.result_num_fields = 13,
- .ident_start_idx = 20,
+ .ident_start_idx = 24,
.ident_nums = 0
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 43,
+ .cond_start_idx = 44,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 468,
+ .key_start_idx = 515,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .result_start_idx = 452,
+ .result_start_idx = 377,
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 4, , table: int_vtag_encap_record.vfr_egr0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 43,
+ .cond_start_idx = 44,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 456,
- .result_bit_size = 0,
- .result_num_fields = 0,
- .encap_num_fields = 12
+ .key_start_idx = 516,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 24,
+ .ident_nums = 0
},
- { /* class_tid: 4, , table: int_full_act_record.vfr_egr0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
- .execute_info = {
+ { /* class_tid: 4, , table: control.egr_2 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 44,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .direction = TF_DIR_TX,
+ .execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 43,
+ .cond_start_idx = 45,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 517,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 381,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .ident_start_idx = 24,
+ .ident_nums = 1
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 45,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 530,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 394,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 4, , table: int_full_act_record.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 47,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 468,
+ .result_start_idx = 398,
.result_bit_size = 128,
- .result_num_fields = 26
+ .result_num_fields = 26,
+ .encap_num_fields = 0
+ },
+ { /* class_tid: 4, , table: parif_def_lkup_arec_ptr.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 47,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 424,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 47,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 425,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 47,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 426,
+ .result_bit_size = 32,
+ .result_num_fields = 1
},
- { /* class_tid: 4, , table: int_full_act_record.vfr_ing0 */
+ { /* class_tid: 5, , table: int_full_act_record.loopback */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_RX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 43,
+ .cond_start_idx = 47,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 494,
+ .result_start_idx = 427,
.result_bit_size = 128,
- .result_num_fields = 26
+ .result_num_fields = 26,
+ .encap_num_fields = 0
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 47,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 531,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 25,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: control.vf_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 47,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */
+ { /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .direction = TF_DIR_RX,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 43,
+ .cond_start_idx = 48,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 469,
+ .key_start_idx = 532,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 520,
+ .result_start_idx = 453,
.result_bit_size = 64,
.result_num_fields = 13,
- .ident_start_idx = 20,
- .ident_nums = 0
+ .ident_start_idx = 25,
+ .ident_nums = 1
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 545,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 466,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 5, , table: parif_def_lkup_arec_ptr.vf_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
+ .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 470,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
+ .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 471,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
+ .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 472,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 5, , table: int_full_act_record.vf_ing */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 473,
+ .result_bit_size = 128,
+ .result_num_fields = 26,
+ .encap_num_fields = 0
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */
+ { /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vf_ing */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
.direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 0,
- .cond_false_goto = 0,
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 43,
+ .cond_start_idx = 48,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
@@ -1629,19 +1747,224 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .key_start_idx = 482,
+ .key_start_idx = 546,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 533,
+ .result_start_idx = 499,
.result_bit_size = 64,
.result_num_fields = 13,
- .ident_start_idx = 20,
+ .ident_start_idx = 26,
.ident_nums = 0
- }
-};
-
-struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_rd_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 559,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 26,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: control.vfr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 48,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 560,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 512,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .ident_start_idx = 26,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 573,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 525,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 5, , table: int_vtag_encap_record.vfr_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 529,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 12
+ },
+ { /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 541,
+ .result_bit_size = 128,
+ .result_num_fields = 26
+ },
+ { /* class_tid: 5, , table: int_full_act_record.vfr_ing0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_start_idx = 567,
+ .result_bit_size = 128,
+ .result_num_fields = 26
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 574,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 593,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .ident_start_idx = 26,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_start_idx = 587,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 606,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .ident_start_idx = 26,
+ .ident_nums = 0
+ }
+};
+
+struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {
/* cond_reject: wh_plus, class_tid: 1 */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
@@ -1751,32 +2074,61 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
.cond_operand = BNXT_ULP_CF_IDX_WC_MATCH
},
- /* cond_execute: class_tid: 2, l2_cntxt_tcam_cache.rd */
+ /* cond_execute: class_tid: 2, control.tunnel_cache_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 2, control.flow_type_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_F1
+ },
+ /* cond_execute: class_tid: 2, control.mac_addr_cache_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 2, control.profile_tcam_cache.f2_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 2, em.tun */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET,
+ },
+ /* cond_reject: wh_plus, class_tid: 3 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH
+ },
+ /* cond_execute: class_tid: 3, l2_cntxt_tcam_cache.rd */
{
.cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET,
.cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC
},
- /* cond_execute: class_tid: 2, control.0 */
+ /* cond_execute: class_tid: 3, control.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 2, control.gen_tbl_miss */
+ /* cond_execute: class_tid: 3, control.gen_tbl_miss */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 2, control.conflict_check */
+ /* cond_execute: class_tid: 3, control.conflict_check */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_CC
},
- /* cond_execute: class_tid: 2, profile_tcam.ipv4 */
+ /* cond_execute: class_tid: 3, profile_tcam.ipv4 */
{
.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
},
- /* cond_execute: class_tid: 2, em.ipv4 */
+ /* cond_execute: class_tid: 3, em.ipv4 */
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET,
},
@@ -1784,7 +2136,7 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
},
- /* cond_execute: class_tid: 2, eem.ipv4 */
+ /* cond_execute: class_tid: 3, eem.ipv4 */
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_IS_SET,
},
@@ -1792,31 +2144,31 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
},
- /* cond_execute: class_tid: 2, em.ipv6 */
+ /* cond_execute: class_tid: 3, em.ipv6 */
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET,
},
- /* cond_execute: class_tid: 3, control.ing_0 */
+ /* cond_execute: class_tid: 4, control.ing_0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 3, control.egr_0 */
+ /* cond_execute: class_tid: 4, control.egr_0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
},
- /* cond_execute: class_tid: 3, control.egr_1 */
+ /* cond_execute: class_tid: 4, control.egr_1 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 3, control.egr_2 */
+ /* cond_execute: class_tid: 4, control.egr_2 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 3, l2_cntxt_tcam_cache.egr_wr */
+ /* cond_execute: class_tid: 4, l2_cntxt_tcam_cache.egr_wr */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
@@ -1825,12 +2177,12 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 4, control.vf_0 */
+ /* cond_execute: class_tid: 5, control.vf_0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 4, control.vfr_0 */
+ /* cond_execute: class_tid: 5, control.vfr_0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
@@ -5669,7 +6021,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
}
},
- /* class_tid: 2, , table: l2_cntxt_tcam_cache.rd */
+ /* class_tid: 2, , table: tunnel_cache.rd */
{
.field_info_mask = {
.description = "svif",
@@ -5690,181 +6042,52 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
}
},
- /* class_tid: 2, , table: mac_addr_cache.rd */
{
.field_info_mask = {
- .description = "svif",
+ .description = "tunnel_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ 0xff}
},
.field_info_spec = {
- .description = "svif",
+ .description = "tunnel_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ (BNXT_ULP_CF_IDX_TUNNEL_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_TUNNEL_ID & 0xff}
}
},
+ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
{
.field_info_mask = {
- .description = "tun_hdr",
- .field_bit_size = 4,
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr",
- .field_bit_size = 4,
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "one_tag",
- .field_bit_size = 1,
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "one_tag",
- .field_bit_size = 1,
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
- }
- },
- {
- .field_info_mask = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
- },
- .field_info_spec = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
- }
- },
- /* class_tid: 2, , table: l2_cntxt_tcam.0 */
- {
- .field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -5872,19 +6095,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "mac0_addr",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "mac0_addr",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -5892,19 +6109,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "svif",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "svif",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -5968,18 +6179,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "l2_num_vtags",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l2_num_vtags",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -6046,7 +6252,47 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
1}
}
},
- /* class_tid: 2, , table: mac_addr_cache.wr */
+ /* class_tid: 2, , table: tunnel_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_TUNNEL_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_TUNNEL_ID & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: mac_addr_cache.rd */
{
.field_info_mask = {
.description = "svif",
@@ -6072,17 +6318,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "tun_hdr",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ 0xff}
},
.field_info_spec = {
.description = "tun_hdr",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -6090,60 +6334,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "one_tag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "one_tag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
.description = "vid",
.field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "vid",
.field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -6153,8 +6364,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
},
.field_info_spec = {
.description = "mac_addr",
@@ -6162,204 +6373,166 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
- /* class_tid: 2, , table: profile_tcam_cache.rd */
+ /* class_tid: 2, , table: l2_cntxt_tcam.0 */
{
.field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
+ .description = "mac0_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
+ .description = "mac0_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
- /* class_tid: 2, , table: profile_tcam.ipv4 */
{
.field_info_mask = {
- .description = "l4_hdr_is_udp_tcp",
- .field_bit_size = 1,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
},
.field_info_spec = {
- .description = "l4_hdr_is_udp_tcp",
- .field_bit_size = 1,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
}
},
{
.field_info_mask = {
- .description = "l4_hdr_type",
+ .description = "sparif",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l4_hdr_type",
+ .description = "sparif",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_WP_SYM_L4_HDR_TYPE_TCP},
- .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr3 = {
- ULP_WP_SYM_L4_HDR_TYPE_UDP}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4_hdr_error",
- .field_bit_size = 1,
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l4_hdr_error",
- .field_bit_size = 1,
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4_hdr_valid",
- .field_bit_size = 1,
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l4_hdr_valid",
- .field_bit_size = 1,
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_ipv6_cmp_dst",
- .field_bit_size = 1,
+ .description = "mac1_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_ipv6_cmp_dst",
- .field_bit_size = 1,
+ .description = "mac1_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_hdr_type",
+ .description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
@@ -6367,7 +6540,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "l3_hdr_type",
+ .description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6375,162 +6548,200 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "l3_hdr_error",
- .field_bit_size = 1,
+ .description = "key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_hdr_error",
- .field_bit_size = 1,
+ .description = "key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_hdr_valid",
+ .description = "valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 0xff}
+ 1}
},
.field_info_spec = {
- .description = "l3_hdr_valid",
+ .description = "valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ULP_WP_SYM_L3_HDR_VALID_YES}
+ 1}
}
},
+ /* class_tid: 2, , table: mac_addr_cache.wr */
{
.field_info_mask = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
+ .description = "tun_hdr",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_vtag_present",
+ .description = "one_tag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_vtag_present",
+ .description = "one_tag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_uc_mc_bc",
- .field_bit_size = 2,
+ .description = "vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_uc_mc_bc",
- .field_bit_size = 2,
+ .description = "vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_hdr_type",
- .field_bit_size = 2,
+ .description = "mac_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "l2_hdr_type",
- .field_bit_size = 2,
+ .description = "mac_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
+ /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
{
.field_info_mask = {
- .description = "l2_hdr_error",
- .field_bit_size = 1,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l2_hdr_error",
- .field_bit_size = 1,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_hdr_valid",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l2_hdr_valid",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- ULP_WP_SYM_L2_HDR_VALID_YES}
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "tun_hdr_flags",
- .field_bit_size = 3,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: profile_tcam.f2 */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_flags",
- .field_bit_size = 3,
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
+ .description = "l4_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_type",
+ .description = "l4_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6538,13 +6749,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tun_hdr_err",
+ .description = "l4_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_err",
+ .description = "l4_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6552,15 +6763,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tun_hdr_valid",
+ .description = "l4_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_valid",
+ .description = "l4_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6568,13 +6777,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl4_hdr_is_udp_tcp",
+ .description = "l3_ipv6_cmp_dst",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4_hdr_is_udp_tcp",
+ .description = "l3_ipv6_cmp_dst",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6582,27 +6791,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl4_hdr_type",
- .field_bit_size = 4,
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4_hdr_type",
- .field_bit_size = 4,
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4_hdr_error",
+ .description = "l3_hdr_isIP",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4_hdr_error",
+ .description = "l3_hdr_isIP",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6610,29 +6819,44 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl4_hdr_valid",
- .field_bit_size = 1,
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "tl4_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_WP_SYM_L3_HDR_TYPE_IPV4},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_WP_SYM_L3_HDR_TYPE_IPV6}
}
},
{
.field_info_mask = {
- .description = "tl3_ipv6_cmp_dst",
+ .description = "l3_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3_ipv6_cmp_dst",
+ .description = "l3_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6640,27 +6864,31 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl3_ipv6_cmp_src",
+ .description = "l3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3_ipv6_cmp_src",
+ .description = "l3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_L3_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl3_hdr_isIP",
+ .description = "l2_two_vtags",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3_hdr_isIP",
+ .description = "l2_two_vtags",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6668,57 +6896,55 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl3_hdr_type",
- .field_bit_size = 4,
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3_hdr_type",
- .field_bit_size = 4,
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3_hdr_error",
- .field_bit_size = 1,
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3_hdr_error",
- .field_bit_size = 1,
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3_hdr_valid",
- .field_bit_size = 1,
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3_hdr_valid",
- .field_bit_size = 1,
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_two_vtags",
+ .description = "l2_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_two_vtags",
+ .description = "l2_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6726,13 +6952,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl2_vtag_present",
+ .description = "l2_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_vtag_present",
+ .description = "l2_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6740,35 +6966,37 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl2_uc_mc_bc",
- .field_bit_size = 2,
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_uc_mc_bc",
- .field_bit_size = 2,
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_hdr_type",
- .field_bit_size = 2,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_hdr_type",
- .field_bit_size = 2,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_hdr_valid",
+ .description = "tun_hdr_err",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
@@ -6776,7 +7004,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "tl2_hdr_valid",
+ .description = "tun_hdr_err",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6784,68 +7012,65 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "hrec_next",
+ .description = "tun_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "hrec_next",
+ .description = "tun_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_TUN_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "reserved",
- .field_bit_size = 9,
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "reserved",
- .field_bit_size = 9,
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ ULP_WP_SYM_TL4_HDR_TYPE_UDP}
}
},
{
.field_info_mask = {
- .description = "agg_error",
+ .description = "tl4_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "agg_error",
+ .description = "tl4_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -6853,159 +7078,137 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_TL4_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "pkt_type_0",
- .field_bit_size = 2,
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "pkt_type_0",
- .field_bit_size = 2,
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "pkt_type_1",
- .field_bit_size = 2,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "pkt_type_1",
- .field_bit_size = 2,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "valid",
+ .description = "tl3_hdr_isIP",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "valid",
+ .description = "tl3_hdr_isIP",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 2, , table: profile_tcam.ipv6 */
{
.field_info_mask = {
- .description = "l4_hdr_is_udp_tcp",
- .field_bit_size = 1,
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "l4_hdr_is_udp_tcp",
- .field_bit_size = 1,
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ 0xff}
},
.field_info_spec = {
- .description = "l4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_WP_SYM_L4_HDR_TYPE_TCP},
- .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr3 = {
- ULP_WP_SYM_L4_HDR_TYPE_UDP}
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4_hdr_error",
+ .description = "tl3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ 0xff}
},
.field_info_spec = {
- .description = "l4_hdr_error",
+ .description = "tl3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_TL3_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "l4_hdr_valid",
+ .description = "tl2_two_vtags",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l4_hdr_valid",
+ .description = "tl2_two_vtags",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_ipv6_cmp_dst",
+ .description = "tl2_vtag_present",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_ipv6_cmp_dst",
+ .description = "tl2_vtag_present",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -7013,61 +7216,61 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_hdr_type",
- .field_bit_size = 4,
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l3_hdr_type",
- .field_bit_size = 4,
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ULP_WP_SYM_L3_HDR_TYPE_IPV6}
+ ULP_WP_SYM_TL2_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "l3_hdr_error",
+ .description = "hrec_next",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_hdr_error",
+ .description = "hrec_next",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -7075,68 +7278,60 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "l3_hdr_valid",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_hdr_valid",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_L3_HDR_VALID_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "l2_vtag_present",
+ .description = "agg_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_vtag_present",
+ .description = "agg_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_uc_mc_bc",
+ .description = "recycle_cnt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_uc_mc_bc",
+ .description = "recycle_cnt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -7144,15 +7339,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "l2_hdr_type",
+ .description = "pkt_type_0",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_hdr_type",
+ .description = "pkt_type_0",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -7160,1487 +7353,1459 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "l2_hdr_error",
- .field_bit_size = 1,
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_hdr_error",
- .field_bit_size = 1,
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_hdr_valid",
+ .description = "valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 0xff}
+ 1}
},
.field_info_spec = {
- .description = "l2_hdr_valid",
+ .description = "valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ULP_WP_SYM_L2_HDR_VALID_YES}
+ 1}
}
},
+ /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
{
.field_info_mask = {
- .description = "tun_hdr_flags",
- .field_bit_size = 3,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tun_hdr_flags",
- .field_bit_size = 3,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "tun_hdr_err",
- .field_bit_size = 1,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tun_hdr_err",
- .field_bit_size = 1,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
}
},
+ /* class_tid: 2, , table: em.tun */
{
.field_info_mask = {
- .description = "tun_hdr_valid",
- .field_bit_size = 1,
+ .description = "spare",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_valid",
- .field_bit_size = 1,
+ .description = "spare",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4_hdr_is_udp_tcp",
- .field_bit_size = 1,
+ .description = "l2.ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4_hdr_is_udp_tcp",
- .field_bit_size = 1,
+ .description = "l2.ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2.dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "tl4_hdr_type",
- .field_bit_size = 4,
+ .description = "l2.dmac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl4_hdr_error",
- .field_bit_size = 1,
+ .description = "tun_id",
+ .field_bit_size = 24,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}
},
.field_info_spec = {
- .description = "tl4_hdr_error",
- .field_bit_size = 1,
+ .description = "tun_id",
+ .field_bit_size = 24,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl4_hdr_valid",
- .field_bit_size = 1,
+ .description = "tun_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4_hdr_valid",
- .field_bit_size = 1,
+ .description = "tun_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3_ipv6_cmp_dst",
- .field_bit_size = 1,
+ .description = "tun_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3_ipv6_cmp_dst",
- .field_bit_size = 1,
+ .description = "tun_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3_ipv6_cmp_src",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "tl3_ipv6_cmp_src",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl3_hdr_isIP",
- .field_bit_size = 1,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3_hdr_isIP",
- .field_bit_size = 1,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
}
},
+ /* class_tid: 2, , table: eem.tun */
{
.field_info_mask = {
- .description = "tl3_hdr_type",
- .field_bit_size = 4,
+ .description = "spare",
+ .field_bit_size = 339,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3_hdr_type",
- .field_bit_size = 4,
+ .description = "spare",
+ .field_bit_size = 339,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3_hdr_error",
- .field_bit_size = 1,
+ .description = "l2.ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3_hdr_error",
- .field_bit_size = 1,
+ .description = "l2.ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3_hdr_valid",
- .field_bit_size = 1,
+ .description = "l2.dmac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "tl3_hdr_valid",
- .field_bit_size = 1,
+ .description = "l2.dmac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl2_two_vtags",
- .field_bit_size = 1,
+ .description = "tun_id",
+ .field_bit_size = 24,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}
},
.field_info_spec = {
- .description = "tl2_two_vtags",
- .field_bit_size = 1,
+ .description = "tun_id",
+ .field_bit_size = 24,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl2_vtag_present",
- .field_bit_size = 1,
+ .description = "tun_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_vtag_present",
- .field_bit_size = 1,
+ .description = "tun_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_uc_mc_bc",
- .field_bit_size = 2,
+ .description = "tun_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_uc_mc_bc",
- .field_bit_size = 2,
+ .description = "tun_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_hdr_type",
- .field_bit_size = 2,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_hdr_type",
- .field_bit_size = 2,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl2_hdr_valid",
- .field_bit_size = 1,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "tl2_hdr_valid",
- .field_bit_size = 1,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
}
},
+ /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
{
.field_info_mask = {
- .description = "hrec_next",
- .field_bit_size = 1,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
},
.field_info_spec = {
- .description = "hrec_next",
- .field_bit_size = 1,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
}
},
+ /* class_tid: 3, , table: mac_addr_cache.rd */
{
.field_info_mask = {
- .description = "reserved",
- .field_bit_size = 9,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
},
.field_info_spec = {
- .description = "reserved",
- .field_bit_size = 9,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
}
},
{
.field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "tun_hdr",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 0xff}
+ ULP_WP_SYM_TUN_HDR_TYPE_NONE}
},
.field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ ULP_WP_SYM_TUN_HDR_TYPE_NONE}
}
},
{
.field_info_mask = {
- .description = "agg_error",
+ .description = "one_tag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "agg_error",
+ .description = "one_tag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
}
},
{
.field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "pkt_type_0",
- .field_bit_size = 2,
+ .description = "mac_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
},
.field_info_spec = {
- .description = "pkt_type_0",
- .field_bit_size = 2,
+ .description = "mac_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
}
},
+ /* class_tid: 3, , table: l2_cntxt_tcam.0 */
{
.field_info_mask = {
- .description = "pkt_type_1",
- .field_bit_size = 2,
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "pkt_type_1",
- .field_bit_size = 2,
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
+ .description = "mac0_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
},
.field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
+ .description = "mac0_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
}
},
- /* class_tid: 2, , table: profile_tcam_cache.wr */
{
.field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 0xff}
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
},
.field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
}
},
{
.field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "sparif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 2, , table: em.ipv4 */
{
.field_info_mask = {
- .description = "spare",
- .field_bit_size = 3,
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "spare",
- .field_bit_size = 3,
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "mac1_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "mac1_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4.dst",
- .field_bit_size = 16,
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff}
}
},
{
.field_info_mask = {
- .description = "l4.src",
- .field_bit_size = 16,
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3.prot",
- .field_bit_size = 8,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 0xff}
+ ULP_WP_SYM_TUN_HDR_TYPE_NONE}
},
.field_info_spec = {
- .description = "l3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ ULP_WP_SYM_TUN_HDR_TYPE_NONE}
}
},
{
.field_info_mask = {
- .description = "l3.dst",
- .field_bit_size = 32,
+ .description = "key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3.dst",
- .field_bit_size = 32,
+ .description = "key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3.src",
- .field_bit_size = 32,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ 1}
},
.field_info_spec = {
- .description = "l3.src",
- .field_bit_size = 32,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ 1}
}
},
+ /* class_tid: 3, , table: mac_addr_cache.wr */
{
.field_info_mask = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
},
.field_info_spec = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
}
},
{
.field_info_mask = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "tun_hdr",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 0xff,
- 0xff}
+ ULP_WP_SYM_TUN_HDR_TYPE_NONE}
},
.field_info_spec = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "tun_hdr",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ ULP_WP_SYM_TUN_HDR_TYPE_NONE}
}
},
{
.field_info_mask = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "one_tag",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "one_tag",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
}
},
- /* class_tid: 2, , table: eem.ipv4 */
{
.field_info_mask = {
- .description = "spare",
- .field_bit_size = 275,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "spare",
- .field_bit_size = 275,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "mac_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
},
.field_info_spec = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "mac_addr",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
}
},
+ /* class_tid: 3, , table: profile_tcam_cache.rd */
{
.field_info_mask = {
- .description = "l4.dst",
- .field_bit_size = 16,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4.src",
- .field_bit_size = 16,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l4.src",
- .field_bit_size = 16,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "l3.prot",
- .field_bit_size = 8,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
}
},
+ /* class_tid: 3, , table: profile_tcam.ipv4 */
{
.field_info_mask = {
- .description = "l3.dst",
- .field_bit_size = 32,
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3.dst",
- .field_bit_size = 32,
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3.src",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3.src",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_WP_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_WP_SYM_L4_HDR_TYPE_UDP}
}
},
{
.field_info_mask = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
},
.field_info_spec = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 0xff,
- 0xff}
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
},
.field_info_spec = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
}
},
{
.field_info_mask = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 2, , table: em.ipv6 */
{
.field_info_mask = {
- .description = "spare",
- .field_bit_size = 3,
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "spare",
- .field_bit_size = 3,
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4.dst",
- .field_bit_size = 16,
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4.src",
- .field_bit_size = 16,
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3.prot",
- .field_bit_size = 8,
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ ULP_WP_SYM_L3_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "l3.dst",
- .field_bit_size = 128,
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ 0xff}
},
.field_info_spec = {
- .description = "l3.dst",
- .field_bit_size = 128,
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3.src",
- .field_bit_size = 128,
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ 0xff}
},
.field_info_spec = {
- .description = "l3.src",
- .field_bit_size = 128,
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
}
},
{
.field_info_mask = {
- .description = "l2.smac",
- .field_bit_size = 48,
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "l2.smac",
- .field_bit_size = 48,
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ 0xff}
},
.field_info_spec = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ ULP_WP_SYM_L2_HDR_VALID_YES}
}
},
- /* class_tid: 2, , table: eem.ipv6 */
{
.field_info_mask = {
- .description = "spare",
- .field_bit_size = 35,
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "spare",
- .field_bit_size = 35,
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "local_cos",
- .field_bit_size = 3,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4.dst",
- .field_bit_size = 16,
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l4.src",
- .field_bit_size = 16,
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3.prot",
- .field_bit_size = 8,
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "l3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr2 = {
- (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l3.dst",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
- },
- .field_info_spec = {
- .description = "l3.dst",
- .field_bit_size = 128,
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3.src",
- .field_bit_size = 128,
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3.src",
- .field_bit_size = 128,
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2.smac",
- .field_bit_size = 48,
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2.smac",
- .field_bit_size = 48,
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2.dmac",
- .field_bit_size = 48,
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l2_num_vtags",
+ .description = "tl2_hdr_type",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_num_vtags",
+ .description = "tl2_hdr_type",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -8648,491 +8813,511 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "hrec_next",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "hrec_next",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "reserved",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "reserved",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- .field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- }
- },
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */
- {
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd_vfr */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "agg_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "agg_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_bypass.egr_vfr */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 0xff}
+ 1}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ 1}
}
},
+ /* class_tid: 3, , table: profile_tcam.ipv6 */
{
.field_info_mask = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_WP_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_WP_SYM_L4_HDR_TYPE_UDP}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
},
.field_info_spec = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
},
.field_info_spec = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
}
},
{
.field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
+ .description = "l3_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tun_hdr_type",
+ .description = "l3_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_L3_HDR_TYPE_IPV6}
}
},
{
.field_info_mask = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "valid",
+ .description = "l3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 1}
+ 0xff}
},
.field_info_spec = {
- .description = "valid",
+ .description = "l3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ ULP_WP_SYM_L3_HDR_VALID_YES}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
- }
- },
- {
- .field_info_mask = {
- .description = "sparif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "sparif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ ULP_WP_SYM_L2_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
+ .description = "tl4_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_type",
+ .description = "tl4_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -9140,203 +9325,171 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "valid",
+ .description = "tl4_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 1}
+ 0xff}
},
.field_info_spec = {
- .description = "valid",
+ .description = "tl4_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_rd_egr */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "sparif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_num_vtags",
+ .description = "tl2_hdr_type",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_num_vtags",
+ .description = "tl2_hdr_type",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -9344,280 +9497,294 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
{
.field_info_mask = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "hrec_next",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "hrec_next",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "reserved",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "reserved",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 1}
+ 0xff}
},
.field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_egr_wr */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "agg_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "agg_error",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vf_ing */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 0xff}
+ 1}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ 1}
}
},
+ /* class_tid: 3, , table: profile_tcam_cache.wr */
{
.field_info_mask = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
}
},
+ /* class_tid: 3, , table: em.ipv4 */
{
.field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "spare",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "spare",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "local_cos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "local_cos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "l4.dst",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "l4.src",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "key_type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "key_type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- .field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_rd_egr0 */
{
.field_info_mask = {
- .description = "svif",
+ .description = "l3.prot",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
@@ -9625,211 +9792,305 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "svif",
+ .description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_egr0 */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l3.dst",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l3.dst",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l3.src",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l3.src",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
+ .description = "l2.dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "mac0_addr",
+ .description = "l2.dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
+ 0xff,
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
}
},
{
.field_info_mask = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
}
},
+ /* class_tid: 3, , table: eem.ipv4 */
{
.field_info_mask = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "spare",
+ .field_bit_size = 275,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "spare",
+ .field_bit_size = 275,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "local_cos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "local_cos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
+ .description = "l4.dst",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "l4.src",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "l3.prot",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "l3.dst",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
},
.field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "l3.dst",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
}
},
{
.field_info_mask = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "l3.src",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
},
.field_info_spec = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "l3.src",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
}
},
{
.field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
+ .description = "l2.dmac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
+ .description = "l2.dmac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
{
.field_info_mask = {
- .description = "svif",
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "em_profile_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
@@ -9837,34 +10098,48 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "svif",
+ .description = "em_profile_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */
+ /* class_tid: 3, , table: em.ipv6 */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "spare",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "spare",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "local_cos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "local_cos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
@@ -9872,32 +10147,48 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
+ .description = "l4.src",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "svif",
+ .description = "l3.prot",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
@@ -9905,154 +10196,314 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "svif",
+ .description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "l3.dst",
+ .field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
},
.field_info_spec = {
- .description = "sparif",
- .field_bit_size = 4,
+ .description = "l3.dst",
+ .field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l3.src",
+ .field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
},
.field_info_spec = {
- .description = "tl2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l3.src",
+ .field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l2.smac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovlan_vid",
- .field_bit_size = 12,
+ .description = "l2.smac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mac1_addr",
+ .description = "l2.dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "mac1_addr",
+ .description = "l2.dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
{
.field_info_mask = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
+ 0xff,
0xff}
},
.field_info_spec = {
- .description = "l2_num_vtags",
- .field_bit_size = 2,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- 2}
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_num_vtags",
- .field_bit_size = 2,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
}
},
+ /* class_tid: 3, , table: eem.ipv6 */
{
.field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "spare",
+ .field_bit_size = 35,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
+ .description = "spare",
+ .field_bit_size = 35,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "local_cos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "key_type",
- .field_bit_size = 2,
+ .description = "local_cos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
+ .description = "l4.dst",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 1}
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 1}
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dst",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3.dst",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.src",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3.src",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2.smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2.smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2.dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2.dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
@@ -10060,13 +10511,67 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -10112,8 +10617,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
}
},
{
@@ -10177,17 +10682,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "l2_num_vtags",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l2_num_vtags",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -10249,529 +10750,2581 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.field_opr1 = {
1}
}
- }
-};
-
-struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
- /* class_tid: 1, , table: l2_cntxt_tcam.0 */
- {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
{
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ }
},
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd_vfr */
{
- .description = "l2_byp_lkup_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_bypass.egr_vfr */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vf_ing */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_rd_egr0 */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_egr0 */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 2}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "sparif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_num_vtags",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ }
+};
+
+struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
+ /* class_tid: 1, , table: l2_cntxt_tcam.0 */
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}
+ },
+ {
+ .description = "l2_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ },
+ {
+ .description = "allowed_pri",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "default_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "allowed_tpid",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "default_tpid",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "bd_act_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "byp_sp_lkup",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "pri_anti_spoof_ctl",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tpid_anti_spoof_ctl",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: mac_addr_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.ipv4 */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.0",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_mask.1",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ },
+ {
+ .description = "em_key_mask.2",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ },
+ {
+ .description = "em_key_mask.3",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ },
+ {
+ .description = "em_key_mask.4",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}
+ },
+ {
+ .description = "em_key_mask.5",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}
+ },
+ {
+ .description = "em_key_mask.6",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}
+ },
+ {
+ .description = "em_key_mask.7",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.8",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.9",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.ipv6 */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.0",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_mask.1",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.2",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ },
+ {
+ .description = "em_key_mask.3",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
},
{
- .description = "parif",
+ .description = "em_key_mask.4",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ },
+ {
+ .description = "em_key_mask.5",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}
+ },
+ {
+ .description = "em_key_mask.6",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}
+ },
+ {
+ .description = "em_key_mask.7",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}
+ },
+ {
+ .description = "em_key_mask.8",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.9",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 7}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.ipv4_vxlan */
+ {
+ .description = "wc_key_id",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.0",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_mask.1",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.2",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.3",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.4",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_mask.5",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_mask.6",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_mask.7",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.8",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_mask.9",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 20}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
+ /* class_tid: 1, , table: em.ipv4 */
{
- .description = "allowed_pri",
- .field_bit_size = 8,
+ .description = "act_rec_ptr",
+ .field_bit_size = 33,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "default_pri",
- .field_bit_size = 3,
+ .description = "ext_flow_cntr",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "allowed_tpid",
- .field_bit_size = 6,
+ .description = "act_rec_int",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "default_tpid",
- .field_bit_size = 3,
+ .description = "act_rec_size",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "bd_act_en",
- .field_bit_size = 1,
+ .description = "key_size",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
+ .description = "reserved",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "byp_sp_lkup",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ 3}
},
{
- .description = "pri_anti_spoof_ctl",
- .field_bit_size = 2,
+ .description = "l1_cacheable",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tpid_anti_spoof_ctl",
- .field_bit_size = 2,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
- /* class_tid: 1, , table: mac_addr_cache.wr */
+ /* class_tid: 1, , table: eem.ipv4 */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "act_rec_ptr",
+ .field_bit_size = 33,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "l2_cntxt_tcam_index",
- .field_bit_size = 10,
+ .description = "ext_flow_cntr",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "act_rec_int",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "act_rec_size",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "key_size",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ (173 >> 8) & 0xff,
+ 173 & 0xff}
},
- /* class_tid: 1, , table: profile_tcam.ipv4 */
{
- .description = "wc_key_id",
- .field_bit_size = 4,
+ .description = "reserved",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
},
{
- .description = "wc_search_en",
+ .description = "l1_cacheable",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.0",
+ .description = "valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 1, , table: em.ipv6 */
{
- .description = "em_key_mask.1",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 33,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "em_key_mask.2",
+ .description = "ext_flow_cntr",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.3",
+ .description = "act_rec_int",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.4",
- .field_bit_size = 1,
+ .description = "act_rec_size",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "key_size",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}
+ 3}
},
{
- .description = "em_key_mask.5",
+ .description = "l1_cacheable",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.6",
+ .description = "valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}
+ 1}
},
+ /* class_tid: 1, , table: eem.ipv6 */
{
- .description = "em_key_mask.7",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 33,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "em_key_mask.8",
+ .description = "ext_flow_cntr",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.9",
+ .description = "act_rec_int",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
+ .description = "act_rec_size",
.field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- 3}
+ (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "key_size",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ (413 >> 8) & 0xff,
+ 413 & 0xff}
},
{
- .description = "em_search_en",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ 3}
},
{
- .description = "pl_byp_lkup_en",
+ .description = "l1_cacheable",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam.ipv6 */
{
- .description = "wc_key_id",
- .field_bit_size = 4,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 1, , table: em.vxlan */
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "act_rec_ptr",
+ .field_bit_size = 33,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "wc_search_en",
+ .description = "ext_flow_cntr",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.0",
+ .description = "act_rec_int",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.1",
- .field_bit_size = 1,
+ .description = "act_rec_size",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.2",
- .field_bit_size = 1,
+ .description = "key_size",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.3",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.4",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ 3}
},
{
- .description = "em_key_mask.5",
+ .description = "l1_cacheable",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.6",
+ .description = "valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}
+ 1}
},
+ /* class_tid: 1, , table: eem.vxlan */
{
- .description = "em_key_mask.7",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .description = "act_rec_ptr",
+ .field_bit_size = 33,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "em_key_mask.8",
+ .description = "ext_flow_cntr",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.9",
+ .description = "act_rec_int",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
+ .description = "act_rec_size",
.field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 7}
- },
- {
- .description = "em_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}
},
{
- .description = "em_search_en",
- .field_bit_size = 1,
+ .description = "key_size",
+ .field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
- },
- {
- .description = "pl_byp_lkup_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (197 >> 8) & 0xff,
+ 197 & 0xff}
},
- /* class_tid: 1, , table: profile_tcam.ipv4_vxlan */
{
- .description = "wc_key_id",
- .field_bit_size = 4,
+ .description = "reserved",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
},
{
- .description = "wc_search_en",
+ .description = "l1_cacheable",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.0",
+ .description = "valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
{
- .description = "em_key_mask.1",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.2",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.3",
+ .description = "l2_byp_lkup_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.4",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.5",
- .field_bit_size = 1,
+ .description = "allowed_pri",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.6",
- .field_bit_size = 1,
+ .description = "default_pri",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.7",
- .field_bit_size = 1,
+ .description = "allowed_tpid",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.8",
- .field_bit_size = 1,
+ .description = "default_tpid",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_mask.9",
+ .description = "bd_act_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 20}
- },
- {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_search_en",
+ .description = "byp_sp_lkup",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -10779,12 +13332,18 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
1}
},
{
- .description = "pl_byp_lkup_en",
- .field_bit_size = 1,
+ .description = "pri_anti_spoof_ctl",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam_cache.wr */
+ {
+ .description = "tpid_anti_spoof_ctl",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 2, , table: tunnel_cache.wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -10795,299 +13354,303 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "profile_tcam_index",
+ .description = "l2_cntxt_tcam_index",
.field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
- },
- {
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
+ /* class_tid: 2, , table: l2_cntxt_tcam.0 */
{
- .description = "flow_sig_id",
- .field_bit_size = 64,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
- /* class_tid: 1, , table: em.ipv4 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 33,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
},
{
- .description = "ext_flow_cntr",
+ .description = "l2_byp_lkup_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "act_rec_int",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ },
+ {
+ .description = "allowed_pri",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "act_rec_size",
- .field_bit_size = 5,
+ .description = "default_pri",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "key_size",
- .field_bit_size = 9,
+ .description = "allowed_tpid",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "reserved",
- .field_bit_size = 11,
+ .description = "default_tpid",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "bd_act_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 3}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l1_cacheable",
- .field_bit_size = 1,
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "valid",
+ .description = "byp_sp_lkup",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
- /* class_tid: 1, , table: eem.ipv4 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 33,
+ .description = "pri_anti_spoof_ctl",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ext_flow_cntr",
- .field_bit_size = 1,
+ .description = "tpid_anti_spoof_ctl",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 2, , table: mac_addr_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
{
- .description = "act_rec_int",
- .field_bit_size = 1,
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "act_rec_size",
- .field_bit_size = 5,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,
- BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .description = "key_size",
- .field_bit_size = 9,
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- (173 >> 8) & 0xff,
- 173 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 2, , table: profile_tcam.f2 */
{
- .description = "reserved",
- .field_bit_size = 11,
+ .description = "wc_key_id",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 3}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l1_cacheable",
+ .description = "wc_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "valid",
+ .description = "em_key_mask.0",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
- /* class_tid: 1, , table: em.ipv6 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 33,
+ .description = "em_key_mask.1",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ 1}
},
{
- .description = "ext_flow_cntr",
+ .description = "em_key_mask.2",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "act_rec_int",
+ .description = "em_key_mask.3",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "act_rec_size",
- .field_bit_size = 5,
+ .description = "em_key_mask.4",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "key_size",
- .field_bit_size = 9,
+ .description = "em_key_mask.5",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "reserved",
- .field_bit_size = 11,
+ .description = "em_key_mask.6",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "em_key_mask.7",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 3}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l1_cacheable",
+ .description = "em_key_mask.8",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "valid",
+ .description = "em_key_mask.9",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ 8}
},
- /* class_tid: 1, , table: eem.ipv6 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 33,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
},
{
- .description = "ext_flow_cntr",
+ .description = "em_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "act_rec_int",
+ .description = "pl_byp_lkup_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
{
- .description = "act_rec_size",
- .field_bit_size = 5,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,
- BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "key_size",
- .field_bit_size = 9,
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (413 >> 8) & 0xff,
- 413 & 0xff}
- },
- {
- .description = "reserved",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- 3}
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
},
{
- .description = "l1_cacheable",
- .field_bit_size = 1,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "valid",
- .field_bit_size = 1,
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
- /* class_tid: 1, , table: em.vxlan */
+ /* class_tid: 2, , table: em.tun */
{
.description = "act_rec_ptr",
.field_bit_size = 33,
@@ -11149,7 +13712,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 1, , table: eem.vxlan */
+ /* class_tid: 2, , table: eem.tun */
{
.description = "act_rec_ptr",
.field_bit_size = 33,
@@ -11186,8 +13749,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (197 >> 8) & 0xff,
- 197 & 0xff}
+ (109 >> 8) & 0xff,
+ 109 & 0xff}
},
{
.description = "reserved",
@@ -11217,7 +13780,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 2, , table: l2_cntxt_tcam.0 */
+ /* class_tid: 3, , table: l2_cntxt_tcam.0 */
{
.description = "l2_cntxt_id",
.field_bit_size = 10,
@@ -11317,7 +13880,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: mac_addr_cache.wr */
+ /* class_tid: 3, , table: mac_addr_cache.wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -11351,7 +13914,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: profile_tcam.ipv4 */
+ /* class_tid: 3, , table: profile_tcam.ipv4 */
{
.description = "wc_key_id",
.field_bit_size = 4,
@@ -11497,7 +14060,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: profile_tcam.ipv6 */
+ /* class_tid: 3, , table: profile_tcam.ipv6 */
{
.description = "wc_key_id",
.field_bit_size = 4,
@@ -11643,7 +14206,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: profile_tcam_cache.wr */
+ /* class_tid: 3, , table: profile_tcam_cache.wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -11686,7 +14249,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
- /* class_tid: 2, , table: em.ipv4 */
+ /* class_tid: 3, , table: em.ipv4 */
{
.description = "act_rec_ptr",
.field_bit_size = 33,
@@ -11748,7 +14311,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 2, , table: eem.ipv4 */
+ /* class_tid: 3, , table: eem.ipv4 */
{
.description = "act_rec_ptr",
.field_bit_size = 33,
@@ -11816,7 +14379,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 2, , table: em.ipv6 */
+ /* class_tid: 3, , table: em.ipv6 */
{
.description = "act_rec_ptr",
.field_bit_size = 33,
@@ -11878,7 +14441,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 2, , table: eem.ipv6 */
+ /* class_tid: 3, , table: eem.ipv6 */
{
.description = "act_rec_ptr",
.field_bit_size = 33,
@@ -11946,7 +14509,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 3, , table: int_full_act_record.ing_0 */
+ /* class_tid: 4, , table: int_full_act_record.ing_0 */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -12106,7 +14669,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
.description = "l2_cntxt_id",
.field_bit_size = 10,
@@ -12196,7 +14759,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -12230,7 +14793,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: parif_def_lkup_arec_ptr.ing_0 */
+ /* class_tid: 4, , table: parif_def_lkup_arec_ptr.ing_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -12240,7 +14803,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */
+ /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -12250,7 +14813,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */
+ /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -12260,7 +14823,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 3, , table: int_full_act_record.egr_vfr */
+ /* class_tid: 4, , table: int_full_act_record.egr_vfr */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -12420,7 +14983,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: l2_cntxt_tcam_bypass.egr_vfr */
+ /* class_tid: 4, , table: l2_cntxt_tcam_bypass.egr_vfr */
{
.description = "act_record_ptr",
.field_bit_size = 16,
@@ -12508,7 +15071,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
{
.description = "rid",
.field_bit_size = 32,
@@ -12539,7 +15102,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
.description = "l2_cntxt_id",
.field_bit_size = 10,
@@ -12629,7 +15192,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -12663,7 +15226,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: int_full_act_record.egr_0 */
+ /* class_tid: 4, , table: int_full_act_record.egr_0 */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -12823,7 +15386,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: parif_def_lkup_arec_ptr.egr_0 */
+ /* class_tid: 4, , table: parif_def_lkup_arec_ptr.egr_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -12833,7 +15396,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */
+ /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -12843,7 +15406,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */
+ /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -12853,7 +15416,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
- /* class_tid: 4, , table: int_full_act_record.loopback */
+ /* class_tid: 5, , table: int_full_act_record.loopback */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -13013,7 +15576,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
{
.description = "l2_cntxt_id",
.field_bit_size = 10,
@@ -13102,7 +15665,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -13136,7 +15699,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: parif_def_lkup_arec_ptr.vf_egr */
+ /* class_tid: 5, , table: parif_def_lkup_arec_ptr.vf_egr */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -13146,7 +15709,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
- /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */
+ /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -13156,7 +15719,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
- /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */
+ /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@@ -13166,7 +15729,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
- /* class_tid: 4, , table: int_full_act_record.vf_ing */
+ /* class_tid: 5, , table: int_full_act_record.vf_ing */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -13326,7 +15889,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vf_ing */
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vf_ing */
{
.description = "act_record_ptr",
.field_bit_size = 16,
@@ -13412,7 +15975,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_egr0 */
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_egr0 */
{
.description = "act_record_ptr",
.field_bit_size = 16,
@@ -13497,7 +16060,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
{
.description = "rid",
.field_bit_size = 32,
@@ -13528,7 +16091,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: int_vtag_encap_record.vfr_egr0 */
+ /* class_tid: 5, , table: int_vtag_encap_record.vfr_egr0 */
{
.description = "ecv_tun_type",
.field_bit_size = 3,
@@ -13611,7 +16174,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: int_full_act_record.vfr_egr0 */
+ /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -13774,7 +16337,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: int_full_act_record.vfr_ing0 */
+ /* class_tid: 5, , table: int_full_act_record.vfr_ing0 */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -13936,7 +16499,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */
{
.description = "act_record_ptr",
.field_bit_size = 16,
@@ -14022,7 +16585,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */
+ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */
{
.description = "act_record_ptr",
.field_bit_size = 16,
@@ -14180,13 +16743,22 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 8,
.ident_bit_pos = 28
},
- /* class_tid: 2, , table: l2_cntxt_tcam_cache.rd */
+ /* class_tid: 2, , table: tunnel_cache.rd */
{
.description = "l2_cntxt_id",
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 42
},
+ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
+ {
+ .description = "l2_cntxt_id",
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 0
+ },
/* class_tid: 2, , table: mac_addr_cache.rd */
{
.description = "l2_cntxt_id",
@@ -14194,7 +16766,40 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 42
},
- /* class_tid: 2, , table: l2_cntxt_tcam.0 */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
+ {
+ .description = "em_profile_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 42
+ },
+ {
+ .description = "flow_sig_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .ident_bit_size = 64,
+ .ident_bit_pos = 58
+ },
+ {
+ .description = "profile_tcam_index",
+ .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ {
+ .description = "l2_cntxt_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 42
+ },
+ /* class_tid: 3, , table: mac_addr_cache.rd */
+ {
+ .description = "l2_cntxt_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 42
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam.0 */
{
.description = "l2_cntxt_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -14203,7 +16808,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 0
},
- /* class_tid: 2, , table: profile_tcam_cache.rd */
+ /* class_tid: 3, , table: profile_tcam_cache.rd */
{
.description = "em_profile_id",
.regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
@@ -14222,7 +16827,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 32
},
- /* class_tid: 2, , table: profile_tcam.ipv4 */
+ /* class_tid: 3, , table: profile_tcam.ipv4 */
{
.description = "em_profile_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -14231,7 +16836,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 8,
.ident_bit_pos = 28
},
- /* class_tid: 2, , table: profile_tcam.ipv6 */
+ /* class_tid: 3, , table: profile_tcam.ipv6 */
{
.description = "em_profile_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -14240,7 +16845,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 8,
.ident_bit_pos = 28
},
- /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
.description = "l2_cntxt_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -14249,7 +16854,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 0
},
- /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
.description = "l2_cntxt_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -14258,7 +16863,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 0
},
- /* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
{
.description = "l2_cntxt_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
index 22c51976ac..d6b4f93d31 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
@@ -413,11 +413,13 @@ static int ulp_get_single_flow_stat(struct bnxt_ulp_context *ctxt,
}
/* Update the parent counters if it is child flow */
- if (sw_acc_tbl_entry->parent_flow_id) {
+ if (sw_acc_tbl_entry->pc_flow_idx & FLOW_CNTR_PC_FLOW_VALID) {
+ uint32_t pc_idx;
+
/* Update the parent counters */
t_sw = sw_acc_tbl_entry;
- if (ulp_flow_db_parent_flow_count_update(ctxt,
- t_sw->parent_flow_id,
+ pc_idx = t_sw->pc_flow_idx & ~FLOW_CNTR_PC_FLOW_VALID;
+ if (ulp_flow_db_parent_flow_count_update(ctxt, pc_idx,
t_sw->pkt_count,
t_sw->byte_count)) {
PMD_DRV_LOG(ERR, "Error updating parent counters\n");
@@ -658,6 +660,7 @@ int32_t ulp_fc_mgr_cntr_reset(struct bnxt_ulp_context *ctxt, enum tf_dir dir,
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].hw_cntr_id = 0;
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].pkt_count = 0;
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].byte_count = 0;
+ ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].pc_flow_idx = 0;
ulp_fc_info->num_entries--;
pthread_mutex_unlock(&ulp_fc_info->fc_lock);
@@ -688,6 +691,8 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
uint32_t hw_cntr_id = 0, sw_cntr_idx = 0;
struct sw_acc_counter *sw_acc_tbl_entry;
bool found_cntr_resource = false;
+ bool found_parent_flow = false;
+ uint32_t pc_idx = 0;
ulp_fc_info = bnxt_ulp_cntxt_ptr2_fc_info_get(ctxt);
if (!ulp_fc_info)
@@ -707,12 +712,16 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
(params.resource_sub_type ==
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT ||
params.resource_sub_type ==
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_EXT_COUNT ||
- params.resource_sub_type ==
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC)) {
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_EXT_COUNT)) {
found_cntr_resource = true;
break;
}
+ if (params.resource_func ==
+ BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW) {
+ found_parent_flow = true;
+ pc_idx = params.resource_hndl;
+ }
+
} while (!rc && nxt_resource_index);
bnxt_ulp_cntxt_release_fdb_lock(ctxt);
@@ -722,7 +731,8 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
dir = params.direction;
hw_cntr_id = params.resource_hndl;
- if (params.resource_sub_type ==
+ if (!found_parent_flow &&
+ params.resource_sub_type ==
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT) {
if (!ulp_fc_info->num_counters)
return ulp_fc_tf_flow_stat_get(ctxt, ¶ms, count);
@@ -745,14 +755,17 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
sw_acc_tbl_entry->byte_count = 0;
}
pthread_mutex_unlock(&ulp_fc_info->fc_lock);
- } else if (params.resource_sub_type ==
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC) {
+ } else if (found_parent_flow &&
+ params.resource_sub_type ==
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT) {
/* Get stats from the parent child table */
- ulp_flow_db_parent_flow_count_get(ctxt, flow_id,
+ ulp_flow_db_parent_flow_count_get(ctxt, pc_idx,
&count->hits, &count->bytes,
count->reset);
- count->hits_set = 1;
- count->bytes_set = 1;
+ if (count->hits)
+ count->hits_set = 1;
+ if (count->bytes)
+ count->bytes_set = 1;
} else {
/* TBD: Handle External counters */
rc = -EINVAL;
@@ -770,13 +783,13 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
*
* hw_cntr_id [in] The HW flow counter ID
*
- * fid [in] parent flow id
+ * pc_idx [in] parent child db index
*
*/
int32_t ulp_fc_mgr_cntr_parent_flow_set(struct bnxt_ulp_context *ctxt,
enum tf_dir dir,
uint32_t hw_cntr_id,
- uint32_t fid)
+ uint32_t pc_idx)
{
struct bnxt_ulp_fc_info *ulp_fc_info;
uint32_t sw_cntr_idx;
@@ -789,10 +802,11 @@ int32_t ulp_fc_mgr_cntr_parent_flow_set(struct bnxt_ulp_context *ctxt,
pthread_mutex_lock(&ulp_fc_info->fc_lock);
sw_cntr_idx = hw_cntr_id - ulp_fc_info->shadow_hw_tbl[dir].start_idx;
if (ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].valid) {
- ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].parent_flow_id = fid;
+ pc_idx |= FLOW_CNTR_PC_FLOW_VALID;
+ ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].pc_flow_idx = pc_idx;
} else {
BNXT_TF_DBG(ERR, "Failed to set parent flow id %x:%x\n",
- hw_cntr_id, fid);
+ hw_cntr_id, pc_idx);
rc = -ENOENT;
}
pthread_mutex_unlock(&ulp_fc_info->fc_lock);
diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
index 448d05c118..9825ed2a27 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
@@ -21,12 +21,14 @@
#define FLOW_CNTR_BYTES(v, d) (((v) & (d)->byte_count_mask) >> \
(d)->byte_count_shift)
+#define FLOW_CNTR_PC_FLOW_VALID 0x1000000
+
struct sw_acc_counter {
uint64_t pkt_count;
uint64_t byte_count;
bool valid;
uint32_t hw_cntr_id;
- uint32_t parent_flow_id;
+ uint32_t pc_flow_idx;
};
struct hw_fc_mem_info {
@@ -175,12 +177,12 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ulp_ctx,
*
* hw_cntr_id [in] The HW flow counter ID
*
- * fid [in] parent flow id
+ * pc_idx [in] parent child db index
*
*/
int32_t ulp_fc_mgr_cntr_parent_flow_set(struct bnxt_ulp_context *ctxt,
enum tf_dir dir,
uint32_t hw_cntr_id,
- uint32_t fid);
+ uint32_t pc_idx);
#endif /* _ULP_FC_MGR_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
index 016c86fb6e..9e6bd90aea 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
@@ -386,101 +386,6 @@ ulp_flow_db_parent_tbl_deinit(struct bnxt_ulp_flow_db *flow_db)
}
}
-/* internal validation function for parent flow tbl */
-static struct bnxt_ulp_flow_db *
-ulp_flow_db_parent_arg_validation(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t fid)
-{
- struct bnxt_ulp_flow_db *flow_db;
-
- flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
- if (!flow_db) {
- BNXT_TF_DBG(ERR, "Invalid Arguments\n");
- return NULL;
- }
-
- /* check for max flows */
- if (fid >= flow_db->flow_tbl.num_flows || !fid) {
- BNXT_TF_DBG(ERR, "Invalid flow index\n");
- return NULL;
- }
-
- /* No support for parent child db then just exit */
- if (!flow_db->parent_child_db.entries_count) {
- BNXT_TF_DBG(ERR, "parent child db not supported\n");
- return NULL;
- }
-
- return flow_db;
-}
-
-/*
- * Set the tunnel index in the parent flow
- *
- * ulp_ctxt [in] Ptr to ulp_context
- * parent_idx [in] The parent index of the parent flow entry
- *
- * returns index on success and negative on failure.
- */
-static int32_t
-ulp_flow_db_parent_tun_idx_set(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_idx, uint8_t tun_idx)
-{
- struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
-
- flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
- if (!flow_db) {
- BNXT_TF_DBG(ERR, "Invalid Arguments\n");
- return -EINVAL;
- }
-
- /* check for parent idx validity */
- p_pdb = &flow_db->parent_child_db;
- if (parent_idx >= p_pdb->entries_count ||
- !p_pdb->parent_flow_tbl[parent_idx].parent_fid) {
- BNXT_TF_DBG(ERR, "Invalid parent flow index %x\n", parent_idx);
- return -EINVAL;
- }
-
- p_pdb->parent_flow_tbl[parent_idx].tun_idx = tun_idx;
- return 0;
-}
-
-/*
- * Get the tunnel index from the parent flow
- *
- * ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
- *
- * returns 0 if counter accum is set else -1.
- */
-static int32_t
-ulp_flow_db_parent_tun_idx_get(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid, uint8_t *tun_idx)
-{
- struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
- uint32_t idx;
-
- /* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
- if (!flow_db) {
- BNXT_TF_DBG(ERR, "parent child db validation failed\n");
- return -EINVAL;
- }
-
- p_pdb = &flow_db->parent_child_db;
- for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
- *tun_idx = p_pdb->parent_flow_tbl[idx].tun_idx;
- return 0;
- }
- }
-
- return -EINVAL;
-}
-
/*
* Initialize the flow database. Memory is allocated in this
* call and assigned to the flow database.
@@ -783,9 +688,6 @@ ulp_flow_db_resource_del(struct bnxt_ulp_context *ulp_ctxt,
struct bnxt_ulp_flow_tbl *flow_tbl;
struct ulp_fdb_resource_info *nxt_resource, *fid_resource;
uint32_t nxt_idx = 0;
- struct bnxt_tun_cache_entry *tun_tbl;
- uint8_t tun_idx = 0;
- int rc;
flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
if (!flow_db) {
@@ -862,18 +764,6 @@ ulp_flow_db_resource_del(struct bnxt_ulp_context *ulp_ctxt,
params->resource_hndl);
}
- if (params->resource_func == BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW) {
- tun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(ulp_ctxt);
- if (!tun_tbl)
- return -EINVAL;
-
- rc = ulp_flow_db_parent_tun_idx_get(ulp_ctxt, fid, &tun_idx);
- if (rc)
- return rc;
-
- ulp_clear_tun_entry(tun_tbl, tun_idx);
- }
-
/* all good, return success */
return 0;
}
@@ -892,7 +782,6 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt,
enum bnxt_ulp_fdb_type flow_type,
uint32_t fid)
{
- struct bnxt_tun_cache_entry *tun_tbl;
struct bnxt_ulp_flow_tbl *flow_tbl;
struct bnxt_ulp_flow_db *flow_db;
@@ -934,12 +823,6 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt,
if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR)
ulp_flow_db_func_id_set(flow_db, fid, 0);
- tun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(ulp_ctxt);
- if (!tun_tbl)
- return -EINVAL;
-
- ulp_clear_tun_inner_entry(tun_tbl, fid);
-
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
BNXT_TF_DBG(ERR, "flow_id = %u:%u freed\n", flow_type, fid);
#endif
@@ -1307,24 +1190,84 @@ ulp_default_flow_db_cfa_action_get(struct bnxt_ulp_context *ulp_ctx,
return 0;
}
+/* internal validation function for parent flow tbl */
+static struct ulp_fdb_parent_info *
+ulp_flow_db_pc_db_entry_get(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t pc_idx)
+{
+ struct bnxt_ulp_flow_db *flow_db;
+
+ flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
+ if (!flow_db) {
+ BNXT_TF_DBG(ERR, "Invalid Arguments\n");
+ return NULL;
+ }
+
+ /* check for max flows */
+ if (pc_idx >= BNXT_ULP_MAX_TUN_CACHE_ENTRIES) {
+ BNXT_TF_DBG(ERR, "Invalid tunnel index\n");
+ return NULL;
+ }
+
+ /* No support for parent child db then just exit */
+ if (!flow_db->parent_child_db.entries_count) {
+ BNXT_TF_DBG(ERR, "parent child db not supported\n");
+ return NULL;
+ }
+ if (!flow_db->parent_child_db.parent_flow_tbl[pc_idx].valid) {
+ BNXT_TF_DBG(ERR, "Not a valid tunnel index\n");
+ return NULL;
+ }
+
+ return &flow_db->parent_child_db.parent_flow_tbl[pc_idx];
+}
+
+/* internal validation function for parent flow tbl */
+static struct bnxt_ulp_flow_db *
+ulp_flow_db_parent_arg_validation(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t tun_idx)
+{
+ struct bnxt_ulp_flow_db *flow_db;
+
+ flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
+ if (!flow_db) {
+ BNXT_TF_DBG(ERR, "Invalid Arguments\n");
+ return NULL;
+ }
+
+ /* check for max flows */
+ if (tun_idx >= BNXT_ULP_MAX_TUN_CACHE_ENTRIES) {
+ BNXT_TF_DBG(ERR, "Invalid tunnel index\n");
+ return NULL;
+ }
+
+ /* No support for parent child db then just exit */
+ if (!flow_db->parent_child_db.entries_count) {
+ BNXT_TF_DBG(ERR, "parent child db not supported\n");
+ return NULL;
+ }
+
+ return flow_db;
+}
+
/*
* Allocate the entry in the parent-child database
*
* ulp_ctxt [in] Ptr to ulp_context
- * fid [in] The flow id to the flow entry
+ * tun_idx [in] The tunnel index of the flow entry
*
* returns index on success and negative on failure.
*/
-int32_t
-ulp_flow_db_parent_flow_alloc(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t fid)
+static int32_t
+ulp_flow_db_pc_db_idx_alloc(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t tun_idx)
{
struct bnxt_ulp_flow_db *flow_db;
struct ulp_fdb_parent_child_db *p_pdb;
uint32_t idx, free_idx = 0;
/* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, fid);
+ flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, tun_idx);
if (!flow_db) {
BNXT_TF_DBG(ERR, "parent child db validation failed\n");
return -EINVAL;
@@ -1332,11 +1275,11 @@ ulp_flow_db_parent_flow_alloc(struct bnxt_ulp_context *ulp_ctxt,
p_pdb = &flow_db->parent_child_db;
for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == fid) {
- BNXT_TF_DBG(ERR, "fid is already allocated\n");
- return -EINVAL;
+ if (p_pdb->parent_flow_tbl[idx].valid &&
+ p_pdb->parent_flow_tbl[idx].tun_idx == tun_idx) {
+ return idx;
}
- if (!p_pdb->parent_flow_tbl[idx].parent_fid && !free_idx)
+ if (!p_pdb->parent_flow_tbl[idx].valid && !free_idx)
free_idx = idx + 1;
}
/* no free slots */
@@ -1347,132 +1290,148 @@ ulp_flow_db_parent_flow_alloc(struct bnxt_ulp_context *ulp_ctxt,
free_idx -= 1;
/* set the Fid in the parent child */
- p_pdb->parent_flow_tbl[free_idx].parent_fid = fid;
+ p_pdb->parent_flow_tbl[free_idx].tun_idx = tun_idx;
+ p_pdb->parent_flow_tbl[free_idx].valid = 1;
return free_idx;
}
/*
* Free the entry in the parent-child database
*
- * ulp_ctxt [in] Ptr to ulp_context
- * fid [in] The flow id to the flow entry
+ * pc_entry [in] Ptr to parent child db entry
*
- * returns 0 on success and negative on failure.
+ * returns none.
*/
-int32_t
-ulp_flow_db_parent_flow_free(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t fid)
+static void
+ulp_flow_db_pc_db_entry_free(struct bnxt_ulp_context *ulp_ctxt,
+ struct ulp_fdb_parent_info *pc_entry)
{
+ struct bnxt_tun_cache_entry *tun_tbl;
struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
- uint32_t idx;
+ uint64_t *tmp_bitset;
- /* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, fid);
- if (!flow_db) {
- BNXT_TF_DBG(ERR, "parent child db validation failed\n");
- return -EINVAL;
- }
+ /* free the tunnel entry */
+ tun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(ulp_ctxt);
+ if (tun_tbl)
+ ulp_tunnel_offload_entry_clear(tun_tbl, pc_entry->tun_idx);
- p_pdb = &flow_db->parent_child_db;
- for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == fid) {
- /* free the contents */
- p_pdb->parent_flow_tbl[idx].parent_fid = 0;
- memset(p_pdb->parent_flow_tbl[idx].child_fid_bitset,
- 0, p_pdb->child_bitset_size);
- return 0;
- }
- }
- BNXT_TF_DBG(ERR, "parent entry not found = %x\n", fid);
- return -EINVAL;
+ /* free the child bitset*/
+ flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
+ if (flow_db)
+ memset(pc_entry->child_fid_bitset, 0,
+ flow_db->parent_child_db.child_bitset_size);
+
+ /* free the contents */
+ tmp_bitset = pc_entry->child_fid_bitset;
+ memset(pc_entry, 0, sizeof(struct ulp_fdb_parent_info));
+ pc_entry->child_fid_bitset = tmp_bitset;
}
/*
- * Set or reset the child flow in the parent-child database
+ * Set or reset the parent flow in the parent-child database
*
* ulp_ctxt [in] Ptr to ulp_context
+ * pc_idx [in] The index to parent child db
* parent_fid [in] The flow id of the parent flow entry
- * child_fid [in] The flow id of the child flow entry
* set_flag [in] Use 1 for setting child, 0 to reset
*
* returns zero on success and negative on failure.
*/
int32_t
-ulp_flow_db_parent_child_flow_set(struct bnxt_ulp_context *ulp_ctxt,
+ulp_flow_db_pc_db_parent_flow_set(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t pc_idx,
uint32_t parent_fid,
- uint32_t child_fid,
uint32_t set_flag)
{
+ struct ulp_fdb_parent_info *pc_entry;
struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
- uint32_t idx, a_idx;
- uint64_t *t;
- /* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
+ flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
if (!flow_db) {
BNXT_TF_DBG(ERR, "parent child db validation failed\n");
return -EINVAL;
}
/* check for fid validity */
- if (child_fid >= flow_db->flow_tbl.num_flows || !child_fid) {
- BNXT_TF_DBG(ERR, "Invalid child flow index %x\n", child_fid);
+ if (parent_fid >= flow_db->flow_tbl.num_flows || !parent_fid) {
+ BNXT_TF_DBG(ERR, "Invalid parent flow index %x\n", parent_fid);
return -EINVAL;
}
- p_pdb = &flow_db->parent_child_db;
- a_idx = child_fid / ULP_INDEX_BITMAP_SIZE;
- for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
- t = p_pdb->parent_flow_tbl[idx].child_fid_bitset;
- if (set_flag)
- ULP_INDEX_BITMAP_SET(t[a_idx], child_fid);
- else
- ULP_INDEX_BITMAP_RESET(t[a_idx], child_fid);
- return 0;
- }
+ /* validate the arguments and parent child entry */
+ pc_entry = ulp_flow_db_pc_db_entry_get(ulp_ctxt, pc_idx);
+ if (!pc_entry) {
+ BNXT_TF_DBG(ERR, "failed to get the parent child entry\n");
+ return -EINVAL;
}
- BNXT_TF_DBG(ERR, "Unable to set the parent-child flow %x:%x\n",
- parent_fid, child_fid);
- return -1;
+
+ if (set_flag) {
+ pc_entry->parent_fid = parent_fid;
+ } else {
+ if (pc_entry->parent_fid != parent_fid)
+ BNXT_TF_DBG(ERR, "Panic: invalid parent id\n");
+ pc_entry->parent_fid = 0;
+
+ /* Free the parent child db entry if no user present */
+ if (!pc_entry->f2_cnt)
+ ulp_flow_db_pc_db_entry_free(ulp_ctxt, pc_entry);
+ }
+ return 0;
}
/*
- * Get the parent index from the parent-child database
+ * Set or reset the child flow in the parent-child database
*
* ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
- * parent_idx [out] The parent index of parent flow entry
+ * pc_idx [in] The index to parent child db
+ * child_fid [in] The flow id of the child flow entry
+ * set_flag [in] Use 1 for setting child, 0 to reset
*
* returns zero on success and negative on failure.
*/
int32_t
-ulp_flow_db_parent_flow_idx_get(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid,
- uint32_t *parent_idx)
+ulp_flow_db_pc_db_child_flow_set(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t pc_idx,
+ uint32_t child_fid,
+ uint32_t set_flag)
{
+ struct ulp_fdb_parent_info *pc_entry;
struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
- uint32_t idx;
+ uint32_t a_idx;
+ uint64_t *t;
- /* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
+ flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
if (!flow_db) {
BNXT_TF_DBG(ERR, "parent child db validation failed\n");
return -EINVAL;
}
- p_pdb = &flow_db->parent_child_db;
- for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
- *parent_idx = idx;
- return 0;
- }
+ /* check for fid validity */
+ if (child_fid >= flow_db->flow_tbl.num_flows || !child_fid) {
+ BNXT_TF_DBG(ERR, "Invalid child flow index %x\n", child_fid);
+ return -EINVAL;
}
- BNXT_TF_DBG(ERR, "Unable to get the parent flow %x\n", parent_fid);
- return -1;
+
+ /* validate the arguments and parent child entry */
+ pc_entry = ulp_flow_db_pc_db_entry_get(ulp_ctxt, pc_idx);
+ if (!pc_entry) {
+ BNXT_TF_DBG(ERR, "failed to get the parent child entry\n");
+ return -EINVAL;
+ }
+
+ a_idx = child_fid / ULP_INDEX_BITMAP_SIZE;
+ t = pc_entry->child_fid_bitset;
+ if (set_flag) {
+ ULP_INDEX_BITMAP_SET(t[a_idx], child_fid);
+ pc_entry->f2_cnt++;
+ } else {
+ ULP_INDEX_BITMAP_RESET(t[a_idx], child_fid);
+ if (pc_entry->f2_cnt)
+ pc_entry->f2_cnt--;
+ if (!pc_entry->f2_cnt && !pc_entry->parent_fid)
+ ulp_flow_db_pc_db_entry_free(ulp_ctxt, pc_entry);
+ }
+ return 0;
}
/*
@@ -1541,13 +1500,13 @@ ulp_flow_db_parent_child_flow_next_entry_get(struct bnxt_ulp_flow_db *flow_db,
* Set the counter accumulation in the parent flow
*
* ulp_ctxt [in] Ptr to ulp_context
- * parent_idx [in] The parent index of the parent flow entry
+ * pc_idx [in] The parent child index of the parent flow entry
*
* returns index on success and negative on failure.
*/
static int32_t
ulp_flow_db_parent_flow_count_accum_set(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_idx)
+ uint32_t pc_idx)
{
struct bnxt_ulp_flow_db *flow_db;
struct ulp_fdb_parent_child_db *p_pdb;
@@ -1560,50 +1519,16 @@ ulp_flow_db_parent_flow_count_accum_set(struct bnxt_ulp_context *ulp_ctxt,
/* check for parent idx validity */
p_pdb = &flow_db->parent_child_db;
- if (parent_idx >= p_pdb->entries_count ||
- !p_pdb->parent_flow_tbl[parent_idx].parent_fid) {
- BNXT_TF_DBG(ERR, "Invalid parent flow index %x\n", parent_idx);
+ if (pc_idx >= p_pdb->entries_count ||
+ !p_pdb->parent_flow_tbl[pc_idx].parent_fid) {
+ BNXT_TF_DBG(ERR, "Invalid parent child index %x\n", pc_idx);
return -EINVAL;
}
- p_pdb->parent_flow_tbl[parent_idx].counter_acc = 1;
+ p_pdb->parent_flow_tbl[pc_idx].counter_acc = 1;
return 0;
}
-/*
- * Get the counter accumulation in the parent flow
- *
- * ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
- *
- * returns 0 if counter accum is set else -1.
- */
-static int32_t
-ulp_flow_db_parent_flow_count_accum_get(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid)
-{
- struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
- uint32_t idx;
-
- /* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
- if (!flow_db) {
- BNXT_TF_DBG(ERR, "parent child db validation failed\n");
- return -EINVAL;
- }
-
- p_pdb = &flow_db->parent_child_db;
- for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
- if (p_pdb->parent_flow_tbl[idx].counter_acc)
- return 0;
- break;
- }
- }
- return -1;
-}
-
/*
* Orphan the child flow entry
* This is called only for child flows that have
@@ -1677,22 +1602,30 @@ int32_t
ulp_flow_db_parent_flow_create(struct bnxt_ulp_mapper_parms *parms)
{
struct ulp_flow_db_res_params fid_parms;
- uint32_t sub_typ = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC;
+ uint32_t sub_typ = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT;
struct ulp_flow_db_res_params res_params;
- int32_t fid_idx, rc;
+ int32_t pc_idx;
- /* create the child flow entry in parent flow table */
- fid_idx = ulp_flow_db_parent_flow_alloc(parms->ulp_ctx, parms->fid);
- if (fid_idx < 0) {
- BNXT_TF_DBG(ERR, "Error in creating parent flow fid %x\n",
- parms->fid);
- return -1;
+ /* create or get the parent child database */
+ pc_idx = ulp_flow_db_pc_db_idx_alloc(parms->ulp_ctx, parms->tun_idx);
+ if (pc_idx < 0) {
+ BNXT_TF_DBG(ERR, "Error in getting parent child db %x\n",
+ parms->tun_idx);
+ return -EINVAL;
+ }
+
+ /* Update the parent fid */
+ if (ulp_flow_db_pc_db_parent_flow_set(parms->ulp_ctx, pc_idx,
+ parms->fid, 1)) {
+ BNXT_TF_DBG(ERR, "Error in setting parent fid %x\n",
+ parms->tun_idx);
+ return -EINVAL;
}
/* Add the parent details in the resource list of the flow */
memset(&fid_parms, 0, sizeof(fid_parms));
fid_parms.resource_func = BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW;
- fid_parms.resource_hndl = fid_idx;
+ fid_parms.resource_hndl = pc_idx;
fid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO;
if (ulp_flow_db_resource_add(parms->ulp_ctx, BNXT_ULP_FDB_TYPE_REGULAR,
parms->fid, &fid_parms)) {
@@ -1710,20 +1643,13 @@ ulp_flow_db_parent_flow_create(struct bnxt_ulp_mapper_parms *parms)
&res_params)) {
/* Enable the counter accumulation in parent entry */
if (ulp_flow_db_parent_flow_count_accum_set(parms->ulp_ctx,
- fid_idx)) {
+ pc_idx)) {
BNXT_TF_DBG(ERR, "Error in setting counter acc %x\n",
parms->fid);
return -1;
}
}
- rc = ulp_flow_db_parent_tun_idx_set(parms->ulp_ctx, fid_idx,
- parms->tun_idx);
- if (rc) {
- BNXT_TF_DBG(ERR, "Error setting tun_idx in the parent flow\n");
- return rc;
- }
-
return 0;
}
@@ -1741,13 +1667,19 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
uint32_t sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT;
enum bnxt_ulp_resource_func res_fun;
struct ulp_flow_db_res_params res_p;
- uint32_t parent_fid = parms->parent_fid;
- int32_t rc;
+ int32_t rc, pc_idx;
+
+ /* create or get the parent child database */
+ pc_idx = ulp_flow_db_pc_db_idx_alloc(parms->ulp_ctx, parms->tun_idx);
+ if (pc_idx < 0) {
+ BNXT_TF_DBG(ERR, "Error in getting parent child db %x\n",
+ parms->tun_idx);
+ return -1;
+ }
/* create the parent flow entry in parent flow table */
- rc = ulp_flow_db_parent_child_flow_set(parms->ulp_ctx,
- parms->parent_fid,
- parms->fid, 1);
+ rc = ulp_flow_db_pc_db_child_flow_set(parms->ulp_ctx, pc_idx,
+ parms->fid, 1);
if (rc) {
BNXT_TF_DBG(ERR, "Error in setting child fid %x\n", parms->fid);
return rc;
@@ -1756,7 +1688,7 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
/* Add the parent details in the resource list of the flow */
memset(&fid_parms, 0, sizeof(fid_parms));
fid_parms.resource_func = BNXT_ULP_RESOURCE_FUNC_CHILD_FLOW;
- fid_parms.resource_hndl = parms->parent_fid;
+ fid_parms.resource_hndl = pc_idx;
fid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO;
rc = ulp_flow_db_resource_add(parms->ulp_ctx,
BNXT_ULP_FDB_TYPE_REGULAR,
@@ -1767,30 +1699,26 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
return rc;
}
- /* check if accumulation count is set for parent flow */
- rc = ulp_flow_db_parent_flow_count_accum_get(parms->ulp_ctx,
- parms->parent_fid);
+ /* check if internal count action included for this flow.*/
+ res_fun = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE;
+ rc = ulp_flow_db_resource_params_get(parms->ulp_ctx,
+ BNXT_ULP_FDB_TYPE_REGULAR,
+ parms->fid,
+ res_fun,
+ sub_type,
+ &res_p);
if (!rc) {
- /* check if internal count action included for this flow.*/
- res_fun = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE;
- rc = ulp_flow_db_resource_params_get(parms->ulp_ctx,
- BNXT_ULP_FDB_TYPE_REGULAR,
- parms->fid,
- res_fun,
- sub_type,
- &res_p);
- if (!rc) {
- /* update the counter manager to include parent fid */
- if (ulp_fc_mgr_cntr_parent_flow_set(parms->ulp_ctx,
- res_p.direction,
- res_p.resource_hndl,
- parent_fid)) {
- BNXT_TF_DBG(ERR, "Error in setting child %x\n",
- parms->fid);
- return -1;
- }
+ /* update the counter manager to include parent fid */
+ if (ulp_fc_mgr_cntr_parent_flow_set(parms->ulp_ctx,
+ res_p.direction,
+ res_p.resource_hndl,
+ pc_idx)) {
+ BNXT_TF_DBG(ERR, "Error in setting child %x\n",
+ parms->fid);
+ return -1;
}
}
+
/* return success */
return 0;
}
@@ -1799,7 +1727,7 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
* Update the parent counters
*
* ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
+ * pc_idx [in] The parent flow entry idx
* packet_count [in] - packet count
* byte_count [in] - byte count
*
@@ -1807,41 +1735,31 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
*/
int32_t
ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid,
+ uint32_t pc_idx,
uint64_t packet_count,
uint64_t byte_count)
{
- struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
- uint32_t idx;
+ struct ulp_fdb_parent_info *pc_entry;
- /* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
- if (!flow_db) {
- BNXT_TF_DBG(ERR, "parent child db validation failed\n");
+ /* validate the arguments and get parent child entry */
+ pc_entry = ulp_flow_db_pc_db_entry_get(ulp_ctxt, pc_idx);
+ if (!pc_entry) {
+ BNXT_TF_DBG(ERR, "failed to get the parent child entry\n");
return -EINVAL;
}
- p_pdb = &flow_db->parent_child_db;
- for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
- if (p_pdb->parent_flow_tbl[idx].counter_acc) {
- p_pdb->parent_flow_tbl[idx].pkt_count +=
- packet_count;
- p_pdb->parent_flow_tbl[idx].byte_count +=
- byte_count;
- }
- return 0;
- }
+ if (pc_entry->counter_acc) {
+ pc_entry->pkt_count += packet_count;
+ pc_entry->byte_count += byte_count;
}
- return -ENOENT;
+ return 0;
}
/*
* Get the parent accumulation counters
*
* ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
+ * pc_idx [in] The parent flow entry idx
* packet_count [out] - packet count
* byte_count [out] - byte count
*
@@ -1849,37 +1767,27 @@ ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt,
*/
int32_t
ulp_flow_db_parent_flow_count_get(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid, uint64_t *packet_count,
+ uint32_t pc_idx, uint64_t *packet_count,
uint64_t *byte_count, uint8_t count_reset)
{
- struct bnxt_ulp_flow_db *flow_db;
- struct ulp_fdb_parent_child_db *p_pdb;
- uint32_t idx;
+ struct ulp_fdb_parent_info *pc_entry;
- /* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
- if (!flow_db) {
- BNXT_TF_DBG(ERR, "parent child db validation failed\n");
+ /* validate the arguments and get parent child entry */
+ pc_entry = ulp_flow_db_pc_db_entry_get(ulp_ctxt, pc_idx);
+ if (!pc_entry) {
+ BNXT_TF_DBG(ERR, "failed to get the parent child entry\n");
return -EINVAL;
}
- p_pdb = &flow_db->parent_child_db;
- for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
- if (p_pdb->parent_flow_tbl[idx].counter_acc) {
- *packet_count =
- p_pdb->parent_flow_tbl[idx].pkt_count;
- *byte_count =
- p_pdb->parent_flow_tbl[idx].byte_count;
- if (count_reset) {
- p_pdb->parent_flow_tbl[idx].pkt_count = 0;
- p_pdb->parent_flow_tbl[idx].byte_count = 0;
- }
- }
- return 0;
+ if (pc_entry->counter_acc) {
+ *packet_count = pc_entry->pkt_count;
+ *byte_count = pc_entry->byte_count;
+ if (count_reset) {
+ pc_entry->pkt_count = 0;
+ pc_entry->byte_count = 0;
}
}
- return -ENOENT;
+ return 0;
}
/*
@@ -1897,7 +1805,7 @@ ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt)
uint32_t idx;
/* validate the arguments */
- flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, 1);
+ flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
if (!flow_db) {
BNXT_TF_DBG(ERR, "parent child db validation failed\n");
return;
@@ -1905,7 +1813,7 @@ ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt)
p_pdb = &flow_db->parent_child_db;
for (idx = 0; idx < p_pdb->entries_count; idx++) {
- if (p_pdb->parent_flow_tbl[idx].parent_fid &&
+ if (p_pdb->parent_flow_tbl[idx].valid &&
p_pdb->parent_flow_tbl[idx].counter_acc) {
p_pdb->parent_flow_tbl[idx].pkt_count = 0;
p_pdb->parent_flow_tbl[idx].byte_count = 0;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
index 0ddfa6f66d..8680ee8f65 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
@@ -58,6 +58,7 @@ struct bnxt_ulp_flow_tbl {
/* Structure to maintain parent-child flow relationships */
struct ulp_fdb_parent_info {
+ uint32_t valid;
uint32_t parent_fid;
uint32_t counter_acc;
uint64_t pkt_count;
@@ -259,45 +260,38 @@ int32_t
ulp_default_flow_db_cfa_action_get(struct bnxt_ulp_context *ulp_ctx,
uint32_t flow_id,
uint16_t *cfa_action);
-/*
- * Allocate the entry in the parent-child database
- *
- * ulp_ctxt [in] Ptr to ulp_context
- * fid [in] The flow id to the flow entry
- *
- * returns index on success and negative on failure.
- */
-int32_t
-ulp_flow_db_parent_flow_alloc(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t fid);
/*
- * Free the entry in the parent-child database
+ * Set or reset the parent flow in the parent-child database
*
* ulp_ctxt [in] Ptr to ulp_context
- * fid [in] The flow id to the flow entry
+ * pc_idx [in] The index to parent child db
+ * parent_fid [in] The flow id of the parent flow entry
+ * set_flag [in] Use 1 for setting child, 0 to reset
*
- * returns 0 on success and negative on failure.
+ * returns zero on success and negative on failure.
*/
int32_t
-ulp_flow_db_parent_flow_free(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t fid);
+ulp_flow_db_pc_db_parent_flow_set(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t pc_idx,
+ uint32_t parent_fid,
+ uint32_t set_flag);
/*
* Set or reset the child flow in the parent-child database
*
* ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
+ * pc_idx [in] The index to parent child db
* child_fid [in] The flow id of the child flow entry
* set_flag [in] Use 1 for setting child, 0 to reset
*
* returns zero on success and negative on failure.
*/
int32_t
-ulp_flow_db_parent_child_flow_set(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid,
- uint32_t child_fid,
- uint32_t set_flag);
+ulp_flow_db_pc_db_child_flow_set(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t pc_idx,
+ uint32_t child_fid,
+ uint32_t set_flag);
/*
* Get the parent index from the parent-child database
@@ -368,7 +362,7 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms);
* Update the parent counters
*
* ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
+ * pc_idx [in] The parent flow entry idx
* packet_count [in] - packet count
* byte_count [in] - byte count
*
@@ -376,14 +370,14 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms);
*/
int32_t
ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid,
+ uint32_t pc_idx,
uint64_t packet_count,
uint64_t byte_count);
/*
* Get the parent accumulation counters
*
* ulp_ctxt [in] Ptr to ulp_context
- * parent_fid [in] The flow id of the parent flow entry
+ * pc_idx [in] The parent flow entry idx
* packet_count [out] - packet count
* byte_count [out] - byte count
*
@@ -391,7 +385,7 @@ ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt,
*/
int32_t
ulp_flow_db_parent_flow_count_get(struct bnxt_ulp_context *ulp_ctxt,
- uint32_t parent_fid,
+ uint32_t pc_idx,
uint64_t *packet_count,
uint64_t *byte_count,
uint8_t count_reset);
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 7fc3767b33..6d804c7ef9 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -544,34 +544,14 @@ ulp_mapper_parent_flow_free(struct bnxt_ulp_context *ulp,
uint32_t parent_fid,
struct ulp_flow_db_res_params *res)
{
- uint32_t idx, child_fid = 0, parent_idx;
- struct bnxt_ulp_flow_db *flow_db;
+ uint32_t pc_idx;
- parent_idx = (uint32_t)res->resource_hndl;
+ pc_idx = (uint32_t)res->resource_hndl;
- /* check the validity of the parent fid */
- if (ulp_flow_db_parent_flow_idx_get(ulp, parent_fid, &idx) ||
- idx != parent_idx) {
- BNXT_TF_DBG(ERR, "invalid parent flow id %x\n", parent_fid);
- return -EINVAL;
- }
-
- /* Clear all the child flows parent index */
- flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp);
- while (!ulp_flow_db_parent_child_flow_next_entry_get(flow_db, idx,
- &child_fid)) {
- /* update the child flows resource handle */
- if (ulp_flow_db_child_flow_reset(ulp, BNXT_ULP_FDB_TYPE_REGULAR,
- child_fid)) {
- BNXT_TF_DBG(ERR, "failed to reset child flow %x\n",
- child_fid);
- return -EINVAL;
- }
- }
-
- /* free the parent entry in the parent table flow */
- if (ulp_flow_db_parent_flow_free(ulp, parent_fid)) {
- BNXT_TF_DBG(ERR, "failed to free parent flow %x\n", parent_fid);
+ /* reset the child flow bitset*/
+ if (ulp_flow_db_pc_db_parent_flow_set(ulp, pc_idx, parent_fid, 0)) {
+ BNXT_TF_DBG(ERR, "error in reset parent flow bitset %x:%x\n",
+ pc_idx, parent_fid);
return -EINVAL;
}
return 0;
@@ -582,16 +562,14 @@ ulp_mapper_child_flow_free(struct bnxt_ulp_context *ulp,
uint32_t child_fid,
struct ulp_flow_db_res_params *res)
{
- uint32_t parent_fid;
+ uint32_t pc_idx;
- parent_fid = (uint32_t)res->resource_hndl;
- if (!parent_fid)
- return 0; /* Already freed - orphan child*/
+ pc_idx = (uint32_t)res->resource_hndl;
/* reset the child flow bitset*/
- if (ulp_flow_db_parent_child_flow_set(ulp, parent_fid, child_fid, 0)) {
+ if (ulp_flow_db_pc_db_child_flow_set(ulp, pc_idx, child_fid, 0)) {
BNXT_TF_DBG(ERR, "error in resetting child flow bitset %x:%x\n",
- parent_fid, child_fid);
+ pc_idx, child_fid);
return -EINVAL;
}
return 0;
@@ -1944,6 +1922,12 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
+ /* If only allocation of identifier then perform and exit */
+ if (tbl->tbl_opcode == BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT) {
+ rc = ulp_mapper_tcam_tbl_scan_ident_alloc(parms, tbl);
+ return rc;
+ }
+
kflds = ulp_mapper_key_fields_get(parms, tbl, &num_kflds);
if (!kflds || !num_kflds) {
BNXT_TF_DBG(ERR, "Failed to get key fields\n");
@@ -3889,7 +3873,7 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
parms.class_tid = cparms->class_tid;
parms.flow_type = cparms->flow_type;
parms.parent_flow = cparms->parent_flow;
- parms.parent_fid = cparms->parent_fid;
+ parms.child_flow = cparms->child_flow;
parms.fid = cparms->flow_id;
parms.tun_idx = cparms->tun_idx;
parms.app_priority = cparms->app_priority;
@@ -3954,7 +3938,7 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
rc = ulp_flow_db_parent_flow_create(&parms);
if (rc)
goto flow_error;
- } else if (parms.parent_fid) {
+ } else if (parms.child_flow) {
/* create a child flow details */
rc = ulp_flow_db_child_flow_create(&parms);
if (rc)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
index 004e89ac2b..d4d6969bb5 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
@@ -53,7 +53,7 @@ struct bnxt_ulp_mapper_parms {
enum bnxt_ulp_fdb_type flow_type;
struct bnxt_ulp_mapper_data *mapper_data;
struct bnxt_ulp_device_params *device_params;
- uint32_t parent_fid;
+ uint32_t child_flow;
uint32_t parent_flow;
uint8_t tun_idx;
uint32_t app_priority;
@@ -79,8 +79,8 @@ struct bnxt_ulp_mapper_create_parms {
enum bnxt_ulp_fdb_type flow_type;
uint32_t flow_id;
- /* if set then create it as a child flow with parent as parent_fid */
- uint32_t parent_fid;
+ /* if set then create it as a child flow */
+ uint32_t child_flow;
/* if set then create a parent flow */
uint32_t parent_flow;
uint8_t tun_idx;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
index 35e9858727..9b165c12b5 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
@@ -215,6 +215,21 @@ struct bnxt_ulp_rte_act_info ulp_act_info[] = {
}
};
+struct bnxt_ulp_rte_act_info ulp_vendor_act_info[] = {
+ [BNXT_RTE_FLOW_ACTION_TYPE_END - BNXT_RTE_FLOW_ACTION_TYPE_END] = {
+ .act_type = BNXT_ULP_ACT_TYPE_END,
+ .proto_act_func = NULL
+ },
+ [BNXT_RTE_FLOW_ACTION_TYPE_VXLAN_DECAP - BNXT_RTE_FLOW_ACTION_TYPE_END] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_vendor_vxlan_decap_act_handler
+ },
+ [BNXT_RTE_FLOW_ACTION_TYPE_LAST - BNXT_RTE_FLOW_ACTION_TYPE_END] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ }
+};
+
/*
* This table has to be indexed based on the rte_flow_item_type that is part of
* DPDK. The below array is list of parsing functions for each of the flow items
@@ -414,3 +429,19 @@ struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = {
.proto_hdr_func = NULL
}
};
+
+struct bnxt_ulp_rte_hdr_info ulp_vendor_hdr_info[] = {
+ [BNXT_RTE_FLOW_ITEM_TYPE_END - BNXT_RTE_FLOW_ITEM_TYPE_END] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_END,
+ .proto_hdr_func = NULL
+ },
+ [BNXT_RTE_FLOW_ITEM_TYPE_VXLAN_DECAP - BNXT_RTE_FLOW_ITEM_TYPE_END] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_vendor_vxlan_decap_hdr_handler
+ },
+ [BNXT_RTE_FLOW_ITEM_TYPE_LAST - BNXT_RTE_FLOW_ITEM_TYPE_END] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+
+};
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index 79b9957781..fadcd3873c 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -125,13 +125,21 @@ bnxt_ulp_rte_parser_hdr_parse(const struct rte_flow_item pattern[],
/* Parse all the items in the pattern */
while (item && item->type != RTE_FLOW_ITEM_TYPE_END) {
- /* get the header information from the flow_hdr_info table */
- hdr_info = &ulp_hdr_info[item->type];
+ if (item->type >= (uint32_t)
+ BNXT_RTE_FLOW_ITEM_TYPE_END) {
+ if (item->type >=
+ (uint32_t)BNXT_RTE_FLOW_ITEM_TYPE_LAST)
+ goto hdr_parser_error;
+ /* get the header information */
+ hdr_info = &ulp_vendor_hdr_info[item->type -
+ BNXT_RTE_FLOW_ITEM_TYPE_END];
+ } else {
+ if (item->type > RTE_FLOW_ITEM_TYPE_HIGIG2)
+ goto hdr_parser_error;
+ hdr_info = &ulp_hdr_info[item->type];
+ }
if (hdr_info->hdr_type == BNXT_ULP_HDR_TYPE_NOT_SUPPORTED) {
- BNXT_TF_DBG(ERR,
- "Truflow parser does not support type %d\n",
- item->type);
- return BNXT_TF_RC_PARSE_ERR;
+ goto hdr_parser_error;
} else if (hdr_info->hdr_type == BNXT_ULP_HDR_TYPE_SUPPORTED) {
/* call the registered callback handler */
if (hdr_info->proto_hdr_func) {
@@ -145,6 +153,11 @@ bnxt_ulp_rte_parser_hdr_parse(const struct rte_flow_item pattern[],
}
/* update the implied SVIF */
return ulp_rte_parser_implicit_match_port_process(params);
+
+hdr_parser_error:
+ BNXT_TF_DBG(ERR, "Truflow parser does not support type %d\n",
+ item->type);
+ return BNXT_TF_RC_PARSE_ERR;
}
/*
@@ -160,16 +173,23 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[],
/* Parse all the items in the pattern */
while (action_item && action_item->type != RTE_FLOW_ACTION_TYPE_END) {
- /* get the header information from the flow_hdr_info table */
- hdr_info = &ulp_act_info[action_item->type];
- if (hdr_info->act_type ==
- BNXT_ULP_ACT_TYPE_NOT_SUPPORTED) {
- BNXT_TF_DBG(ERR,
- "Truflow parser does not support act %u\n",
- action_item->type);
- return BNXT_TF_RC_ERROR;
- } else if (hdr_info->act_type ==
- BNXT_ULP_ACT_TYPE_SUPPORTED) {
+ if (action_item->type >=
+ (uint32_t)BNXT_RTE_FLOW_ACTION_TYPE_END) {
+ if (action_item->type >=
+ (uint32_t)BNXT_RTE_FLOW_ACTION_TYPE_LAST)
+ goto act_parser_error;
+ /* get the header information from bnxt actinfo table */
+ hdr_info = &ulp_vendor_act_info[action_item->type -
+ BNXT_RTE_FLOW_ACTION_TYPE_END];
+ } else {
+ if (action_item->type > RTE_FLOW_ACTION_TYPE_SHARED)
+ goto act_parser_error;
+ /* get the header information from the act info table */
+ hdr_info = &ulp_act_info[action_item->type];
+ }
+ if (hdr_info->act_type == BNXT_ULP_ACT_TYPE_NOT_SUPPORTED) {
+ goto act_parser_error;
+ } else if (hdr_info->act_type == BNXT_ULP_ACT_TYPE_SUPPORTED) {
/* call the registered callback handler */
if (hdr_info->proto_act_func) {
if (hdr_info->proto_act_func(action_item,
@@ -184,6 +204,11 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[],
/* update the implied port details */
ulp_rte_parser_implicit_act_port_process(params);
return BNXT_TF_RC_SUCCESS;
+
+act_parser_error:
+ BNXT_TF_DBG(ERR, "Truflow parser does not support act %u\n",
+ action_item->type);
+ return BNXT_TF_RC_ERROR;
}
/*
@@ -325,11 +350,10 @@ ulp_post_process_normal_flow(struct ulp_rte_parser_params *params)
/*
* Function to handle the post processing of the parsing details
*/
-int32_t
+void
bnxt_ulp_rte_parser_post_process(struct ulp_rte_parser_params *params)
{
ulp_post_process_normal_flow(params);
- return ulp_post_process_tun_flow(params);
}
/*
@@ -660,7 +684,7 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item,
{
const struct rte_flow_item_eth *eth_spec = item->spec;
const struct rte_flow_item_eth *eth_mask = item->mask;
- uint32_t idx = 0;
+ uint32_t idx = 0, dmac_idx = 0;
uint32_t size;
uint16_t eth_type = 0;
uint32_t inner_flag = 0;
@@ -686,6 +710,7 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item,
* Copy the rte_flow_item for eth into hdr_field using ethernet
* header fields
*/
+ dmac_idx = idx;
size = sizeof(((struct rte_flow_item_eth *)NULL)->dst.addr_bytes);
ulp_rte_prsr_fld_mask(params, &idx, size,
ulp_deference_struct(eth_spec, dst.addr_bytes),
@@ -719,6 +744,8 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item,
inner_flag = 1;
} else {
ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_ETH);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID,
+ dmac_idx);
}
/* Update the field protocol hdr bitmap */
ulp_rte_l2_proto_type_update(params, eth_type, inner_flag);
@@ -926,7 +953,7 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
const struct rte_flow_item_ipv4 *ipv4_spec = item->spec;
const struct rte_flow_item_ipv4 *ipv4_mask = item->mask;
struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap;
- uint32_t idx = 0;
+ uint32_t idx = 0, dip_idx = 0;
uint32_t size;
uint8_t proto = 0;
uint32_t inner_flag = 0;
@@ -939,22 +966,6 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
return BNXT_TF_RC_ERROR;
}
- if (!ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
- BNXT_ULP_HDR_BIT_O_ETH) &&
- !ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
- BNXT_ULP_HDR_BIT_I_ETH)) {
- /* Since F2 flow does not include eth item, when parser detects
- * IPv4/IPv6 item list and it belongs to the outer header; i.e.,
- * o_ipv4/o_ipv6, check if O_ETH and I_ETH is set. If not set,
- * then add offset sizeof(o_eth/oo_vlan/oi_vlan) to the index.
- * This will allow the parser post processor to update the
- * t_dmac in hdr_field[o_eth.dmac]
- */
- idx += (BNXT_ULP_PROTO_HDR_ETH_NUM +
- BNXT_ULP_PROTO_HDR_VLAN_NUM);
- params->field_idx = idx;
- }
-
if (ulp_rte_prsr_fld_size_validate(params, &idx,
BNXT_ULP_PROTO_HDR_IPV4_NUM)) {
BNXT_TF_DBG(ERR, "Error parsing protocol header\n");
@@ -1033,6 +1044,7 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
ulp_deference_struct(ipv4_mask, hdr.src_addr),
ULP_PRSR_ACT_DEFAULT);
+ dip_idx = idx;
size = sizeof(((struct rte_flow_item_ipv4 *)NULL)->hdr.dst_addr);
ulp_rte_prsr_fld_mask(params, &idx, size,
ulp_deference_struct(ipv4_spec, hdr.dst_addr),
@@ -1048,6 +1060,9 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
} else {
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3, 1);
+ /* Update the tunnel offload dest ip offset */
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID,
+ dip_idx);
}
/* Some of the PMD applications may set the protocol field
@@ -1071,7 +1086,7 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
const struct rte_flow_item_ipv6 *ipv6_spec = item->spec;
const struct rte_flow_item_ipv6 *ipv6_mask = item->mask;
struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap;
- uint32_t idx = 0;
+ uint32_t idx = 0, dip_idx = 0;
uint32_t size;
uint32_t ver_spec = 0, ver_mask = 0;
uint32_t tc_spec = 0, tc_mask = 0;
@@ -1087,22 +1102,6 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
return BNXT_TF_RC_ERROR;
}
- if (!ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
- BNXT_ULP_HDR_BIT_O_ETH) &&
- !ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
- BNXT_ULP_HDR_BIT_I_ETH)) {
- /* Since F2 flow does not include eth item, when parser detects
- * IPv4/IPv6 item list and it belongs to the outer header; i.e.,
- * o_ipv4/o_ipv6, check if O_ETH and I_ETH is set. If not set,
- * then add offset sizeof(o_eth/oo_vlan/oi_vlan) to the index.
- * This will allow the parser post processor to update the
- * t_dmac in hdr_field[o_eth.dmac]
- */
- idx += (BNXT_ULP_PROTO_HDR_ETH_NUM +
- BNXT_ULP_PROTO_HDR_VLAN_NUM);
- params->field_idx = idx;
- }
-
if (ulp_rte_prsr_fld_size_validate(params, &idx,
BNXT_ULP_PROTO_HDR_IPV6_NUM)) {
BNXT_TF_DBG(ERR, "Error parsing protocol header\n");
@@ -1171,6 +1170,7 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
ulp_deference_struct(ipv6_mask, hdr.src_addr),
ULP_PRSR_ACT_DEFAULT);
+ dip_idx = idx;
size = sizeof(((struct rte_flow_item_ipv6 *)NULL)->hdr.dst_addr);
ulp_rte_prsr_fld_mask(params, &idx, size,
ulp_deference_struct(ipv6_spec, hdr.dst_addr),
@@ -1186,6 +1186,9 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
} else {
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3, 1);
+ /* Update the tunnel offload dest ip offset */
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID,
+ dip_idx);
}
/* Update the field protocol hdr bitmap */
@@ -1200,9 +1203,11 @@ static void
ulp_rte_l4_proto_type_update(struct ulp_rte_parser_params *param,
uint16_t dst_port)
{
- if (dst_port == tfp_cpu_to_be_16(ULP_UDP_PORT_VXLAN))
+ if (dst_port == tfp_cpu_to_be_16(ULP_UDP_PORT_VXLAN)) {
ULP_BITMAP_SET(param->hdr_fp_bit.bits,
BNXT_ULP_HDR_BIT_T_VXLAN);
+ ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_L3_TUN, 1);
+ }
if (ULP_BITMAP_ISSET(param->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_T_VXLAN) ||
@@ -2484,3 +2489,24 @@ ulp_rte_sample_act_handler(const struct rte_flow_action *action_item,
return ret;
}
+
+/* Function to handle the parsing of bnxt vendor Flow action vxlan Header. */
+int32_t
+ulp_vendor_vxlan_decap_act_handler(const struct rte_flow_action *action_item,
+ struct ulp_rte_parser_params *params)
+{
+ /* Set the F1 flow header bit */
+ ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F1);
+ return ulp_rte_vxlan_decap_act_handler(action_item, params);
+}
+
+/* Function to handle the parsing of bnxt vendor Flow item vxlan Header. */
+int32_t
+ulp_rte_vendor_vxlan_decap_hdr_handler(const struct rte_flow_item *item,
+ struct ulp_rte_parser_params *params)
+{
+ RTE_SET_USED(item);
+ /* Set the F2 flow header bit */
+ ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F2);
+ return ulp_rte_vxlan_decap_act_handler(NULL, params);
+}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
index 4431f1bbd0..673172c811 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
@@ -75,7 +75,7 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[],
/*
* Function to handle the post processing of the parsing details
*/
-int32_t
+void
bnxt_ulp_rte_parser_post_process(struct ulp_rte_parser_params *params);
/* Function to handle the parsing of RTE Flow item PF Header. */
@@ -270,4 +270,12 @@ int32_t
ulp_rte_shared_act_handler(const struct rte_flow_action *action_item,
struct ulp_rte_parser_params *params);
+int32_t
+ulp_vendor_vxlan_decap_act_handler(const struct rte_flow_action *action_item,
+ struct ulp_rte_parser_params *params);
+
+int32_t
+ulp_rte_vendor_vxlan_decap_hdr_handler(const struct rte_flow_item *item,
+ struct ulp_rte_parser_params *params);
+
#endif /* _ULP_RTE_PARSER_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index 0cbac66237..2685e63432 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -78,17 +78,19 @@ struct ulp_rte_parser_params {
uint32_t priority;
uint32_t fid;
uint32_t parent_flow;
- uint32_t parent_fid;
+ uint32_t child_flow;
uint16_t func_id;
uint16_t port_id;
uint32_t class_id;
uint32_t act_tmpl;
struct bnxt_ulp_context *ulp_ctx;
uint32_t hdr_sig_id;
- uint32_t flow_sig_id;
+ uint64_t flow_sig_id;
uint32_t flow_pattern_id;
uint32_t act_pattern_id;
uint8_t app_id;
+ uint8_t tun_idx;
+
};
/* Flow Parser Header Information Structure */
@@ -101,6 +103,7 @@ struct bnxt_ulp_rte_hdr_info {
/* Flow Parser Header Information Structure Array defined in template source*/
extern struct bnxt_ulp_rte_hdr_info ulp_hdr_info[];
+extern struct bnxt_ulp_rte_hdr_info ulp_vendor_hdr_info[];
/* Flow Parser Action Information Structure */
struct bnxt_ulp_rte_act_info {
@@ -113,6 +116,7 @@ struct bnxt_ulp_rte_act_info {
/* Flow Parser Action Information Structure Array defined in template source*/
extern struct bnxt_ulp_rte_act_info ulp_act_info[];
+extern struct bnxt_ulp_rte_act_info ulp_vendor_act_info[];
/* Flow Matcher structures */
struct bnxt_ulp_header_match_info {
@@ -136,7 +140,7 @@ struct bnxt_ulp_class_match_info {
uint8_t wc_pri;
uint8_t app_sig;
uint32_t hdr_sig_id;
- uint32_t flow_sig_id;
+ uint64_t flow_sig_id;
uint32_t flow_pattern_id;
};
diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.c b/drivers/net/bnxt/tf_ulp/ulp_tun.c
index a1dd5b902c..7ce6740633 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_tun.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_tun.c
@@ -3,225 +3,111 @@
* All rights reserved.
*/
-#include <sys/queue.h>
-
-#include <rte_malloc.h>
-
+#include "bnxt.h"
+#include "bnxt_ulp.h"
#include "ulp_tun.h"
-#include "ulp_rte_parser.h"
-#include "ulp_template_db_enum.h"
-#include "ulp_template_struct.h"
-#include "ulp_matcher.h"
-#include "ulp_mapper.h"
-#include "ulp_flow_db.h"
+#include "ulp_utils.h"
-/* This function programs the outer tunnel flow in the hardware. */
-static int32_t
-ulp_install_outer_tun_flow(struct ulp_rte_parser_params *params,
- struct bnxt_tun_cache_entry *tun_entry,
- uint16_t tun_idx)
+/* returns negative on error, 1 if new entry is allocated or zero if old */
+int32_t
+ulp_app_tun_search_entry(struct bnxt_ulp_context *ulp_ctx,
+ struct rte_flow_tunnel *app_tunnel,
+ struct bnxt_flow_app_tun_ent **tun_entry)
{
- struct bnxt_ulp_mapper_create_parms mparms = { 0 };
- int ret;
-
- /* Reset the JUMP action bit in the action bitmap as we don't
- * offload this action.
- */
- ULP_BITMAP_RESET(params->act_bitmap.bits, BNXT_ULP_ACT_BIT_JUMP);
-
- ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F1);
-
-#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
-#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER
- /* Dump the rte flow pattern */
- ulp_parser_hdr_info_dump(params);
- /* Dump the rte flow action */
- ulp_parser_act_info_dump(params);
-#endif
-#endif
-
- ret = ulp_matcher_pattern_match(params, ¶ms->class_id);
- if (ret != BNXT_TF_RC_SUCCESS)
- goto err;
+ struct bnxt_flow_app_tun_ent *tun_ent_list;
+ int32_t i, rc = 0, free_entry = -1;
- ret = ulp_matcher_action_match(params, ¶ms->act_tmpl);
- if (ret != BNXT_TF_RC_SUCCESS)
- goto err;
-
- params->parent_flow = true;
- bnxt_ulp_init_mapper_params(&mparms, params,
- BNXT_ULP_FDB_TYPE_REGULAR);
- mparms.tun_idx = tun_idx;
-
- /* Call the ulp mapper to create the flow in the hardware. */
- ret = ulp_mapper_flow_create(params->ulp_ctx, &mparms);
- if (ret)
- goto err;
-
- /* Store the tunnel dmac in the tunnel cache table and use it while
- * programming tunnel inner flow.
- */
- memcpy(tun_entry->t_dmac,
- ¶ms->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX].spec,
- RTE_ETHER_ADDR_LEN);
-
- tun_entry->tun_flow_info[params->port_id].state =
- BNXT_ULP_FLOW_STATE_TUN_O_OFFLD;
- tun_entry->outer_tun_flow_id = params->fid;
-
- /* Tunnel outer flow and it's related inner flows are correlated
- * based on Tunnel Destination IP Address.
- */
- if (tun_entry->t_dst_ip_valid)
- goto done;
- if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV4))
- memcpy(&tun_entry->t_dst_ip,
- ¶ms->hdr_field[ULP_TUN_O_IPV4_DIP_INDEX].spec,
- sizeof(rte_be32_t));
- else
- memcpy(tun_entry->t_dst_ip6,
- ¶ms->hdr_field[ULP_TUN_O_IPV6_DIP_INDEX].spec,
- sizeof(tun_entry->t_dst_ip6));
- tun_entry->t_dst_ip_valid = true;
+ tun_ent_list = bnxt_ulp_cntxt_ptr2_app_tun_list_get(ulp_ctx);
+ if (!tun_ent_list) {
+ BNXT_TF_DBG(ERR, "unable to get the app tunnel list\n");
+ return -EINVAL;
+ }
-done:
- return BNXT_TF_RC_FID;
+ for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {
+ if (!tun_ent_list[i].ref_cnt) {
+ if (free_entry < 0)
+ free_entry = i;
+ } else {
+ if (!memcmp(&tun_ent_list[i].app_tunnel,
+ app_tunnel,
+ sizeof(struct rte_flow_tunnel))) {
+ *tun_entry = &tun_ent_list[i];
+ tun_ent_list[free_entry].ref_cnt++;
+ return rc;
+ }
+ }
+ }
+ if (free_entry >= 0) {
+ *tun_entry = &tun_ent_list[free_entry];
+ memcpy(&tun_ent_list[free_entry].app_tunnel, app_tunnel,
+ sizeof(struct rte_flow_tunnel));
+ tun_ent_list[free_entry].ref_cnt = 1;
+ rc = 1;
+ } else {
+ BNXT_TF_DBG(ERR, "ulp app tunnel list is full\n");
+ return -ENOMEM;
+ }
-err:
- memset(tun_entry, 0, sizeof(struct bnxt_tun_cache_entry));
- return BNXT_TF_RC_ERROR;
+ return rc;
}
-/* This function programs the inner tunnel flow in the hardware. */
-static void
-ulp_install_inner_tun_flow(struct bnxt_tun_cache_entry *tun_entry,
- struct ulp_rte_parser_params *tun_o_params)
+void
+ulp_app_tun_entry_delete(struct bnxt_flow_app_tun_ent *tun_entry)
{
- struct bnxt_ulp_mapper_create_parms mparms = { 0 };
- struct ulp_per_port_flow_info *flow_info;
- struct ulp_rte_parser_params *inner_params;
- int ret;
-
- /* Tunnel inner flow doesn't have tunnel dmac, use the tunnel
- * dmac that was stored during F1 programming.
- */
- flow_info = &tun_entry->tun_flow_info[tun_o_params->port_id];
- STAILQ_FOREACH(inner_params, &flow_info->tun_i_prms_list, next) {
- memcpy(&inner_params->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX],
- tun_entry->t_dmac, RTE_ETHER_ADDR_LEN);
- inner_params->parent_fid = tun_entry->outer_tun_flow_id;
-
- bnxt_ulp_init_mapper_params(&mparms, inner_params,
- BNXT_ULP_FDB_TYPE_REGULAR);
-
- ret = ulp_mapper_flow_create(inner_params->ulp_ctx, &mparms);
- if (ret)
- PMD_DRV_LOG(ERR,
- "Failed to create inner tun flow, FID:%u.",
- inner_params->fid);
+ if (tun_entry) {
+ if (tun_entry->ref_cnt) {
+ tun_entry->ref_cnt--;
+ if (!tun_entry->ref_cnt)
+ memset(tun_entry, 0,
+ sizeof(struct bnxt_flow_app_tun_ent));
+ }
}
}
-/* This function either install outer tunnel flow & inner tunnel flow
- * or just the outer tunnel flow based on the flow state.
- */
-static int32_t
-ulp_post_process_outer_tun_flow(struct ulp_rte_parser_params *params,
- struct bnxt_tun_cache_entry *tun_entry,
- uint16_t tun_idx)
+int32_t
+ulp_app_tun_entry_set_decap_action(struct bnxt_flow_app_tun_ent *tun_entry)
{
- int ret;
-
- ret = ulp_install_outer_tun_flow(params, tun_entry, tun_idx);
- if (ret == BNXT_TF_RC_ERROR) {
- PMD_DRV_LOG(ERR, "Failed to create outer tunnel flow.");
- return ret;
- }
+ if (!tun_entry)
+ return -EINVAL;
- /* Install any cached tunnel inner flows that came before tunnel
- * outer flow.
- */
- ulp_install_inner_tun_flow(tun_entry, params);
-
- return BNXT_TF_RC_FID;
+ tun_entry->action.type = (typeof(tun_entry->action.type))
+ BNXT_RTE_FLOW_ACTION_TYPE_VXLAN_DECAP;
+ tun_entry->action.conf = tun_entry;
+ return 0;
}
-/* This function will be called if inner tunnel flow request comes before
- * outer tunnel flow request.
- */
-static int32_t
-ulp_post_process_cache_inner_tun_flow(struct ulp_rte_parser_params *params,
- struct bnxt_tun_cache_entry *tun_entry)
+int32_t
+ulp_app_tun_entry_set_decap_item(struct bnxt_flow_app_tun_ent *tun_entry)
{
- struct ulp_rte_parser_params *inner_tun_params;
- struct ulp_per_port_flow_info *flow_info;
- int ret;
-
-#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
-#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER
- /* Dump the rte flow pattern */
- ulp_parser_hdr_info_dump(params);
- /* Dump the rte flow action */
- ulp_parser_act_info_dump(params);
-#endif
-#endif
-
- ret = ulp_matcher_pattern_match(params, ¶ms->class_id);
- if (ret != BNXT_TF_RC_SUCCESS)
- return BNXT_TF_RC_ERROR;
-
- ret = ulp_matcher_action_match(params, ¶ms->act_tmpl);
- if (ret != BNXT_TF_RC_SUCCESS)
- return BNXT_TF_RC_ERROR;
-
- /* If Tunnel inner flow comes first then we can't install it in the
- * hardware, because, Tunnel inner flow will not have L2 context
- * information. So, just cache the Tunnel inner flow information
- * and program it in the context of F1 flow installation.
- */
- flow_info = &tun_entry->tun_flow_info[params->port_id];
- inner_tun_params = rte_zmalloc("ulp_inner_tun_params",
- sizeof(struct ulp_rte_parser_params), 0);
- if (!inner_tun_params)
- return BNXT_TF_RC_ERROR;
- memcpy(inner_tun_params, params, sizeof(struct ulp_rte_parser_params));
- STAILQ_INSERT_TAIL(&flow_info->tun_i_prms_list, inner_tun_params,
- next);
- flow_info->tun_i_cnt++;
-
- /* F1 and it's related Tunnel inner flows are correlated based on
- * Tunnel Destination IP Address. It could be already set, if
- * the inner flow got offloaded first.
- */
- if (tun_entry->t_dst_ip_valid)
- goto done;
- if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV4))
- memcpy(&tun_entry->t_dst_ip,
- ¶ms->hdr_field[ULP_TUN_O_IPV4_DIP_INDEX].spec,
- sizeof(rte_be32_t));
- else
- memcpy(tun_entry->t_dst_ip6,
- ¶ms->hdr_field[ULP_TUN_O_IPV6_DIP_INDEX].spec,
- sizeof(tun_entry->t_dst_ip6));
- tun_entry->t_dst_ip_valid = true;
-
-done:
- return BNXT_TF_RC_FID;
+ if (!tun_entry)
+ return -EINVAL;
+
+ tun_entry->item.type = (typeof(tun_entry->item.type))
+ BNXT_RTE_FLOW_ITEM_TYPE_VXLAN_DECAP;
+ tun_entry->item.spec = tun_entry;
+ tun_entry->item.last = NULL;
+ tun_entry->item.mask = NULL;
+ return 0;
}
-/* This function will be called if inner tunnel flow request comes after
- * the outer tunnel flow request.
- */
-static int32_t
-ulp_post_process_inner_tun_flow(struct ulp_rte_parser_params *params,
- struct bnxt_tun_cache_entry *tun_entry)
+struct bnxt_flow_app_tun_ent *
+ulp_app_tun_match_entry(struct bnxt_ulp_context *ulp_ctx,
+ const void *ctx)
{
- memcpy(¶ms->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX],
- tun_entry->t_dmac, RTE_ETHER_ADDR_LEN);
+ struct bnxt_flow_app_tun_ent *tun_ent_list;
+ int32_t i;
- params->parent_fid = tun_entry->outer_tun_flow_id;
+ tun_ent_list = bnxt_ulp_cntxt_ptr2_app_tun_list_get(ulp_ctx);
+ if (!tun_ent_list) {
+ BNXT_TF_DBG(ERR, "unable to get the app tunnel list\n");
+ return NULL;
+ }
- return BNXT_TF_RC_NORMAL;
+ for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {
+ if (&tun_ent_list[i] == ctx)
+ return &tun_ent_list[i];
+ }
+ return NULL;
}
static int32_t
@@ -229,203 +115,116 @@ ulp_get_tun_entry(struct ulp_rte_parser_params *params,
struct bnxt_tun_cache_entry **tun_entry,
uint16_t *tun_idx)
{
- int i, first_free_entry = BNXT_ULP_TUN_ENTRY_INVALID;
+ int32_t i, first_free_entry = BNXT_ULP_TUN_ENTRY_INVALID;
struct bnxt_tun_cache_entry *tun_tbl;
- bool tun_entry_found = false, free_entry_found = false;
+ uint32_t dip_idx, dmac_idx, use_ipv4 = 0;
tun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(params->ulp_ctx);
- if (!tun_tbl)
+ if (!tun_tbl) {
+ BNXT_TF_DBG(ERR, "Error: could not get Tunnel table\n");
return BNXT_TF_RC_ERROR;
+ }
+
+ /* get the outer destination ip field index */
+ dip_idx = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID);
+ dmac_idx = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID);
+ if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV4))
+ use_ipv4 = 1;
for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {
- if (!memcmp(&tun_tbl[i].t_dst_ip,
- ¶ms->hdr_field[ULP_TUN_O_IPV4_DIP_INDEX].spec,
- sizeof(rte_be32_t)) ||
- !memcmp(&tun_tbl[i].t_dst_ip6,
- ¶ms->hdr_field[ULP_TUN_O_IPV6_DIP_INDEX].spec,
- 16)) {
- tun_entry_found = true;
- break;
+ if (!tun_tbl[i].t_dst_ip_valid) {
+ if (first_free_entry == BNXT_ULP_TUN_ENTRY_INVALID)
+ first_free_entry = i;
+ continue;
}
-
- if (!tun_tbl[i].t_dst_ip_valid && !free_entry_found) {
- first_free_entry = i;
- free_entry_found = true;
+ /* match on the destination ip of the tunnel */
+ if ((use_ipv4 && !memcmp(&tun_tbl[i].t_dst_ip,
+ params->hdr_field[dip_idx].spec,
+ sizeof(rte_be32_t))) ||
+ (!use_ipv4 &&
+ !memcmp(tun_tbl[i].t_dst_ip6,
+ params->hdr_field[dip_idx].spec,
+ sizeof(((struct bnxt_tun_cache_entry *)
+ NULL)->t_dst_ip6)))) {
+ *tun_entry = &tun_tbl[i];
+ *tun_idx = i;
+ return 0;
}
}
-
- if (tun_entry_found) {
- *tun_entry = &tun_tbl[i];
- *tun_idx = i;
- } else {
- if (first_free_entry == BNXT_ULP_TUN_ENTRY_INVALID)
- return BNXT_TF_RC_ERROR;
- *tun_entry = &tun_tbl[first_free_entry];
- *tun_idx = first_free_entry;
- }
-
- return 0;
-}
-
-int32_t
-ulp_post_process_tun_flow(struct ulp_rte_parser_params *params)
-{
- bool inner_tun_sig, cache_inner_tun_flow;
- bool outer_tun_reject, outer_tun_flow, inner_tun_flow;
- enum bnxt_ulp_tun_flow_state flow_state;
- struct bnxt_tun_cache_entry *tun_entry;
- uint32_t l3_tun, l3_tun_decap;
- uint16_t tun_idx;
- int rc;
-
- /* Computational fields that indicate it's a TUNNEL DECAP flow */
- l3_tun = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_TUN);
- l3_tun_decap = ULP_COMP_FLD_IDX_RD(params,
- BNXT_ULP_CF_IDX_L3_TUN_DECAP);
- if (!l3_tun)
- return BNXT_TF_RC_NORMAL;
-
- rc = ulp_get_tun_entry(params, &tun_entry, &tun_idx);
- if (rc == BNXT_TF_RC_ERROR)
- return rc;
-
- if (params->port_id >= RTE_MAX_ETHPORTS)
+ if (first_free_entry == BNXT_ULP_TUN_ENTRY_INVALID) {
+ BNXT_TF_DBG(ERR, "Error: No entry available in tunnel table\n");
return BNXT_TF_RC_ERROR;
- flow_state = tun_entry->tun_flow_info[params->port_id].state;
- /* Outer tunnel flow validation */
- outer_tun_flow = BNXT_OUTER_TUN_FLOW(l3_tun, params);
- outer_tun_reject = BNXT_REJECT_OUTER_TUN_FLOW(flow_state,
- outer_tun_flow);
-
- /* Inner tunnel flow validation */
- inner_tun_sig = BNXT_INNER_TUN_SIGNATURE(l3_tun, l3_tun_decap, params);
- cache_inner_tun_flow = BNXT_CACHE_INNER_TUN_FLOW(flow_state,
- inner_tun_sig);
- inner_tun_flow = BNXT_INNER_TUN_FLOW(flow_state, inner_tun_sig);
-
- if (outer_tun_reject) {
- tun_entry->outer_tun_rej_cnt++;
- BNXT_TF_DBG(ERR,
- "Tunnel F1 flow rejected, COUNT: %d\n",
- tun_entry->outer_tun_rej_cnt);
}
- if (outer_tun_reject)
- return BNXT_TF_RC_ERROR;
- else if (cache_inner_tun_flow)
- return ulp_post_process_cache_inner_tun_flow(params, tun_entry);
- else if (outer_tun_flow)
- return ulp_post_process_outer_tun_flow(params, tun_entry,
- tun_idx);
- else if (inner_tun_flow)
- return ulp_post_process_inner_tun_flow(params, tun_entry);
- else
- return BNXT_TF_RC_NORMAL;
-}
+ *tun_idx = first_free_entry;
+ *tun_entry = &tun_tbl[first_free_entry];
+ tun_tbl[first_free_entry].t_dst_ip_valid = true;
-void
-ulp_tun_tbl_init(struct bnxt_tun_cache_entry *tun_tbl)
-{
- struct ulp_per_port_flow_info *flow_info;
- int i, j;
+ /* Update the destination ip and mac */
+ if (use_ipv4)
+ memcpy(&tun_tbl[first_free_entry].t_dst_ip,
+ params->hdr_field[dip_idx].spec, sizeof(rte_be32_t));
+ else
+ memcpy(tun_tbl[first_free_entry].t_dst_ip6,
+ params->hdr_field[dip_idx].spec,
+ sizeof(((struct bnxt_tun_cache_entry *)
+ NULL)->t_dst_ip6));
+ memcpy(tun_tbl[first_free_entry].t_dmac,
+ params->hdr_field[dmac_idx].spec, RTE_ETHER_ADDR_LEN);
- for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {
- for (j = 0; j < RTE_MAX_ETHPORTS; j++) {
- flow_info = &tun_tbl[i].tun_flow_info[j];
- STAILQ_INIT(&flow_info->tun_i_prms_list);
- }
- }
+ return 0;
}
+/* Tunnel API to delete the tunnel entry */
void
-ulp_clear_tun_entry(struct bnxt_tun_cache_entry *tun_tbl, uint8_t tun_idx)
+ulp_tunnel_offload_entry_clear(struct bnxt_tun_cache_entry *tun_tbl,
+ uint8_t tun_idx)
{
- struct ulp_rte_parser_params *inner_params;
- struct ulp_per_port_flow_info *flow_info;
- int j;
-
- for (j = 0; j < RTE_MAX_ETHPORTS; j++) {
- flow_info = &tun_tbl[tun_idx].tun_flow_info[j];
- STAILQ_FOREACH(inner_params,
- &flow_info->tun_i_prms_list,
- next) {
- STAILQ_REMOVE(&flow_info->tun_i_prms_list,
- inner_params,
- ulp_rte_parser_params, next);
- rte_free(inner_params);
- }
- }
-
- memset(&tun_tbl[tun_idx], 0,
- sizeof(struct bnxt_tun_cache_entry));
-
- for (j = 0; j < RTE_MAX_ETHPORTS; j++) {
- flow_info = &tun_tbl[tun_idx].tun_flow_info[j];
- STAILQ_INIT(&flow_info->tun_i_prms_list);
- }
+ memset(&tun_tbl[tun_idx], 0, sizeof(struct bnxt_tun_cache_entry));
}
-static bool
-ulp_chk_and_rem_tun_i_flow(struct bnxt_tun_cache_entry *tun_entry,
- struct ulp_per_port_flow_info *flow_info,
- uint32_t fid)
+/* Tunnel API to perform tunnel offload process when there is F1/F2 flows */
+int32_t
+ulp_tunnel_offload_process(struct ulp_rte_parser_params *params)
{
- struct ulp_rte_parser_params *inner_params;
- int j;
-
- STAILQ_FOREACH(inner_params,
- &flow_info->tun_i_prms_list,
- next) {
- if (inner_params->fid == fid) {
- STAILQ_REMOVE(&flow_info->tun_i_prms_list,
- inner_params,
- ulp_rte_parser_params,
- next);
- rte_free(inner_params);
- flow_info->tun_i_cnt--;
- /* When a dpdk application offloads a duplicate
- * tunnel inner flow on a port that it is not
- * destined to, there won't be a tunnel outer flow
- * associated with these duplicate tunnel inner flows.
- * So, when the last tunnel inner flow ages out, the
- * driver has to clear the tunnel entry, otherwise
- * the tunnel entry cannot be reused.
- */
- if (!flow_info->tun_i_cnt &&
- flow_info->state != BNXT_ULP_FLOW_STATE_TUN_O_OFFLD) {
- memset(tun_entry, 0,
- sizeof(struct bnxt_tun_cache_entry));
- for (j = 0; j < RTE_MAX_ETHPORTS; j++)
- STAILQ_INIT(&flow_info->tun_i_prms_list);
- }
- return true;
- }
- }
+ struct bnxt_tun_cache_entry *tun_entry;
+ uint16_t tun_idx;
+ int32_t rc = BNXT_TF_RC_SUCCESS;
- return false;
-}
+ /* Perform the tunnel offload only for F1 and F2 flows */
+ if (!ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
+ BNXT_ULP_HDR_BIT_F1) &&
+ !ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
+ BNXT_ULP_HDR_BIT_F2))
+ return rc;
-/* When a dpdk application offloads the same tunnel inner flow
- * on all the uplink ports, a tunnel inner flow entry is cached
- * even if it is not for the right uplink port. Such tunnel
- * inner flows will eventually get aged out as there won't be
- * any traffic on these ports. When such a flow destroy is
- * called, cleanup the tunnel inner flow entry.
- */
-void
-ulp_clear_tun_inner_entry(struct bnxt_tun_cache_entry *tun_tbl, uint32_t fid)
-{
- struct ulp_per_port_flow_info *flow_info;
- int i, j;
+ /* search for the tunnel entry if not found create one */
+ rc = ulp_get_tun_entry(params, &tun_entry, &tun_idx);
+ if (rc == BNXT_TF_RC_ERROR)
+ return rc;
- for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {
- if (!tun_tbl[i].t_dst_ip_valid)
- continue;
- for (j = 0; j < RTE_MAX_ETHPORTS; j++) {
- flow_info = &tun_tbl[i].tun_flow_info[j];
- if (ulp_chk_and_rem_tun_i_flow(&tun_tbl[i],
- flow_info, fid) == true)
- return;
- }
+ /* Tunnel offload for the outer Tunnel flow */
+ if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
+ BNXT_ULP_HDR_BIT_F1)) {
+ /* Reset the JUMP action bit in the action bitmap as we don't
+ * offload this action.
+ */
+ ULP_BITMAP_RESET(params->act_bitmap.bits,
+ BNXT_ULP_ACT_BIT_JUMP);
+ params->parent_flow = true;
+ params->tun_idx = tun_idx;
+ tun_entry->outer_tun_flow_id = params->fid;
+ } else if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
+ BNXT_ULP_HDR_BIT_F2)) {
+ ULP_BITMAP_RESET(params->hdr_bitmap.bits,
+ BNXT_ULP_HDR_BIT_F2);
+ /* add the vxlan decap action for F2 flows */
+ ULP_BITMAP_SET(params->act_bitmap.bits,
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP);
+ params->child_flow = true;
+ params->tun_idx = tun_idx;
+ params->parent_flow = false;
}
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_TUNNEL_ID, tun_idx);
+ return rc;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.h b/drivers/net/bnxt/tf_ulp/ulp_tun.h
index 898071bfe7..0fc2ac39d1 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_tun.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_tun.h
@@ -8,7 +8,6 @@
#include <inttypes.h>
#include <stdbool.h>
-#include <sys/queue.h>
#include "rte_version.h"
#include "rte_ethdev.h"
@@ -16,60 +15,6 @@
#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
-#define BNXT_OUTER_TUN_FLOW(l3_tun, params) \
- ((l3_tun) && \
- ULP_BITMAP_ISSET((params)->act_bitmap.bits, \
- BNXT_ULP_ACT_BIT_JUMP))
-#define BNXT_INNER_TUN_SIGNATURE(l3_tun, l3_tun_decap, params) \
- ((l3_tun) && (l3_tun_decap) && \
- !ULP_BITMAP_ISSET((params)->hdr_bitmap.bits, \
- BNXT_ULP_HDR_BIT_O_ETH))
-
-#define BNXT_CACHE_INNER_TUN_FLOW(state, inner_tun_sig) \
- ((state) == BNXT_ULP_FLOW_STATE_NORMAL && (inner_tun_sig))
-#define BNXT_INNER_TUN_FLOW(state, inner_tun_sig) \
- ((state) == BNXT_ULP_FLOW_STATE_TUN_O_OFFLD && (inner_tun_sig))
-
-/* It is invalid to get another outer flow offload request
- * for the same tunnel, while the outer flow is already offloaded.
- */
-#define BNXT_REJECT_OUTER_TUN_FLOW(state, outer_tun_sig) \
- ((state) == BNXT_ULP_FLOW_STATE_TUN_O_OFFLD && (outer_tun_sig))
-
-#define ULP_TUN_O_DMAC_HDR_FIELD_INDEX 1
-#define ULP_TUN_O_IPV4_DIP_INDEX 19
-#define ULP_TUN_O_IPV6_DIP_INDEX 17
-
-/* When a flow offload request comes the following state transitions
- * happen based on the order in which the outer & inner flow offload
- * requests arrive.
- *
- * If inner tunnel flow offload request arrives first then the flow
- * state will remain in BNXT_ULP_FLOW_STATE_NORMAL state.
- * The following outer tunnel flow offload request will change the
- * state of the flow to BNXT_ULP_FLOW_STATE_TUN_O_OFFLD from
- * BNXT_ULP_FLOW_STATE_NORMAL.
- *
- * If outer tunnel flow offload request arrives first then the flow state
- * will change from BNXT_ULP_FLOW_STATE_NORMAL to
- * BNXT_ULP_FLOW_STATE_TUN_O_OFFLD.
- *
- * Once the flow state is in BNXT_ULP_FLOW_STATE_TUN_O_OFFLD, any inner
- * tunnel flow offload requests after that point will be treated as a
- * normal flow and the tunnel flow state remains in
- * BNXT_ULP_FLOW_STATE_TUN_O_OFFLD
- */
-enum bnxt_ulp_tun_flow_state {
- BNXT_ULP_FLOW_STATE_NORMAL = 0,
- BNXT_ULP_FLOW_STATE_TUN_O_OFFLD,
-};
-
-struct ulp_per_port_flow_info {
- enum bnxt_ulp_tun_flow_state state;
- uint32_t tun_i_cnt;
- STAILQ_HEAD(, ulp_rte_parser_params) tun_i_prms_list;
-};
-
struct bnxt_tun_cache_entry {
bool t_dst_ip_valid;
uint8_t t_dmac[RTE_ETHER_ADDR_LEN];
@@ -78,17 +23,39 @@ struct bnxt_tun_cache_entry {
uint8_t t_dst_ip6[16];
};
uint32_t outer_tun_flow_id;
- uint16_t outer_tun_rej_cnt;
- struct ulp_per_port_flow_info tun_flow_info[RTE_MAX_ETHPORTS];
};
-void
-ulp_tun_tbl_init(struct bnxt_tun_cache_entry *tun_tbl);
+struct bnxt_flow_app_tun_ent {
+ struct rte_flow_tunnel app_tunnel;
+ uint32_t tun_id;
+ uint32_t ref_cnt;
+ struct rte_flow_action action;
+ struct rte_flow_item item;
+};
+
+int32_t
+ulp_app_tun_search_entry(struct bnxt_ulp_context *ulp_ctx,
+ struct rte_flow_tunnel *app_tunnel,
+ struct bnxt_flow_app_tun_ent **tun_entry);
void
-ulp_clear_tun_entry(struct bnxt_tun_cache_entry *tun_tbl, uint8_t tun_idx);
+ulp_app_tun_entry_delete(struct bnxt_flow_app_tun_ent *tun_entry);
+int32_t
+ulp_app_tun_entry_set_decap_action(struct bnxt_flow_app_tun_ent *tun_entry);
+
+int32_t
+ulp_app_tun_entry_set_decap_item(struct bnxt_flow_app_tun_ent *tun_entry);
+
+struct bnxt_flow_app_tun_ent *
+ulp_app_tun_match_entry(struct bnxt_ulp_context *ulp_ctx, const void *ctx);
+
+/* Tunnel API to delete the tunnel entry */
void
-ulp_clear_tun_inner_entry(struct bnxt_tun_cache_entry *tun_tbl, uint32_t fid);
+ulp_tunnel_offload_entry_clear(struct bnxt_tun_cache_entry *tun_tbl,
+ uint8_t tun_idx);
+
+int32_t
+ulp_tunnel_offload_process(struct ulp_rte_parser_params *params);
#endif
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* Re: [dpdk-dev] [PATCH v4 06/13] net/bnxt: add support for tunnel offload API
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 06/13] net/bnxt: add support for tunnel offload API Venkat Duvvuru
@ 2021-09-28 12:43 ` Ferruh Yigit
2021-09-28 15:46 ` Thomas Monjalon
2021-09-28 21:32 ` Ajit Khaparde
0 siblings, 2 replies; 83+ messages in thread
From: Ferruh Yigit @ 2021-09-28 12:43 UTC (permalink / raw)
To: Venkat Duvvuru, dev, Ajit Khaparde
Cc: Kishore Padmanabha, jerinj, Thomas Monjalon
On 9/20/2021 8:42 AM, Venkat Duvvuru wrote:
> From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
>
> Add support for tunnel offload APIs. Specifically the following
> are supported.
> tunnel_decap_set, tunnel_match, tunnel_action_decap_release,
> tunnel_item_release.
>
> This provides support for VXLAN decap action where two flows
> can indicate tunnel offload rule. The first flow indicates the
> tunnel properties and second flow indicates the inner packet
> structure. The templates are updated to support this
> feature.
>
> Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
> Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com>
> Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Hi Ajit,
Following warning is reported by Jerin & Thomas:
$ ./devtools/check-doc-vs-code.sh
rte_flow doc out of sync for bnxt
action shared
This is mainly saying 'RTE_FLOW_ACTION_TYPE_SHARED' flow action is supported but
not documented. But from code I am not sure if shared action is used, there is
only one range check using this enum in the code, can you please clarify?
If it is supported I can update the documentation.
Thanks,
ferruh
^ permalink raw reply [flat|nested] 83+ messages in thread* Re: [dpdk-dev] [PATCH v4 06/13] net/bnxt: add support for tunnel offload API
2021-09-28 12:43 ` Ferruh Yigit
@ 2021-09-28 15:46 ` Thomas Monjalon
2021-09-28 15:57 ` Ferruh Yigit
2021-09-28 21:32 ` Ajit Khaparde
1 sibling, 1 reply; 83+ messages in thread
From: Thomas Monjalon @ 2021-09-28 15:46 UTC (permalink / raw)
To: Venkat Duvvuru, Ajit Khaparde, Ferruh Yigit
Cc: dev, Kishore Padmanabha, jerinj
28/09/2021 14:43, Ferruh Yigit:
> On 9/20/2021 8:42 AM, Venkat Duvvuru wrote:
> > From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
> >
> > Add support for tunnel offload APIs. Specifically the following
> > are supported.
> > tunnel_decap_set, tunnel_match, tunnel_action_decap_release,
> > tunnel_item_release.
> >
> > This provides support for VXLAN decap action where two flows
> > can indicate tunnel offload rule. The first flow indicates the
> > tunnel properties and second flow indicates the inner packet
> > structure. The templates are updated to support this
> > feature.
> >
> > Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
> > Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
> > Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com>
> > Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
>
>
> Hi Ajit,
>
> Following warning is reported by Jerin & Thomas:
>
> $ ./devtools/check-doc-vs-code.sh
> rte_flow doc out of sync for bnxt
> action shared
>
>
> This is mainly saying 'RTE_FLOW_ACTION_TYPE_SHARED' flow action is supported but
> not documented. But from code I am not sure if shared action is used, there is
> only one range check using this enum in the code, can you please clarify?
> If it is supported I can update the documentation.
Please fix it in the right commit atomically.
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [dpdk-dev] [PATCH v4 06/13] net/bnxt: add support for tunnel offload API
2021-09-28 15:46 ` Thomas Monjalon
@ 2021-09-28 15:57 ` Ferruh Yigit
0 siblings, 0 replies; 83+ messages in thread
From: Ferruh Yigit @ 2021-09-28 15:57 UTC (permalink / raw)
To: Thomas Monjalon, Venkat Duvvuru, Ajit Khaparde
Cc: dev, Kishore Padmanabha, jerinj
On 9/28/2021 4:46 PM, Thomas Monjalon wrote:
> 28/09/2021 14:43, Ferruh Yigit:
>> On 9/20/2021 8:42 AM, Venkat Duvvuru wrote:
>>> From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
>>>
>>> Add support for tunnel offload APIs. Specifically the following
>>> are supported.
>>> tunnel_decap_set, tunnel_match, tunnel_action_decap_release,
>>> tunnel_item_release.
>>>
>>> This provides support for VXLAN decap action where two flows
>>> can indicate tunnel offload rule. The first flow indicates the
>>> tunnel properties and second flow indicates the inner packet
>>> structure. The templates are updated to support this
>>> feature.
>>>
>>> Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
>>> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
>>> Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com>
>>> Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
>>
>>
>> Hi Ajit,
>>
>> Following warning is reported by Jerin & Thomas:
>>
>> $ ./devtools/check-doc-vs-code.sh
>> rte_flow doc out of sync for bnxt
>> action shared
>>
>>
>> This is mainly saying 'RTE_FLOW_ACTION_TYPE_SHARED' flow action is supported but
>> not documented. But from code I am not sure if shared action is used, there is
>> only one range check using this enum in the code, can you please clarify?
>> If it is supported I can update the documentation.
>
> Please fix it in the right commit atomically.
>
Sure I will fix it in the relevant commit, but first I want to be sure what
script detected is correct or not.
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [dpdk-dev] [PATCH v4 06/13] net/bnxt: add support for tunnel offload API
2021-09-28 12:43 ` Ferruh Yigit
2021-09-28 15:46 ` Thomas Monjalon
@ 2021-09-28 21:32 ` Ajit Khaparde
2021-09-29 8:20 ` Thomas Monjalon
1 sibling, 1 reply; 83+ messages in thread
From: Ajit Khaparde @ 2021-09-28 21:32 UTC (permalink / raw)
To: Ferruh Yigit
Cc: Venkat Duvvuru, dpdk-dev, Kishore Padmanabha, jerinj, Thomas Monjalon
[-- Attachment #1: Type: text/plain, Size: 1588 bytes --]
On Tue, Sep 28, 2021 at 5:43 AM Ferruh Yigit <ferruh.yigit@intel.com> wrote:
>
> On 9/20/2021 8:42 AM, Venkat Duvvuru wrote:
> > From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
> >
> > Add support for tunnel offload APIs. Specifically the following
> > are supported.
> > tunnel_decap_set, tunnel_match, tunnel_action_decap_release,
> > tunnel_item_release.
> >
> > This provides support for VXLAN decap action where two flows
> > can indicate tunnel offload rule. The first flow indicates the
> > tunnel properties and second flow indicates the inner packet
> > structure. The templates are updated to support this
> > feature.
> >
> > Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
> > Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
> > Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com>
> > Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
>
>
> Hi Ajit,
>
> Following warning is reported by Jerin & Thomas:
>
> $ ./devtools/check-doc-vs-code.sh
> rte_flow doc out of sync for bnxt
> action shared
>
>
> This is mainly saying 'RTE_FLOW_ACTION_TYPE_SHARED' flow action is supported but
> not documented. But from code I am not sure if shared action is used, there is
> only one range check using this enum in the code, can you please clarify?
Correct. RTE_FLOW_ACTION_TYPE_SHARED is being used only for a range check.
It is not really a supported action right now as far as the code is concerned.
As of now, no document update is necessary. Thanks
> If it is supported I can update the documentation.
>
> Thanks,
> ferruh
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [dpdk-dev] [PATCH v4 06/13] net/bnxt: add support for tunnel offload API
2021-09-28 21:32 ` Ajit Khaparde
@ 2021-09-29 8:20 ` Thomas Monjalon
2021-09-29 9:44 ` Ferruh Yigit
0 siblings, 1 reply; 83+ messages in thread
From: Thomas Monjalon @ 2021-09-29 8:20 UTC (permalink / raw)
To: Ferruh Yigit, Ajit Khaparde
Cc: Venkat Duvvuru, dpdk-dev, Kishore Padmanabha, jerinj
28/09/2021 23:32, Ajit Khaparde:
> On Tue, Sep 28, 2021 at 5:43 AM Ferruh Yigit <ferruh.yigit@intel.com> wrote:
> > Following warning is reported by Jerin & Thomas:
> >
> > $ ./devtools/check-doc-vs-code.sh
> > rte_flow doc out of sync for bnxt
> > action shared
> >
> >
> > This is mainly saying 'RTE_FLOW_ACTION_TYPE_SHARED' flow action is supported but
> > not documented. But from code I am not sure if shared action is used, there is
> > only one range check using this enum in the code, can you please clarify?
>
> Correct. RTE_FLOW_ACTION_TYPE_SHARED is being used only for a range check.
> It is not really a supported action right now as far as the code is concerned.
> As of now, no document update is necessary. Thanks
You need to update something to make the check OK.
If it is a false positive, it can be handled in the script,
but we cannot let the script returning an error.
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [dpdk-dev] [PATCH v4 06/13] net/bnxt: add support for tunnel offload API
2021-09-29 8:20 ` Thomas Monjalon
@ 2021-09-29 9:44 ` Ferruh Yigit
2021-09-29 16:44 ` Ajit Khaparde
0 siblings, 1 reply; 83+ messages in thread
From: Ferruh Yigit @ 2021-09-29 9:44 UTC (permalink / raw)
To: Thomas Monjalon, Ajit Khaparde
Cc: Venkat Duvvuru, dpdk-dev, Kishore Padmanabha, jerinj
On 9/29/2021 9:20 AM, Thomas Monjalon wrote:
> 28/09/2021 23:32, Ajit Khaparde:
>> On Tue, Sep 28, 2021 at 5:43 AM Ferruh Yigit <ferruh.yigit@intel.com> wrote:
>>> Following warning is reported by Jerin & Thomas:
>>>
>>> $ ./devtools/check-doc-vs-code.sh
>>> rte_flow doc out of sync for bnxt
>>> action shared
>>>
>>>
>>> This is mainly saying 'RTE_FLOW_ACTION_TYPE_SHARED' flow action is supported but
>>> not documented. But from code I am not sure if shared action is used, there is
>>> only one range check using this enum in the code, can you please clarify?
>>
>> Correct. RTE_FLOW_ACTION_TYPE_SHARED is being used only for a range check.
>> It is not really a supported action right now as far as the code is concerned.
>> As of now, no document update is necessary. Thanks
>
> You need to update something to make the check OK.
> If it is a false positive, it can be handled in the script,
> but we cannot let the script returning an error.
>
>
I will add following exception to the script (suggested by Thomas) in the next-net:
diff --git a/devtools/parse-flow-support.sh b/devtools/parse-flow-support.sh
index 8462abe53603..63c0b20e234f 100755
--- a/devtools/parse-flow-support.sh
+++ b/devtools/parse-flow-support.sh
@@ -25,7 +25,8 @@ exclude() # <pattern>
$dir/tf_ulp/ulp_rte_handler_tbl.c |
grep -wo "$1[[:alnum:]_]*" | sort -u |
tr '\n' '|' | sed 's,.$,\n,')
- grep -vE "$filter";;
+ exceptions='RTE_FLOW_ACTION_TYPE_SHARED'
+ grep -vE "$filter" | grep -vE $exceptions;;
*) cat
esac
}
^ permalink raw reply [flat|nested] 83+ messages in thread* Re: [dpdk-dev] [PATCH v4 06/13] net/bnxt: add support for tunnel offload API
2021-09-29 9:44 ` Ferruh Yigit
@ 2021-09-29 16:44 ` Ajit Khaparde
0 siblings, 0 replies; 83+ messages in thread
From: Ajit Khaparde @ 2021-09-29 16:44 UTC (permalink / raw)
To: Ferruh Yigit
Cc: Thomas Monjalon, Venkat Duvvuru, dpdk-dev, Kishore Padmanabha, jerinj
[-- Attachment #1: Type: text/plain, Size: 1863 bytes --]
On Wed, Sep 29, 2021 at 2:44 AM Ferruh Yigit <ferruh.yigit@intel.com> wrote:
>
> On 9/29/2021 9:20 AM, Thomas Monjalon wrote:
> > 28/09/2021 23:32, Ajit Khaparde:
> >> On Tue, Sep 28, 2021 at 5:43 AM Ferruh Yigit <ferruh.yigit@intel.com> wrote:
> >>> Following warning is reported by Jerin & Thomas:
> >>>
> >>> $ ./devtools/check-doc-vs-code.sh
> >>> rte_flow doc out of sync for bnxt
> >>> action shared
> >>>
> >>>
> >>> This is mainly saying 'RTE_FLOW_ACTION_TYPE_SHARED' flow action is supported but
> >>> not documented. But from code I am not sure if shared action is used, there is
> >>> only one range check using this enum in the code, can you please clarify?
> >>
> >> Correct. RTE_FLOW_ACTION_TYPE_SHARED is being used only for a range check.
> >> It is not really a supported action right now as far as the code is concerned.
> >> As of now, no document update is necessary. Thanks
> >
> > You need to update something to make the check OK.
> > If it is a false positive, it can be handled in the script,
> > but we cannot let the script returning an error.
> >
> >
>
> I will add following exception to the script (suggested by Thomas) in the next-net:
>
> diff --git a/devtools/parse-flow-support.sh b/devtools/parse-flow-support.sh
> index 8462abe53603..63c0b20e234f 100755
> --- a/devtools/parse-flow-support.sh
> +++ b/devtools/parse-flow-support.sh
> @@ -25,7 +25,8 @@ exclude() # <pattern>
> $dir/tf_ulp/ulp_rte_handler_tbl.c |
> grep -wo "$1[[:alnum:]_]*" | sort -u |
> tr '\n' '|' | sed 's,.$,\n,')
> - grep -vE "$filter";;
> + exceptions='RTE_FLOW_ACTION_TYPE_SHARED'
> + grep -vE "$filter" | grep -vE $exceptions;;
> *) cat
> esac
> }
ACK
>
>
^ permalink raw reply [flat|nested] 83+ messages in thread
* [dpdk-dev] [PATCH v4 07/13] net/bnxt: add support for dynamic encap action
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 " Venkat Duvvuru
` (5 preceding siblings ...)
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 06/13] net/bnxt: add support for tunnel offload API Venkat Duvvuru
@ 2021-09-20 7:42 ` Venkat Duvvuru
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 08/13] net/bnxt: add wild card TCAM byte order for Thor Venkat Duvvuru
` (6 subsequent siblings)
13 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-20 7:42 UTC (permalink / raw)
To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
The encapsulation record processing is enhanced to handle data
dynamically. Different combinations of VXLAN encapsulation using
no VLAN or single or double VLAN can be supported and also supports
both IPv4 and IPv6 versions.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 25 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 2 +
.../generic_templates/ulp_template_db_enum.h | 44 +-
.../generic_templates/ulp_template_db_tbl.c | 8 +-
.../ulp_template_db_thor_act.c | 4 +-
.../ulp_template_db_thor_class.c | 46 +-
.../ulp_template_db_wh_plus_act.c | 1700 ++++++++++++-----
.../ulp_template_db_wh_plus_class.c | 222 +--
drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 4 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 2 +-
drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 152 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.h | 4 +
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 337 ++--
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 2 +
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 10 +-
drivers/net/bnxt/tf_ulp/ulp_utils.c | 73 +-
drivers/net/bnxt/tf_ulp/ulp_utils.h | 27 +-
18 files changed, 1716 insertions(+), 948 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index dfafd9ff5b..3b86410fb1 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -830,13 +830,12 @@ ulp_ctx_init(struct bnxt *bp,
goto error_deinit;
}
- /* TODO: For now we are overriding to APP:1 on this branch*/
- bp->app_id = 1;
rc = bnxt_ulp_cntxt_app_id_set(bp->ulp_ctx, bp->app_id);
if (rc) {
BNXT_TF_DBG(ERR, "Unable to set app_id for ULP init.\n");
goto error_deinit;
}
+ BNXT_TF_DBG(DEBUG, "Ulp initialized with app id %d\n", bp->app_id);
rc = bnxt_ulp_cntxt_app_caps_init(bp->ulp_ctx, bp->app_id, devid);
if (rc) {
@@ -1393,13 +1392,17 @@ bnxt_ulp_port_init(struct bnxt *bp)
uint32_t ulp_flags;
int32_t rc = 0;
- if (!bp || !BNXT_TRUFLOW_EN(bp))
- return rc;
-
if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
BNXT_TF_DBG(ERR,
"Skip ulp init for port: %d, not a TVF or PF\n",
- bp->eth_dev->data->port_id);
+ bp->eth_dev->data->port_id);
+ return rc;
+ }
+
+ if (!BNXT_TRUFLOW_EN(bp)) {
+ BNXT_TF_DBG(ERR,
+ "Skip ulp init for port: %d, truflow is not enabled\n",
+ bp->eth_dev->data->port_id);
return rc;
}
@@ -1520,9 +1523,6 @@ bnxt_ulp_port_deinit(struct bnxt *bp)
struct rte_pci_device *pci_dev;
struct rte_pci_addr *pci_addr;
- if (!BNXT_TRUFLOW_EN(bp))
- return;
-
if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
BNXT_TF_DBG(ERR,
"Skip ULP deinit port:%d, not a TVF or PF\n",
@@ -1530,6 +1530,13 @@ bnxt_ulp_port_deinit(struct bnxt *bp)
return;
}
+ if (!BNXT_TRUFLOW_EN(bp)) {
+ BNXT_TF_DBG(ERR,
+ "Skip ULP deinit for port:%d, truflow is not enabled\n",
+ bp->eth_dev->data->port_id);
+ return;
+ }
+
if (!bp->ulp_ctx) {
BNXT_TF_DBG(DEBUG, "ulp ctx already de-allocated\n");
return;
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
index 3daf5942e8..413e4c3b26 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
@@ -96,7 +96,9 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms,
mapper_cparms->act_tid = params->act_tmpl;
mapper_cparms->func_id = params->func_id;
mapper_cparms->hdr_bitmap = ¶ms->hdr_bitmap;
+ mapper_cparms->enc_hdr_bitmap = ¶ms->enc_hdr_bitmap;
mapper_cparms->hdr_field = params->hdr_field;
+ mapper_cparms->enc_field = params->enc_field;
mapper_cparms->comp_fld = params->comp_fld;
mapper_cparms->act = ¶ms->act_bitmap;
mapper_cparms->act_prop = ¶ms->act_prop;
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
index e55d0923a5..9010d9a749 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 20 11:56:39 2021 */
+/* date: Thu May 27 17:35:19 2021 */
#ifndef ULP_TEMPLATE_DB_H_
#define ULP_TEMPLATE_DB_H_
@@ -41,7 +41,7 @@
#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 89
#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 600
#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 26
-#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 619
+#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 618
#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 49
#define ULP_THOR_CLASS_TMPL_LIST_SIZE 6
#define ULP_THOR_CLASS_TBL_LIST_SIZE 33
@@ -53,7 +53,7 @@
#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 35
#define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2
#define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 1
-#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 512
+#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 527
#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 39
#define ULP_THOR_ACT_TMPL_LIST_SIZE 7
#define ULP_THOR_ACT_TBL_LIST_SIZE 2
@@ -229,7 +229,9 @@ enum bnxt_ulp_cond_opc {
BNXT_ULP_COND_OPC_ACT_PAT_MATCH = 11,
BNXT_ULP_COND_OPC_EXT_MEM_IS_SET = 12,
BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET = 13,
- BNXT_ULP_COND_OPC_LAST = 14
+ BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET = 14,
+ BNXT_ULP_COND_OPC_ENC_HDR_BIT_NOT_SET = 15,
+ BNXT_ULP_COND_OPC_LAST = 16
};
enum bnxt_ulp_critical_resource {
@@ -257,6 +259,36 @@ enum bnxt_ulp_direction {
BNXT_ULP_DIRECTION_LAST = 2
};
+enum bnxt_ulp_enc_field {
+ BNXT_ULP_ENC_FIELD_ETH_DMAC = 0,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC = 1,
+ BNXT_ULP_ENC_FIELD_ETH_TYPE = 2,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TCI = 3,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TYPE = 4,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TCI = 5,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TYPE = 6,
+ BNXT_ULP_ENC_FIELD_IPV4_IHL = 7,
+ BNXT_ULP_ENC_FIELD_IPV4_TOS = 8,
+ BNXT_ULP_ENC_FIELD_IPV4_PKT_ID = 9,
+ BNXT_ULP_ENC_FIELD_IPV4_FRAG = 10,
+ BNXT_ULP_ENC_FIELD_IPV4_TTL = 11,
+ BNXT_ULP_ENC_FIELD_IPV4_PROTO = 12,
+ BNXT_ULP_ENC_FIELD_IPV4_SADDR = 13,
+ BNXT_ULP_ENC_FIELD_IPV4_DADDR = 14,
+ BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW = 15,
+ BNXT_ULP_ENC_FIELD_IPV6_PROTO = 16,
+ BNXT_ULP_ENC_FIELD_IPV6_TTL = 17,
+ BNXT_ULP_ENC_FIELD_IPV6_SADDR = 18,
+ BNXT_ULP_ENC_FIELD_IPV6_DADDR = 19,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT = 20,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT = 21,
+ BNXT_ULP_ENC_FIELD_VXLAN_FLAGS = 22,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 = 23,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI = 24,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 = 25,
+ BNXT_ULP_ENC_FIELD_LAST = 26
+};
+
enum bnxt_ulp_fdb_opc {
BNXT_ULP_FDB_OPC_PUSH_FID = 0,
BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE = 1,
@@ -304,7 +336,9 @@ enum bnxt_ulp_field_src {
BNXT_ULP_FIELD_SRC_SKIP = 13,
BNXT_ULP_FIELD_SRC_REJECT = 14,
BNXT_ULP_FIELD_SRC_PORT_TABLE = 15,
- BNXT_ULP_FIELD_SRC_LAST = 16
+ BNXT_ULP_FIELD_SRC_ENC_HDR_BIT = 16,
+ BNXT_ULP_FIELD_SRC_ENC_FIELD = 17,
+ BNXT_ULP_FIELD_SRC_LAST = 18
};
enum bnxt_ulp_func_opc {
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
index 58b4dba63c..b5bce6f4c7 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
@@ -198,7 +198,9 @@ const struct bnxt_ulp_template_device_tbls ulp_template_thor_tbls[] = {
struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
[BNXT_ULP_DEVICE_ID_WH_PLUS] = {
.description = "Whitney_Plus",
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .encap_byte_order = BNXT_ULP_BYTE_ORDER_BE,
.encap_byte_swap = 1,
.int_flow_db_num_entries = 16384,
.ext_flow_db_num_entries = 32768,
@@ -218,7 +220,9 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
},
[BNXT_ULP_DEVICE_ID_THOR] = {
.description = "Thor",
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .key_byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .encap_byte_order = BNXT_ULP_BYTE_ORDER_BE,
.encap_byte_swap = 1,
.int_flow_db_num_entries = 16384,
.ext_flow_db_num_entries = 32768,
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
index ce5a70b0c5..9faf25aaf0 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 13 18:15:56 2021 */
+/* date: Wed May 26 15:11:34 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -41,7 +41,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 0,
.result_bit_size = 64,
.result_num_fields = 1
@@ -62,7 +61,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 1,
.result_bit_size = 128,
.result_num_fields = 17
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
index d20c4197fa..ea9b9773a5 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 20 11:56:39 2021 */
+/* date: Wed May 26 15:11:34 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -59,7 +59,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 0,
.blob_key_bit_size = 10,
.key_bit_size = 10,
@@ -82,7 +81,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 1,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -104,7 +102,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 2,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -122,8 +119,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_start_idx = 5,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 1, , table: l2_cntxt_tcam.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -141,7 +137,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 7,
.blob_key_bit_size = 213,
.key_bit_size = 213,
@@ -166,7 +161,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 28,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -189,7 +183,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 33,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -207,8 +200,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_start_idx = 6,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 1, , table: fkb_select.l3_l4_wm */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -223,7 +215,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 10,
.result_bit_size = 106,
.result_num_fields = 106
@@ -246,7 +237,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 36,
.blob_key_bit_size = 94,
.key_bit_size = 94,
@@ -271,7 +261,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 79,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -297,7 +286,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_BE,
.key_start_idx = 82,
.blob_key_bit_size = 0,
.key_bit_size = 0,
@@ -322,7 +310,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 136,
.result_bit_size = 128,
.result_num_fields = 17
@@ -341,7 +328,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 196,
.blob_key_bit_size = 10,
.key_bit_size = 10,
@@ -364,7 +350,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 197,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -382,8 +367,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_start_idx = 9,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -403,7 +387,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 198,
.blob_key_bit_size = 213,
.key_bit_size = 213,
@@ -428,7 +411,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 219,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -450,7 +432,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 168,
.result_bit_size = 32,
.result_num_fields = 1
@@ -468,7 +449,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 169,
.result_bit_size = 32,
.result_num_fields = 1
@@ -482,8 +462,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 10,
.cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
{ /* class_tid: 4, , table: int_full_act_record.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -501,7 +480,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 170,
.result_bit_size = 128,
.result_num_fields = 17,
@@ -521,7 +499,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 220,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -539,8 +516,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_start_idx = 11,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -558,7 +534,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 221,
.blob_key_bit_size = 213,
.key_bit_size = 213,
@@ -582,7 +557,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 193,
.result_bit_size = 32,
.result_num_fields = 1
@@ -600,7 +574,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 194,
.result_bit_size = 32,
.result_num_fields = 1
@@ -621,7 +594,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 195,
.result_bit_size = 128,
.result_num_fields = 17,
@@ -640,7 +612,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 212,
.result_bit_size = 32,
.result_num_fields = 1
@@ -658,7 +629,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 213,
.result_bit_size = 32,
.result_num_fields = 1
@@ -679,7 +649,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 214,
.result_bit_size = 128,
.result_num_fields = 17,
@@ -701,7 +670,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .record_size = 16,
.result_start_idx = 231,
.result_bit_size = 0,
.result_num_fields = 0,
@@ -723,7 +692,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 242,
.result_bit_size = 128,
.result_num_fields = 17
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
index de924fe81a..578ede8bba 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Mon May 17 15:54:03 2021 */
+/* date: Tue Jun 1 16:05:30 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -90,7 +90,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 0,
.blob_key_bit_size = 1,
.key_bit_size = 1,
@@ -114,14 +113,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 0,
.result_bit_size = 64,
.result_num_fields = 1
},
{ /* act_tid: 1, , table: int_vtag_encap_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
.direction = TF_DIR_RX,
@@ -135,11 +133,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .record_size = 8,
.result_start_idx = 1,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 1, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -157,8 +155,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 13,
+ .result_start_idx = 12,
.result_bit_size = 128,
.result_num_fields = 26,
.encap_num_fields = 0
@@ -179,11 +176,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 39,
+ .result_start_idx = 38,
.result_bit_size = 128,
.result_num_fields = 26,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 2, , table: control.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
@@ -195,8 +191,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_start_idx = 14,
.cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* act_tid: 2, , table: mirror_tbl.alloc */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -215,8 +210,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 77,
+ .result_start_idx = 75,
.result_bit_size = 32,
.result_num_fields = 6
},
@@ -237,8 +231,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 83,
+ .result_start_idx = 81,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -259,8 +252,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 84,
+ .result_start_idx = 82,
.result_bit_size = 128,
.result_num_fields = 26,
.encap_num_fields = 0
@@ -282,11 +274,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 110,
+ .result_start_idx = 108,
.result_bit_size = 128,
.result_num_fields = 26,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 2, , table: mirror_tbl.wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -304,8 +295,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 148,
+ .result_start_idx = 145,
.result_bit_size = 32,
.result_num_fields = 6
},
@@ -324,12 +314,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 1,
.blob_key_bit_size = 1,
.key_bit_size = 1,
.key_num_fields = 1,
- .result_start_idx = 154,
+ .result_start_idx = 151,
.result_bit_size = 34,
.result_num_fields = 2
},
@@ -348,8 +337,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 156,
+ .result_start_idx = 153,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -368,8 +356,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 157,
+ .result_start_idx = 154,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -388,8 +375,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 158,
+ .result_start_idx = 155,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -408,11 +394,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 159,
+ .record_size = 16,
+ .result_start_idx = 156,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 3, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -429,8 +415,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 171,
+ .result_start_idx = 167,
.result_bit_size = 128,
.result_num_fields = 26
},
@@ -449,11 +434,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 197,
+ .result_start_idx = 193,
.result_bit_size = 128,
.result_num_fields = 26,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 4, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -470,8 +454,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 235,
+ .result_start_idx = 230,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -490,11 +473,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 236,
+ .record_size = 8,
+ .result_start_idx = 231,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 4, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -511,8 +494,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 248,
+ .result_start_idx = 242,
.result_bit_size = 128,
.result_num_fields = 26
},
@@ -531,11 +513,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 274,
+ .result_start_idx = 268,
.result_bit_size = 128,
.result_num_fields = 26,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 4, , table: ext_full_act_record.one_tag */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -552,11 +533,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 312,
+ .result_start_idx = 305,
.result_bit_size = 128,
.result_num_fields = 26,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 5, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -573,8 +553,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 350,
+ .result_start_idx = 342,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -593,8 +572,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 351,
+ .result_start_idx = 343,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -613,8 +591,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 352,
+ .result_start_idx = 344,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -633,11 +610,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 353,
+ .record_size = 16,
+ .result_start_idx = 345,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 5, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -654,8 +631,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 365,
+ .result_start_idx = 356,
.result_bit_size = 128,
.result_num_fields = 26
},
@@ -674,11 +650,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 391,
+ .result_start_idx = 382,
.result_bit_size = 128,
.result_num_fields = 26,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* act_tid: 6, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -695,8 +670,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 429,
+ .result_start_idx = 419,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -715,11 +689,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 430,
+ .record_size = 16,
+ .result_start_idx = 420,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 3
+ .encap_num_fields = 2
},
{ /* act_tid: 6, , table: sp_smac_ipv6.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -736,11 +710,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 433,
+ .record_size = 24,
+ .result_start_idx = 422,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 3
+ .encap_num_fields = 2
},
{ /* act_tid: 6, , table: int_tun_encap_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -757,11 +731,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 436,
+ .record_size = 64,
+ .result_start_idx = 424,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 12
+ .encap_num_fields = 30
},
{ /* act_tid: 6, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -778,8 +752,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 448,
+ .result_start_idx = 454,
.result_bit_size = 128,
.result_num_fields = 26
},
@@ -798,11 +771,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 474,
+ .result_start_idx = 480,
.result_bit_size = 128,
.result_num_fields = 26,
- .encap_num_fields = 12
+ .encap_num_fields = 30
}
};
@@ -1033,22 +1005,26 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
},
/* act_tid: 1, , table: int_vtag_encap_record.0 */
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
},
{
.description = "ecv_l2_en",
@@ -1057,26 +1033,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "vtag_tpid",
@@ -1088,13 +1060,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
},
{
.description = "vtag_de",
@@ -1103,19 +1075,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
- },
- {
- .description = "spare",
- .field_bit_size = 80,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
},
/* act_tid: 1, , table: int_full_act_record.0 */
{
@@ -1628,20 +1594,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -1649,25 +1617,23 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.description = "ecv_l2_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_L2_EN_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -1678,8 +1644,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -1690,14 +1656,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 0,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2105,20 +2065,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2126,25 +2088,23 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.description = "ecv_l2_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_L2_EN_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2155,8 +2115,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2167,14 +2127,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 0,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2268,20 +2222,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
},
/* act_tid: 3, , table: int_encap_mac_record.0 */
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2294,24 +2250,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
ULP_WP_SYM_ECV_L2_EN_YES}
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "vtag_tpid",
@@ -2320,8 +2274,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2332,14 +2286,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 80,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2806,20 +2754,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2827,25 +2777,23 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.description = "ecv_l2_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_L2_EN_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2856,8 +2804,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2868,14 +2816,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 0,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -2888,23 +2830,27 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
},
/* act_tid: 4, , table: int_vtag_encap_record.0 */
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
+ },
{
.description = "ecv_l2_en",
.field_bit_size = 1,
@@ -2912,26 +2858,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "vtag_tpid",
@@ -2943,13 +2885,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
},
{
.description = "vtag_de",
@@ -2958,19 +2900,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
- },
- {
- .description = "spare",
- .field_bit_size = 80,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
},
/* act_tid: 4, , table: int_full_act_record.0 */
{
@@ -3350,20 +3286,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -3371,25 +3309,23 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.description = "ecv_l2_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_L2_EN_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -3400,8 +3336,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -3412,14 +3348,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 0,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -3620,22 +3550,26 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
},
{
.description = "ecv_l2_en",
@@ -3644,26 +3578,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "vtag_tpid",
@@ -3675,13 +3605,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
},
{
.description = "vtag_de",
@@ -3690,19 +3620,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
- },
- {
- .description = "spare",
- .field_bit_size = 0,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
},
/* act_tid: 5, , table: int_flow_counter_tbl.0 */
{
@@ -3733,20 +3657,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
},
/* act_tid: 5, , table: int_encap_mac_record.dummy */
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -3759,24 +3685,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
ULP_WP_SYM_ECV_L2_EN_YES}
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "vtag_tpid",
@@ -3785,8 +3709,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -3797,14 +3721,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 80,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -4271,20 +4189,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -4292,25 +4212,23 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.description = "ecv_l2_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_L2_EN_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -4321,8 +4239,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -4333,14 +4251,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 0,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -4356,76 +4268,62 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.description = "smac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC & 0xff}
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
},
{
.description = "ipv4_src_addr",
.field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC & 0xff}
- },
- {
- .description = "reserved",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}
},
/* act_tid: 6, , table: sp_smac_ipv6.0 */
{
.description = "smac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC & 0xff}
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
},
{
.description = "ipv6_src_addr",
.field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC & 0xff}
- },
- {
- .description = "reserved",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ENC_FIELD_IPV6_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_SADDR & 0xff}
},
/* act_tid: 6, , table: int_tun_encap_record.0 */
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ULP_WP_SYM_ECV_TUN_TYPE_VXLAN}
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
},
{
.description = "ecv_l2_en",
@@ -4433,81 +4331,478 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ ULP_WP_SYM_ECV_L2_EN_YES}
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM}
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ ULP_WP_SYM_ECV_TUN_TYPE_VXLAN}
},
{
- .description = "encap_l2_dmac",
+ .description = "enc_eth_dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC & 0xff}
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
},
{
- .description = "encap_vtag",
- .field_bit_size = 0,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ,
+ .description = "enc_o_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_o_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_ihl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_tos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_pkt_id",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_frag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_daddr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_vtc",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_zero",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG & 0xff,
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ZERO,
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
- .description = "encap_ip",
- .field_bit_size = 0,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ,
+ .description = "enc_ipv6_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_daddr",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_vxlan_flags",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_IP & 0xff,
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
- .description = "encap_udp",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .description = "enc_vxlan_rsvd0",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
- .description = "encap_tun",
- .field_bit_size = 0,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ,
+ .description = "enc_vxlan_vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN & 0xff,
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_vxlan_rsvd1",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
/* act_tid: 6, , table: int_full_act_record.0 */
{
@@ -4857,29 +5152,27 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ULP_WP_SYM_ECV_TUN_TYPE_VXLAN}
+ ULP_WP_SYM_ECV_VALID_YES}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
},
{
.description = "ecv_l2_en",
@@ -4887,79 +5180,478 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ ULP_WP_SYM_ECV_L2_EN_YES}
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM}
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ ULP_WP_SYM_ECV_TUN_TYPE_VXLAN}
},
{
- .description = "encap_l2_dmac",
+ .description = "enc_eth_dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC & 0xff}
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
},
{
- .description = "encap_vtag",
- .field_bit_size = 0,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ,
+ .description = "enc_o_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_o_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_ihl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_tos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_pkt_id",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_frag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_daddr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_vtc",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_zero",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG & 0xff,
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ZERO,
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
- .description = "encap_ip",
- .field_bit_size = 0,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ,
+ .description = "enc_ipv6_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv6_daddr",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_UDP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_vxlan_flags",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_vxlan_rsvd0",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_IP & 0xff,
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
- .description = "encap_udp",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .description = "enc_vxlan_vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
- .description = "encap_tun",
- .field_bit_size = 80,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .description = "enc_vxlan_rsvd1",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
index 7b6ee03a4b..7203dcf1fb 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Mon May 17 15:54:03 2021 */
+/* date: Fri May 28 16:46:46 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -80,7 +80,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 0,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -102,7 +101,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 1,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -120,8 +118,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 2,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 1, , table: l2_cntxt_tcam.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -139,7 +136,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 6,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -164,7 +160,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 19,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -188,7 +183,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 24,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -206,8 +200,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 3,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 1, , table: control.2 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
@@ -225,8 +218,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
.func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
.func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
- .func_dst_opr = BNXT_ULP_RF_IDX_CC },
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
},
{ /* class_tid: 1, , table: profile_tcam.ipv4 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -244,7 +236,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 27,
.blob_key_bit_size = 81,
.key_bit_size = 81,
@@ -271,7 +262,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 70,
.blob_key_bit_size = 81,
.key_bit_size = 81,
@@ -298,7 +288,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 113,
.blob_key_bit_size = 81,
.key_bit_size = 81,
@@ -324,7 +313,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 156,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -346,7 +334,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 159,
.blob_key_bit_size = 176,
.key_bit_size = 176,
@@ -368,7 +355,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 169,
.blob_key_bit_size = 448,
.key_bit_size = 448,
@@ -390,7 +376,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 179,
.blob_key_bit_size = 416,
.key_bit_size = 416,
@@ -412,7 +397,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 190,
.blob_key_bit_size = 448,
.key_bit_size = 448,
@@ -434,7 +418,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 201,
.blob_key_bit_size = 200,
.key_bit_size = 200,
@@ -456,7 +439,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 212,
.blob_key_bit_size = 448,
.key_bit_size = 448,
@@ -479,7 +461,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 223,
.blob_key_bit_size = 16,
.key_bit_size = 16,
@@ -497,8 +478,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 25,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -516,7 +496,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 225,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -541,7 +520,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 238,
.blob_key_bit_size = 16,
.key_bit_size = 16,
@@ -559,8 +537,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 26,
.cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
{ /* class_tid: 2, , table: mac_addr_cache.rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
@@ -576,7 +553,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 240,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -594,8 +570,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 27,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 2, , table: l2_cntxt_tcam.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -613,7 +588,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 245,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -638,7 +612,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 258,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -662,7 +635,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 263,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -680,8 +652,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 28,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 2, , table: profile_tcam.f2 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -701,7 +672,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_operand = 1,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 266,
.blob_key_bit_size = 81,
.key_bit_size = 81,
@@ -725,7 +695,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 309,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -747,7 +716,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 312,
.blob_key_bit_size = 112,
.key_bit_size = 112,
@@ -769,7 +737,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 320,
.blob_key_bit_size = 448,
.key_bit_size = 448,
@@ -792,7 +759,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 328,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -814,7 +780,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 329,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -832,8 +797,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 32,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 3, , table: l2_cntxt_tcam.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -851,7 +815,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 334,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -876,7 +839,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 347,
.blob_key_bit_size = 73,
.key_bit_size = 73,
@@ -899,7 +861,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 352,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -917,8 +878,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 33,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 3, , table: control.conflict_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
@@ -936,8 +896,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
.func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
.func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
- .func_dst_opr = BNXT_ULP_RF_IDX_CC },
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
},
{ /* class_tid: 3, , table: profile_tcam.ipv4 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -955,7 +914,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 355,
.blob_key_bit_size = 81,
.key_bit_size = 81,
@@ -982,7 +940,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 398,
.blob_key_bit_size = 81,
.key_bit_size = 81,
@@ -1007,7 +964,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 441,
.blob_key_bit_size = 14,
.key_bit_size = 14,
@@ -1029,7 +985,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 444,
.blob_key_bit_size = 176,
.key_bit_size = 176,
@@ -1051,7 +1006,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 454,
.blob_key_bit_size = 448,
.key_bit_size = 448,
@@ -1073,7 +1027,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 464,
.blob_key_bit_size = 416,
.key_bit_size = 416,
@@ -1095,7 +1048,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 475,
.blob_key_bit_size = 448,
.key_bit_size = 448,
@@ -1120,7 +1072,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 292,
.result_bit_size = 128,
.result_num_fields = 26
@@ -1139,7 +1090,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 486,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1157,8 +1107,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 41,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1178,7 +1127,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 487,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -1203,7 +1151,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 500,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1225,7 +1172,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 335,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1243,7 +1189,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 336,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1261,7 +1206,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 337,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1275,8 +1219,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 42,
.cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
{ /* class_tid: 4, , table: int_full_act_record.egr_vfr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1294,7 +1237,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 338,
.result_bit_size = 128,
.result_num_fields = 26,
@@ -1314,7 +1256,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 501,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1332,8 +1273,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 43,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 4, , table: l2_cntxt_tcam_bypass.egr_vfr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1351,7 +1291,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 502,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -1376,7 +1315,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 515,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1399,7 +1337,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 516,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1417,8 +1354,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 44,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1436,7 +1372,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 517,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -1461,7 +1396,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 530,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1486,7 +1420,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 398,
.result_bit_size = 128,
.result_num_fields = 26,
@@ -1505,7 +1438,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 424,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1523,7 +1455,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 425,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1541,7 +1472,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 426,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1562,7 +1492,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 427,
.result_bit_size = 128,
.result_num_fields = 26,
@@ -1582,7 +1511,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 531,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1600,8 +1528,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 47,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1619,7 +1546,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 532,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -1644,7 +1570,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 545,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1666,7 +1591,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 470,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1684,7 +1608,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 471,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1702,7 +1625,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 472,
.result_bit_size = 32,
.result_num_fields = 1
@@ -1723,7 +1645,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 473,
.result_bit_size = 128,
.result_num_fields = 26,
@@ -1746,7 +1667,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 546,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -1771,7 +1691,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 559,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1789,8 +1708,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_start_idx = 48,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
{ /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_egr0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1808,7 +1726,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 560,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -1833,7 +1750,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 573,
.blob_key_bit_size = 8,
.key_bit_size = 8,
@@ -1858,11 +1774,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .record_size = 8,
.result_start_idx = 529,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 12
+ .encap_num_fields = 11
},
{ /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1880,8 +1796,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 541,
+ .result_start_idx = 540,
.result_bit_size = 128,
.result_num_fields = 26
},
@@ -1901,8 +1816,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .result_start_idx = 567,
+ .result_start_idx = 566,
.result_bit_size = 128,
.result_num_fields = 26
},
@@ -1923,12 +1837,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 574,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 593,
+ .result_start_idx = 592,
.result_bit_size = 64,
.result_num_fields = 13,
.ident_start_idx = 26,
@@ -1951,12 +1864,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 587,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 606,
+ .result_start_idx = 605,
.result_bit_size = 64,
.result_num_fields = 13,
.ident_start_idx = 26,
@@ -2522,17 +2434,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -6207,17 +6115,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -8046,17 +7950,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "tun_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_TUN_HDR_TYPE_NONE}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -16093,22 +15993,26 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
},
/* class_tid: 5, , table: int_vtag_encap_record.vfr_egr0 */
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
},
{
.description = "ecv_l2_en",
@@ -16117,26 +16021,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "vtag_tpid",
@@ -16148,13 +16048,10 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
0x00}
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "vtag_de",
@@ -16163,16 +16060,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spare",
- .field_bit_size = 80,
+ .description = "vtag_vid",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
},
/* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
{
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
index 9e6bd90aea..1cb52e9bfa 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
@@ -116,7 +116,7 @@ ulp_flow_db_resource_func_get(struct ulp_fdb_resource_info *res_info)
func = (((res_info->nxt_resource_idx & ULP_FLOW_DB_RES_FUNC_MASK) >>
ULP_FLOW_DB_RES_FUNC_BITS) << ULP_FLOW_DB_RES_FUNC_UPPER);
- /* The reource func is split into upper and lower */
+ /* The resource func is split into upper and lower */
if (func & ULP_FLOW_DB_RES_FUNC_NEED_LOWER)
return (func | res_info->resource_func_lower);
return func;
@@ -674,7 +674,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt,
* flow_type [in] Specify it is regular or default flow
* fid [in] The index to the flow entry
* params [in/out] The contents to be copied into params.
- * Onlythe critical_resource needs to be set by the caller.
+ * Only the critical_resource needs to be set by the caller.
*
* Returns 0 on success and negative on failure.
*/
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
index 8680ee8f65..6dbec92745 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
@@ -18,7 +18,7 @@
/*
* Structure for the flow database resource information
- * The below structure is based on the below paritions
+ * The below structure is based on the below partitions
* nxt_resource_idx = dir[31],resource_func_upper[30:28],nxt_resource_idx[27:0]
* If resource_func is EM_TBL then use resource_em_handle.
* Else the other part of the union is used and
diff --git a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
index bc5627ec5b..5f5b5d639e 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
@@ -185,7 +185,7 @@ ulp_ha_mgr_timer_cb(void *arg __rte_unused)
rc = ulp_ha_mgr_state_get(ulp_ctx, &curr_state);
if (rc) {
/*
- * This shouldn't happen, if it does, resetart the timer
+ * This shouldn't happen, if it does, reset the timer
* and try again next time.
*/
BNXT_TF_DBG(ERR, "Failed(%d) to get state.\n",
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 6d804c7ef9..2687a545f3 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -1010,7 +1010,7 @@ ulp_mapper_field_src_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
idx = tfp_be_to_cpu_16(idx);
- if (idx >= BNXT_ULP_CF_IDX_LAST || bytelen > sizeof(uint32_t)) {
+ if (idx >= BNXT_ULP_CF_IDX_LAST || bytelen > sizeof(uint64_t)) {
BNXT_TF_DBG(ERR, "comp field [%d] read oob %d\n", idx,
bytelen);
return -EINVAL;
@@ -1215,8 +1215,47 @@ ulp_mapper_field_src_process(struct bnxt_ulp_mapper_parms *parms,
BNXT_TF_DBG(ERR, "field port table failed\n");
return -EINVAL;
}
+ break;
+ case BNXT_ULP_FIELD_SRC_ENC_HDR_BIT:
+ if (!ulp_operand_read(field_opr,
+ (uint8_t *)&lregval, sizeof(uint64_t))) {
+ BNXT_TF_DBG(ERR, "Header bit read failed\n");
+ return -EINVAL;
+ }
+ lregval = tfp_be_to_cpu_64(lregval);
+ if (ULP_BITMAP_ISSET(parms->enc_hdr_bitmap->bits, lregval)) {
+ *val = mapper_fld_one;
+ *value = 1;
+ } else {
+ *val = mapper_fld_zeros;
+ }
+ break;
+ case BNXT_ULP_FIELD_SRC_ENC_FIELD:
+ if (!ulp_operand_read(field_opr,
+ (uint8_t *)&idx, sizeof(uint16_t))) {
+ BNXT_TF_DBG(ERR, "Header field read failed\n");
+ return -EINVAL;
+ }
+ idx = tfp_be_to_cpu_16(idx);
+ /* get the index from the global field list */
+ if (idx >= BNXT_ULP_ENC_FIELD_LAST) {
+ BNXT_TF_DBG(ERR, "invalid encap field tbl idx %d\n",
+ idx);
+ return -EINVAL;
+ }
+ buffer = parms->enc_field[idx].spec;
+ field_size = parms->enc_field[idx].size;
+ if (bytelen > field_size) {
+ BNXT_TF_DBG(ERR, "Encap field[%d] size small %u\n",
+ idx, field_size);
+ return -EINVAL;
+ }
+ *val = &buffer[field_size - bytelen];
+ break;
case BNXT_ULP_FIELD_SRC_SKIP:
/* do nothing */
+ *val = mapper_fld_zeros;
+ *val_len = 0;
break;
case BNXT_ULP_FIELD_SRC_REJECT:
return -EINVAL;
@@ -1270,6 +1309,8 @@ static int32_t ulp_mapper_field_blob_write(enum bnxt_ulp_field_src fld_src,
BNXT_TF_DBG(ERR, "encap blob push failed\n");
return -EINVAL;
}
+ } else if (fld_src == BNXT_ULP_FIELD_SRC_SKIP) {
+ /* do nothing */
} else {
if (!ulp_blob_push(blob, val, val_len)) {
BNXT_TF_DBG(ERR, "push of val1 failed\n");
@@ -1465,7 +1506,7 @@ ulp_mapper_field_opc_process(struct bnxt_ulp_mapper_parms *parms,
if (!rc) {
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
- if (fld->field_src1 != BNXT_ULP_FIELD_SRC_ZERO)
+ if (fld->field_src1 != BNXT_ULP_FIELD_SRC_ZERO && val_len)
ulp_mapper_field_dump(name, fld, blob, write_idx, val,
val_len);
#endif
@@ -1489,7 +1530,8 @@ ulp_mapper_tbl_result_build(struct bnxt_ulp_mapper_parms *parms,
const char *name)
{
struct bnxt_ulp_mapper_field_info *dflds;
- uint32_t i, num_flds = 0, encap_flds = 0;
+ uint32_t i = 0, num_flds = 0, encap_flds = 0;
+ struct ulp_blob encap_blob;
int32_t rc = 0;
/* Get the result field list */
@@ -1506,33 +1548,60 @@ ulp_mapper_tbl_result_build(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
- /* process the result fields, loop through them */
- for (i = 0; i < (num_flds + encap_flds); i++) {
- /* set the swap index if encap swap bit is enabled */
- if (parms->device_params->encap_byte_swap && encap_flds &&
- i == num_flds)
- ulp_blob_encap_swap_idx_set(data);
-
- /* Process the result fields */
+ /* process the result fields */
+ for (i = 0; i < num_flds; i++) {
rc = ulp_mapper_field_opc_process(parms, tbl->direction,
&dflds[i], data, 0, name);
if (rc) {
- BNXT_TF_DBG(ERR, "data field failed\n");
+ BNXT_TF_DBG(ERR, "result field processing failed\n");
return rc;
}
}
- /* if encap bit swap is enabled perform the bit swap */
- if (parms->device_params->encap_byte_swap && encap_flds) {
- ulp_blob_perform_encap_swap(data);
+ /* process encap fields if any */
+ if (encap_flds) {
+ uint32_t pad = 0;
+ /* Initialize the encap blob */
+ if (!tbl->record_size) {
+ BNXT_TF_DBG(ERR, "Encap tbl record size incorrect\n");
+ return -EINVAL;
+ }
+ if (!ulp_blob_init(&encap_blob,
+ ULP_BYTE_2_BITS(tbl->record_size),
+ parms->device_params->encap_byte_order)) {
+ BNXT_TF_DBG(ERR, "blob inits failed.\n");
+ return -EINVAL;
+ }
+ for (; i < encap_flds; i++) {
+ rc = ulp_mapper_field_opc_process(parms, tbl->direction,
+ &dflds[i],
+ &encap_blob, 0, name);
+ if (rc) {
+ BNXT_TF_DBG(ERR,
+ "encap field processing failed\n");
+ return rc;
+ }
+ }
+ /* add the dynamic pad push */
+ pad = ULP_BYTE_2_BITS(tbl->record_size) -
+ ulp_blob_data_len_get(&encap_blob);
+ ulp_blob_pad_push(&encap_blob, pad);
+
+ /* perform the 64 bit byte swap */
+ ulp_blob_perform_64B_byte_swap(&encap_blob);
+ /* Append encap blob to the result blob */
+ rc = ulp_blob_buffer_copy(data, &encap_blob);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "encap buffer copy failed\n");
+ return rc;
+ }
+ }
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
- BNXT_TF_DBG(INFO, "Dump after encap swap\n");
- ulp_mapper_blob_dump(data);
+ BNXT_TF_DBG(DEBUG, "Result dump\n");
+ ulp_mapper_blob_dump(data);
#endif
#endif
- }
-
return rc;
}
@@ -1934,11 +2003,14 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
- if (!ulp_blob_init(key, tbl->blob_key_bit_size, tbl->byte_order) ||
- !ulp_blob_init(mask, tbl->blob_key_bit_size, tbl->byte_order) ||
- !ulp_blob_init(&data, tbl->result_bit_size, dparms->byte_order) ||
+ if (!ulp_blob_init(key, tbl->blob_key_bit_size,
+ dparms->key_byte_order) ||
+ !ulp_blob_init(mask, tbl->blob_key_bit_size,
+ dparms->key_byte_order) ||
+ !ulp_blob_init(&data, tbl->result_bit_size,
+ dparms->result_byte_order) ||
!ulp_blob_init(&update_data, tbl->result_bit_size,
- dparms->byte_order)) {
+ dparms->result_byte_order)) {
BNXT_TF_DBG(ERR, "blob inits failed.\n");
return -EINVAL;
}
@@ -2145,9 +2217,9 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
/* Initialize the key/result blobs */
if (!ulp_blob_init(&key, tbl->blob_key_bit_size,
- tbl->byte_order) ||
+ dparms->key_byte_order) ||
!ulp_blob_init(&data, tbl->result_bit_size,
- tbl->byte_order)) {
+ dparms->result_byte_order)) {
BNXT_TF_DBG(ERR, "blob inits failed.\n");
return -EINVAL;
}
@@ -2336,7 +2408,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
/* Initialize the blob data */
if (!ulp_blob_init(&data, bit_size,
- parms->device_params->byte_order)) {
+ parms->device_params->result_byte_order)) {
BNXT_TF_DBG(ERR, "Failed to initialize index table blob\n");
return -EINVAL;
}
@@ -2627,7 +2699,7 @@ ulp_mapper_if_tbl_process(struct bnxt_ulp_mapper_parms *parms,
tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session);
/* Initialize the blob data */
if (!ulp_blob_init(&data, tbl->result_bit_size,
- parms->device_params->byte_order)) {
+ parms->device_params->result_byte_order)) {
BNXT_TF_DBG(ERR, "Failed initial index table blob\n");
return -EINVAL;
}
@@ -2658,7 +2730,7 @@ ulp_mapper_if_tbl_process(struct bnxt_ulp_mapper_parms *parms,
case BNXT_ULP_IF_TBL_OPC_RD_COMP_FIELD:
/* Initialize the result blob */
if (!ulp_blob_init(&res_blob, tbl->result_bit_size,
- parms->device_params->byte_order)) {
+ parms->device_params->result_byte_order)) {
BNXT_TF_DBG(ERR, "Failed initial result blob\n");
return -EINVAL;
}
@@ -2747,7 +2819,7 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms,
}
if (!ulp_blob_init(&key, tbl->key_bit_size,
- parms->device_params->byte_order)) {
+ parms->device_params->key_byte_order)) {
BNXT_TF_DBG(ERR, "Failed to alloc blob\n");
return -EINVAL;
}
@@ -3252,6 +3324,26 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms,
}
*res = (mtype == BNXT_ULP_FLOW_MEM_TYPE_INT) ? 1 : 0;
break;
+ case BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET:
+ if (operand < BNXT_ULP_HDR_BIT_LAST) {
+ *res = ULP_BITMAP_ISSET(parms->enc_hdr_bitmap->bits,
+ operand);
+ } else {
+ BNXT_TF_DBG(ERR, "header bit out of bounds %d\n",
+ operand);
+ rc = -EINVAL;
+ }
+ break;
+ case BNXT_ULP_COND_OPC_ENC_HDR_BIT_NOT_SET:
+ if (operand < BNXT_ULP_HDR_BIT_LAST) {
+ *res = !ULP_BITMAP_ISSET(parms->enc_hdr_bitmap->bits,
+ operand);
+ } else {
+ BNXT_TF_DBG(ERR, "header bit out of bounds %d\n",
+ operand);
+ rc = -EINVAL;
+ }
+ break;
default:
BNXT_TF_DBG(ERR, "Invalid conditional opcode %d\n", opc);
rc = -EINVAL;
@@ -3864,8 +3956,10 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
parms.act_prop = cparms->act_prop;
parms.act_bitmap = cparms->act;
parms.hdr_bitmap = cparms->hdr_bitmap;
+ parms.enc_hdr_bitmap = cparms->enc_hdr_bitmap;
parms.regfile = ®file;
parms.hdr_field = cparms->hdr_field;
+ parms.enc_field = cparms->enc_field;
parms.fld_bitmap = cparms->fld_bitmap;
parms.comp_fld = cparms->comp_fld;
parms.ulp_ctx = ulp_ctx;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
index d4d6969bb5..4d6ba0f73a 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
@@ -44,7 +44,9 @@ struct bnxt_ulp_mapper_parms {
struct ulp_rte_act_prop *act_prop;
struct ulp_rte_act_bitmap *act_bitmap;
struct ulp_rte_hdr_bitmap *hdr_bitmap;
+ struct ulp_rte_hdr_bitmap *enc_hdr_bitmap;
struct ulp_rte_hdr_field *hdr_field;
+ struct ulp_rte_hdr_field *enc_field;
struct ulp_rte_field_bitmap *fld_bitmap;
uint64_t *comp_fld;
struct ulp_regfile *regfile;
@@ -67,7 +69,9 @@ struct bnxt_ulp_mapper_parms {
struct bnxt_ulp_mapper_create_parms {
uint32_t app_priority;
struct ulp_rte_hdr_bitmap *hdr_bitmap;
+ struct ulp_rte_hdr_bitmap *enc_hdr_bitmap;
struct ulp_rte_hdr_field *hdr_field;
+ struct ulp_rte_hdr_field *enc_field;
uint64_t *comp_fld;
struct ulp_rte_act_bitmap *act;
struct ulp_rte_act_prop *act_prop;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index fadcd3873c..4e9968e5fa 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -40,6 +40,18 @@ ulp_rte_item_skip_void(const struct rte_flow_item **item, uint32_t increment)
return 0;
}
+/* Utility function to copy field spec items */
+static struct ulp_rte_hdr_field *
+ulp_rte_parser_fld_copy(struct ulp_rte_hdr_field *field,
+ const void *buffer,
+ uint32_t size)
+{
+ field->size = size;
+ memcpy(field->spec, buffer, field->size);
+ field++;
+ return field;
+}
+
/* Utility function to update the field_bitmap */
static void
ulp_rte_parser_field_bitmap_update(struct ulp_rte_parser_params *params,
@@ -883,7 +895,7 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
BNXT_ULP_HDR_BIT_II_VLAN);
inner_flag = 1;
} else {
- BNXT_TF_DBG(ERR, "Error Parsing:Vlan hdr found withtout eth\n");
+ BNXT_TF_DBG(ERR, "Error Parsing:Vlan hdr found without eth\n");
return BNXT_TF_RC_ERROR;
}
/* Update the field protocol hdr bitmap */
@@ -1726,6 +1738,184 @@ ulp_rte_rss_act_handler(const struct rte_flow_action *action_item,
return BNXT_TF_RC_SUCCESS;
}
+/* Function to handle the parsing of RTE Flow item eth Header. */
+static void
+ulp_rte_enc_eth_hdr_handler(struct ulp_rte_parser_params *params,
+ const struct rte_flow_item_eth *eth_spec)
+{
+ struct ulp_rte_hdr_field *field;
+ uint32_t size;
+
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_ETH_DMAC];
+ size = sizeof(eth_spec->dst.addr_bytes);
+ field = ulp_rte_parser_fld_copy(field, eth_spec->dst.addr_bytes, size);
+
+ size = sizeof(eth_spec->src.addr_bytes);
+ field = ulp_rte_parser_fld_copy(field, eth_spec->src.addr_bytes, size);
+
+ size = sizeof(eth_spec->type);
+ field = ulp_rte_parser_fld_copy(field, ð_spec->type, size);
+
+ ULP_BITMAP_SET(params->enc_hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_ETH);
+}
+
+/* Function to handle the parsing of RTE Flow item vlan Header. */
+static void
+ulp_rte_enc_vlan_hdr_handler(struct ulp_rte_parser_params *params,
+ const struct rte_flow_item_vlan *vlan_spec,
+ uint32_t inner)
+{
+ struct ulp_rte_hdr_field *field;
+ uint32_t size;
+
+ if (!inner) {
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_O_VLAN_TCI];
+ ULP_BITMAP_SET(params->enc_hdr_bitmap.bits,
+ BNXT_ULP_HDR_BIT_OO_VLAN);
+ } else {
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_I_VLAN_TCI];
+ ULP_BITMAP_SET(params->enc_hdr_bitmap.bits,
+ BNXT_ULP_HDR_BIT_OI_VLAN);
+ }
+
+ size = sizeof(vlan_spec->tci);
+ field = ulp_rte_parser_fld_copy(field, &vlan_spec->tci, size);
+
+ size = sizeof(vlan_spec->inner_type);
+ field = ulp_rte_parser_fld_copy(field, &vlan_spec->inner_type, size);
+}
+
+/* Function to handle the parsing of RTE Flow item ipv4 Header. */
+static void
+ulp_rte_enc_ipv4_hdr_handler(struct ulp_rte_parser_params *params,
+ const struct rte_flow_item_ipv4 *ip)
+{
+ struct ulp_rte_hdr_field *field;
+ uint32_t size;
+ uint8_t val8;
+
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_IPV4_IHL];
+ size = sizeof(ip->hdr.version_ihl);
+ if (!ip->hdr.version_ihl)
+ val8 = RTE_IPV4_VHL_DEF;
+ else
+ val8 = ip->hdr.version_ihl;
+ field = ulp_rte_parser_fld_copy(field, &val8, size);
+
+ size = sizeof(ip->hdr.type_of_service);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.type_of_service, size);
+
+ size = sizeof(ip->hdr.packet_id);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.packet_id, size);
+
+ size = sizeof(ip->hdr.fragment_offset);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.fragment_offset, size);
+
+ size = sizeof(ip->hdr.time_to_live);
+ if (!ip->hdr.time_to_live)
+ val8 = BNXT_ULP_DEFAULT_TTL;
+ else
+ val8 = ip->hdr.time_to_live;
+ field = ulp_rte_parser_fld_copy(field, &val8, size);
+
+ size = sizeof(ip->hdr.next_proto_id);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.next_proto_id, size);
+
+ size = sizeof(ip->hdr.src_addr);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.src_addr, size);
+
+ size = sizeof(ip->hdr.dst_addr);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.dst_addr, size);
+
+ ULP_BITMAP_SET(params->enc_hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV4);
+}
+
+/* Function to handle the parsing of RTE Flow item ipv6 Header. */
+static void
+ulp_rte_enc_ipv6_hdr_handler(struct ulp_rte_parser_params *params,
+ const struct rte_flow_item_ipv6 *ip)
+{
+ struct ulp_rte_hdr_field *field;
+ uint32_t size;
+ uint32_t val32;
+ uint8_t val8;
+
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW];
+ size = sizeof(ip->hdr.vtc_flow);
+ if (!ip->hdr.vtc_flow)
+ val32 = rte_cpu_to_be_32(BNXT_ULP_IPV6_DFLT_VER);
+ else
+ val32 = ip->hdr.vtc_flow;
+ field = ulp_rte_parser_fld_copy(field, &val32, size);
+
+ size = sizeof(ip->hdr.proto);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.proto, size);
+
+ size = sizeof(ip->hdr.hop_limits);
+ if (!ip->hdr.hop_limits)
+ val8 = BNXT_ULP_DEFAULT_TTL;
+ else
+ val8 = ip->hdr.hop_limits;
+ field = ulp_rte_parser_fld_copy(field, &val8, size);
+
+ size = sizeof(ip->hdr.src_addr);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.src_addr, size);
+
+ size = sizeof(ip->hdr.dst_addr);
+ field = ulp_rte_parser_fld_copy(field, &ip->hdr.dst_addr, size);
+
+ ULP_BITMAP_SET(params->enc_hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV6);
+}
+
+/* Function to handle the parsing of RTE Flow item UDP Header. */
+static void
+ulp_rte_enc_udp_hdr_handler(struct ulp_rte_parser_params *params,
+ const struct rte_flow_item_udp *udp_spec)
+{
+ struct ulp_rte_hdr_field *field;
+ uint32_t size;
+ uint8_t type = IPPROTO_UDP;
+
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_UDP_SPORT];
+ size = sizeof(udp_spec->hdr.src_port);
+ field = ulp_rte_parser_fld_copy(field, &udp_spec->hdr.src_port, size);
+
+ size = sizeof(udp_spec->hdr.dst_port);
+ field = ulp_rte_parser_fld_copy(field, &udp_spec->hdr.dst_port, size);
+
+ ULP_BITMAP_SET(params->enc_hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_UDP);
+
+ /* Update thhe ip header protocol */
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_IPV4_PROTO];
+ ulp_rte_parser_fld_copy(field, &type, sizeof(type));
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_IPV6_PROTO];
+ ulp_rte_parser_fld_copy(field, &type, sizeof(type));
+}
+
+/* Function to handle the parsing of RTE Flow item vxlan Header. */
+static void
+ulp_rte_enc_vxlan_hdr_handler(struct ulp_rte_parser_params *params,
+ struct rte_flow_item_vxlan *vxlan_spec)
+{
+ struct ulp_rte_hdr_field *field;
+ uint32_t size;
+
+ field = ¶ms->enc_field[BNXT_ULP_ENC_FIELD_VXLAN_FLAGS];
+ size = sizeof(vxlan_spec->flags);
+ field = ulp_rte_parser_fld_copy(field, &vxlan_spec->flags, size);
+
+ size = sizeof(vxlan_spec->rsvd0);
+ field = ulp_rte_parser_fld_copy(field, &vxlan_spec->rsvd0, size);
+
+ size = sizeof(vxlan_spec->vni);
+ field = ulp_rte_parser_fld_copy(field, &vxlan_spec->vni, size);
+
+ size = sizeof(vxlan_spec->rsvd1);
+ field = ulp_rte_parser_fld_copy(field, &vxlan_spec->rsvd1, size);
+
+ ULP_BITMAP_SET(params->enc_hdr_bitmap.bits, BNXT_ULP_HDR_BIT_T_VXLAN);
+}
+
/* Function to handle the parsing of RTE Flow action vxlan_encap Header. */
int32_t
ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
@@ -1733,23 +1923,14 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
{
const struct rte_flow_action_vxlan_encap *vxlan_encap;
const struct rte_flow_item *item;
- const struct rte_flow_item_eth *eth_spec;
const struct rte_flow_item_ipv4 *ipv4_spec;
const struct rte_flow_item_ipv6 *ipv6_spec;
struct rte_flow_item_vxlan vxlan_spec;
uint32_t vlan_num = 0, vlan_size = 0;
uint32_t ip_size = 0, ip_type = 0;
uint32_t vxlan_size = 0;
- uint8_t *buff;
- /* IP header per byte - ver/hlen, TOS, ID, ID, FRAG, FRAG, TTL, PROTO */
- const uint8_t def_ipv4_hdr[] = {0x45, 0x00, 0x00, 0x01, 0x00,
- 0x00, 0x40, 0x11};
- /* IPv6 header per byte - vtc-flow,flow,zero,nexthdr-ttl */
- const uint8_t def_ipv6_hdr[] = {0x60, 0x00, 0x00, 0x01, 0x00,
- 0x00, 0x11, 0xf6};
struct ulp_rte_act_bitmap *act = ¶ms->act_bitmap;
struct ulp_rte_act_prop *ap = ¶ms->act_prop;
- const uint8_t *tmp_buff;
vxlan_encap = action_item->conf;
if (!vxlan_encap) {
@@ -1771,18 +1952,10 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
BNXT_TF_DBG(ERR, "Parse Error:vxlan encap does not have eth\n");
return BNXT_TF_RC_ERROR;
}
- eth_spec = item->spec;
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC];
- ulp_encap_buffer_copy(buff,
- eth_spec->dst.addr_bytes,
- BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_DMAC,
- ULP_BUFFER_ALIGN_8_BYTE);
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC];
- ulp_encap_buffer_copy(buff,
- eth_spec->src.addr_bytes,
- BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_SMAC,
- ULP_BUFFER_ALIGN_8_BYTE);
+ /* Parse the ethernet header */
+ if (item->spec)
+ ulp_rte_enc_eth_hdr_handler(params, item->spec);
/* Goto the next item */
if (!ulp_rte_item_skip_void(&item, 1))
@@ -1791,11 +1964,8 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
/* May have vlan header */
if (item->type == RTE_FLOW_ITEM_TYPE_VLAN) {
vlan_num++;
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG];
- ulp_encap_buffer_copy(buff,
- item->spec,
- sizeof(struct rte_flow_item_vlan),
- ULP_BUFFER_ALIGN_8_BYTE);
+ if (item->spec)
+ ulp_rte_enc_vlan_hdr_handler(params, item->spec, 0);
if (!ulp_rte_item_skip_void(&item, 1))
return BNXT_TF_RC_ERROR;
@@ -1804,13 +1974,13 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
/* may have two vlan headers */
if (item->type == RTE_FLOW_ITEM_TYPE_VLAN) {
vlan_num++;
- memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG +
- sizeof(struct rte_flow_item_vlan)],
- item->spec,
- sizeof(struct rte_flow_item_vlan));
+ if (item->spec)
+ ulp_rte_enc_vlan_hdr_handler(params, item->spec, 1);
+
if (!ulp_rte_item_skip_void(&item, 1))
return BNXT_TF_RC_ERROR;
}
+
/* Update the vlan count and size of more than one */
if (vlan_num) {
vlan_size = vlan_num * sizeof(struct rte_flow_item_vlan);
@@ -1829,49 +1999,6 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
ipv4_spec = item->spec;
ip_size = BNXT_ULP_ENCAP_IPV4_SIZE;
- /* copy the ipv4 details */
- if (ulp_buffer_is_empty(&ipv4_spec->hdr.version_ihl,
- BNXT_ULP_ENCAP_IPV4_VER_HLEN_TOS)) {
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP];
- ulp_encap_buffer_copy(buff,
- def_ipv4_hdr,
- BNXT_ULP_ENCAP_IPV4_VER_HLEN_TOS +
- BNXT_ULP_ENCAP_IPV4_ID_PROTO,
- ULP_BUFFER_ALIGN_8_BYTE);
- } else {
- /* Total length being ignored in the ip hdr. */
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP];
- tmp_buff = (const uint8_t *)&ipv4_spec->hdr.packet_id;
- ulp_encap_buffer_copy(buff,
- tmp_buff,
- BNXT_ULP_ENCAP_IPV4_ID_PROTO,
- ULP_BUFFER_ALIGN_8_BYTE);
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP +
- BNXT_ULP_ENCAP_IPV4_ID_PROTO];
- ulp_encap_buffer_copy(buff,
- &ipv4_spec->hdr.version_ihl,
- BNXT_ULP_ENCAP_IPV4_VER_HLEN_TOS,
- ULP_BUFFER_ALIGN_8_BYTE);
- }
-
- /* Update the dst ip address in ip encap buffer */
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP +
- BNXT_ULP_ENCAP_IPV4_VER_HLEN_TOS +
- BNXT_ULP_ENCAP_IPV4_ID_PROTO];
- ulp_encap_buffer_copy(buff,
- (const uint8_t *)&ipv4_spec->hdr.dst_addr,
- sizeof(ipv4_spec->hdr.dst_addr),
- ULP_BUFFER_ALIGN_8_BYTE);
-
- /* Update the src ip address */
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC +
- BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SRC -
- sizeof(ipv4_spec->hdr.src_addr)];
- ulp_encap_buffer_copy(buff,
- (const uint8_t *)&ipv4_spec->hdr.src_addr,
- sizeof(ipv4_spec->hdr.src_addr),
- ULP_BUFFER_ALIGN_8_BYTE);
-
/* Update the ip size details */
ip_size = tfp_cpu_to_be_32(ip_size);
memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ],
@@ -1885,6 +2012,8 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
/* update the computed field to notify it is ipv4 header */
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG,
1);
+ if (ipv4_spec)
+ ulp_rte_enc_ipv4_hdr_handler(params, ipv4_spec);
if (!ulp_rte_item_skip_void(&item, 1))
return BNXT_TF_RC_ERROR;
@@ -1892,47 +2021,6 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
ipv6_spec = item->spec;
ip_size = BNXT_ULP_ENCAP_IPV6_SIZE;
- /* copy the ipv6 details */
- tmp_buff = (const uint8_t *)&ipv6_spec->hdr.vtc_flow;
- if (ulp_buffer_is_empty(tmp_buff,
- BNXT_ULP_ENCAP_IPV6_VTC_FLOW)) {
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP];
- ulp_encap_buffer_copy(buff,
- def_ipv6_hdr,
- sizeof(def_ipv6_hdr),
- ULP_BUFFER_ALIGN_8_BYTE);
- } else {
- /* The payload length being ignored in the ip hdr. */
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP];
- tmp_buff = (const uint8_t *)&ipv6_spec->hdr.proto;
- ulp_encap_buffer_copy(buff,
- tmp_buff,
- BNXT_ULP_ENCAP_IPV6_PROTO_TTL,
- ULP_BUFFER_ALIGN_8_BYTE);
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP +
- BNXT_ULP_ENCAP_IPV6_PROTO_TTL +
- BNXT_ULP_ENCAP_IPV6_DO];
- tmp_buff = (const uint8_t *)&ipv6_spec->hdr.vtc_flow;
- ulp_encap_buffer_copy(buff,
- tmp_buff,
- BNXT_ULP_ENCAP_IPV6_VTC_FLOW,
- ULP_BUFFER_ALIGN_8_BYTE);
- }
- /* Update the dst ip address in ip encap buffer */
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP +
- sizeof(def_ipv6_hdr)];
- ulp_encap_buffer_copy(buff,
- (const uint8_t *)ipv6_spec->hdr.dst_addr,
- sizeof(ipv6_spec->hdr.dst_addr),
- ULP_BUFFER_ALIGN_8_BYTE);
-
- /* Update the src ip address */
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC];
- ulp_encap_buffer_copy(buff,
- (const uint8_t *)ipv6_spec->hdr.src_addr,
- sizeof(ipv6_spec->hdr.src_addr),
- ULP_BUFFER_ALIGN_16_BYTE);
-
/* Update the ip size details */
ip_size = tfp_cpu_to_be_32(ip_size);
memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ],
@@ -1946,6 +2034,8 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
/* update the computed field to notify it is ipv6 header */
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG,
1);
+ if (ipv6_spec)
+ ulp_rte_enc_ipv6_hdr_handler(params, ipv6_spec);
if (!ulp_rte_item_skip_void(&item, 1))
return BNXT_TF_RC_ERROR;
@@ -1959,10 +2049,8 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
BNXT_TF_DBG(ERR, "vxlan encap does not have udp\n");
return BNXT_TF_RC_ERROR;
}
- /* copy the udp details */
- ulp_encap_buffer_copy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP],
- item->spec, BNXT_ULP_ENCAP_UDP_SIZE,
- ULP_BUFFER_ALIGN_8_BYTE);
+ if (item->spec)
+ ulp_rte_enc_udp_hdr_handler(params, item->spec);
if (!ulp_rte_item_skip_void(&item, 1))
return BNXT_TF_RC_ERROR;
@@ -1976,21 +2064,12 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
/* copy the vxlan details */
memcpy(&vxlan_spec, item->spec, vxlan_size);
vxlan_spec.flags = 0x08;
- buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN];
- if (ip_type == rte_cpu_to_be_32(BNXT_ULP_ETH_IPV4)) {
- ulp_encap_buffer_copy(buff, (const uint8_t *)&vxlan_spec,
- vxlan_size, ULP_BUFFER_ALIGN_8_BYTE);
- } else {
- ulp_encap_buffer_copy(buff, (const uint8_t *)&vxlan_spec,
- vxlan_size / 2, ULP_BUFFER_ALIGN_8_BYTE);
- ulp_encap_buffer_copy(buff + (vxlan_size / 2),
- (const uint8_t *)&vxlan_spec.vni,
- vxlan_size / 2, ULP_BUFFER_ALIGN_8_BYTE);
- }
vxlan_size = tfp_cpu_to_be_32(vxlan_size);
memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ],
&vxlan_size, sizeof(uint32_t));
+ ulp_rte_enc_vxlan_hdr_handler(params, &vxlan_spec);
+
/* update the hdr_bitmap with vxlan */
ULP_BITMAP_SET(act->bits, BNXT_ULP_ACT_BIT_VXLAN_ENCAP);
return BNXT_TF_RC_SUCCESS;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
index 673172c811..e14f86278a 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
@@ -33,8 +33,10 @@
#define BNXT_ULP_GET_IPV6_FLOWLABEL(vtcf) \
((vtcf) & BNXT_ULP_PARSER_IPV6_FLOW_LABEL)
#define BNXT_ULP_PARSER_IPV6_VER_MASK 0xf0000000
+#define BNXT_ULP_IPV6_DFLT_VER 0x60000000
#define BNXT_ULP_PARSER_IPV6_TC 0x0ff00000
#define BNXT_ULP_PARSER_IPV6_FLOW_LABEL 0x000fffff
+#define BNXT_ULP_DEFAULT_TTL 64
enum bnxt_ulp_prsr_action {
ULP_PRSR_ACT_DEFAULT = 0,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index 2685e63432..904763f27d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -30,6 +30,7 @@
#define BNXT_ULP_PROTO_HDR_GRE_NUM 6
#define BNXT_ULP_PROTO_HDR_ICMP_NUM 5
#define BNXT_ULP_PROTO_HDR_MAX 128
+#define BNXT_ULP_PROTO_HDR_ENCAP_MAX 64
#define BNXT_ULP_PROTO_HDR_FIELD_SVIF_IDX 1
/* Direction attributes */
@@ -64,12 +65,13 @@ struct ulp_rte_act_prop {
/* Structure to be used for passing all the parser functions */
struct ulp_rte_parser_params {
- STAILQ_ENTRY(ulp_rte_parser_params) next;
struct ulp_rte_hdr_bitmap hdr_bitmap;
+ struct ulp_rte_hdr_bitmap enc_hdr_bitmap;
struct ulp_rte_hdr_bitmap hdr_fp_bit;
struct ulp_rte_field_bitmap fld_bitmap;
struct ulp_rte_field_bitmap fld_s_bitmap;
struct ulp_rte_hdr_field hdr_field[BNXT_ULP_PROTO_HDR_MAX];
+ struct ulp_rte_hdr_field enc_field[BNXT_ULP_PROTO_HDR_ENCAP_MAX];
uint64_t comp_fld[BNXT_ULP_CF_IDX_LAST];
uint32_t field_idx;
struct ulp_rte_act_bitmap act_bitmap;
@@ -207,7 +209,9 @@ struct bnxt_ulp_template_device_tbls {
/* Device specific parameters */
struct bnxt_ulp_device_params {
uint8_t description[16];
- enum bnxt_ulp_byte_order byte_order;
+ enum bnxt_ulp_byte_order key_byte_order;
+ enum bnxt_ulp_byte_order result_byte_order;
+ enum bnxt_ulp_byte_order encap_byte_order;
uint8_t encap_byte_swap;
uint8_t num_phy_ports;
uint32_t mark_db_lfid_entries;
@@ -254,7 +258,6 @@ struct bnxt_ulp_mapper_tbl_info {
uint8_t direction;
enum bnxt_ulp_pri_opc pri_opcode;
uint32_t pri_operand;
- enum bnxt_ulp_byte_order byte_order;
/* conflict resolution opcode */
enum bnxt_ulp_accept_opc accept_opcode;
@@ -267,6 +270,7 @@ struct bnxt_ulp_mapper_tbl_info {
uint16_t key_num_fields;
/* Size of the blob that holds the key */
uint16_t blob_key_bit_size;
+ uint16_t record_size;
/* Information for accessing the ulp_class_result_field_list */
uint32_t result_start_idx;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c
index 1649e157f2..fc4f435c97 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c
@@ -62,7 +62,7 @@ ulp_regfile_read(struct ulp_regfile *regfile,
* data [in] The value is written into this variable. It is going to be in the
* same byte order as it was written.
*
- * size [in] The size in bytes of the value beingritten into this
+ * size [in] The size in bytes of the value being written into this
* variable.
*
* returns 0 on success
@@ -295,7 +295,7 @@ ulp_blob_push(struct ulp_blob *blob,
datalen,
data);
if (!rc) {
- BNXT_TF_DBG(ERR, "Failed ro write blob\n");
+ BNXT_TF_DBG(ERR, "Failed to write blob\n");
return 0;
}
blob->write_idx += datalen;
@@ -355,7 +355,7 @@ ulp_blob_insert(struct ulp_blob *blob, uint32_t offset,
datalen,
data);
if (!rc) {
- BNXT_TF_DBG(ERR, "Failed ro write blob\n");
+ BNXT_TF_DBG(ERR, "Failed to write blob\n");
return 0;
}
/* copy the previously stored data */
@@ -409,7 +409,7 @@ ulp_blob_push_64(struct ulp_blob *blob,
*
* data [in] 32-bit value to be added to the blob.
*
- * datalen [in] The number of bits to be added ot the blob.
+ * datalen [in] The number of bits to be added to the blob.
*
* The offset of the data is updated after each push of data.
* NULL returned on error, pointer pushed value otherwise.
@@ -987,6 +987,33 @@ ulp_blob_append(struct ulp_blob *dst, struct ulp_blob *src,
return 0;
}
+/*
+ * Perform the blob buffer copy.
+ * This api makes the src blob merged to the dst blob.
+ *
+ * dst [in] The destination blob, the blob to be merged.
+ * src [in] The src blob.
+ *
+ * returns 0 on success.
+ */
+int32_t
+ulp_blob_buffer_copy(struct ulp_blob *dst, struct ulp_blob *src)
+{
+ if ((dst->write_idx + src->write_idx) > dst->bitlen) {
+ BNXT_TF_DBG(ERR, "source buffer too large\n");
+ return -EINVAL;
+ }
+ if (ULP_BITS_IS_BYTE_NOT_ALIGNED(dst->write_idx) ||
+ ULP_BITS_IS_BYTE_NOT_ALIGNED(src->write_idx)) {
+ BNXT_TF_DBG(ERR, "source buffer is not aligned\n");
+ return -EINVAL;
+ }
+ memcpy(&dst->data[ULP_BITS_2_BYTE_NR(dst->write_idx)],
+ src->data, ULP_BITS_2_BYTE_NR(src->write_idx));
+ dst->write_idx += src->write_idx;
+ return 0;
+}
+
/*
* Read data from the operand
*
@@ -1012,44 +1039,6 @@ ulp_operand_read(uint8_t *operand,
return bytes;
}
-/*
- * copy the buffer in the encap format which is 2 bytes.
- * The MSB of the src is placed at the LSB of dst.
- *
- * dst [out] The destination buffer
- * src [in] The source buffer dst
- * size[in] size of the buffer.
- * align[in] The alignment is either 8 or 16.
- */
-void
-ulp_encap_buffer_copy(uint8_t *dst,
- const uint8_t *src,
- uint16_t size,
- uint16_t align)
-{
- uint16_t idx, tmp_size = 0;
-
- do {
- dst += tmp_size;
- src += tmp_size;
- idx = 0;
- if (size > align) {
- tmp_size = align;
- size -= align;
- } else {
- tmp_size = size;
- size = 0;
- }
- /* copy 2 bytes at a time. Write MSB to LSB */
- while ((idx + sizeof(uint16_t)) <= tmp_size) {
- memcpy(&dst[idx],
- &src[tmp_size - idx - sizeof(uint16_t)],
- sizeof(uint16_t));
- idx += sizeof(uint16_t);
- }
- } while (size);
-}
-
/*
* Check the buffer is empty
*
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.h b/drivers/net/bnxt/tf_ulp/ulp_utils.h
index e1b0e773f3..68a537fa0a 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.h
@@ -475,6 +475,18 @@ int32_t
ulp_blob_append(struct ulp_blob *dst, struct ulp_blob *src,
uint16_t src_offset, uint16_t src_len);
+/*
+ * Perform the blob buffer copy.
+ * This api makes the src blob merged to the dst blob.
+ *
+ * dst [in] The destination blob, the blob to be merged.
+ * src [in] The src blob.
+ *
+ * returns 0 on success.
+ */
+int32_t
+ulp_blob_buffer_copy(struct ulp_blob *dst, struct ulp_blob *src);
+
/*
* Read data from the operand
*
@@ -491,21 +503,6 @@ ulp_operand_read(uint8_t *operand,
uint8_t *val,
uint16_t bitlen);
-/*
- * copy the buffer in the encap format which is 2 bytes.
- * The MSB of the src is placed at the LSB of dst.
- *
- * dst [out] The destination buffer
- * src [in] The source buffer dst
- * size[in] size of the buffer.
- * align[in] The alignment is either 8 or 16.
- */
-void
-ulp_encap_buffer_copy(uint8_t *dst,
- const uint8_t *src,
- uint16_t size,
- uint16_t align);
-
/*
* Check the buffer is empty
*
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v4 08/13] net/bnxt: add wild card TCAM byte order for Thor
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 " Venkat Duvvuru
` (6 preceding siblings ...)
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 07/13] net/bnxt: add support for dynamic encap action Venkat Duvvuru
@ 2021-09-20 7:42 ` Venkat Duvvuru
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 09/13] net/bnxt: add flow templates " Venkat Duvvuru
` (5 subsequent siblings)
13 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-20 7:42 UTC (permalink / raw)
To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
The wild card TCAM for Thor platform is different from the profile TCAM
byte order.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Shuanglin Wang <shuanglin.wang@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
.../generic_templates/ulp_template_db_tbl.c | 2 ++
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 25 +++++++++++++------
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 1 +
3 files changed, 21 insertions(+), 7 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
index b5bce6f4c7..68f1b5fd00 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
@@ -201,6 +201,7 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
.key_byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE,
.encap_byte_order = BNXT_ULP_BYTE_ORDER_BE,
+ .wc_key_byte_order = BNXT_ULP_BYTE_ORDER_BE,
.encap_byte_swap = 1,
.int_flow_db_num_entries = 16384,
.ext_flow_db_num_entries = 32768,
@@ -223,6 +224,7 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
.key_byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE,
.encap_byte_order = BNXT_ULP_BYTE_ORDER_BE,
+ .wc_key_byte_order = BNXT_ULP_BYTE_ORDER_BE,
.encap_byte_swap = 1,
.int_flow_db_num_entries = 16384,
.ext_flow_db_num_entries = 32768,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 2687a545f3..bcc089b3e1 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -1953,6 +1953,15 @@ static void ulp_mapper_wc_tcam_tbl_post_process(struct ulp_blob *blob)
#endif
}
+static int32_t ulp_mapper_tcam_is_wc_tcam(struct bnxt_ulp_mapper_tbl_info *tbl)
+{
+ if (tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM ||
+ tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM_HIGH ||
+ tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM_LOW)
+ return 1;
+ return 0;
+}
+
static int32_t
ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
struct bnxt_ulp_mapper_tbl_info *tbl)
@@ -1972,6 +1981,7 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
uint32_t hit = 0;
uint16_t tmplen = 0;
uint16_t idx;
+ enum bnxt_ulp_byte_order key_byte_order;
/* Set the key and mask to the original key and mask. */
key = &okey;
@@ -2003,10 +2013,13 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
- if (!ulp_blob_init(key, tbl->blob_key_bit_size,
- dparms->key_byte_order) ||
- !ulp_blob_init(mask, tbl->blob_key_bit_size,
- dparms->key_byte_order) ||
+ if (ulp_mapper_tcam_is_wc_tcam(tbl))
+ key_byte_order = dparms->wc_key_byte_order;
+ else
+ key_byte_order = dparms->key_byte_order;
+
+ if (!ulp_blob_init(key, tbl->blob_key_bit_size, key_byte_order) ||
+ !ulp_blob_init(mask, tbl->blob_key_bit_size, key_byte_order) ||
!ulp_blob_init(&data, tbl->result_bit_size,
dparms->result_byte_order) ||
!ulp_blob_init(&update_data, tbl->result_bit_size,
@@ -2043,9 +2056,7 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
}
/* For wild card tcam perform the post process to swap the blob */
- if (tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM ||
- tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM_HIGH ||
- tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM_LOW) {
+ if (ulp_mapper_tcam_is_wc_tcam(tbl)) {
if (dparms->dynamic_pad_en) {
/* Sets up the slices for writing to the WC TCAM */
rc = ulp_mapper_wc_tcam_tbl_dyn_post_process(dparms,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index 904763f27d..e2a4b81cec 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -212,6 +212,7 @@ struct bnxt_ulp_device_params {
enum bnxt_ulp_byte_order key_byte_order;
enum bnxt_ulp_byte_order result_byte_order;
enum bnxt_ulp_byte_order encap_byte_order;
+ enum bnxt_ulp_byte_order wc_key_byte_order;
uint8_t encap_byte_swap;
uint8_t num_phy_ports;
uint32_t mark_db_lfid_entries;
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v4 09/13] net/bnxt: add flow templates for Thor
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 " Venkat Duvvuru
` (7 preceding siblings ...)
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 08/13] net/bnxt: add wild card TCAM byte order for Thor Venkat Duvvuru
@ 2021-09-20 7:42 ` Venkat Duvvuru
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 10/13] net/bnxt: change log level to debug Venkat Duvvuru
` (4 subsequent siblings)
13 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-20 7:42 UTC (permalink / raw)
To: dev; +Cc: Kishore Padmanabha, Mike Baucom, Venkat Duvvuru
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
1. Add support for egress flows with port and count action for
Thor platform.
2. Added templates to support VXLAN encapsulation feature for Thor.
3. Added support for VXLAN decap and VLAN pop actions along with
the ingress flow.
4. Added templates to enable VXLAN decap support for f1 and f2 flows.
5. Added templates Thor VF Rep support
6. Added Thor ingress mod table actions for NAT, NAPT, and TTL.
7. Added mirror/sample table support
8. Added supported for IPv6 flows for Thor.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Mike Baucom <michael.baucom@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/tf_core/tf_tcam.c | 6 +-
.../generic_templates/ulp_template_db_enum.h | 123 +-
.../generic_templates/ulp_template_db_tbl.c | 182 +-
.../ulp_template_db_thor_act.c | 4329 +-
.../ulp_template_db_thor_class.c | 44219 ++++++++++++++--
.../ulp_template_db_wh_plus_class.c | 4 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 10 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 18 +-
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 1 +
drivers/net/bnxt/tf_ulp/ulp_utils.c | 3 +
10 files changed, 44734 insertions(+), 4161 deletions(-)
diff --git a/drivers/net/bnxt/tf_core/tf_tcam.c b/drivers/net/bnxt/tf_core/tf_tcam.c
index 806af3070a..273f20858b 100644
--- a/drivers/net/bnxt/tf_core/tf_tcam.c
+++ b/drivers/net/bnxt/tf_core/tf_tcam.c
@@ -323,8 +323,12 @@ tf_tcam_alloc(struct tf *tfp,
}
/* return the start index of each row */
- if (i == 0)
+ if (parms->priority == 0) {
+ if (i == 0)
+ parms->idx = index;
+ } else {
parms->idx = index;
+ }
}
return 0;
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
index 9010d9a749..84e3d92f41 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
@@ -3,12 +3,12 @@
* All rights reserved.
*/
-/* date: Thu May 27 17:35:19 2021 */
+/* date: Tue Jul 13 12:36:40 2021 */
#ifndef ULP_TEMPLATE_DB_H_
#define ULP_TEMPLATE_DB_H_
-#define BNXT_ULP_REGFILE_MAX_SZ 40
+#define BNXT_ULP_REGFILE_MAX_SZ 42
#define BNXT_ULP_MAX_NUM_DEVICES 4
#define BNXT_ULP_LOG2_MAX_NUM_DEV 2
#define BNXT_ULP_GEN_TBL_MAX_SZ 12
@@ -27,9 +27,9 @@
#define BNXT_ULP_ACT_HID_SHFTL 26
#define BNXT_ULP_ACT_HID_MASK 2047
#define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 8
-#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 43
+#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 62
#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 50
-#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 204
+#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 206
#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 6
#define BNXT_ULP_COND_GOTO_REJECT 1023
#define BNXT_ULP_COND_GOTO_RF 0x10000
@@ -44,23 +44,23 @@
#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 618
#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 49
#define ULP_THOR_CLASS_TMPL_LIST_SIZE 6
-#define ULP_THOR_CLASS_TBL_LIST_SIZE 33
-#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 242
-#define ULP_THOR_CLASS_IDENT_LIST_SIZE 8
-#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 259
-#define ULP_THOR_CLASS_COND_LIST_SIZE 13
+#define ULP_THOR_CLASS_TBL_LIST_SIZE 114
+#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 2305
+#define ULP_THOR_CLASS_IDENT_LIST_SIZE 39
+#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1192
+#define ULP_THOR_CLASS_COND_LIST_SIZE 55
#define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7
#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 35
#define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2
#define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 1
-#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 527
+#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 536
#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 39
#define ULP_THOR_ACT_TMPL_LIST_SIZE 7
-#define ULP_THOR_ACT_TBL_LIST_SIZE 2
-#define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 0
-#define ULP_THOR_ACT_IDENT_LIST_SIZE 0
-#define ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE 18
-#define ULP_THOR_ACT_COND_LIST_SIZE 5
+#define ULP_THOR_ACT_TBL_LIST_SIZE 28
+#define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 2
+#define ULP_THOR_ACT_IDENT_LIST_SIZE 1
+#define ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE 479
+#define ULP_THOR_ACT_COND_LIST_SIZE 20
enum bnxt_ulp_act_bit {
BNXT_ULP_ACT_BIT_MARK = 0x0000000000000001,
@@ -203,7 +203,11 @@ enum bnxt_ulp_cf_idx {
BNXT_ULP_CF_IDX_TUNNEL_ID = 63,
BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID = 64,
BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID = 65,
- BNXT_ULP_CF_IDX_LAST = 66
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID = 66,
+ BNXT_ULP_CF_IDX_OI_VLAN_FB_VID = 67,
+ BNXT_ULP_CF_IDX_IO_VLAN_FB_VID = 68,
+ BNXT_ULP_CF_IDX_II_VLAN_FB_VID = 69,
+ BNXT_ULP_CF_IDX_LAST = 70
};
enum bnxt_ulp_cond_list_opc {
@@ -386,29 +390,42 @@ enum bnxt_ulp_glb_rf_idx {
BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR = 5,
BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 = 6,
BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 = 7,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0 = 8,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1 = 9,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 = 10,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 = 11,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0 = 12,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1 = 13,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 14,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 = 15,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2 = 16,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 17,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 18,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 19,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 20,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 21,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 22,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 23,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 24,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 25,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 26,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 27,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 28,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 29,
- BNXT_ULP_GLB_RF_IDX_LAST = 30
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 = 8,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 = 9,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 = 10,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 = 11,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0 = 12,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1 = 13,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 = 14,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 = 15,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 = 16,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3 = 17,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4 = 18,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0 = 19,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1 = 20,
+ BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0 = 21,
+ BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_1 = 22,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 = 23,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 = 24,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 = 25,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 26,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 = 27,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2 = 28,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 29,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 30,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 31,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 32,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 33,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 34,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 35,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 36,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 37,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 38,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 39,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 40,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 41,
+ BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID = 42,
+ BNXT_ULP_GLB_RF_IDX_LAST = 43
};
enum bnxt_ulp_hdr_type {
@@ -520,7 +537,9 @@ enum bnxt_ulp_rf_idx {
BNXT_ULP_RF_IDX_CC = 37,
BNXT_ULP_RF_IDX_CF_FLOW_SIG_ID = 38,
BNXT_ULP_RF_IDX_PHY_PORT = 39,
- BNXT_ULP_RF_IDX_LAST = 40
+ BNXT_ULP_RF_IDX_METADATA_PROF = 40,
+ BNXT_ULP_RF_IDX_MODIFY_PTR = 41,
+ BNXT_ULP_RF_IDX_LAST = 42
};
enum bnxt_ulp_shared_session {
@@ -693,6 +712,13 @@ enum bnxt_ulp_act_prop_idx {
};
enum ulp_wp_sym {
+ ULP_WP_SYM_METADATA_OP_NORMAL = 0,
+ ULP_WP_SYM_METADATA_OP_L2_HASH = 0,
+ ULP_WP_SYM_METADATA_OP_L4_HASH = 0,
+ ULP_WP_SYM_FWD_OP_BYPASS_CFA = 0,
+ ULP_WP_SYM_FWD_OP_BYPASS_CFA_ROCE = 0,
+ ULP_WP_SYM_FWD_OP_BYPASS_LKUP = 0,
+ ULP_WP_SYM_FWD_OP_NORMAL_FLOW = 0,
ULP_WP_SYM_CTXT_OPCODE_BYPASS_CFA = 0,
ULP_WP_SYM_CTXT_OPCODE_BYPASS_LKUP = 0,
ULP_WP_SYM_CTXT_OPCODE_META_UPDATE = 0,
@@ -843,6 +869,10 @@ enum ulp_wp_sym {
ULP_WP_SYM_L4_HDR_IS_UDP_TCP_YES = 1,
ULP_WP_SYM_POP_VLAN_NO = 0,
ULP_WP_SYM_POP_VLAN_YES = 1,
+ ULP_WP_SYM_VLAN_DEL_RPT_DISABLED = 0,
+ ULP_WP_SYM_VLAN_DEL_RPT_STRIP_OUTER = 0,
+ ULP_WP_SYM_VLAN_DEL_RPT_STRIP_BOTH = 0,
+ ULP_WP_SYM_VLAN_DEL_RPT_DYN_STRIP = 0,
ULP_WP_SYM_DECAP_FUNC_NONE = 0,
ULP_WP_SYM_DECAP_FUNC_THRU_TL2 = 3,
ULP_WP_SYM_DECAP_FUNC_THRU_TL3 = 8,
@@ -916,6 +946,13 @@ enum ulp_wp_sym {
};
enum ulp_thor_sym {
+ ULP_THOR_SYM_METADATA_OP_NORMAL = 0,
+ ULP_THOR_SYM_METADATA_OP_L2_HASH = 1,
+ ULP_THOR_SYM_METADATA_OP_L4_HASH = 2,
+ ULP_THOR_SYM_FWD_OP_BYPASS_CFA = 0,
+ ULP_THOR_SYM_FWD_OP_BYPASS_CFA_ROCE = 1,
+ ULP_THOR_SYM_FWD_OP_BYPASS_LKUP = 2,
+ ULP_THOR_SYM_FWD_OP_NORMAL_FLOW = 3,
ULP_THOR_SYM_CTXT_OPCODE_BYPASS_CFA = 0,
ULP_THOR_SYM_CTXT_OPCODE_BYPASS_LKUP = 1,
ULP_THOR_SYM_CTXT_OPCODE_META_UPDATE = 2,
@@ -1066,6 +1103,10 @@ enum ulp_thor_sym {
ULP_THOR_SYM_L4_HDR_IS_UDP_TCP_YES = 1,
ULP_THOR_SYM_POP_VLAN_NO = 0,
ULP_THOR_SYM_POP_VLAN_YES = 1,
+ ULP_THOR_SYM_VLAN_DEL_RPT_DISABLED = 0,
+ ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER = 1,
+ ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_BOTH = 2,
+ ULP_THOR_SYM_VLAN_DEL_RPT_DYN_STRIP = 3,
ULP_THOR_SYM_DECAP_FUNC_NONE = 0,
ULP_THOR_SYM_DECAP_FUNC_THRU_TL2 = 3,
ULP_THOR_SYM_DECAP_FUNC_THRU_TL3 = 8,
@@ -1122,7 +1163,7 @@ enum ulp_thor_sym {
ULP_THOR_SYM_ACT_REC_POP_VLAN_NO = 0,
ULP_THOR_SYM_ACT_REC_METER_EN_YES = 1,
ULP_THOR_SYM_ACT_REC_METER_EN_NO = 0,
- ULP_THOR_SYM_LOOPBACK_PORT = 3,
+ ULP_THOR_SYM_LOOPBACK_PORT = 16,
ULP_THOR_SYM_LOOPBACK_PARIF = 15,
ULP_THOR_SYM_EXT_EM_MAX_KEY_SIZE = 0,
ULP_THOR_SYM_MATCH_TYPE_EM = 0,
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
index 68f1b5fd00..3d1e95d18c 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 20 11:56:39 2021 */
+/* date: Thu Jul 8 08:44:00 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -187,6 +187,10 @@ const struct bnxt_ulp_template_device_tbls ulp_template_thor_tbls[] = {
.tmpl_list_size = ULP_THOR_ACT_TMPL_LIST_SIZE,
.tbl_list = ulp_thor_act_tbl_list,
.tbl_list_size = ULP_THOR_ACT_TBL_LIST_SIZE,
+ .key_info_list = ulp_thor_act_key_info_list,
+ .key_info_list_size = ULP_THOR_ACT_KEY_INFO_LIST_SIZE,
+ .ident_list = ulp_thor_act_ident_list,
+ .ident_list_size = ULP_THOR_ACT_IDENT_LIST_SIZE,
.cond_list = ulp_thor_act_cond_list,
.cond_list_size = ULP_THOR_ACT_COND_LIST_SIZE,
.result_field_list = ulp_thor_act_result_field_list,
@@ -202,6 +206,7 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE,
.encap_byte_order = BNXT_ULP_BYTE_ORDER_BE,
.wc_key_byte_order = BNXT_ULP_BYTE_ORDER_BE,
+ .em_byte_order = BNXT_ULP_BYTE_ORDER_LE,
.encap_byte_swap = 1,
.int_flow_db_num_entries = 16384,
.ext_flow_db_num_entries = 32768,
@@ -225,11 +230,12 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE,
.encap_byte_order = BNXT_ULP_BYTE_ORDER_BE,
.wc_key_byte_order = BNXT_ULP_BYTE_ORDER_BE,
+ .em_byte_order = BNXT_ULP_BYTE_ORDER_BE,
.encap_byte_swap = 1,
.int_flow_db_num_entries = 16384,
.ext_flow_db_num_entries = 32768,
- .mark_db_lfid_entries = 0,
- .mark_db_gfid_entries = 0,
+ .mark_db_lfid_entries = 65536,
+ .mark_db_gfid_entries = 65536,
.flow_count_db_entries = 16384,
.fdb_parent_flow_entries = 2,
.num_resources_per_flow = 8,
@@ -909,6 +915,14 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = {
{
.app_id = 0,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
@@ -941,12 +955,156 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = {
{
.app_id = 0,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
.direction = TF_DIR_RX
},
{
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
.app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1204,7 +1362,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 63
+ .count = 15
},
{
.app_id = 0,
@@ -1666,6 +1824,14 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.app_id = 0,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
.count = 200
@@ -1703,6 +1869,14 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 15232
},
{
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .count = 1
+ },
+ {
.app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
index 9faf25aaf0..223ecbf843 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Wed May 26 15:11:34 2021 */
+/* date: Thu Jul 8 08:44:00 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -15,16 +15,88 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {
/* act_tid: 1, ingress */
[1] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 2,
+ .num_tbls = 4,
.start_tbl_idx = 0,
.reject_info = {
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
.cond_start_idx = 0,
- .cond_nums = 4 }
+ .cond_nums = 0 }
+ },
+ /* act_tid: 2, ingress */
+ [2] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 6,
+ .start_tbl_idx = 4,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 3,
+ .cond_nums = 0 }
+ },
+ /* act_tid: 3, ingress */
+ [3] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 4,
+ .start_tbl_idx = 10,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 4,
+ .cond_nums = 0 }
+ },
+ /* act_tid: 4, egress */
+ [4] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 4,
+ .start_tbl_idx = 14,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 7,
+ .cond_nums = 0 }
+ },
+ /* act_tid: 5, egress */
+ [5] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 4,
+ .start_tbl_idx = 18,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 10,
+ .cond_nums = 0 }
+ },
+ /* act_tid: 6, egress */
+ [6] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 6,
+ .start_tbl_idx = 22,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 13,
+ .cond_nums = 0 }
}
};
struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
+ { /* act_tid: 1, , table: shared_mirror_record.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 0,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .key_start_idx = 0,
+ .blob_key_bit_size = 1,
+ .key_bit_size = 1,
+ .key_num_fields = 1,
+ .ident_start_idx = 0,
+ .ident_nums = 1
+ },
{ /* act_tid: 1, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
@@ -35,7 +107,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 4,
+ .cond_start_idx = 1,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
@@ -45,73 +117,4205 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.result_bit_size = 64,
.result_num_fields = 1
},
- { /* act_tid: 1, , table: int_full_act_record.0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 0,
- .cond_false_goto = 0,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 5,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 1,
- .result_bit_size = 128,
- .result_num_fields = 17
- }
-};
-
-struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = {
- /* cond_reject: thor, act_tid: 1 */
+ { /* act_tid: 1, , table: mod_record.ing_ttl */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 2,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 1,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 1, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 3,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 48,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* act_tid: 2, , table: control.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 3,
+ .cond_nums = 0 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* act_tid: 2, , table: mirror_tbl.alloc */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 3,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 65,
+ .result_bit_size = 32,
+ .result_num_fields = 5
+ },
+ { /* act_tid: 2, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 3,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 70,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 2, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 4,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 71,
+ .result_bit_size = 128,
+ .result_num_fields = 17,
+ .encap_num_fields = 0
+ },
+ { /* act_tid: 2, , table: mirror_tbl.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 4,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 88,
+ .result_bit_size = 32,
+ .result_num_fields = 5
+ },
+ { /* act_tid: 2, , table: shared_mirror_record.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 4,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .key_start_idx = 1,
+ .blob_key_bit_size = 1,
+ .key_bit_size = 1,
+ .key_num_fields = 1,
+ .result_start_idx = 93,
+ .result_bit_size = 36,
+ .result_num_fields = 2
+ },
+ { /* act_tid: 3, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 4,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 95,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 3, , table: mod_record.ing_ttl */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 5,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 96,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 3, , table: mod_record.ing_no_ttl */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 6,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 143,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 3, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 7,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 190,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* act_tid: 4, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 7,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 207,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 4, , table: int_vtag_encap_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 8,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 8,
+ .result_start_idx = 208,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 11
+ },
+ { /* act_tid: 4, , table: mod_record.dec_ttl_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 9,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 219,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 4, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 10,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 266,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* act_tid: 5, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 10,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 283,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 5, , table: mod_record.ing_ttl */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 11,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 284,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 5, , table: mod_record.ing_no_ttl */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 12,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 331,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 5, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 13,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 378,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* act_tid: 6, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 13,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 395,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 6, , table: sp_smac_ipv4.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 14,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 16,
+ .result_start_idx = 396,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 3
+ },
+ { /* act_tid: 6, , table: sp_smac_ipv6.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 15,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 32,
+ .result_start_idx = 399,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 3
+ },
+ { /* act_tid: 6, , table: int_tun_encap_record.ipv4_vxlan */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 16,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 402,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 30
+ },
+ { /* act_tid: 6, , table: int_tun_encap_record.ipv6_vxlan */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 18,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 432,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 30
+ },
+ { /* act_tid: 6, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 20,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 462,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ }
+};
+
+struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = {
+ /* cond_execute: act_tid: 1, shared_mirror_record.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+ },
+ /* cond_execute: act_tid: 1, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 1, mod_record.ing_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 2, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 3, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 3, mod_record.ing_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 3, mod_record.ing_no_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 4, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 4, int_vtag_encap_record.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
+ },
+ /* cond_execute: act_tid: 4, mod_record.dec_ttl_egr */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 5, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 5, mod_record.ing_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 5, mod_record.ing_no_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 6, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 6, sp_smac_ipv4.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG
+ },
+ /* cond_execute: act_tid: 6, sp_smac_ipv6.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG
+ },
+ /* cond_execute: act_tid: 6, int_tun_encap_record.ipv4_vxlan */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: act_tid: 6, int_tun_encap_record.ipv6_vxlan */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ }
+};
+
+struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = {
+ /* act_tid: 1, , table: shared_mirror_record.rd */
+ {
+ .field_info_mask = {
+ .description = "shared_index",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "shared_index",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff}
+ }
+ },
+ /* act_tid: 2, , table: shared_mirror_record.wr */
+ {
+ .field_info_mask = {
+ .description = "shared_index",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "shared_index",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
+ }
+ }
+};
+
+struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
+ /* act_tid: 1, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 1, , table: mod_record.ing_ttl */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ /* act_tid: 1, , table: int_full_act_record.0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr2 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_DECAP_FUNC_THRU_TUN},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_DECAP_FUNC_NONE}
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr2 = {
+ (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 2, , table: mirror_tbl.alloc */
+ {
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 13,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ignore_drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "copy_ing_or_egr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "enable",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 2, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 2, , table: int_full_act_record.0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 2, , table: mirror_tbl.wr */
+ {
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 13,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ignore_drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "copy_ing_or_egr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "enable",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 2, , table: shared_mirror_record.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "mirror_id",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
+ },
+ /* act_tid: 3, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 3, , table: mod_record.ing_ttl */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ /* act_tid: 3, , table: mod_record.ing_no_ttl */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ /* act_tid: 3, , table: int_full_act_record.0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 4, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 4, , table: int_vtag_encap_record.0 */
+ {
+ .description = "ecv_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
+ },
+ {
+ .description = "ecv_l2_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vtag_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}
+ },
+ {
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
+ },
+ {
+ .description = "vtag_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vtag_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
+ },
+ /* act_tid: 4, , table: mod_record.dec_ttl_egr */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ /* act_tid: 4, , table: int_full_act_record.0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
+ },
+ {
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 5, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 5, , table: mod_record.ing_ttl */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ /* act_tid: 5, , table: mod_record.ing_no_ttl */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ /* act_tid: 5, , table: int_full_act_record.0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 6, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 6, , table: sp_smac_ipv4.0 */
+ {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
+ },
+ {
+ .description = "ipv4_src_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 6, , table: sp_smac_ipv6.0 */
+ {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
+ },
+ {
+ .description = "ipv6_src_addr",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_SADDR & 0xff}
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 6, , table: int_tun_encap_record.ipv4_vxlan */
+ {
+ .description = "ecv_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_VALID_YES}
+ },
+ {
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
+ },
+ {
+ .description = "ecv_l2_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_L2_EN_YES}
+ },
+ {
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
+ },
+ {
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_L4_TYPE_UDP_CSUM}
+ },
+ {
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_TUN_TYPE_VXLAN}
+ },
+ {
+ .description = "enc_eth_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
+ },
+ {
+ .description = "enc_o_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_o_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_ihl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff}
+ },
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_POP_VLAN
+ .description = "enc_ipv4_tos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff}
},
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ .description = "enc_ipv4_pkt_id",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff}
},
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_VXLAN_DECAP
+ .description = "enc_ipv4_frag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff}
},
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+ .description = "enc_ipv4_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff}
},
- /* cond_execute: act_tid: 1, int_flow_counter_tbl.0 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_COUNT
- }
-};
-
-struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
- /* act_tid: 1, , table: int_flow_counter_tbl.0 */
+ .description = "enc_ipv4_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff}
+ },
{
- .description = "count",
- .field_bit_size = 64,
+ .description = "enc_ipv4_daddr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}
+ },
+ {
+ .description = "enc_ipv6_vtc",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv6_zero",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv6_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv6_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv6_daddr",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
+ },
+ {
+ .description = "enc_udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
+ },
+ {
+ .description = "enc_vxlan_flags",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}
+ },
+ {
+ .description = "enc_vxlan_rsvd0",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}
+ },
+ {
+ .description = "enc_vxlan_vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
+ },
+ {
+ .description = "enc_vxlan_rsvd1",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}
+ },
+ /* act_tid: 6, , table: int_tun_encap_record.ipv6_vxlan */
+ {
+ .description = "ecv_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_VALID_YES}
+ },
+ {
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 1, , table: int_full_act_record.0 */
{
- .description = "sp_rec_ptr",
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
+ },
+ {
+ .description = "ecv_l2_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_L2_EN_YES}
+ },
+ {
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
+ },
+ {
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_L4_TYPE_UDP_CSUM}
+ },
+ {
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_TUN_TYPE_VXLAN}
+ },
+ {
+ .description = "enc_eth_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
+ },
+ {
+ .description = "enc_o_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_o_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_ihl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv4_tos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv4_pkt_id",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv4_frag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv4_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv4_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv4_daddr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv6_vtc",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff}
+ },
+ {
+ .description = "enc_ipv6_zero",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
+ .description = "enc_ipv6_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff}
+ },
+ {
+ .description = "enc_ipv6_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff}
+ },
+ {
+ .description = "enc_ipv6_daddr",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff}
+ },
+ {
+ .description = "enc_udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
+ },
+ {
+ .description = "enc_udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
+ },
+ {
+ .description = "enc_vxlan_flags",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}
+ },
+ {
+ .description = "enc_vxlan_rsvd0",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}
+ },
+ {
+ .description = "enc_vxlan_vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
+ },
+ {
+ .description = "enc_vxlan_rsvd1",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}
+ },
+ /* act_tid: 6, , table: int_full_act_record.0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_SP_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_SP_PTR & 0xff}
+ },
+ {
.description = "encap_ptr",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
},
{
.description = "mod_rec_ptr",
@@ -164,8 +4368,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
},
{
.description = "use_default",
@@ -195,16 +4399,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "drop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "hit",
@@ -221,3 +4416,13 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
1}
}
};
+
+struct bnxt_ulp_mapper_ident_info ulp_thor_act_ident_list[] = {
+ /* act_tid: 1, , table: shared_mirror_record.rd */
+ {
+ .description = "mirror_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_MIRROR_ID_0,
+ .ident_bit_size = 4,
+ .ident_bit_pos = 32
+ }
+};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
index ea9b9773a5..bcb204ae13 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Wed May 26 15:11:34 2021 */
+/* date: Fri Jul 30 09:57:44 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -15,32 +15,52 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {
/* class_tid: 1, ingress */
[1] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 12,
+ .num_tbls = 28,
.start_tbl_idx = 0,
.reject_info = {
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 0,
- .cond_nums = 4 }
+ .cond_nums = 1 }
+ },
+ /* class_tid: 2, ingress */
+ [2] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 17,
+ .start_tbl_idx = 28,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 29,
+ .cond_nums = 0 }
+ },
+ /* class_tid: 3, egress */
+ [3] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 24,
+ .start_tbl_idx = 45,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 36,
+ .cond_nums = 0 }
},
/* class_tid: 4, ingress */
[4] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 15,
- .start_tbl_idx = 12,
+ .num_tbls = 21,
+ .start_tbl_idx = 69,
.reject_info = {
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 8,
- .cond_nums = 1 }
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 }
},
/* class_tid: 5, egress */
[5] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 6,
- .start_tbl_idx = 27,
+ .num_tbls = 24,
+ .start_tbl_idx = 90,
.reject_info = {
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 12,
- .cond_nums = 1 }
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 }
}
};
@@ -54,7 +74,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 4,
+ .cond_start_idx = 1,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
@@ -76,7 +96,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 5,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 4,
+ .cond_start_idx = 1,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
@@ -97,7 +117,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 5,
+ .cond_start_idx = 2,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
@@ -116,7 +136,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 3,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 5,
+ .cond_start_idx = 2,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
@@ -129,7 +149,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 6,
+ .cond_start_idx = 3,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
@@ -156,7 +176,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 6,
+ .cond_start_idx = 3,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
@@ -169,17 +189,28 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 1, , table: profile_tcam_cache.l3_l4_rd */
+ { /* class_tid: 1, , table: control.ipv6_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 8,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 3,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* class_tid: 1, , table: profile_tcam_cache.ipv6_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 6,
- .cond_nums = 0 },
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 4,
+ .cond_nums = 1 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
@@ -188,23 +219,41 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.key_bit_size = 14,
.key_num_fields = 3,
.ident_start_idx = 6,
- .ident_nums = 0
+ .ident_nums = 4
},
- { /* class_tid: 1, , table: control.l3_l4 */
+ { /* class_tid: 1, , table: control.ipv6_prof_cache_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 4,
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 6,
+ .cond_start_idx = 5,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 1, , table: fkb_select.l3_l4_wm */
+ { /* class_tid: 1, , table: control.v6_conflict_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 4,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 6,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .func_info = {
+ .func_opc = BNXT_ULP_FUNC_OPC_EQ,
+ .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
+ .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
+ .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
+ },
+ { /* class_tid: 1, , table: fkb_select.l2_l3_l4_v6_em */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
@@ -212,23 +261,24 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 7,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
- .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
.result_start_idx = 10,
.result_bit_size = 106,
.result_num_fields = 106
},
- { /* class_tid: 1, , table: profile_tcam.l3_l4 */
+ { /* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 7,
- .cond_nums = 0 },
+ .cond_nums = 1 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
@@ -244,11 +294,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_start_idx = 116,
.result_bit_size = 33,
.result_num_fields = 8,
- .ident_start_idx = 6,
- .ident_nums = 0
+ .ident_start_idx = 10,
+ .ident_nums = 1
},
- { /* class_tid: 1, , table: profile_tcam_cache.l3_l4_wr */
+ { /* class_tid: 1, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_RX,
@@ -256,7 +307,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 7,
+ .cond_start_idx = 8,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
@@ -269,4026 +320,39779 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 138,
.result_num_fields = 7
},
- { /* class_tid: 1, , table: wm.l3_l4 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ { /* class_tid: 1, , table: em.l2_l3_l4_v6.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_INTERNAL,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 0,
- .cond_false_goto = 0,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 7,
- .cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 8,
+ .cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
- .pri_operand = 0,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.key_start_idx = 82,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
.result_start_idx = 131,
- .result_bit_size = 38,
- .result_num_fields = 5
+ .result_bit_size = 0,
+ .result_num_fields = 6
},
- { /* class_tid: 4, , table: int_full_act_record.0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ { /* class_tid: 1, , table: profile_tcam_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 9,
+ .cond_start_idx = 8,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 136,
- .result_bit_size = 128,
- .result_num_fields = 17
+ .key_start_idx = 196,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .ident_start_idx = 11,
+ .ident_nums = 2
},
- { /* class_tid: 4, , table: port_table.wr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
+ { /* class_tid: 1, , table: control.gen_tbl_miss */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 9,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 196,
- .blob_key_bit_size = 10,
- .key_bit_size = 10,
- .key_num_fields = 1,
- .result_start_idx = 153,
- .result_bit_size = 152,
- .result_num_fields = 5
+ .cond_false_goto = 6,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 8,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ { /* class_tid: 1, , table: fkb_select.l3_l4_wm */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 9,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 197,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .ident_start_idx = 6,
- .ident_nums = 0
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 137,
+ .result_bit_size = 106,
+ .result_num_fields = 106
},
- { /* class_tid: 4, , table: control.ing_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ { /* class_tid: 1, , table: fkb_select.l3_l4_wm_vxlan */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 3,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 9,
+ .cond_start_idx = 10,
.cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 243,
+ .result_bit_size = 106,
+ .result_num_fields = 106
},
- { /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
+ { /* class_tid: 1, , table: profile_tcam.l3_l4.ip */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 11,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 199,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 349,
+ .result_bit_size = 33,
+ .result_num_fields = 8,
+ .ident_start_idx = 13,
+ .ident_nums = 0
+ },
+ { /* class_tid: 1, , table: profile_tcam.l3_l4.vxlan */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 10,
- .cond_nums = 0 },
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 13,
+ .cond_nums = 1 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 198,
- .blob_key_bit_size = 213,
- .key_bit_size = 213,
- .key_num_fields = 21,
- .result_start_idx = 158,
- .result_bit_size = 43,
- .result_num_fields = 6,
- .ident_start_idx = 6,
- .ident_nums = 1
+ .key_start_idx = 242,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 357,
+ .result_bit_size = 33,
+ .result_num_fields = 8,
+ .ident_start_idx = 13,
+ .ident_nums = 0
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
+ { /* class_tid: 1, , table: profile_tcam_cache.wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 10,
+ .cond_start_idx = 14,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 219,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .result_start_idx = 164,
- .result_bit_size = 62,
- .result_num_fields = 4
+ .key_start_idx = 285,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .result_start_idx = 365,
+ .result_bit_size = 138,
+ .result_num_fields = 7
},
- { /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+ { /* class_tid: 1, , table: wm.l3_l4.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 10,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 168,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 14,
+ .cond_nums = 3 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 288,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 372,
+ .result_bit_size = 38,
+ .result_num_fields = 5
},
- { /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
- .direction = TF_DIR_RX,
+ { /* class_tid: 1, , table: wm.l3_l4.ipv6 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 10,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 169,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 17,
+ .cond_nums = 3 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 402,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 377,
+ .result_bit_size = 38,
+ .result_num_fields = 5
},
- { /* class_tid: 4, , table: control.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ { /* class_tid: 1, , table: wm.l3.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 0,
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 10,
+ .cond_start_idx = 20,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 516,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 382,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 1, , table: wm.l3.ipv6 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 22,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 630,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 387,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 1, , table: wm.l2 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 24,
.cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 744,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 392,
+ .result_bit_size = 38,
+ .result_num_fields = 5
},
- { /* class_tid: 4, , table: int_full_act_record.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ { /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 25,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 858,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 397,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv6 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 27,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 972,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 402,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 2, , table: port_table.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 11,
+ .cond_start_idx = 29,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 170,
- .result_bit_size = 128,
- .result_num_fields = 17,
- .encap_num_fields = 0
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .key_start_idx = 1086,
+ .blob_key_bit_size = 10,
+ .key_bit_size = 10,
+ .key_num_fields = 1,
+ .ident_start_idx = 13,
+ .ident_nums = 3
},
- { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */
+ { /* class_tid: 2, , table: tunnel_cache.rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 11,
+ .cond_start_idx = 29,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 220,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .ident_start_idx = 7,
- .ident_nums = 0
+ .key_start_idx = 1087,
+ .blob_key_bit_size = 16,
+ .key_bit_size = 16,
+ .key_num_fields = 2,
+ .ident_start_idx = 16,
+ .ident_nums = 1
},
- { /* class_tid: 4, , table: control.egr_1 */
+ { /* class_tid: 2, , table: control.tunnel_cache_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 2,
+ .cond_false_goto = 3,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 11,
+ .cond_start_idx = 29,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
+ { /* class_tid: 2, , table: l2_cntxt_tcam.1 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .direction = TF_DIR_TX,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 12,
+ .cond_start_idx = 30,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT,
.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 221,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .key_start_idx = 1089,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
- .result_start_idx = 187,
+ .result_start_idx = 407,
.result_bit_size = 43,
.result_num_fields = 6,
- .ident_start_idx = 7,
+ .ident_start_idx = 17,
.ident_nums = 1
},
- { /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
- .direction = TF_DIR_TX,
+ { /* class_tid: 2, , table: tunnel_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 12,
+ .cond_start_idx = 30,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 193,
- .result_bit_size = 32,
- .result_num_fields = 1
- },
- { /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
- .direction = TF_DIR_TX,
+ .key_start_idx = 1110,
+ .blob_key_bit_size = 16,
+ .key_bit_size = 16,
+ .key_num_fields = 2,
+ .result_start_idx = 413,
+ .result_bit_size = 52,
+ .result_num_fields = 3
+ },
+ { /* class_tid: 2, , table: control.flow_type_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 0,
- .cond_false_goto = 0,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 12,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 194,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .cond_true_goto = 1,
+ .cond_false_goto = 5,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 30,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
- { /* class_tid: 5, , table: int_full_act_record.loopback */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ { /* class_tid: 2, , table: mac_addr_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 13,
+ .cond_start_idx = 31,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE,
- .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 195,
- .result_bit_size = 128,
- .result_num_fields = 17,
- .encap_num_fields = 0
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1112,
+ .blob_key_bit_size = 73,
+ .key_bit_size = 73,
+ .key_num_fields = 5,
+ .ident_start_idx = 18,
+ .ident_nums = 1
},
- { /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
- .direction = TF_DIR_TX,
+ { /* class_tid: 2, , table: control.mac_addr_cache_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 31,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 2, , table: l2_cntxt_tcam.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 13,
+ .cond_start_idx = 32,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
- .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 212,
- .result_bit_size = 32,
- .result_num_fields = 1
- },
- { /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
- .direction = TF_DIR_TX,
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .key_start_idx = 1117,
+ .blob_key_bit_size = 213,
+ .key_bit_size = 213,
+ .key_num_fields = 21,
+ .result_start_idx = 416,
+ .result_bit_size = 43,
+ .result_num_fields = 6,
+ .ident_start_idx = 19,
+ .ident_nums = 0
+ },
+ { /* class_tid: 2, , table: mac_addr_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 13,
+ .cond_start_idx = 32,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
- .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 213,
- .result_bit_size = 32,
- .result_num_fields = 1
+ .key_start_idx = 1138,
+ .blob_key_bit_size = 73,
+ .key_bit_size = 73,
+ .key_num_fields = 5,
+ .result_start_idx = 422,
+ .result_bit_size = 62,
+ .result_num_fields = 4
},
- { /* class_tid: 5, , table: int_full_act_record.vf_ing */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 13,
+ .cond_start_idx = 32,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
- .result_start_idx = 214,
- .result_bit_size = 128,
- .result_num_fields = 17,
- .encap_num_fields = 0
+ .key_start_idx = 1143,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .ident_start_idx = 19,
+ .ident_nums = 3
+ },
+ { /* class_tid: 2, , table: control.profile_tcam_cache.f2_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 4,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 32,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 5, , table: vtag_encap_record.vfr_egr0 */
+ { /* class_tid: 2, , table: fkb_select.f2_wm */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 33,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 426,
+ .result_bit_size = 106,
+ .result_num_fields = 106
+ },
+ { /* class_tid: 2, , table: profile_tcam.f2 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 34,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 1,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 1146,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 532,
+ .result_bit_size = 33,
+ .result_num_fields = 8
+ },
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 13,
+ .cond_start_idx = 34,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1189,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .result_start_idx = 540,
+ .result_bit_size = 138,
+ .result_num_fields = 7
+ },
+ { /* class_tid: 2, , table: wm.l3_l4.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 34,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .record_size = 16,
- .result_start_idx = 231,
- .result_bit_size = 0,
- .result_num_fields = 0,
- .encap_num_fields = 11
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 1192,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 547,
+ .result_bit_size = 38,
+ .result_num_fields = 5
},
- { /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
+ { /* class_tid: 2, , table: wm.l3_l4.ipv6 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 0,
.cond_false_goto = 0,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 13,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 35,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 242,
- .result_bit_size = 128,
- .result_num_fields = 17
- }
-};
-
-struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {
- /* cond_reject: thor, class_tid: 1 */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
- .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 1306,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 552,
+ .result_bit_size = 38,
+ .result_num_fields = 5
},
- {
- .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET,
- .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC
+ { /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 6,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 36,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1420,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 22,
+ .ident_nums = 1
},
- {
- .cond_opcode = BNXT_ULP_COND_OPC_FLOW_PAT_MATCH,
- .cond_operand = 2
+ { /* class_tid: 3, , table: mac_addr_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 37,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1421,
+ .blob_key_bit_size = 73,
+ .key_bit_size = 73,
+ .key_num_fields = 5,
+ .ident_start_idx = 23,
+ .ident_nums = 1
},
- {
- .cond_opcode = BNXT_ULP_COND_OPC_FLOW_PAT_MATCH,
- .cond_operand = 3
+ { /* class_tid: 3, , table: control.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 4,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 37,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
- /* cond_execute: class_tid: 1, l2_cntxt_tcam_cache.rd */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET,
- .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC
+ { /* class_tid: 3, , table: port_table.egr.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 38,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .key_start_idx = 1426,
+ .blob_key_bit_size = 10,
+ .key_bit_size = 10,
+ .key_num_fields = 1,
+ .ident_start_idx = 24,
+ .ident_nums = 3
},
- /* cond_execute: class_tid: 1, control.0 */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
- .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ { /* class_tid: 3, , table: l2_cntxt_tcam.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 38,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .key_start_idx = 1427,
+ .blob_key_bit_size = 213,
+ .key_bit_size = 213,
+ .key_num_fields = 21,
+ .result_start_idx = 557,
+ .result_bit_size = 43,
+ .result_num_fields = 6,
+ .ident_start_idx = 27,
+ .ident_nums = 1
},
- /* cond_execute: class_tid: 1, control.l3_l4 */
- {
+ { /* class_tid: 3, , table: mac_addr_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 38,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1448,
+ .blob_key_bit_size = 73,
+ .key_bit_size = 73,
+ .key_num_fields = 5,
+ .result_start_idx = 563,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 3, , table: control.ipv6_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 8,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 38,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* class_tid: 3, , table: profile_tcam_cache.ipv6_rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 39,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1453,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .ident_start_idx = 28,
+ .ident_nums = 4
+ },
+ { /* class_tid: 3, , table: control.ipv6_prof_cache_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 40,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 3, , table: control.v6_conflict_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 4,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 41,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .func_info = {
+ .func_opc = BNXT_ULP_FUNC_OPC_EQ,
+ .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
+ .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
+ .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
+ },
+ { /* class_tid: 3, , table: fkb_select.l2_l3_l4_v6_em */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 42,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .result_start_idx = 567,
+ .result_bit_size = 106,
+ .result_num_fields = 106
+ },
+ { /* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 42,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 1456,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 673,
+ .result_bit_size = 33,
+ .result_num_fields = 8,
+ .ident_start_idx = 32,
+ .ident_nums = 1
+ },
+ { /* class_tid: 3, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 42,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1499,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .result_start_idx = 681,
+ .result_bit_size = 138,
+ .result_num_fields = 7
+ },
+ { /* class_tid: 3, , table: em.l2_l3_l4_v6.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_INTERNAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 42,
+ .cond_nums = 0 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 1502,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 688,
+ .result_bit_size = 0,
+ .result_num_fields = 6
+ },
+ { /* class_tid: 3, , table: profile_tcam_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 42,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1616,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .ident_start_idx = 33,
+ .ident_nums = 2
+ },
+ { /* class_tid: 3, , table: control.gen_tbl_miss */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 42,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 3, , table: control.conflict_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 5,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 43,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .func_info = {
+ .func_opc = BNXT_ULP_FUNC_OPC_EQ,
+ .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
+ .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
+ .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
+ },
+ { /* class_tid: 3, , table: fkb_select.l3_l4_wc */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 44,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 694,
+ .result_bit_size = 106,
+ .result_num_fields = 106
+ },
+ { /* class_tid: 3, , table: profile_tcam.l3_l4.ip */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 44,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 1619,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 800,
+ .result_bit_size = 33,
+ .result_num_fields = 8,
+ .ident_start_idx = 35,
+ .ident_nums = 0
+ },
+ { /* class_tid: 3, , table: profile_tcam.l3_l4.nonip */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 45,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 1662,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 808,
+ .result_bit_size = 33,
+ .result_num_fields = 8,
+ .ident_start_idx = 35,
+ .ident_nums = 0
+ },
+ { /* class_tid: 3, , table: profile_tcam_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 45,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1705,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .result_start_idx = 816,
+ .result_bit_size = 138,
+ .result_num_fields = 7
+ },
+ { /* class_tid: 3, , table: wm.l3_l4.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 45,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 1708,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 823,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 3, , table: wm.l3.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 47,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 1822,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 828,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 3, , table: wm.l2 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 1936,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 833,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 4, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 838,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* class_tid: 4, , table: port_table.ing_wr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2050,
+ .blob_key_bit_size = 10,
+ .key_bit_size = 10,
+ .key_num_fields = 1,
+ .result_start_idx = 855,
+ .result_bit_size = 152,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 48,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2051,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 35,
+ .ident_nums = 0
+ },
+ { /* class_tid: 4, , table: control.ing_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 48,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 2052,
+ .blob_key_bit_size = 213,
+ .key_bit_size = 213,
+ .key_num_fields = 21,
+ .result_start_idx = 860,
+ .result_bit_size = 43,
+ .result_num_fields = 6,
+ .ident_start_idx = 35,
+ .ident_nums = 1
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2073,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 866,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 870,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 871,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 4, , table: int_full_act_record.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 872,
+ .result_bit_size = 128,
+ .result_num_fields = 17,
+ .encap_num_fields = 0
+ },
+ { /* class_tid: 4, , table: port_table.egr_wr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 49,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2074,
+ .blob_key_bit_size = 10,
+ .key_bit_size = 10,
+ .key_num_fields = 1,
+ .result_start_idx = 889,
+ .result_bit_size = 152,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 4, , table: control.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 5,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 49,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd_vfr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 50,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2075,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 36,
+ .ident_nums = 0
+ },
+ { /* class_tid: 4, , table: control.egr_1 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 50,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 4, , table: ilt_tbl.egr_vfr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_ILT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 51,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .result_start_idx = 894,
+ .result_bit_size = 64,
+ .result_num_fields = 8
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 51,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2076,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 902,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 51,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2077,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 36,
+ .ident_nums = 0
+ },
+ { /* class_tid: 4, , table: control.egr_2 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 51,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 2078,
+ .blob_key_bit_size = 213,
+ .key_bit_size = 213,
+ .key_num_fields = 21,
+ .result_start_idx = 906,
+ .result_bit_size = 43,
+ .result_num_fields = 6,
+ .ident_start_idx = 36,
+ .ident_nums = 1
+ },
+ { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2099,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 912,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 916,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 917,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 5, , table: int_full_act_record.loopback */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 918,
+ .result_bit_size = 128,
+ .result_num_fields = 17,
+ .encap_num_fields = 0
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2100,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 37,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: control.vf_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 52,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 53,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .key_start_idx = 2101,
+ .blob_key_bit_size = 213,
+ .key_bit_size = 213,
+ .key_num_fields = 21,
+ .result_start_idx = 935,
+ .result_bit_size = 43,
+ .result_num_fields = 6,
+ .ident_start_idx = 37,
+ .ident_nums = 1
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 53,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2122,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 941,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 53,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
+ .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 945,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 53,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
+ .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 946,
+ .result_bit_size = 32,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 5, , table: int_full_act_record.vf_ing */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 53,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
+ .result_start_idx = 947,
+ .result_bit_size = 128,
+ .result_num_fields = 17,
+ .encap_num_fields = 0
+ },
+ { /* class_tid: 5, , table: ilt_tbl.vf_ing */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_ILT,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 53,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_SVIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 964,
+ .result_bit_size = 64,
+ .result_num_fields = 8
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.rd_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 53,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2123,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 38,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: control.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 53,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 5, , table: ilt_tbl.vfr_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_ILT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .result_start_idx = 972,
+ .result_bit_size = 64,
+ .result_num_fields = 8
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2124,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .result_start_idx = 980,
+ .result_bit_size = 62,
+ .result_num_fields = 4
+ },
+ { /* class_tid: 5, , table: metadata_record.vfr_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 984,
+ .result_bit_size = 16,
+ .result_num_fields = 1
+ },
+ { /* class_tid: 5, , table: mod_record.vfr_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 64,
+ .result_start_idx = 985,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* class_tid: 5, , table: int_full_act_record.vfr_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 1032,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_rd_vfr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2125,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 38,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: control.ing_rd_vfr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 5,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 54,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam.vfr_ing0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 2126,
+ .blob_key_bit_size = 213,
+ .key_bit_size = 213,
+ .key_num_fields = 21,
+ .result_start_idx = 1049,
+ .result_bit_size = 43,
+ .result_num_fields = 6,
+ .ident_start_idx = 38,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: fkb_select.vfr_em */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 1055,
+ .result_bit_size = 106,
+ .result_num_fields = 106
+ },
+ { /* class_tid: 5, , table: profile_tcam.vfr_ing0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 2147,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 1161,
+ .result_bit_size = 33,
+ .result_num_fields = 8
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_wr_vfr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2190,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 38,
+ .ident_nums = 1
+ },
+ { /* class_tid: 5, , table: int_full_act_record.vfr_ing0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 1169,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* class_tid: 5, , table: em.vfr.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_INTERNAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 2191,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 1186,
+ .result_bit_size = 0,
+ .result_num_fields = 6
+ }
+};
+
+struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {
+ /* cond_reject: thor, class_tid: 1 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH
+ },
+ /* cond_execute: class_tid: 1, l2_cntxt_tcam_cache.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC
+ },
+ /* cond_execute: class_tid: 1, control.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 1, control.ipv6_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ },
+ /* cond_execute: class_tid: 1, profile_tcam_cache.ipv6_rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH
+ },
+ /* cond_execute: class_tid: 1, control.ipv6_prof_cache_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 1, control.v6_conflict_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_CC
+ },
+ /* cond_execute: class_tid: 1, profile_tcam.l2_l3_l4_v6_em */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, control.gen_tbl_miss */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 1, fkb_select.l3_l4_wm */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, fkb_select.l3_l4_wm_vxlan */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, profile_tcam.l3_l4.ip */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_O_L3
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, profile_tcam.l3_l4.vxlan */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, wm.l3_l4.ipv4 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_O_L4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, wm.l3_l4.ipv6 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_O_L4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, wm.l3.ipv4 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, wm.l3.ipv6 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, wm.l2 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 1, wm.l3_l4.vxlan.ipv4 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ /* cond_execute: class_tid: 1, wm.l3_l4.vxlan.ipv6 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ },
+ /* cond_execute: class_tid: 2, control.tunnel_cache_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 2, control.flow_type_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_F1
+ },
+ /* cond_execute: class_tid: 2, control.mac_addr_cache_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 2, control.profile_tcam_cache.f2_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 2, fkb_select.f2_wm */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: class_tid: 2, wm.l3_l4.ipv4 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ /* cond_execute: class_tid: 2, wm.l3_l4.ipv6 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ },
+ /* cond_execute: class_tid: 3, l2_cntxt_tcam_cache.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC
+ },
+ /* cond_execute: class_tid: 3, control.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 3, control.ipv6_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ },
+ /* cond_execute: class_tid: 3, profile_tcam_cache.ipv6_rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH
+ },
+ /* cond_execute: class_tid: 3, control.ipv6_prof_cache_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 3, control.v6_conflict_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_CC
+ },
+ /* cond_execute: class_tid: 3, control.gen_tbl_miss */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 3, control.conflict_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_CC
+ },
+ /* cond_execute: class_tid: 3, profile_tcam.l3_l4.ip */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_O_L3
+ },
+ /* cond_execute: class_tid: 3, wm.l3_l4.ipv4 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_O_L4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ /* cond_execute: class_tid: 3, wm.l3.ipv4 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ /* cond_execute: class_tid: 4, control.ing_0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 4, control.egr_0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
+ },
+ /* cond_execute: class_tid: 4, control.egr_1 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 4, control.egr_2 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 5, control.vf_0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 5, control.0 */
+ {
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 1, wm.l3_l4 */
+ /* cond_execute: class_tid: 5, control.ing_rd_vfr */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ }
+};
+
+struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
+ /* class_tid: 1, , table: port_table.rd */
+ {
+ .field_info_mask = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: l2_cntxt_tcam_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: mac_addr_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: l2_cntxt_tcam.0 */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 2}
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 1, , table: mac_addr_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.ipv6_rd */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_UDP}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_YES},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_NO}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: em.l2_l3_l4_v6.0 */
+ {
+ .field_info_mask = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: profile_tcam.l3_l4.ip */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_UDP}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L4_HDR_VALID_YES},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L4_HDR_VALID_IGNORE}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV4},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_YES},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_NO}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 1, , table: profile_tcam.l3_l4.vxlan */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL4_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV4},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_TL2_VTAG_PRESENT_YES},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_TL2_VTAG_PRESENT_NO}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 1, , table: wm.l3_l4.ipv4 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 1, , table: wm.l3_l4.ipv6 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 1, , table: wm.l3.ipv4 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 1, , table: wm.l3.ipv6 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 1, , table: wm.l2 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv4 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv6 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 2, , table: port_table.rd */
+ {
+ .field_info_mask = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: tunnel_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_TUNNEL_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_TUNNEL_ID & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 2, , table: tunnel_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_TUNNEL_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_TUNNEL_ID & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: mac_addr_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: l2_cntxt_tcam.0 */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 2}
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 2, , table: mac_addr_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: profile_tcam.f2 */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL4_HDR_TYPE_UDP}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL4_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 2, , table: wm.l3_l4.ipv4 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 2, , table: wm.l3_l4.ipv6 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: mac_addr_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: port_table.egr.rd */
+ {
+ .field_info_mask = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam.0 */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 3, , table: mac_addr_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "one_tag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ },
+ .field_info_spec = {
+ .description = "mac_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam_cache.ipv6_rd */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_UDP}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_YES},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_NO}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: em.l2_l3_l4_v6.0 */
+ {
+ .field_info_mask = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam.l3_l4.ip */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_UDP}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV4},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_YES},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_NO}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam.l3_l4.nonip */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_YES},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L2_VTAG_PRESENT_NO}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L2_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: wm.l3_l4.ipv4 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 3, , table: wm.l3.ipv4 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 3, , table: wm.l2 */
+ {
+ .field_info_mask = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 4, , table: port_table.ing_wr_0 */
+ {
+ .field_info_mask = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: port_table.egr_wr_0 */
+ {
+ .field_info_mask = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dev.port_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd_vfr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.rd_egr0 */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_rd_vfr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam.vfr_ing0 */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: profile_tcam.vfr_ing0 */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_flags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_err",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tl2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hrec_next",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_wr_vfr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: em.vfr.0 */
+ {
+ .field_info_mask = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ }
+};
+
+struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
+ /* class_tid: 1, , table: l2_cntxt_tcam.0 */
+ {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ },
+ {
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ },
+ {
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ },
+ /* class_tid: 1, , table: mac_addr_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: fkb_select.l2_l3_l4_v6_em */
+ {
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "parif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "spif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "lcos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "loopback.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tuntype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tflags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tqos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "terr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ },
+ {
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ },
+ {
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ },
+ {
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}
+ },
+ {
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}
+ },
+ {
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_win.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ },
+ /* class_tid: 1, , table: em.l2_l3_l4_v6.0 */
+ {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: fkb_select.l3_l4_wm */
+ {
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "parif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "spif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "lcos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "loopback.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tuntype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tflags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tqos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "terr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_win.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: fkb_select.l3_l4_wm_vxlan */
+ {
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "parif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "spif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "lcos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "loopback.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tuntype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tflags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tqos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "terr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_win.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.l3_l4.ip */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.l3_l4.vxlan */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 & 0xff}
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ },
+ /* class_tid: 1, , table: wm.l3_l4.ipv4 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 1, , table: wm.l3_l4.ipv6 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 1, , table: wm.l3.ipv4 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 1, , table: wm.l3.ipv6 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 1, , table: wm.l2 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv4 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv6 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
+ {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 2, , table: tunnel_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ /* class_tid: 2, , table: l2_cntxt_tcam.0 */
+ {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
+ },
+ {
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ },
+ {
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ },
+ /* class_tid: 2, , table: mac_addr_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 2, , table: fkb_select.f2_wm */
+ {
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "parif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "spif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "lcos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "loopback.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tuntype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tflags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tqos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "terr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_win.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 2, , table: profile_tcam.f2 */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 & 0xff}
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ },
+ /* class_tid: 2, , table: wm.l3_l4.ipv4 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 2, , table: wm.l3_l4.ipv6 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam.0 */
+ {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}
+ },
+ {
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ },
+ {
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ },
+ /* class_tid: 3, , table: mac_addr_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 3, , table: fkb_select.l2_l3_l4_v6_em */
+ {
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "parif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "spif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "lcos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "loopback.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
{
- .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
- .cond_operand = BNXT_ULP_CF_IDX_O_L4
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_reject: thor, class_tid: 4 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
- .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: class_tid: 4, control.ing_0 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
- .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: class_tid: 4, control.egr_0 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
- .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: class_tid: 4, control.egr_1 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
- .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tuntype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tflags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tqos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "terr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ },
+ {
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ },
+ {
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ },
+ {
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_reject: thor, class_tid: 5 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
- .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
- }
-};
-
-struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
- /* class_tid: 1, , table: port_table.rd */
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
{
- .field_info_mask = {
- .description = "dev.port_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "dev.port_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
- }
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: l2_cntxt_tcam_cache.rd */
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- }
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: mac_addr_cache.rd */
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- }
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
- },
- .field_info_spec = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
- }
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
- },
- .field_info_spec = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
- }
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: l2_cntxt_tcam.0 */
{
- .field_info_mask = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}
},
{
- .field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}
},
{
- .field_info_mask = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_win.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
- },
- .field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
- }
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
- },
- .field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
- }
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- }
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 2}
- },
- .field_info_spec = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- .field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- }
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: mac_addr_cache.wr */
+ /* class_tid: 3, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- }
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .field_info_mask = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
- },
- .field_info_spec = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
- }
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "em_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
- },
- .field_info_spec = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
- }
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam_cache.l3_l4_rd */
{
- .field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "wc_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
- }
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
+ /* class_tid: 3, , table: em.l2_l3_l4_v6.0 */
{
- .field_info_mask = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
- }
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
- /* class_tid: 1, , table: profile_tcam.l3_l4 */
{
- .field_info_mask = {
- .description = "l4_hdr_is_udp_tcp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l4_hdr_is_udp_tcp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
},
{
- .field_info_mask = {
- .description = "l4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_THOR_SYM_L4_HDR_TYPE_TCP},
- .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr3 = {
- ULP_THOR_SYM_L4_HDR_TYPE_UDP}
- }
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
- },
- .field_info_spec = {
- .description = "l4_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
- },
- .field_info_spec = {
- .description = "l4_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
- }
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 3, , table: fkb_select.l3_l4_wc */
{
- .field_info_mask = {
- .description = "ieh",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "ieh",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "l3_ipv6_cmp_dst",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l3_ipv6_cmp_dst",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "parif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "spif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "l3_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "lcos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "l3_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "meta.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "l3_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_L3_HDR_VALID_YES}
- }
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "loopback.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_uc_mc_bc",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "l2_uc_mc_bc",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_hdr_type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "l2_hdr_type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "l2_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "l2_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_L2_HDR_VALID_YES}
- }
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tun_hdr_flags",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tun_hdr_flags",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tun_hdr_err",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tun_hdr_err",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tun_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "tun_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4_hdr_is_udp_tcp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl4_hdr_is_udp_tcp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl4_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "tl4_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3_ipv6_cmp_dst",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl3_ipv6_cmp_dst",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3_ipv6_cmp_src",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl3_ipv6_cmp_src",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3_hdr_isIP",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl3_hdr_isIP",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl3_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl3_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "tl3_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl2_two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl2_vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_uc_mc_bc",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl2_uc_mc_bc",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_hdr_type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tl2_hdr_type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "tl2_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "hrec_next",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "hrec_next",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
- }
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "agg_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "agg_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "pkt_type_0",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "pkt_type_0",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "pkt_type_1",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "pkt_type_1",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- .field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- }
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam_cache.l3_l4_wr */
{
- .field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
- }
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
- }
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l3_l4 */
{
- .field_info_mask = {
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
- }
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
- }
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "lcos",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "lcos",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "meta",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "meta",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "rcyc_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "rcyc_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tuntype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tflags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_l2type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_l2type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tctxts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_dt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_dt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tctxt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_sa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_sa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "tqos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_nvt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_nvt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "terr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "tl2_ovp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ovp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_ovd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ovd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_ovv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ovv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_ovt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ovt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_ivp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ivp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_ivd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ivd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_ivv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ivv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_ivt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ivt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl2_etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.l3type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.l3type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.sip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.sip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "tl3.sip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.sip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.sip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.sip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.dip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.dip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.dip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.dip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "tl3.dip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.dip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.fid.ipv4",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.fid.ipv4",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.fid.ipv6",
- .field_bit_size = 20,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.fid.ipv6",
- .field_bit_size = 20,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.qos",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.qos",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_nonext",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_nonext",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_esp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_esp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_auth",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_auth",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl3.l3err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.l3err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "tl4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "tl4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_win.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tl4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tuntype",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tuntype",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tflags",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tflags",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tids",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tids",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tid",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tid",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 3, , table: profile_tcam.l3_l4.ip */
{
- .field_info_mask = {
- .description = "tctxts",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tctxts",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 & 0xff}
},
{
- .field_info_mask = {
- .description = "tctxt",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tctxt",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
},
{
- .field_info_mask = {
- .description = "tqos",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tqos",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "terr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "terr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_l2type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_l2type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_dt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_dt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 3, , table: profile_tcam.l3_l4.nonip */
{
- .field_info_mask = {
- .description = "l2_sa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_sa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 & 0xff}
},
{
- .field_info_mask = {
- .description = "l2_nvt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_nvt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
},
{
- .field_info_mask = {
- .description = "l2_ovp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ovp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "l2_ovd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ovd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ovv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ovv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ovt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ovt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ivp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ivp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ivd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ivd",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 3, , table: profile_tcam_cache.wr */
{
- .field_info_mask = {
- .description = "l2_ivv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ivv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .field_info_mask = {
- .description = "l2_ivt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_ivt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "l2_etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.l3type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.l3type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "em_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.sip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
- },
- .field_info_spec = {
- .description = "l3.sip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
- }
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.sip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.sip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.sip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.sip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
+ /* class_tid: 3, , table: wm.l3_l4.ipv4 */
{
- .field_info_mask = {
- .description = "l3.dip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
- },
- .field_info_spec = {
- .description = "l3.dip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
- }
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.dip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.dip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.dip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.dip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .field_info_mask = {
- .description = "l3.ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 3, , table: wm.l3.ipv4 */
{
- .field_info_mask = {
- .description = "l3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}
- }
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.fid.ipv4",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.fid.ipv4",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.fid.ipv6",
- .field_bit_size = 20,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.fid.ipv6",
- .field_bit_size = 20,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.qos",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.qos",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .field_info_mask = {
- .description = "l3.ieh_nonext",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_nonext",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 3, , table: wm.l2 */
{
- .field_info_mask = {
- .description = "l3.ieh_esp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_esp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_auth",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_auth",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .field_info_mask = {
- .description = "l3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 4, , table: int_full_act_record.0 */
{
- .field_info_mask = {
- .description = "l3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.l3err.ipv4",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.l3err.ipv4",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.l3err.ipv6",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.l3err.ipv6",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
- },
- .field_info_spec = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
- }
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
- },
- .field_info_spec = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
- }
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}
},
{
- .field_info_mask = {
- .description = "l4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.ack",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.ack",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.win",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.win",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.tsval",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.tsval",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
- {
- .field_info_mask = {
- .description = "l4.txecr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.txecr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ /* class_tid: 4, , table: port_table.ing_wr_0 */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "drv_func.mac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: port_table.wr_0 */
{
- .field_info_mask = {
- .description = "dev.port_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "dev.port_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
- }
+ .description = "drv_func.parent.mac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
- }
+ .description = "phy_port",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "default_arec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
/* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
- .field_info_mask = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
},
{
- .field_info_mask = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
{
- .field_info_mask = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
},
{
- .field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
},
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
{
- .field_info_mask = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
{
- .field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
+ /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
{
- .field_info_mask = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
+ /* class_tid: 4, , table: int_full_act_record.egr_0 */
{
- .field_info_mask = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
- }
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- .field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- }
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
- }
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
- }
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
- .field_info_mask = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 4, , table: port_table.egr_wr_0 */
{
- .field_info_mask = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "drv_func.mac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "drv_func.parent.mac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "phy_port",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "default_arec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
+ /* class_tid: 4, , table: ilt_tbl.egr_vfr */
{
- .field_info_mask = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "ilt_destination",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "fwd_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_FWD_OP_BYPASS_LKUP}
},
{
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
- }
+ .description = "en_ilt_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "en_bd_action",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "en_bd_meta",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "reserved",
+ .field_bit_size = 23,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
{
- .field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .field_info_mask = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- .field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- }
- }
-};
-
-struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
- /* class_tid: 1, , table: l2_cntxt_tcam.0 */
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
.description = "prof_func_id",
.field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
},
@@ -4304,8 +40108,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
.description = "ctxt_opcode",
@@ -4330,10 +40134,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
},
- /* class_tid: 1, , table: mac_addr_cache.wr */
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -4347,7 +40151,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_cntxt_tcam_index",
.field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
},
{
.description = "l2_cntxt_id",
@@ -4364,461 +40171,494 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: fkb_select.l3_l4_wm */
+ /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
{
- .description = "l2_cntxt_id.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- 1}
- },
- {
- .description = "parif.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "spif.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "svif.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "lcos.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "meta.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "rcyc_cnt.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
+ /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
{
- .description = "loopback.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
+ /* class_tid: 5, , table: int_full_act_record.loopback */
{
- .description = "tl2_l2type.en",
- .field_bit_size = 1,
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_dmac.en",
- .field_bit_size = 1,
+ .description = "encap_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_smac.en",
- .field_bit_size = 1,
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_dt.en",
- .field_bit_size = 1,
+ .description = "rsvd1",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_sa.en",
- .field_bit_size = 1,
+ .description = "rsvd0",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_nvt.en",
- .field_bit_size = 1,
+ .description = "decap_func",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovp.en",
- .field_bit_size = 1,
+ .description = "meter",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovd.en",
+ .description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovv.en",
- .field_bit_size = 1,
+ .description = "stats_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovt.en",
- .field_bit_size = 1,
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff,
+ ULP_THOR_SYM_LOOPBACK_PORT & 0xff}
},
{
- .description = "tl2_ivp.en",
+ .description = "use_default",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivd.en",
- .field_bit_size = 1,
+ .description = "mirror",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivv.en",
+ .description = "cond_copy",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivt.en",
- .field_bit_size = 1,
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_etype.en",
+ .description = "drop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_l3type.en",
+ .description = "hit",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_sip.en",
- .field_bit_size = 1,
+ .description = "type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
{
- .description = "tl3_sip_selcmp.en",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
},
{
- .description = "tl3_dip.en",
- .field_bit_size = 1,
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_dip_selcmp.en",
- .field_bit_size = 1,
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
{
- .description = "tl3_ttl.en",
- .field_bit_size = 1,
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
},
{
- .description = "tl3_prot.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .description = "tl3_fid.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_LOOPBACK_PARIF}
},
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
{
- .description = "tl3_qos.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "tl3_ieh_nonext.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
},
{
- .description = "tl3_ieh_esp.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .description = "tl3_ieh_auth.en",
- .field_bit_size = 1,
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
{
- .description = "tl3_ieh_dest.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
+ /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
{
- .description = "tl3_ieh_frag.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
+ /* class_tid: 5, , table: int_full_act_record.vf_ing */
{
- .description = "tl3_ieh_rthdr.en",
- .field_bit_size = 1,
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_hop.en",
- .field_bit_size = 1,
+ .description = "encap_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_1frag.en",
- .field_bit_size = 1,
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_df.en",
- .field_bit_size = 1,
+ .description = "rsvd1",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_l3err.en",
- .field_bit_size = 1,
+ .description = "rsvd0",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_l4type.en",
- .field_bit_size = 1,
+ .description = "decap_func",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_src.en",
- .field_bit_size = 1,
+ .description = "meter",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_dst.en",
+ .description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_flags.en",
- .field_bit_size = 1,
+ .description = "stats_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_seq.en",
- .field_bit_size = 1,
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}
},
{
- .description = "tl4_pa.en",
+ .description = "use_default",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_opt.en",
- .field_bit_size = 1,
+ .description = "mirror",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_tcpts.en",
+ .description = "cond_copy",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_err.en",
- .field_bit_size = 1,
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tuntype.en",
+ .description = "drop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tflags.en",
+ .description = "hit",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tids.en",
- .field_bit_size = 1,
+ .description = "type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 5, , table: ilt_tbl.vf_ing */
{
- .description = "tid.en",
- .field_bit_size = 1,
+ .description = "ilt_destination",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tctxts.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tctxt.en",
- .field_bit_size = 1,
+ .description = "fwd_op",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_FWD_OP_BYPASS_LKUP}
},
{
- .description = "tqos.en",
+ .description = "en_ilt_dest",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "terr.en",
+ .description = "en_bd_action",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_l2type.en",
+ .description = "en_bd_meta",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_dmac.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_smac.en",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 23,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: ilt_tbl.vfr_egr */
{
- .description = "l2_dt.en",
- .field_bit_size = 1,
+ .description = "ilt_destination",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_sa.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_nvt.en",
- .field_bit_size = 1,
+ .description = "fwd_op",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_FWD_OP_BYPASS_LKUP}
},
{
- .description = "l2_ovp.en",
+ .description = "en_ilt_dest",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovd.en",
+ .description = "en_bd_action",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "l2_ovv.en",
+ .description = "en_bd_meta",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovt.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivp.en",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 23,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
{
- .description = "l2_ivd.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "l2_ivv.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivt.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_etype.en",
- .field_bit_size = 1,
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: metadata_record.vfr_egr */
{
- .description = "l3_l3type.en",
- .field_bit_size = 1,
+ .description = "prof_meta_mask",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
+ /* class_tid: 5, , table: mod_record.vfr_egr */
{
- .description = "l3_sip.en",
+ .description = "metadata_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -4826,1078 +40666,1113 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
1}
},
{
- .description = "l3_sip_selcmp.en",
+ .description = "rem_ovlan",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- {
- .description = "l3_dip_selcmp.en",
+ .description = "rem_ivlan",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ttl.en",
+ .description = "rep_add_ivlan",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_prot.en",
+ .description = "rep_add_ovlan",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_fid.en",
+ .description = "ttl_update",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_qos.en",
+ .description = "tun_md_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_nonext.en",
+ .description = "reserved_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_esp.en",
+ .description = "l2_dmac_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_auth.en",
+ .description = "l2_smac_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_dest.en",
+ .description = "l3_sip_ipv6_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_frag.en",
+ .description = "l3_dip_ipv6_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_rthdr.en",
+ .description = "l3_sip_ipv4_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_hop.en",
+ .description = "l3_dip_ipv4_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_1frag.en",
+ .description = "l4_sport_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_df.en",
+ .description = "l4_dport_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_l3err.en",
- .field_bit_size = 1,
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_l4type.en",
- .field_bit_size = 1,
+ .description = "metadata_op",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_src.en",
- .field_bit_size = 1,
+ .description = "metadata_prof",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0 & 0xff}
},
{
- .description = "l4_dst.en",
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_flags.en",
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_seq.en",
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_dec",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_ack.en",
+ .description = "ttl_il3_dec",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_win.en",
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_rdir",
.field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ /* class_tid: 5, , table: int_full_act_record.vfr_egr */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_pa.en",
- .field_bit_size = 1,
+ .description = "encap_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_opt.en",
- .field_bit_size = 1,
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_tcpts.en",
- .field_bit_size = 1,
+ .description = "rsvd0",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_tsval.en",
- .field_bit_size = 1,
+ .description = "decap_func",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_txecr.en",
- .field_bit_size = 1,
+ .description = "meter",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_err.en",
+ .description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam.l3_l4 */
{
- .description = "wc_key_id",
- .field_bit_size = 6,
+ .description = "stats_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff,
+ ULP_THOR_SYM_LOOPBACK_PORT & 0xff}
},
{
- .description = "wc_search_en",
+ .description = "use_default",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_type",
- .field_bit_size = 2,
+ .description = "mirror",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 6,
+ .description = "cond_copy",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_search_en",
+ .description = "drop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "pl_byp_lkup_en",
+ .description = "hit",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam_cache.l3_l4_wr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ 1}
},
+ /* class_tid: 5, , table: l2_cntxt_tcam.vfr_ing0 */
{
- .description = "profile_tcam_index",
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 & 0xff}
+ },
+ {
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ },
+ {
+ .description = "l2_cntxt_id",
.field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
+ },
+ /* class_tid: 5, , table: fkb_select.vfr_em */
+ {
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 8,
+ .description = "parif.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "spif.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_key_id",
- .field_bit_size = 8,
+ .description = "svif.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "flow_sig_id",
- .field_bit_size = 64,
+ .description = "lcos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l3_l4 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "meta.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "loopback.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: int_full_act_record.0 */
{
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "encap_ptr",
- .field_bit_size = 16,
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd1",
- .field_bit_size = 16,
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd0",
- .field_bit_size = 8,
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "decap_func",
- .field_bit_size = 5,
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meter",
- .field_bit_size = 10,
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_op",
+ .description = "tl2_ovt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_ptr",
- .field_bit_size = 16,
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 11,
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "use_default",
+ .description = "tl2_ivv.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mirror",
- .field_bit_size = 4,
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "cond_copy",
+ .description = "tl2_etype.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drop",
+ .description = "tl3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "hit",
+ .description = "tl3_sip_selcmp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "type",
- .field_bit_size = 3,
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: port_table.wr_0 */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drv_func.mac",
- .field_bit_size = 48,
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drv_func.parent.mac",
- .field_bit_size = 48,
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "phy_port",
- .field_bit_size = 8,
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "default_arec_ptr",
- .field_bit_size = 16,
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_tcam_index",
- .field_bit_size = 10,
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: int_full_act_record.egr_0 */
{
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "encap_ptr",
- .field_bit_size = 16,
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd1",
- .field_bit_size = 16,
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd0",
- .field_bit_size = 8,
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "decap_func",
- .field_bit_size = 5,
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meter",
- .field_bit_size = 10,
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_op",
+ .description = "tuntype.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_ptr",
- .field_bit_size = 16,
+ .description = "tflags.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 11,
+ .description = "tids.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "use_default",
+ .description = "tid.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mirror",
- .field_bit_size = 4,
+ .description = "tctxts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "cond_copy",
+ .description = "tctxt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
+ .description = "tqos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drop",
+ .description = "terr.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "hit",
+ .description = "l2_l2type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "type",
- .field_bit_size = 3,
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: int_full_act_record.loopback */
{
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "encap_ptr",
- .field_bit_size = 16,
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd1",
- .field_bit_size = 16,
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd0",
- .field_bit_size = 8,
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "decap_func",
- .field_bit_size = 5,
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meter",
- .field_bit_size = 10,
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_op",
+ .description = "l3_sip_selcmp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_ptr",
- .field_bit_size = 16,
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 11,
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff,
- ULP_THOR_SYM_LOOPBACK_PORT & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "use_default",
+ .description = "l3_ttl.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mirror",
- .field_bit_size = 4,
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "cond_copy",
+ .description = "l3_fid.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drop",
+ .description = "l3_ieh_nonext.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "hit",
+ .description = "l3_ieh_esp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "type",
- .field_bit_size = 3,
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: int_full_act_record.vf_ing */
{
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "encap_ptr",
- .field_bit_size = 16,
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd1",
- .field_bit_size = 16,
+ .description = "l3_df.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd0",
- .field_bit_size = 8,
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "decap_func",
- .field_bit_size = 5,
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meter",
- .field_bit_size = 10,
+ .description = "l4_src.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_op",
+ .description = "l4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_ptr",
- .field_bit_size = 16,
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 11,
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "use_default",
+ .description = "l4_ack.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mirror",
- .field_bit_size = 4,
+ .description = "l4_win.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "cond_copy",
+ .description = "l4_pa.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drop",
+ .description = "l4_tcpts.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "hit",
+ .description = "l4_tsval.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "type",
- .field_bit_size = 3,
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: vtag_encap_record.vfr_egr0 */
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "l4_err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: profile_tcam.vfr_ing0 */
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "wc_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l2_en",
+ .description = "wc_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
- },
- {
- .description = "rsrvd",
- .field_bit_size = 1,
+ .description = "em_key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "em_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 & 0xff}
},
{
- .description = "vtag_tpid",
- .field_bit_size = 16,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- 0x81,
- 0x00}
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 & 0xff}
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "em_search_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ 1}
},
{
- .description = "vtag_de",
+ .description = "pl_byp_lkup_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- {
- .description = "vtag_pcp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
- },
- /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
+ /* class_tid: 5, , table: int_full_act_record.vfr_ing0 */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -5908,10 +41783,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "encap_ptr",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "mod_rec_ptr",
@@ -5959,10 +41831,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "vnic_or_vport",
.field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff,
- ULP_THOR_SYM_LOOPBACK_PORT & 0xff}
+ (BNXT_ULP_CF_IDX_VF_FUNC_VNIC >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_VNIC & 0xff}
},
{
.description = "use_default",
@@ -6007,6 +41879,50 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
+ },
+ /* class_tid: 5, , table: em.vfr.0 */
+ {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
};
@@ -6053,6 +41969,203 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 29
},
+ /* class_tid: 1, , table: profile_tcam_cache.ipv6_rd */
+ {
+ .description = "em_key_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_KEY_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 50
+ },
+ {
+ .description = "em_profile_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 42
+ },
+ {
+ .description = "flow_sig_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .ident_bit_size = 64,
+ .ident_bit_pos = 74
+ },
+ {
+ .description = "profile_tcam_index",
+ .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
+ },
+ /* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */
+ {
+ .description = "em_profile_id",
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_EM_PROF,
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 23
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.rd */
+ {
+ .description = "flow_sig_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .ident_bit_size = 64,
+ .ident_bit_pos = 74
+ },
+ {
+ .description = "profile_tcam_index",
+ .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
+ },
+ /* class_tid: 2, , table: port_table.rd */
+ {
+ .description = "default_arec_ptr",
+ .regfile_idx = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
+ .ident_bit_size = 16,
+ .ident_bit_pos = 136
+ },
+ {
+ .description = "drv_func.parent.mac",
+ .regfile_idx = BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC,
+ .ident_bit_size = 48,
+ .ident_bit_pos = 80
+ },
+ {
+ .description = "phy_port",
+ .regfile_idx = BNXT_ULP_RF_IDX_PHY_PORT,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 128
+ },
+ /* class_tid: 2, , table: tunnel_cache.rd */
+ {
+ .description = "l2_cntxt_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 42
+ },
+ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
+ {
+ .description = "l2_cntxt_id",
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 29
+ },
+ /* class_tid: 2, , table: mac_addr_cache.rd */
+ {
+ .description = "l2_cntxt_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 42
+ },
+ /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
+ {
+ .description = "em_profile_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 42
+ },
+ {
+ .description = "flow_sig_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .ident_bit_size = 64,
+ .ident_bit_pos = 74
+ },
+ {
+ .description = "profile_tcam_index",
+ .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ {
+ .description = "l2_cntxt_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 42
+ },
+ /* class_tid: 3, , table: mac_addr_cache.rd */
+ {
+ .description = "l2_cntxt_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 42
+ },
+ /* class_tid: 3, , table: port_table.egr.rd */
+ {
+ .description = "default_arec_ptr",
+ .regfile_idx = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
+ .ident_bit_size = 16,
+ .ident_bit_pos = 136
+ },
+ {
+ .description = "drv_func.parent.mac",
+ .regfile_idx = BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC,
+ .ident_bit_size = 48,
+ .ident_bit_pos = 80
+ },
+ {
+ .description = "phy_port",
+ .regfile_idx = BNXT_ULP_RF_IDX_PHY_PORT,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 128
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam.0 */
+ {
+ .description = "l2_cntxt_id",
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 29
+ },
+ /* class_tid: 3, , table: profile_tcam_cache.ipv6_rd */
+ {
+ .description = "em_key_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_KEY_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 50
+ },
+ {
+ .description = "em_profile_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 42
+ },
+ {
+ .description = "flow_sig_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .ident_bit_size = 64,
+ .ident_bit_pos = 74
+ },
+ {
+ .description = "profile_tcam_index",
+ .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
+ },
+ /* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */
+ {
+ .description = "em_profile_id",
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_EM_PROF,
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 23
+ },
+ /* class_tid: 3, , table: profile_tcam_cache.rd */
+ {
+ .description = "flow_sig_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .ident_bit_size = 64,
+ .ident_bit_pos = 74
+ },
+ {
+ .description = "profile_tcam_index",
+ .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
+ },
/* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
.description = "l2_cntxt_id",
@@ -6070,5 +42183,21 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 29
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
+ {
+ .description = "l2_cntxt_id",
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 29
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_wr_vfr */
+ {
+ .description = "rid",
+ .regfile_idx = BNXT_ULP_RF_IDX_RID,
+ .ident_bit_size = 32,
+ .ident_bit_pos = 0
}
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
index 7203dcf1fb..2870a0615a 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Fri May 28 16:46:46 2021 */
+/* date: Wed Jun 30 14:36:16 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -1488,7 +1488,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 47,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE,
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index bcc089b3e1..234f7ea2fa 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -2212,6 +2212,7 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
int32_t trc;
int32_t rc = 0;
int32_t pad = 0;
+ enum bnxt_ulp_byte_order key_order, res_order;
tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session);
rc = bnxt_ulp_cntxt_mem_type_get(parms->ulp_ctx, &mtype);
@@ -2226,11 +2227,12 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
+ key_order = dparms->em_byte_order;
+ res_order = dparms->em_byte_order;
+
/* Initialize the key/result blobs */
- if (!ulp_blob_init(&key, tbl->blob_key_bit_size,
- dparms->key_byte_order) ||
- !ulp_blob_init(&data, tbl->result_bit_size,
- dparms->result_byte_order)) {
+ if (!ulp_blob_init(&key, tbl->blob_key_bit_size, key_order) ||
+ !ulp_blob_init(&data, tbl->result_bit_size, res_order)) {
BNXT_TF_DBG(ERR, "blob inits failed.\n");
return -EINVAL;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index 4e9968e5fa..dce95de05c 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -826,12 +826,12 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
*/
ulp_rte_prsr_fld_mask(params, &idx, size,
&priority,
- &priority_mask,
+ (vlan_mask) ? &priority_mask : NULL,
ULP_PRSR_ACT_MASK_IGNORE);
ulp_rte_prsr_fld_mask(params, &idx, size,
&vlan_tag,
- &vlan_tag_mask,
+ (vlan_mask) ? &vlan_tag_mask : NULL,
ULP_PRSR_ACT_DEFAULT);
size = sizeof(((struct rte_flow_item_vlan *)NULL)->inner_type);
@@ -859,6 +859,10 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_ONE_VTAG, 1);
ULP_BITMAP_SET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_OO_VLAN);
+ if (vlan_mask && vlan_tag_mask)
+ ULP_COMP_FLD_IDX_WR(params,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID, 1);
+
} else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) &&
!ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_I_ETH) &&
outer_vtag_num == 1) {
@@ -870,6 +874,10 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_ONE_VTAG, 0);
ULP_BITMAP_SET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_OI_VLAN);
+ if (vlan_mask && vlan_tag_mask)
+ ULP_COMP_FLD_IDX_WR(params,
+ BNXT_ULP_CF_IDX_OI_VLAN_FB_VID, 1);
+
} else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) &&
ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_I_ETH) &&
!inner_vtag_num) {
@@ -881,6 +889,9 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_ONE_VTAG, 1);
ULP_BITMAP_SET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_IO_VLAN);
+ if (vlan_mask && vlan_tag_mask)
+ ULP_COMP_FLD_IDX_WR(params,
+ BNXT_ULP_CF_IDX_IO_VLAN_FB_VID, 1);
inner_flag = 1;
} else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) &&
ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_I_ETH) &&
@@ -893,6 +904,9 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_ONE_VTAG, 0);
ULP_BITMAP_SET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_II_VLAN);
+ if (vlan_mask && vlan_tag_mask)
+ ULP_COMP_FLD_IDX_WR(params,
+ BNXT_ULP_CF_IDX_II_VLAN_FB_VID, 1);
inner_flag = 1;
} else {
BNXT_TF_DBG(ERR, "Error Parsing:Vlan hdr found without eth\n");
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index e2a4b81cec..1683cd7ec4 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -213,6 +213,7 @@ struct bnxt_ulp_device_params {
enum bnxt_ulp_byte_order result_byte_order;
enum bnxt_ulp_byte_order encap_byte_order;
enum bnxt_ulp_byte_order wc_key_byte_order;
+ enum bnxt_ulp_byte_order em_byte_order;
uint8_t encap_byte_swap;
uint8_t num_phy_ports;
uint32_t mark_db_lfid_entries;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c
index fc4f435c97..686b80e456 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c
@@ -964,8 +964,11 @@ ulp_blob_append(struct ulp_blob *dst, struct ulp_blob *src,
ulp_bs_put_msb(dst->data, dst->write_idx,
ULP_BLOB_BYTE, bluff);
dst->write_idx += remaining;
+ src_offset += remaining;
}
+ src_buf += ULP_BITS_2_BYTE_NR(src_offset);
+
/* Push the byte aligned pieces */
for (k = 0; k < ULP_BITS_2_BYTE_NR(src_len); k++) {
ulp_bs_put_msb(dst->data, dst->write_idx, ULP_BLOB_BYTE,
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v4 10/13] net/bnxt: change log level to debug
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 " Venkat Duvvuru
` (8 preceding siblings ...)
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 09/13] net/bnxt: add flow templates " Venkat Duvvuru
@ 2021-09-20 7:42 ` Venkat Duvvuru
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 11/13] net/bnxt: dynamically allocate space for EM defrag function Venkat Duvvuru
` (3 subsequent siblings)
13 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-20 7:42 UTC (permalink / raw)
To: dev; +Cc: Farah Smith
From: Farah Smith <farah.smith@broadcom.com>
Adjust info message to debug level to prevent excessive
logging.
Signed-off-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/tf_core/tf_tbl_sram.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.c b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
index ea10afecb6..d7727f7a11 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl_sram.c
+++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
@@ -130,7 +130,7 @@ static int tf_tbl_sram_get_info(struct tf_tbl_sram_get_info_parms *parms)
if (slices)
parms->slice_size = tf_tbl_sram_slices_2_size[slices];
- TFP_DRV_LOG(INFO,
+ TFP_DRV_LOG(DEBUG,
"(%s) bank(%s) slice_size(%s)\n",
tf_tbl_type_2_str(parms->tbl_type),
tf_sram_bank_2_str(parms->bank_id),
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v4 11/13] net/bnxt: dynamically allocate space for EM defrag function
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 " Venkat Duvvuru
` (9 preceding siblings ...)
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 10/13] net/bnxt: change log level to debug Venkat Duvvuru
@ 2021-09-20 7:42 ` Venkat Duvvuru
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 12/13] net/bnxt: add SRAM manager shared session Venkat Duvvuru
` (2 subsequent siblings)
13 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-20 7:42 UTC (permalink / raw)
To: dev; +Cc: Randy Schacher
From: Randy Schacher <stuart.schacher@broadcom.com>
The dynamic pool allocation defrag function currently uses stack
allocation. To improve use of stack space, dynamically allocate
and deallocate memory for use to defragment the dynamic pool of
EM resources.
Signed-off-by: Randy Schacher <stuart.schacher@broadcom.com>
Reviewed-by: Peter Spreadborough <peter.spreadborough@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/tf_core/dpool.c | 38 +++++++++++++++++++++-----------
1 file changed, 25 insertions(+), 13 deletions(-)
diff --git a/drivers/net/bnxt/tf_core/dpool.c b/drivers/net/bnxt/tf_core/dpool.c
index 145efa486f..5c03f775a5 100644
--- a/drivers/net/bnxt/tf_core/dpool.c
+++ b/drivers/net/bnxt/tf_core/dpool.c
@@ -7,9 +7,6 @@
#include <stdbool.h>
#include <stdint.h>
#include <errno.h>
-
-#include <rte_malloc.h>
-
#include "tfp.h"
#include "dpool.h"
@@ -84,13 +81,13 @@ static int dpool_move(struct dpool *dpool,
return 0;
}
-
int dpool_defrag(struct dpool *dpool,
uint32_t entry_size,
uint8_t defrag)
{
struct dpool_free_list *free_list;
struct dpool_adj_list *adj_list;
+ struct tfp_calloc_parms parms;
uint32_t count;
uint32_t index;
uint32_t used;
@@ -103,15 +100,31 @@ int dpool_defrag(struct dpool *dpool,
uint32_t max_size = 0;
int rc;
- free_list = rte_zmalloc("dpool_free_list",
- sizeof(struct dpool_free_list), 0);
+ parms.nitems = 1;
+ parms.size = sizeof(struct dpool_free_list);
+ parms.alignment = 0;
+
+ rc = tfp_calloc(&parms);
+
+ if (rc)
+ return rc;
+
+ free_list = (struct dpool_free_list *)parms.mem_va;
if (free_list == NULL) {
TFP_DRV_LOG(ERR, "dpool free list allocation failed\n");
return -ENOMEM;
}
- adj_list = rte_zmalloc("dpool_adjacent_list",
- sizeof(struct dpool_adj_list), 0);
+ parms.nitems = 1;
+ parms.size = sizeof(struct dpool_adj_list);
+ parms.alignment = 0;
+
+ rc = tfp_calloc(&parms);
+
+ if (rc)
+ return rc;
+
+ adj_list = (struct dpool_adj_list *)parms.mem_va;
if (adj_list == NULL) {
TFP_DRV_LOG(ERR, "dpool adjacent list allocation failed\n");
return -ENOMEM;
@@ -239,8 +252,8 @@ int dpool_defrag(struct dpool *dpool,
free_list->entry[largest_free_index].index,
max_index);
if (rc) {
- rte_free(free_list);
- rte_free(adj_list);
+ tfp_free(free_list);
+ tfp_free(adj_list);
return rc;
}
} else {
@@ -249,12 +262,11 @@ int dpool_defrag(struct dpool *dpool,
}
done:
- rte_free(free_list);
- rte_free(adj_list);
+ tfp_free(free_list);
+ tfp_free(adj_list);
return largest_free_size;
}
-
uint32_t dpool_alloc(struct dpool *dpool,
uint32_t size,
uint8_t defrag)
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v4 12/13] net/bnxt: add SRAM manager shared session
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 " Venkat Duvvuru
` (10 preceding siblings ...)
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 11/13] net/bnxt: dynamically allocate space for EM defrag function Venkat Duvvuru
@ 2021-09-20 7:42 ` Venkat Duvvuru
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 13/13] net/bnxt: add enhancements to TF ULP Venkat Duvvuru
2021-09-21 4:50 ` [dpdk-dev] [PATCH v4 00/13] enhancements to host based flow table management Ajit Khaparde
13 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-20 7:42 UTC (permalink / raw)
To: dev; +Cc: Farah Smith
From: Farah Smith <farah.smith@broadcom.com>
Fix shared session support issues due to SRAM manager
additions. Shared session does not support slices within
RM blocks. Calculate resources required without slices
and determine base addresses using old methods for the
shared session.
Signed-off-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/tf_core/tf_em_internal.c | 5 +-
drivers/net/bnxt/tf_core/tf_rm.c | 134 +++++++++++++++++++---
drivers/net/bnxt/tf_core/tf_tbl_sram.c | 73 +++++++++---
3 files changed, 176 insertions(+), 36 deletions(-)
diff --git a/drivers/net/bnxt/tf_core/tf_em_internal.c b/drivers/net/bnxt/tf_core/tf_em_internal.c
index 2d57595f17..67ba011eae 100644
--- a/drivers/net/bnxt/tf_core/tf_em_internal.c
+++ b/drivers/net/bnxt/tf_core/tf_em_internal.c
@@ -326,8 +326,11 @@ tf_em_int_unbind(struct tf *tfp)
return rc;
if (!tf_session_is_shared_session(tfs)) {
- for (i = 0; i < TF_DIR_MAX; i++)
+ for (i = 0; i < TF_DIR_MAX; i++) {
+ if (tfs->em_pool[i] == NULL)
+ continue;
dpool_free_all(tfs->em_pool[i]);
+ }
}
rc = tf_session_get_db(tfp, TF_MODULE_TYPE_EM, &em_db_ptr);
diff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c
index 03c958a7d6..dd537aaece 100644
--- a/drivers/net/bnxt/tf_core/tf_rm.c
+++ b/drivers/net/bnxt/tf_core/tf_rm.c
@@ -18,6 +18,9 @@
#include "tfp.h"
#include "tf_msg.h"
+/* Logging defines */
+#define TF_RM_DEBUG 0
+
/**
* Generic RM Element data type that an RM DB is build upon.
*/
@@ -207,6 +210,45 @@ tf_rm_adjust_index(struct tf_rm_element *db,
return rc;
}
+/**
+ * Logs an array of found residual entries to the console.
+ *
+ * [in] dir
+ * Receive or transmit direction
+ *
+ * [in] module
+ * Type of Device Module
+ *
+ * [in] count
+ * Number of entries in the residual array
+ *
+ * [in] residuals
+ * Pointer to an array of residual entries. Array is index same as
+ * the DB in which this function is used. Each entry holds residual
+ * value for that entry.
+ */
+#if (TF_RM_DEBUG == 1)
+static void
+tf_rm_log_residuals(enum tf_dir dir,
+ enum tf_module_type module,
+ uint16_t count,
+ uint16_t *residuals)
+{
+ int i;
+
+ /* Walk the residual array and log the types that wasn't
+ * cleaned up to the console.
+ */
+ for (i = 0; i < count; i++) {
+ if (residuals[i] != 0)
+ TFP_DRV_LOG(INFO,
+ "%s, %s was not cleaned up, %d outstanding\n",
+ tf_dir_2_str(dir),
+ tf_module_subtype_2_str(module, i),
+ residuals[i]);
+ }
+}
+#endif /* TF_RM_DEBUG == 1 */
/**
* Performs a check of the passed in DB for any lingering elements. If
* a resource type was found to not have been cleaned up by the caller
@@ -322,6 +364,12 @@ tf_rm_check_residuals(struct tf_rm_new_db *rm_db,
*resv_size = found;
}
+#if (TF_RM_DEBUG == 1)
+ tf_rm_log_residuals(rm_db->dir,
+ rm_db->module,
+ rm_db->num_entries,
+ residuals);
+#endif
tfp_free((void *)residuals);
*resv = local_resv;
@@ -367,7 +415,8 @@ tf_rm_update_parent_reservations(struct tf *tfp,
struct tf_rm_element_cfg *cfg,
uint16_t *alloc_cnt,
uint16_t num_elements,
- uint16_t *req_cnt)
+ uint16_t *req_cnt,
+ bool shared_session)
{
int parent, child;
const char *type_str;
@@ -378,18 +427,28 @@ tf_rm_update_parent_reservations(struct tf *tfp,
/* If I am a parent */
if (cfg[parent].cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_PARENT) {
- /* start with my own count */
- RTE_ASSERT(cfg[parent].slices);
- combined_cnt =
- alloc_cnt[parent] / cfg[parent].slices;
+ uint8_t p_slices = 1;
+
+ /* Shared session doesn't support slices */
+ if (!shared_session)
+ p_slices = cfg[parent].slices;
+
+ RTE_ASSERT(p_slices);
- if (alloc_cnt[parent] % cfg[parent].slices)
+ combined_cnt = alloc_cnt[parent] / p_slices;
+
+ if (alloc_cnt[parent] % p_slices)
combined_cnt++;
if (alloc_cnt[parent]) {
dev->ops->tf_dev_get_resource_str(tfp,
cfg[parent].hcapi_type,
&type_str);
+#if (TF_RM_DEBUG == 1)
+ printf("%s:%s cnt(%d) slices(%d)\n",
+ type_str, tf_tbl_type_2_str(parent),
+ alloc_cnt[parent], p_slices);
+#endif /* (TF_RM_DEBUG == 1) */
}
/* Search again through all the elements */
@@ -399,20 +458,31 @@ tf_rm_update_parent_reservations(struct tf *tfp,
TF_RM_ELEM_CFG_HCAPI_BA_CHILD &&
cfg[child].parent_subtype == parent &&
alloc_cnt[child]) {
+ uint8_t c_slices = 1;
uint16_t cnt = 0;
- RTE_ASSERT(cfg[child].slices);
+
+ if (!shared_session)
+ c_slices = cfg[child].slices;
+
+ RTE_ASSERT(c_slices);
dev->ops->tf_dev_get_resource_str(tfp,
cfg[child].hcapi_type,
&type_str);
+#if (TF_RM_DEBUG == 1)
+ printf("%s:%s cnt(%d) slices(%d)\n",
+ type_str,
+ tf_tbl_type_2_str(child),
+ alloc_cnt[child],
+ c_slices);
+#endif /* (TF_RM_DEBUG == 1) */
/* Increment the parents combined count
* with each child's count adjusted for
- * number of slices per RM allocated item.
+ * number of slices per RM alloc item.
*/
- cnt =
- alloc_cnt[child] / cfg[child].slices;
+ cnt = alloc_cnt[child] / c_slices;
- if (alloc_cnt[child] % cfg[child].slices)
+ if (alloc_cnt[child] % c_slices)
cnt++;
combined_cnt += cnt;
@@ -422,6 +492,10 @@ tf_rm_update_parent_reservations(struct tf *tfp,
}
/* Save the parent count to be requested */
req_cnt[parent] = combined_cnt;
+#if (TF_RM_DEBUG == 1)
+ printf("%s calculated total:%d\n\n",
+ type_str, req_cnt[parent]);
+#endif /* (TF_RM_DEBUG == 1) */
}
}
return 0;
@@ -444,6 +518,7 @@ tf_rm_create_db(struct tf *tfp,
struct tf_rm_new_db *rm_db;
struct tf_rm_element *db;
uint32_t pool_size;
+ bool shared_session = 0;
TF_CHECK_PARMS2(tfp, parms);
@@ -460,7 +535,6 @@ tf_rm_create_db(struct tf *tfp,
/* Need device max number of elements for the RM QCAPS */
rc = dev->ops->tf_dev_get_max_types(tfp, &max_types);
-
/* Allocate memory for RM QCAPS request */
cparms.nitems = max_types;
cparms.size = sizeof(struct tf_rm_resc_req_entry);
@@ -496,12 +570,15 @@ tf_rm_create_db(struct tf *tfp,
tfp_memcpy(req_cnt, parms->alloc_cnt,
parms->num_elements * sizeof(uint16_t));
+ shared_session = tf_session_is_shared_session(tfs);
+
/* Update the req_cnt based upon the element configuration
*/
tf_rm_update_parent_reservations(tfp, dev, parms->cfg,
parms->alloc_cnt,
parms->num_elements,
- req_cnt);
+ req_cnt,
+ shared_session);
/* Process capabilities against DB requirements. However, as a
* DB can hold elements that are not HCAPI we can reduce the
@@ -517,6 +594,12 @@ tf_rm_create_db(struct tf *tfp,
&hcapi_items);
if (hcapi_items == 0) {
+#if (TF_RM_DEBUG == 1)
+ TFP_DRV_LOG(INFO,
+ "%s: module: %s Empty RM DB create request\n",
+ tf_dir_2_str(parms->dir),
+ tf_module_2_str(parms->module));
+#endif
parms->rm_db = NULL;
return -ENOMEM;
}
@@ -565,11 +648,11 @@ tf_rm_create_db(struct tf *tfp,
hcapi_type,
&type_str);
TFP_DRV_LOG(ERR,
- "Failure, %s:%d:%s req:%d avail:%d\n",
- tf_dir_2_str(parms->dir),
- hcapi_type, type_str,
- req_cnt[i],
- query[hcapi_type].max);
+ "Failure, %s:%d:%s req:%d avail:%d\n",
+ tf_dir_2_str(parms->dir),
+ hcapi_type, type_str,
+ req_cnt[i],
+ query[hcapi_type].max);
return -EINVAL;
}
}
@@ -689,6 +772,13 @@ tf_rm_create_db(struct tf *tfp,
rm_db->module = parms->module;
*parms->rm_db = (void *)rm_db;
+#if (TF_RM_DEBUG == 1)
+
+ printf("%s: module:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_module_2_str(parms->module));
+#endif /* (TF_RM_DEBUG == 1) */
+
tfp_free((void *)req);
tfp_free((void *)resv);
tfp_free((void *)req_cnt);
@@ -922,6 +1012,13 @@ tf_rm_create_db_no_reservation(struct tf *tfp,
rm_db->module = parms->module;
*parms->rm_db = (void *)rm_db;
+#if (TF_RM_DEBUG == 1)
+
+ printf("%s: module:%s\n",
+ tf_dir_2_str(parms->dir),
+ tf_module_2_str(parms->module));
+#endif /* (TF_RM_DEBUG == 1) */
+
tfp_free((void *)req);
tfp_free((void *)resv);
tfp_free((void *)req_cnt);
@@ -1185,7 +1282,6 @@ tf_rm_is_allocated(struct tf_rm_is_allocated_parms *parms)
cfg_type = rm_db->db[parms->subtype].cfg_type;
-
/* Bail out if not controlled by RM */
if (cfg_type != TF_RM_ELEM_CFG_HCAPI_BA &&
cfg_type != TF_RM_ELEM_CFG_HCAPI_BA_PARENT &&
diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.c b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
index d7727f7a11..167078a8c6 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl_sram.c
+++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
@@ -21,6 +21,10 @@
#define DBG_SRAM 0
+#define TF_TBL_PTR_TO_RM(new_idx, idx, base, shift) { \
+ *(new_idx) = (((idx) >> (shift)) - (base)); \
+}
+
/**
* tf_sram_tbl_get_info_parms parameter definition
*/
@@ -394,6 +398,7 @@ tf_tbl_sram_set(struct tf *tfp,
{
int rc;
bool allocated = 0;
+ int rallocated = 0;
uint16_t hcapi_type;
struct tf_rm_get_hcapi_parms hparms = { 0 };
struct tf_session *tfs;
@@ -402,7 +407,9 @@ tf_tbl_sram_set(struct tf *tfp,
void *tbl_db_ptr = NULL;
struct tf_tbl_sram_get_info_parms iparms = { 0 };
struct tf_sram_mgr_is_allocated_parms aparms = { 0 };
+ struct tf_rm_is_allocated_parms raparms = { 0 };
void *sram_handle = NULL;
+ uint16_t base = 0, shift = 0;
TF_CHECK_PARMS3(tfp, parms, parms->data);
@@ -442,23 +449,57 @@ tf_tbl_sram_set(struct tf *tfp,
return rc;
}
- aparms.sram_offset = parms->idx;
- aparms.slice_size = iparms.slice_size;
- aparms.bank_id = iparms.bank_id;
- aparms.dir = parms->dir;
- aparms.is_allocated = &allocated;
- rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
- if (rc || !allocated) {
- TFP_DRV_LOG(ERR,
- "%s: Entry not allocated:%s idx(%d):(%s)\n",
- tf_dir_2_str(parms->dir),
- tf_tbl_type_2_str(parms->type),
- parms->idx,
- strerror(-rc));
- rc = -ENOMEM;
- return rc;
+ if (tf_session_is_shared_session(tfs)) {
+ /* Only get table info if required for the device */
+ if (dev->ops->tf_dev_get_tbl_info) {
+ rc = dev->ops->tf_dev_get_tbl_info(tfp,
+ tbl_db->tbl_db[parms->dir],
+ parms->type,
+ &base,
+ &shift);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: Failed to get table info:%d\n",
+ tf_dir_2_str(parms->dir),
+ parms->type);
+ return rc;
+ }
+ }
+ TF_TBL_PTR_TO_RM(&raparms.index, parms->idx, base, shift);
+
+ raparms.rm_db = tbl_db->tbl_db[parms->dir];
+ raparms.subtype = parms->type;
+ raparms.allocated = &rallocated;
+ rc = tf_rm_is_allocated(&raparms);
+ if (rc)
+ return rc;
+
+ if (rallocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
+ TFP_DRV_LOG(ERR,
+ "%s, Invalid or not allocated index, type:%s, idx:%d\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->idx);
+ return -EINVAL;
+ }
+ } else {
+ aparms.sram_offset = parms->idx;
+ aparms.slice_size = iparms.slice_size;
+ aparms.bank_id = iparms.bank_id;
+ aparms.dir = parms->dir;
+ aparms.is_allocated = &allocated;
+ rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
+ if (rc || !allocated) {
+ TFP_DRV_LOG(ERR,
+ "%s: Entry not allocated:%s idx(%d):(%s)\n",
+ tf_dir_2_str(parms->dir),
+ tf_tbl_type_2_str(parms->type),
+ parms->idx,
+ strerror(-rc));
+ rc = -ENOMEM;
+ return rc;
+ }
}
-
/* Set the entry */
hparms.rm_db = tbl_db->tbl_db[parms->dir];
hparms.subtype = parms->type;
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* [dpdk-dev] [PATCH v4 13/13] net/bnxt: add enhancements to TF ULP
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 " Venkat Duvvuru
` (11 preceding siblings ...)
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 12/13] net/bnxt: add SRAM manager shared session Venkat Duvvuru
@ 2021-09-20 7:42 ` Venkat Duvvuru
2021-09-21 4:50 ` [dpdk-dev] [PATCH v4 00/13] enhancements to host based flow table management Ajit Khaparde
13 siblings, 0 replies; 83+ messages in thread
From: Venkat Duvvuru @ 2021-09-20 7:42 UTC (permalink / raw)
To: dev; +Cc: Kishore Padmanabha, Mike Baucom, Venkat Duvvuru
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
1. Added support to specify l4 port masks in the template. Also enabled
source mac in the wild card key for ingress flows.
2. Added support to enable offload for ipv6 traffic within the vxlan
tunnel connection.
3. The flow counters is reduced from 7168 to 6912 for Whitney.
The stats operation is updated to reflect counts for packets
at egress from CFA instead of ingress to CFA
4. The miss path for the l2 context table is updated with correct
parif and default action handler to handle the miss path for
egress flows.
5. This support enables allocation of encapsulation, modification and
action records dynamically based on a given flow actions.
6. Reduce the l2context resource requests during open_session. Move the
SMAC from the L2Context to the EM/WM
7. Remap the parif in the bd action in order to eliminate incorrect
replication of broadcast packets. The layer 4 source port mask
was incorrectly updated in the outer layer 4 source port mask
instead of inner layer 4. Add the l3 proto to egress rules, switch
to using computed fields for l4 ports, add internal smac to f1/f2
flows, add l3 proto to ingress ipv6 flows
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Mike Baucom <michael.baucom@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
---
doc/guides/rel_notes/release_21_11.rst | 6 +
drivers/net/bnxt/tf_core/tf_tbl_sram.c | 7 -
.../generic_templates/ulp_template_db_class.c | 8102 ++++++++++++-----
.../generic_templates/ulp_template_db_enum.h | 675 +-
.../generic_templates/ulp_template_db_field.h | 195 +-
.../generic_templates/ulp_template_db_tbl.c | 2136 ++++-
.../ulp_template_db_thor_act.c | 996 +-
.../ulp_template_db_thor_class.c | 7495 ++++++++-------
.../ulp_template_db_wh_plus_class.c | 14 +-
drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c | 4 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 135 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 175 +-
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 10 +
drivers/net/bnxt/tf_ulp/ulp_utils.c | 3 +-
14 files changed, 13544 insertions(+), 6409 deletions(-)
diff --git a/doc/guides/rel_notes/release_21_11.rst b/doc/guides/rel_notes/release_21_11.rst
index 43d367bcad..d82cd8c279 100644
--- a/doc/guides/rel_notes/release_21_11.rst
+++ b/doc/guides/rel_notes/release_21_11.rst
@@ -82,6 +82,12 @@ New Features
* Added PDCP short MAC-I support.
+* **Updated Broadcom bnxt PMD.**
+
+ * Added flow offload support for Thor.
+ * Implement support for tunnel offload.
+ * Updated HWRM API to version 1.10.2.44
+
* **Added multi-process support for testpmd.**
Added command-line options to specify total number of processes and
diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.c b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
index 167078a8c6..636811bc2d 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl_sram.c
+++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
@@ -134,11 +134,6 @@ static int tf_tbl_sram_get_info(struct tf_tbl_sram_get_info_parms *parms)
if (slices)
parms->slice_size = tf_tbl_sram_slices_2_size[slices];
- TFP_DRV_LOG(DEBUG,
- "(%s) bank(%s) slice_size(%s)\n",
- tf_tbl_type_2_str(parms->tbl_type),
- tf_sram_bank_2_str(parms->bank_id),
- tf_sram_slice_2_str(parms->slice_size));
return rc;
}
@@ -373,7 +368,6 @@ tf_tbl_sram_free(struct tf *tfp __rte_unused,
return rc;
}
-
#if (DBG_SRAM == 1)
{
struct tf_sram_mgr_dump_parms dparms;
@@ -411,7 +405,6 @@ tf_tbl_sram_set(struct tf *tfp,
void *sram_handle = NULL;
uint16_t base = 0, shift = 0;
-
TF_CHECK_PARMS3(tfp, parms, parms->data);
/* Retrieve the session information */
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
index f74687acfa..ad3866243d 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 20 11:56:39 2021 */
+/* date: Fri Aug 6 11:15:47 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -362,508 +362,652 @@ uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {
[BNXT_ULP_CLASS_HID_315d] = 344,
[BNXT_ULP_CLASS_HID_3612] = 345,
[BNXT_ULP_CLASS_HID_66da] = 346,
- [BNXT_ULP_CLASS_HID_6165] = 347,
- [BNXT_ULP_CLASS_HID_2aa1] = 348,
- [BNXT_ULP_CLASS_HID_09cd] = 349,
- [BNXT_ULP_CLASS_HID_3845] = 350,
- [BNXT_ULP_CLASS_HID_11e9] = 351,
- [BNXT_ULP_CLASS_HID_4361] = 352,
- [BNXT_ULP_CLASS_HID_218d] = 353,
- [BNXT_ULP_CLASS_HID_5105] = 354,
- [BNXT_ULP_CLASS_HID_0c89] = 355,
- [BNXT_ULP_CLASS_HID_3e81] = 356,
- [BNXT_ULP_CLASS_HID_1dad] = 357,
- [BNXT_ULP_CLASS_HID_4ca5] = 358,
- [BNXT_ULP_CLASS_HID_25c9] = 359,
- [BNXT_ULP_CLASS_HID_57c1] = 360,
- [BNXT_ULP_CLASS_HID_33ed] = 361,
- [BNXT_ULP_CLASS_HID_65e5] = 362,
- [BNXT_ULP_CLASS_HID_6dd9] = 363,
- [BNXT_ULP_CLASS_HID_261d] = 364,
- [BNXT_ULP_CLASS_HID_0571] = 365,
- [BNXT_ULP_CLASS_HID_34f9] = 366,
- [BNXT_ULP_CLASS_HID_1d55] = 367,
- [BNXT_ULP_CLASS_HID_4fdd] = 368,
- [BNXT_ULP_CLASS_HID_2d31] = 369,
- [BNXT_ULP_CLASS_HID_5db9] = 370,
- [BNXT_ULP_CLASS_HID_0035] = 371,
- [BNXT_ULP_CLASS_HID_323d] = 372,
- [BNXT_ULP_CLASS_HID_1111] = 373,
- [BNXT_ULP_CLASS_HID_4019] = 374,
- [BNXT_ULP_CLASS_HID_2975] = 375,
- [BNXT_ULP_CLASS_HID_5b7d] = 376,
- [BNXT_ULP_CLASS_HID_3f51] = 377,
- [BNXT_ULP_CLASS_HID_6959] = 378,
- [BNXT_ULP_CLASS_HID_0e85] = 379,
- [BNXT_ULP_CLASS_HID_380d] = 380,
- [BNXT_ULP_CLASS_HID_1f21] = 381,
- [BNXT_ULP_CLASS_HID_4ea9] = 382,
- [BNXT_ULP_CLASS_HID_1705] = 383,
- [BNXT_ULP_CLASS_HID_418d] = 384,
- [BNXT_ULP_CLASS_HID_2721] = 385,
- [BNXT_ULP_CLASS_HID_57a9] = 386,
- [BNXT_ULP_CLASS_HID_1a25] = 387,
- [BNXT_ULP_CLASS_HID_342d] = 388,
- [BNXT_ULP_CLASS_HID_2b01] = 389,
- [BNXT_ULP_CLASS_HID_5a09] = 390,
- [BNXT_ULP_CLASS_HID_2325] = 391,
- [BNXT_ULP_CLASS_HID_5d2d] = 392,
- [BNXT_ULP_CLASS_HID_3101] = 393,
- [BNXT_ULP_CLASS_HID_6309] = 394,
- [BNXT_ULP_CLASS_HID_0bad] = 395,
- [BNXT_ULP_CLASS_HID_2535] = 396,
- [BNXT_ULP_CLASS_HID_1869] = 397,
- [BNXT_ULP_CLASS_HID_4bf1] = 398,
- [BNXT_ULP_CLASS_HID_136d] = 399,
- [BNXT_ULP_CLASS_HID_43f5] = 400,
- [BNXT_ULP_CLASS_HID_2129] = 401,
- [BNXT_ULP_CLASS_HID_53b1] = 402,
- [BNXT_ULP_CLASS_HID_072d] = 403,
- [BNXT_ULP_CLASS_HID_3135] = 404,
- [BNXT_ULP_CLASS_HID_1429] = 405,
- [BNXT_ULP_CLASS_HID_4731] = 406,
- [BNXT_ULP_CLASS_HID_2f6d] = 407,
- [BNXT_ULP_CLASS_HID_5f75] = 408,
- [BNXT_ULP_CLASS_HID_3d69] = 409,
- [BNXT_ULP_CLASS_HID_6f71] = 410,
- [BNXT_ULP_CLASS_HID_0dbd] = 411,
- [BNXT_ULP_CLASS_HID_3f25] = 412,
- [BNXT_ULP_CLASS_HID_1239] = 413,
- [BNXT_ULP_CLASS_HID_4da1] = 414,
- [BNXT_ULP_CLASS_HID_153d] = 415,
- [BNXT_ULP_CLASS_HID_45a5] = 416,
- [BNXT_ULP_CLASS_HID_3bb9] = 417,
- [BNXT_ULP_CLASS_HID_55a1] = 418,
- [BNXT_ULP_CLASS_HID_193d] = 419,
- [BNXT_ULP_CLASS_HID_4b25] = 420,
- [BNXT_ULP_CLASS_HID_2e39] = 421,
- [BNXT_ULP_CLASS_HID_5921] = 422,
- [BNXT_ULP_CLASS_HID_213d] = 423,
- [BNXT_ULP_CLASS_HID_5125] = 424,
- [BNXT_ULP_CLASS_HID_3739] = 425,
- [BNXT_ULP_CLASS_HID_093d] = 426,
- [BNXT_ULP_CLASS_HID_684d] = 427,
- [BNXT_ULP_CLASS_HID_2389] = 428,
- [BNXT_ULP_CLASS_HID_00e5] = 429,
- [BNXT_ULP_CLASS_HID_316d] = 430,
- [BNXT_ULP_CLASS_HID_18c1] = 431,
- [BNXT_ULP_CLASS_HID_4a49] = 432,
- [BNXT_ULP_CLASS_HID_28a5] = 433,
- [BNXT_ULP_CLASS_HID_582d] = 434,
- [BNXT_ULP_CLASS_HID_05a1] = 435,
- [BNXT_ULP_CLASS_HID_37a9] = 436,
- [BNXT_ULP_CLASS_HID_1485] = 437,
- [BNXT_ULP_CLASS_HID_458d] = 438,
- [BNXT_ULP_CLASS_HID_2ce1] = 439,
- [BNXT_ULP_CLASS_HID_5ee9] = 440,
- [BNXT_ULP_CLASS_HID_3ac5] = 441,
- [BNXT_ULP_CLASS_HID_6ccd] = 442,
- [BNXT_ULP_CLASS_HID_0b11] = 443,
- [BNXT_ULP_CLASS_HID_3d99] = 444,
- [BNXT_ULP_CLASS_HID_1ab5] = 445,
- [BNXT_ULP_CLASS_HID_4b3d] = 446,
- [BNXT_ULP_CLASS_HID_1291] = 447,
- [BNXT_ULP_CLASS_HID_4419] = 448,
- [BNXT_ULP_CLASS_HID_22b5] = 449,
- [BNXT_ULP_CLASS_HID_523d] = 450,
- [BNXT_ULP_CLASS_HID_1fb1] = 451,
- [BNXT_ULP_CLASS_HID_31b9] = 452,
- [BNXT_ULP_CLASS_HID_2e95] = 453,
- [BNXT_ULP_CLASS_HID_5f9d] = 454,
- [BNXT_ULP_CLASS_HID_26b1] = 455,
- [BNXT_ULP_CLASS_HID_58b9] = 456,
- [BNXT_ULP_CLASS_HID_3495] = 457,
- [BNXT_ULP_CLASS_HID_669d] = 458,
- [BNXT_ULP_CLASS_HID_0e39] = 459,
- [BNXT_ULP_CLASS_HID_20a1] = 460,
- [BNXT_ULP_CLASS_HID_1dfd] = 461,
- [BNXT_ULP_CLASS_HID_4e65] = 462,
- [BNXT_ULP_CLASS_HID_16f9] = 463,
- [BNXT_ULP_CLASS_HID_4661] = 464,
- [BNXT_ULP_CLASS_HID_24bd] = 465,
- [BNXT_ULP_CLASS_HID_5625] = 466,
- [BNXT_ULP_CLASS_HID_02b9] = 467,
- [BNXT_ULP_CLASS_HID_34a1] = 468,
- [BNXT_ULP_CLASS_HID_11bd] = 469,
- [BNXT_ULP_CLASS_HID_42a5] = 470,
- [BNXT_ULP_CLASS_HID_2af9] = 471,
- [BNXT_ULP_CLASS_HID_5ae1] = 472,
- [BNXT_ULP_CLASS_HID_38fd] = 473,
- [BNXT_ULP_CLASS_HID_6ae5] = 474,
- [BNXT_ULP_CLASS_HID_0829] = 475,
- [BNXT_ULP_CLASS_HID_3ab1] = 476,
- [BNXT_ULP_CLASS_HID_17ad] = 477,
- [BNXT_ULP_CLASS_HID_4835] = 478,
- [BNXT_ULP_CLASS_HID_10a9] = 479,
- [BNXT_ULP_CLASS_HID_4031] = 480,
- [BNXT_ULP_CLASS_HID_3e2d] = 481,
- [BNXT_ULP_CLASS_HID_5035] = 482,
- [BNXT_ULP_CLASS_HID_1ca9] = 483,
- [BNXT_ULP_CLASS_HID_4eb1] = 484,
- [BNXT_ULP_CLASS_HID_2bad] = 485,
- [BNXT_ULP_CLASS_HID_5cb5] = 486,
- [BNXT_ULP_CLASS_HID_24a9] = 487,
- [BNXT_ULP_CLASS_HID_54b1] = 488,
- [BNXT_ULP_CLASS_HID_32ad] = 489,
- [BNXT_ULP_CLASS_HID_0ca9] = 490,
- [BNXT_ULP_CLASS_HID_7f35] = 491,
- [BNXT_ULP_CLASS_HID_34f1] = 492,
- [BNXT_ULP_CLASS_HID_179d] = 493,
- [BNXT_ULP_CLASS_HID_2615] = 494,
- [BNXT_ULP_CLASS_HID_0fb9] = 495,
- [BNXT_ULP_CLASS_HID_5d31] = 496,
- [BNXT_ULP_CLASS_HID_3fdd] = 497,
- [BNXT_ULP_CLASS_HID_4f55] = 498,
- [BNXT_ULP_CLASS_HID_12d9] = 499,
- [BNXT_ULP_CLASS_HID_20d1] = 500,
- [BNXT_ULP_CLASS_HID_03fd] = 501,
- [BNXT_ULP_CLASS_HID_52f5] = 502,
- [BNXT_ULP_CLASS_HID_3b99] = 503,
- [BNXT_ULP_CLASS_HID_4991] = 504,
- [BNXT_ULP_CLASS_HID_2dbd] = 505,
- [BNXT_ULP_CLASS_HID_7bb5] = 506,
- [BNXT_ULP_CLASS_HID_34c6] = 507,
- [BNXT_ULP_CLASS_HID_0c22] = 508,
- [BNXT_ULP_CLASS_HID_1cbe] = 509,
- [BNXT_ULP_CLASS_HID_179a] = 510,
- [BNXT_ULP_CLASS_HID_59be] = 511,
- [BNXT_ULP_CLASS_HID_515a] = 512,
- [BNXT_ULP_CLASS_HID_1c72] = 513,
- [BNXT_ULP_CLASS_HID_171e] = 514,
- [BNXT_ULP_CLASS_HID_19c8] = 515,
- [BNXT_ULP_CLASS_HID_112c] = 516,
- [BNXT_ULP_CLASS_HID_4d68] = 517,
- [BNXT_ULP_CLASS_HID_444c] = 518,
- [BNXT_ULP_CLASS_HID_0e8c] = 519,
- [BNXT_ULP_CLASS_HID_09e0] = 520,
- [BNXT_ULP_CLASS_HID_1af0] = 521,
- [BNXT_ULP_CLASS_HID_15d4] = 522,
- [BNXT_ULP_CLASS_HID_1dd0] = 523,
- [BNXT_ULP_CLASS_HID_14f4] = 524,
- [BNXT_ULP_CLASS_HID_70b0] = 525,
- [BNXT_ULP_CLASS_HID_4854] = 526,
- [BNXT_ULP_CLASS_HID_3dd4] = 527,
- [BNXT_ULP_CLASS_HID_34f8] = 528,
- [BNXT_ULP_CLASS_HID_09e8] = 529,
- [BNXT_ULP_CLASS_HID_008c] = 530,
- [BNXT_ULP_CLASS_HID_34e6] = 531,
- [BNXT_ULP_CLASS_HID_0c02] = 532,
- [BNXT_ULP_CLASS_HID_1c9e] = 533,
- [BNXT_ULP_CLASS_HID_17ba] = 534,
- [BNXT_ULP_CLASS_HID_429e] = 535,
- [BNXT_ULP_CLASS_HID_5dba] = 536,
- [BNXT_ULP_CLASS_HID_2a16] = 537,
- [BNXT_ULP_CLASS_HID_2532] = 538,
- [BNXT_ULP_CLASS_HID_2da2] = 539,
- [BNXT_ULP_CLASS_HID_24fe] = 540,
- [BNXT_ULP_CLASS_HID_355a] = 541,
- [BNXT_ULP_CLASS_HID_0c76] = 542,
- [BNXT_ULP_CLASS_HID_13e6] = 543,
- [BNXT_ULP_CLASS_HID_7276] = 544,
- [BNXT_ULP_CLASS_HID_42d2] = 545,
- [BNXT_ULP_CLASS_HID_5dee] = 546,
- [BNXT_ULP_CLASS_HID_59de] = 547,
- [BNXT_ULP_CLASS_HID_513a] = 548,
- [BNXT_ULP_CLASS_HID_1c12] = 549,
- [BNXT_ULP_CLASS_HID_177e] = 550,
- [BNXT_ULP_CLASS_HID_0e92] = 551,
- [BNXT_ULP_CLASS_HID_09fe] = 552,
- [BNXT_ULP_CLASS_HID_5c1a] = 553,
- [BNXT_ULP_CLASS_HID_5746] = 554,
- [BNXT_ULP_CLASS_HID_79da] = 555,
- [BNXT_ULP_CLASS_HID_7106] = 556,
- [BNXT_ULP_CLASS_HID_3c1e] = 557,
- [BNXT_ULP_CLASS_HID_377a] = 558,
- [BNXT_ULP_CLASS_HID_2e9e] = 559,
- [BNXT_ULP_CLASS_HID_29fa] = 560,
- [BNXT_ULP_CLASS_HID_14d2] = 561,
- [BNXT_ULP_CLASS_HID_7742] = 562,
- [BNXT_ULP_CLASS_HID_3706] = 563,
- [BNXT_ULP_CLASS_HID_0fe2] = 564,
- [BNXT_ULP_CLASS_HID_1f7e] = 565,
- [BNXT_ULP_CLASS_HID_145a] = 566,
- [BNXT_ULP_CLASS_HID_417e] = 567,
- [BNXT_ULP_CLASS_HID_5e5a] = 568,
- [BNXT_ULP_CLASS_HID_29f6] = 569,
- [BNXT_ULP_CLASS_HID_26d2] = 570,
- [BNXT_ULP_CLASS_HID_2e42] = 571,
- [BNXT_ULP_CLASS_HID_271e] = 572,
- [BNXT_ULP_CLASS_HID_36ba] = 573,
- [BNXT_ULP_CLASS_HID_0f96] = 574,
- [BNXT_ULP_CLASS_HID_1006] = 575,
- [BNXT_ULP_CLASS_HID_7196] = 576,
- [BNXT_ULP_CLASS_HID_4132] = 577,
- [BNXT_ULP_CLASS_HID_5e0e] = 578,
- [BNXT_ULP_CLASS_HID_59fe] = 579,
- [BNXT_ULP_CLASS_HID_511a] = 580,
- [BNXT_ULP_CLASS_HID_1c32] = 581,
- [BNXT_ULP_CLASS_HID_175e] = 582,
- [BNXT_ULP_CLASS_HID_0eb2] = 583,
- [BNXT_ULP_CLASS_HID_09de] = 584,
- [BNXT_ULP_CLASS_HID_5c3a] = 585,
- [BNXT_ULP_CLASS_HID_5766] = 586,
- [BNXT_ULP_CLASS_HID_79fa] = 587,
- [BNXT_ULP_CLASS_HID_7126] = 588,
- [BNXT_ULP_CLASS_HID_3c3e] = 589,
- [BNXT_ULP_CLASS_HID_375a] = 590,
- [BNXT_ULP_CLASS_HID_2ebe] = 591,
- [BNXT_ULP_CLASS_HID_29da] = 592,
- [BNXT_ULP_CLASS_HID_14f2] = 593,
- [BNXT_ULP_CLASS_HID_7762] = 594,
- [BNXT_ULP_CLASS_HID_19e8] = 595,
- [BNXT_ULP_CLASS_HID_110c] = 596,
- [BNXT_ULP_CLASS_HID_4d48] = 597,
- [BNXT_ULP_CLASS_HID_446c] = 598,
- [BNXT_ULP_CLASS_HID_0eac] = 599,
- [BNXT_ULP_CLASS_HID_09c0] = 600,
- [BNXT_ULP_CLASS_HID_1ad0] = 601,
- [BNXT_ULP_CLASS_HID_15f4] = 602,
- [BNXT_ULP_CLASS_HID_39ec] = 603,
- [BNXT_ULP_CLASS_HID_3100] = 604,
- [BNXT_ULP_CLASS_HID_0210] = 605,
- [BNXT_ULP_CLASS_HID_1d34] = 606,
- [BNXT_ULP_CLASS_HID_2ea0] = 607,
- [BNXT_ULP_CLASS_HID_29c4] = 608,
- [BNXT_ULP_CLASS_HID_3ad4] = 609,
- [BNXT_ULP_CLASS_HID_35e8] = 610,
- [BNXT_ULP_CLASS_HID_5d80] = 611,
- [BNXT_ULP_CLASS_HID_54a4] = 612,
- [BNXT_ULP_CLASS_HID_29b4] = 613,
- [BNXT_ULP_CLASS_HID_20c8] = 614,
- [BNXT_ULP_CLASS_HID_7244] = 615,
- [BNXT_ULP_CLASS_HID_4d98] = 616,
- [BNXT_ULP_CLASS_HID_5e68] = 617,
- [BNXT_ULP_CLASS_HID_598c] = 618,
- [BNXT_ULP_CLASS_HID_1248] = 619,
- [BNXT_ULP_CLASS_HID_74d8] = 620,
- [BNXT_ULP_CLASS_HID_49a8] = 621,
- [BNXT_ULP_CLASS_HID_40cc] = 622,
- [BNXT_ULP_CLASS_HID_0b0c] = 623,
- [BNXT_ULP_CLASS_HID_0220] = 624,
- [BNXT_ULP_CLASS_HID_1730] = 625,
- [BNXT_ULP_CLASS_HID_7980] = 626,
- [BNXT_ULP_CLASS_HID_1db0] = 627,
- [BNXT_ULP_CLASS_HID_1494] = 628,
- [BNXT_ULP_CLASS_HID_70d0] = 629,
- [BNXT_ULP_CLASS_HID_4834] = 630,
- [BNXT_ULP_CLASS_HID_3db4] = 631,
- [BNXT_ULP_CLASS_HID_3498] = 632,
- [BNXT_ULP_CLASS_HID_0988] = 633,
- [BNXT_ULP_CLASS_HID_00ec] = 634,
- [BNXT_ULP_CLASS_HID_3f44] = 635,
- [BNXT_ULP_CLASS_HID_36a8] = 636,
- [BNXT_ULP_CLASS_HID_0b58] = 637,
- [BNXT_ULP_CLASS_HID_02bc] = 638,
- [BNXT_ULP_CLASS_HID_5f48] = 639,
- [BNXT_ULP_CLASS_HID_56ac] = 640,
- [BNXT_ULP_CLASS_HID_2b5c] = 641,
- [BNXT_ULP_CLASS_HID_2280] = 642,
- [BNXT_ULP_CLASS_HID_4000] = 643,
- [BNXT_ULP_CLASS_HID_5b64] = 644,
- [BNXT_ULP_CLASS_HID_2c14] = 645,
- [BNXT_ULP_CLASS_HID_2778] = 646,
- [BNXT_ULP_CLASS_HID_18f8] = 647,
- [BNXT_ULP_CLASS_HID_13dc] = 648,
- [BNXT_ULP_CLASS_HID_4c18] = 649,
- [BNXT_ULP_CLASS_HID_477c] = 650,
- [BNXT_ULP_CLASS_HID_1a88] = 651,
- [BNXT_ULP_CLASS_HID_15ec] = 652,
- [BNXT_ULP_CLASS_HID_4e28] = 653,
- [BNXT_ULP_CLASS_HID_490c] = 654,
- [BNXT_ULP_CLASS_HID_3a8c] = 655,
- [BNXT_ULP_CLASS_HID_35f0] = 656,
- [BNXT_ULP_CLASS_HID_06e0] = 657,
- [BNXT_ULP_CLASS_HID_01c4] = 658,
- [BNXT_ULP_CLASS_HID_1a08] = 659,
- [BNXT_ULP_CLASS_HID_12ec] = 660,
- [BNXT_ULP_CLASS_HID_4ea8] = 661,
- [BNXT_ULP_CLASS_HID_478c] = 662,
- [BNXT_ULP_CLASS_HID_0d4c] = 663,
- [BNXT_ULP_CLASS_HID_0a20] = 664,
- [BNXT_ULP_CLASS_HID_1930] = 665,
- [BNXT_ULP_CLASS_HID_1614] = 666,
- [BNXT_ULP_CLASS_HID_3a0c] = 667,
- [BNXT_ULP_CLASS_HID_32e0] = 668,
- [BNXT_ULP_CLASS_HID_01f0] = 669,
- [BNXT_ULP_CLASS_HID_1ed4] = 670,
- [BNXT_ULP_CLASS_HID_2d40] = 671,
- [BNXT_ULP_CLASS_HID_2a24] = 672,
- [BNXT_ULP_CLASS_HID_3934] = 673,
- [BNXT_ULP_CLASS_HID_3608] = 674,
- [BNXT_ULP_CLASS_HID_5e60] = 675,
- [BNXT_ULP_CLASS_HID_5744] = 676,
- [BNXT_ULP_CLASS_HID_2a54] = 677,
- [BNXT_ULP_CLASS_HID_2328] = 678,
- [BNXT_ULP_CLASS_HID_71a4] = 679,
- [BNXT_ULP_CLASS_HID_4e78] = 680,
- [BNXT_ULP_CLASS_HID_5d88] = 681,
- [BNXT_ULP_CLASS_HID_5a6c] = 682,
- [BNXT_ULP_CLASS_HID_11a8] = 683,
- [BNXT_ULP_CLASS_HID_7738] = 684,
- [BNXT_ULP_CLASS_HID_4a48] = 685,
- [BNXT_ULP_CLASS_HID_432c] = 686,
- [BNXT_ULP_CLASS_HID_08ec] = 687,
- [BNXT_ULP_CLASS_HID_01c0] = 688,
- [BNXT_ULP_CLASS_HID_14d0] = 689,
- [BNXT_ULP_CLASS_HID_7a60] = 690,
- [BNXT_ULP_CLASS_HID_1d90] = 691,
- [BNXT_ULP_CLASS_HID_14b4] = 692,
- [BNXT_ULP_CLASS_HID_70f0] = 693,
- [BNXT_ULP_CLASS_HID_4814] = 694,
- [BNXT_ULP_CLASS_HID_3d94] = 695,
- [BNXT_ULP_CLASS_HID_34b8] = 696,
- [BNXT_ULP_CLASS_HID_09a8] = 697,
- [BNXT_ULP_CLASS_HID_00cc] = 698,
- [BNXT_ULP_CLASS_HID_3f64] = 699,
- [BNXT_ULP_CLASS_HID_3688] = 700,
- [BNXT_ULP_CLASS_HID_0b78] = 701,
- [BNXT_ULP_CLASS_HID_029c] = 702,
- [BNXT_ULP_CLASS_HID_5f68] = 703,
- [BNXT_ULP_CLASS_HID_568c] = 704,
- [BNXT_ULP_CLASS_HID_2b7c] = 705,
- [BNXT_ULP_CLASS_HID_22a0] = 706,
- [BNXT_ULP_CLASS_HID_4020] = 707,
- [BNXT_ULP_CLASS_HID_5b44] = 708,
- [BNXT_ULP_CLASS_HID_2c34] = 709,
- [BNXT_ULP_CLASS_HID_2758] = 710,
- [BNXT_ULP_CLASS_HID_18d8] = 711,
- [BNXT_ULP_CLASS_HID_13fc] = 712,
- [BNXT_ULP_CLASS_HID_4c38] = 713,
- [BNXT_ULP_CLASS_HID_475c] = 714,
- [BNXT_ULP_CLASS_HID_1aa8] = 715,
- [BNXT_ULP_CLASS_HID_15cc] = 716,
- [BNXT_ULP_CLASS_HID_4e08] = 717,
- [BNXT_ULP_CLASS_HID_492c] = 718,
- [BNXT_ULP_CLASS_HID_3aac] = 719,
- [BNXT_ULP_CLASS_HID_35d0] = 720,
- [BNXT_ULP_CLASS_HID_06c0] = 721,
- [BNXT_ULP_CLASS_HID_01e4] = 722,
- [BNXT_ULP_CLASS_HID_4d32] = 723,
- [BNXT_ULP_CLASS_HID_54aa] = 724,
- [BNXT_ULP_CLASS_HID_0686] = 725,
- [BNXT_ULP_CLASS_HID_540e] = 726,
- [BNXT_ULP_CLASS_HID_2e3c] = 727,
- [BNXT_ULP_CLASS_HID_3a20] = 728,
- [BNXT_ULP_CLASS_HID_46f0] = 729,
- [BNXT_ULP_CLASS_HID_52e4] = 730,
- [BNXT_ULP_CLASS_HID_55e4] = 731,
- [BNXT_ULP_CLASS_HID_21f8] = 732,
- [BNXT_ULP_CLASS_HID_75e8] = 733,
- [BNXT_ULP_CLASS_HID_41fc] = 734,
- [BNXT_ULP_CLASS_HID_4d12] = 735,
- [BNXT_ULP_CLASS_HID_548a] = 736,
- [BNXT_ULP_CLASS_HID_3356] = 737,
- [BNXT_ULP_CLASS_HID_1ace] = 738,
- [BNXT_ULP_CLASS_HID_1a9a] = 739,
- [BNXT_ULP_CLASS_HID_4d46] = 740,
- [BNXT_ULP_CLASS_HID_2812] = 741,
- [BNXT_ULP_CLASS_HID_338a] = 742,
- [BNXT_ULP_CLASS_HID_06e6] = 743,
- [BNXT_ULP_CLASS_HID_546e] = 744,
- [BNXT_ULP_CLASS_HID_46ee] = 745,
- [BNXT_ULP_CLASS_HID_0d22] = 746,
- [BNXT_ULP_CLASS_HID_26e2] = 747,
- [BNXT_ULP_CLASS_HID_746a] = 748,
- [BNXT_ULP_CLASS_HID_1fa6] = 749,
- [BNXT_ULP_CLASS_HID_2d2e] = 750,
- [BNXT_ULP_CLASS_HID_4ef2] = 751,
- [BNXT_ULP_CLASS_HID_576a] = 752,
- [BNXT_ULP_CLASS_HID_30b6] = 753,
- [BNXT_ULP_CLASS_HID_192e] = 754,
- [BNXT_ULP_CLASS_HID_197a] = 755,
- [BNXT_ULP_CLASS_HID_4ea6] = 756,
- [BNXT_ULP_CLASS_HID_2bf2] = 757,
- [BNXT_ULP_CLASS_HID_306a] = 758,
- [BNXT_ULP_CLASS_HID_06c6] = 759,
- [BNXT_ULP_CLASS_HID_544e] = 760,
- [BNXT_ULP_CLASS_HID_46ce] = 761,
- [BNXT_ULP_CLASS_HID_0d02] = 762,
- [BNXT_ULP_CLASS_HID_26c2] = 763,
- [BNXT_ULP_CLASS_HID_744a] = 764,
- [BNXT_ULP_CLASS_HID_1f86] = 765,
- [BNXT_ULP_CLASS_HID_2d0e] = 766,
- [BNXT_ULP_CLASS_HID_2e1c] = 767,
- [BNXT_ULP_CLASS_HID_3a00] = 768,
- [BNXT_ULP_CLASS_HID_46d0] = 769,
- [BNXT_ULP_CLASS_HID_52c4] = 770,
- [BNXT_ULP_CLASS_HID_4e10] = 771,
- [BNXT_ULP_CLASS_HID_5a04] = 772,
- [BNXT_ULP_CLASS_HID_1f98] = 773,
- [BNXT_ULP_CLASS_HID_72f8] = 774,
- [BNXT_ULP_CLASS_HID_0a78] = 775,
- [BNXT_ULP_CLASS_HID_166c] = 776,
- [BNXT_ULP_CLASS_HID_233c] = 777,
- [BNXT_ULP_CLASS_HID_0f20] = 778,
- [BNXT_ULP_CLASS_HID_2a7c] = 779,
- [BNXT_ULP_CLASS_HID_3660] = 780,
- [BNXT_ULP_CLASS_HID_4330] = 781,
- [BNXT_ULP_CLASS_HID_2f24] = 782,
- [BNXT_ULP_CLASS_HID_5584] = 783,
- [BNXT_ULP_CLASS_HID_2198] = 784,
- [BNXT_ULP_CLASS_HID_7588] = 785,
- [BNXT_ULP_CLASS_HID_419c] = 786,
- [BNXT_ULP_CLASS_HID_7758] = 787,
- [BNXT_ULP_CLASS_HID_43ac] = 788,
- [BNXT_ULP_CLASS_HID_0c10] = 789,
- [BNXT_ULP_CLASS_HID_1864] = 790,
- [BNXT_ULP_CLASS_HID_30c8] = 791,
- [BNXT_ULP_CLASS_HID_1cdc] = 792,
- [BNXT_ULP_CLASS_HID_50cc] = 793,
- [BNXT_ULP_CLASS_HID_3d20] = 794,
- [BNXT_ULP_CLASS_HID_529c] = 795,
- [BNXT_ULP_CLASS_HID_3ef0] = 796,
- [BNXT_ULP_CLASS_HID_72e0] = 797,
- [BNXT_ULP_CLASS_HID_5ef4] = 798,
- [BNXT_ULP_CLASS_HID_2dfc] = 799,
- [BNXT_ULP_CLASS_HID_39e0] = 800,
- [BNXT_ULP_CLASS_HID_4530] = 801,
- [BNXT_ULP_CLASS_HID_5124] = 802,
- [BNXT_ULP_CLASS_HID_4df0] = 803,
- [BNXT_ULP_CLASS_HID_59e4] = 804,
- [BNXT_ULP_CLASS_HID_1c78] = 805,
- [BNXT_ULP_CLASS_HID_7118] = 806,
- [BNXT_ULP_CLASS_HID_0998] = 807,
- [BNXT_ULP_CLASS_HID_158c] = 808,
- [BNXT_ULP_CLASS_HID_20dc] = 809,
- [BNXT_ULP_CLASS_HID_0cc0] = 810,
- [BNXT_ULP_CLASS_HID_299c] = 811,
- [BNXT_ULP_CLASS_HID_3580] = 812,
- [BNXT_ULP_CLASS_HID_40d0] = 813,
- [BNXT_ULP_CLASS_HID_2cc4] = 814,
- [BNXT_ULP_CLASS_HID_55a4] = 815,
- [BNXT_ULP_CLASS_HID_21b8] = 816,
- [BNXT_ULP_CLASS_HID_75a8] = 817,
- [BNXT_ULP_CLASS_HID_41bc] = 818,
- [BNXT_ULP_CLASS_HID_7778] = 819,
- [BNXT_ULP_CLASS_HID_438c] = 820,
- [BNXT_ULP_CLASS_HID_0c30] = 821,
- [BNXT_ULP_CLASS_HID_1844] = 822,
- [BNXT_ULP_CLASS_HID_30e8] = 823,
- [BNXT_ULP_CLASS_HID_1cfc] = 824,
- [BNXT_ULP_CLASS_HID_50ec] = 825,
- [BNXT_ULP_CLASS_HID_3d00] = 826,
- [BNXT_ULP_CLASS_HID_52bc] = 827,
- [BNXT_ULP_CLASS_HID_3ed0] = 828,
- [BNXT_ULP_CLASS_HID_72c0] = 829,
- [BNXT_ULP_CLASS_HID_5ed4] = 830,
- [BNXT_ULP_CLASS_HID_3866] = 831,
- [BNXT_ULP_CLASS_HID_381e] = 832,
- [BNXT_ULP_CLASS_HID_3860] = 833,
- [BNXT_ULP_CLASS_HID_0454] = 834,
- [BNXT_ULP_CLASS_HID_3818] = 835,
- [BNXT_ULP_CLASS_HID_042c] = 836,
- [BNXT_ULP_CLASS_HID_3846] = 837,
- [BNXT_ULP_CLASS_HID_387e] = 838,
- [BNXT_ULP_CLASS_HID_3ba6] = 839,
- [BNXT_ULP_CLASS_HID_385e] = 840,
- [BNXT_ULP_CLASS_HID_3840] = 841,
- [BNXT_ULP_CLASS_HID_0474] = 842,
- [BNXT_ULP_CLASS_HID_3878] = 843,
- [BNXT_ULP_CLASS_HID_044c] = 844,
- [BNXT_ULP_CLASS_HID_3ba0] = 845,
- [BNXT_ULP_CLASS_HID_0794] = 846,
- [BNXT_ULP_CLASS_HID_3858] = 847,
- [BNXT_ULP_CLASS_HID_046c] = 848
+ [BNXT_ULP_CLASS_HID_e082] = 347,
+ [BNXT_ULP_CLASS_HID_ab46] = 348,
+ [BNXT_ULP_CLASS_HID_c82a] = 349,
+ [BNXT_ULP_CLASS_HID_f9a2] = 350,
+ [BNXT_ULP_CLASS_HID_d8ce] = 351,
+ [BNXT_ULP_CLASS_HID_a2d2] = 352,
+ [BNXT_ULP_CLASS_HID_c076] = 353,
+ [BNXT_ULP_CLASS_HID_f1ee] = 354,
+ [BNXT_ULP_CLASS_HID_a96e] = 355,
+ [BNXT_ULP_CLASS_HID_dae6] = 356,
+ [BNXT_ULP_CLASS_HID_c7aa] = 357,
+ [BNXT_ULP_CLASS_HID_c26e] = 358,
+ [BNXT_ULP_CLASS_HID_a0fa] = 359,
+ [BNXT_ULP_CLASS_HID_d272] = 360,
+ [BNXT_ULP_CLASS_HID_fff6] = 361,
+ [BNXT_ULP_CLASS_HID_e16e] = 362,
+ [BNXT_ULP_CLASS_HID_e165] = 363,
+ [BNXT_ULP_CLASS_HID_aaa1] = 364,
+ [BNXT_ULP_CLASS_HID_c9cd] = 365,
+ [BNXT_ULP_CLASS_HID_f845] = 366,
+ [BNXT_ULP_CLASS_HID_90f9] = 367,
+ [BNXT_ULP_CLASS_HID_c371] = 368,
+ [BNXT_ULP_CLASS_HID_e19d] = 369,
+ [BNXT_ULP_CLASS_HID_d015] = 370,
+ [BNXT_ULP_CLASS_HID_8c09] = 371,
+ [BNXT_ULP_CLASS_HID_be89] = 372,
+ [BNXT_ULP_CLASS_HID_ddad] = 373,
+ [BNXT_ULP_CLASS_HID_cc2d] = 374,
+ [BNXT_ULP_CLASS_HID_a4d9] = 375,
+ [BNXT_ULP_CLASS_HID_d759] = 376,
+ [BNXT_ULP_CLASS_HID_f27d] = 377,
+ [BNXT_ULP_CLASS_HID_e4fd] = 378,
+ [BNXT_ULP_CLASS_HID_ecf6] = 379,
+ [BNXT_ULP_CLASS_HID_a732] = 380,
+ [BNXT_ULP_CLASS_HID_c45e] = 381,
+ [BNXT_ULP_CLASS_HID_f5d6] = 382,
+ [BNXT_ULP_CLASS_HID_d4ba] = 383,
+ [BNXT_ULP_CLASS_HID_aea6] = 384,
+ [BNXT_ULP_CLASS_HID_cc02] = 385,
+ [BNXT_ULP_CLASS_HID_fd9a] = 386,
+ [BNXT_ULP_CLASS_HID_a51a] = 387,
+ [BNXT_ULP_CLASS_HID_d692] = 388,
+ [BNXT_ULP_CLASS_HID_cbde] = 389,
+ [BNXT_ULP_CLASS_HID_ce1a] = 390,
+ [BNXT_ULP_CLASS_HID_ac8e] = 391,
+ [BNXT_ULP_CLASS_HID_de06] = 392,
+ [BNXT_ULP_CLASS_HID_f382] = 393,
+ [BNXT_ULP_CLASS_HID_ed1a] = 394,
+ [BNXT_ULP_CLASS_HID_9d6a] = 395,
+ [BNXT_ULP_CLASS_HID_cee2] = 396,
+ [BNXT_ULP_CLASS_HID_ec0e] = 397,
+ [BNXT_ULP_CLASS_HID_dd86] = 398,
+ [BNXT_ULP_CLASS_HID_852e] = 399,
+ [BNXT_ULP_CLASS_HID_b6a6] = 400,
+ [BNXT_ULP_CLASS_HID_eb82] = 401,
+ [BNXT_ULP_CLASS_HID_c50a] = 402,
+ [BNXT_ULP_CLASS_HID_ccca] = 403,
+ [BNXT_ULP_CLASS_HID_8706] = 404,
+ [BNXT_ULP_CLASS_HID_d38e] = 405,
+ [BNXT_ULP_CLASS_HID_d5ca] = 406,
+ [BNXT_ULP_CLASS_HID_b48e] = 407,
+ [BNXT_ULP_CLASS_HID_8e8a] = 408,
+ [BNXT_ULP_CLASS_HID_db02] = 409,
+ [BNXT_ULP_CLASS_HID_dd8e] = 410,
+ [BNXT_ULP_CLASS_HID_819a] = 411,
+ [BNXT_ULP_CLASS_HID_b31a] = 412,
+ [BNXT_ULP_CLASS_HID_d03e] = 413,
+ [BNXT_ULP_CLASS_HID_c1be] = 414,
+ [BNXT_ULP_CLASS_HID_890e] = 415,
+ [BNXT_ULP_CLASS_HID_ba8e] = 416,
+ [BNXT_ULP_CLASS_HID_dfaa] = 417,
+ [BNXT_ULP_CLASS_HID_c93a] = 418,
+ [BNXT_ULP_CLASS_HID_b11a] = 419,
+ [BNXT_ULP_CLASS_HID_8b4e] = 420,
+ [BNXT_ULP_CLASS_HID_c79e] = 421,
+ [BNXT_ULP_CLASS_HID_d9da] = 422,
+ [BNXT_ULP_CLASS_HID_b88e] = 423,
+ [BNXT_ULP_CLASS_HID_ea0e] = 424,
+ [BNXT_ULP_CLASS_HID_cf0a] = 425,
+ [BNXT_ULP_CLASS_HID_c18e] = 426,
+ [BNXT_ULP_CLASS_HID_a94a] = 427,
+ [BNXT_ULP_CLASS_HID_daca] = 428,
+ [BNXT_ULP_CLASS_HID_ffee] = 429,
+ [BNXT_ULP_CLASS_HID_e96e] = 430,
+ [BNXT_ULP_CLASS_HID_910e] = 431,
+ [BNXT_ULP_CLASS_HID_c28e] = 432,
+ [BNXT_ULP_CLASS_HID_e7aa] = 433,
+ [BNXT_ULP_CLASS_HID_d12a] = 434,
+ [BNXT_ULP_CLASS_HID_d8ca] = 435,
+ [BNXT_ULP_CLASS_HID_930e] = 436,
+ [BNXT_ULP_CLASS_HID_ef4e] = 437,
+ [BNXT_ULP_CLASS_HID_e18a] = 438,
+ [BNXT_ULP_CLASS_HID_c08e] = 439,
+ [BNXT_ULP_CLASS_HID_9a8a] = 440,
+ [BNXT_ULP_CLASS_HID_d70a] = 441,
+ [BNXT_ULP_CLASS_HID_e90e] = 442,
+ [BNXT_ULP_CLASS_HID_edd9] = 443,
+ [BNXT_ULP_CLASS_HID_a61d] = 444,
+ [BNXT_ULP_CLASS_HID_c571] = 445,
+ [BNXT_ULP_CLASS_HID_f4f9] = 446,
+ [BNXT_ULP_CLASS_HID_9c45] = 447,
+ [BNXT_ULP_CLASS_HID_cfcd] = 448,
+ [BNXT_ULP_CLASS_HID_ed21] = 449,
+ [BNXT_ULP_CLASS_HID_dca9] = 450,
+ [BNXT_ULP_CLASS_HID_80b5] = 451,
+ [BNXT_ULP_CLASS_HID_b235] = 452,
+ [BNXT_ULP_CLASS_HID_d111] = 453,
+ [BNXT_ULP_CLASS_HID_c091] = 454,
+ [BNXT_ULP_CLASS_HID_a865] = 455,
+ [BNXT_ULP_CLASS_HID_dbe5] = 456,
+ [BNXT_ULP_CLASS_HID_fec1] = 457,
+ [BNXT_ULP_CLASS_HID_e841] = 458,
+ [BNXT_ULP_CLASS_HID_8e85] = 459,
+ [BNXT_ULP_CLASS_HID_b80d] = 460,
+ [BNXT_ULP_CLASS_HID_df65] = 461,
+ [BNXT_ULP_CLASS_HID_ceed] = 462,
+ [BNXT_ULP_CLASS_HID_9645] = 463,
+ [BNXT_ULP_CLASS_HID_c1cd] = 464,
+ [BNXT_ULP_CLASS_HID_e725] = 465,
+ [BNXT_ULP_CLASS_HID_d6ad] = 466,
+ [BNXT_ULP_CLASS_HID_9aa5] = 467,
+ [BNXT_ULP_CLASS_HID_b425] = 468,
+ [BNXT_ULP_CLASS_HID_eb05] = 469,
+ [BNXT_ULP_CLASS_HID_da85] = 470,
+ [BNXT_ULP_CLASS_HID_a265] = 471,
+ [BNXT_ULP_CLASS_HID_dde5] = 472,
+ [BNXT_ULP_CLASS_HID_f0c5] = 473,
+ [BNXT_ULP_CLASS_HID_e245] = 474,
+ [BNXT_ULP_CLASS_HID_8b8f] = 475,
+ [BNXT_ULP_CLASS_HID_a517] = 476,
+ [BNXT_ULP_CLASS_HID_d86b] = 477,
+ [BNXT_ULP_CLASS_HID_cbf3] = 478,
+ [BNXT_ULP_CLASS_HID_934f] = 479,
+ [BNXT_ULP_CLASS_HID_c2c7] = 480,
+ [BNXT_ULP_CLASS_HID_e02b] = 481,
+ [BNXT_ULP_CLASS_HID_d3a3] = 482,
+ [BNXT_ULP_CLASS_HID_87a7] = 483,
+ [BNXT_ULP_CLASS_HID_b137] = 484,
+ [BNXT_ULP_CLASS_HID_d403] = 485,
+ [BNXT_ULP_CLASS_HID_c793] = 486,
+ [BNXT_ULP_CLASS_HID_af67] = 487,
+ [BNXT_ULP_CLASS_HID_dee7] = 488,
+ [BNXT_ULP_CLASS_HID_fdc3] = 489,
+ [BNXT_ULP_CLASS_HID_ef43] = 490,
+ [BNXT_ULP_CLASS_HID_8dbf] = 491,
+ [BNXT_ULP_CLASS_HID_bf07] = 492,
+ [BNXT_ULP_CLASS_HID_d21f] = 493,
+ [BNXT_ULP_CLASS_HID_cde7] = 494,
+ [BNXT_ULP_CLASS_HID_956f] = 495,
+ [BNXT_ULP_CLASS_HID_c4c7] = 496,
+ [BNXT_ULP_CLASS_HID_fbcf] = 497,
+ [BNXT_ULP_CLASS_HID_d5a7] = 498,
+ [BNXT_ULP_CLASS_HID_9957] = 499,
+ [BNXT_ULP_CLASS_HID_cb27] = 500,
+ [BNXT_ULP_CLASS_HID_ee37] = 501,
+ [BNXT_ULP_CLASS_HID_d987] = 502,
+ [BNXT_ULP_CLASS_HID_a107] = 503,
+ [BNXT_ULP_CLASS_HID_d0e7] = 504,
+ [BNXT_ULP_CLASS_HID_f7e7] = 505,
+ [BNXT_ULP_CLASS_HID_c827] = 506,
+ [BNXT_ULP_CLASS_HID_f76a] = 507,
+ [BNXT_ULP_CLASS_HID_bcae] = 508,
+ [BNXT_ULP_CLASS_HID_dfc2] = 509,
+ [BNXT_ULP_CLASS_HID_ee4a] = 510,
+ [BNXT_ULP_CLASS_HID_cf26] = 511,
+ [BNXT_ULP_CLASS_HID_b53a] = 512,
+ [BNXT_ULP_CLASS_HID_d79e] = 513,
+ [BNXT_ULP_CLASS_HID_e606] = 514,
+ [BNXT_ULP_CLASS_HID_be86] = 515,
+ [BNXT_ULP_CLASS_HID_cd0e] = 516,
+ [BNXT_ULP_CLASS_HID_d042] = 517,
+ [BNXT_ULP_CLASS_HID_d586] = 518,
+ [BNXT_ULP_CLASS_HID_b712] = 519,
+ [BNXT_ULP_CLASS_HID_c59a] = 520,
+ [BNXT_ULP_CLASS_HID_e81e] = 521,
+ [BNXT_ULP_CLASS_HID_f686] = 522,
+ [BNXT_ULP_CLASS_HID_86f6] = 523,
+ [BNXT_ULP_CLASS_HID_d57e] = 524,
+ [BNXT_ULP_CLASS_HID_f792] = 525,
+ [BNXT_ULP_CLASS_HID_c61a] = 526,
+ [BNXT_ULP_CLASS_HID_9eb2] = 527,
+ [BNXT_ULP_CLASS_HID_ad3a] = 528,
+ [BNXT_ULP_CLASS_HID_f01e] = 529,
+ [BNXT_ULP_CLASS_HID_de96] = 530,
+ [BNXT_ULP_CLASS_HID_d756] = 531,
+ [BNXT_ULP_CLASS_HID_9c9a] = 532,
+ [BNXT_ULP_CLASS_HID_c812] = 533,
+ [BNXT_ULP_CLASS_HID_ce56] = 534,
+ [BNXT_ULP_CLASS_HID_af12] = 535,
+ [BNXT_ULP_CLASS_HID_9516] = 536,
+ [BNXT_ULP_CLASS_HID_c09e] = 537,
+ [BNXT_ULP_CLASS_HID_c612] = 538,
+ [BNXT_ULP_CLASS_HID_9a06] = 539,
+ [BNXT_ULP_CLASS_HID_a886] = 540,
+ [BNXT_ULP_CLASS_HID_cba2] = 541,
+ [BNXT_ULP_CLASS_HID_da22] = 542,
+ [BNXT_ULP_CLASS_HID_9292] = 543,
+ [BNXT_ULP_CLASS_HID_a112] = 544,
+ [BNXT_ULP_CLASS_HID_c436] = 545,
+ [BNXT_ULP_CLASS_HID_d2a6] = 546,
+ [BNXT_ULP_CLASS_HID_aa86] = 547,
+ [BNXT_ULP_CLASS_HID_90d2] = 548,
+ [BNXT_ULP_CLASS_HID_dc02] = 549,
+ [BNXT_ULP_CLASS_HID_c246] = 550,
+ [BNXT_ULP_CLASS_HID_a312] = 551,
+ [BNXT_ULP_CLASS_HID_f192] = 552,
+ [BNXT_ULP_CLASS_HID_d496] = 553,
+ [BNXT_ULP_CLASS_HID_da12] = 554,
+ [BNXT_ULP_CLASS_HID_b2d6] = 555,
+ [BNXT_ULP_CLASS_HID_c156] = 556,
+ [BNXT_ULP_CLASS_HID_e472] = 557,
+ [BNXT_ULP_CLASS_HID_f2f2] = 558,
+ [BNXT_ULP_CLASS_HID_8a92] = 559,
+ [BNXT_ULP_CLASS_HID_d912] = 560,
+ [BNXT_ULP_CLASS_HID_fc36] = 561,
+ [BNXT_ULP_CLASS_HID_cab6] = 562,
+ [BNXT_ULP_CLASS_HID_c356] = 563,
+ [BNXT_ULP_CLASS_HID_8892] = 564,
+ [BNXT_ULP_CLASS_HID_f4d2] = 565,
+ [BNXT_ULP_CLASS_HID_fa16] = 566,
+ [BNXT_ULP_CLASS_HID_db12] = 567,
+ [BNXT_ULP_CLASS_HID_8116] = 568,
+ [BNXT_ULP_CLASS_HID_cc96] = 569,
+ [BNXT_ULP_CLASS_HID_f292] = 570,
+ [BNXT_ULP_CLASS_HID_e84d] = 571,
+ [BNXT_ULP_CLASS_HID_a389] = 572,
+ [BNXT_ULP_CLASS_HID_c0e5] = 573,
+ [BNXT_ULP_CLASS_HID_f16d] = 574,
+ [BNXT_ULP_CLASS_HID_99d1] = 575,
+ [BNXT_ULP_CLASS_HID_ca59] = 576,
+ [BNXT_ULP_CLASS_HID_e8b5] = 577,
+ [BNXT_ULP_CLASS_HID_d93d] = 578,
+ [BNXT_ULP_CLASS_HID_8521] = 579,
+ [BNXT_ULP_CLASS_HID_b7a1] = 580,
+ [BNXT_ULP_CLASS_HID_d485] = 581,
+ [BNXT_ULP_CLASS_HID_c505] = 582,
+ [BNXT_ULP_CLASS_HID_adf1] = 583,
+ [BNXT_ULP_CLASS_HID_de71] = 584,
+ [BNXT_ULP_CLASS_HID_fb55] = 585,
+ [BNXT_ULP_CLASS_HID_edd5] = 586,
+ [BNXT_ULP_CLASS_HID_8b11] = 587,
+ [BNXT_ULP_CLASS_HID_bd99] = 588,
+ [BNXT_ULP_CLASS_HID_daf1] = 589,
+ [BNXT_ULP_CLASS_HID_cb79] = 590,
+ [BNXT_ULP_CLASS_HID_93d1] = 591,
+ [BNXT_ULP_CLASS_HID_c459] = 592,
+ [BNXT_ULP_CLASS_HID_e2b1] = 593,
+ [BNXT_ULP_CLASS_HID_d339] = 594,
+ [BNXT_ULP_CLASS_HID_9f31] = 595,
+ [BNXT_ULP_CLASS_HID_b1b1] = 596,
+ [BNXT_ULP_CLASS_HID_ee91] = 597,
+ [BNXT_ULP_CLASS_HID_df11] = 598,
+ [BNXT_ULP_CLASS_HID_a7f1] = 599,
+ [BNXT_ULP_CLASS_HID_d871] = 600,
+ [BNXT_ULP_CLASS_HID_f551] = 601,
+ [BNXT_ULP_CLASS_HID_e7d1] = 602,
+ [BNXT_ULP_CLASS_HID_8e1b] = 603,
+ [BNXT_ULP_CLASS_HID_a083] = 604,
+ [BNXT_ULP_CLASS_HID_ddff] = 605,
+ [BNXT_ULP_CLASS_HID_ce67] = 606,
+ [BNXT_ULP_CLASS_HID_96db] = 607,
+ [BNXT_ULP_CLASS_HID_c753] = 608,
+ [BNXT_ULP_CLASS_HID_e5bf] = 609,
+ [BNXT_ULP_CLASS_HID_d637] = 610,
+ [BNXT_ULP_CLASS_HID_8233] = 611,
+ [BNXT_ULP_CLASS_HID_b4a3] = 612,
+ [BNXT_ULP_CLASS_HID_d197] = 613,
+ [BNXT_ULP_CLASS_HID_c207] = 614,
+ [BNXT_ULP_CLASS_HID_aaf3] = 615,
+ [BNXT_ULP_CLASS_HID_db73] = 616,
+ [BNXT_ULP_CLASS_HID_f857] = 617,
+ [BNXT_ULP_CLASS_HID_ead7] = 618,
+ [BNXT_ULP_CLASS_HID_882b] = 619,
+ [BNXT_ULP_CLASS_HID_ba93] = 620,
+ [BNXT_ULP_CLASS_HID_d78b] = 621,
+ [BNXT_ULP_CLASS_HID_c873] = 622,
+ [BNXT_ULP_CLASS_HID_90fb] = 623,
+ [BNXT_ULP_CLASS_HID_c153] = 624,
+ [BNXT_ULP_CLASS_HID_fe5b] = 625,
+ [BNXT_ULP_CLASS_HID_d033] = 626,
+ [BNXT_ULP_CLASS_HID_9cc3] = 627,
+ [BNXT_ULP_CLASS_HID_ceb3] = 628,
+ [BNXT_ULP_CLASS_HID_eba3] = 629,
+ [BNXT_ULP_CLASS_HID_dc13] = 630,
+ [BNXT_ULP_CLASS_HID_a493] = 631,
+ [BNXT_ULP_CLASS_HID_d573] = 632,
+ [BNXT_ULP_CLASS_HID_f273] = 633,
+ [BNXT_ULP_CLASS_HID_cdb3] = 634,
+ [BNXT_ULP_CLASS_HID_ff35] = 635,
+ [BNXT_ULP_CLASS_HID_b4f1] = 636,
+ [BNXT_ULP_CLASS_HID_d79d] = 637,
+ [BNXT_ULP_CLASS_HID_e615] = 638,
+ [BNXT_ULP_CLASS_HID_8ea9] = 639,
+ [BNXT_ULP_CLASS_HID_dd21] = 640,
+ [BNXT_ULP_CLASS_HID_ffcd] = 641,
+ [BNXT_ULP_CLASS_HID_ce45] = 642,
+ [BNXT_ULP_CLASS_HID_9259] = 643,
+ [BNXT_ULP_CLASS_HID_a0d9] = 644,
+ [BNXT_ULP_CLASS_HID_c3fd] = 645,
+ [BNXT_ULP_CLASS_HID_d27d] = 646,
+ [BNXT_ULP_CLASS_HID_ba89] = 647,
+ [BNXT_ULP_CLASS_HID_c909] = 648,
+ [BNXT_ULP_CLASS_HID_ec2d] = 649,
+ [BNXT_ULP_CLASS_HID_faad] = 650,
+ [BNXT_ULP_CLASS_HID_34c6] = 651,
+ [BNXT_ULP_CLASS_HID_0c22] = 652,
+ [BNXT_ULP_CLASS_HID_1cbe] = 653,
+ [BNXT_ULP_CLASS_HID_179a] = 654,
+ [BNXT_ULP_CLASS_HID_59be] = 655,
+ [BNXT_ULP_CLASS_HID_515a] = 656,
+ [BNXT_ULP_CLASS_HID_1c72] = 657,
+ [BNXT_ULP_CLASS_HID_171e] = 658,
+ [BNXT_ULP_CLASS_HID_19c8] = 659,
+ [BNXT_ULP_CLASS_HID_112c] = 660,
+ [BNXT_ULP_CLASS_HID_4d68] = 661,
+ [BNXT_ULP_CLASS_HID_444c] = 662,
+ [BNXT_ULP_CLASS_HID_0e8c] = 663,
+ [BNXT_ULP_CLASS_HID_09e0] = 664,
+ [BNXT_ULP_CLASS_HID_1af0] = 665,
+ [BNXT_ULP_CLASS_HID_15d4] = 666,
+ [BNXT_ULP_CLASS_HID_1dd0] = 667,
+ [BNXT_ULP_CLASS_HID_14f4] = 668,
+ [BNXT_ULP_CLASS_HID_70b0] = 669,
+ [BNXT_ULP_CLASS_HID_4854] = 670,
+ [BNXT_ULP_CLASS_HID_3dd4] = 671,
+ [BNXT_ULP_CLASS_HID_34f8] = 672,
+ [BNXT_ULP_CLASS_HID_09e8] = 673,
+ [BNXT_ULP_CLASS_HID_008c] = 674,
+ [BNXT_ULP_CLASS_HID_34e6] = 675,
+ [BNXT_ULP_CLASS_HID_0c02] = 676,
+ [BNXT_ULP_CLASS_HID_1c9e] = 677,
+ [BNXT_ULP_CLASS_HID_17ba] = 678,
+ [BNXT_ULP_CLASS_HID_429e] = 679,
+ [BNXT_ULP_CLASS_HID_5dba] = 680,
+ [BNXT_ULP_CLASS_HID_2a16] = 681,
+ [BNXT_ULP_CLASS_HID_2532] = 682,
+ [BNXT_ULP_CLASS_HID_2da2] = 683,
+ [BNXT_ULP_CLASS_HID_24fe] = 684,
+ [BNXT_ULP_CLASS_HID_355a] = 685,
+ [BNXT_ULP_CLASS_HID_0c76] = 686,
+ [BNXT_ULP_CLASS_HID_13e6] = 687,
+ [BNXT_ULP_CLASS_HID_7276] = 688,
+ [BNXT_ULP_CLASS_HID_42d2] = 689,
+ [BNXT_ULP_CLASS_HID_5dee] = 690,
+ [BNXT_ULP_CLASS_HID_59de] = 691,
+ [BNXT_ULP_CLASS_HID_513a] = 692,
+ [BNXT_ULP_CLASS_HID_1c12] = 693,
+ [BNXT_ULP_CLASS_HID_177e] = 694,
+ [BNXT_ULP_CLASS_HID_0e92] = 695,
+ [BNXT_ULP_CLASS_HID_09fe] = 696,
+ [BNXT_ULP_CLASS_HID_5c1a] = 697,
+ [BNXT_ULP_CLASS_HID_5746] = 698,
+ [BNXT_ULP_CLASS_HID_79da] = 699,
+ [BNXT_ULP_CLASS_HID_7106] = 700,
+ [BNXT_ULP_CLASS_HID_3c1e] = 701,
+ [BNXT_ULP_CLASS_HID_377a] = 702,
+ [BNXT_ULP_CLASS_HID_2e9e] = 703,
+ [BNXT_ULP_CLASS_HID_29fa] = 704,
+ [BNXT_ULP_CLASS_HID_14d2] = 705,
+ [BNXT_ULP_CLASS_HID_7742] = 706,
+ [BNXT_ULP_CLASS_HID_3706] = 707,
+ [BNXT_ULP_CLASS_HID_0fe2] = 708,
+ [BNXT_ULP_CLASS_HID_1f7e] = 709,
+ [BNXT_ULP_CLASS_HID_145a] = 710,
+ [BNXT_ULP_CLASS_HID_417e] = 711,
+ [BNXT_ULP_CLASS_HID_5e5a] = 712,
+ [BNXT_ULP_CLASS_HID_29f6] = 713,
+ [BNXT_ULP_CLASS_HID_26d2] = 714,
+ [BNXT_ULP_CLASS_HID_2e42] = 715,
+ [BNXT_ULP_CLASS_HID_271e] = 716,
+ [BNXT_ULP_CLASS_HID_36ba] = 717,
+ [BNXT_ULP_CLASS_HID_0f96] = 718,
+ [BNXT_ULP_CLASS_HID_1006] = 719,
+ [BNXT_ULP_CLASS_HID_7196] = 720,
+ [BNXT_ULP_CLASS_HID_4132] = 721,
+ [BNXT_ULP_CLASS_HID_5e0e] = 722,
+ [BNXT_ULP_CLASS_HID_59fe] = 723,
+ [BNXT_ULP_CLASS_HID_511a] = 724,
+ [BNXT_ULP_CLASS_HID_1c32] = 725,
+ [BNXT_ULP_CLASS_HID_175e] = 726,
+ [BNXT_ULP_CLASS_HID_0eb2] = 727,
+ [BNXT_ULP_CLASS_HID_09de] = 728,
+ [BNXT_ULP_CLASS_HID_5c3a] = 729,
+ [BNXT_ULP_CLASS_HID_5766] = 730,
+ [BNXT_ULP_CLASS_HID_79fa] = 731,
+ [BNXT_ULP_CLASS_HID_7126] = 732,
+ [BNXT_ULP_CLASS_HID_3c3e] = 733,
+ [BNXT_ULP_CLASS_HID_375a] = 734,
+ [BNXT_ULP_CLASS_HID_2ebe] = 735,
+ [BNXT_ULP_CLASS_HID_29da] = 736,
+ [BNXT_ULP_CLASS_HID_14f2] = 737,
+ [BNXT_ULP_CLASS_HID_7762] = 738,
+ [BNXT_ULP_CLASS_HID_19e8] = 739,
+ [BNXT_ULP_CLASS_HID_110c] = 740,
+ [BNXT_ULP_CLASS_HID_4d48] = 741,
+ [BNXT_ULP_CLASS_HID_446c] = 742,
+ [BNXT_ULP_CLASS_HID_0eac] = 743,
+ [BNXT_ULP_CLASS_HID_09c0] = 744,
+ [BNXT_ULP_CLASS_HID_1ad0] = 745,
+ [BNXT_ULP_CLASS_HID_15f4] = 746,
+ [BNXT_ULP_CLASS_HID_39ec] = 747,
+ [BNXT_ULP_CLASS_HID_3100] = 748,
+ [BNXT_ULP_CLASS_HID_0210] = 749,
+ [BNXT_ULP_CLASS_HID_1d34] = 750,
+ [BNXT_ULP_CLASS_HID_2ea0] = 751,
+ [BNXT_ULP_CLASS_HID_29c4] = 752,
+ [BNXT_ULP_CLASS_HID_3ad4] = 753,
+ [BNXT_ULP_CLASS_HID_35e8] = 754,
+ [BNXT_ULP_CLASS_HID_5d80] = 755,
+ [BNXT_ULP_CLASS_HID_54a4] = 756,
+ [BNXT_ULP_CLASS_HID_29b4] = 757,
+ [BNXT_ULP_CLASS_HID_20c8] = 758,
+ [BNXT_ULP_CLASS_HID_7244] = 759,
+ [BNXT_ULP_CLASS_HID_4d98] = 760,
+ [BNXT_ULP_CLASS_HID_5e68] = 761,
+ [BNXT_ULP_CLASS_HID_598c] = 762,
+ [BNXT_ULP_CLASS_HID_1248] = 763,
+ [BNXT_ULP_CLASS_HID_74d8] = 764,
+ [BNXT_ULP_CLASS_HID_49a8] = 765,
+ [BNXT_ULP_CLASS_HID_40cc] = 766,
+ [BNXT_ULP_CLASS_HID_0b0c] = 767,
+ [BNXT_ULP_CLASS_HID_0220] = 768,
+ [BNXT_ULP_CLASS_HID_1730] = 769,
+ [BNXT_ULP_CLASS_HID_7980] = 770,
+ [BNXT_ULP_CLASS_HID_1db0] = 771,
+ [BNXT_ULP_CLASS_HID_1494] = 772,
+ [BNXT_ULP_CLASS_HID_70d0] = 773,
+ [BNXT_ULP_CLASS_HID_4834] = 774,
+ [BNXT_ULP_CLASS_HID_3db4] = 775,
+ [BNXT_ULP_CLASS_HID_3498] = 776,
+ [BNXT_ULP_CLASS_HID_0988] = 777,
+ [BNXT_ULP_CLASS_HID_00ec] = 778,
+ [BNXT_ULP_CLASS_HID_3f44] = 779,
+ [BNXT_ULP_CLASS_HID_36a8] = 780,
+ [BNXT_ULP_CLASS_HID_0b58] = 781,
+ [BNXT_ULP_CLASS_HID_02bc] = 782,
+ [BNXT_ULP_CLASS_HID_5f48] = 783,
+ [BNXT_ULP_CLASS_HID_56ac] = 784,
+ [BNXT_ULP_CLASS_HID_2b5c] = 785,
+ [BNXT_ULP_CLASS_HID_2280] = 786,
+ [BNXT_ULP_CLASS_HID_4000] = 787,
+ [BNXT_ULP_CLASS_HID_5b64] = 788,
+ [BNXT_ULP_CLASS_HID_2c14] = 789,
+ [BNXT_ULP_CLASS_HID_2778] = 790,
+ [BNXT_ULP_CLASS_HID_18f8] = 791,
+ [BNXT_ULP_CLASS_HID_13dc] = 792,
+ [BNXT_ULP_CLASS_HID_4c18] = 793,
+ [BNXT_ULP_CLASS_HID_477c] = 794,
+ [BNXT_ULP_CLASS_HID_1a88] = 795,
+ [BNXT_ULP_CLASS_HID_15ec] = 796,
+ [BNXT_ULP_CLASS_HID_4e28] = 797,
+ [BNXT_ULP_CLASS_HID_490c] = 798,
+ [BNXT_ULP_CLASS_HID_3a8c] = 799,
+ [BNXT_ULP_CLASS_HID_35f0] = 800,
+ [BNXT_ULP_CLASS_HID_06e0] = 801,
+ [BNXT_ULP_CLASS_HID_01c4] = 802,
+ [BNXT_ULP_CLASS_HID_1a08] = 803,
+ [BNXT_ULP_CLASS_HID_12ec] = 804,
+ [BNXT_ULP_CLASS_HID_4ea8] = 805,
+ [BNXT_ULP_CLASS_HID_478c] = 806,
+ [BNXT_ULP_CLASS_HID_0d4c] = 807,
+ [BNXT_ULP_CLASS_HID_0a20] = 808,
+ [BNXT_ULP_CLASS_HID_1930] = 809,
+ [BNXT_ULP_CLASS_HID_1614] = 810,
+ [BNXT_ULP_CLASS_HID_3a0c] = 811,
+ [BNXT_ULP_CLASS_HID_32e0] = 812,
+ [BNXT_ULP_CLASS_HID_01f0] = 813,
+ [BNXT_ULP_CLASS_HID_1ed4] = 814,
+ [BNXT_ULP_CLASS_HID_2d40] = 815,
+ [BNXT_ULP_CLASS_HID_2a24] = 816,
+ [BNXT_ULP_CLASS_HID_3934] = 817,
+ [BNXT_ULP_CLASS_HID_3608] = 818,
+ [BNXT_ULP_CLASS_HID_5e60] = 819,
+ [BNXT_ULP_CLASS_HID_5744] = 820,
+ [BNXT_ULP_CLASS_HID_2a54] = 821,
+ [BNXT_ULP_CLASS_HID_2328] = 822,
+ [BNXT_ULP_CLASS_HID_71a4] = 823,
+ [BNXT_ULP_CLASS_HID_4e78] = 824,
+ [BNXT_ULP_CLASS_HID_5d88] = 825,
+ [BNXT_ULP_CLASS_HID_5a6c] = 826,
+ [BNXT_ULP_CLASS_HID_11a8] = 827,
+ [BNXT_ULP_CLASS_HID_7738] = 828,
+ [BNXT_ULP_CLASS_HID_4a48] = 829,
+ [BNXT_ULP_CLASS_HID_432c] = 830,
+ [BNXT_ULP_CLASS_HID_08ec] = 831,
+ [BNXT_ULP_CLASS_HID_01c0] = 832,
+ [BNXT_ULP_CLASS_HID_14d0] = 833,
+ [BNXT_ULP_CLASS_HID_7a60] = 834,
+ [BNXT_ULP_CLASS_HID_1d90] = 835,
+ [BNXT_ULP_CLASS_HID_14b4] = 836,
+ [BNXT_ULP_CLASS_HID_70f0] = 837,
+ [BNXT_ULP_CLASS_HID_4814] = 838,
+ [BNXT_ULP_CLASS_HID_3d94] = 839,
+ [BNXT_ULP_CLASS_HID_34b8] = 840,
+ [BNXT_ULP_CLASS_HID_09a8] = 841,
+ [BNXT_ULP_CLASS_HID_00cc] = 842,
+ [BNXT_ULP_CLASS_HID_3f64] = 843,
+ [BNXT_ULP_CLASS_HID_3688] = 844,
+ [BNXT_ULP_CLASS_HID_0b78] = 845,
+ [BNXT_ULP_CLASS_HID_029c] = 846,
+ [BNXT_ULP_CLASS_HID_5f68] = 847,
+ [BNXT_ULP_CLASS_HID_568c] = 848,
+ [BNXT_ULP_CLASS_HID_2b7c] = 849,
+ [BNXT_ULP_CLASS_HID_22a0] = 850,
+ [BNXT_ULP_CLASS_HID_4020] = 851,
+ [BNXT_ULP_CLASS_HID_5b44] = 852,
+ [BNXT_ULP_CLASS_HID_2c34] = 853,
+ [BNXT_ULP_CLASS_HID_2758] = 854,
+ [BNXT_ULP_CLASS_HID_18d8] = 855,
+ [BNXT_ULP_CLASS_HID_13fc] = 856,
+ [BNXT_ULP_CLASS_HID_4c38] = 857,
+ [BNXT_ULP_CLASS_HID_475c] = 858,
+ [BNXT_ULP_CLASS_HID_1aa8] = 859,
+ [BNXT_ULP_CLASS_HID_15cc] = 860,
+ [BNXT_ULP_CLASS_HID_4e08] = 861,
+ [BNXT_ULP_CLASS_HID_492c] = 862,
+ [BNXT_ULP_CLASS_HID_3aac] = 863,
+ [BNXT_ULP_CLASS_HID_35d0] = 864,
+ [BNXT_ULP_CLASS_HID_06c0] = 865,
+ [BNXT_ULP_CLASS_HID_01e4] = 866,
+ [BNXT_ULP_CLASS_HID_4d32] = 867,
+ [BNXT_ULP_CLASS_HID_54aa] = 868,
+ [BNXT_ULP_CLASS_HID_0686] = 869,
+ [BNXT_ULP_CLASS_HID_540e] = 870,
+ [BNXT_ULP_CLASS_HID_2e3c] = 871,
+ [BNXT_ULP_CLASS_HID_3a20] = 872,
+ [BNXT_ULP_CLASS_HID_46f0] = 873,
+ [BNXT_ULP_CLASS_HID_52e4] = 874,
+ [BNXT_ULP_CLASS_HID_55e4] = 875,
+ [BNXT_ULP_CLASS_HID_21f8] = 876,
+ [BNXT_ULP_CLASS_HID_75e8] = 877,
+ [BNXT_ULP_CLASS_HID_41fc] = 878,
+ [BNXT_ULP_CLASS_HID_4d12] = 879,
+ [BNXT_ULP_CLASS_HID_548a] = 880,
+ [BNXT_ULP_CLASS_HID_3356] = 881,
+ [BNXT_ULP_CLASS_HID_1ace] = 882,
+ [BNXT_ULP_CLASS_HID_1a9a] = 883,
+ [BNXT_ULP_CLASS_HID_4d46] = 884,
+ [BNXT_ULP_CLASS_HID_2812] = 885,
+ [BNXT_ULP_CLASS_HID_338a] = 886,
+ [BNXT_ULP_CLASS_HID_06e6] = 887,
+ [BNXT_ULP_CLASS_HID_546e] = 888,
+ [BNXT_ULP_CLASS_HID_46ee] = 889,
+ [BNXT_ULP_CLASS_HID_0d22] = 890,
+ [BNXT_ULP_CLASS_HID_26e2] = 891,
+ [BNXT_ULP_CLASS_HID_746a] = 892,
+ [BNXT_ULP_CLASS_HID_1fa6] = 893,
+ [BNXT_ULP_CLASS_HID_2d2e] = 894,
+ [BNXT_ULP_CLASS_HID_4ef2] = 895,
+ [BNXT_ULP_CLASS_HID_576a] = 896,
+ [BNXT_ULP_CLASS_HID_30b6] = 897,
+ [BNXT_ULP_CLASS_HID_192e] = 898,
+ [BNXT_ULP_CLASS_HID_197a] = 899,
+ [BNXT_ULP_CLASS_HID_4ea6] = 900,
+ [BNXT_ULP_CLASS_HID_2bf2] = 901,
+ [BNXT_ULP_CLASS_HID_306a] = 902,
+ [BNXT_ULP_CLASS_HID_06c6] = 903,
+ [BNXT_ULP_CLASS_HID_544e] = 904,
+ [BNXT_ULP_CLASS_HID_46ce] = 905,
+ [BNXT_ULP_CLASS_HID_0d02] = 906,
+ [BNXT_ULP_CLASS_HID_26c2] = 907,
+ [BNXT_ULP_CLASS_HID_744a] = 908,
+ [BNXT_ULP_CLASS_HID_1f86] = 909,
+ [BNXT_ULP_CLASS_HID_2d0e] = 910,
+ [BNXT_ULP_CLASS_HID_2e1c] = 911,
+ [BNXT_ULP_CLASS_HID_3a00] = 912,
+ [BNXT_ULP_CLASS_HID_46d0] = 913,
+ [BNXT_ULP_CLASS_HID_52c4] = 914,
+ [BNXT_ULP_CLASS_HID_4e10] = 915,
+ [BNXT_ULP_CLASS_HID_5a04] = 916,
+ [BNXT_ULP_CLASS_HID_1f98] = 917,
+ [BNXT_ULP_CLASS_HID_72f8] = 918,
+ [BNXT_ULP_CLASS_HID_0a78] = 919,
+ [BNXT_ULP_CLASS_HID_166c] = 920,
+ [BNXT_ULP_CLASS_HID_233c] = 921,
+ [BNXT_ULP_CLASS_HID_0f20] = 922,
+ [BNXT_ULP_CLASS_HID_2a7c] = 923,
+ [BNXT_ULP_CLASS_HID_3660] = 924,
+ [BNXT_ULP_CLASS_HID_4330] = 925,
+ [BNXT_ULP_CLASS_HID_2f24] = 926,
+ [BNXT_ULP_CLASS_HID_5584] = 927,
+ [BNXT_ULP_CLASS_HID_2198] = 928,
+ [BNXT_ULP_CLASS_HID_7588] = 929,
+ [BNXT_ULP_CLASS_HID_419c] = 930,
+ [BNXT_ULP_CLASS_HID_7758] = 931,
+ [BNXT_ULP_CLASS_HID_43ac] = 932,
+ [BNXT_ULP_CLASS_HID_0c10] = 933,
+ [BNXT_ULP_CLASS_HID_1864] = 934,
+ [BNXT_ULP_CLASS_HID_30c8] = 935,
+ [BNXT_ULP_CLASS_HID_1cdc] = 936,
+ [BNXT_ULP_CLASS_HID_50cc] = 937,
+ [BNXT_ULP_CLASS_HID_3d20] = 938,
+ [BNXT_ULP_CLASS_HID_529c] = 939,
+ [BNXT_ULP_CLASS_HID_3ef0] = 940,
+ [BNXT_ULP_CLASS_HID_72e0] = 941,
+ [BNXT_ULP_CLASS_HID_5ef4] = 942,
+ [BNXT_ULP_CLASS_HID_2dfc] = 943,
+ [BNXT_ULP_CLASS_HID_39e0] = 944,
+ [BNXT_ULP_CLASS_HID_4530] = 945,
+ [BNXT_ULP_CLASS_HID_5124] = 946,
+ [BNXT_ULP_CLASS_HID_4df0] = 947,
+ [BNXT_ULP_CLASS_HID_59e4] = 948,
+ [BNXT_ULP_CLASS_HID_1c78] = 949,
+ [BNXT_ULP_CLASS_HID_7118] = 950,
+ [BNXT_ULP_CLASS_HID_0998] = 951,
+ [BNXT_ULP_CLASS_HID_158c] = 952,
+ [BNXT_ULP_CLASS_HID_20dc] = 953,
+ [BNXT_ULP_CLASS_HID_0cc0] = 954,
+ [BNXT_ULP_CLASS_HID_299c] = 955,
+ [BNXT_ULP_CLASS_HID_3580] = 956,
+ [BNXT_ULP_CLASS_HID_40d0] = 957,
+ [BNXT_ULP_CLASS_HID_2cc4] = 958,
+ [BNXT_ULP_CLASS_HID_55a4] = 959,
+ [BNXT_ULP_CLASS_HID_21b8] = 960,
+ [BNXT_ULP_CLASS_HID_75a8] = 961,
+ [BNXT_ULP_CLASS_HID_41bc] = 962,
+ [BNXT_ULP_CLASS_HID_7778] = 963,
+ [BNXT_ULP_CLASS_HID_438c] = 964,
+ [BNXT_ULP_CLASS_HID_0c30] = 965,
+ [BNXT_ULP_CLASS_HID_1844] = 966,
+ [BNXT_ULP_CLASS_HID_30e8] = 967,
+ [BNXT_ULP_CLASS_HID_1cfc] = 968,
+ [BNXT_ULP_CLASS_HID_50ec] = 969,
+ [BNXT_ULP_CLASS_HID_3d00] = 970,
+ [BNXT_ULP_CLASS_HID_52bc] = 971,
+ [BNXT_ULP_CLASS_HID_3ed0] = 972,
+ [BNXT_ULP_CLASS_HID_72c0] = 973,
+ [BNXT_ULP_CLASS_HID_5ed4] = 974,
+ [BNXT_ULP_CLASS_HID_3866] = 975,
+ [BNXT_ULP_CLASS_HID_381e] = 976,
+ [BNXT_ULP_CLASS_HID_3860] = 977,
+ [BNXT_ULP_CLASS_HID_0454] = 978,
+ [BNXT_ULP_CLASS_HID_3818] = 979,
+ [BNXT_ULP_CLASS_HID_042c] = 980,
+ [BNXT_ULP_CLASS_HID_3846] = 981,
+ [BNXT_ULP_CLASS_HID_387e] = 982,
+ [BNXT_ULP_CLASS_HID_3ba6] = 983,
+ [BNXT_ULP_CLASS_HID_385e] = 984,
+ [BNXT_ULP_CLASS_HID_3840] = 985,
+ [BNXT_ULP_CLASS_HID_0474] = 986,
+ [BNXT_ULP_CLASS_HID_3878] = 987,
+ [BNXT_ULP_CLASS_HID_044c] = 988,
+ [BNXT_ULP_CLASS_HID_3ba0] = 989,
+ [BNXT_ULP_CLASS_HID_0794] = 990,
+ [BNXT_ULP_CLASS_HID_3858] = 991,
+ [BNXT_ULP_CLASS_HID_046c] = 992
};
/* Array for the proto matcher list */
@@ -7165,7 +7309,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT }
},
[347] = {
- .class_hid = BNXT_ULP_CLASS_HID_6165,
+ .class_hid = BNXT_ULP_CLASS_HID_e082,
.class_tid = 2,
.hdr_sig_id = 1,
.flow_sig_id = 1313792,
@@ -7176,7 +7320,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7185,7 +7329,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC }
},
[348] = {
- .class_hid = BNXT_ULP_CLASS_HID_2aa1,
+ .class_hid = BNXT_ULP_CLASS_HID_ab46,
.class_tid = 2,
.hdr_sig_id = 1,
.flow_sig_id = 1321984,
@@ -7196,7 +7340,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7206,7 +7350,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC }
},
[349] = {
- .class_hid = BNXT_ULP_CLASS_HID_09cd,
+ .class_hid = BNXT_ULP_CLASS_HID_c82a,
.class_tid = 2,
.hdr_sig_id = 1,
.flow_sig_id = 3410944,
@@ -7217,7 +7361,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7227,7 +7371,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }
},
[350] = {
- .class_hid = BNXT_ULP_CLASS_HID_3845,
+ .class_hid = BNXT_ULP_CLASS_HID_f9a2,
.class_tid = 2,
.hdr_sig_id = 1,
.flow_sig_id = 3419136,
@@ -7238,7 +7382,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7249,10 +7393,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }
},
[351] = {
- .class_hid = BNXT_ULP_CLASS_HID_11e9,
+ .class_hid = BNXT_ULP_CLASS_HID_d8ce,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 2148797440,
+ .flow_sig_id = 538184704,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7260,20 +7404,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
},
[352] = {
- .class_hid = BNXT_ULP_CLASS_HID_4361,
+ .class_hid = BNXT_ULP_CLASS_HID_a2d2,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 2148805632,
+ .flow_sig_id = 538192896,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7281,7 +7425,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7289,13 +7433,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
},
[353] = {
- .class_hid = BNXT_ULP_CLASS_HID_218d,
+ .class_hid = BNXT_ULP_CLASS_HID_c076,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 2150894592,
+ .flow_sig_id = 540281856,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7303,7 +7447,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7311,13 +7455,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
},
[354] = {
- .class_hid = BNXT_ULP_CLASS_HID_5105,
+ .class_hid = BNXT_ULP_CLASS_HID_f1ee,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 2150902784,
+ .flow_sig_id = 540290048,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7325,7 +7469,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7334,13 +7478,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
},
[355] = {
- .class_hid = BNXT_ULP_CLASS_HID_0c89,
+ .class_hid = BNXT_ULP_CLASS_HID_a96e,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 4296281088,
+ .flow_sig_id = 1075055616,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7348,20 +7492,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[356] = {
- .class_hid = BNXT_ULP_CLASS_HID_3e81,
+ .class_hid = BNXT_ULP_CLASS_HID_dae6,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 4296289280,
+ .flow_sig_id = 1075063808,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7369,7 +7513,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7377,13 +7521,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[357] = {
- .class_hid = BNXT_ULP_CLASS_HID_1dad,
+ .class_hid = BNXT_ULP_CLASS_HID_c7aa,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 4298378240,
+ .flow_sig_id = 1077152768,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7391,7 +7535,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7399,13 +7543,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[358] = {
- .class_hid = BNXT_ULP_CLASS_HID_4ca5,
+ .class_hid = BNXT_ULP_CLASS_HID_c26e,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 4298386432,
+ .flow_sig_id = 1077160960,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7413,7 +7557,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7422,13 +7566,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[359] = {
- .class_hid = BNXT_ULP_CLASS_HID_25c9,
+ .class_hid = BNXT_ULP_CLASS_HID_a0fa,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 6443764736,
+ .flow_sig_id = 1611926528,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7436,21 +7580,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[360] = {
- .class_hid = BNXT_ULP_CLASS_HID_57c1,
+ .class_hid = BNXT_ULP_CLASS_HID_d272,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 6443772928,
+ .flow_sig_id = 1611934720,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7458,7 +7602,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7466,14 +7610,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[361] = {
- .class_hid = BNXT_ULP_CLASS_HID_33ed,
+ .class_hid = BNXT_ULP_CLASS_HID_fff6,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 6445861888,
+ .flow_sig_id = 1614023680,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7481,7 +7625,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7489,14 +7633,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[362] = {
- .class_hid = BNXT_ULP_CLASS_HID_65e5,
+ .class_hid = BNXT_ULP_CLASS_HID_e16e,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 6445870080,
+ .flow_sig_id = 1614031872,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7504,7 +7648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
@@ -7513,11 +7657,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
},
[363] = {
- .class_hid = BNXT_ULP_CLASS_HID_6dd9,
+ .class_hid = BNXT_ULP_CLASS_HID_e165,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 1313792,
@@ -7529,7 +7673,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7538,7 +7681,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }
},
[364] = {
- .class_hid = BNXT_ULP_CLASS_HID_261d,
+ .class_hid = BNXT_ULP_CLASS_HID_aaa1,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 1321984,
@@ -7550,7 +7693,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7560,7 +7702,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }
},
[365] = {
- .class_hid = BNXT_ULP_CLASS_HID_0571,
+ .class_hid = BNXT_ULP_CLASS_HID_c9cd,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 3410944,
@@ -7572,7 +7714,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7582,7 +7723,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
},
[366] = {
- .class_hid = BNXT_ULP_CLASS_HID_34f9,
+ .class_hid = BNXT_ULP_CLASS_HID_f845,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 3419136,
@@ -7594,7 +7735,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7605,7 +7745,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
},
[367] = {
- .class_hid = BNXT_ULP_CLASS_HID_1d55,
+ .class_hid = BNXT_ULP_CLASS_HID_90f9,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 2148797440,
@@ -7617,7 +7757,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7627,7 +7766,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
},
[368] = {
- .class_hid = BNXT_ULP_CLASS_HID_4fdd,
+ .class_hid = BNXT_ULP_CLASS_HID_c371,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 2148805632,
@@ -7639,7 +7778,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7650,7 +7788,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
},
[369] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d31,
+ .class_hid = BNXT_ULP_CLASS_HID_e19d,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 2150894592,
@@ -7662,7 +7800,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7673,7 +7810,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
},
[370] = {
- .class_hid = BNXT_ULP_CLASS_HID_5db9,
+ .class_hid = BNXT_ULP_CLASS_HID_d015,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 2150902784,
@@ -7685,7 +7822,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7697,7 +7833,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
},
[371] = {
- .class_hid = BNXT_ULP_CLASS_HID_0035,
+ .class_hid = BNXT_ULP_CLASS_HID_8c09,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 4296281088,
@@ -7709,7 +7845,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7719,7 +7854,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[372] = {
- .class_hid = BNXT_ULP_CLASS_HID_323d,
+ .class_hid = BNXT_ULP_CLASS_HID_be89,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 4296289280,
@@ -7731,7 +7866,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7742,7 +7876,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[373] = {
- .class_hid = BNXT_ULP_CLASS_HID_1111,
+ .class_hid = BNXT_ULP_CLASS_HID_ddad,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 4298378240,
@@ -7754,7 +7888,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7765,7 +7898,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[374] = {
- .class_hid = BNXT_ULP_CLASS_HID_4019,
+ .class_hid = BNXT_ULP_CLASS_HID_cc2d,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 4298386432,
@@ -7777,7 +7910,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7789,7 +7921,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[375] = {
- .class_hid = BNXT_ULP_CLASS_HID_2975,
+ .class_hid = BNXT_ULP_CLASS_HID_a4d9,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 6443764736,
@@ -7801,7 +7933,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7812,7 +7943,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[376] = {
- .class_hid = BNXT_ULP_CLASS_HID_5b7d,
+ .class_hid = BNXT_ULP_CLASS_HID_d759,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 6443772928,
@@ -7824,7 +7955,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7836,7 +7966,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[377] = {
- .class_hid = BNXT_ULP_CLASS_HID_3f51,
+ .class_hid = BNXT_ULP_CLASS_HID_f27d,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 6445861888,
@@ -7848,7 +7978,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7860,7 +7989,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[378] = {
- .class_hid = BNXT_ULP_CLASS_HID_6959,
+ .class_hid = BNXT_ULP_CLASS_HID_e4fd,
.class_tid = 2,
.hdr_sig_id = 2,
.flow_sig_id = 6445870080,
@@ -7872,7 +8001,6 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
@@ -7885,10 +8013,10 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
},
[379] = {
- .class_hid = BNXT_ULP_CLASS_HID_0e85,
+ .class_hid = BNXT_ULP_CLASS_HID_ecf6,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 8591248384,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1313792,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7896,21 +8024,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
},
[380] = {
- .class_hid = BNXT_ULP_CLASS_HID_380d,
+ .class_hid = BNXT_ULP_CLASS_HID_a732,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 8591256576,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1321984,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7918,22 +8045,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
},
[381] = {
- .class_hid = BNXT_ULP_CLASS_HID_1f21,
+ .class_hid = BNXT_ULP_CLASS_HID_c45e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 8593345536,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3410944,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7941,22 +8067,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
},
[382] = {
- .class_hid = BNXT_ULP_CLASS_HID_4ea9,
+ .class_hid = BNXT_ULP_CLASS_HID_f5d6,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 8593353728,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3419136,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7964,23 +8089,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
},
[383] = {
- .class_hid = BNXT_ULP_CLASS_HID_1705,
+ .class_hid = BNXT_ULP_CLASS_HID_d4ba,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 10738732032,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 538184704,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -7988,22 +8112,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[384] = {
- .class_hid = BNXT_ULP_CLASS_HID_418d,
+ .class_hid = BNXT_ULP_CLASS_HID_aea6,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 10738740224,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 538192896,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8011,23 +8134,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[385] = {
- .class_hid = BNXT_ULP_CLASS_HID_2721,
+ .class_hid = BNXT_ULP_CLASS_HID_cc02,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 10740829184,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 540281856,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8035,23 +8157,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[386] = {
- .class_hid = BNXT_ULP_CLASS_HID_57a9,
+ .class_hid = BNXT_ULP_CLASS_HID_fd9a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 10740837376,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 540290048,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8059,24 +8180,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[387] = {
- .class_hid = BNXT_ULP_CLASS_HID_1a25,
+ .class_hid = BNXT_ULP_CLASS_HID_a51a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 12886215680,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1075055616,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8084,22 +8204,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[388] = {
- .class_hid = BNXT_ULP_CLASS_HID_342d,
+ .class_hid = BNXT_ULP_CLASS_HID_d692,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 12886223872,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1075063808,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8107,23 +8226,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[389] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b01,
+ .class_hid = BNXT_ULP_CLASS_HID_cbde,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 12888312832,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1077152768,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8131,23 +8249,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[390] = {
- .class_hid = BNXT_ULP_CLASS_HID_5a09,
+ .class_hid = BNXT_ULP_CLASS_HID_ce1a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 12888321024,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1077160960,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8155,24 +8272,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[391] = {
- .class_hid = BNXT_ULP_CLASS_HID_2325,
+ .class_hid = BNXT_ULP_CLASS_HID_ac8e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 15033699328,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1611926528,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8180,23 +8296,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[392] = {
- .class_hid = BNXT_ULP_CLASS_HID_5d2d,
+ .class_hid = BNXT_ULP_CLASS_HID_de06,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 15033707520,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1611934720,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8204,24 +8319,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[393] = {
- .class_hid = BNXT_ULP_CLASS_HID_3101,
+ .class_hid = BNXT_ULP_CLASS_HID_f382,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 15035796480,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1614023680,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8229,24 +8343,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[394] = {
- .class_hid = BNXT_ULP_CLASS_HID_6309,
+ .class_hid = BNXT_ULP_CLASS_HID_ed1a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 15035804672,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1614031872,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8254,25 +8367,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[395] = {
- .class_hid = BNXT_ULP_CLASS_HID_0bad,
+ .class_hid = BNXT_ULP_CLASS_HID_9d6a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 17181182976,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2148797440,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8280,21 +8392,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[396] = {
- .class_hid = BNXT_ULP_CLASS_HID_2535,
+ .class_hid = BNXT_ULP_CLASS_HID_cee2,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 17181191168,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2148805632,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8302,22 +8414,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[397] = {
- .class_hid = BNXT_ULP_CLASS_HID_1869,
+ .class_hid = BNXT_ULP_CLASS_HID_ec0e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 17183280128,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2150894592,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8325,22 +8437,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[398] = {
- .class_hid = BNXT_ULP_CLASS_HID_4bf1,
+ .class_hid = BNXT_ULP_CLASS_HID_dd86,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 17183288320,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2150902784,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8348,23 +8460,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[399] = {
- .class_hid = BNXT_ULP_CLASS_HID_136d,
+ .class_hid = BNXT_ULP_CLASS_HID_852e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 19328666624,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2685668352,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8372,22 +8484,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[400] = {
- .class_hid = BNXT_ULP_CLASS_HID_43f5,
+ .class_hid = BNXT_ULP_CLASS_HID_b6a6,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 19328674816,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2685676544,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8395,23 +8507,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[401] = {
- .class_hid = BNXT_ULP_CLASS_HID_2129,
+ .class_hid = BNXT_ULP_CLASS_HID_eb82,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 19330763776,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2687765504,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8419,23 +8531,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[402] = {
- .class_hid = BNXT_ULP_CLASS_HID_53b1,
+ .class_hid = BNXT_ULP_CLASS_HID_c50a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 19330771968,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2687773696,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8443,24 +8555,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[403] = {
- .class_hid = BNXT_ULP_CLASS_HID_072d,
+ .class_hid = BNXT_ULP_CLASS_HID_ccca,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 21476150272,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3222539264,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8468,22 +8580,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[404] = {
- .class_hid = BNXT_ULP_CLASS_HID_3135,
+ .class_hid = BNXT_ULP_CLASS_HID_8706,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 21476158464,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3222547456,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8491,23 +8603,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[405] = {
- .class_hid = BNXT_ULP_CLASS_HID_1429,
+ .class_hid = BNXT_ULP_CLASS_HID_d38e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 21478247424,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3224636416,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8515,23 +8627,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[406] = {
- .class_hid = BNXT_ULP_CLASS_HID_4731,
+ .class_hid = BNXT_ULP_CLASS_HID_d5ca,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 21478255616,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3224644608,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8539,24 +8651,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[407] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f6d,
+ .class_hid = BNXT_ULP_CLASS_HID_b48e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 23623633920,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3759410176,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8564,23 +8676,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[408] = {
- .class_hid = BNXT_ULP_CLASS_HID_5f75,
+ .class_hid = BNXT_ULP_CLASS_HID_8e8a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 23623642112,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3759418368,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8588,24 +8700,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[409] = {
- .class_hid = BNXT_ULP_CLASS_HID_3d69,
+ .class_hid = BNXT_ULP_CLASS_HID_db02,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 23625731072,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3761507328,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8613,24 +8725,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
},
[410] = {
- .class_hid = BNXT_ULP_CLASS_HID_6f71,
+ .class_hid = BNXT_ULP_CLASS_HID_dd8e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 23625739264,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3761515520,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8638,25 +8750,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
- },
- [411] = {
- .class_hid = BNXT_ULP_CLASS_HID_0dbd,
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ },
+ [411] = {
+ .class_hid = BNXT_ULP_CLASS_HID_819a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 25771117568,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4296281088,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8664,22 +8776,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[412] = {
- .class_hid = BNXT_ULP_CLASS_HID_3f25,
+ .class_hid = BNXT_ULP_CLASS_HID_b31a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 25771125760,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4296289280,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8687,23 +8798,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[413] = {
- .class_hid = BNXT_ULP_CLASS_HID_1239,
+ .class_hid = BNXT_ULP_CLASS_HID_d03e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 25773214720,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4298378240,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8711,23 +8821,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[414] = {
- .class_hid = BNXT_ULP_CLASS_HID_4da1,
+ .class_hid = BNXT_ULP_CLASS_HID_c1be,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 25773222912,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4298386432,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8735,24 +8844,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[415] = {
- .class_hid = BNXT_ULP_CLASS_HID_153d,
+ .class_hid = BNXT_ULP_CLASS_HID_890e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 27918601216,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4833152000,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8760,23 +8868,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[416] = {
- .class_hid = BNXT_ULP_CLASS_HID_45a5,
+ .class_hid = BNXT_ULP_CLASS_HID_ba8e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 27918609408,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4833160192,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8784,24 +8891,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[417] = {
- .class_hid = BNXT_ULP_CLASS_HID_3bb9,
+ .class_hid = BNXT_ULP_CLASS_HID_dfaa,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 27920698368,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4835249152,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8809,24 +8915,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[418] = {
- .class_hid = BNXT_ULP_CLASS_HID_55a1,
+ .class_hid = BNXT_ULP_CLASS_HID_c93a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 27920706560,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 4835257344,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8834,25 +8939,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[419] = {
- .class_hid = BNXT_ULP_CLASS_HID_193d,
+ .class_hid = BNXT_ULP_CLASS_HID_b11a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 30066084864,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5370022912,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8860,23 +8964,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[420] = {
- .class_hid = BNXT_ULP_CLASS_HID_4b25,
+ .class_hid = BNXT_ULP_CLASS_HID_8b4e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 30066093056,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5370031104,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8884,24 +8987,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[421] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e39,
+ .class_hid = BNXT_ULP_CLASS_HID_c79e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 30068182016,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5372120064,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8909,24 +9011,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[422] = {
- .class_hid = BNXT_ULP_CLASS_HID_5921,
+ .class_hid = BNXT_ULP_CLASS_HID_d9da,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 30068190208,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5372128256,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8934,25 +9035,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[423] = {
- .class_hid = BNXT_ULP_CLASS_HID_213d,
+ .class_hid = BNXT_ULP_CLASS_HID_b88e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 32213568512,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5906893824,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8960,24 +9060,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[424] = {
- .class_hid = BNXT_ULP_CLASS_HID_5125,
+ .class_hid = BNXT_ULP_CLASS_HID_ea0e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 32213576704,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5906902016,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8985,25 +9084,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[425] = {
- .class_hid = BNXT_ULP_CLASS_HID_3739,
+ .class_hid = BNXT_ULP_CLASS_HID_cf0a,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 32215665664,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5908990976,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -9011,25 +9109,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
},
[426] = {
- .class_hid = BNXT_ULP_CLASS_HID_093d,
+ .class_hid = BNXT_ULP_CLASS_HID_c18e,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 32215673856,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 5908999168,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -9037,25 +9134,3496 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [427] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a94a,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6443764736,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [428] = {
+ .class_hid = BNXT_ULP_CLASS_HID_daca,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6443772928,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [429] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ffee,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6445861888,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [430] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e96e,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6445870080,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [431] = {
+ .class_hid = BNXT_ULP_CLASS_HID_910e,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6980635648,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [432] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c28e,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6980643840,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [433] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e7aa,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6982732800,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [434] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d12a,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 6982740992,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [435] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d8ca,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 7517506560,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [436] = {
+ .class_hid = BNXT_ULP_CLASS_HID_930e,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 7517514752,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [437] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ef4e,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 7519603712,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [438] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e18a,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 7519611904,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [439] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c08e,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8054377472,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [440] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9a8a,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8054385664,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [441] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d70a,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8056474624,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [442] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e90e,
+ .class_tid = 2,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 8056482816,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ },
+ [443] = {
+ .class_hid = BNXT_ULP_CLASS_HID_edd9,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1313792,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ },
+ [444] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a61d,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1321984,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ },
+ [445] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c571,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 3410944,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ },
+ [446] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f4f9,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 3419136,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ },
+ [447] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9c45,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2148797440,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [448] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cfcd,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2148805632,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [449] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ed21,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2150894592,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [450] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dca9,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 2150902784,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [451] = {
+ .class_hid = BNXT_ULP_CLASS_HID_80b5,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4296281088,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [452] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b235,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4296289280,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [453] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d111,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4298378240,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [454] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c091,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 4298386432,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [455] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a865,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6443764736,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [456] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dbe5,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6443772928,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [457] = {
+ .class_hid = BNXT_ULP_CLASS_HID_fec1,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6445861888,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [458] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e841,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 6445870080,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [459] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8e85,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 8591248384,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [460] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b80d,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 8591256576,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [461] = {
+ .class_hid = BNXT_ULP_CLASS_HID_df65,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 8593345536,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [462] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ceed,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 8593353728,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [463] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9645,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 10738732032,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [464] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1cd,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 10738740224,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [465] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e725,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 10740829184,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [466] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d6ad,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 10740837376,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [467] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9aa5,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 12886215680,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [468] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b425,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 12886223872,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [469] = {
+ .class_hid = BNXT_ULP_CLASS_HID_eb05,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 12888312832,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [470] = {
+ .class_hid = BNXT_ULP_CLASS_HID_da85,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 12888321024,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [471] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a265,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 15033699328,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [472] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dde5,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 15033707520,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [473] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f0c5,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 15035796480,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [474] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e245,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 15035804672,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ },
+ [475] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8b8f,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 17181182976,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [476] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a517,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 17181191168,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [477] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d86b,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 17183280128,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [478] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cbf3,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 17183288320,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [479] = {
+ .class_hid = BNXT_ULP_CLASS_HID_934f,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 19328666624,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [480] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c2c7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 19328674816,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [481] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e02b,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 19330763776,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [482] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d3a3,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 19330771968,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [483] = {
+ .class_hid = BNXT_ULP_CLASS_HID_87a7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 21476150272,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [484] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b137,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 21476158464,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [485] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d403,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 21478247424,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [486] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c793,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 21478255616,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [487] = {
+ .class_hid = BNXT_ULP_CLASS_HID_af67,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 23623633920,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [488] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dee7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 23623642112,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [489] = {
+ .class_hid = BNXT_ULP_CLASS_HID_fdc3,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 23625731072,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [490] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ef43,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 23625739264,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [491] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8dbf,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 25771117568,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [492] = {
+ .class_hid = BNXT_ULP_CLASS_HID_bf07,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 25771125760,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [493] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d21f,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 25773214720,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [494] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cde7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 25773222912,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [495] = {
+ .class_hid = BNXT_ULP_CLASS_HID_956f,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 27918601216,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [496] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c4c7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 27918609408,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [497] = {
+ .class_hid = BNXT_ULP_CLASS_HID_fbcf,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 27920698368,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [498] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d5a7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 27920706560,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [499] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9957,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 30066084864,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [500] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cb27,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 30066093056,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [501] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ee37,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 30068182016,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [502] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d987,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 30068190208,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [503] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a107,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 32213568512,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [504] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d0e7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 32213576704,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [505] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f7e7,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 32215665664,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [506] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c827,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 32215673856,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ },
+ [507] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f76a,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1313792,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC }
+ },
+ [508] = {
+ .class_hid = BNXT_ULP_CLASS_HID_bcae,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1321984,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC }
+ },
+ [509] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dfc2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3410944,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC }
+ },
+ [510] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ee4a,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3419136,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC }
+ },
+ [511] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cf26,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 538184704,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [512] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b53a,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 538192896,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [513] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d79e,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 540281856,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [514] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e606,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 540290048,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [515] = {
+ .class_hid = BNXT_ULP_CLASS_HID_be86,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1075055616,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [516] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cd0e,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1075063808,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [517] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d042,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1077152768,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [518] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d586,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1077160960,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [519] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b712,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1611926528,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [520] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c59a,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1611934720,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [521] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e81e,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1614023680,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [522] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f686,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1614031872,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [523] = {
+ .class_hid = BNXT_ULP_CLASS_HID_86f6,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2148797440,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [524] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d57e,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2148805632,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [525] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f792,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2150894592,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [526] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c61a,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2150902784,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [527] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9eb2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2685668352,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [528] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ad3a,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2685676544,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [529] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f01e,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2687765504,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [530] = {
+ .class_hid = BNXT_ULP_CLASS_HID_de96,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2687773696,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [531] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d756,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3222539264,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [532] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9c9a,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3222547456,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [533] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c812,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3224636416,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [534] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ce56,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3224644608,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [535] = {
+ .class_hid = BNXT_ULP_CLASS_HID_af12,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3759410176,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [536] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9516,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3759418368,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [537] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c09e,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3761507328,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [538] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c612,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3761515520,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ },
+ [539] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9a06,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4296281088,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [540] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a886,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4296289280,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [541] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cba2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4298378240,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [542] = {
+ .class_hid = BNXT_ULP_CLASS_HID_da22,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4298386432,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [543] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9292,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4833152000,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [544] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a112,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4833160192,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [545] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c436,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4835249152,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [546] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d2a6,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4835257344,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [547] = {
+ .class_hid = BNXT_ULP_CLASS_HID_aa86,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5370022912,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [548] = {
+ .class_hid = BNXT_ULP_CLASS_HID_90d2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5370031104,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [549] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dc02,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5372120064,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [550] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c246,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5372128256,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [551] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a312,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5906893824,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [552] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f192,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5906902016,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [553] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d496,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5908990976,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [554] = {
+ .class_hid = BNXT_ULP_CLASS_HID_da12,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 5908999168,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [555] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b2d6,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6443764736,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [556] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c156,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6443772928,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [557] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e472,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6445861888,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [558] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f2f2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6445870080,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [559] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8a92,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6980635648,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [560] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d912,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6980643840,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [561] = {
+ .class_hid = BNXT_ULP_CLASS_HID_fc36,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6982732800,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [562] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cab6,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6982740992,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [563] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c356,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 7517506560,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [564] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8892,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 7517514752,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [565] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f4d2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 7519603712,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [566] = {
+ .class_hid = BNXT_ULP_CLASS_HID_fa16,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 7519611904,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [567] = {
+ .class_hid = BNXT_ULP_CLASS_HID_db12,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 8054377472,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [568] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8116,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 8054385664,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [569] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cc96,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 8056474624,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ },
+ [570] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f292,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 8056482816,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
},
- [427] = {
- .class_hid = BNXT_ULP_CLASS_HID_684d,
+ [571] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e84d,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 1313792,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9068,15 +12636,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC }
},
- [428] = {
- .class_hid = BNXT_ULP_CLASS_HID_2389,
+ [572] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a389,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 1321984,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9089,16 +12657,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC }
},
- [429] = {
- .class_hid = BNXT_ULP_CLASS_HID_00e5,
+ [573] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c0e5,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 3410944,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9111,16 +12679,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC }
},
- [430] = {
- .class_hid = BNXT_ULP_CLASS_HID_316d,
+ [574] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f16d,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 3419136,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9133,17 +12701,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC }
},
- [431] = {
- .class_hid = BNXT_ULP_CLASS_HID_18c1,
+ [575] = {
+ .class_hid = BNXT_ULP_CLASS_HID_99d1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 2148797440,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9156,16 +12724,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
},
- [432] = {
- .class_hid = BNXT_ULP_CLASS_HID_4a49,
+ [576] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ca59,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 2148805632,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9178,17 +12746,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
},
- [433] = {
- .class_hid = BNXT_ULP_CLASS_HID_28a5,
+ [577] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e8b5,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 2150894592,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9201,17 +12769,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
},
- [434] = {
- .class_hid = BNXT_ULP_CLASS_HID_582d,
+ [578] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d93d,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 2150902784,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9224,18 +12792,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
},
- [435] = {
- .class_hid = BNXT_ULP_CLASS_HID_05a1,
+ [579] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8521,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 4296281088,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9248,16 +12816,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [436] = {
- .class_hid = BNXT_ULP_CLASS_HID_37a9,
+ [580] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b7a1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 4296289280,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9270,17 +12838,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [437] = {
- .class_hid = BNXT_ULP_CLASS_HID_1485,
+ [581] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d485,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 4298378240,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9293,17 +12861,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [438] = {
- .class_hid = BNXT_ULP_CLASS_HID_458d,
+ [582] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c505,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 4298386432,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9316,18 +12884,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [439] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ce1,
+ [583] = {
+ .class_hid = BNXT_ULP_CLASS_HID_adf1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 6443764736,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9340,17 +12908,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [440] = {
- .class_hid = BNXT_ULP_CLASS_HID_5ee9,
+ [584] = {
+ .class_hid = BNXT_ULP_CLASS_HID_de71,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 6443772928,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9363,18 +12931,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [441] = {
- .class_hid = BNXT_ULP_CLASS_HID_3ac5,
+ [585] = {
+ .class_hid = BNXT_ULP_CLASS_HID_fb55,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 6445861888,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9387,18 +12955,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [442] = {
- .class_hid = BNXT_ULP_CLASS_HID_6ccd,
+ [586] = {
+ .class_hid = BNXT_ULP_CLASS_HID_edd5,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 6445870080,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9411,19 +12979,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
},
- [443] = {
- .class_hid = BNXT_ULP_CLASS_HID_0b11,
+ [587] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8b11,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 8591248384,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9436,16 +13004,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [444] = {
- .class_hid = BNXT_ULP_CLASS_HID_3d99,
+ [588] = {
+ .class_hid = BNXT_ULP_CLASS_HID_bd99,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 8591256576,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9458,17 +13026,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [445] = {
- .class_hid = BNXT_ULP_CLASS_HID_1ab5,
+ [589] = {
+ .class_hid = BNXT_ULP_CLASS_HID_daf1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 8593345536,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9481,17 +13049,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [446] = {
- .class_hid = BNXT_ULP_CLASS_HID_4b3d,
+ [590] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cb79,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 8593353728,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9504,18 +13072,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [447] = {
- .class_hid = BNXT_ULP_CLASS_HID_1291,
+ [591] = {
+ .class_hid = BNXT_ULP_CLASS_HID_93d1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 10738732032,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9528,17 +13096,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [448] = {
- .class_hid = BNXT_ULP_CLASS_HID_4419,
+ [592] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c459,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 10738740224,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9551,18 +13119,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [449] = {
- .class_hid = BNXT_ULP_CLASS_HID_22b5,
+ [593] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e2b1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 10740829184,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9575,18 +13143,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [450] = {
- .class_hid = BNXT_ULP_CLASS_HID_523d,
+ [594] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d339,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 10740837376,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9599,19 +13167,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [451] = {
- .class_hid = BNXT_ULP_CLASS_HID_1fb1,
+ [595] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9f31,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 12886215680,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9624,17 +13192,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [452] = {
- .class_hid = BNXT_ULP_CLASS_HID_31b9,
+ [596] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b1b1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 12886223872,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9647,18 +13215,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [453] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e95,
+ [597] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ee91,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 12888312832,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9671,18 +13239,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [454] = {
- .class_hid = BNXT_ULP_CLASS_HID_5f9d,
+ [598] = {
+ .class_hid = BNXT_ULP_CLASS_HID_df11,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 12888321024,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9695,19 +13263,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [455] = {
- .class_hid = BNXT_ULP_CLASS_HID_26b1,
+ [599] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a7f1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 15033699328,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9720,18 +13288,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [456] = {
- .class_hid = BNXT_ULP_CLASS_HID_58b9,
+ [600] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d871,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 15033707520,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9744,19 +13312,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [457] = {
- .class_hid = BNXT_ULP_CLASS_HID_3495,
+ [601] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f551,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 15035796480,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9769,19 +13337,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [458] = {
- .class_hid = BNXT_ULP_CLASS_HID_669d,
+ [602] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e7d1,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 15035804672,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9794,20 +13362,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
},
- [459] = {
- .class_hid = BNXT_ULP_CLASS_HID_0e39,
+ [603] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8e1b,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 17181182976,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9820,16 +13388,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [460] = {
- .class_hid = BNXT_ULP_CLASS_HID_20a1,
+ [604] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a083,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 17181191168,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9842,17 +13410,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [461] = {
- .class_hid = BNXT_ULP_CLASS_HID_1dfd,
+ [605] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ddff,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 17183280128,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9865,17 +13433,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [462] = {
- .class_hid = BNXT_ULP_CLASS_HID_4e65,
+ [606] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ce67,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 17183288320,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9888,18 +13456,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [463] = {
- .class_hid = BNXT_ULP_CLASS_HID_16f9,
+ [607] = {
+ .class_hid = BNXT_ULP_CLASS_HID_96db,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 19328666624,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9912,17 +13480,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [464] = {
- .class_hid = BNXT_ULP_CLASS_HID_4661,
+ [608] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c753,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 19328674816,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9935,18 +13503,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [465] = {
- .class_hid = BNXT_ULP_CLASS_HID_24bd,
+ [609] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e5bf,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 19330763776,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9959,18 +13527,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [466] = {
- .class_hid = BNXT_ULP_CLASS_HID_5625,
+ [610] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d637,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 19330771968,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -9983,19 +13551,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [467] = {
- .class_hid = BNXT_ULP_CLASS_HID_02b9,
+ [611] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8233,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 21476150272,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10008,17 +13576,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [468] = {
- .class_hid = BNXT_ULP_CLASS_HID_34a1,
+ [612] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b4a3,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 21476158464,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10031,18 +13599,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [469] = {
- .class_hid = BNXT_ULP_CLASS_HID_11bd,
+ [613] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d197,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 21478247424,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10055,18 +13623,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [470] = {
- .class_hid = BNXT_ULP_CLASS_HID_42a5,
+ [614] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c207,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 21478255616,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10079,19 +13647,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [471] = {
- .class_hid = BNXT_ULP_CLASS_HID_2af9,
+ [615] = {
+ .class_hid = BNXT_ULP_CLASS_HID_aaf3,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 23623633920,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10104,18 +13672,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [472] = {
- .class_hid = BNXT_ULP_CLASS_HID_5ae1,
+ [616] = {
+ .class_hid = BNXT_ULP_CLASS_HID_db73,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 23623642112,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10128,19 +13696,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [473] = {
- .class_hid = BNXT_ULP_CLASS_HID_38fd,
+ [617] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f857,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 23625731072,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10153,19 +13721,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [474] = {
- .class_hid = BNXT_ULP_CLASS_HID_6ae5,
+ [618] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ead7,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 23625739264,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10178,20 +13746,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [475] = {
- .class_hid = BNXT_ULP_CLASS_HID_0829,
+ [619] = {
+ .class_hid = BNXT_ULP_CLASS_HID_882b,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 25771117568,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10204,17 +13772,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [476] = {
- .class_hid = BNXT_ULP_CLASS_HID_3ab1,
+ [620] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ba93,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 25771125760,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10227,18 +13795,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [477] = {
- .class_hid = BNXT_ULP_CLASS_HID_17ad,
+ [621] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d78b,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 25773214720,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10251,18 +13819,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [478] = {
- .class_hid = BNXT_ULP_CLASS_HID_4835,
+ [622] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c873,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 25773222912,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10275,19 +13843,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [479] = {
- .class_hid = BNXT_ULP_CLASS_HID_10a9,
+ [623] = {
+ .class_hid = BNXT_ULP_CLASS_HID_90fb,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 27918601216,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10300,18 +13868,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [480] = {
- .class_hid = BNXT_ULP_CLASS_HID_4031,
+ [624] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c153,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 27918609408,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10324,19 +13892,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [481] = {
- .class_hid = BNXT_ULP_CLASS_HID_3e2d,
+ [625] = {
+ .class_hid = BNXT_ULP_CLASS_HID_fe5b,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 27920698368,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10349,19 +13917,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [482] = {
- .class_hid = BNXT_ULP_CLASS_HID_5035,
+ [626] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d033,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 27920706560,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10374,20 +13942,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [483] = {
- .class_hid = BNXT_ULP_CLASS_HID_1ca9,
+ [627] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9cc3,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 30066084864,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10400,18 +13968,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [484] = {
- .class_hid = BNXT_ULP_CLASS_HID_4eb1,
+ [628] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ceb3,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 30066093056,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10424,19 +13992,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [485] = {
- .class_hid = BNXT_ULP_CLASS_HID_2bad,
+ [629] = {
+ .class_hid = BNXT_ULP_CLASS_HID_eba3,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 30068182016,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10449,19 +14017,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [486] = {
- .class_hid = BNXT_ULP_CLASS_HID_5cb5,
+ [630] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dc13,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 30068190208,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10474,20 +14042,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [487] = {
- .class_hid = BNXT_ULP_CLASS_HID_24a9,
+ [631] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a493,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 32213568512,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10500,19 +14068,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [488] = {
- .class_hid = BNXT_ULP_CLASS_HID_54b1,
+ [632] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d573,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 32213576704,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10525,20 +14093,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [489] = {
- .class_hid = BNXT_ULP_CLASS_HID_32ad,
+ [633] = {
+ .class_hid = BNXT_ULP_CLASS_HID_f273,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 32215665664,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10551,20 +14119,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [490] = {
- .class_hid = BNXT_ULP_CLASS_HID_0ca9,
+ [634] = {
+ .class_hid = BNXT_ULP_CLASS_HID_cdb3,
.class_tid = 2,
- .hdr_sig_id = 3,
+ .hdr_sig_id = 6,
.flow_sig_id = 32215673856,
.flow_pattern_id = 1,
.app_sig = 0,
@@ -10577,21 +14145,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
},
- [491] = {
- .class_hid = BNXT_ULP_CLASS_HID_7f35,
+ [635] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ff35,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 1313792,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10604,15 +14172,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC }
},
- [492] = {
- .class_hid = BNXT_ULP_CLASS_HID_34f1,
+ [636] = {
+ .class_hid = BNXT_ULP_CLASS_HID_b4f1,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 1321984,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10625,16 +14193,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC }
},
- [493] = {
- .class_hid = BNXT_ULP_CLASS_HID_179d,
+ [637] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d79d,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 3410944,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10647,16 +14215,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC }
},
- [494] = {
- .class_hid = BNXT_ULP_CLASS_HID_2615,
+ [638] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e615,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 3419136,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10669,17 +14237,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC }
},
- [495] = {
- .class_hid = BNXT_ULP_CLASS_HID_0fb9,
+ [639] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8ea9,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 2148797440,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10692,16 +14260,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
},
- [496] = {
- .class_hid = BNXT_ULP_CLASS_HID_5d31,
+ [640] = {
+ .class_hid = BNXT_ULP_CLASS_HID_dd21,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 2148805632,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10714,17 +14282,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
},
- [497] = {
- .class_hid = BNXT_ULP_CLASS_HID_3fdd,
+ [641] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ffcd,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 2150894592,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10737,17 +14305,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
},
- [498] = {
- .class_hid = BNXT_ULP_CLASS_HID_4f55,
+ [642] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ce45,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 2150902784,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10760,18 +14328,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
},
- [499] = {
- .class_hid = BNXT_ULP_CLASS_HID_12d9,
+ [643] = {
+ .class_hid = BNXT_ULP_CLASS_HID_9259,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 4296281088,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10784,16 +14352,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [500] = {
- .class_hid = BNXT_ULP_CLASS_HID_20d1,
+ [644] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a0d9,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 4296289280,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10806,17 +14374,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [501] = {
- .class_hid = BNXT_ULP_CLASS_HID_03fd,
+ [645] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c3fd,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 4298378240,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10829,17 +14397,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [502] = {
- .class_hid = BNXT_ULP_CLASS_HID_52f5,
+ [646] = {
+ .class_hid = BNXT_ULP_CLASS_HID_d27d,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 4298386432,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10852,18 +14420,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [503] = {
- .class_hid = BNXT_ULP_CLASS_HID_3b99,
+ [647] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ba89,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 6443764736,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10876,17 +14444,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [504] = {
- .class_hid = BNXT_ULP_CLASS_HID_4991,
+ [648] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c909,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 6443772928,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10899,18 +14467,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [505] = {
- .class_hid = BNXT_ULP_CLASS_HID_2dbd,
+ [649] = {
+ .class_hid = BNXT_ULP_CLASS_HID_ec2d,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 6445861888,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10923,18 +14491,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [506] = {
- .class_hid = BNXT_ULP_CLASS_HID_7bb5,
+ [650] = {
+ .class_hid = BNXT_ULP_CLASS_HID_faad,
.class_tid = 2,
- .hdr_sig_id = 4,
+ .hdr_sig_id = 7,
.flow_sig_id = 6445870080,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -10947,16 +14515,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
},
- [507] = {
+ [651] = {
.class_hid = BNXT_ULP_CLASS_HID_34c6,
.class_tid = 3,
.hdr_sig_id = 0,
@@ -10971,7 +14539,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [508] = {
+ [652] = {
.class_hid = BNXT_ULP_CLASS_HID_0c22,
.class_tid = 3,
.hdr_sig_id = 0,
@@ -10987,7 +14555,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [509] = {
+ [653] = {
.class_hid = BNXT_ULP_CLASS_HID_1cbe,
.class_tid = 3,
.hdr_sig_id = 0,
@@ -11003,7 +14571,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [510] = {
+ [654] = {
.class_hid = BNXT_ULP_CLASS_HID_179a,
.class_tid = 3,
.hdr_sig_id = 0,
@@ -11020,7 +14588,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [511] = {
+ [655] = {
.class_hid = BNXT_ULP_CLASS_HID_59be,
.class_tid = 3,
.hdr_sig_id = 1,
@@ -11035,7 +14603,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [512] = {
+ [656] = {
.class_hid = BNXT_ULP_CLASS_HID_515a,
.class_tid = 3,
.hdr_sig_id = 1,
@@ -11051,7 +14619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [513] = {
+ [657] = {
.class_hid = BNXT_ULP_CLASS_HID_1c72,
.class_tid = 3,
.hdr_sig_id = 1,
@@ -11067,7 +14635,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [514] = {
+ [658] = {
.class_hid = BNXT_ULP_CLASS_HID_171e,
.class_tid = 3,
.hdr_sig_id = 1,
@@ -11084,7 +14652,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [515] = {
+ [659] = {
.class_hid = BNXT_ULP_CLASS_HID_19c8,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11100,7 +14668,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [516] = {
+ [660] = {
.class_hid = BNXT_ULP_CLASS_HID_112c,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11117,7 +14685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [517] = {
+ [661] = {
.class_hid = BNXT_ULP_CLASS_HID_4d68,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11134,7 +14702,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [518] = {
+ [662] = {
.class_hid = BNXT_ULP_CLASS_HID_444c,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11152,7 +14720,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [519] = {
+ [663] = {
.class_hid = BNXT_ULP_CLASS_HID_0e8c,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11169,7 +14737,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [520] = {
+ [664] = {
.class_hid = BNXT_ULP_CLASS_HID_09e0,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11187,7 +14755,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [521] = {
+ [665] = {
.class_hid = BNXT_ULP_CLASS_HID_1af0,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11205,7 +14773,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [522] = {
+ [666] = {
.class_hid = BNXT_ULP_CLASS_HID_15d4,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -11224,7 +14792,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [523] = {
+ [667] = {
.class_hid = BNXT_ULP_CLASS_HID_1dd0,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11240,7 +14808,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [524] = {
+ [668] = {
.class_hid = BNXT_ULP_CLASS_HID_14f4,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11257,7 +14825,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [525] = {
+ [669] = {
.class_hid = BNXT_ULP_CLASS_HID_70b0,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11274,7 +14842,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [526] = {
+ [670] = {
.class_hid = BNXT_ULP_CLASS_HID_4854,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11292,7 +14860,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [527] = {
+ [671] = {
.class_hid = BNXT_ULP_CLASS_HID_3dd4,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11309,7 +14877,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [528] = {
+ [672] = {
.class_hid = BNXT_ULP_CLASS_HID_34f8,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11327,7 +14895,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [529] = {
+ [673] = {
.class_hid = BNXT_ULP_CLASS_HID_09e8,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11345,7 +14913,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [530] = {
+ [674] = {
.class_hid = BNXT_ULP_CLASS_HID_008c,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -11364,7 +14932,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [531] = {
+ [675] = {
.class_hid = BNXT_ULP_CLASS_HID_34e6,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11380,7 +14948,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [532] = {
+ [676] = {
.class_hid = BNXT_ULP_CLASS_HID_0c02,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11397,7 +14965,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [533] = {
+ [677] = {
.class_hid = BNXT_ULP_CLASS_HID_1c9e,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11414,7 +14982,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [534] = {
+ [678] = {
.class_hid = BNXT_ULP_CLASS_HID_17ba,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11432,7 +15000,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [535] = {
+ [679] = {
.class_hid = BNXT_ULP_CLASS_HID_429e,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11449,7 +15017,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [536] = {
+ [680] = {
.class_hid = BNXT_ULP_CLASS_HID_5dba,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11467,7 +15035,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [537] = {
+ [681] = {
.class_hid = BNXT_ULP_CLASS_HID_2a16,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11485,7 +15053,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [538] = {
+ [682] = {
.class_hid = BNXT_ULP_CLASS_HID_2532,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11504,7 +15072,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [539] = {
+ [683] = {
.class_hid = BNXT_ULP_CLASS_HID_2da2,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11521,7 +15089,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [540] = {
+ [684] = {
.class_hid = BNXT_ULP_CLASS_HID_24fe,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11539,7 +15107,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [541] = {
+ [685] = {
.class_hid = BNXT_ULP_CLASS_HID_355a,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11557,7 +15125,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [542] = {
+ [686] = {
.class_hid = BNXT_ULP_CLASS_HID_0c76,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11576,7 +15144,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [543] = {
+ [687] = {
.class_hid = BNXT_ULP_CLASS_HID_13e6,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11594,7 +15162,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [544] = {
+ [688] = {
.class_hid = BNXT_ULP_CLASS_HID_7276,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11613,7 +15181,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [545] = {
+ [689] = {
.class_hid = BNXT_ULP_CLASS_HID_42d2,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11632,7 +15200,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [546] = {
+ [690] = {
.class_hid = BNXT_ULP_CLASS_HID_5dee,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -11652,7 +15220,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [547] = {
+ [691] = {
.class_hid = BNXT_ULP_CLASS_HID_59de,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11668,7 +15236,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [548] = {
+ [692] = {
.class_hid = BNXT_ULP_CLASS_HID_513a,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11685,7 +15253,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [549] = {
+ [693] = {
.class_hid = BNXT_ULP_CLASS_HID_1c12,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11702,7 +15270,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [550] = {
+ [694] = {
.class_hid = BNXT_ULP_CLASS_HID_177e,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11720,7 +15288,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [551] = {
+ [695] = {
.class_hid = BNXT_ULP_CLASS_HID_0e92,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11737,7 +15305,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [552] = {
+ [696] = {
.class_hid = BNXT_ULP_CLASS_HID_09fe,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11755,7 +15323,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [553] = {
+ [697] = {
.class_hid = BNXT_ULP_CLASS_HID_5c1a,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11773,7 +15341,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [554] = {
+ [698] = {
.class_hid = BNXT_ULP_CLASS_HID_5746,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11792,7 +15360,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [555] = {
+ [699] = {
.class_hid = BNXT_ULP_CLASS_HID_79da,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11809,7 +15377,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [556] = {
+ [700] = {
.class_hid = BNXT_ULP_CLASS_HID_7106,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11827,7 +15395,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [557] = {
+ [701] = {
.class_hid = BNXT_ULP_CLASS_HID_3c1e,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11845,7 +15413,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [558] = {
+ [702] = {
.class_hid = BNXT_ULP_CLASS_HID_377a,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11864,7 +15432,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [559] = {
+ [703] = {
.class_hid = BNXT_ULP_CLASS_HID_2e9e,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11882,7 +15450,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [560] = {
+ [704] = {
.class_hid = BNXT_ULP_CLASS_HID_29fa,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11901,7 +15469,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [561] = {
+ [705] = {
.class_hid = BNXT_ULP_CLASS_HID_14d2,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11920,7 +15488,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [562] = {
+ [706] = {
.class_hid = BNXT_ULP_CLASS_HID_7742,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -11940,7 +15508,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [563] = {
+ [707] = {
.class_hid = BNXT_ULP_CLASS_HID_3706,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -11956,7 +15524,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [564] = {
+ [708] = {
.class_hid = BNXT_ULP_CLASS_HID_0fe2,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -11973,7 +15541,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [565] = {
+ [709] = {
.class_hid = BNXT_ULP_CLASS_HID_1f7e,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -11990,7 +15558,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [566] = {
+ [710] = {
.class_hid = BNXT_ULP_CLASS_HID_145a,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12008,7 +15576,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [567] = {
+ [711] = {
.class_hid = BNXT_ULP_CLASS_HID_417e,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12025,7 +15593,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [568] = {
+ [712] = {
.class_hid = BNXT_ULP_CLASS_HID_5e5a,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12043,7 +15611,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [569] = {
+ [713] = {
.class_hid = BNXT_ULP_CLASS_HID_29f6,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12061,7 +15629,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [570] = {
+ [714] = {
.class_hid = BNXT_ULP_CLASS_HID_26d2,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12080,7 +15648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [571] = {
+ [715] = {
.class_hid = BNXT_ULP_CLASS_HID_2e42,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12097,7 +15665,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [572] = {
+ [716] = {
.class_hid = BNXT_ULP_CLASS_HID_271e,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12115,7 +15683,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [573] = {
+ [717] = {
.class_hid = BNXT_ULP_CLASS_HID_36ba,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12133,7 +15701,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [574] = {
+ [718] = {
.class_hid = BNXT_ULP_CLASS_HID_0f96,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12152,7 +15720,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [575] = {
+ [719] = {
.class_hid = BNXT_ULP_CLASS_HID_1006,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12170,7 +15738,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [576] = {
+ [720] = {
.class_hid = BNXT_ULP_CLASS_HID_7196,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12189,7 +15757,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [577] = {
+ [721] = {
.class_hid = BNXT_ULP_CLASS_HID_4132,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12208,7 +15776,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [578] = {
+ [722] = {
.class_hid = BNXT_ULP_CLASS_HID_5e0e,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -12228,7 +15796,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [579] = {
+ [723] = {
.class_hid = BNXT_ULP_CLASS_HID_59fe,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12244,7 +15812,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [580] = {
+ [724] = {
.class_hid = BNXT_ULP_CLASS_HID_511a,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12261,7 +15829,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [581] = {
+ [725] = {
.class_hid = BNXT_ULP_CLASS_HID_1c32,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12278,7 +15846,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [582] = {
+ [726] = {
.class_hid = BNXT_ULP_CLASS_HID_175e,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12296,7 +15864,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [583] = {
+ [727] = {
.class_hid = BNXT_ULP_CLASS_HID_0eb2,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12313,7 +15881,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [584] = {
+ [728] = {
.class_hid = BNXT_ULP_CLASS_HID_09de,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12331,7 +15899,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [585] = {
+ [729] = {
.class_hid = BNXT_ULP_CLASS_HID_5c3a,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12349,7 +15917,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [586] = {
+ [730] = {
.class_hid = BNXT_ULP_CLASS_HID_5766,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12368,7 +15936,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [587] = {
+ [731] = {
.class_hid = BNXT_ULP_CLASS_HID_79fa,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12385,7 +15953,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [588] = {
+ [732] = {
.class_hid = BNXT_ULP_CLASS_HID_7126,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12403,7 +15971,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [589] = {
+ [733] = {
.class_hid = BNXT_ULP_CLASS_HID_3c3e,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12421,7 +15989,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [590] = {
+ [734] = {
.class_hid = BNXT_ULP_CLASS_HID_375a,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12440,7 +16008,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [591] = {
+ [735] = {
.class_hid = BNXT_ULP_CLASS_HID_2ebe,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12458,7 +16026,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [592] = {
+ [736] = {
.class_hid = BNXT_ULP_CLASS_HID_29da,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12477,7 +16045,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [593] = {
+ [737] = {
.class_hid = BNXT_ULP_CLASS_HID_14f2,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12496,7 +16064,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [594] = {
+ [738] = {
.class_hid = BNXT_ULP_CLASS_HID_7762,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -12516,7 +16084,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [595] = {
+ [739] = {
.class_hid = BNXT_ULP_CLASS_HID_19e8,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12533,7 +16101,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [596] = {
+ [740] = {
.class_hid = BNXT_ULP_CLASS_HID_110c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12551,7 +16119,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [597] = {
+ [741] = {
.class_hid = BNXT_ULP_CLASS_HID_4d48,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12569,7 +16137,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [598] = {
+ [742] = {
.class_hid = BNXT_ULP_CLASS_HID_446c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12588,7 +16156,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [599] = {
+ [743] = {
.class_hid = BNXT_ULP_CLASS_HID_0eac,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12606,7 +16174,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [600] = {
+ [744] = {
.class_hid = BNXT_ULP_CLASS_HID_09c0,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12625,7 +16193,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [601] = {
+ [745] = {
.class_hid = BNXT_ULP_CLASS_HID_1ad0,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12644,7 +16212,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [602] = {
+ [746] = {
.class_hid = BNXT_ULP_CLASS_HID_15f4,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12664,7 +16232,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [603] = {
+ [747] = {
.class_hid = BNXT_ULP_CLASS_HID_39ec,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12682,7 +16250,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [604] = {
+ [748] = {
.class_hid = BNXT_ULP_CLASS_HID_3100,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12701,7 +16269,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [605] = {
+ [749] = {
.class_hid = BNXT_ULP_CLASS_HID_0210,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12720,7 +16288,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [606] = {
+ [750] = {
.class_hid = BNXT_ULP_CLASS_HID_1d34,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12740,7 +16308,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [607] = {
+ [751] = {
.class_hid = BNXT_ULP_CLASS_HID_2ea0,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12759,7 +16327,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [608] = {
+ [752] = {
.class_hid = BNXT_ULP_CLASS_HID_29c4,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12779,7 +16347,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [609] = {
+ [753] = {
.class_hid = BNXT_ULP_CLASS_HID_3ad4,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12799,7 +16367,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [610] = {
+ [754] = {
.class_hid = BNXT_ULP_CLASS_HID_35e8,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12820,7 +16388,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [611] = {
+ [755] = {
.class_hid = BNXT_ULP_CLASS_HID_5d80,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12838,7 +16406,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [612] = {
+ [756] = {
.class_hid = BNXT_ULP_CLASS_HID_54a4,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12857,7 +16425,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [613] = {
+ [757] = {
.class_hid = BNXT_ULP_CLASS_HID_29b4,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12876,7 +16444,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [614] = {
+ [758] = {
.class_hid = BNXT_ULP_CLASS_HID_20c8,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12896,7 +16464,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [615] = {
+ [759] = {
.class_hid = BNXT_ULP_CLASS_HID_7244,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12915,7 +16483,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [616] = {
+ [760] = {
.class_hid = BNXT_ULP_CLASS_HID_4d98,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12935,7 +16503,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [617] = {
+ [761] = {
.class_hid = BNXT_ULP_CLASS_HID_5e68,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12955,7 +16523,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [618] = {
+ [762] = {
.class_hid = BNXT_ULP_CLASS_HID_598c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12976,7 +16544,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [619] = {
+ [763] = {
.class_hid = BNXT_ULP_CLASS_HID_1248,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -12995,7 +16563,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [620] = {
+ [764] = {
.class_hid = BNXT_ULP_CLASS_HID_74d8,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -13015,7 +16583,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [621] = {
+ [765] = {
.class_hid = BNXT_ULP_CLASS_HID_49a8,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -13035,7 +16603,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [622] = {
+ [766] = {
.class_hid = BNXT_ULP_CLASS_HID_40cc,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -13056,7 +16624,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [623] = {
+ [767] = {
.class_hid = BNXT_ULP_CLASS_HID_0b0c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -13076,7 +16644,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [624] = {
+ [768] = {
.class_hid = BNXT_ULP_CLASS_HID_0220,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -13097,7 +16665,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [625] = {
+ [769] = {
.class_hid = BNXT_ULP_CLASS_HID_1730,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -13118,7 +16686,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [626] = {
+ [770] = {
.class_hid = BNXT_ULP_CLASS_HID_7980,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -13140,7 +16708,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [627] = {
+ [771] = {
.class_hid = BNXT_ULP_CLASS_HID_1db0,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13157,7 +16725,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [628] = {
+ [772] = {
.class_hid = BNXT_ULP_CLASS_HID_1494,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13175,7 +16743,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [629] = {
+ [773] = {
.class_hid = BNXT_ULP_CLASS_HID_70d0,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13193,7 +16761,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [630] = {
+ [774] = {
.class_hid = BNXT_ULP_CLASS_HID_4834,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13212,7 +16780,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [631] = {
+ [775] = {
.class_hid = BNXT_ULP_CLASS_HID_3db4,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13230,7 +16798,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [632] = {
+ [776] = {
.class_hid = BNXT_ULP_CLASS_HID_3498,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13249,7 +16817,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [633] = {
+ [777] = {
.class_hid = BNXT_ULP_CLASS_HID_0988,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13268,7 +16836,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [634] = {
+ [778] = {
.class_hid = BNXT_ULP_CLASS_HID_00ec,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13288,7 +16856,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [635] = {
+ [779] = {
.class_hid = BNXT_ULP_CLASS_HID_3f44,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13306,7 +16874,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [636] = {
+ [780] = {
.class_hid = BNXT_ULP_CLASS_HID_36a8,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13325,7 +16893,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [637] = {
+ [781] = {
.class_hid = BNXT_ULP_CLASS_HID_0b58,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13344,7 +16912,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [638] = {
+ [782] = {
.class_hid = BNXT_ULP_CLASS_HID_02bc,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13364,7 +16932,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [639] = {
+ [783] = {
.class_hid = BNXT_ULP_CLASS_HID_5f48,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13383,7 +16951,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [640] = {
+ [784] = {
.class_hid = BNXT_ULP_CLASS_HID_56ac,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13403,7 +16971,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [641] = {
+ [785] = {
.class_hid = BNXT_ULP_CLASS_HID_2b5c,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13423,7 +16991,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [642] = {
+ [786] = {
.class_hid = BNXT_ULP_CLASS_HID_2280,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13444,7 +17012,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [643] = {
+ [787] = {
.class_hid = BNXT_ULP_CLASS_HID_4000,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13462,7 +17030,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [644] = {
+ [788] = {
.class_hid = BNXT_ULP_CLASS_HID_5b64,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13481,7 +17049,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [645] = {
+ [789] = {
.class_hid = BNXT_ULP_CLASS_HID_2c14,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13500,7 +17068,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [646] = {
+ [790] = {
.class_hid = BNXT_ULP_CLASS_HID_2778,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13520,7 +17088,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [647] = {
+ [791] = {
.class_hid = BNXT_ULP_CLASS_HID_18f8,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13539,7 +17107,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [648] = {
+ [792] = {
.class_hid = BNXT_ULP_CLASS_HID_13dc,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13559,7 +17127,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [649] = {
+ [793] = {
.class_hid = BNXT_ULP_CLASS_HID_4c18,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13579,7 +17147,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [650] = {
+ [794] = {
.class_hid = BNXT_ULP_CLASS_HID_477c,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13600,7 +17168,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [651] = {
+ [795] = {
.class_hid = BNXT_ULP_CLASS_HID_1a88,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13619,7 +17187,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [652] = {
+ [796] = {
.class_hid = BNXT_ULP_CLASS_HID_15ec,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13639,7 +17207,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [653] = {
+ [797] = {
.class_hid = BNXT_ULP_CLASS_HID_4e28,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13659,7 +17227,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [654] = {
+ [798] = {
.class_hid = BNXT_ULP_CLASS_HID_490c,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13680,7 +17248,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [655] = {
+ [799] = {
.class_hid = BNXT_ULP_CLASS_HID_3a8c,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13700,7 +17268,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [656] = {
+ [800] = {
.class_hid = BNXT_ULP_CLASS_HID_35f0,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13721,7 +17289,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [657] = {
+ [801] = {
.class_hid = BNXT_ULP_CLASS_HID_06e0,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13742,7 +17310,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [658] = {
+ [802] = {
.class_hid = BNXT_ULP_CLASS_HID_01c4,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -13764,7 +17332,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [659] = {
+ [803] = {
.class_hid = BNXT_ULP_CLASS_HID_1a08,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13781,7 +17349,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [660] = {
+ [804] = {
.class_hid = BNXT_ULP_CLASS_HID_12ec,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13799,7 +17367,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [661] = {
+ [805] = {
.class_hid = BNXT_ULP_CLASS_HID_4ea8,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13817,7 +17385,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [662] = {
+ [806] = {
.class_hid = BNXT_ULP_CLASS_HID_478c,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13836,7 +17404,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [663] = {
+ [807] = {
.class_hid = BNXT_ULP_CLASS_HID_0d4c,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13854,7 +17422,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [664] = {
+ [808] = {
.class_hid = BNXT_ULP_CLASS_HID_0a20,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13873,7 +17441,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [665] = {
+ [809] = {
.class_hid = BNXT_ULP_CLASS_HID_1930,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13892,7 +17460,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [666] = {
+ [810] = {
.class_hid = BNXT_ULP_CLASS_HID_1614,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13912,7 +17480,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [667] = {
+ [811] = {
.class_hid = BNXT_ULP_CLASS_HID_3a0c,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13930,7 +17498,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [668] = {
+ [812] = {
.class_hid = BNXT_ULP_CLASS_HID_32e0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13949,7 +17517,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [669] = {
+ [813] = {
.class_hid = BNXT_ULP_CLASS_HID_01f0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13968,7 +17536,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [670] = {
+ [814] = {
.class_hid = BNXT_ULP_CLASS_HID_1ed4,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -13988,7 +17556,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [671] = {
+ [815] = {
.class_hid = BNXT_ULP_CLASS_HID_2d40,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14007,7 +17575,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [672] = {
+ [816] = {
.class_hid = BNXT_ULP_CLASS_HID_2a24,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14027,7 +17595,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [673] = {
+ [817] = {
.class_hid = BNXT_ULP_CLASS_HID_3934,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14047,7 +17615,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [674] = {
+ [818] = {
.class_hid = BNXT_ULP_CLASS_HID_3608,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14068,7 +17636,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [675] = {
+ [819] = {
.class_hid = BNXT_ULP_CLASS_HID_5e60,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14086,7 +17654,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [676] = {
+ [820] = {
.class_hid = BNXT_ULP_CLASS_HID_5744,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14105,7 +17673,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [677] = {
+ [821] = {
.class_hid = BNXT_ULP_CLASS_HID_2a54,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14124,7 +17692,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [678] = {
+ [822] = {
.class_hid = BNXT_ULP_CLASS_HID_2328,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14144,7 +17712,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [679] = {
+ [823] = {
.class_hid = BNXT_ULP_CLASS_HID_71a4,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14163,7 +17731,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [680] = {
+ [824] = {
.class_hid = BNXT_ULP_CLASS_HID_4e78,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14183,7 +17751,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [681] = {
+ [825] = {
.class_hid = BNXT_ULP_CLASS_HID_5d88,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14203,7 +17771,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [682] = {
+ [826] = {
.class_hid = BNXT_ULP_CLASS_HID_5a6c,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14224,7 +17792,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [683] = {
+ [827] = {
.class_hid = BNXT_ULP_CLASS_HID_11a8,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14243,7 +17811,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [684] = {
+ [828] = {
.class_hid = BNXT_ULP_CLASS_HID_7738,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14263,7 +17831,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [685] = {
+ [829] = {
.class_hid = BNXT_ULP_CLASS_HID_4a48,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14283,7 +17851,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [686] = {
+ [830] = {
.class_hid = BNXT_ULP_CLASS_HID_432c,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14304,7 +17872,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [687] = {
+ [831] = {
.class_hid = BNXT_ULP_CLASS_HID_08ec,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14324,7 +17892,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [688] = {
+ [832] = {
.class_hid = BNXT_ULP_CLASS_HID_01c0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14345,7 +17913,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [689] = {
+ [833] = {
.class_hid = BNXT_ULP_CLASS_HID_14d0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14366,7 +17934,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [690] = {
+ [834] = {
.class_hid = BNXT_ULP_CLASS_HID_7a60,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -14388,7 +17956,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [691] = {
+ [835] = {
.class_hid = BNXT_ULP_CLASS_HID_1d90,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14405,7 +17973,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [692] = {
+ [836] = {
.class_hid = BNXT_ULP_CLASS_HID_14b4,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14423,7 +17991,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [693] = {
+ [837] = {
.class_hid = BNXT_ULP_CLASS_HID_70f0,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14441,7 +18009,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [694] = {
+ [838] = {
.class_hid = BNXT_ULP_CLASS_HID_4814,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14460,7 +18028,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [695] = {
+ [839] = {
.class_hid = BNXT_ULP_CLASS_HID_3d94,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14478,7 +18046,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [696] = {
+ [840] = {
.class_hid = BNXT_ULP_CLASS_HID_34b8,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14497,7 +18065,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [697] = {
+ [841] = {
.class_hid = BNXT_ULP_CLASS_HID_09a8,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14516,7 +18084,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [698] = {
+ [842] = {
.class_hid = BNXT_ULP_CLASS_HID_00cc,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14536,7 +18104,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [699] = {
+ [843] = {
.class_hid = BNXT_ULP_CLASS_HID_3f64,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14554,7 +18122,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [700] = {
+ [844] = {
.class_hid = BNXT_ULP_CLASS_HID_3688,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14573,7 +18141,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [701] = {
+ [845] = {
.class_hid = BNXT_ULP_CLASS_HID_0b78,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14592,7 +18160,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [702] = {
+ [846] = {
.class_hid = BNXT_ULP_CLASS_HID_029c,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14612,7 +18180,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [703] = {
+ [847] = {
.class_hid = BNXT_ULP_CLASS_HID_5f68,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14631,7 +18199,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [704] = {
+ [848] = {
.class_hid = BNXT_ULP_CLASS_HID_568c,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14651,7 +18219,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [705] = {
+ [849] = {
.class_hid = BNXT_ULP_CLASS_HID_2b7c,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14671,7 +18239,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [706] = {
+ [850] = {
.class_hid = BNXT_ULP_CLASS_HID_22a0,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14692,7 +18260,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [707] = {
+ [851] = {
.class_hid = BNXT_ULP_CLASS_HID_4020,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14710,7 +18278,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [708] = {
+ [852] = {
.class_hid = BNXT_ULP_CLASS_HID_5b44,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14729,7 +18297,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [709] = {
+ [853] = {
.class_hid = BNXT_ULP_CLASS_HID_2c34,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14748,7 +18316,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [710] = {
+ [854] = {
.class_hid = BNXT_ULP_CLASS_HID_2758,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14768,7 +18336,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [711] = {
+ [855] = {
.class_hid = BNXT_ULP_CLASS_HID_18d8,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14787,7 +18355,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [712] = {
+ [856] = {
.class_hid = BNXT_ULP_CLASS_HID_13fc,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14807,7 +18375,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [713] = {
+ [857] = {
.class_hid = BNXT_ULP_CLASS_HID_4c38,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14827,7 +18395,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [714] = {
+ [858] = {
.class_hid = BNXT_ULP_CLASS_HID_475c,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14848,7 +18416,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [715] = {
+ [859] = {
.class_hid = BNXT_ULP_CLASS_HID_1aa8,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14867,7 +18435,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [716] = {
+ [860] = {
.class_hid = BNXT_ULP_CLASS_HID_15cc,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14887,7 +18455,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [717] = {
+ [861] = {
.class_hid = BNXT_ULP_CLASS_HID_4e08,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14907,7 +18475,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [718] = {
+ [862] = {
.class_hid = BNXT_ULP_CLASS_HID_492c,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14928,7 +18496,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [719] = {
+ [863] = {
.class_hid = BNXT_ULP_CLASS_HID_3aac,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14948,7 +18516,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [720] = {
+ [864] = {
.class_hid = BNXT_ULP_CLASS_HID_35d0,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14969,7 +18537,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [721] = {
+ [865] = {
.class_hid = BNXT_ULP_CLASS_HID_06c0,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -14990,7 +18558,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [722] = {
+ [866] = {
.class_hid = BNXT_ULP_CLASS_HID_01e4,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -15012,7 +18580,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [723] = {
+ [867] = {
.class_hid = BNXT_ULP_CLASS_HID_4d32,
.class_tid = 3,
.hdr_sig_id = 0,
@@ -15026,7 +18594,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [724] = {
+ [868] = {
.class_hid = BNXT_ULP_CLASS_HID_54aa,
.class_tid = 3,
.hdr_sig_id = 0,
@@ -15041,7 +18609,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [725] = {
+ [869] = {
.class_hid = BNXT_ULP_CLASS_HID_0686,
.class_tid = 3,
.hdr_sig_id = 1,
@@ -15055,7 +18623,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [726] = {
+ [870] = {
.class_hid = BNXT_ULP_CLASS_HID_540e,
.class_tid = 3,
.hdr_sig_id = 1,
@@ -15070,7 +18638,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [727] = {
+ [871] = {
.class_hid = BNXT_ULP_CLASS_HID_2e3c,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -15085,7 +18653,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [728] = {
+ [872] = {
.class_hid = BNXT_ULP_CLASS_HID_3a20,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -15101,7 +18669,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [729] = {
+ [873] = {
.class_hid = BNXT_ULP_CLASS_HID_46f0,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -15117,7 +18685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [730] = {
+ [874] = {
.class_hid = BNXT_ULP_CLASS_HID_52e4,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -15134,7 +18702,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [731] = {
+ [875] = {
.class_hid = BNXT_ULP_CLASS_HID_55e4,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -15149,7 +18717,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [732] = {
+ [876] = {
.class_hid = BNXT_ULP_CLASS_HID_21f8,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -15165,7 +18733,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [733] = {
+ [877] = {
.class_hid = BNXT_ULP_CLASS_HID_75e8,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -15181,7 +18749,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [734] = {
+ [878] = {
.class_hid = BNXT_ULP_CLASS_HID_41fc,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -15198,7 +18766,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [735] = {
+ [879] = {
.class_hid = BNXT_ULP_CLASS_HID_4d12,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15213,7 +18781,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [736] = {
+ [880] = {
.class_hid = BNXT_ULP_CLASS_HID_548a,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15229,7 +18797,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [737] = {
+ [881] = {
.class_hid = BNXT_ULP_CLASS_HID_3356,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15245,7 +18813,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [738] = {
+ [882] = {
.class_hid = BNXT_ULP_CLASS_HID_1ace,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15262,7 +18830,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [739] = {
+ [883] = {
.class_hid = BNXT_ULP_CLASS_HID_1a9a,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15278,7 +18846,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [740] = {
+ [884] = {
.class_hid = BNXT_ULP_CLASS_HID_4d46,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15295,7 +18863,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [741] = {
+ [885] = {
.class_hid = BNXT_ULP_CLASS_HID_2812,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15312,7 +18880,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [742] = {
+ [886] = {
.class_hid = BNXT_ULP_CLASS_HID_338a,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -15330,7 +18898,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [743] = {
+ [887] = {
.class_hid = BNXT_ULP_CLASS_HID_06e6,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15345,7 +18913,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [744] = {
+ [888] = {
.class_hid = BNXT_ULP_CLASS_HID_546e,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15361,7 +18929,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [745] = {
+ [889] = {
.class_hid = BNXT_ULP_CLASS_HID_46ee,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15377,7 +18945,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [746] = {
+ [890] = {
.class_hid = BNXT_ULP_CLASS_HID_0d22,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15394,7 +18962,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [747] = {
+ [891] = {
.class_hid = BNXT_ULP_CLASS_HID_26e2,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15410,7 +18978,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [748] = {
+ [892] = {
.class_hid = BNXT_ULP_CLASS_HID_746a,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15427,7 +18995,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [749] = {
+ [893] = {
.class_hid = BNXT_ULP_CLASS_HID_1fa6,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15444,7 +19012,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [750] = {
+ [894] = {
.class_hid = BNXT_ULP_CLASS_HID_2d2e,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -15462,7 +19030,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [751] = {
+ [895] = {
.class_hid = BNXT_ULP_CLASS_HID_4ef2,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15477,7 +19045,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [752] = {
+ [896] = {
.class_hid = BNXT_ULP_CLASS_HID_576a,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15493,7 +19061,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [753] = {
+ [897] = {
.class_hid = BNXT_ULP_CLASS_HID_30b6,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15509,7 +19077,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [754] = {
+ [898] = {
.class_hid = BNXT_ULP_CLASS_HID_192e,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15526,7 +19094,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [755] = {
+ [899] = {
.class_hid = BNXT_ULP_CLASS_HID_197a,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15542,7 +19110,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [756] = {
+ [900] = {
.class_hid = BNXT_ULP_CLASS_HID_4ea6,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15559,7 +19127,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [757] = {
+ [901] = {
.class_hid = BNXT_ULP_CLASS_HID_2bf2,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15576,7 +19144,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [758] = {
+ [902] = {
.class_hid = BNXT_ULP_CLASS_HID_306a,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -15594,7 +19162,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [759] = {
+ [903] = {
.class_hid = BNXT_ULP_CLASS_HID_06c6,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15609,7 +19177,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [760] = {
+ [904] = {
.class_hid = BNXT_ULP_CLASS_HID_544e,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15625,7 +19193,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [761] = {
+ [905] = {
.class_hid = BNXT_ULP_CLASS_HID_46ce,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15641,7 +19209,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [762] = {
+ [906] = {
.class_hid = BNXT_ULP_CLASS_HID_0d02,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15658,7 +19226,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [763] = {
+ [907] = {
.class_hid = BNXT_ULP_CLASS_HID_26c2,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15674,7 +19242,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [764] = {
+ [908] = {
.class_hid = BNXT_ULP_CLASS_HID_744a,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15691,7 +19259,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [765] = {
+ [909] = {
.class_hid = BNXT_ULP_CLASS_HID_1f86,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15708,7 +19276,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [766] = {
+ [910] = {
.class_hid = BNXT_ULP_CLASS_HID_2d0e,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -15726,7 +19294,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [767] = {
+ [911] = {
.class_hid = BNXT_ULP_CLASS_HID_2e1c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15742,7 +19310,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [768] = {
+ [912] = {
.class_hid = BNXT_ULP_CLASS_HID_3a00,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15759,7 +19327,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [769] = {
+ [913] = {
.class_hid = BNXT_ULP_CLASS_HID_46d0,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15776,7 +19344,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [770] = {
+ [914] = {
.class_hid = BNXT_ULP_CLASS_HID_52c4,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15794,7 +19362,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [771] = {
+ [915] = {
.class_hid = BNXT_ULP_CLASS_HID_4e10,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15811,7 +19379,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [772] = {
+ [916] = {
.class_hid = BNXT_ULP_CLASS_HID_5a04,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15829,7 +19397,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [773] = {
+ [917] = {
.class_hid = BNXT_ULP_CLASS_HID_1f98,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15847,7 +19415,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [774] = {
+ [918] = {
.class_hid = BNXT_ULP_CLASS_HID_72f8,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15866,7 +19434,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [775] = {
+ [919] = {
.class_hid = BNXT_ULP_CLASS_HID_0a78,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15883,7 +19451,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [776] = {
+ [920] = {
.class_hid = BNXT_ULP_CLASS_HID_166c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15901,7 +19469,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [777] = {
+ [921] = {
.class_hid = BNXT_ULP_CLASS_HID_233c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15919,7 +19487,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [778] = {
+ [922] = {
.class_hid = BNXT_ULP_CLASS_HID_0f20,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15938,7 +19506,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [779] = {
+ [923] = {
.class_hid = BNXT_ULP_CLASS_HID_2a7c,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15956,7 +19524,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [780] = {
+ [924] = {
.class_hid = BNXT_ULP_CLASS_HID_3660,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15975,7 +19543,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [781] = {
+ [925] = {
.class_hid = BNXT_ULP_CLASS_HID_4330,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -15994,7 +19562,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [782] = {
+ [926] = {
.class_hid = BNXT_ULP_CLASS_HID_2f24,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -16014,7 +19582,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [783] = {
+ [927] = {
.class_hid = BNXT_ULP_CLASS_HID_5584,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16030,7 +19598,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [784] = {
+ [928] = {
.class_hid = BNXT_ULP_CLASS_HID_2198,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16047,7 +19615,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [785] = {
+ [929] = {
.class_hid = BNXT_ULP_CLASS_HID_7588,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16064,7 +19632,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [786] = {
+ [930] = {
.class_hid = BNXT_ULP_CLASS_HID_419c,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16082,7 +19650,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [787] = {
+ [931] = {
.class_hid = BNXT_ULP_CLASS_HID_7758,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16099,7 +19667,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [788] = {
+ [932] = {
.class_hid = BNXT_ULP_CLASS_HID_43ac,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16117,7 +19685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [789] = {
+ [933] = {
.class_hid = BNXT_ULP_CLASS_HID_0c10,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16135,7 +19703,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [790] = {
+ [934] = {
.class_hid = BNXT_ULP_CLASS_HID_1864,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16154,7 +19722,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [791] = {
+ [935] = {
.class_hid = BNXT_ULP_CLASS_HID_30c8,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16171,7 +19739,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [792] = {
+ [936] = {
.class_hid = BNXT_ULP_CLASS_HID_1cdc,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16189,7 +19757,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [793] = {
+ [937] = {
.class_hid = BNXT_ULP_CLASS_HID_50cc,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16207,7 +19775,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [794] = {
+ [938] = {
.class_hid = BNXT_ULP_CLASS_HID_3d20,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16226,7 +19794,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [795] = {
+ [939] = {
.class_hid = BNXT_ULP_CLASS_HID_529c,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16244,7 +19812,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [796] = {
+ [940] = {
.class_hid = BNXT_ULP_CLASS_HID_3ef0,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16263,7 +19831,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [797] = {
+ [941] = {
.class_hid = BNXT_ULP_CLASS_HID_72e0,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16282,7 +19850,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [798] = {
+ [942] = {
.class_hid = BNXT_ULP_CLASS_HID_5ef4,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -16302,7 +19870,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [799] = {
+ [943] = {
.class_hid = BNXT_ULP_CLASS_HID_2dfc,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16318,7 +19886,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [800] = {
+ [944] = {
.class_hid = BNXT_ULP_CLASS_HID_39e0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16335,7 +19903,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [801] = {
+ [945] = {
.class_hid = BNXT_ULP_CLASS_HID_4530,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16352,7 +19920,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [802] = {
+ [946] = {
.class_hid = BNXT_ULP_CLASS_HID_5124,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16370,7 +19938,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [803] = {
+ [947] = {
.class_hid = BNXT_ULP_CLASS_HID_4df0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16387,7 +19955,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [804] = {
+ [948] = {
.class_hid = BNXT_ULP_CLASS_HID_59e4,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16405,7 +19973,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [805] = {
+ [949] = {
.class_hid = BNXT_ULP_CLASS_HID_1c78,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16423,7 +19991,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [806] = {
+ [950] = {
.class_hid = BNXT_ULP_CLASS_HID_7118,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16442,7 +20010,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [807] = {
+ [951] = {
.class_hid = BNXT_ULP_CLASS_HID_0998,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16459,7 +20027,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [808] = {
+ [952] = {
.class_hid = BNXT_ULP_CLASS_HID_158c,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16477,7 +20045,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [809] = {
+ [953] = {
.class_hid = BNXT_ULP_CLASS_HID_20dc,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16495,7 +20063,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [810] = {
+ [954] = {
.class_hid = BNXT_ULP_CLASS_HID_0cc0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16514,7 +20082,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [811] = {
+ [955] = {
.class_hid = BNXT_ULP_CLASS_HID_299c,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16532,7 +20100,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [812] = {
+ [956] = {
.class_hid = BNXT_ULP_CLASS_HID_3580,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16551,7 +20119,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [813] = {
+ [957] = {
.class_hid = BNXT_ULP_CLASS_HID_40d0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16570,7 +20138,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [814] = {
+ [958] = {
.class_hid = BNXT_ULP_CLASS_HID_2cc4,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -16590,7 +20158,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [815] = {
+ [959] = {
.class_hid = BNXT_ULP_CLASS_HID_55a4,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16606,7 +20174,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [816] = {
+ [960] = {
.class_hid = BNXT_ULP_CLASS_HID_21b8,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16623,7 +20191,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [817] = {
+ [961] = {
.class_hid = BNXT_ULP_CLASS_HID_75a8,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16640,7 +20208,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [818] = {
+ [962] = {
.class_hid = BNXT_ULP_CLASS_HID_41bc,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16658,7 +20226,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [819] = {
+ [963] = {
.class_hid = BNXT_ULP_CLASS_HID_7778,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16675,7 +20243,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [820] = {
+ [964] = {
.class_hid = BNXT_ULP_CLASS_HID_438c,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16693,7 +20261,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [821] = {
+ [965] = {
.class_hid = BNXT_ULP_CLASS_HID_0c30,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16711,7 +20279,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [822] = {
+ [966] = {
.class_hid = BNXT_ULP_CLASS_HID_1844,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16730,7 +20298,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [823] = {
+ [967] = {
.class_hid = BNXT_ULP_CLASS_HID_30e8,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16747,7 +20315,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [824] = {
+ [968] = {
.class_hid = BNXT_ULP_CLASS_HID_1cfc,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16765,7 +20333,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [825] = {
+ [969] = {
.class_hid = BNXT_ULP_CLASS_HID_50ec,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16783,7 +20351,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [826] = {
+ [970] = {
.class_hid = BNXT_ULP_CLASS_HID_3d00,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16802,7 +20370,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [827] = {
+ [971] = {
.class_hid = BNXT_ULP_CLASS_HID_52bc,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16820,7 +20388,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [828] = {
+ [972] = {
.class_hid = BNXT_ULP_CLASS_HID_3ed0,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16839,7 +20407,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [829] = {
+ [973] = {
.class_hid = BNXT_ULP_CLASS_HID_72c0,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16858,7 +20426,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [830] = {
+ [974] = {
.class_hid = BNXT_ULP_CLASS_HID_5ed4,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -16878,7 +20446,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [831] = {
+ [975] = {
.class_hid = BNXT_ULP_CLASS_HID_3866,
.class_tid = 3,
.hdr_sig_id = 0,
@@ -16893,7 +20461,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC }
},
- [832] = {
+ [976] = {
.class_hid = BNXT_ULP_CLASS_HID_381e,
.class_tid = 3,
.hdr_sig_id = 1,
@@ -16908,7 +20476,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC }
},
- [833] = {
+ [977] = {
.class_hid = BNXT_ULP_CLASS_HID_3860,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -16924,7 +20492,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC }
},
- [834] = {
+ [978] = {
.class_hid = BNXT_ULP_CLASS_HID_0454,
.class_tid = 3,
.hdr_sig_id = 2,
@@ -16941,7 +20509,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID }
},
- [835] = {
+ [979] = {
.class_hid = BNXT_ULP_CLASS_HID_3818,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -16957,7 +20525,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC }
},
- [836] = {
+ [980] = {
.class_hid = BNXT_ULP_CLASS_HID_042c,
.class_tid = 3,
.hdr_sig_id = 3,
@@ -16974,7 +20542,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID }
},
- [837] = {
+ [981] = {
.class_hid = BNXT_ULP_CLASS_HID_3846,
.class_tid = 3,
.hdr_sig_id = 4,
@@ -16990,7 +20558,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC }
},
- [838] = {
+ [982] = {
.class_hid = BNXT_ULP_CLASS_HID_387e,
.class_tid = 3,
.hdr_sig_id = 5,
@@ -17006,7 +20574,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC }
},
- [839] = {
+ [983] = {
.class_hid = BNXT_ULP_CLASS_HID_3ba6,
.class_tid = 3,
.hdr_sig_id = 6,
@@ -17022,7 +20590,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC }
},
- [840] = {
+ [984] = {
.class_hid = BNXT_ULP_CLASS_HID_385e,
.class_tid = 3,
.hdr_sig_id = 7,
@@ -17038,7 +20606,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC }
},
- [841] = {
+ [985] = {
.class_hid = BNXT_ULP_CLASS_HID_3840,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -17055,7 +20623,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC }
},
- [842] = {
+ [986] = {
.class_hid = BNXT_ULP_CLASS_HID_0474,
.class_tid = 3,
.hdr_sig_id = 8,
@@ -17073,7 +20641,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID }
},
- [843] = {
+ [987] = {
.class_hid = BNXT_ULP_CLASS_HID_3878,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -17090,7 +20658,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC }
},
- [844] = {
+ [988] = {
.class_hid = BNXT_ULP_CLASS_HID_044c,
.class_tid = 3,
.hdr_sig_id = 9,
@@ -17108,7 +20676,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID }
},
- [845] = {
+ [989] = {
.class_hid = BNXT_ULP_CLASS_HID_3ba0,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -17125,7 +20693,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC }
},
- [846] = {
+ [990] = {
.class_hid = BNXT_ULP_CLASS_HID_0794,
.class_tid = 3,
.hdr_sig_id = 10,
@@ -17143,7 +20711,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID }
},
- [847] = {
+ [991] = {
.class_hid = BNXT_ULP_CLASS_HID_3858,
.class_tid = 3,
.hdr_sig_id = 11,
@@ -17160,7 +20728,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC }
},
- [848] = {
+ [992] = {
.class_hid = BNXT_ULP_CLASS_HID_046c,
.class_tid = 3,
.hdr_sig_id = 11,
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
index 84e3d92f41..c016e1940a 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Tue Jul 13 12:36:40 2021 */
+/* date: Fri Aug 20 17:59:14 2021 */
#ifndef ULP_TEMPLATE_DB_H_
#define ULP_TEMPLATE_DB_H_
@@ -11,14 +11,14 @@
#define BNXT_ULP_REGFILE_MAX_SZ 42
#define BNXT_ULP_MAX_NUM_DEVICES 4
#define BNXT_ULP_LOG2_MAX_NUM_DEV 2
-#define BNXT_ULP_GEN_TBL_MAX_SZ 12
-#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 32768
-#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 849
+#define BNXT_ULP_GEN_TBL_MAX_SZ 16
+#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 65536
+#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 993
#define BNXT_ULP_CLASS_HID_LOW_PRIME 6701
#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907
-#define BNXT_ULP_CLASS_HID_SHFTR 24
-#define BNXT_ULP_CLASS_HID_SHFTL 24
-#define BNXT_ULP_CLASS_HID_MASK 32767
+#define BNXT_ULP_CLASS_HID_SHFTR 28
+#define BNXT_ULP_CLASS_HID_SHFTL 28
+#define BNXT_ULP_CLASS_HID_MASK 65535
#define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048
#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 86
#define BNXT_ULP_ACT_HID_LOW_PRIME 7919
@@ -27,10 +27,10 @@
#define BNXT_ULP_ACT_HID_SHFTL 26
#define BNXT_ULP_ACT_HID_MASK 2047
#define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 8
-#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 62
+#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 110
#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 50
-#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 206
-#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 6
+#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 278
+#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 8
#define BNXT_ULP_COND_GOTO_REJECT 1023
#define BNXT_ULP_COND_GOTO_RF 0x10000
#define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7
@@ -44,10 +44,10 @@
#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 618
#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 49
#define ULP_THOR_CLASS_TMPL_LIST_SIZE 6
-#define ULP_THOR_CLASS_TBL_LIST_SIZE 114
-#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 2305
-#define ULP_THOR_CLASS_IDENT_LIST_SIZE 39
-#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1192
+#define ULP_THOR_CLASS_TBL_LIST_SIZE 116
+#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 2323
+#define ULP_THOR_CLASS_IDENT_LIST_SIZE 38
+#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1313
#define ULP_THOR_CLASS_COND_LIST_SIZE 55
#define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7
#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 35
@@ -56,11 +56,11 @@
#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 536
#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 39
#define ULP_THOR_ACT_TMPL_LIST_SIZE 7
-#define ULP_THOR_ACT_TBL_LIST_SIZE 28
-#define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 2
-#define ULP_THOR_ACT_IDENT_LIST_SIZE 1
-#define ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE 479
-#define ULP_THOR_ACT_COND_LIST_SIZE 20
+#define ULP_THOR_ACT_TBL_LIST_SIZE 36
+#define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 16
+#define ULP_THOR_ACT_IDENT_LIST_SIZE 3
+#define ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE 505
+#define ULP_THOR_ACT_COND_LIST_SIZE 27
enum bnxt_ulp_act_bit {
BNXT_ULP_ACT_BIT_MARK = 0x0000000000000001,
@@ -158,56 +158,60 @@ enum bnxt_ulp_cf_idx {
BNXT_ULP_CF_IDX_O_L4_DST_PORT = 18,
BNXT_ULP_CF_IDX_I_L4_SRC_PORT = 19,
BNXT_ULP_CF_IDX_I_L4_DST_PORT = 20,
- BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT = 21,
- BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT = 22,
- BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT = 23,
- BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT = 24,
- BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID = 25,
- BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID = 26,
- BNXT_ULP_CF_IDX_O_L3_PROTO_ID = 27,
- BNXT_ULP_CF_IDX_I_L3_PROTO_ID = 28,
- BNXT_ULP_CF_IDX_DEV_PORT_ID = 29,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 30,
- BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 31,
- BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 32,
- BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 33,
- BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 34,
- BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 35,
- BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 36,
- BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 37,
- BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 38,
- BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 39,
- BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 40,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 41,
- BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 42,
- BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG = 43,
- BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG = 44,
- BNXT_ULP_CF_IDX_ACT_DEC_TTL = 45,
- BNXT_ULP_CF_IDX_ACT_T_DEC_TTL = 46,
- BNXT_ULP_CF_IDX_ACT_PORT_IS_SET = 47,
- BNXT_ULP_CF_IDX_ACT_PORT_TYPE = 48,
- BNXT_ULP_CF_IDX_MATCH_PORT_TYPE = 49,
- BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP = 50,
- BNXT_ULP_CF_IDX_MATCH_PORT_IS_PF = 51,
- BNXT_ULP_CF_IDX_VF_TO_VF = 52,
- BNXT_ULP_CF_IDX_L3_HDR_CNT = 53,
- BNXT_ULP_CF_IDX_L4_HDR_CNT = 54,
- BNXT_ULP_CF_IDX_VFR_MODE = 55,
- BNXT_ULP_CF_IDX_L3_TUN = 56,
- BNXT_ULP_CF_IDX_L3_TUN_DECAP = 57,
- BNXT_ULP_CF_IDX_FID = 58,
- BNXT_ULP_CF_IDX_HDR_SIG_ID = 59,
- BNXT_ULP_CF_IDX_FLOW_SIG_ID = 60,
- BNXT_ULP_CF_IDX_WC_MATCH = 61,
- BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG = 62,
- BNXT_ULP_CF_IDX_TUNNEL_ID = 63,
- BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID = 64,
- BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID = 65,
- BNXT_ULP_CF_IDX_OO_VLAN_FB_VID = 66,
- BNXT_ULP_CF_IDX_OI_VLAN_FB_VID = 67,
- BNXT_ULP_CF_IDX_IO_VLAN_FB_VID = 68,
- BNXT_ULP_CF_IDX_II_VLAN_FB_VID = 69,
- BNXT_ULP_CF_IDX_LAST = 70
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK = 21,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK = 22,
+ BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK = 23,
+ BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK = 24,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT = 25,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT = 26,
+ BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT = 27,
+ BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT = 28,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID = 29,
+ BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID = 30,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID = 31,
+ BNXT_ULP_CF_IDX_I_L3_PROTO_ID = 32,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID = 33,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 34,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 35,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 36,
+ BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 37,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 38,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 39,
+ BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 40,
+ BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 41,
+ BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 42,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 43,
+ BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 44,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 45,
+ BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 46,
+ BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG = 47,
+ BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG = 48,
+ BNXT_ULP_CF_IDX_ACT_DEC_TTL = 49,
+ BNXT_ULP_CF_IDX_ACT_T_DEC_TTL = 50,
+ BNXT_ULP_CF_IDX_ACT_PORT_IS_SET = 51,
+ BNXT_ULP_CF_IDX_ACT_PORT_TYPE = 52,
+ BNXT_ULP_CF_IDX_MATCH_PORT_TYPE = 53,
+ BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP = 54,
+ BNXT_ULP_CF_IDX_MATCH_PORT_IS_PF = 55,
+ BNXT_ULP_CF_IDX_VF_TO_VF = 56,
+ BNXT_ULP_CF_IDX_L3_HDR_CNT = 57,
+ BNXT_ULP_CF_IDX_L4_HDR_CNT = 58,
+ BNXT_ULP_CF_IDX_VFR_MODE = 59,
+ BNXT_ULP_CF_IDX_L3_TUN = 60,
+ BNXT_ULP_CF_IDX_L3_TUN_DECAP = 61,
+ BNXT_ULP_CF_IDX_FID = 62,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID = 63,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID = 64,
+ BNXT_ULP_CF_IDX_WC_MATCH = 65,
+ BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG = 66,
+ BNXT_ULP_CF_IDX_TUNNEL_ID = 67,
+ BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID = 68,
+ BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID = 69,
+ BNXT_ULP_CF_IDX_OO_VLAN_FB_VID = 70,
+ BNXT_ULP_CF_IDX_OI_VLAN_FB_VID = 71,
+ BNXT_ULP_CF_IDX_IO_VLAN_FB_VID = 72,
+ BNXT_ULP_CF_IDX_II_VLAN_FB_VID = 73,
+ BNXT_ULP_CF_IDX_LAST = 74
};
enum bnxt_ulp_cond_list_opc {
@@ -394,38 +398,49 @@ enum bnxt_ulp_glb_rf_idx {
BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 = 9,
BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 = 10,
BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 = 11,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0 = 12,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1 = 13,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_6 = 12,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_7 = 13,
BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 = 14,
BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 = 15,
BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 = 16,
BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3 = 17,
BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4 = 18,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0 = 19,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1 = 20,
- BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0 = 21,
- BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_1 = 22,
- BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 = 23,
- BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 = 24,
- BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 = 25,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 26,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 = 27,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2 = 28,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 29,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 30,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 31,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 32,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 33,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 34,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 35,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 36,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 37,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 38,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 39,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 40,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 41,
- BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID = 42,
- BNXT_ULP_GLB_RF_IDX_LAST = 43
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0 = 19,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1 = 20,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2 = 21,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3 = 22,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_4 = 23,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_5 = 24,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_6 = 25,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_7 = 26,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0 = 27,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1 = 28,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2 = 29,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3 = 30,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_4 = 31,
+ BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0 = 32,
+ BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_1 = 33,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 = 34,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 = 35,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 = 36,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 37,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 = 38,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2 = 39,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 40,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 41,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 42,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 43,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 44,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 45,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 46,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 47,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 48,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 49,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 50,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 51,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 52,
+ BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID = 53,
+ BNXT_ULP_GLB_RF_IDX_LAST = 54
};
enum bnxt_ulp_hdr_type {
@@ -608,7 +623,9 @@ enum bnxt_ulp_resource_sub_type {
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR = 2,
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE = 3,
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE = 4,
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE = 5
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE = 5,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE = 6,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE = 7
};
enum bnxt_ulp_act_prop_sz {
@@ -1526,166 +1543,310 @@ enum bnxt_ulp_class_hid {
BNXT_ULP_CLASS_HID_315d = 0x315d,
BNXT_ULP_CLASS_HID_3612 = 0x3612,
BNXT_ULP_CLASS_HID_66da = 0x66da,
- BNXT_ULP_CLASS_HID_6165 = 0x6165,
- BNXT_ULP_CLASS_HID_2aa1 = 0x2aa1,
- BNXT_ULP_CLASS_HID_09cd = 0x09cd,
- BNXT_ULP_CLASS_HID_3845 = 0x3845,
- BNXT_ULP_CLASS_HID_11e9 = 0x11e9,
- BNXT_ULP_CLASS_HID_4361 = 0x4361,
- BNXT_ULP_CLASS_HID_218d = 0x218d,
- BNXT_ULP_CLASS_HID_5105 = 0x5105,
- BNXT_ULP_CLASS_HID_0c89 = 0x0c89,
- BNXT_ULP_CLASS_HID_3e81 = 0x3e81,
- BNXT_ULP_CLASS_HID_1dad = 0x1dad,
- BNXT_ULP_CLASS_HID_4ca5 = 0x4ca5,
- BNXT_ULP_CLASS_HID_25c9 = 0x25c9,
- BNXT_ULP_CLASS_HID_57c1 = 0x57c1,
- BNXT_ULP_CLASS_HID_33ed = 0x33ed,
- BNXT_ULP_CLASS_HID_65e5 = 0x65e5,
- BNXT_ULP_CLASS_HID_6dd9 = 0x6dd9,
- BNXT_ULP_CLASS_HID_261d = 0x261d,
- BNXT_ULP_CLASS_HID_0571 = 0x0571,
- BNXT_ULP_CLASS_HID_34f9 = 0x34f9,
- BNXT_ULP_CLASS_HID_1d55 = 0x1d55,
- BNXT_ULP_CLASS_HID_4fdd = 0x4fdd,
- BNXT_ULP_CLASS_HID_2d31 = 0x2d31,
- BNXT_ULP_CLASS_HID_5db9 = 0x5db9,
- BNXT_ULP_CLASS_HID_0035 = 0x0035,
- BNXT_ULP_CLASS_HID_323d = 0x323d,
- BNXT_ULP_CLASS_HID_1111 = 0x1111,
- BNXT_ULP_CLASS_HID_4019 = 0x4019,
- BNXT_ULP_CLASS_HID_2975 = 0x2975,
- BNXT_ULP_CLASS_HID_5b7d = 0x5b7d,
- BNXT_ULP_CLASS_HID_3f51 = 0x3f51,
- BNXT_ULP_CLASS_HID_6959 = 0x6959,
- BNXT_ULP_CLASS_HID_0e85 = 0x0e85,
- BNXT_ULP_CLASS_HID_380d = 0x380d,
- BNXT_ULP_CLASS_HID_1f21 = 0x1f21,
- BNXT_ULP_CLASS_HID_4ea9 = 0x4ea9,
- BNXT_ULP_CLASS_HID_1705 = 0x1705,
- BNXT_ULP_CLASS_HID_418d = 0x418d,
- BNXT_ULP_CLASS_HID_2721 = 0x2721,
- BNXT_ULP_CLASS_HID_57a9 = 0x57a9,
- BNXT_ULP_CLASS_HID_1a25 = 0x1a25,
- BNXT_ULP_CLASS_HID_342d = 0x342d,
- BNXT_ULP_CLASS_HID_2b01 = 0x2b01,
- BNXT_ULP_CLASS_HID_5a09 = 0x5a09,
- BNXT_ULP_CLASS_HID_2325 = 0x2325,
- BNXT_ULP_CLASS_HID_5d2d = 0x5d2d,
- BNXT_ULP_CLASS_HID_3101 = 0x3101,
- BNXT_ULP_CLASS_HID_6309 = 0x6309,
- BNXT_ULP_CLASS_HID_0bad = 0x0bad,
- BNXT_ULP_CLASS_HID_2535 = 0x2535,
- BNXT_ULP_CLASS_HID_1869 = 0x1869,
- BNXT_ULP_CLASS_HID_4bf1 = 0x4bf1,
- BNXT_ULP_CLASS_HID_136d = 0x136d,
- BNXT_ULP_CLASS_HID_43f5 = 0x43f5,
- BNXT_ULP_CLASS_HID_2129 = 0x2129,
- BNXT_ULP_CLASS_HID_53b1 = 0x53b1,
- BNXT_ULP_CLASS_HID_072d = 0x072d,
- BNXT_ULP_CLASS_HID_3135 = 0x3135,
- BNXT_ULP_CLASS_HID_1429 = 0x1429,
- BNXT_ULP_CLASS_HID_4731 = 0x4731,
- BNXT_ULP_CLASS_HID_2f6d = 0x2f6d,
- BNXT_ULP_CLASS_HID_5f75 = 0x5f75,
- BNXT_ULP_CLASS_HID_3d69 = 0x3d69,
- BNXT_ULP_CLASS_HID_6f71 = 0x6f71,
- BNXT_ULP_CLASS_HID_0dbd = 0x0dbd,
- BNXT_ULP_CLASS_HID_3f25 = 0x3f25,
- BNXT_ULP_CLASS_HID_1239 = 0x1239,
- BNXT_ULP_CLASS_HID_4da1 = 0x4da1,
- BNXT_ULP_CLASS_HID_153d = 0x153d,
- BNXT_ULP_CLASS_HID_45a5 = 0x45a5,
- BNXT_ULP_CLASS_HID_3bb9 = 0x3bb9,
- BNXT_ULP_CLASS_HID_55a1 = 0x55a1,
- BNXT_ULP_CLASS_HID_193d = 0x193d,
- BNXT_ULP_CLASS_HID_4b25 = 0x4b25,
- BNXT_ULP_CLASS_HID_2e39 = 0x2e39,
- BNXT_ULP_CLASS_HID_5921 = 0x5921,
- BNXT_ULP_CLASS_HID_213d = 0x213d,
- BNXT_ULP_CLASS_HID_5125 = 0x5125,
- BNXT_ULP_CLASS_HID_3739 = 0x3739,
- BNXT_ULP_CLASS_HID_093d = 0x093d,
- BNXT_ULP_CLASS_HID_684d = 0x684d,
- BNXT_ULP_CLASS_HID_2389 = 0x2389,
- BNXT_ULP_CLASS_HID_00e5 = 0x00e5,
- BNXT_ULP_CLASS_HID_316d = 0x316d,
- BNXT_ULP_CLASS_HID_18c1 = 0x18c1,
- BNXT_ULP_CLASS_HID_4a49 = 0x4a49,
- BNXT_ULP_CLASS_HID_28a5 = 0x28a5,
- BNXT_ULP_CLASS_HID_582d = 0x582d,
- BNXT_ULP_CLASS_HID_05a1 = 0x05a1,
- BNXT_ULP_CLASS_HID_37a9 = 0x37a9,
- BNXT_ULP_CLASS_HID_1485 = 0x1485,
- BNXT_ULP_CLASS_HID_458d = 0x458d,
- BNXT_ULP_CLASS_HID_2ce1 = 0x2ce1,
- BNXT_ULP_CLASS_HID_5ee9 = 0x5ee9,
- BNXT_ULP_CLASS_HID_3ac5 = 0x3ac5,
- BNXT_ULP_CLASS_HID_6ccd = 0x6ccd,
- BNXT_ULP_CLASS_HID_0b11 = 0x0b11,
- BNXT_ULP_CLASS_HID_3d99 = 0x3d99,
- BNXT_ULP_CLASS_HID_1ab5 = 0x1ab5,
- BNXT_ULP_CLASS_HID_4b3d = 0x4b3d,
- BNXT_ULP_CLASS_HID_1291 = 0x1291,
- BNXT_ULP_CLASS_HID_4419 = 0x4419,
- BNXT_ULP_CLASS_HID_22b5 = 0x22b5,
- BNXT_ULP_CLASS_HID_523d = 0x523d,
- BNXT_ULP_CLASS_HID_1fb1 = 0x1fb1,
- BNXT_ULP_CLASS_HID_31b9 = 0x31b9,
- BNXT_ULP_CLASS_HID_2e95 = 0x2e95,
- BNXT_ULP_CLASS_HID_5f9d = 0x5f9d,
- BNXT_ULP_CLASS_HID_26b1 = 0x26b1,
- BNXT_ULP_CLASS_HID_58b9 = 0x58b9,
- BNXT_ULP_CLASS_HID_3495 = 0x3495,
- BNXT_ULP_CLASS_HID_669d = 0x669d,
- BNXT_ULP_CLASS_HID_0e39 = 0x0e39,
- BNXT_ULP_CLASS_HID_20a1 = 0x20a1,
- BNXT_ULP_CLASS_HID_1dfd = 0x1dfd,
- BNXT_ULP_CLASS_HID_4e65 = 0x4e65,
- BNXT_ULP_CLASS_HID_16f9 = 0x16f9,
- BNXT_ULP_CLASS_HID_4661 = 0x4661,
- BNXT_ULP_CLASS_HID_24bd = 0x24bd,
- BNXT_ULP_CLASS_HID_5625 = 0x5625,
- BNXT_ULP_CLASS_HID_02b9 = 0x02b9,
- BNXT_ULP_CLASS_HID_34a1 = 0x34a1,
- BNXT_ULP_CLASS_HID_11bd = 0x11bd,
- BNXT_ULP_CLASS_HID_42a5 = 0x42a5,
- BNXT_ULP_CLASS_HID_2af9 = 0x2af9,
- BNXT_ULP_CLASS_HID_5ae1 = 0x5ae1,
- BNXT_ULP_CLASS_HID_38fd = 0x38fd,
- BNXT_ULP_CLASS_HID_6ae5 = 0x6ae5,
- BNXT_ULP_CLASS_HID_0829 = 0x0829,
- BNXT_ULP_CLASS_HID_3ab1 = 0x3ab1,
- BNXT_ULP_CLASS_HID_17ad = 0x17ad,
- BNXT_ULP_CLASS_HID_4835 = 0x4835,
- BNXT_ULP_CLASS_HID_10a9 = 0x10a9,
- BNXT_ULP_CLASS_HID_4031 = 0x4031,
- BNXT_ULP_CLASS_HID_3e2d = 0x3e2d,
- BNXT_ULP_CLASS_HID_5035 = 0x5035,
- BNXT_ULP_CLASS_HID_1ca9 = 0x1ca9,
- BNXT_ULP_CLASS_HID_4eb1 = 0x4eb1,
- BNXT_ULP_CLASS_HID_2bad = 0x2bad,
- BNXT_ULP_CLASS_HID_5cb5 = 0x5cb5,
- BNXT_ULP_CLASS_HID_24a9 = 0x24a9,
- BNXT_ULP_CLASS_HID_54b1 = 0x54b1,
- BNXT_ULP_CLASS_HID_32ad = 0x32ad,
- BNXT_ULP_CLASS_HID_0ca9 = 0x0ca9,
- BNXT_ULP_CLASS_HID_7f35 = 0x7f35,
- BNXT_ULP_CLASS_HID_34f1 = 0x34f1,
- BNXT_ULP_CLASS_HID_179d = 0x179d,
- BNXT_ULP_CLASS_HID_2615 = 0x2615,
- BNXT_ULP_CLASS_HID_0fb9 = 0x0fb9,
- BNXT_ULP_CLASS_HID_5d31 = 0x5d31,
- BNXT_ULP_CLASS_HID_3fdd = 0x3fdd,
- BNXT_ULP_CLASS_HID_4f55 = 0x4f55,
- BNXT_ULP_CLASS_HID_12d9 = 0x12d9,
- BNXT_ULP_CLASS_HID_20d1 = 0x20d1,
- BNXT_ULP_CLASS_HID_03fd = 0x03fd,
- BNXT_ULP_CLASS_HID_52f5 = 0x52f5,
- BNXT_ULP_CLASS_HID_3b99 = 0x3b99,
- BNXT_ULP_CLASS_HID_4991 = 0x4991,
- BNXT_ULP_CLASS_HID_2dbd = 0x2dbd,
- BNXT_ULP_CLASS_HID_7bb5 = 0x7bb5,
+ BNXT_ULP_CLASS_HID_e082 = 0xe082,
+ BNXT_ULP_CLASS_HID_ab46 = 0xab46,
+ BNXT_ULP_CLASS_HID_c82a = 0xc82a,
+ BNXT_ULP_CLASS_HID_f9a2 = 0xf9a2,
+ BNXT_ULP_CLASS_HID_d8ce = 0xd8ce,
+ BNXT_ULP_CLASS_HID_a2d2 = 0xa2d2,
+ BNXT_ULP_CLASS_HID_c076 = 0xc076,
+ BNXT_ULP_CLASS_HID_f1ee = 0xf1ee,
+ BNXT_ULP_CLASS_HID_a96e = 0xa96e,
+ BNXT_ULP_CLASS_HID_dae6 = 0xdae6,
+ BNXT_ULP_CLASS_HID_c7aa = 0xc7aa,
+ BNXT_ULP_CLASS_HID_c26e = 0xc26e,
+ BNXT_ULP_CLASS_HID_a0fa = 0xa0fa,
+ BNXT_ULP_CLASS_HID_d272 = 0xd272,
+ BNXT_ULP_CLASS_HID_fff6 = 0xfff6,
+ BNXT_ULP_CLASS_HID_e16e = 0xe16e,
+ BNXT_ULP_CLASS_HID_e165 = 0xe165,
+ BNXT_ULP_CLASS_HID_aaa1 = 0xaaa1,
+ BNXT_ULP_CLASS_HID_c9cd = 0xc9cd,
+ BNXT_ULP_CLASS_HID_f845 = 0xf845,
+ BNXT_ULP_CLASS_HID_90f9 = 0x90f9,
+ BNXT_ULP_CLASS_HID_c371 = 0xc371,
+ BNXT_ULP_CLASS_HID_e19d = 0xe19d,
+ BNXT_ULP_CLASS_HID_d015 = 0xd015,
+ BNXT_ULP_CLASS_HID_8c09 = 0x8c09,
+ BNXT_ULP_CLASS_HID_be89 = 0xbe89,
+ BNXT_ULP_CLASS_HID_ddad = 0xddad,
+ BNXT_ULP_CLASS_HID_cc2d = 0xcc2d,
+ BNXT_ULP_CLASS_HID_a4d9 = 0xa4d9,
+ BNXT_ULP_CLASS_HID_d759 = 0xd759,
+ BNXT_ULP_CLASS_HID_f27d = 0xf27d,
+ BNXT_ULP_CLASS_HID_e4fd = 0xe4fd,
+ BNXT_ULP_CLASS_HID_ecf6 = 0xecf6,
+ BNXT_ULP_CLASS_HID_a732 = 0xa732,
+ BNXT_ULP_CLASS_HID_c45e = 0xc45e,
+ BNXT_ULP_CLASS_HID_f5d6 = 0xf5d6,
+ BNXT_ULP_CLASS_HID_d4ba = 0xd4ba,
+ BNXT_ULP_CLASS_HID_aea6 = 0xaea6,
+ BNXT_ULP_CLASS_HID_cc02 = 0xcc02,
+ BNXT_ULP_CLASS_HID_fd9a = 0xfd9a,
+ BNXT_ULP_CLASS_HID_a51a = 0xa51a,
+ BNXT_ULP_CLASS_HID_d692 = 0xd692,
+ BNXT_ULP_CLASS_HID_cbde = 0xcbde,
+ BNXT_ULP_CLASS_HID_ce1a = 0xce1a,
+ BNXT_ULP_CLASS_HID_ac8e = 0xac8e,
+ BNXT_ULP_CLASS_HID_de06 = 0xde06,
+ BNXT_ULP_CLASS_HID_f382 = 0xf382,
+ BNXT_ULP_CLASS_HID_ed1a = 0xed1a,
+ BNXT_ULP_CLASS_HID_9d6a = 0x9d6a,
+ BNXT_ULP_CLASS_HID_cee2 = 0xcee2,
+ BNXT_ULP_CLASS_HID_ec0e = 0xec0e,
+ BNXT_ULP_CLASS_HID_dd86 = 0xdd86,
+ BNXT_ULP_CLASS_HID_852e = 0x852e,
+ BNXT_ULP_CLASS_HID_b6a6 = 0xb6a6,
+ BNXT_ULP_CLASS_HID_eb82 = 0xeb82,
+ BNXT_ULP_CLASS_HID_c50a = 0xc50a,
+ BNXT_ULP_CLASS_HID_ccca = 0xccca,
+ BNXT_ULP_CLASS_HID_8706 = 0x8706,
+ BNXT_ULP_CLASS_HID_d38e = 0xd38e,
+ BNXT_ULP_CLASS_HID_d5ca = 0xd5ca,
+ BNXT_ULP_CLASS_HID_b48e = 0xb48e,
+ BNXT_ULP_CLASS_HID_8e8a = 0x8e8a,
+ BNXT_ULP_CLASS_HID_db02 = 0xdb02,
+ BNXT_ULP_CLASS_HID_dd8e = 0xdd8e,
+ BNXT_ULP_CLASS_HID_819a = 0x819a,
+ BNXT_ULP_CLASS_HID_b31a = 0xb31a,
+ BNXT_ULP_CLASS_HID_d03e = 0xd03e,
+ BNXT_ULP_CLASS_HID_c1be = 0xc1be,
+ BNXT_ULP_CLASS_HID_890e = 0x890e,
+ BNXT_ULP_CLASS_HID_ba8e = 0xba8e,
+ BNXT_ULP_CLASS_HID_dfaa = 0xdfaa,
+ BNXT_ULP_CLASS_HID_c93a = 0xc93a,
+ BNXT_ULP_CLASS_HID_b11a = 0xb11a,
+ BNXT_ULP_CLASS_HID_8b4e = 0x8b4e,
+ BNXT_ULP_CLASS_HID_c79e = 0xc79e,
+ BNXT_ULP_CLASS_HID_d9da = 0xd9da,
+ BNXT_ULP_CLASS_HID_b88e = 0xb88e,
+ BNXT_ULP_CLASS_HID_ea0e = 0xea0e,
+ BNXT_ULP_CLASS_HID_cf0a = 0xcf0a,
+ BNXT_ULP_CLASS_HID_c18e = 0xc18e,
+ BNXT_ULP_CLASS_HID_a94a = 0xa94a,
+ BNXT_ULP_CLASS_HID_daca = 0xdaca,
+ BNXT_ULP_CLASS_HID_ffee = 0xffee,
+ BNXT_ULP_CLASS_HID_e96e = 0xe96e,
+ BNXT_ULP_CLASS_HID_910e = 0x910e,
+ BNXT_ULP_CLASS_HID_c28e = 0xc28e,
+ BNXT_ULP_CLASS_HID_e7aa = 0xe7aa,
+ BNXT_ULP_CLASS_HID_d12a = 0xd12a,
+ BNXT_ULP_CLASS_HID_d8ca = 0xd8ca,
+ BNXT_ULP_CLASS_HID_930e = 0x930e,
+ BNXT_ULP_CLASS_HID_ef4e = 0xef4e,
+ BNXT_ULP_CLASS_HID_e18a = 0xe18a,
+ BNXT_ULP_CLASS_HID_c08e = 0xc08e,
+ BNXT_ULP_CLASS_HID_9a8a = 0x9a8a,
+ BNXT_ULP_CLASS_HID_d70a = 0xd70a,
+ BNXT_ULP_CLASS_HID_e90e = 0xe90e,
+ BNXT_ULP_CLASS_HID_edd9 = 0xedd9,
+ BNXT_ULP_CLASS_HID_a61d = 0xa61d,
+ BNXT_ULP_CLASS_HID_c571 = 0xc571,
+ BNXT_ULP_CLASS_HID_f4f9 = 0xf4f9,
+ BNXT_ULP_CLASS_HID_9c45 = 0x9c45,
+ BNXT_ULP_CLASS_HID_cfcd = 0xcfcd,
+ BNXT_ULP_CLASS_HID_ed21 = 0xed21,
+ BNXT_ULP_CLASS_HID_dca9 = 0xdca9,
+ BNXT_ULP_CLASS_HID_80b5 = 0x80b5,
+ BNXT_ULP_CLASS_HID_b235 = 0xb235,
+ BNXT_ULP_CLASS_HID_d111 = 0xd111,
+ BNXT_ULP_CLASS_HID_c091 = 0xc091,
+ BNXT_ULP_CLASS_HID_a865 = 0xa865,
+ BNXT_ULP_CLASS_HID_dbe5 = 0xdbe5,
+ BNXT_ULP_CLASS_HID_fec1 = 0xfec1,
+ BNXT_ULP_CLASS_HID_e841 = 0xe841,
+ BNXT_ULP_CLASS_HID_8e85 = 0x8e85,
+ BNXT_ULP_CLASS_HID_b80d = 0xb80d,
+ BNXT_ULP_CLASS_HID_df65 = 0xdf65,
+ BNXT_ULP_CLASS_HID_ceed = 0xceed,
+ BNXT_ULP_CLASS_HID_9645 = 0x9645,
+ BNXT_ULP_CLASS_HID_c1cd = 0xc1cd,
+ BNXT_ULP_CLASS_HID_e725 = 0xe725,
+ BNXT_ULP_CLASS_HID_d6ad = 0xd6ad,
+ BNXT_ULP_CLASS_HID_9aa5 = 0x9aa5,
+ BNXT_ULP_CLASS_HID_b425 = 0xb425,
+ BNXT_ULP_CLASS_HID_eb05 = 0xeb05,
+ BNXT_ULP_CLASS_HID_da85 = 0xda85,
+ BNXT_ULP_CLASS_HID_a265 = 0xa265,
+ BNXT_ULP_CLASS_HID_dde5 = 0xdde5,
+ BNXT_ULP_CLASS_HID_f0c5 = 0xf0c5,
+ BNXT_ULP_CLASS_HID_e245 = 0xe245,
+ BNXT_ULP_CLASS_HID_8b8f = 0x8b8f,
+ BNXT_ULP_CLASS_HID_a517 = 0xa517,
+ BNXT_ULP_CLASS_HID_d86b = 0xd86b,
+ BNXT_ULP_CLASS_HID_cbf3 = 0xcbf3,
+ BNXT_ULP_CLASS_HID_934f = 0x934f,
+ BNXT_ULP_CLASS_HID_c2c7 = 0xc2c7,
+ BNXT_ULP_CLASS_HID_e02b = 0xe02b,
+ BNXT_ULP_CLASS_HID_d3a3 = 0xd3a3,
+ BNXT_ULP_CLASS_HID_87a7 = 0x87a7,
+ BNXT_ULP_CLASS_HID_b137 = 0xb137,
+ BNXT_ULP_CLASS_HID_d403 = 0xd403,
+ BNXT_ULP_CLASS_HID_c793 = 0xc793,
+ BNXT_ULP_CLASS_HID_af67 = 0xaf67,
+ BNXT_ULP_CLASS_HID_dee7 = 0xdee7,
+ BNXT_ULP_CLASS_HID_fdc3 = 0xfdc3,
+ BNXT_ULP_CLASS_HID_ef43 = 0xef43,
+ BNXT_ULP_CLASS_HID_8dbf = 0x8dbf,
+ BNXT_ULP_CLASS_HID_bf07 = 0xbf07,
+ BNXT_ULP_CLASS_HID_d21f = 0xd21f,
+ BNXT_ULP_CLASS_HID_cde7 = 0xcde7,
+ BNXT_ULP_CLASS_HID_956f = 0x956f,
+ BNXT_ULP_CLASS_HID_c4c7 = 0xc4c7,
+ BNXT_ULP_CLASS_HID_fbcf = 0xfbcf,
+ BNXT_ULP_CLASS_HID_d5a7 = 0xd5a7,
+ BNXT_ULP_CLASS_HID_9957 = 0x9957,
+ BNXT_ULP_CLASS_HID_cb27 = 0xcb27,
+ BNXT_ULP_CLASS_HID_ee37 = 0xee37,
+ BNXT_ULP_CLASS_HID_d987 = 0xd987,
+ BNXT_ULP_CLASS_HID_a107 = 0xa107,
+ BNXT_ULP_CLASS_HID_d0e7 = 0xd0e7,
+ BNXT_ULP_CLASS_HID_f7e7 = 0xf7e7,
+ BNXT_ULP_CLASS_HID_c827 = 0xc827,
+ BNXT_ULP_CLASS_HID_f76a = 0xf76a,
+ BNXT_ULP_CLASS_HID_bcae = 0xbcae,
+ BNXT_ULP_CLASS_HID_dfc2 = 0xdfc2,
+ BNXT_ULP_CLASS_HID_ee4a = 0xee4a,
+ BNXT_ULP_CLASS_HID_cf26 = 0xcf26,
+ BNXT_ULP_CLASS_HID_b53a = 0xb53a,
+ BNXT_ULP_CLASS_HID_d79e = 0xd79e,
+ BNXT_ULP_CLASS_HID_e606 = 0xe606,
+ BNXT_ULP_CLASS_HID_be86 = 0xbe86,
+ BNXT_ULP_CLASS_HID_cd0e = 0xcd0e,
+ BNXT_ULP_CLASS_HID_d042 = 0xd042,
+ BNXT_ULP_CLASS_HID_d586 = 0xd586,
+ BNXT_ULP_CLASS_HID_b712 = 0xb712,
+ BNXT_ULP_CLASS_HID_c59a = 0xc59a,
+ BNXT_ULP_CLASS_HID_e81e = 0xe81e,
+ BNXT_ULP_CLASS_HID_f686 = 0xf686,
+ BNXT_ULP_CLASS_HID_86f6 = 0x86f6,
+ BNXT_ULP_CLASS_HID_d57e = 0xd57e,
+ BNXT_ULP_CLASS_HID_f792 = 0xf792,
+ BNXT_ULP_CLASS_HID_c61a = 0xc61a,
+ BNXT_ULP_CLASS_HID_9eb2 = 0x9eb2,
+ BNXT_ULP_CLASS_HID_ad3a = 0xad3a,
+ BNXT_ULP_CLASS_HID_f01e = 0xf01e,
+ BNXT_ULP_CLASS_HID_de96 = 0xde96,
+ BNXT_ULP_CLASS_HID_d756 = 0xd756,
+ BNXT_ULP_CLASS_HID_9c9a = 0x9c9a,
+ BNXT_ULP_CLASS_HID_c812 = 0xc812,
+ BNXT_ULP_CLASS_HID_ce56 = 0xce56,
+ BNXT_ULP_CLASS_HID_af12 = 0xaf12,
+ BNXT_ULP_CLASS_HID_9516 = 0x9516,
+ BNXT_ULP_CLASS_HID_c09e = 0xc09e,
+ BNXT_ULP_CLASS_HID_c612 = 0xc612,
+ BNXT_ULP_CLASS_HID_9a06 = 0x9a06,
+ BNXT_ULP_CLASS_HID_a886 = 0xa886,
+ BNXT_ULP_CLASS_HID_cba2 = 0xcba2,
+ BNXT_ULP_CLASS_HID_da22 = 0xda22,
+ BNXT_ULP_CLASS_HID_9292 = 0x9292,
+ BNXT_ULP_CLASS_HID_a112 = 0xa112,
+ BNXT_ULP_CLASS_HID_c436 = 0xc436,
+ BNXT_ULP_CLASS_HID_d2a6 = 0xd2a6,
+ BNXT_ULP_CLASS_HID_aa86 = 0xaa86,
+ BNXT_ULP_CLASS_HID_90d2 = 0x90d2,
+ BNXT_ULP_CLASS_HID_dc02 = 0xdc02,
+ BNXT_ULP_CLASS_HID_c246 = 0xc246,
+ BNXT_ULP_CLASS_HID_a312 = 0xa312,
+ BNXT_ULP_CLASS_HID_f192 = 0xf192,
+ BNXT_ULP_CLASS_HID_d496 = 0xd496,
+ BNXT_ULP_CLASS_HID_da12 = 0xda12,
+ BNXT_ULP_CLASS_HID_b2d6 = 0xb2d6,
+ BNXT_ULP_CLASS_HID_c156 = 0xc156,
+ BNXT_ULP_CLASS_HID_e472 = 0xe472,
+ BNXT_ULP_CLASS_HID_f2f2 = 0xf2f2,
+ BNXT_ULP_CLASS_HID_8a92 = 0x8a92,
+ BNXT_ULP_CLASS_HID_d912 = 0xd912,
+ BNXT_ULP_CLASS_HID_fc36 = 0xfc36,
+ BNXT_ULP_CLASS_HID_cab6 = 0xcab6,
+ BNXT_ULP_CLASS_HID_c356 = 0xc356,
+ BNXT_ULP_CLASS_HID_8892 = 0x8892,
+ BNXT_ULP_CLASS_HID_f4d2 = 0xf4d2,
+ BNXT_ULP_CLASS_HID_fa16 = 0xfa16,
+ BNXT_ULP_CLASS_HID_db12 = 0xdb12,
+ BNXT_ULP_CLASS_HID_8116 = 0x8116,
+ BNXT_ULP_CLASS_HID_cc96 = 0xcc96,
+ BNXT_ULP_CLASS_HID_f292 = 0xf292,
+ BNXT_ULP_CLASS_HID_e84d = 0xe84d,
+ BNXT_ULP_CLASS_HID_a389 = 0xa389,
+ BNXT_ULP_CLASS_HID_c0e5 = 0xc0e5,
+ BNXT_ULP_CLASS_HID_f16d = 0xf16d,
+ BNXT_ULP_CLASS_HID_99d1 = 0x99d1,
+ BNXT_ULP_CLASS_HID_ca59 = 0xca59,
+ BNXT_ULP_CLASS_HID_e8b5 = 0xe8b5,
+ BNXT_ULP_CLASS_HID_d93d = 0xd93d,
+ BNXT_ULP_CLASS_HID_8521 = 0x8521,
+ BNXT_ULP_CLASS_HID_b7a1 = 0xb7a1,
+ BNXT_ULP_CLASS_HID_d485 = 0xd485,
+ BNXT_ULP_CLASS_HID_c505 = 0xc505,
+ BNXT_ULP_CLASS_HID_adf1 = 0xadf1,
+ BNXT_ULP_CLASS_HID_de71 = 0xde71,
+ BNXT_ULP_CLASS_HID_fb55 = 0xfb55,
+ BNXT_ULP_CLASS_HID_edd5 = 0xedd5,
+ BNXT_ULP_CLASS_HID_8b11 = 0x8b11,
+ BNXT_ULP_CLASS_HID_bd99 = 0xbd99,
+ BNXT_ULP_CLASS_HID_daf1 = 0xdaf1,
+ BNXT_ULP_CLASS_HID_cb79 = 0xcb79,
+ BNXT_ULP_CLASS_HID_93d1 = 0x93d1,
+ BNXT_ULP_CLASS_HID_c459 = 0xc459,
+ BNXT_ULP_CLASS_HID_e2b1 = 0xe2b1,
+ BNXT_ULP_CLASS_HID_d339 = 0xd339,
+ BNXT_ULP_CLASS_HID_9f31 = 0x9f31,
+ BNXT_ULP_CLASS_HID_b1b1 = 0xb1b1,
+ BNXT_ULP_CLASS_HID_ee91 = 0xee91,
+ BNXT_ULP_CLASS_HID_df11 = 0xdf11,
+ BNXT_ULP_CLASS_HID_a7f1 = 0xa7f1,
+ BNXT_ULP_CLASS_HID_d871 = 0xd871,
+ BNXT_ULP_CLASS_HID_f551 = 0xf551,
+ BNXT_ULP_CLASS_HID_e7d1 = 0xe7d1,
+ BNXT_ULP_CLASS_HID_8e1b = 0x8e1b,
+ BNXT_ULP_CLASS_HID_a083 = 0xa083,
+ BNXT_ULP_CLASS_HID_ddff = 0xddff,
+ BNXT_ULP_CLASS_HID_ce67 = 0xce67,
+ BNXT_ULP_CLASS_HID_96db = 0x96db,
+ BNXT_ULP_CLASS_HID_c753 = 0xc753,
+ BNXT_ULP_CLASS_HID_e5bf = 0xe5bf,
+ BNXT_ULP_CLASS_HID_d637 = 0xd637,
+ BNXT_ULP_CLASS_HID_8233 = 0x8233,
+ BNXT_ULP_CLASS_HID_b4a3 = 0xb4a3,
+ BNXT_ULP_CLASS_HID_d197 = 0xd197,
+ BNXT_ULP_CLASS_HID_c207 = 0xc207,
+ BNXT_ULP_CLASS_HID_aaf3 = 0xaaf3,
+ BNXT_ULP_CLASS_HID_db73 = 0xdb73,
+ BNXT_ULP_CLASS_HID_f857 = 0xf857,
+ BNXT_ULP_CLASS_HID_ead7 = 0xead7,
+ BNXT_ULP_CLASS_HID_882b = 0x882b,
+ BNXT_ULP_CLASS_HID_ba93 = 0xba93,
+ BNXT_ULP_CLASS_HID_d78b = 0xd78b,
+ BNXT_ULP_CLASS_HID_c873 = 0xc873,
+ BNXT_ULP_CLASS_HID_90fb = 0x90fb,
+ BNXT_ULP_CLASS_HID_c153 = 0xc153,
+ BNXT_ULP_CLASS_HID_fe5b = 0xfe5b,
+ BNXT_ULP_CLASS_HID_d033 = 0xd033,
+ BNXT_ULP_CLASS_HID_9cc3 = 0x9cc3,
+ BNXT_ULP_CLASS_HID_ceb3 = 0xceb3,
+ BNXT_ULP_CLASS_HID_eba3 = 0xeba3,
+ BNXT_ULP_CLASS_HID_dc13 = 0xdc13,
+ BNXT_ULP_CLASS_HID_a493 = 0xa493,
+ BNXT_ULP_CLASS_HID_d573 = 0xd573,
+ BNXT_ULP_CLASS_HID_f273 = 0xf273,
+ BNXT_ULP_CLASS_HID_cdb3 = 0xcdb3,
+ BNXT_ULP_CLASS_HID_ff35 = 0xff35,
+ BNXT_ULP_CLASS_HID_b4f1 = 0xb4f1,
+ BNXT_ULP_CLASS_HID_d79d = 0xd79d,
+ BNXT_ULP_CLASS_HID_e615 = 0xe615,
+ BNXT_ULP_CLASS_HID_8ea9 = 0x8ea9,
+ BNXT_ULP_CLASS_HID_dd21 = 0xdd21,
+ BNXT_ULP_CLASS_HID_ffcd = 0xffcd,
+ BNXT_ULP_CLASS_HID_ce45 = 0xce45,
+ BNXT_ULP_CLASS_HID_9259 = 0x9259,
+ BNXT_ULP_CLASS_HID_a0d9 = 0xa0d9,
+ BNXT_ULP_CLASS_HID_c3fd = 0xc3fd,
+ BNXT_ULP_CLASS_HID_d27d = 0xd27d,
+ BNXT_ULP_CLASS_HID_ba89 = 0xba89,
+ BNXT_ULP_CLASS_HID_c909 = 0xc909,
+ BNXT_ULP_CLASS_HID_ec2d = 0xec2d,
+ BNXT_ULP_CLASS_HID_faad = 0xfaad,
BNXT_ULP_CLASS_HID_34c6 = 0x34c6,
BNXT_ULP_CLASS_HID_0c22 = 0x0c22,
BNXT_ULP_CLASS_HID_1cbe = 0x1cbe,
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h
index 1d7bbfe2cc..0a5c7e3d6e 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu May 20 11:56:39 2021 */
+/* date: Fri Aug 6 11:15:47 2021 */
#ifndef ULP_HDR_FIELD_ENUMS_H_
#define ULP_HDR_FIELD_ENUMS_H_
@@ -459,16 +459,14 @@ enum bnxt_ulp_hf_0_2_1_bitmask {
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC = 0x0000080000000000,
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC = 0x0000040000000000,
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_TYPE = 0x0000020000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_VER = 0x0000010000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_TOS = 0x0000008000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_LEN = 0x0000004000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_TTL = 0x0000000800000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_TC = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_FLOW_LABEL = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_PROTO_ID = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR = 0x0000000200000000
};
enum bnxt_ulp_hf_0_2_2_bitmask {
@@ -504,16 +502,7 @@ enum bnxt_ulp_hf_0_2_2_bitmask {
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT = 0x0000000040000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT = 0x0000000020000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SENT_SEQ = 0x0000000010000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_RECV_ACK = 0x0000000008000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DATA_OFF = 0x0000000004000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_TCP_FLAGS = 0x0000000002000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_RX_WIN = 0x0000000001000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_CSUM = 0x0000000000800000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_URP = 0x0000000000400000
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000
};
enum bnxt_ulp_hf_0_2_3_bitmask {
@@ -540,20 +529,23 @@ enum bnxt_ulp_hf_0_2_3_bitmask {
BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC = 0x0000080000000000,
BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC = 0x0000040000000000,
BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_TYPE = 0x0000020000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_VER = 0x0000010000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_TOS = 0x0000008000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_LEN = 0x0000004000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_TTL = 0x0000000800000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT = 0x0000000040000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT = 0x0000000020000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_LENGTH = 0x0000000010000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_CSUM = 0x0000000008000000
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_TC = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_FLOW_LABEL = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_PROTO_ID = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SENT_SEQ = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_RECV_ACK = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DATA_OFF = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_TCP_FLAGS = 0x0000000008000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_RX_WIN = 0x0000000004000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_CSUM = 0x0000000002000000,
+ BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_URP = 0x0000000001000000
};
enum bnxt_ulp_hf_0_2_4_bitmask {
@@ -590,11 +582,134 @@ enum bnxt_ulp_hf_0_2_4_bitmask {
BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_TYPE = 0x0000000040000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_CODE = 0x0000000020000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_CSUM = 0x0000000010000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_IDENT = 0x0000000008000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_SEQ_NUM = 0x0000000004000000
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SENT_SEQ = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_RECV_ACK = 0x0000000008000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DATA_OFF = 0x0000000004000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_TCP_FLAGS = 0x0000000002000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_RX_WIN = 0x0000000001000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_CSUM = 0x0000000000800000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_URP = 0x0000000000400000
+};
+
+enum bnxt_ulp_hf_0_2_5_bitmask {
+ BNXT_ULP_HF_0_2_5_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_TC = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_FLOW_LABEL = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_PROTO_ID = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_LENGTH = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_CSUM = 0x0000000020000000
+};
+
+enum bnxt_ulp_hf_0_2_6_bitmask {
+ BNXT_ULP_HF_0_2_6_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_LENGTH = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_CSUM = 0x0000000008000000
+};
+
+enum bnxt_ulp_hf_0_2_7_bitmask {
+ BNXT_ULP_HF_0_2_7_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_TYPE = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_CODE = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_CSUM = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_IDENT = 0x0000000008000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_SEQ_NUM = 0x0000000004000000
};
enum bnxt_ulp_hf_0_3_0_bitmask {
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
index 3d1e95d18c..684fa66f48 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu Jul 8 08:44:00 2021 */
+/* date: Tue Aug 17 12:16:42 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -131,6 +131,46 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = {
.num_buckets = 8,
.hash_tbl_entries = 1024,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE << 1 |
+ BNXT_ULP_DIRECTION_INGRESS] = {
+ .name = "INGRESS GEN_TABLE_SOURCE_PROPERTY_CACHE",
+ .result_num_entries = 0,
+ .result_num_bytes = 6,
+ .key_num_bytes = 10,
+ .num_buckets = 4,
+ .hash_tbl_entries = 0,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE << 1 |
+ BNXT_ULP_DIRECTION_EGRESS] = {
+ .name = "INGRESS GEN_TABLE_SOURCE_PROPERTY_CACHE",
+ .result_num_entries = 128,
+ .result_num_bytes = 6,
+ .key_num_bytes = 10,
+ .num_buckets = 4,
+ .hash_tbl_entries = 512,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE << 1 |
+ BNXT_ULP_DIRECTION_INGRESS] = {
+ .name = "INGRESS GEN_TABLE_VXLAN_ENCAP_REC_CACHE",
+ .result_num_entries = 0,
+ .result_num_bytes = 6,
+ .key_num_bytes = 17,
+ .num_buckets = 8,
+ .hash_tbl_entries = 0,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE << 1 |
+ BNXT_ULP_DIRECTION_EGRESS] = {
+ .name = "INGRESS GEN_TABLE_VXLAN_ENCAP_REC_CACHE",
+ .result_num_entries = 256,
+ .result_num_bytes = 6,
+ .key_num_bytes = 17,
+ .num_buckets = 8,
+ .hash_tbl_entries = 1024,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
}
};
@@ -222,6 +262,7 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
.byte_count_shift = 0,
.packet_count_shift = 36,
.dynamic_pad_en = 0,
+ .dynamic_sram_en = 0,
.dev_tbls = ulp_template_wh_plus_tbls
},
[BNXT_ULP_DEVICE_ID_THOR] = {
@@ -246,12 +287,24 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
.byte_count_shift = 0,
.packet_count_shift = 35,
.dynamic_pad_en = 1,
+ .dynamic_sram_en = 1,
+ .dyn_encap_list_size = 4,
+ .dyn_encap_sizes = {{64, TF_TBL_TYPE_ACT_ENCAP_8B},
+ {128, TF_TBL_TYPE_ACT_ENCAP_16B},
+ {256, TF_TBL_TYPE_ACT_ENCAP_32B},
+ {512, TF_TBL_TYPE_ACT_ENCAP_64B}},
+ .dyn_modify_list_size = 4,
+ .dyn_modify_sizes = {{64, TF_TBL_TYPE_ACT_MODIFY_8B},
+ {128, TF_TBL_TYPE_ACT_MODIFY_16B},
+ {256, TF_TBL_TYPE_ACT_MODIFY_32B},
+ {512, TF_TBL_TYPE_ACT_MODIFY_64B}},
.em_blk_size_bits = 100,
.em_blk_align_bits = 128,
.em_key_align_bytes = 80,
.wc_slice_width = 160,
.wc_max_slices = 4,
- .wc_mode_list = {0x0000000c, 0x0000000e, 0x0000000f, 0x0000000f},
+ .wc_mode_list = {0x0000000c, 0x0000000e,
+ 0x0000000f, 0x0000000f},
.wc_mod_list_max_size = 4,
.wc_ctl_size_bits = 32,
.dev_tbls = ulp_template_thor_tbls
@@ -307,6 +360,16 @@ struct bnxt_ulp_app_capabilities_info ulp_app_cap_info_list[] = {
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.flags = BNXT_ULP_APP_CAP_SHARED_EN |
BNXT_ULP_APP_CAP_UNICAST_ONLY
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY
}
};
@@ -1279,333 +1342,1261 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = {
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
.direction = TF_DIR_TX
- }
-};
-
-/* List of tf resources required to be reserved per app/device */
-struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
+ },
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 422
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 6
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 191
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 63
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 192
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 8192
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 6912
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 1023
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 511
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 15
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
- .count = 255
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
- .count = 1
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 422
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 6
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 960
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 88
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
- .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 13168
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
- .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
- .count = 1
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 292
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 148
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 191
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 63
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 192
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 8192
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_6,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_7,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_6,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_7,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3,
+ .direction = TF_DIR_RX
+ }
+};
+
+/* List of tf resources required to be reserved per app/device */
+struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 422
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 191
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 6912
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 511
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 15
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
+ .count = 255
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 422
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 960
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 88
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 13168
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 292
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 148
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 191
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 6912
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 511
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 223
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 255
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 488
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
+ .count = 511
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 292
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 144
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 960
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 928
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 15232
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 272
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 31
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 64
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 64
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 272
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 128
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4096
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 16384
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 272
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 64
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 100
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 272
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 128
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4096
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 16384
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .count = 1
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 32
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 2
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 128
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 128
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 32
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 2
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 32
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 1024
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 32
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 2
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 128
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 6912
+ .count = 128
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 1023
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 511
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 223
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 255
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 488
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
- .count = 511
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
- .count = 1
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 292
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 144
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 960
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 928
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 15232
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
- .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
- .count = 1
+ .count = 1024
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 422
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 6
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1613,15 +2604,15 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 32
+ .count = 16
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1629,255 +2620,223 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 2048
- },
- {
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 512
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 528
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
- .count = 5
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 256
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 32
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 31
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 64
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 64
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 300
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 6
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 128
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 2048
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 13200
+ .count = 1024
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 26
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 26
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 32
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 63
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 32
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 1023
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_STATS_64,
.count = 512
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
- .count = 5
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 256
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 32
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 32
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 64
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 100
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
- .count = 32
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 200
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 110
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 128
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 2048
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 15232
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_METADATA,
- .count = 1
+ .count = 1024
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1885,7 +2844,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1893,7 +2852,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1901,7 +2860,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1909,7 +2868,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -1917,7 +2876,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1925,7 +2884,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 128
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1933,7 +2892,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 128
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1941,7 +2900,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1949,7 +2908,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1957,7 +2916,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -1965,7 +2924,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1973,7 +2932,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1981,7 +2940,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -1989,15 +2948,15 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 64
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
@@ -2005,7 +2964,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 1024
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2013,7 +2972,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2021,7 +2980,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2029,7 +2988,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2037,7 +2996,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2045,7 +3004,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2053,7 +3012,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 128
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2061,7 +3020,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 128
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2069,7 +3028,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2077,7 +3036,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2085,7 +3044,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2093,7 +3052,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2101,7 +3060,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2109,7 +3068,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2117,7 +3076,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2125,7 +3084,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2133,7 +3092,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2141,7 +3100,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
@@ -2149,7 +3108,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 1024
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2157,7 +3116,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2165,7 +3124,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2173,7 +3132,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2181,7 +3140,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 16
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2189,7 +3148,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2197,7 +3156,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 528
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2205,7 +3164,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 256
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2213,7 +3172,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2221,7 +3180,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2229,7 +3188,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2237,7 +3196,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2245,7 +3204,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2253,7 +3212,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2261,15 +3220,15 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 512
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
@@ -2277,7 +3236,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 1024
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2285,7 +3244,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2293,7 +3252,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2301,7 +3260,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2309,7 +3268,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -2317,7 +3276,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2325,7 +3284,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 512
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2333,7 +3292,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 256
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2341,7 +3300,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2349,7 +3308,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2357,7 +3316,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2365,7 +3324,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2373,7 +3332,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2381,7 +3340,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 2
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2389,7 +3348,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 32
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -2397,7 +3356,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 4
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
@@ -2405,532 +3364,596 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.count = 1024
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 422
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 191
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 63
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 192
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 128
+ .count = 8192
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 128
+ .count = 7168
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 4
+ .count = 1023
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 4
+ .count = 511
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 4
+ .count = 15
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
- .count = 4
+ .count = 255
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 422
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 960
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 64
+ .count = 88
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 13168
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 292
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 148
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 191
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 63
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 192
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 128
+ .count = 8192
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 128
+ .count = 7168
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 4
+ .count = 1023
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .count = 511
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 4
+ .count = 223
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 4
+ .count = 255
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .count = 488
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
- .count = 4
+ .count = 511
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 292
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 144
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 960
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 928
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 15232
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 16
+ .count = 63
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 528
+ .count = 4096
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 256
+ .count = 1024
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 4
+ .count = 32
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 4
+ .count = 32
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .count = 1024
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .count = 1024
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 1024
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 512
+ .count = 2048
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 6144
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 63
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 512
+ .count = 4096
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 256
+ .count = 1024
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 4
+ .count = 32
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 4
+ .count = 32
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .count = 1024
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .count = 1024
},
{
- .app_id = 2,
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 1024
+ },
+ {
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 2048
},
{
- .app_id = 2,
+ .app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 6144
}
};
@@ -3322,25 +4345,23 @@ uint8_t ulp_glb_field_tbl[] = {
[4229] = 21,
[4231] = 22,
[4244] = 2,
- [4245] = 23,
[4246] = 3,
- [4247] = 24,
[4248] = 4,
- [4249] = 25,
[4250] = 5,
- [4251] = 26,
[4252] = 6,
- [4253] = 27,
[4254] = 7,
- [4255] = 28,
[4256] = 8,
- [4257] = 29,
[4258] = 9,
- [4259] = 30,
[4260] = 10,
- [4261] = 31,
[4262] = 11,
- [4263] = 32,
+ [4265] = 23,
+ [4267] = 24,
+ [4269] = 25,
+ [4271] = 26,
+ [4273] = 27,
+ [4275] = 28,
+ [4277] = 29,
+ [4279] = 30,
[4298] = 12,
[4300] = 13,
[4302] = 14,
@@ -3374,15 +4395,6 @@ uint8_t ulp_glb_field_tbl[] = {
[4389] = 31,
[4390] = 11,
[4391] = 32,
- [4409] = 33,
- [4411] = 34,
- [4413] = 35,
- [4415] = 36,
- [4417] = 37,
- [4419] = 38,
- [4421] = 39,
- [4423] = 40,
- [4425] = 41,
[4426] = 12,
[4428] = 13,
[4430] = 14,
@@ -3397,33 +4409,36 @@ uint8_t ulp_glb_field_tbl[] = {
[4485] = 21,
[4487] = 22,
[4500] = 2,
- [4501] = 23,
[4502] = 3,
- [4503] = 24,
[4504] = 4,
- [4505] = 25,
[4506] = 5,
- [4507] = 26,
[4508] = 6,
- [4509] = 27,
[4510] = 7,
- [4511] = 28,
[4512] = 8,
- [4513] = 29,
[4514] = 9,
- [4515] = 30,
[4516] = 10,
- [4517] = 31,
[4518] = 11,
- [4519] = 32,
+ [4521] = 23,
+ [4523] = 24,
+ [4525] = 25,
+ [4527] = 26,
+ [4529] = 27,
+ [4531] = 28,
+ [4533] = 29,
+ [4535] = 30,
+ [4537] = 31,
+ [4539] = 32,
+ [4541] = 33,
+ [4543] = 34,
+ [4545] = 35,
+ [4547] = 36,
+ [4549] = 37,
+ [4551] = 38,
+ [4553] = 39,
[4554] = 12,
- [4555] = 33,
[4556] = 13,
- [4557] = 34,
[4558] = 14,
- [4559] = 35,
[4560] = 15,
- [4561] = 36,
[4574] = 16,
[4575] = 17,
[4576] = 18,
@@ -3433,11 +4448,6 @@ uint8_t ulp_glb_field_tbl[] = {
[4611] = 20,
[4613] = 21,
[4615] = 22,
- [4619] = 33,
- [4621] = 34,
- [4623] = 35,
- [4625] = 36,
- [4627] = 37,
[4628] = 2,
[4629] = 23,
[4630] = 3,
@@ -3458,6 +4468,15 @@ uint8_t ulp_glb_field_tbl[] = {
[4645] = 31,
[4646] = 11,
[4647] = 32,
+ [4665] = 33,
+ [4667] = 34,
+ [4669] = 35,
+ [4671] = 36,
+ [4673] = 37,
+ [4675] = 38,
+ [4677] = 39,
+ [4679] = 40,
+ [4681] = 41,
[4682] = 12,
[4684] = 13,
[4686] = 14,
@@ -3466,6 +4485,116 @@ uint8_t ulp_glb_field_tbl[] = {
[4703] = 17,
[4704] = 18,
[4705] = 19,
+ [4736] = 0,
+ [4737] = 1,
+ [4739] = 20,
+ [4741] = 21,
+ [4743] = 22,
+ [4756] = 2,
+ [4758] = 3,
+ [4760] = 4,
+ [4762] = 5,
+ [4764] = 6,
+ [4766] = 7,
+ [4768] = 8,
+ [4770] = 9,
+ [4772] = 10,
+ [4774] = 11,
+ [4777] = 23,
+ [4779] = 24,
+ [4781] = 25,
+ [4783] = 26,
+ [4785] = 27,
+ [4787] = 28,
+ [4789] = 29,
+ [4791] = 30,
+ [4810] = 12,
+ [4811] = 31,
+ [4812] = 13,
+ [4813] = 32,
+ [4814] = 14,
+ [4815] = 33,
+ [4816] = 15,
+ [4817] = 34,
+ [4830] = 16,
+ [4831] = 17,
+ [4832] = 18,
+ [4833] = 19,
+ [4864] = 0,
+ [4865] = 1,
+ [4867] = 20,
+ [4869] = 21,
+ [4871] = 22,
+ [4884] = 2,
+ [4885] = 23,
+ [4886] = 3,
+ [4887] = 24,
+ [4888] = 4,
+ [4889] = 25,
+ [4890] = 5,
+ [4891] = 26,
+ [4892] = 6,
+ [4893] = 27,
+ [4894] = 7,
+ [4895] = 28,
+ [4896] = 8,
+ [4897] = 29,
+ [4898] = 9,
+ [4899] = 30,
+ [4900] = 10,
+ [4901] = 31,
+ [4902] = 11,
+ [4903] = 32,
+ [4938] = 12,
+ [4939] = 33,
+ [4940] = 13,
+ [4941] = 34,
+ [4942] = 14,
+ [4943] = 35,
+ [4944] = 15,
+ [4945] = 36,
+ [4958] = 16,
+ [4959] = 17,
+ [4960] = 18,
+ [4961] = 19,
+ [4992] = 0,
+ [4993] = 1,
+ [4995] = 20,
+ [4997] = 21,
+ [4999] = 22,
+ [5003] = 33,
+ [5005] = 34,
+ [5007] = 35,
+ [5009] = 36,
+ [5011] = 37,
+ [5012] = 2,
+ [5013] = 23,
+ [5014] = 3,
+ [5015] = 24,
+ [5016] = 4,
+ [5017] = 25,
+ [5018] = 5,
+ [5019] = 26,
+ [5020] = 6,
+ [5021] = 27,
+ [5022] = 7,
+ [5023] = 28,
+ [5024] = 8,
+ [5025] = 29,
+ [5026] = 9,
+ [5027] = 30,
+ [5028] = 10,
+ [5029] = 31,
+ [5030] = 11,
+ [5031] = 32,
+ [5066] = 12,
+ [5068] = 13,
+ [5070] = 14,
+ [5072] = 15,
+ [5086] = 16,
+ [5087] = 17,
+ [5088] = 18,
+ [5089] = 19,
[6144] = 0,
[6145] = 1,
[6146] = 2,
@@ -3705,4 +4834,3 @@ uint8_t ulp_glb_field_tbl[] = {
[7638] = 6,
[7642] = 7
};
-
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
index 223ecbf843..e49c1151d3 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Thu Jul 8 08:44:00 2021 */
+/* date: Tue Aug 17 12:16:42 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -15,7 +15,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {
/* act_tid: 1, ingress */
[1] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 4,
+ .num_tbls = 5,
.start_tbl_idx = 0,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
@@ -26,7 +26,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {
[2] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
.num_tbls = 6,
- .start_tbl_idx = 4,
+ .start_tbl_idx = 5,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
.cond_start_idx = 3,
@@ -36,7 +36,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {
[3] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
.num_tbls = 4,
- .start_tbl_idx = 10,
+ .start_tbl_idx = 11,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
.cond_start_idx = 4,
@@ -45,8 +45,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {
/* act_tid: 4, egress */
[4] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 4,
- .start_tbl_idx = 14,
+ .num_tbls = 5,
+ .start_tbl_idx = 15,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
.cond_start_idx = 7,
@@ -56,20 +56,20 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {
[5] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
.num_tbls = 4,
- .start_tbl_idx = 18,
+ .start_tbl_idx = 20,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 10,
+ .cond_start_idx = 12,
.cond_nums = 0 }
},
/* act_tid: 6, egress */
[6] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 6,
- .start_tbl_idx = 22,
+ .num_tbls = 12,
+ .start_tbl_idx = 24,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 13,
+ .cond_start_idx = 15,
.cond_nums = 0 }
}
};
@@ -125,14 +125,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
+ .cond_false_goto = 2,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 2,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
.result_start_idx = 1,
.result_bit_size = 0,
.result_num_fields = 0,
@@ -146,7 +145,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 0,
- .cond_false_goto = 0,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 3,
.cond_nums = 0 },
@@ -158,6 +157,26 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.result_bit_size = 128,
.result_num_fields = 17
},
+ { /* act_tid: 1, , table: int_compact_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_COMPACT_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 3,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 65,
+ .result_bit_size = 64,
+ .result_num_fields = 13
+ },
{ /* act_tid: 2, , table: control.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
@@ -187,7 +206,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 65,
+ .result_start_idx = 78,
.result_bit_size = 32,
.result_num_fields = 5
},
@@ -208,13 +227,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 70,
+ .result_start_idx = 83,
.result_bit_size = 64,
.result_num_fields = 1
},
- { /* act_tid: 2, , table: int_full_act_record.0 */
+ { /* act_tid: 2, , table: int_compact_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_type = TF_TBL_TYPE_COMPACT_ACT_RECORD,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
.direction = TF_DIR_RX,
@@ -229,9 +248,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 71,
- .result_bit_size = 128,
- .result_num_fields = 17,
+ .result_start_idx = 84,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
.encap_num_fields = 0
},
{ /* act_tid: 2, , table: mirror_tbl.wr */
@@ -250,7 +269,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 88,
+ .result_start_idx = 97,
.result_bit_size = 32,
.result_num_fields = 5
},
@@ -273,7 +292,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.blob_key_bit_size = 1,
.key_bit_size = 1,
.key_num_fields = 1,
- .result_start_idx = 93,
+ .result_start_idx = 102,
.result_bit_size = 36,
.result_num_fields = 2
},
@@ -292,7 +311,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 95,
+ .result_start_idx = 104,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -311,8 +330,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 96,
+ .result_start_idx = 105,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 47
@@ -332,8 +350,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 143,
+ .result_start_idx = 152,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 47
@@ -353,7 +370,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 190,
+ .result_start_idx = 199,
.result_bit_size = 128,
.result_num_fields = 17
},
@@ -372,7 +389,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 207,
+ .result_start_idx = 216,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -391,8 +408,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 8,
- .result_start_idx = 208,
+ .result_start_idx = 217,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 11
@@ -412,8 +428,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 219,
+ .result_start_idx = 228,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 47
@@ -426,17 +441,36 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 0,
- .cond_false_goto = 0,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
.cond_start_idx = 10,
- .cond_nums = 0 },
+ .cond_nums = 2 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 266,
+ .result_start_idx = 275,
.result_bit_size = 128,
.result_num_fields = 17
},
+ { /* act_tid: 4, , table: int_compact_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_COMPACT_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 12,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 292,
+ .result_bit_size = 64,
+ .result_num_fields = 13
+ },
{ /* act_tid: 5, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
@@ -447,12 +481,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 10,
+ .cond_start_idx = 12,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 283,
+ .result_start_idx = 305,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -466,13 +500,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 2,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 11,
+ .cond_start_idx = 13,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 284,
+ .result_start_idx = 306,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 47
@@ -487,13 +520,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 12,
+ .cond_start_idx = 14,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 331,
+ .result_start_idx = 353,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 47
@@ -508,12 +540,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 13,
+ .cond_start_idx = 15,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 378,
+ .result_start_idx = 400,
.result_bit_size = 128,
.result_num_fields = 17
},
@@ -527,15 +559,48 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 13,
+ .cond_start_idx = 15,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 395,
+ .result_start_idx = 417,
.result_bit_size = 64,
.result_num_fields = 1
},
+ { /* act_tid: 6, , table: source_property_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 16,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2,
+ .blob_key_bit_size = 80,
+ .key_bit_size = 80,
+ .key_num_fields = 2,
+ .ident_start_idx = 1,
+ .ident_nums = 1
+ },
+ { /* act_tid: 6, , table: control.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 17,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
{ /* act_tid: 6, , table: sp_smac_ipv4.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
@@ -546,17 +611,40 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 14,
+ .cond_start_idx = 18,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
.record_size = 16,
- .result_start_idx = 396,
+ .result_start_idx = 418,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 3
},
+ { /* act_tid: 6, , table: source_property_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 19,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 4,
+ .blob_key_bit_size = 80,
+ .key_bit_size = 80,
+ .key_num_fields = 2,
+ .result_start_idx = 421,
+ .result_bit_size = 48,
+ .result_num_fields = 2
+ },
{ /* act_tid: 6, , table: sp_smac_ipv6.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
@@ -567,17 +655,50 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 15,
+ .cond_start_idx = 19,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.record_size = 32,
- .result_start_idx = 399,
+ .result_start_idx = 423,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 3
},
+ { /* act_tid: 6, , table: vxlan_encap_rec_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 20,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 6,
+ .blob_key_bit_size = 136,
+ .key_bit_size = 136,
+ .key_num_fields = 5,
+ .ident_start_idx = 2,
+ .ident_nums = 1
+ },
+ { /* act_tid: 6, , table: control.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 22,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
{ /* act_tid: 6, , table: int_tun_encap_record.ipv4_vxlan */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
@@ -588,17 +709,39 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 16,
+ .cond_start_idx = 23,
.cond_nums = 2 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 402,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .result_start_idx = 426,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 30
},
+ { /* act_tid: 6, , table: vxlan_encap_rec_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 25,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 11,
+ .blob_key_bit_size = 136,
+ .key_bit_size = 136,
+ .key_num_fields = 5,
+ .result_start_idx = 456,
+ .result_bit_size = 48,
+ .result_num_fields = 2
+ },
{ /* act_tid: 6, , table: int_tun_encap_record.ipv6_vxlan */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
@@ -609,13 +752,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 18,
+ .cond_start_idx = 25,
.cond_nums = 2 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 432,
+ .result_start_idx = 458,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 30
@@ -630,13 +772,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 20,
+ .cond_start_idx = 27,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 462,
+ .result_start_idx = 488,
.result_bit_size = 128,
.result_num_fields = 17
}
@@ -693,6 +835,15 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
.cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
},
+ /* cond_execute: act_tid: 4, int_full_act_record.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
+ },
/* cond_execute: act_tid: 5, int_flow_counter_tbl.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
@@ -713,6 +864,16 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
.cond_operand = BNXT_ULP_ACT_BIT_COUNT
},
+ /* cond_execute: act_tid: 6, source_property_cache.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG
+ },
+ /* cond_execute: act_tid: 6, control.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
/* cond_execute: act_tid: 6, sp_smac_ipv4.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
@@ -723,6 +884,20 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
.cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG
},
+ /* cond_execute: act_tid: 6, vxlan_encap_rec_cache.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: act_tid: 6, control.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
/* cond_execute: act_tid: 6, int_tun_encap_record.ipv4_vxlan */
{
.cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
@@ -783,6 +958,316 @@ struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = {
(BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
}
+ },
+ /* act_tid: 6, , table: source_property_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ipv4_src_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "ipv4_src_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}
+ }
+ },
+ /* act_tid: 6, , table: source_property_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ipv4_src_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "ipv4_src_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}
+ }
+ },
+ /* act_tid: 6, , table: vxlan_encap_rec_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ipv4_dst_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "ipv4_dst_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
+ }
+ },
+ /* act_tid: 6, , table: vxlan_encap_rec_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ipv4_dst_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "ipv4_dst_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
+ }
}
};
@@ -1069,38 +1554,178 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "encap_ptr",
- .field_bit_size = 16,
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr2 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_DECAP_FUNC_THRU_TUN},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_DECAP_FUNC_NONE}
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr2 = {
+ (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_RF,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr2 = {
- (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff},
+ ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER},
.field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd1",
- .field_bit_size = 16,
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 1, , table: int_compact_act_record.0 */
+ {
.description = "rsvd0",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
@@ -1137,7 +1762,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -1233,9 +1860,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "type",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
/* act_tid: 2, , table: mirror_tbl.alloc */
{
@@ -1277,31 +1902,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 2, , table: int_full_act_record.0 */
- {
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "encap_ptr",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "rsvd1",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
+ /* act_tid: 2, , table: int_compact_act_record.0 */
{
.description = "rsvd0",
.field_bit_size = 8,
@@ -1324,7 +1925,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -1387,9 +1990,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "type",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
/* act_tid: 2, , table: mirror_tbl.wr */
{
@@ -2250,7 +2851,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -2721,16 +3324,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
+ 1}
},
{
.description = "stats_ptr",
@@ -2803,6 +3399,102 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_opr1 = {
1}
},
+ /* act_tid: 4, , table: int_compact_act_record.0 */
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
/* act_tid: 5, , table: int_flow_counter_tbl.0 */
{
.description = "count",
@@ -3708,6 +4400,25 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* act_tid: 6, , table: source_property_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_SP_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_SP_PTR & 0xff}
+ },
/* act_tid: 6, , table: sp_smac_ipv6.0 */
{
.description = "smac",
@@ -4021,6 +4732,25 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
(BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff,
BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}
},
+ /* act_tid: 6, , table: vxlan_encap_rec_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "enc_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
+ },
/* act_tid: 6, , table: int_tun_encap_record.ipv6_vxlan */
{
.description = "ecv_valid",
@@ -4351,7 +5081,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -4424,5 +5156,19 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_act_ident_list[] = {
.regfile_idx = BNXT_ULP_RF_IDX_MIRROR_ID_0,
.ident_bit_size = 4,
.ident_bit_pos = 32
+ },
+ /* act_tid: 6, , table: source_property_cache.rd */
+ {
+ .description = "sp_rec_ptr",
+ .regfile_idx = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
+ .ident_bit_size = 16,
+ .ident_bit_pos = 32
+ },
+ /* act_tid: 6, , table: vxlan_encap_rec_cache.rd */
+ {
+ .description = "enc_rec_ptr",
+ .regfile_idx = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .ident_bit_size = 16,
+ .ident_bit_pos = 32
}
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
index bcb204ae13..68c1e292b2 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Fri Jul 30 09:57:44 2021 */
+/* date: Fri Aug 20 18:05:25 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -25,7 +25,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {
/* class_tid: 2, ingress */
[2] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 17,
+ .num_tbls = 24,
.start_tbl_idx = 28,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
@@ -35,18 +35,18 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {
/* class_tid: 3, egress */
[3] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 24,
- .start_tbl_idx = 45,
+ .num_tbls = 18,
+ .start_tbl_idx = 52,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 36,
+ .cond_start_idx = 39,
.cond_nums = 0 }
},
/* class_tid: 4, ingress */
[4] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
.num_tbls = 21,
- .start_tbl_idx = 69,
+ .start_tbl_idx = 70,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
.cond_start_idx = 48,
@@ -55,8 +55,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {
/* class_tid: 5, egress */
[5] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 24,
- .start_tbl_idx = 90,
+ .num_tbls = 25,
+ .start_tbl_idx = 91,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
.cond_start_idx = 52,
@@ -855,18 +855,28 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
+ { /* class_tid: 2, , table: control.ipv6_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 8,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 32,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_ipv6_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 32,
- .cond_nums = 0 },
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 33,
+ .cond_nums = 1 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
@@ -875,38 +885,57 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.key_bit_size = 14,
.key_num_fields = 3,
.ident_start_idx = 19,
- .ident_nums = 3
+ .ident_nums = 4
},
- { /* class_tid: 2, , table: control.profile_tcam_cache.f2_check */
+ { /* class_tid: 2, , table: control.f2_ipv6_prof_cache_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 4,
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 32,
+ .cond_start_idx = 34,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 2, , table: fkb_select.f2_wm */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
+ { /* class_tid: 2, , table: control.f2_v6_conflict_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
+ .cond_true_goto = 4,
+ .cond_false_goto = 1023,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 33,
+ .cond_start_idx = 35,
.cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
- .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .func_info = {
+ .func_opc = BNXT_ULP_FUNC_OPC_EQ,
+ .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
+ .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
+ .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
+ },
+ { /* class_tid: 2, , table: fkb_select.f2_l2_l3_l4_v6_em */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 36,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
.result_start_idx = 426,
.result_bit_size = 106,
.result_num_fields = 106
},
- { /* class_tid: 2, , table: profile_tcam.f2 */
+ { /* class_tid: 2, , table: profile_tcam.f2_l2_l3_l4_v6_em */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.direction = TF_DIR_RX,
@@ -914,14 +943,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 34,
+ .cond_start_idx = 36,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
- .pri_operand = 1,
+ .pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.key_start_idx = 1146,
@@ -930,9 +959,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.key_num_fields = 43,
.result_start_idx = 532,
.result_bit_size = 33,
- .result_num_fields = 8
+ .result_num_fields = 8,
+ .ident_start_idx = 23,
+ .ident_nums = 1
},
- { /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_l2_l3_l4_v6_wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
@@ -942,7 +973,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 34,
+ .cond_start_idx = 36,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
@@ -955,135 +986,81 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 138,
.result_num_fields = 7
},
- { /* class_tid: 2, , table: wm.l3_l4.ipv4 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ { /* class_tid: 2, , table: em.f2_l2_l3_l4_v6.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_INTERNAL,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 0,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 34,
- .cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 36,
+ .cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
- .pri_operand = 0,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.key_start_idx = 1192,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
.result_start_idx = 547,
- .result_bit_size = 38,
- .result_num_fields = 5
- },
- { /* class_tid: 2, , table: wm.l3_l4.ipv6 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 0,
- .cond_false_goto = 0,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 35,
- .cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
- .pri_operand = 0,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1306,
- .blob_key_bit_size = 0,
- .key_bit_size = 0,
- .key_num_fields = 114,
- .result_start_idx = 552,
- .result_bit_size = 38,
- .result_num_fields = 5
- },
- { /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 6,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 36,
- .cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1420,
- .blob_key_bit_size = 8,
- .key_bit_size = 8,
- .key_num_fields = 1,
- .ident_start_idx = 22,
- .ident_nums = 1
+ .result_bit_size = 0,
+ .result_num_fields = 6
},
- { /* class_tid: 3, , table: mac_addr_cache.rd */
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 37,
+ .cond_start_idx = 36,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1421,
- .blob_key_bit_size = 73,
- .key_bit_size = 73,
- .key_num_fields = 5,
- .ident_start_idx = 23,
- .ident_nums = 1
+ .key_start_idx = 1306,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .ident_start_idx = 24,
+ .ident_nums = 3
},
- { /* class_tid: 3, , table: control.0 */
+ { /* class_tid: 2, , table: control.profile_tcam_cache.f2_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 4,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 37,
+ .cond_start_idx = 36,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 3, , table: port_table.egr.rd */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
- .direction = TF_DIR_TX,
+ { /* class_tid: 2, , table: fkb_select.f2_wm */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 38,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 37,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .key_start_idx = 1426,
- .blob_key_bit_size = 10,
- .key_bit_size = 10,
- .key_num_fields = 1,
- .ident_start_idx = 24,
- .ident_nums = 3
+ .result_start_idx = 553,
+ .result_bit_size = 106,
+ .result_num_fields = 106
},
- { /* class_tid: 3, , table: l2_cntxt_tcam.0 */
+ { /* class_tid: 2, , table: profile_tcam.f2 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .direction = TF_DIR_TX,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
@@ -1091,26 +1068,27 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_start_idx = 38,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
- .pri_operand = 0,
- .key_start_idx = 1427,
- .blob_key_bit_size = 213,
- .key_bit_size = 213,
- .key_num_fields = 21,
- .result_start_idx = 557,
- .result_bit_size = 43,
- .result_num_fields = 6,
- .ident_start_idx = 27,
- .ident_nums = 1
+ .pri_operand = 1,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 1309,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 659,
+ .result_bit_size = 33,
+ .result_num_fields = 8
},
- { /* class_tid: 3, , table: mac_addr_cache.wr */
+ { /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
@@ -1118,15 +1096,61 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_start_idx = 38,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1448,
- .blob_key_bit_size = 73,
- .key_bit_size = 73,
- .key_num_fields = 5,
- .result_start_idx = 563,
- .result_bit_size = 62,
- .result_num_fields = 4
+ .key_start_idx = 1352,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .result_start_idx = 667,
+ .result_bit_size = 138,
+ .result_num_fields = 7
+ },
+ { /* class_tid: 2, , table: wm.l3_l4.ipv4 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 38,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .key_start_idx = 1355,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 674,
+ .result_bit_size = 38,
+ .result_num_fields = 5
+ },
+ { /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 39,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1469,
+ .blob_key_bit_size = 8,
+ .key_bit_size = 8,
+ .key_num_fields = 1,
+ .ident_start_idx = 27,
+ .ident_nums = 1
},
{ /* class_tid: 3, , table: control.ipv6_check */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
@@ -1135,7 +1159,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 8,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 38,
+ .cond_start_idx = 39,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
@@ -1148,12 +1172,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1023,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 39,
+ .cond_start_idx = 40,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1453,
+ .key_start_idx = 1470,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -1167,7 +1191,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 2,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 40,
+ .cond_start_idx = 41,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
@@ -1179,7 +1203,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 4,
.cond_false_goto = 1023,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 41,
+ .cond_start_idx = 42,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.func_info = {
@@ -1198,13 +1222,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .result_start_idx = 567,
+ .result_start_idx = 679,
.result_bit_size = 106,
.result_num_fields = 106
},
@@ -1216,7 +1240,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
@@ -1226,11 +1250,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 1456,
+ .key_start_idx = 1473,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
- .result_start_idx = 673,
+ .result_start_idx = 785,
.result_bit_size = 33,
.result_num_fields = 8,
.ident_start_idx = 32,
@@ -1246,16 +1270,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1499,
+ .key_start_idx = 1516,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
- .result_start_idx = 681,
+ .result_start_idx = 793,
.result_bit_size = 138,
.result_num_fields = 7
},
@@ -1267,15 +1291,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1502,
+ .key_start_idx = 1519,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
- .result_start_idx = 688,
+ .result_start_idx = 800,
.result_bit_size = 0,
.result_num_fields = 6
},
@@ -1288,12 +1312,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1616,
+ .key_start_idx = 1633,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -1304,32 +1328,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_TX,
.execute_info = {
- .cond_true_goto = 2,
- .cond_false_goto = 1,
+ .cond_true_goto = 1,
+ .cond_false_goto = 5,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 42,
+ .cond_start_idx = 43,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 3, , table: control.conflict_check */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 5,
- .cond_false_goto = 1023,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 43,
- .cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .func_info = {
- .func_opc = BNXT_ULP_FUNC_OPC_EQ,
- .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
- .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
- .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD,
- .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID,
- .func_dst_opr = BNXT_ULP_RF_IDX_CC }
- },
{ /* class_tid: 3, , table: fkb_select.l3_l4_wc */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
@@ -1343,7 +1349,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 694,
+ .result_start_idx = 806,
.result_bit_size = 106,
.result_num_fields = 106
},
@@ -1365,11 +1371,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 1619,
+ .key_start_idx = 1636,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
- .result_start_idx = 800,
+ .result_start_idx = 912,
.result_bit_size = 33,
.result_num_fields = 8,
.ident_start_idx = 35,
@@ -1393,11 +1399,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 1662,
+ .key_start_idx = 1679,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
- .result_start_idx = 808,
+ .result_start_idx = 920,
.result_bit_size = 33,
.result_num_fields = 8,
.ident_start_idx = 35,
@@ -1418,11 +1424,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1705,
+ .key_start_idx = 1722,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
- .result_start_idx = 816,
+ .result_start_idx = 928,
.result_bit_size = 138,
.result_num_fields = 7
},
@@ -1443,11 +1449,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1708,
+ .key_start_idx = 1725,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
- .result_start_idx = 823,
+ .result_start_idx = 935,
.result_bit_size = 38,
.result_num_fields = 5
},
@@ -1468,11 +1474,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1822,
+ .key_start_idx = 1839,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
- .result_start_idx = 828,
+ .result_start_idx = 940,
.result_bit_size = 38,
.result_num_fields = 5
},
@@ -1493,11 +1499,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1936,
+ .key_start_idx = 1953,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
- .result_start_idx = 833,
+ .result_start_idx = 945,
.result_bit_size = 38,
.result_num_fields = 5
},
@@ -1517,7 +1523,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 838,
+ .result_start_idx = 950,
.result_bit_size = 128,
.result_num_fields = 17
},
@@ -1535,11 +1541,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2050,
+ .key_start_idx = 2067,
.blob_key_bit_size = 10,
.key_bit_size = 10,
.key_num_fields = 1,
- .result_start_idx = 855,
+ .result_start_idx = 967,
.result_bit_size = 152,
.result_num_fields = 5
},
@@ -1557,7 +1563,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2051,
+ .key_start_idx = 2068,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1594,11 +1600,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 2052,
+ .key_start_idx = 2069,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
- .result_start_idx = 860,
+ .result_start_idx = 972,
.result_bit_size = 43,
.result_num_fields = 6,
.ident_start_idx = 35,
@@ -1618,11 +1624,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2073,
+ .key_start_idx = 2090,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .result_start_idx = 866,
+ .result_start_idx = 978,
.result_bit_size = 62,
.result_num_fields = 4
},
@@ -1639,7 +1645,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 870,
+ .result_start_idx = 982,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -1656,7 +1662,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 871,
+ .result_start_idx = 983,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -1676,7 +1682,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 872,
+ .result_start_idx = 984,
.result_bit_size = 128,
.result_num_fields = 17,
.encap_num_fields = 0
@@ -1695,11 +1701,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2074,
+ .key_start_idx = 2091,
.blob_key_bit_size = 10,
.key_bit_size = 10,
.key_num_fields = 1,
- .result_start_idx = 889,
+ .result_start_idx = 1001,
.result_bit_size = 152,
.result_num_fields = 5
},
@@ -1728,7 +1734,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2075,
+ .key_start_idx = 2092,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1761,7 +1767,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .result_start_idx = 894,
+ .result_start_idx = 1006,
.result_bit_size = 64,
.result_num_fields = 8
},
@@ -1779,11 +1785,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2076,
+ .key_start_idx = 2093,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .result_start_idx = 902,
+ .result_start_idx = 1014,
.result_bit_size = 62,
.result_num_fields = 4
},
@@ -1801,7 +1807,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2077,
+ .key_start_idx = 2094,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1836,11 +1842,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 2078,
+ .key_start_idx = 2095,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
- .result_start_idx = 906,
+ .result_start_idx = 1018,
.result_bit_size = 43,
.result_num_fields = 6,
.ident_start_idx = 36,
@@ -1860,11 +1866,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2099,
+ .key_start_idx = 2116,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .result_start_idx = 912,
+ .result_start_idx = 1024,
.result_bit_size = 62,
.result_num_fields = 4
},
@@ -1881,7 +1887,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 916,
+ .result_start_idx = 1028,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -1898,7 +1904,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 917,
+ .result_start_idx = 1029,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -1918,11 +1924,33 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 918,
+ .result_start_idx = 1030,
.result_bit_size = 128,
.result_num_fields = 17,
.encap_num_fields = 0
},
+ { /* class_tid: 5, , table: port_table.egr_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2117,
+ .blob_key_bit_size = 10,
+ .key_bit_size = 10,
+ .key_num_fields = 1,
+ .result_start_idx = 1047,
+ .result_bit_size = 152,
+ .result_num_fields = 5
+ },
{ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
@@ -1937,7 +1965,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2100,
+ .key_start_idx = 2118,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1972,11 +2000,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .key_start_idx = 2101,
+ .key_start_idx = 2119,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
- .result_start_idx = 935,
+ .result_start_idx = 1052,
.result_bit_size = 43,
.result_num_fields = 6,
.ident_start_idx = 37,
@@ -1996,11 +2024,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2122,
+ .key_start_idx = 2140,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .result_start_idx = 941,
+ .result_start_idx = 1058,
.result_bit_size = 62,
.result_num_fields = 4
},
@@ -2017,7 +2045,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 945,
+ .result_start_idx = 1062,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -2034,7 +2062,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 946,
+ .result_start_idx = 1063,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -2054,7 +2082,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
- .result_start_idx = 947,
+ .result_start_idx = 1064,
.result_bit_size = 128,
.result_num_fields = 17,
.encap_num_fields = 0
@@ -2072,7 +2100,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_SVIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 964,
+ .result_start_idx = 1081,
.result_bit_size = 64,
.result_num_fields = 8
},
@@ -2091,7 +2119,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2123,
+ .key_start_idx = 2141,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -2124,7 +2152,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .result_start_idx = 972,
+ .result_start_idx = 1089,
.result_bit_size = 64,
.result_num_fields = 8
},
@@ -2142,11 +2170,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2124,
+ .key_start_idx = 2142,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .result_start_idx = 980,
+ .result_start_idx = 1097,
.result_bit_size = 62,
.result_num_fields = 4
},
@@ -2165,7 +2193,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 984,
+ .result_start_idx = 1101,
.result_bit_size = 16,
.result_num_fields = 1
},
@@ -2184,8 +2212,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 64,
- .result_start_idx = 985,
+ .result_start_idx = 1102,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 47
@@ -2206,7 +2233,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 1032,
+ .result_start_idx = 1149,
.result_bit_size = 128,
.result_num_fields = 17
},
@@ -2224,7 +2251,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2125,
+ .key_start_idx = 2143,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -2261,11 +2288,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 2126,
+ .key_start_idx = 2144,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
- .result_start_idx = 1049,
+ .result_start_idx = 1166,
.result_bit_size = 43,
.result_num_fields = 6,
.ident_start_idx = 38,
@@ -2284,7 +2311,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 1055,
+ .result_start_idx = 1172,
.result_bit_size = 106,
.result_num_fields = 106
},
@@ -2306,11 +2333,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 2147,
+ .key_start_idx = 2165,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
- .result_start_idx = 1161,
+ .result_start_idx = 1278,
.result_bit_size = 33,
.result_num_fields = 8
},
@@ -2325,15 +2352,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 55,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2190,
+ .key_start_idx = 2208,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
- .ident_start_idx = 38,
- .ident_nums = 1
+ .result_start_idx = 1286,
+ .result_bit_size = 62,
+ .result_num_fields = 4
},
{ /* class_tid: 5, , table: int_full_act_record.vfr_ing0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -2351,7 +2379,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 1169,
+ .result_start_idx = 1290,
.result_bit_size = 128,
.result_num_fields = 17
},
@@ -2367,11 +2395,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 2191,
+ .key_start_idx = 2209,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
- .result_start_idx = 1186,
+ .result_start_idx = 1307,
.result_bit_size = 0,
.result_num_fields = 6
}
@@ -2529,6 +2557,26 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
+ /* cond_execute: class_tid: 2, control.ipv6_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6
+ },
+ /* cond_execute: class_tid: 2, profile_tcam_cache.f2_ipv6_rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH
+ },
+ /* cond_execute: class_tid: 2, control.f2_ipv6_prof_cache_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 2, control.f2_v6_conflict_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_CC
+ },
/* cond_execute: class_tid: 2, control.profile_tcam_cache.f2_check */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
@@ -2544,21 +2592,6 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
},
- /* cond_execute: class_tid: 2, wm.l3_l4.ipv6 */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
- .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
- },
- /* cond_execute: class_tid: 3, l2_cntxt_tcam_cache.rd */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET,
- .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC
- },
- /* cond_execute: class_tid: 3, control.0 */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
- .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
- },
/* cond_execute: class_tid: 3, control.ipv6_check */
{
.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
@@ -2584,11 +2617,6 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 3, control.conflict_check */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
- .cond_operand = BNXT_ULP_RF_IDX_CC
- },
/* cond_execute: class_tid: 3, profile_tcam.l3_l4.ip */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
@@ -5115,12 +5143,24 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -8346,7 +8386,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr1 = {
(BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
@@ -8373,7 +8416,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr1 = {
(BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
@@ -15050,7 +15096,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr1 = {
(BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
@@ -15077,7 +15126,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr1 = {
(BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
@@ -16551,7 +16603,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr1 = {
(BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
@@ -16578,7 +16633,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr1 = {
(BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
@@ -18283,7 +18341,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
- /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_ipv6_rd */
{
.field_info_mask = {
.description = "recycle_cnt",
@@ -18338,7 +18396,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
}
},
- /* class_tid: 2, , table: profile_tcam.f2 */
+ /* class_tid: 2, , table: profile_tcam.f2_l2_l3_l4_v6_em */
{
.field_info_mask = {
.description = "l4_hdr_is_udp_tcp",
@@ -18357,14 +18415,34 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l4_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l4_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_I_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_UDP}
}
},
{
@@ -18372,7 +18450,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l4_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4 & 0xff}
},
.field_info_spec = {
.description = "l4_hdr_error",
@@ -18386,13 +18467,19 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l4_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4 & 0xff}
},
.field_info_spec = {
.description = "l4_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4 & 0xff}
}
},
{
@@ -18456,13 +18543,17 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l3_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
.description = "l3_hdr_type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
}
},
{
@@ -18470,7 +18561,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l3_hdr_error",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
.description = "l3_hdr_error",
@@ -18484,13 +18577,17 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
.description = "l3_hdr_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
}
},
{
@@ -18526,7 +18623,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l2_uc_mc_bc",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
.description = "l2_uc_mc_bc",
@@ -18990,15 +19089,13 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
1}
}
},
- /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_l2_l3_l4_v6_wr */
{
.field_info_mask = {
.description = "recycle_cnt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "recycle_cnt",
@@ -19045,10 +19142,10 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
}
},
- /* class_tid: 2, , table: wm.l3_l4.ipv4 */
+ /* class_tid: 2, , table: em.f2_l2_l3_l4_v6.0 */
{
.field_info_mask = {
- .description = "wc_profile_id",
+ .description = "em_profile_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
@@ -19056,13 +19153,13 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "wc_profile_id",
+ .description = "em_profile_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 & 0xff}
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
}
},
{
@@ -19401,20 +19498,12 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "tl3.dip.ipv4",
.field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
.description = "tl3.dip.ipv4",
.field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
@@ -19766,7 +19855,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr2 = {
(BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
.field_info_spec = {
.description = "tids",
@@ -19780,7 +19869,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opr2 = {
(BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -19879,12 +19968,30 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
.field_info_spec = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -20059,12 +20166,30 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.sip.ipv6",
.field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
.field_info_spec = {
.description = "l3.sip.ipv6",
.field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -20083,42 +20208,42 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.dip.ipv4",
.field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
.description = "l3.dip.ipv4",
.field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
.description = "l3.dip.ipv6",
.field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
.field_info_spec = {
.description = "l3.dip.ipv6",
.field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -20149,12 +20274,24 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -20341,24 +20478,50 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l4.src",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
.description = "l4.src",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
.field_info_mask = {
.description = "l4.dst",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
.description = "l4.dst",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -20481,2254 +20644,2585 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
- /* class_tid: 2, , table: wm.l3_l4.ipv6 */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
{
.field_info_mask = {
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
0xff}
},
.field_info_spec = {
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 & 0xff}
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
}
},
+ /* class_tid: 2, , table: profile_tcam.f2 */
{
.field_info_mask = {
- .description = "parif",
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "parif",
+ .description = "l4_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "lcos",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "lcos",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "meta",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "meta",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "rcyc_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "rcyc_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "loopback",
+ .description = "l3_hdr_isIP",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "loopback",
+ .description = "l3_hdr_isIP",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_l2type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_l2type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl2_dt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_dt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_sa",
+ .description = "l2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_sa",
+ .description = "l2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_nvt",
+ .description = "l2_uc_mc_bc",
.field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_nvt",
+ .description = "l2_uc_mc_bc",
.field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ovp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovd",
+ .description = "l2_hdr_error",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ovd",
+ .description = "l2_hdr_error",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ovv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L2_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl2_ovt",
+ .description = "tun_hdr_flags",
.field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovt",
+ .description = "tun_hdr_flags",
.field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ivp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivd",
+ .description = "tun_hdr_err",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ivd",
+ .description = "tun_hdr_err",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl2_ivv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl2_ivv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl2_ivt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TUN_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl2_etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.l3type",
+ .description = "tl4_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.l3type",
+ .description = "tl4_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL4_HDR_TYPE_UDP}
}
},
{
.field_info_mask = {
- .description = "tl3.sip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.sip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.sip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.sip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL4_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl3.sip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.sip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.dip.ipv4",
- .field_bit_size = 32,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.dip.ipv4",
- .field_bit_size = 32,
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.dip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.dip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.dip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.dip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl3.fid.ipv4",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.fid.ipv4",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl3.fid.ipv6",
- .field_bit_size = 20,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.fid.ipv6",
- .field_bit_size = 20,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl3.qos",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.qos",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl3.ieh_nonext",
+ .description = "tl3_hdr_error",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.ieh_nonext",
+ .description = "tl3_hdr_error",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_esp",
+ .description = "tl3_hdr_valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.ieh_esp",
+ .description = "tl3_hdr_valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL3_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_auth",
+ .description = "tl2_two_vtags",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.ieh_auth",
+ .description = "tl2_two_vtags",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_dest",
+ .description = "tl2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.ieh_dest",
+ .description = "tl2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_hop",
+ .description = "tl2_hdr_valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.ieh_hop",
+ .description = "tl2_hdr_valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_TL2_HDR_VALID_YES}
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_1frag",
+ .description = "hrec_next",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.ieh_1frag",
+ .description = "hrec_next",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl3.l3err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.l3err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "agg_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
.field_info_spec = {
- .description = "tl4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
}
},
+ /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
{
.field_info_mask = {
- .description = "tl4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
}
},
+ /* class_tid: 2, , table: wm.l3_l4.ipv4 */
{
.field_info_mask = {
- .description = "tl4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "tl4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
}
},
{
.field_info_mask = {
- .description = "tuntype",
+ .description = "parif",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tuntype",
+ .description = "parif",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tflags",
- .field_bit_size = 3,
+ .description = "spif",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tflags",
- .field_bit_size = 3,
+ .description = "spif",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tids",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tids",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "tid",
- .field_bit_size = 32,
+ .description = "svif",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tid",
- .field_bit_size = 32,
+ .description = "svif",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tctxts",
- .field_bit_size = 24,
+ .description = "lcos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tctxts",
- .field_bit_size = 24,
+ .description = "lcos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tctxt",
- .field_bit_size = 32,
+ .description = "meta",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tctxt",
- .field_bit_size = 32,
+ .description = "meta",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tqos",
- .field_bit_size = 3,
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tqos",
- .field_bit_size = 3,
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "terr",
- .field_bit_size = 4,
+ .description = "loopback",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "terr",
- .field_bit_size = 4,
+ .description = "loopback",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_l2type",
+ .description = "tl2_l2type",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_l2type",
+ .description = "tl2_l2type",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_dmac",
+ .description = "tl2_dmac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_dmac",
+ .description = "tl2_dmac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_smac",
+ .description = "tl2_smac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_smac",
+ .description = "tl2_smac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_dt",
+ .description = "tl2_dt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_dt",
+ .description = "tl2_dt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_sa",
+ .description = "tl2_sa",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_sa",
+ .description = "tl2_sa",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_nvt",
+ .description = "tl2_nvt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_nvt",
+ .description = "tl2_nvt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovp",
+ .description = "tl2_ovp",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovp",
+ .description = "tl2_ovp",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovd",
+ .description = "tl2_ovd",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovd",
+ .description = "tl2_ovd",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovv",
+ .description = "tl2_ovv",
.field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovv",
+ .description = "tl2_ovv",
.field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovt",
+ .description = "tl2_ovt",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovt",
+ .description = "tl2_ovt",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivp",
+ .description = "tl2_ivp",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivp",
+ .description = "tl2_ivp",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivd",
+ .description = "tl2_ivd",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivd",
+ .description = "tl2_ivd",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivv",
+ .description = "tl2_ivv",
.field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivv",
+ .description = "tl2_ivv",
.field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivt",
+ .description = "tl2_ivt",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivt",
+ .description = "tl2_ivt",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_etype",
+ .description = "tl2_etype",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_etype",
+ .description = "tl2_etype",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.l3type",
+ .description = "tl3.l3type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.l3type",
+ .description = "tl3.l3type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.sip.ipv4",
+ .description = "tl3.sip.ipv4",
.field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.sip.ipv4",
+ .description = "tl3.sip.ipv4",
.field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.sip.ipv6",
+ .description = "tl3.sip.ipv6",
.field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.sip.ipv6",
+ .description = "tl3.sip.ipv6",
.field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.sip_selcmp.ipv6",
+ .description = "tl3.sip_selcmp.ipv6",
.field_bit_size = 72,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.sip_selcmp.ipv6",
+ .description = "tl3.sip_selcmp.ipv6",
.field_bit_size = 72,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.dip.ipv4",
+ .description = "tl3.dip.ipv4",
.field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.dip.ipv4",
+ .description = "tl3.dip.ipv4",
.field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.dip.ipv6",
+ .description = "tl3.dip.ipv6",
.field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.dip.ipv6",
+ .description = "tl3.dip.ipv6",
.field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.dip_selcmp.ipv6",
+ .description = "tl3.dip_selcmp.ipv6",
.field_bit_size = 72,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.dip_selcmp.ipv6",
+ .description = "tl3.dip_selcmp.ipv6",
.field_bit_size = 72,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ttl",
+ .description = "tl3.ttl",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ttl",
+ .description = "tl3.ttl",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.prot",
+ .description = "tl3.prot",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.prot",
+ .description = "tl3.prot",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.fid.ipv4",
+ .description = "tl3.fid.ipv4",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.fid.ipv4",
+ .description = "tl3.fid.ipv4",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.fid.ipv6",
+ .description = "tl3.fid.ipv6",
.field_bit_size = 20,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.fid.ipv6",
+ .description = "tl3.fid.ipv6",
.field_bit_size = 20,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.qos",
+ .description = "tl3.qos",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.qos",
+ .description = "tl3.qos",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_nonext",
+ .description = "tl3.ieh_nonext",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_nonext",
+ .description = "tl3.ieh_nonext",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_esp",
+ .description = "tl3.ieh_esp",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_esp",
+ .description = "tl3.ieh_esp",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_auth",
+ .description = "tl3.ieh_auth",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_auth",
+ .description = "tl3.ieh_auth",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_dest",
+ .description = "tl3.ieh_dest",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_dest",
+ .description = "tl3.ieh_dest",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_frag",
+ .description = "tl3.ieh_frag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_frag",
+ .description = "tl3.ieh_frag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_rthdr",
+ .description = "tl3.ieh_rthdr",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_rthdr",
+ .description = "tl3.ieh_rthdr",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_hop",
+ .description = "tl3.ieh_hop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_hop",
+ .description = "tl3.ieh_hop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_1frag",
+ .description = "tl3.ieh_1frag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_1frag",
+ .description = "tl3.ieh_1frag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.df",
+ .description = "tl3.df",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.df",
+ .description = "tl3.df",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.l3err.ipv4",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.l3err.ipv4",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "l3.l3err.ipv6",
+ .description = "tl3.l3err",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.l3err.ipv6",
+ .description = "tl3.l3err",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.l4type",
+ .description = "tl4.l4type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.l4type",
+ .description = "tl4.l4type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.src",
+ .description = "tl4.src",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.src",
+ .description = "tl4.src",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.dst",
+ .description = "tl4.dst",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.dst",
+ .description = "tl4.dst",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.flags",
+ .description = "tl4.flags",
.field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.flags",
+ .description = "tl4.flags",
.field_bit_size = 9,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.seq",
+ .description = "tl4.seq",
.field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.seq",
+ .description = "tl4.seq",
.field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.ack",
- .field_bit_size = 32,
+ .description = "tl4.pa",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.ack",
- .field_bit_size = 32,
+ .description = "tl4.pa",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.win",
- .field_bit_size = 16,
+ .description = "tl4.opt",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.win",
- .field_bit_size = 16,
+ .description = "tl4.opt",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.pa",
+ .description = "tl4.tcpts",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.pa",
+ .description = "tl4.tcpts",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.opt",
- .field_bit_size = 1,
+ .description = "tl4.err",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.opt",
- .field_bit_size = 1,
+ .description = "tl4.err",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.tcpts",
- .field_bit_size = 1,
+ .description = "tuntype",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.tcpts",
- .field_bit_size = 1,
+ .description = "tuntype",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.tsval",
- .field_bit_size = 32,
+ .description = "tflags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.tsval",
- .field_bit_size = 32,
+ .description = "tflags",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4.txecr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l4.txecr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l4.err",
- .field_bit_size = 4,
+ .description = "tid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4.err",
- .field_bit_size = 4,
+ .description = "tid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
- /* class_tid: 3, , table: mac_addr_cache.rd */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "mac_addr",
+ .description = "l2_dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
},
.field_info_spec = {
- .description = "mac_addr",
+ .description = "l2_dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
}
},
- /* class_tid: 3, , table: port_table.egr.rd */
{
.field_info_mask = {
- .description = "dev.port_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- 0xff,
- 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "dev.port_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 3, , table: l2_cntxt_tcam.0 */
{
.field_info_mask = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_tpid_sel",
+ .description = "l2_ovp",
.field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovlan_tpid_sel",
+ .description = "l2_ovp",
.field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
- }
- },
- {
- .field_info_mask = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
- /* class_tid: 3, , table: mac_addr_cache.wr */
{
.field_info_mask = {
- .description = "svif",
+ .description = "l3.ttl",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "svif",
+ .description = "l3.ttl",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ (BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tun_hdr",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ULP_THOR_SYM_TUN_HDR_TYPE_NONE}
+ (BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "one_tag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "mac_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
- /* class_tid: 3, , table: profile_tcam_cache.ipv6_rd */
{
.field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "hdr_sig_id",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
- /* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */
{
.field_info_mask = {
- .description = "l4_hdr_is_udp_tcp",
+ .description = "l3.ieh_dest",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4_hdr_is_udp_tcp",
+ .description = "l3.ieh_dest",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_THOR_SYM_L4_HDR_TYPE_TCP},
- .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr3 = {
- ULP_THOR_SYM_L4_HDR_TYPE_UDP}
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4_hdr_error",
+ .description = "l3.ieh_rthdr",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4_hdr_error",
+ .description = "l3.ieh_rthdr",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l4_hdr_valid",
+ .description = "l3.ieh_hop",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l4_hdr_valid",
+ .description = "l3.ieh_hop",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "ieh",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "ieh",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3_ipv6_cmp_dst",
+ .description = "l3.df",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3_ipv6_cmp_dst",
+ .description = "l3.df",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3_ipv6_cmp_src",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3_hdr_isIP",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3_hdr_type",
+ .description = "l4.l4type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3_hdr_type",
+ .description = "l4.l4type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 0xff}
+ (BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_hdr_error",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l3_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 0xff}
+ (BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "l3_hdr_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ULP_THOR_SYM_L3_HDR_VALID_YES}
+ (BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_I_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_vtag_present",
- .field_bit_size = 1,
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam_cache.ipv6_rd */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+ }
+ },
+ /* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_TCP},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_L4_HDR_TYPE_UDP}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ },
+ .field_info_spec = {
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_TYPE_IPV6}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_L3_HDR_VALID_YES}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "l2_vtag_present",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
.field_opr1 = {
@@ -23114,17 +23608,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_spec = {
.description = "prof_func_id",
.field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
@@ -23230,17 +23716,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_spec = {
.description = "prof_func_id",
.field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
@@ -24082,12 +24560,30 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
.field_info_spec = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -24388,12 +24884,24 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
}
},
{
@@ -24773,17 +25281,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_spec = {
.description = "prof_func_id",
.field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
@@ -25425,17 +25925,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_spec = {
.description = "prof_func_id",
.field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
@@ -26095,17 +26587,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_spec = {
.description = "prof_func_id",
.field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
@@ -26211,17 +26695,9 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_spec = {
.description = "prof_func_id",
.field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
}
@@ -27063,12 +27539,30 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -27349,12 +27843,27 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -27542,47 +28051,29 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l4.src",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
.field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l4.src",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
.field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -27590,47 +28081,29 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l4.dst",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
.field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l4.dst",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
.field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_HF,
- .field_opr3 = {
- (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
+ (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -28571,12 +29044,30 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -28857,12 +29348,27 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr2 = {
+ (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -30011,12 +30517,30 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -30285,12 +30809,14 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l3.prot",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -31393,227 +31919,11 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
}
},
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
- {
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
- }
- },
- /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
- {
- .field_info_mask = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_tpid_sel",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "l2_ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
+ /* class_tid: 5, , table: port_table.egr_wr */
{
.field_info_mask = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "two_vtags",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "vtag_present",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac1_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mac0_addr",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tunnel_id",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "tun_hdr_type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "llc",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "roce",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "metadata",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
+ .description = "dev.port_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
@@ -31621,104 +31931,16 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
+ .description = "dev.port_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
- }
- },
- {
- .field_info_mask = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "loopback",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "recycle_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- .field_info_spec = {
- .description = "mpass_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- }
- },
- {
- .field_info_mask = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- .field_info_spec = {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
}
},
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
{
.field_info_mask = {
.description = "svif",
@@ -31738,67 +31960,392 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
}
},
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.rd_egr0 */
- {
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
- }
- },
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
- {
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
- }
- },
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_rd_vfr */
- {
- .field_info_mask = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
- }
- },
- /* class_tid: 5, , table: l2_cntxt_tcam.vfr_ing0 */
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.rd_egr0 */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_rd_vfr */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam.vfr_ing0 */
{
.field_info_mask = {
.description = "etype",
@@ -33860,332 +34407,1091 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
}
},
{
- .field_info_mask = {
- .description = "l3.ieh_auth",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_auth",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ }
+};
+
+struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
+ /* class_tid: 1, , table: l2_cntxt_tcam.0 */
+ {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ },
+ {
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ },
+ {
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ },
+ /* class_tid: 1, , table: mac_addr_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: fkb_select.l2_l3_l4_v6_em */
+ {
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "parif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "spif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "lcos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "loopback.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tuntype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tflags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tqos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "terr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ },
+ {
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ },
+ {
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ },
+ {
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}
+ },
+ {
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.l3err.ipv4",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.l3err.ipv4",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}
},
{
- .field_info_mask = {
- .description = "l3.l3err.ipv6",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.l3err.ipv6",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}
},
{
- .field_info_mask = {
- .description = "l4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_win.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.ack",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.ack",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.win",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.win",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */
{
- .field_info_mask = {
- .description = "l4.tsval",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.tsval",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.txecr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.txecr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- }
-};
-
-struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
- /* class_tid: 1, , table: l2_cntxt_tcam.0 */
- {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "em_key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "em_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "em_search_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ 1}
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: mac_addr_cache.wr */
+ /* class_tid: 1, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -34196,27 +35502,98 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "l2_cntxt_tcam_index",
+ .description = "profile_tcam_index",
.field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "wc_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ },
+ /* class_tid: 1, , table: em.l2_l3_l4_v6.0 */
+ {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: fkb_select.l2_l3_l4_v6_em */
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: fkb_select.l3_l4_wm */
{
.description = "l2_cntxt_id.en",
.field_bit_size = 1,
@@ -34589,10 +35966,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ 1}
},
{
.description = "l2_dt.en",
@@ -34651,22 +36027,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
{
.description = "l2_ivv.en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ 1}
},
{
.description = "l2_ivt.en",
@@ -34690,10 +36054,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ 1}
},
{
.description = "l3_sip_selcmp.en",
@@ -34705,10 +36068,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ 1}
},
{
.description = "l3_dip_selcmp.en",
@@ -34726,7 +36088,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l3_fid.en",
@@ -34810,19 +36174,17 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}
+ 1}
},
{
.description = "l4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}
+ 1}
},
{
.description = "l4_flags.en",
@@ -34884,166 +36246,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */
- {
- .description = "wc_key_id",
- .field_bit_size = 6,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "wc_search_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "em_key_type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "em_key_id",
- .field_bit_size = 6,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
- },
- {
- .description = "em_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
- },
- {
- .description = "em_search_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- {
- .description = "pl_byp_lkup_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- /* class_tid: 1, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
- {
- .description = "rid",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
- },
- {
- .description = "profile_tcam_index",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
- },
- {
- .description = "em_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
- },
- {
- .description = "em_key_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
- },
- {
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "wc_key_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "flow_sig_id",
- .field_bit_size = 64,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
- },
- /* class_tid: 1, , table: em.l2_l3_l4_v6.0 */
- {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- {
- .description = "strength",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 3}
- },
- {
- .description = "data",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
- },
- {
- .description = "opcode",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "meta_prof",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "ctxt_data",
- .field_bit_size = 14,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- /* class_tid: 1, , table: fkb_select.l3_l4_wm */
+ /* class_tid: 1, , table: fkb_select.l3_l4_wm_vxlan */
{
.description = "l2_cntxt_id.en",
.field_bit_size = 1,
@@ -35170,7 +36373,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl2_ivv.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl2_ivt.en",
@@ -35194,7 +36399,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl3_sip_selcmp.en",
@@ -35206,7 +36413,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl3_dip_selcmp.en",
@@ -35224,7 +36433,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl3_fid.en",
@@ -35308,13 +36519,17 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl4_flags.en",
@@ -35478,9 +36693,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_ivv.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l2_ivt.en",
@@ -35504,9 +36717,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l3_sip_selcmp.en",
@@ -35518,9 +36729,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l3_dip_selcmp.en",
@@ -35538,9 +36747,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l3_fid.en",
@@ -35624,17 +36831,13 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l4_flags.en",
@@ -35696,9 +36899,112 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: fkb_select.l3_l4_wm_vxlan */
+ /* class_tid: 1, , table: profile_tcam.l3_l4.ip */
{
- .description = "l2_cntxt_id.en",
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.l3_l4.vxlan */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 & 0xff}
+ },
+ {
+ .description = "wc_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -35706,1131 +37012,1203 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
1}
},
{
- .description = "parif.en",
- .field_bit_size = 1,
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "spif.en",
- .field_bit_size = 1,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "svif.en",
+ .description = "em_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "lcos.en",
+ .description = "pl_byp_lkup_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 1, , table: profile_tcam_cache.wr */
{
- .description = "meta.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "rcyc_cnt.en",
- .field_bit_size = 1,
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
},
{
- .description = "loopback.en",
- .field_bit_size = 1,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_l2type.en",
- .field_bit_size = 1,
+ .description = "em_key_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_dmac.en",
- .field_bit_size = 1,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_smac.en",
- .field_bit_size = 1,
+ .description = "wc_key_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_dt.en",
- .field_bit_size = 1,
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
+ /* class_tid: 1, , table: wm.l3_l4.ipv4 */
{
- .description = "tl2_sa.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_nvt.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovp.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovd.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl2_ovv.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 1, , table: wm.l3_l4.ipv6 */
{
- .description = "tl2_ovt.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivp.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivd.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivv.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 1, , table: wm.l3.ipv4 */
{
- .description = "tl2_ivt.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_etype.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_l3type.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_sip.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 1, , table: wm.l3.ipv6 */
{
- .description = "tl3_sip_selcmp.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_dip.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_dip_selcmp.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ttl.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl3_prot.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 1, , table: wm.l2 */
{
- .description = "tl3_fid.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_qos.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_nonext.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_esp.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl3_ieh_auth.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv4 */
{
- .description = "tl3_ieh_dest.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_frag.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_rthdr.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_hop.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl3_ieh_1frag.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv6 */
{
- .description = "tl3_df.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_l3err.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_l4type.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_src.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl4_dst.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
{
- .description = "tl4_flags.en",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_seq.en",
- .field_bit_size = 1,
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_pa.en",
- .field_bit_size = 1,
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_opt.en",
- .field_bit_size = 1,
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_tcpts.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_err.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 2, , table: tunnel_cache.wr */
{
- .description = "tuntype.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "tflags.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tids.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
+ /* class_tid: 2, , table: l2_cntxt_tcam.0 */
{
- .description = "tid.en",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
},
{
- .description = "tctxts.en",
- .field_bit_size = 1,
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tctxt.en",
- .field_bit_size = 1,
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
{
- .description = "tqos.en",
- .field_bit_size = 1,
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
},
{
- .description = "terr.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .description = "l2_l2type.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
},
+ /* class_tid: 2, , table: mac_addr_cache.wr */
{
- .description = "l2_dmac.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_smac.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 2, , table: fkb_select.f2_l2_l3_l4_v6_em */
{
- .description = "l2_dt.en",
+ .description = "l2_cntxt_id.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "l2_sa.en",
+ .description = "parif.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_nvt.en",
+ .description = "spif.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovp.en",
+ .description = "svif.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovd.en",
+ .description = "lcos.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovv.en",
+ .description = "meta.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovt.en",
+ .description = "rcyc_cnt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivp.en",
+ .description = "loopback.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivd.en",
+ .description = "tl2_l2type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivv.en",
+ .description = "tl2_dmac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivt.en",
+ .description = "tl2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_etype.en",
+ .description = "tl2_dt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_l3type.en",
+ .description = "tl2_sa.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_sip.en",
+ .description = "tl2_nvt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_sip_selcmp.en",
+ .description = "tl2_ovp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip.en",
+ .description = "tl2_ovd.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip_selcmp.en",
+ .description = "tl2_ovv.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ttl.en",
+ .description = "tl2_ovt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_prot.en",
+ .description = "tl2_ivp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_fid.en",
+ .description = "tl2_ivd.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_qos.en",
+ .description = "tl2_ivv.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_nonext.en",
+ .description = "tl2_ivt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_esp.en",
+ .description = "tl2_etype.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_auth.en",
+ .description = "tl3_l3type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_dest.en",
+ .description = "tl3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_frag.en",
+ .description = "tl3_sip_selcmp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_rthdr.en",
+ .description = "tl3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_hop.en",
+ .description = "tl3_dip_selcmp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_1frag.en",
+ .description = "tl3_ttl.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_df.en",
+ .description = "tl3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_l3err.en",
+ .description = "tl3_fid.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_l4type.en",
+ .description = "tl3_qos.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_src.en",
+ .description = "tl3_ieh_nonext.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_dst.en",
+ .description = "tl3_ieh_esp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_flags.en",
+ .description = "tl3_ieh_auth.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_seq.en",
+ .description = "tl3_ieh_dest.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_ack.en",
+ .description = "tl3_ieh_frag.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_win.en",
+ .description = "tl3_ieh_rthdr.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_pa.en",
+ .description = "tl3_ieh_hop.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_opt.en",
+ .description = "tl3_ieh_1frag.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_tcpts.en",
+ .description = "tl3_df.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_tsval.en",
+ .description = "tl3_l3err.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_txecr.en",
+ .description = "tl4_l4type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_err.en",
+ .description = "tl4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam.l3_l4.ip */
{
- .description = "wc_key_id",
- .field_bit_size = 6,
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_search_en",
+ .description = "tl4_seq.en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_type",
- .field_bit_size = 2,
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 6,
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_search_en",
+ .description = "tl4_err.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "pl_byp_lkup_en",
+ .description = "tuntype.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam.l3_l4.vxlan */
{
- .description = "wc_key_id",
- .field_bit_size = 6,
+ .description = "tflags.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 & 0xff}
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}
},
{
- .description = "wc_search_en",
+ .description = "tid.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_type",
- .field_bit_size = 2,
+ .description = "tctxts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 6,
+ .description = "tctxt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "tqos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_search_en",
+ .description = "terr.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "pl_byp_lkup_en",
+ .description = "l2_l2type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam_cache.wr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ 1}
},
{
- .description = "profile_tcam_index",
- .field_bit_size = 10,
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 8,
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_key_id",
- .field_bit_size = 8,
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "flow_sig_id",
- .field_bit_size = 64,
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l3_l4.ipv4 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l3_l4.ipv6 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}
},
- /* class_tid: 1, , table: wm.l3.ipv4 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff}
+ },
+ {
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l3.ipv6 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l2 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l3_df.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ (BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff}
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff}
},
- /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv4 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l4_win.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv6 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l4_err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: l2_cntxt_tcam.1 */
+ /* class_tid: 2, , table: profile_tcam.f2_l2_l3_l4_v6_em */
{
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "wc_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "wc_search_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "em_key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "em_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: tunnel_cache.wr */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_l2_l3_l4_v6_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -36841,99 +38219,94 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "l2_cntxt_tcam_index",
+ .description = "profile_tcam_index",
.field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
},
- /* class_tid: 2, , table: l2_cntxt_tcam.0 */
{
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "em_key_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "wc_key_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
+ /* class_tid: 2, , table: em.f2_l2_l3_l4_v6.0 */
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ 1}
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ 3}
},
- /* class_tid: 2, , table: mac_addr_cache.wr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "l2_cntxt_tcam_index",
- .field_bit_size = 10,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -37100,9 +38473,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "tl3_dip_selcmp.en",
@@ -37316,7 +38687,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l2_dt.en",
@@ -37400,7 +38773,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l3_sip_selcmp.en",
@@ -37432,7 +38807,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l3_fid.en",
@@ -37516,13 +38893,17 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l4_flags.en",
@@ -37743,127 +39124,6 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 2, , table: wm.l3_l4.ipv6 */
- {
- .description = "ctxt_data",
- .field_bit_size = 14,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "meta_prof",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "opcode",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "data",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
- },
- {
- .description = "strength",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- /* class_tid: 3, , table: l2_cntxt_tcam.0 */
- {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}
- },
- {
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "def_ctxt_data",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
- },
- {
- .description = "ctxt_opcode",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
- },
- {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
- },
- {
- .description = "parif",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
- },
- /* class_tid: 3, , table: mac_addr_cache.wr */
- {
- .description = "rid",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
- },
- {
- .description = "l2_cntxt_tcam_index",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
- },
- {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
- },
- {
- .description = "src_property_ptr",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
/* class_tid: 3, , table: fkb_select.l2_l3_l4_v6_em */
{
.description = "l2_cntxt_id.en",
@@ -38240,7 +39500,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
},
{
.description = "l2_dt.en",
@@ -38374,7 +39637,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}
},
{
.description = "l3_fid.en",
@@ -39066,7 +40332,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l2_dt.en",
@@ -39186,7 +40454,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "l3_fid.en",
@@ -39663,7 +40933,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -39910,7 +41182,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -40050,7 +41324,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "parif",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
},
{
.description = "reserved",
@@ -40238,7 +41515,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -40299,6 +41578,43 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
+ /* class_tid: 5, , table: port_table.egr_wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drv_func.mac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drv_func.parent.mac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff}
+ },
+ {
+ .description = "phy_port",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "default_arec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
+ },
/* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
{
.description = "prof_func_id",
@@ -40450,7 +41766,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -40610,7 +41928,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "parif",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
},
{
.description = "reserved",
@@ -40970,7 +42291,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -41772,6 +43095,34 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_wr_vfr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
/* class_tid: 5, , table: int_full_act_record.vfr_ing0 */
{
.description = "sp_rec_ptr",
@@ -41819,7 +43170,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "stats_ptr",
@@ -42058,7 +43411,13 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 42
},
- /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_ipv6_rd */
+ {
+ .description = "em_key_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_KEY_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 50
+ },
{
.description = "em_profile_id",
.regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
@@ -42077,47 +43436,40 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 32
},
- /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
+ /* class_tid: 2, , table: profile_tcam.f2_l2_l3_l4_v6_em */
{
- .description = "l2_cntxt_id",
- .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
- .ident_bit_size = 10,
- .ident_bit_pos = 42
+ .description = "em_profile_id",
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_EM_PROF,
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 23
},
- /* class_tid: 3, , table: mac_addr_cache.rd */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_rd */
{
- .description = "l2_cntxt_id",
- .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
- .ident_bit_size = 10,
+ .description = "em_profile_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+ .ident_bit_size = 8,
.ident_bit_pos = 42
},
- /* class_tid: 3, , table: port_table.egr.rd */
- {
- .description = "default_arec_ptr",
- .regfile_idx = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
- .ident_bit_size = 16,
- .ident_bit_pos = 136
- },
{
- .description = "drv_func.parent.mac",
- .regfile_idx = BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC,
- .ident_bit_size = 48,
- .ident_bit_pos = 80
+ .description = "flow_sig_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+ .ident_bit_size = 64,
+ .ident_bit_pos = 74
},
{
- .description = "phy_port",
- .regfile_idx = BNXT_ULP_RF_IDX_PHY_PORT,
- .ident_bit_size = 8,
- .ident_bit_pos = 128
+ .description = "profile_tcam_index",
+ .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
},
- /* class_tid: 3, , table: l2_cntxt_tcam.0 */
+ /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */
{
.description = "l2_cntxt_id",
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
- .ident_bit_pos = 29
+ .ident_bit_pos = 42
},
/* class_tid: 3, , table: profile_tcam_cache.ipv6_rd */
{
@@ -42168,36 +43520,29 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
},
/* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
- .description = "l2_cntxt_id",
+ .description = "l2_cntxt_id_low",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 29
},
/* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
- .description = "l2_cntxt_id",
+ .description = "l2_cntxt_id_low",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 29
},
/* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
{
- .description = "l2_cntxt_id",
+ .description = "l2_cntxt_id_low",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 29
- },
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_wr_vfr */
- {
- .description = "rid",
- .regfile_idx = BNXT_ULP_RF_IDX_RID,
- .ident_bit_size = 32,
- .ident_bit_pos = 0
}
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
index 2870a0615a..4b9cb7fd5b 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Wed Jun 30 14:36:16 2021 */
+/* date: Wed Aug 11 16:00:16 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -16741,27 +16741,27 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
},
/* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
- .description = "l2_cntxt_id",
+ .description = "l2_cntxt_id_low",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 0
},
/* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
- .description = "l2_cntxt_id",
+ .description = "l2_cntxt_id_low",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 0
},
/* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
{
- .description = "l2_cntxt_id",
+ .description = "l2_cntxt_id_low",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 0
diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
index c6b2b1675d..7b6db7a0f8 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
@@ -75,9 +75,9 @@ ulp_mapper_generic_tbl_list_init(struct bnxt_ulp_mapper_data *mapper_data)
entry->container.byte_data = &entry->mem_data[size];
entry->container.byte_order = tbl->result_byte_order;
} else {
- BNXT_TF_DBG(ERR, "%s:Invalid gen table num of ent %d\n",
+ BNXT_TF_DBG(DEBUG, "%s: Unused Gen tbl entry is %d\n",
tbl->name, idx);
- return -EINVAL;
+ /* return -EINVAL; */
}
if (tbl->hash_tbl_entries) {
cparams.key_size = tbl->key_num_bytes;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 234f7ea2fa..059ee99837 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -438,6 +438,77 @@ ulp_mapper_ident_fields_get(struct bnxt_ulp_mapper_parms *mparms,
return &dev_tbls->ident_list[idx];
}
+static enum tf_tbl_type
+ulp_mapper_dyn_tbl_type_get(struct bnxt_ulp_mapper_parms *mparms,
+ struct bnxt_ulp_mapper_tbl_info *tbl,
+ struct ulp_blob *bdata,
+ uint16_t *out_len)
+{
+ struct bnxt_ulp_device_params *d_params = mparms->device_params;
+ uint16_t blob_len = ulp_blob_data_len_get(bdata);
+ struct bnxt_ulp_dyn_size_map *size_map;
+ uint32_t i;
+
+ if (d_params->dynamic_sram_en) {
+ switch (tbl->resource_type) {
+ case TF_TBL_TYPE_ACT_ENCAP_8B:
+ case TF_TBL_TYPE_ACT_ENCAP_16B:
+ case TF_TBL_TYPE_ACT_ENCAP_32B:
+ case TF_TBL_TYPE_ACT_ENCAP_64B:
+ size_map = d_params->dyn_encap_sizes;
+ for (i = 0; i < d_params->dyn_encap_list_size; i++) {
+ if (blob_len <= size_map[i].slab_size) {
+ *out_len = size_map[i].slab_size;
+ return size_map[i].tbl_type;
+ }
+ }
+ break;
+ case TF_TBL_TYPE_ACT_MODIFY_8B:
+ case TF_TBL_TYPE_ACT_MODIFY_16B:
+ case TF_TBL_TYPE_ACT_MODIFY_32B:
+ case TF_TBL_TYPE_ACT_MODIFY_64B:
+ size_map = d_params->dyn_modify_sizes;
+ for (i = 0; i < d_params->dyn_modify_list_size; i++) {
+ if (blob_len <= size_map[i].slab_size) {
+ *out_len = size_map[i].slab_size;
+ return size_map[i].tbl_type;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ }
+ return tbl->resource_type;
+}
+
+static uint16_t
+ulp_mapper_dyn_blob_size_get(struct bnxt_ulp_mapper_parms *mparms,
+ struct bnxt_ulp_mapper_tbl_info *tbl)
+{
+ struct bnxt_ulp_device_params *d_params = mparms->device_params;
+
+ if (d_params->dynamic_sram_en) {
+ switch (tbl->resource_type) {
+ case TF_TBL_TYPE_ACT_ENCAP_8B:
+ case TF_TBL_TYPE_ACT_ENCAP_16B:
+ case TF_TBL_TYPE_ACT_ENCAP_32B:
+ case TF_TBL_TYPE_ACT_ENCAP_64B:
+ case TF_TBL_TYPE_ACT_MODIFY_8B:
+ case TF_TBL_TYPE_ACT_MODIFY_16B:
+ case TF_TBL_TYPE_ACT_MODIFY_32B:
+ case TF_TBL_TYPE_ACT_MODIFY_64B:
+ /* return max size */
+ return BNXT_ULP_FLMP_BLOB_SIZE_IN_BITS;
+ default:
+ break;
+ }
+ } else if (tbl->encap_num_fields) {
+ return BNXT_ULP_FLMP_BLOB_SIZE_IN_BITS;
+ }
+ return tbl->result_bit_size;
+}
+
static inline int32_t
ulp_mapper_tcam_entry_free(struct bnxt_ulp_context *ulp,
struct tf *tfp,
@@ -1562,7 +1633,8 @@ ulp_mapper_tbl_result_build(struct bnxt_ulp_mapper_parms *parms,
if (encap_flds) {
uint32_t pad = 0;
/* Initialize the encap blob */
- if (!tbl->record_size) {
+ if (!tbl->record_size &&
+ !parms->device_params->dynamic_sram_en) {
BNXT_TF_DBG(ERR, "Encap tbl record size incorrect\n");
return -EINVAL;
}
@@ -1583,9 +1655,21 @@ ulp_mapper_tbl_result_build(struct bnxt_ulp_mapper_parms *parms,
}
}
/* add the dynamic pad push */
- pad = ULP_BYTE_2_BITS(tbl->record_size) -
- ulp_blob_data_len_get(&encap_blob);
- ulp_blob_pad_push(&encap_blob, pad);
+ if (parms->device_params->dynamic_sram_en) {
+ uint16_t rec_s = ULP_BYTE_2_BITS(tbl->record_size);
+
+ (void)ulp_mapper_dyn_tbl_type_get(parms, tbl,
+ &encap_blob, &rec_s);
+ pad = rec_s - ulp_blob_data_len_get(&encap_blob);
+ } else {
+ pad = ULP_BYTE_2_BITS(tbl->record_size) -
+ ulp_blob_data_len_get(&encap_blob);
+ }
+ if (ulp_blob_pad_push(&encap_blob, pad) < 0) {
+ BNXT_TF_DBG(ERR, "encap buffer padding failed\n");
+ return -EINVAL;
+ }
+
/* perform the 64 bit byte swap */
ulp_blob_perform_64B_byte_swap(&encap_blob);
@@ -2411,13 +2495,11 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
bool global = false;
uint64_t act_rec_size;
bool shared = false;
+ enum tf_tbl_type tbl_type = tbl->resource_type;
tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session);
- /* use the max size if encap is enabled */
- if (tbl->encap_num_fields)
- bit_size = BNXT_ULP_FLMP_BLOB_SIZE_IN_BITS;
- else
- bit_size = tbl->result_bit_size;
+ /* compute the blob size */
+ bit_size = ulp_mapper_dyn_blob_size_get(parms, tbl);
/* Initialize the blob data */
if (!ulp_blob_init(&data, bit_size,
@@ -2526,7 +2608,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
gparms.dir = tbl->direction;
gparms.type = tbl->resource_type;
gparms.data = ulp_blob_data_get(&data, &tmplen);
- gparms.data_sz_in_bytes = ULP_BITS_2_BYTE(tbl->result_bit_size);
+ gparms.data_sz_in_bytes = ULP_BITS_2_BYTE(tmplen);
gparms.idx = index;
rc = tf_get_tbl_entry(tfp, &gparms);
if (rc) {
@@ -2568,14 +2650,16 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
if (alloc) {
aparms.dir = tbl->direction;
- aparms.type = tbl->resource_type;
+ tbl_type = ulp_mapper_dyn_tbl_type_get(parms, tbl,
+ &data, &tmplen);
+ aparms.type = tbl_type;
aparms.tbl_scope_id = tbl_scope_id;
/* All failures after the alloc succeeds require a free */
rc = tf_alloc_tbl_entry(tfp, &aparms);
if (rc) {
BNXT_TF_DBG(ERR, "Alloc table[%s][%s] failed rc=%d\n",
- tf_tbl_type_2_str(tbl->resource_type),
+ tf_tbl_type_2_str(aparms.type),
tf_dir_2_str(tbl->direction), rc);
return rc;
}
@@ -2619,8 +2703,10 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
if (write) {
sparms.dir = tbl->direction;
- sparms.type = tbl->resource_type;
sparms.data = ulp_blob_data_get(&data, &tmplen);
+ tbl_type = ulp_mapper_dyn_tbl_type_get(parms, tbl, &data,
+ &tmplen);
+ sparms.type = tbl_type;
sparms.data_sz_in_bytes = ULP_BITS_2_BYTE(tmplen);
sparms.idx = index;
sparms.tbl_scope_id = tbl_scope_id;
@@ -2655,7 +2741,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
memset(&fid_parms, 0, sizeof(fid_parms));
fid_parms.direction = tbl->direction;
fid_parms.resource_func = tbl->resource_func;
- fid_parms.resource_type = tbl->resource_type;
+ fid_parms.resource_type = tbl_type;
fid_parms.resource_sub_type = tbl->resource_sub_type;
fid_parms.resource_hndl = index;
fid_parms.critical_resource = tbl->critical_resource;
@@ -2684,7 +2770,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
* write to the entry or link the flow
*/
free_parms.dir = tbl->direction;
- free_parms.type = tbl->resource_type;
+ free_parms.type = tbl_type;
free_parms.idx = index;
free_parms.tbl_scope_id = tbl_scope_id;
@@ -2862,8 +2948,7 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms,
cache_key = ulp_blob_data_get(&key, &tmplen);
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER
- BNXT_TF_DBG(DEBUG, "The gen_tbl[%u] key\n", tbl_idx);
- ulp_mapper_blob_dump(&key);
+ ulp_mapper_gen_tbl_dump(tbl->resource_sub_type, tbl->direction, &key);
#endif
#endif
/* get the generic table */
@@ -3310,18 +3395,10 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms,
*res = regval == 0;
break;
case BNXT_ULP_COND_OPC_FLOW_PAT_MATCH:
- if (parms->flow_pattern_id == operand) {
- BNXT_TF_DBG(ERR, "field pattern match failed %x\n",
- parms->flow_pattern_id);
- return -EINVAL;
- }
+ *res = parms->flow_pattern_id == operand;
break;
case BNXT_ULP_COND_OPC_ACT_PAT_MATCH:
- if (parms->act_pattern_id == operand) {
- BNXT_TF_DBG(ERR, "act pattern match failed %x\n",
- parms->act_pattern_id);
- return -EINVAL;
- }
+ *res = parms->act_pattern_id == operand;
break;
case BNXT_ULP_COND_OPC_EXT_MEM_IS_SET:
if (bnxt_ulp_cntxt_mem_type_get(parms->ulp_ctx, &mtype)) {
@@ -3507,7 +3584,6 @@ ulp_mapper_func_info_process(struct bnxt_ulp_mapper_parms *parms,
return rc;
}
-
/*
* Processes a list of conditions and returns both a status and result of the
* list. The status must be checked prior to verifying the result.
@@ -3863,8 +3939,7 @@ ulp_mapper_resources_free(struct bnxt_ulp_context *ulp_ctx,
* Set the critical resource on the first resource del, then iterate
* while status is good
*/
- if (flow_type != BNXT_ULP_FDB_TYPE_RID)
- res_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES;
+ res_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES;
rc = ulp_flow_db_resource_del(ulp_ctx, flow_type, fid, &res_parms);
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index dce95de05c..3a9c9bba27 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -1226,20 +1226,66 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
/* Function to handle the update of proto header based on field values */
static void
-ulp_rte_l4_proto_type_update(struct ulp_rte_parser_params *param,
- uint16_t dst_port)
-{
- if (dst_port == tfp_cpu_to_be_16(ULP_UDP_PORT_VXLAN)) {
- ULP_BITMAP_SET(param->hdr_fp_bit.bits,
- BNXT_ULP_HDR_BIT_T_VXLAN);
- ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_L3_TUN, 1);
+ulp_rte_l4_proto_type_update(struct ulp_rte_parser_params *params,
+ uint16_t src_port, uint16_t src_mask,
+ uint16_t dst_port, uint16_t dst_mask,
+ enum bnxt_ulp_hdr_bit hdr_bit)
+{
+ switch (hdr_bit) {
+ case BNXT_ULP_HDR_BIT_I_UDP:
+ case BNXT_ULP_HDR_BIT_I_TCP:
+ ULP_BITMAP_SET(params->hdr_bitmap.bits, hdr_bit);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4, 1);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_SRC_PORT,
+ (uint64_t)rte_be_to_cpu_16(src_port));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_DST_PORT,
+ (uint64_t)rte_be_to_cpu_16(dst_port));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK,
+ (uint64_t)rte_be_to_cpu_16(src_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK,
+ (uint64_t)rte_be_to_cpu_16(dst_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID,
+ 1);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT,
+ !!(src_port & src_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT,
+ !!(dst_port & dst_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_PROTO_ID,
+ (hdr_bit == BNXT_ULP_HDR_BIT_I_UDP) ?
+ IPPROTO_UDP : IPPROTO_TCP);
+ break;
+ case BNXT_ULP_HDR_BIT_O_UDP:
+ case BNXT_ULP_HDR_BIT_O_TCP:
+ ULP_BITMAP_SET(params->hdr_bitmap.bits, hdr_bit);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4, 1);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_SRC_PORT,
+ (uint64_t)rte_be_to_cpu_16(src_port));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DST_PORT,
+ (uint64_t)rte_be_to_cpu_16(dst_port));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK,
+ (uint64_t)rte_be_to_cpu_16(src_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK,
+ (uint64_t)rte_be_to_cpu_16(dst_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID,
+ 1);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT,
+ !!(src_port & src_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT,
+ !!(dst_port & dst_mask));
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_PROTO_ID,
+ (hdr_bit == BNXT_ULP_HDR_BIT_O_UDP) ?
+ IPPROTO_UDP : IPPROTO_TCP);
+ break;
+ default:
+ break;
}
- if (ULP_BITMAP_ISSET(param->hdr_bitmap.bits,
- BNXT_ULP_HDR_BIT_T_VXLAN) ||
- ULP_BITMAP_ISSET(param->hdr_bitmap.bits,
- BNXT_ULP_HDR_BIT_T_GRE))
- ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_L3_TUN, 1);
+ if (hdr_bit == BNXT_ULP_HDR_BIT_O_UDP && dst_port ==
+ tfp_cpu_to_be_16(ULP_UDP_PORT_VXLAN)) {
+ ULP_BITMAP_SET(params->hdr_fp_bit.bits,
+ BNXT_ULP_HDR_BIT_T_VXLAN);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN, 1);
+ }
}
/* Function to handle the parsing of RTE Flow item UDP Header. */
@@ -1253,7 +1299,9 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item,
uint32_t idx = 0;
uint32_t size;
uint16_t dport = 0, sport = 0;
+ uint16_t dport_mask = 0, sport_mask = 0;
uint32_t cnt;
+ enum bnxt_ulp_hdr_bit out_l4 = BNXT_ULP_HDR_BIT_O_UDP;
cnt = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L4_HDR_CNT);
if (cnt == 2) {
@@ -1265,6 +1313,10 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item,
sport = udp_spec->hdr.src_port;
dport = udp_spec->hdr.dst_port;
}
+ if (udp_mask) {
+ sport_mask = udp_mask->hdr.src_port;
+ dport_mask = udp_mask->hdr.dst_port;
+ }
if (ulp_rte_prsr_fld_size_validate(params, &idx,
BNXT_ULP_PROTO_HDR_UDP_NUM)) {
@@ -1302,48 +1354,11 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item,
/* Set the udp header bitmap and computed l4 header bitmaps */
if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP) ||
- ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP)) {
- ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_UDP);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4, 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_SRC_PORT,
- (uint32_t)rte_be_to_cpu_16(sport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_DST_PORT,
- (uint32_t)rte_be_to_cpu_16(dport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID,
- 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_PROTO_ID,
- IPPROTO_UDP);
- if (udp_mask && udp_mask->hdr.src_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT,
- 1);
- if (udp_mask && udp_mask->hdr.dst_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT,
- 1);
- } else {
- ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4, 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_SRC_PORT,
- (uint32_t)rte_be_to_cpu_16(sport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DST_PORT,
- (uint32_t)rte_be_to_cpu_16(dport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID,
- 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_PROTO_ID,
- IPPROTO_UDP);
- if (udp_mask && udp_mask->hdr.src_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT,
- 1);
- if (udp_mask && udp_mask->hdr.dst_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT,
- 1);
+ ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP))
+ out_l4 = BNXT_ULP_HDR_BIT_I_UDP;
- /* Update the field protocol hdr bitmap */
- ulp_rte_l4_proto_type_update(params, dport);
- }
+ ulp_rte_l4_proto_type_update(params, sport, sport_mask, dport,
+ dport_mask, out_l4);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L4_HDR_CNT, ++cnt);
return BNXT_TF_RC_SUCCESS;
}
@@ -1358,8 +1373,10 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item,
struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap;
uint32_t idx = 0;
uint16_t dport = 0, sport = 0;
+ uint16_t dport_mask = 0, sport_mask = 0;
uint32_t size;
uint32_t cnt;
+ enum bnxt_ulp_hdr_bit out_l4 = BNXT_ULP_HDR_BIT_O_TCP;
cnt = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L4_HDR_CNT);
if (cnt == 2) {
@@ -1371,6 +1388,10 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item,
sport = tcp_spec->hdr.src_port;
dport = tcp_spec->hdr.dst_port;
}
+ if (tcp_mask) {
+ sport_mask = tcp_mask->hdr.src_port;
+ dport_mask = tcp_mask->hdr.dst_port;
+ }
if (ulp_rte_prsr_fld_size_validate(params, &idx,
BNXT_ULP_PROTO_HDR_TCP_NUM)) {
@@ -1438,45 +1459,11 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item,
/* Set the udp header bitmap and computed l4 header bitmaps */
if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP) ||
- ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP)) {
- ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_TCP);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4, 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_SRC_PORT,
- (uint32_t)rte_be_to_cpu_16(sport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_DST_PORT,
- (uint32_t)rte_be_to_cpu_16(dport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID,
- 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_PROTO_ID,
- IPPROTO_TCP);
- if (tcp_mask && tcp_mask->hdr.src_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT,
- 1);
- if (tcp_mask && tcp_mask->hdr.dst_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT,
- 1);
- } else {
- ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4, 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_SRC_PORT,
- (uint32_t)rte_be_to_cpu_16(sport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DST_PORT,
- (uint32_t)rte_be_to_cpu_16(dport));
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID,
- 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_PROTO_ID,
- IPPROTO_TCP);
- if (tcp_mask && tcp_mask->hdr.src_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT,
- 1);
- if (tcp_mask && tcp_mask->hdr.dst_port)
- ULP_COMP_FLD_IDX_WR(params,
- BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT,
- 1);
- }
+ ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP))
+ out_l4 = BNXT_ULP_HDR_BIT_I_TCP;
+
+ ulp_rte_l4_proto_type_update(params, sport, sport_mask, dport,
+ dport_mask, out_l4);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L4_HDR_CNT, ++cnt);
return BNXT_TF_RC_SUCCESS;
}
@@ -1528,7 +1515,7 @@ ulp_rte_vxlan_hdr_handler(const struct rte_flow_item *item,
/* Update the hdr_bitmap with vxlan */
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_T_VXLAN);
- ulp_rte_l4_proto_type_update(params, 0);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN, 1);
return BNXT_TF_RC_SUCCESS;
}
@@ -1563,7 +1550,7 @@ ulp_rte_gre_hdr_handler(const struct rte_flow_item *item,
/* Update the hdr_bitmap with GRE */
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_T_GRE);
- ulp_rte_l4_proto_type_update(params, 0);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN, 1);
return BNXT_TF_RC_SUCCESS;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index 1683cd7ec4..d3bfb8c12d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -206,6 +206,11 @@ struct bnxt_ulp_template_device_tbls {
uint32_t cond_list_size;
};
+struct bnxt_ulp_dyn_size_map {
+ uint32_t slab_size;
+ enum tf_tbl_type tbl_type;
+};
+
/* Device specific parameters */
struct bnxt_ulp_device_params {
uint8_t description[16];
@@ -229,6 +234,11 @@ struct bnxt_ulp_device_params {
uint32_t byte_count_shift;
uint32_t packet_count_shift;
uint32_t dynamic_pad_en;
+ uint32_t dynamic_sram_en;
+ uint32_t dyn_encap_list_size;
+ struct bnxt_ulp_dyn_size_map dyn_encap_sizes[4];
+ uint32_t dyn_modify_list_size;
+ struct bnxt_ulp_dyn_size_map dyn_modify_sizes[4];
uint16_t em_blk_size_bits;
uint16_t em_blk_align_bits;
uint16_t em_key_align_bytes;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c
index 686b80e456..df3afaa6fd 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c
@@ -882,7 +882,8 @@ ulp_blob_msb_block_merge(struct ulp_blob *dst, struct ulp_blob *src,
for (i = 0; i < num;) {
if (((dst->write_idx % block_size) + (num - i)) > block_size)
- write_bytes = block_size - dst->write_idx;
+ write_bytes = block_size -
+ (dst->write_idx % block_size);
else
write_bytes = num - i;
for (k = 0; k < ULP_BITS_2_BYTE_NR(write_bytes); k++) {
--
2.17.1
^ permalink raw reply [flat|nested] 83+ messages in thread* Re: [dpdk-dev] [PATCH v4 00/13] enhancements to host based flow table management
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 " Venkat Duvvuru
` (12 preceding siblings ...)
2021-09-20 7:42 ` [dpdk-dev] [PATCH v4 13/13] net/bnxt: add enhancements to TF ULP Venkat Duvvuru
@ 2021-09-21 4:50 ` Ajit Khaparde
2021-09-22 17:36 ` Ferruh Yigit
13 siblings, 1 reply; 83+ messages in thread
From: Ajit Khaparde @ 2021-09-21 4:50 UTC (permalink / raw)
To: Venkat Duvvuru, Ferruh Yigit; +Cc: dpdk-dev
[-- Attachment #1: Type: text/plain, Size: 5385 bytes --]
On Mon, Sep 20, 2021 at 12:42 AM Venkat Duvvuru
<venkatkumar.duvvuru@broadcom.com> wrote:
>
> This patch set adds support for new offload features/enhancments for
> Thor adapters like VF representor support, new flow matches/actions
> & dynamic SRAM manager support.
>
> Farah Smith (4):
> net/bnxt: updates to TF core index table
> net/bnxt: add SRAM manager model
> net/bnxt: change log level to debug
> net/bnxt: add SRAM manager shared session
>
> Jay Ding (1):
> net/bnxt: add flow meter drop counter support
>
> Kishore Padmanabha (6):
> net/bnxt: add flow template support for Thor
> net/bnxt: add support for tunnel offload API
> net/bnxt: add support for dynamic encap action
> net/bnxt: add wild card TCAM byte order for Thor
> net/bnxt: add flow templates for Thor
> net/bnxt: add enhancements to TF ULP
>
> Peter Spreadborough (1):
> net/bnxt: enable dpool allocator
>
> Randy Schacher (1):
> net/bnxt: dynamically allocate space for EM defrag function
For the patchset,
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Patchset applied to dpdk-next-net-brcm.
1) Changed instance of TF to TRUFLOW during merge in patch 1/13 and 13/13.
Please apply to dpdk-next-net. Thanks
>
> doc/guides/rel_notes/release_21_11.rst | 6 +
> drivers/net/bnxt/tf_core/cfa_resource_types.h | 5 +-
> drivers/net/bnxt/tf_core/dpool.c | 38 +-
> drivers/net/bnxt/tf_core/ll.c | 3 +
> drivers/net/bnxt/tf_core/ll.h | 50 +-
> drivers/net/bnxt/tf_core/meson.build | 2 +
> drivers/net/bnxt/tf_core/tf_core.c | 169 +-
> drivers/net/bnxt/tf_core/tf_core.h | 159 +-
> drivers/net/bnxt/tf_core/tf_device.c | 40 +-
> drivers/net/bnxt/tf_core/tf_device.h | 137 +-
> drivers/net/bnxt/tf_core/tf_device_p4.c | 77 +-
> drivers/net/bnxt/tf_core/tf_device_p4.h | 50 +-
> drivers/net/bnxt/tf_core/tf_device_p58.c | 112 +-
> drivers/net/bnxt/tf_core/tf_device_p58.h | 70 +-
> drivers/net/bnxt/tf_core/tf_em.h | 10 -
> drivers/net/bnxt/tf_core/tf_em_common.c | 4 +
> .../net/bnxt/tf_core/tf_em_hash_internal.c | 34 -
> drivers/net/bnxt/tf_core/tf_em_internal.c | 185 +-
> drivers/net/bnxt/tf_core/tf_msg.c | 2 +-
> drivers/net/bnxt/tf_core/tf_rm.c | 180 +-
> drivers/net/bnxt/tf_core/tf_rm.h | 62 +-
> drivers/net/bnxt/tf_core/tf_session.c | 56 +
> drivers/net/bnxt/tf_core/tf_session.h | 58 +-
> drivers/net/bnxt/tf_core/tf_sram_mgr.c | 971 +
> drivers/net/bnxt/tf_core/tf_sram_mgr.h | 317 +
> drivers/net/bnxt/tf_core/tf_tbl.c | 259 +-
> drivers/net/bnxt/tf_core/tf_tbl.h | 87 +-
> drivers/net/bnxt/tf_core/tf_tbl_sram.c | 747 +
> drivers/net/bnxt/tf_core/tf_tbl_sram.h | 154 +
> drivers/net/bnxt/tf_core/tf_tcam.c | 16 +-
> drivers/net/bnxt/tf_core/tf_tcam.h | 7 +
> drivers/net/bnxt/tf_core/tf_tcam_shared.c | 28 +-
> drivers/net/bnxt/tf_core/tf_util.c | 12 +
> drivers/net/bnxt/tf_ulp/bnxt_tf_common.h | 10 +-
> drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 52 +-
> drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 20 +-
> drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 226 +-
> .../bnxt/tf_ulp/generic_templates/meson.build | 3 +
> .../generic_templates/ulp_template_db_act.c | 2 +-
> .../generic_templates/ulp_template_db_class.c | 12109 +++-
> .../generic_templates/ulp_template_db_enum.h | 618 +-
> .../generic_templates/ulp_template_db_field.h | 767 +-
> .../generic_templates/ulp_template_db_tbl.c | 2757 +-
> .../ulp_template_db_thor_act.c | 5079 +-
> .../ulp_template_db_thor_class.c | 45573 ++++++++++++++--
> .../ulp_template_db_wh_plus_act.c | 1700 +-
> .../ulp_template_db_wh_plus_class.c | 8329 ++-
> drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 48 +-
> drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h | 8 +-
> drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 678 +-
> drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 68 +-
> drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c | 9 +-
> drivers/net/bnxt/tf_ulp/ulp_mapper.c | 448 +-
> drivers/net/bnxt/tf_ulp/ulp_mapper.h | 10 +-
> drivers/net/bnxt/tf_ulp/ulp_matcher.c | 13 +
> drivers/net/bnxt/tf_ulp/ulp_port_db.c | 15 +-
> drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c | 31 +
> drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 663 +-
> drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 12 +-
> drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 32 +-
> drivers/net/bnxt/tf_ulp/ulp_tun.c | 521 +-
> drivers/net/bnxt/tf_ulp/ulp_tun.h | 89 +-
> drivers/net/bnxt/tf_ulp/ulp_utils.c | 71 +-
> drivers/net/bnxt/tf_ulp/ulp_utils.h | 27 +-
> 64 files changed, 71146 insertions(+), 12949 deletions(-)
> create mode 100644 drivers/net/bnxt/tf_core/tf_sram_mgr.c
> create mode 100644 drivers/net/bnxt/tf_core/tf_sram_mgr.h
> create mode 100644 drivers/net/bnxt/tf_core/tf_tbl_sram.c
> create mode 100644 drivers/net/bnxt/tf_core/tf_tbl_sram.h
>
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 83+ messages in thread* Re: [dpdk-dev] [PATCH v4 00/13] enhancements to host based flow table management
2021-09-21 4:50 ` [dpdk-dev] [PATCH v4 00/13] enhancements to host based flow table management Ajit Khaparde
@ 2021-09-22 17:36 ` Ferruh Yigit
2021-09-22 20:21 ` Ajit Khaparde
0 siblings, 1 reply; 83+ messages in thread
From: Ferruh Yigit @ 2021-09-22 17:36 UTC (permalink / raw)
To: Ajit Khaparde, Venkat Duvvuru; +Cc: dpdk-dev, David Marchand, Aaron Conole
On 9/21/2021 5:50 AM, Ajit Khaparde wrote:
> On Mon, Sep 20, 2021 at 12:42 AM Venkat Duvvuru
> <venkatkumar.duvvuru@broadcom.com> wrote:
>>
>> This patch set adds support for new offload features/enhancments for
>> Thor adapters like VF representor support, new flow matches/actions
>> & dynamic SRAM manager support.
>>
>> Farah Smith (4):
>> net/bnxt: updates to TF core index table
>> net/bnxt: add SRAM manager model
>> net/bnxt: change log level to debug
>> net/bnxt: add SRAM manager shared session
>>
>> Jay Ding (1):
>> net/bnxt: add flow meter drop counter support
>>
>> Kishore Padmanabha (6):
>> net/bnxt: add flow template support for Thor
>> net/bnxt: add support for tunnel offload API
>> net/bnxt: add support for dynamic encap action
>> net/bnxt: add wild card TCAM byte order for Thor
>> net/bnxt: add flow templates for Thor
>> net/bnxt: add enhancements to TF ULP
>>
>> Peter Spreadborough (1):
>> net/bnxt: enable dpool allocator
>>
>> Randy Schacher (1):
>> net/bnxt: dynamically allocate space for EM defrag function
>
> For the patchset,
> Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
>
> Patchset applied to dpdk-next-net-brcm.
> 1) Changed instance of TF to TRUFLOW during merge in patch 1/13 and 13/13.
>
> Please apply to dpdk-next-net. Thanks
>
Hi Ajit,
The github actions fails on build for gcc, please check it on my personal github
repo:
https://github.com/ferruhy/dpdk/actions/runs/1262767538
I don't have this error in my environment, this can be related to the slightly
older compiler in the github (gcc 7.5)
Can you please check the build error? I will keep the set in next-net for now,
but won't mark it to pull to main until issue is resolved.
If the fix is trivial, we can update it in the next-net (after issue recorded in
mail list), if it is not trivial may require a new version of the set.
btw, in git history 'TruFlow' is used, so I continue to use it, fyi.
Thanks,
ferruh
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [dpdk-dev] [PATCH v4 00/13] enhancements to host based flow table management
2021-09-22 17:36 ` Ferruh Yigit
@ 2021-09-22 20:21 ` Ajit Khaparde
2021-09-23 7:19 ` Ferruh Yigit
0 siblings, 1 reply; 83+ messages in thread
From: Ajit Khaparde @ 2021-09-22 20:21 UTC (permalink / raw)
To: Ferruh Yigit; +Cc: Venkat Duvvuru, dpdk-dev, David Marchand, Aaron Conole
[-- Attachment #1: Type: text/plain, Size: 4922 bytes --]
On Wed, Sep 22, 2021 at 10:36 AM Ferruh Yigit <ferruh.yigit@intel.com> wrote:
>
> On 9/21/2021 5:50 AM, Ajit Khaparde wrote:
> > On Mon, Sep 20, 2021 at 12:42 AM Venkat Duvvuru
> > <venkatkumar.duvvuru@broadcom.com> wrote:
> >>
> >> This patch set adds support for new offload features/enhancments for
> >> Thor adapters like VF representor support, new flow matches/actions
> >> & dynamic SRAM manager support.
> >>
> >> Farah Smith (4):
> >> net/bnxt: updates to TF core index table
> >> net/bnxt: add SRAM manager model
> >> net/bnxt: change log level to debug
> >> net/bnxt: add SRAM manager shared session
> >>
> >> Jay Ding (1):
> >> net/bnxt: add flow meter drop counter support
> >>
> >> Kishore Padmanabha (6):
> >> net/bnxt: add flow template support for Thor
> >> net/bnxt: add support for tunnel offload API
> >> net/bnxt: add support for dynamic encap action
> >> net/bnxt: add wild card TCAM byte order for Thor
> >> net/bnxt: add flow templates for Thor
> >> net/bnxt: add enhancements to TF ULP
> >>
> >> Peter Spreadborough (1):
> >> net/bnxt: enable dpool allocator
> >>
> >> Randy Schacher (1):
> >> net/bnxt: dynamically allocate space for EM defrag function
> >
> > For the patchset,
> > Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
> >
> > Patchset applied to dpdk-next-net-brcm.
> > 1) Changed instance of TF to TRUFLOW during merge in patch 1/13 and 13/13.
> >
> > Please apply to dpdk-next-net. Thanks
> >
>
> Hi Ajit,
>
> The github actions fails on build for gcc, please check it on my personal github
> repo:
> https://github.com/ferruhy/dpdk/actions/runs/1262767538
>
> I don't have this error in my environment, this can be related to the slightly
> older compiler in the github (gcc 7.5)
Yes, even I did not see this. Looks genuine and likely because of some
different compiler.
I will try to submit a fix. Will you be able to squash it with the
relevant commit?
FAILED: drivers/a715181@@tmp_rte_net_bnxt@sta/net_bnxt_tf_core_tf_sram_mgr.c.o
ccache gcc -Idrivers/a715181@@tmp_rte_net_bnxt@sta -Idrivers
-I../drivers -Idrivers/net/bnxt -I../drivers/net/bnxt
-Idrivers/net/bnxt/tf_ulp -I../drivers/net/bnxt/tf_ulp
-Idrivers/net/bnxt/tf_ulp/generic_templates
-I../drivers/net/bnxt/tf_ulp/generic_templates
-Idrivers/net/bnxt/tf_core -I../drivers/net/bnxt/tf_core
-Idrivers/net/bnxt/hcapi/cfa -I../drivers/net/bnxt/hcapi/cfa
-Ilib/ethdev -I../lib/ethdev -I. -I../ -Iconfig -I../config
-Ilib/eal/include -I../lib/eal/include -Ilib/eal/linux/include
-I../lib/eal/linux/include -Ilib/eal/x86/include
-I../lib/eal/x86/include -Ilib/eal/common -I../lib/eal/common
-Ilib/eal -I../lib/eal -Ilib/kvargs -I../lib/kvargs
-Ilib/telemetry/../metrics -I../lib/telemetry/../metrics
-Ilib/telemetry -I../lib/telemetry -Ilib/net -I../lib/net -Ilib/mbuf
-I../lib/mbuf -Ilib/mempool -I../lib/mempool -Ilib/ring -I../lib/ring
-Ilib/meter -I../lib/meter -Idrivers/bus/pci -I../drivers/bus/pci
-I../drivers/bus/pci/linux -Ilib/pci -I../lib/pci -Idrivers/bus/vdev
-I../drivers/bus/vdev -fdiagnostics-color=always -pipe
-D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -Werror -O2 -g -include
rte_config.h -Wextra -Wcast-qual -Wdeprecated -Wformat
-Wformat-nonliteral -Wformat-security -Wmissing-declarations
-Wmissing-prototypes -Wnested-externs -Wold-style-definition
-Wpointer-arith -Wsign-compare -Wstrict-prototypes -Wundef
-Wwrite-strings -Wno-missing-field-initializers -D_GNU_SOURCE -fPIC
-march=corei7 -DALLOW_EXPERIMENTAL_API -DALLOW_INTERNAL_API
-Wno-format-truncation -DRTE_LIBRTE_BNXT_TF -DSUPPORT_CFA_HW_ALL=1
-DCC_AVX2_SUPPORT -DRTE_LOG_DEFAULT_LOGTYPE=pmd.net.bnxt -MD -MQ
'drivers/a715181@@tmp_rte_net_bnxt@sta/net_bnxt_tf_core_tf_sram_mgr.c.o'
-MF 'drivers/a715181@@tmp_rte_net_bnxt@sta/net_bnxt_tf_core_tf_sram_mgr.c.o.d'
-o 'drivers/a715181@@tmp_rte_net_bnxt@sta/net_bnxt_tf_core_tf_sram_mgr.c.o'
-c ../drivers/net/bnxt/tf_core/tf_sram_mgr.c
../drivers/net/bnxt/tf_core/tf_sram_mgr.c: In function ‘tf_sram_mgr_bind’:
../drivers/net/bnxt/tf_core/tf_sram_mgr.c:418:19: error: ‘slice_list’
may be used uninitialized in this function
[-Werror=maybe-uninitialized]
slice_list->tail = NULL;
^
../drivers/net/bnxt/tf_core/tf_sram_mgr.c:574:29: note: ‘slice_list’
was declared here
struct tf_sram_slice_list *slice_list;
^~~~~~~~~~
cc1: all warnings being treated as errors
>
> Can you please check the build error? I will keep the set in next-net for now,
> but won't mark it to pull to main until issue is resolved.
> If the fix is trivial, we can update it in the next-net (after issue recorded in
> mail list), if it is not trivial may require a new version of the set.
>
>
> btw, in git history 'TruFlow' is used, so I continue to use it, fyi.
No problem. Thanks
>
> Thanks,
> ferruh
>
^ permalink raw reply [flat|nested] 83+ messages in thread* Re: [dpdk-dev] [PATCH v4 00/13] enhancements to host based flow table management
2021-09-22 20:21 ` Ajit Khaparde
@ 2021-09-23 7:19 ` Ferruh Yigit
2021-09-25 14:24 ` [dpdk-dev] [PATCH] net/bnxt: remove code to initialize SRAM slice node Ajit Khaparde
0 siblings, 1 reply; 83+ messages in thread
From: Ferruh Yigit @ 2021-09-23 7:19 UTC (permalink / raw)
To: Ajit Khaparde; +Cc: Venkat Duvvuru, dpdk-dev, David Marchand, Aaron Conole
On 9/22/2021 9:21 PM, Ajit Khaparde wrote:
> On Wed, Sep 22, 2021 at 10:36 AM Ferruh Yigit <ferruh.yigit@intel.com> wrote:
>>
>> On 9/21/2021 5:50 AM, Ajit Khaparde wrote:
>>> On Mon, Sep 20, 2021 at 12:42 AM Venkat Duvvuru
>>> <venkatkumar.duvvuru@broadcom.com> wrote:
>>>>
>>>> This patch set adds support for new offload features/enhancments for
>>>> Thor adapters like VF representor support, new flow matches/actions
>>>> & dynamic SRAM manager support.
>>>>
>>>> Farah Smith (4):
>>>> net/bnxt: updates to TF core index table
>>>> net/bnxt: add SRAM manager model
>>>> net/bnxt: change log level to debug
>>>> net/bnxt: add SRAM manager shared session
>>>>
>>>> Jay Ding (1):
>>>> net/bnxt: add flow meter drop counter support
>>>>
>>>> Kishore Padmanabha (6):
>>>> net/bnxt: add flow template support for Thor
>>>> net/bnxt: add support for tunnel offload API
>>>> net/bnxt: add support for dynamic encap action
>>>> net/bnxt: add wild card TCAM byte order for Thor
>>>> net/bnxt: add flow templates for Thor
>>>> net/bnxt: add enhancements to TF ULP
>>>>
>>>> Peter Spreadborough (1):
>>>> net/bnxt: enable dpool allocator
>>>>
>>>> Randy Schacher (1):
>>>> net/bnxt: dynamically allocate space for EM defrag function
>>>
>>> For the patchset,
>>> Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
>>>
>>> Patchset applied to dpdk-next-net-brcm.
>>> 1) Changed instance of TF to TRUFLOW during merge in patch 1/13 and 13/13.
>>>
>>> Please apply to dpdk-next-net. Thanks
>>>
>>
>> Hi Ajit,
>>
>> The github actions fails on build for gcc, please check it on my personal github
>> repo:
>> https://github.com/ferruhy/dpdk/actions/runs/1262767538
>>
>> I don't have this error in my environment, this can be related to the slightly
>> older compiler in the github (gcc 7.5)
>
> Yes, even I did not see this. Looks genuine and likely because of some
> different compiler.
> I will try to submit a fix. Will you be able to squash it with the
> relevant commit?
>
If you can send the fix on top of latest next-net, I can squash it in next-net,
assuming the fix is simple.
>
>
> FAILED: drivers/a715181@@tmp_rte_net_bnxt@sta/net_bnxt_tf_core_tf_sram_mgr.c.o
> ccache gcc -Idrivers/a715181@@tmp_rte_net_bnxt@sta -Idrivers
> -I../drivers -Idrivers/net/bnxt -I../drivers/net/bnxt
> -Idrivers/net/bnxt/tf_ulp -I../drivers/net/bnxt/tf_ulp
> -Idrivers/net/bnxt/tf_ulp/generic_templates
> -I../drivers/net/bnxt/tf_ulp/generic_templates
> -Idrivers/net/bnxt/tf_core -I../drivers/net/bnxt/tf_core
> -Idrivers/net/bnxt/hcapi/cfa -I../drivers/net/bnxt/hcapi/cfa
> -Ilib/ethdev -I../lib/ethdev -I. -I../ -Iconfig -I../config
> -Ilib/eal/include -I../lib/eal/include -Ilib/eal/linux/include
> -I../lib/eal/linux/include -Ilib/eal/x86/include
> -I../lib/eal/x86/include -Ilib/eal/common -I../lib/eal/common
> -Ilib/eal -I../lib/eal -Ilib/kvargs -I../lib/kvargs
> -Ilib/telemetry/../metrics -I../lib/telemetry/../metrics
> -Ilib/telemetry -I../lib/telemetry -Ilib/net -I../lib/net -Ilib/mbuf
> -I../lib/mbuf -Ilib/mempool -I../lib/mempool -Ilib/ring -I../lib/ring
> -Ilib/meter -I../lib/meter -Idrivers/bus/pci -I../drivers/bus/pci
> -I../drivers/bus/pci/linux -Ilib/pci -I../lib/pci -Idrivers/bus/vdev
> -I../drivers/bus/vdev -fdiagnostics-color=always -pipe
> -D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -Werror -O2 -g -include
> rte_config.h -Wextra -Wcast-qual -Wdeprecated -Wformat
> -Wformat-nonliteral -Wformat-security -Wmissing-declarations
> -Wmissing-prototypes -Wnested-externs -Wold-style-definition
> -Wpointer-arith -Wsign-compare -Wstrict-prototypes -Wundef
> -Wwrite-strings -Wno-missing-field-initializers -D_GNU_SOURCE -fPIC
> -march=corei7 -DALLOW_EXPERIMENTAL_API -DALLOW_INTERNAL_API
> -Wno-format-truncation -DRTE_LIBRTE_BNXT_TF -DSUPPORT_CFA_HW_ALL=1
> -DCC_AVX2_SUPPORT -DRTE_LOG_DEFAULT_LOGTYPE=pmd.net.bnxt -MD -MQ
> 'drivers/a715181@@tmp_rte_net_bnxt@sta/net_bnxt_tf_core_tf_sram_mgr.c.o'
> -MF 'drivers/a715181@@tmp_rte_net_bnxt@sta/net_bnxt_tf_core_tf_sram_mgr.c.o.d'
> -o 'drivers/a715181@@tmp_rte_net_bnxt@sta/net_bnxt_tf_core_tf_sram_mgr.c.o'
> -c ../drivers/net/bnxt/tf_core/tf_sram_mgr.c
> ../drivers/net/bnxt/tf_core/tf_sram_mgr.c: In function ‘tf_sram_mgr_bind’:
> ../drivers/net/bnxt/tf_core/tf_sram_mgr.c:418:19: error: ‘slice_list’
> may be used uninitialized in this function
> [-Werror=maybe-uninitialized]
> slice_list->tail = NULL;
> ^
> ../drivers/net/bnxt/tf_core/tf_sram_mgr.c:574:29: note: ‘slice_list’
> was declared here
> struct tf_sram_slice_list *slice_list;
> ^~~~~~~~~~
> cc1: all warnings being treated as errors
>
>>
>> Can you please check the build error? I will keep the set in next-net for now,
>> but won't mark it to pull to main until issue is resolved.
>> If the fix is trivial, we can update it in the next-net (after issue recorded in
>> mail list), if it is not trivial may require a new version of the set.
>>
>>
>> btw, in git history 'TruFlow' is used, so I continue to use it, fyi.
> No problem. Thanks
>
>>
>> Thanks,
>> ferruh
>>
^ permalink raw reply [flat|nested] 83+ messages in thread
* [dpdk-dev] [PATCH] net/bnxt: remove code to initialize SRAM slice node
2021-09-23 7:19 ` Ferruh Yigit
@ 2021-09-25 14:24 ` Ajit Khaparde
2021-09-27 10:25 ` Ferruh Yigit
0 siblings, 1 reply; 83+ messages in thread
From: Ajit Khaparde @ 2021-09-25 14:24 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit, venkatkumar.duvvuru, Kishore Padmanabha, Farah Smith
[-- Attachment #1: Type: text/plain, Size: 2405 bytes --]
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Remove the code to initialize SRAM slice mode explicitly. The
code is redundanat as the memory allocated is initialized to
zero by the rte_zmalloc. This fixes the compilation issue for
uninitialized pointer when debug optimized configuration is used.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/tf_core/tf_sram_mgr.c | 47 --------------------------
1 file changed, 47 deletions(-)
diff --git a/drivers/net/bnxt/tf_core/tf_sram_mgr.c b/drivers/net/bnxt/tf_core/tf_sram_mgr.c
index f633a78b25..a248ef2ce8 100644
--- a/drivers/net/bnxt/tf_core/tf_sram_mgr.c
+++ b/drivers/net/bnxt/tf_core/tf_sram_mgr.c
@@ -407,19 +407,6 @@ tf_sram_is_slice_allocated_in_block(struct tf_sram_block *block,
return rc;
}
-/**
- * Initialize slice list
- */
-static void
-tf_sram_init_slice_list(struct tf_sram_slice_list *slice_list,
- enum tf_sram_slice_size slice_size)
-{
- slice_list->head = NULL;
- slice_list->tail = NULL;
- slice_list->cnt = 0;
- slice_list->size = slice_size;
-}
-
/**
* Get the block count
*/
@@ -568,11 +555,7 @@ int
tf_sram_mgr_bind(void **sram_handle)
{
int rc = 0;
- enum tf_sram_bank_id bank_id;
- enum tf_sram_slice_size slice_size;
struct tf_sram *sram;
- struct tf_sram_slice_list *slice_list;
- enum tf_dir dir;
struct tfp_calloc_parms cparms;
TF_CHECK_PARMS1(sram_handle);
@@ -589,37 +572,7 @@ tf_sram_mgr_bind(void **sram_handle)
return rc;
}
sram = (struct tf_sram *)cparms.mem_va;
-
- /* For each direction
- */
- for (dir = 0; dir < TF_DIR_MAX; dir++) {
- /* For each bank
- */
- for (bank_id = TF_SRAM_BANK_ID_0;
- bank_id < TF_SRAM_BANK_ID_MAX;
- bank_id++) {
- /* Create each sized slice empty list
- */
- for (slice_size = TF_SRAM_SLICE_SIZE_8B;
- slice_size < TF_SRAM_SLICE_SIZE_MAX;
- slice_size++) {
- rc = tf_sram_get_slice_list(sram, &slice_list,
- slice_size, dir,
- bank_id);
- if (rc) {
- /* Log error */
- TFP_DRV_LOG(ERR,
- "No SRAM slice list, rc:%s\n",
- strerror(-rc));
- return rc;
- }
- tf_sram_init_slice_list(slice_list, slice_size);
- }
- }
- }
-
*sram_handle = sram;
-
return rc;
}
--
2.30.1 (Apple Git-130)
^ permalink raw reply [flat|nested] 83+ messages in thread* Re: [dpdk-dev] [PATCH] net/bnxt: remove code to initialize SRAM slice node
2021-09-25 14:24 ` [dpdk-dev] [PATCH] net/bnxt: remove code to initialize SRAM slice node Ajit Khaparde
@ 2021-09-27 10:25 ` Ferruh Yigit
0 siblings, 0 replies; 83+ messages in thread
From: Ferruh Yigit @ 2021-09-27 10:25 UTC (permalink / raw)
To: Ajit Khaparde, dev; +Cc: venkatkumar.duvvuru, Kishore Padmanabha, Farah Smith
On 9/25/2021 3:24 PM, Ajit Khaparde wrote:
> From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
>
> Remove the code to initialize SRAM slice mode explicitly. The
> code is redundanat as the memory allocated is initialized to
> zero by the rte_zmalloc. This fixes the compilation issue for
> uninitialized pointer when debug optimized configuration is used.
>
> Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
> Reviewed-by: Farah Smith <farah.smith@broadcom.com>
> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Squashed into relevant commit [1] in next-net, thanks.
[1]
net/bnxt: add SRAM manager model
^ permalink raw reply [flat|nested] 83+ messages in thread